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x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/ 0000775 0000000 0000000 00000000000 12327752717 0020333 5 ustar 00root root 0000000 0000000 x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/byte_lane.v 0000664 0000000 0000000 00000020467 12327752717 0022475 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: byte_lane
* Date:2014-04-26
* Author: Andrey Filippov
* Description: DDR3 byte lane, ingluding DQS I/O, 8xDQ I/O and DM output
*
* Copyright (c) 2014 Elphel, Inc.
* byte_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* byte_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module byte_lane #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD_DQ = "SSTL15_T_DCI",
parameter IOSTANDARD_DQS = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout [7:0] dq, // DQ I/O pads
inout dm, // DM I/O pad (actually only output)
inout dqs, // DQS I/O pad
inout ndqs, // ~DQS I/O pad
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channels (clk_div is shared between R and W)
input rst,
input dci_disable_dqs, // disable DCI termination during writes and idle for dqs
input dci_disable_dq, // disable DCI termination during writes and idle for dq and dm signals
input [31:0] din, // parallel data to be sent out (4 bits per DG I/))
input [3:0] din_dm, // parallel data to be sent out over DM
input [3:0] tin_dq, // tristate for data out (sent out earlier than data!) and dm
input [3:0] din_dqs, // parallel data to be sent out over DQS
input [3:0] tin_dqs, // tristate for DQS out (sent out earlier than data!)
output [31:0] dout, // parallel data received from DDR3 memory, 4 bits per DG I/O
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [4:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_iv synchronous)
input set // clk_div synchronous set all delays from previously loaded values
);
//(* CLOCK_DEDICATED_ROUTE = "FALSE" *) // does not seem to work
wire dqs_read;
wire iclk; // source-synchronous clock (BUFR from DQS)
reg [31:0] din_r=0;
reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
reg [7:0] dly_data_r=0;
reg set_r=0;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
reg dci_disable_dqs_r, dci_disable_dq_r;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
wire [9:0] decode_sel={
(dly_addr[3:0]==9)?1'b1:1'b0,
(dly_addr[3:0]==8)?1'b1:1'b0,
(dly_addr[3:0]==7)?1'b1:1'b0,
(dly_addr[3:0]==6)?1'b1:1'b0,
(dly_addr[3:0]==5)?1'b1:1'b0,
(dly_addr[3:0]==4)?1'b1:1'b0,
(dly_addr[3:0]==3)?1'b1:1'b0,
(dly_addr[3:0]==2)?1'b1:1'b0,
(dly_addr[3:0]==1)?1'b1:1'b0,
(dly_addr[3:0]==0)?1'b1:1'b0};
always @ (posedge clk_div or posedge rst) begin
if (rst) begin
din_r <= 32'b0; din_dm_r<=0; din_dqs_r<=0; tin_dq_r<=4'hf; tin_dqs_r<=4'hf;
dly_data_r<=8'b0;set_r<=1'b0;
dci_disable_dqs_r <= 1'b1; dci_disable_dq_r <=1'b1;
ld_odly<=8'b0; ld_idly<=8'b0; ld_odly_dqs<=1'b0; ld_idly_dqs<=1'b0; ld_odly_dm<=1'b0;
end else begin
din_r<=din[31:0]; din_dm_r<=din_dm; din_dqs_r<=din_dqs; tin_dq_r<=tin_dq; tin_dqs_r<=tin_dqs;
dly_data_r<=dly_data; set_r<=set;
dci_disable_dqs_r <= dci_disable_dqs; dci_disable_dq_r <= dci_disable_dq;
{ld_odly_dm,ld_odly_dqs,ld_odly[7:0]} <= {10{(~dly_addr[4]) & ld_delay}} & decode_sel;
{ ld_idly_dqs,ld_idly[7:0]} <= {9 {( dly_addr[4]) & ld_delay}} & decode_sel[8:0];
end
end
generate
genvar i;
for (i=0; i<7; i=i+1) begin: dq_block
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dq_i(
.dq(dq[i]), // I/O pad
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_r[4*i+3:4*i]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout(dout[4*i+3:4*i]), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly[i]), // clk_div synchronous set odealy value from loaded
.set_idelay(set_r), // clk_div synchronous load idelay value from dly_data
.ld_idelay(ld_idly[i]) // clk_div synchronous set idealy value from loaded
);
end
endgenerate
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_i(
.dq(dm), // DM output pad
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
.dout(), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm), // clk_div synchronous set odealy value from loaded
.set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
.ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
dqs_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQS),
.SLEW(SLEW),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_i (
.dqs(dqs),
.ndqs(ndqs),
.clk(clk),
.clk_div(clk_div),
.rst(rst),
.dqs_received_dly(dqs_read),
.dci_disable(dci_disable_dqs_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r[7:0]),
.din(din_dqs_r[3:0]),
.tin(tin_dqs_r[3:0]),
.set_odelay(set_r),
.ld_odelay(ld_odly_dqs),
.set_idelay(set_r),
.ld_idelay(ld_idly_dqs)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/cmda_single.v 0000664 0000000 0000000 00000011506 12327752717 0022772 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: cmda_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit CMD/address output
*
* Copyright (c) 2014 Elphel, Inc.
* cmda_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmda_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module cmda_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dq, // I/O pad
input iclk, // source-synchronous clock (BUFR from DQS)
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channel (clk_div is shared between R and W)
input rst,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [3:0] din, // parallel data to be sent out
input [3:0] tin, // tristate for data out (sent out earlier than data!)
output [3:0] dout, // parallel data received from DDR3 memory
input set_odelay, // clk_div synchronous load odelay value from dly_data
input ld_odelay, // clk_div synchronous set odealy value from loaded
input set_idelay, // clk_div synchronous load idelay value from dly_data
input ld_idelay // clk_div synchronous set idealy value from loaded
);
wire d_ser;
wire dq_tri;
wire dq_data_dly;
wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
(* keep = "true" *)
wire dq_di;
oserdes_mem#(
.MODE_DDR("FALSE")
) oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dq_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dq_data_dly)
);
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dq_di),
.IO(dq),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dq_di),
.data_out(dq_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
) iserdes_mem_i (
.iclk(iclk), // source-synchronous clock
.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(clk_div), // oclk divided by 2, front aligned
.inv_clk_div(inv_clk_div), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(rst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(dq_dly), // serial input from idelay
.dout(dout[3:0]) // parallel data out
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/dq_single.v 0000664 0000000 0000000 00000011516 12327752717 0022473 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: dq_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQ I/O, same used for DM
*
* Copyright (c) 2014 Elphel, Inc.
* dq_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dq_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module dq_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dq, // I/O pad
input iclk, // source-synchronous clock (BUFR from DQS)
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input inv_clk_div, // invert clk_div for R channel (clk_div is shared between R and W)
input rst,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [3:0] din, // parallel data to be sent out
input [3:0] tin, // tristate for data out (sent out earlier than data!)
output [3:0] dout, // parallel data received from DDR3 memory
input set_odelay, // clk_div synchronous load odelay value from dly_data
input ld_odelay, // clk_div synchronous set odealy value from loaded
input set_idelay, // clk_div synchronous load idelay value from dly_data
input ld_idelay // clk_div synchronous set idealy value from loaded
);
wire d_ser;
wire dq_tri;
wire dq_data_dly;
wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
(* keep = "true" *)
wire dq_di;
oserdes_mem#(
.MODE_DDR("TRUE")
) oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dq_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dq_data_dly)
);
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dq_di),
.IO(dq),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dq_di),
.data_out(dq_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
) iserdes_mem_i (
.iclk(iclk), // source-synchronous clock
.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div(clk_div), // oclk divided by 2, front aligned
.inv_clk_div(inv_clk_div), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst(rst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(dq_dly), // serial input from idelay
.dout(dout[3:0]) // parallel data out
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/dqs_single.v 0000664 0000000 0000000 00000006503 12327752717 0022656 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: dqs_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQS I/O
*
* Copyright (c) 2014 Elphel, Inc.
* dqs_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dqs_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module dqs_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "DIFF_SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout dqs,
inout ndqs,
input clk,
input clk_div,
input rst,
output dqs_received_dly,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data,
input [3:0] din,
input [3:0] tin,
input set_odelay,
input ld_odelay,
input set_idelay,
input ld_idelay
);
wire d_ser;
wire dqs_tri;
wire dqs_data_dly;
wire dqs_di;
oserdes_mem oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dqs_data_dly)
);
IOBUFDS_DCIEN #(
.DIFF_TERM("FALSE"),
.DQS_BIAS("TRUE"), // outputs 1'b0 when IOB is floating
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
.O(dqs_di),
.IO(dqs),
.IOB(ndqs),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
.ld(ld_idelay),
.delay(dly_data[7:0]),
.data_in(dqs_di),
.data_out(dqs_received_dly)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs.v 0000664 0000000 0000000 00000006502 12327752717 0022353 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs(
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
input set,
input ld_dly_data,
input ld_dly_tri,
input [7:0] dly_data,
input [3:0] data_in,
input [3:0] tri_in,
inout dqs,
inout ndqs,
output dqs_received,
output dly_ready,
input dqs_tri_a,
output dqs_tri
);
wire refclk_b=refclk; // use buffer
wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay
wire dqs_data; // after odelay
wire pre_dqs_data,pre_dqs_tri; // before odelay
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
oserdes_mem oserdes_dqs_i(
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(data_in), // parallel data in
.tin(tri_in), // parallel tri-state in
.dout_dly(), // data out to be connected to odelay input
.dout_iob(pre_dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(refclk_b),
.rst(rst),
.rdy(dly_ready)
);
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
// .T(dqs_tri_a));
.T(1'b0));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs01.v 0000664 0000000 0000000 00000002521 12327752717 0022511 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs01
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs01(
input dqs_data,
inout dqs,
inout ndqs,
output dqs_received,
input dqs_tri
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
.T(dqs_tri));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs01_placement.xdc 0000664 0000000 0000000 00000007161 12327752717 0025057 0 ustar 00root root 0000000 0000000 set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design] x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs02.v 0000664 0000000 0000000 00000007722 12327752717 0022522 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs02
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs02.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs02.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs02(
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
input set,
input ld_dly_data,
input ld_dly_tri,
input [7:0] dly_data,
input [3:0] data_in,
input [3:0] tri_in,
inout dqs,
inout ndqs,
output dqs_received,
output dly_ready,
input dqs_tri_a,
output dqs_tri
// output dqs_data
);
wire refclk_b=refclk; // use buffer
wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay
//wire dqs_data; // after odelay
wire pre_dqs_data,pre_dqs_tri; // before odelay
wire dqs_data;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
oserdes_mem oserdes_dqs_i(
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(data_in), // parallel data in
// .tin(tri_in), // parallel tri-state in
.tin(), // parallel tri-state in
.dout_dly(), //pre_dqs_data), // data out to be connected to odelay input
.dout_iob(dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(refclk_b),
.rst(rst),
.rdy(dly_ready)
);
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data[7:3]),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
*/
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
/*
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
// .T(dqs_tri));
.T());
*/
IOBUF #(
// .DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.I(dqs_data),
// .T(dqs_tri));
.T(dqs_data));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs02_placement.xdc 0000664 0000000 0000000 00000006256 12327752717 0025064 0 ustar 00root root 0000000 0000000 set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
#set_property PACKAGE_PIN N6 [get_ports {ndqs}]
#set_property SLEW FAST [get_ports {ndqs}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri_a}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs03.v 0000664 0000000 0000000 00000004327 12327752717 0022521 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs03
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs03.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs03.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs03(
input dqs_data,
inout dqs,
inout ndqs,
input clk_in,
input clk_ref_in,
input rst,
output dqs_received,
input dqs_tri,
output dly_ready,
input [4:0] dly_data,
input set,
input ld
);
wire clk,clk_div,clk_ref;
wire dqs_data_dly;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.rst(rst),
.rdy(dly_ready)
);
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld),
.delay(dly_data),
.data_in(dqs_data),
.data_out(dqs_data_dly)
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs03_placement.xdc 0000664 0000000 0000000 00000014311 12327752717 0025054 0 ustar 00root root 0000000 0000000 set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
# input clk_in,
# input clk_ref_in,
# input rst,
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs04.v 0000664 0000000 0000000 00000010120 12327752717 0022506 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs04
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs04.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs04.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs04(
input dqs_data,
inout dqs,
inout ndqs,
input clk_in,
input clk_ref_in,
input rst,
output dqs_received,
input dqs_tri,
output dly_ready,
input [4:0] dly_data,
input set,
input ld
);
wire clk,clk_div,clk_ref;
wire dqs_data_dly;
wire dly_ready_0;
assign dly_ready= dly_ready_0 && dqs_data;
wire d_ser;
wire dqs_tri1;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
.OFB (d_ser),
.OQ (), // dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (),
.TQ (dqs_tri1),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (dly_data[0]),
.D2 (dly_data[1]),
.D3 (dly_data[2]),
.D4 (dly_data[3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (dly_data[4]),
.T2 (dly_data[4]),
.T3 (dly_data[4]),
.T4 (dly_data[4]),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN ()
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.rst(rst),
.rdy(dly_ready_0)
);
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld),
.delay(dly_data),
.data_in(d_ser), //dqs_data),
.data_out(dqs_data_dly)
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri1));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs04_placement.xdc 0000664 0000000 0000000 00000014311 12327752717 0025055 0 ustar 00root root 0000000 0000000 set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
# input clk_in,
# input clk_ref_in,
# input rst,
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs05.v 0000664 0000000 0000000 00000013557 12327752717 0022530 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs05
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs05.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs05.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs05(
input dqs_data,
inout dqs,
inout ndqs,
input clk_in,
input clk_ref_in,
input rst,
output dqs_received,
input dqs_tri,
output dly_ready,
input [4:0] dly_data,
input set,
input ld,
input ldt
);
wire clk,clk_div,clk_ref;
wire dqs_data_dly;
wire dly_ready_0;
assign dly_ready= dly_ready_0 && dqs_data;
wire d_ser;
wire dqs_tri1;
wire d_tri;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
// .DATA_RATE_TQ ("DDR"),
.DATA_RATE_TQ ("BUF"),
.DATA_WIDTH (4),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (1),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
.OFB (d_ser),
.OQ (), // dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
// .TFB (d_tri),
// .TQ (dqs_tri1),
.TQ (),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (dly_data[0]),
.D2 (dly_data[1]),
.D3 (dly_data[2]),
.D4 (dly_data[3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
// .T1 (dly_data[4]),
// .T2 (dly_data[4]),
// .T3 (dly_data[4]),
// .T4 (dly_data[4]),
.T1 (),
.T2 (),
.T3 (),
.T4 (),
// .TCE (1'b1),
.TCE (),
.TBYTEOUT (),
.TBYTEIN ()
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.rst(rst),
.rdy(dly_ready_0)
);
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld),
.delay(dly_data),
.data_in(d_ser), //dqs_data),
.data_out(dqs_data_dly)
);
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ldt),
.delay(dly_data),
.data_in(dqs_tri), //d_tri), //dqs_data),
.data_out(dqs_tri1)
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri1));
endmodule
/*
Does not work.
http://forums.xilinx.com/t5/7-Series-FPGAs/How-to-use-2-odelya-on-one-IOB-on-V7/m-p/361317#M2312
There is only one ODELAY per IOI/IOB, therefore to use a second ODELAY you would require the use of a second IOI/IOB.
Secondly the DATAOUT of an ODELAY can ONLY be connected to OBUF (or IOBUF), it will not route to a T port of an IOBUF.
Thirdly when you are using an OSERDES followed by an IOBUFT the T port needs to be driven from the TQ of the OSERDES.
What you can do is take the DATAOUT of the Tristate ODELAY and drive an IOBUFT and then use the input side of the buffer
drive the T1 port of the OSERDES and connect the TQ port of the data IOBUFT. The obvious down side to this is the use of
the second IOB/IOI and the routing delay from IOB to the T1 port of the OSERDES.
Another option would be to use the IDELAY in the data IOB/IOI using the DATAIN port and the DELAY_src=> "DATAIN", you can
LOC the IDELAY to the same site (tools won’t automatically choose this location). You will still have the routing delays
as the output of the IDELAY goes into Fabric to get back to the OSERDES T1 port but it only uses data IOB/IOI.
*/
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs05_placement.xdc 0000664 0000000 0000000 00000014452 12327752717 0025064 0 ustar 00root root 0000000 0000000 set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs}]
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri
#set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
#set_property IOSTANDARD LVCMOS15 [get_ports {refclk}]
#set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
#set_property IOSTANDARD LVCMOS15 [get_ports {set}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {ld_dly_tri}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {data_in[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {tri_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_data}]
set_property PACKAGE_PIN K6 [get_ports {dqs_data}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_date}]
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
# input dqs_data,
# inout dqs,
# inout ndqs,
# output dqs_received,
# input dqs_tri,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
# input clk_in,
# input clk_ref_in,
# input rst,
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
set_property IOSTANDARD LVCMOS15 [get_ports {ldt}]
set_property PACKAGE_PIN M3 [get_ports {ldt}]
# input rst, // reset
# input refclk, // 200MHz/300MHz for delay calibration
# input clk_in,
# input set,
# input ld_dly_data,
# input ld_dly_tri,
# input [7:0] dly_data,
# input [3:0] data_in,
# input [3:0] tri_in,
# inout dqs,
# inout ndqs,
# output dqs_received,
# output dly_ready,
# input dqs_tri_a,
# output dqs_tri
#set_property PACKAGE_PIN A1 [get_ports {COUNT[2]}]
#set_property PACKAGE_PIN B2 [get_ports {COUNT[1]}]
#set_property PACKAGE_PIN C2 [get_ports {COUNT[0]}]
#set_property PULLUP true [get_ports {COUNT[3]}]
#set_property PULLUP true [get_ports {COUNT[2]}]
#set_property PULLUP true [get_ports {COUNT[1]}]
#set_property PULLUP true [get_ports {COUNT[0]}]
#set_property PACKAGE_PIN A4 [get_ports ENABLE]
#set_property PACKAGE_PIN B4 [get_ports RESET]
#set_property PACKAGE_PIN C1 [get_ports CLK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {COUNT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports ENABLE]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports CLK]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs06.v 0000664 0000000 0000000 00000004233 12327752717 0022520 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs06
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs06.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs06.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs06(
inout dqs,
inout ndqs,
output dqs_received,
input clk_in,
input clk_ref_in,
input rst,
input dci_disable,
input [7:0] dly_data,
input set,
input ld,
output dly_ready
);
wire clk,clk_div,clk_ref;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.rst(rst),
.rdy(dly_ready)
);
dqs_single #(
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DIFF_SSTL15_T_DCI"),
.SLEW("FAST"),
.REFCLK_FREQUENCY(300.0)
)dqs_single_i(
.dqs(dqs),
.ndqs(ndqs),
.clk(clk),
.clk_div(clk_div),
.rst(rst),
.dqs_received_dly(dqs_received),
.dci_disable(dci_disable), // disable DCI termination during writes and idle
.dly_data(dly_data[7:0]),
.din(dly_data[3:0]),
.tin({4{dly_data[4]}}),
.set_odelay(set),
.ld_odelay(ld),
.set_idelay(set),
.ld_idelay(ld)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs06_placement.xdc 0000664 0000000 0000000 00000007364 12327752717 0025071 0 ustar 00root root 0000000 0000000
# inout dqs,
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
# inout ndqs,
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# output dqs_received,
set_property IOSTANDARD LVCMOS15 [get_ports {dqs_received}]
set_property PACKAGE_PIN K4 [get_ports {dqs_received}]
# input clk_in,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
# input clk_ref_in,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
# input rst,
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
# input dci_disable,
set_property IOSTANDARD LVCMOS15 [get_ports {dci_disable}]
set_property PACKAGE_PIN K6 [get_ports {dci_disable}]
# input [7:0] dly_data,
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
set_property PACKAGE_PIN H1 [get_ports {dly_data[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
set_property PACKAGE_PIN H2 [get_ports {dly_data[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
set_property PACKAGE_PIN H3 [get_ports {dly_data[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
# input set,
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
# input ld,
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
#set_property IOSTANDARD LVCMOS15 [get_ports {dqs_tri}]
#set_property PACKAGE_PIN K7 [get_ports {dqs_tri}]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs07.v 0000664 0000000 0000000 00000007746 12327752717 0022535 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: test_dqs07
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Testing DQS implementation
*
* Copyright (c) 2014 Elphel, Inc.
* test_dqs07.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_dqs07.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module test_dqs07(
inout dqs,
inout ndqs,
// output dqs_received,
input clk_in,
input clk_ref_in,
input rst,
input dci_disable_dqs,
input [7:0] dly_data,
input set,
input ld,
output dly_ready,
inout dq,
output [3:0] dout,
input dci_disable_dq
);
wire clk,clk_div,clk_ref;
(* CLOCK_DEDICATED_ROUTE = "FALSE" *) wire dqs_read; // does not seem to work
wire iclk;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
//set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dqs_single_i/dqs_in_dly_i/dqs_read]
//BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint above
BUFIO iclk_i (.O(iclk),.I(dqs_read)); // Fails even with the constraint
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.rst(rst),
.rdy(dly_ready)
);
dqs_single #(
.IODELAY_GRP("IODELAY_MEMORY"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DIFF_SSTL15_T_DCI"),
.SLEW("FAST"),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_single_i (
.dqs(dqs),
.ndqs(ndqs),
.clk(clk),
.clk_div(clk_div),
.rst(rst),
.dqs_received_dly(dqs_read),
.dci_disable(dci_disable_dqs), // disable DCI termination during writes and idle
.dly_data(dly_data[7:0]),
.din(dly_data[3:0]),
.tin({4{dly_data[4]}}),
.set_odelay(set),
.ld_odelay(ld),
.set_idelay(set),
.ld_idelay(ld)
);
dq_single #(
.IODELAY_GRP("IODELAY_MEMORY"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("SSTL15_T_DCI"),
.SLEW("FAST"),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dq_single_i (
.dq(dq),
.iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
.inv_clk_div(1'b0), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq), // disable DCI termination during writes and idle
.dly_data(dly_data[7:0]), // delay value (3 LSB - fine delay)
.din(dly_data[3:0]), // parallel data to be sent out
.tin({4{dly_data[4]}}), // tristate for data out (sent out earlier than data!)
.dout(dout[3:0]), // parallel data received from DDR3 memory
.set_odelay(set), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld), // clk_div synchronous set odealy value from loaded
.set_idelay(set), // clk_div synchronous load idelay value from dly_data
.ld_idelay(ld) // clk_div synchronous set idealy value from loaded
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/test_dqs07_placement.xdc 0000664 0000000 0000000 00000010646 12327752717 0025067 0 ustar 00root root 0000000 0000000 # inout dqs,
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]
# inout ndqs,
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]
# input clk_in,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
# input clk_ref_in,
set_property IOSTANDARD LVCMOS15 [get_ports {clk_ref_in}]
set_property PACKAGE_PIN L4 [get_ports {clk_ref_in}]
# input rst,
set_property IOSTANDARD LVCMOS15 [get_ports {rst}]
set_property PACKAGE_PIN L5 [get_ports {rst}]
# input dci_disable,
set_property IOSTANDARD LVCMOS15 [get_ports {dci_disable_dqs}]
set_property PACKAGE_PIN K6 [get_ports {dci_disable_dqs}]
# input [7:0] dly_data,
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[7]}]
set_property PACKAGE_PIN H1 [get_ports {dly_data[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[6]}]
set_property PACKAGE_PIN H2 [get_ports {dly_data[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[5]}]
set_property PACKAGE_PIN H3 [get_ports {dly_data[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[4]}]
set_property PACKAGE_PIN J1 [get_ports {dly_data[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[3]}]
set_property PACKAGE_PIN J3 [get_ports {dly_data[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[2]}]
set_property PACKAGE_PIN J4 [get_ports {dly_data[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[1]}]
set_property PACKAGE_PIN J5 [get_ports {dly_data[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dly_data[0]}]
set_property PACKAGE_PIN J6 [get_ports {dly_data[0]}]
# input set,
set_property IOSTANDARD LVCMOS15 [get_ports {set}]
set_property PACKAGE_PIN L6 [get_ports {set}]
# input ld,
set_property IOSTANDARD LVCMOS15 [get_ports {ld}]
set_property PACKAGE_PIN L7 [get_ports {ld}]
# output dly_ready
set_property IOSTANDARD LVCMOS15 [get_ports {dly_ready}]
set_property PACKAGE_PIN M2 [get_ports {dly_ready}]
# inout dq,
set_property IOSTANDARD SSTL15_T_DCI [get_ports {dq}]
set_property PACKAGE_PIN F6 [get_ports {dq}]
# output [3:0] dout,
set_property IOSTANDARD LVCMOS15 [get_ports {dout[3]}]
set_property PACKAGE_PIN K1 [get_ports {dout[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dout[2]}]
set_property PACKAGE_PIN K2 [get_ports {dout[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dout[1]}]
set_property PACKAGE_PIN K3 [get_ports {dout[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {dout[0]}]
set_property PACKAGE_PIN K4 [get_ports {dout[0]}]
# input dci_disable_dq
set_property IOSTANDARD LVCMOS15 [get_ports {dci_disable_dq}]
set_property PACKAGE_PIN K7 [get_ports {dci_disable_dq}]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
#trying to force BUFR to use fabric input
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dqs_single_i/dqs_in_dly_i/dqs_received]
#puts [get_property CLOCK_DEDICATED_ROUTE [get_nets dqs_single_i/dqs_in_dly_i/dqs_received]] x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/ 0000775 0000000 0000000 00000000000 12327752717 0021304 5 ustar 00root root 0000000 0000000 x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/idelay_ctrl.v 0000664 0000000 0000000 00000002410 12327752717 0023763 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_ctrl
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYCTRL wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_ctrl.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_ctrl
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY"
) (
input refclk,
input rst,
output rdy
);
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYCTRL idelay_ctrl_i(
.RDY(rdy),
.REFCLK(refclk),
.RST(rst));
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/idelay_fine_pipe.v 0000664 0000000 0000000 00000005025 12327752717 0024762 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_DATAIN_INVERTED(1'b0),
.IS_IDATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
idelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.DATAIN(1'b0),
.IDATAIN(data_in),
.IFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/iserdes_mem.v 0000664 0000000 0000000 00000014135 12327752717 0023773 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: iserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: ISERDESE2/ISERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* iserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* iserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module iserdes_mem #
(
parameter DYN_CLKDIV_INV_EN="FALSE"
) (
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
input oclk_div, // oclk divided by 2, front aligned
input inv_clk_div, // invert oclk_div (this clock is shared between iserdes and oserdes
input rst, // reset
input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
input ddly, // serial input from idelay
output [3:0] dout
);
parameter IOBDELAY = "IFD"; // "NONE", "IBUF", "IFD", "BOTH"
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIVP (), // used with phasers, source-sync
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (inv_clk_div),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OCLKB (!oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
ISERDESE1 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (inv_clk_div),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`endif
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/odelay_fine_pipe.v 0000664 0000000 0000000 00000004763 12327752717 0025000 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: odelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: ODELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* odelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module odelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.ODELAY_TYPE("VAR_LOAD_PIPE"),
.ODELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_ODATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
odelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.CLKIN(1'b0),
.ODATAIN(data_in),
.OFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/odelay_pipe.v 0000664 0000000 0000000 00000004165 12327752717 0023773 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: odelay_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: ODELAYE2 wrapper pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* odelay_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module odelay_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [4:0] delay,
input data_in,
output data_out
);
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
// .FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.ODELAY_TYPE("VAR_LOAD_PIPE"),
.ODELAY_VALUE(DELAY_VALUE),
.IS_C_INVERTED(1'b0),
.IS_ODATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
odelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[4:0]),
.CLKIN(1'b0),
.ODATAIN(data_in),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-ea560b4abed74b3ebce75289d4a8d3041d6c8f3a/phy/wrap/oserdes_mem.v 0000664 0000000 0000000 00000014747 12327752717 0024012 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: oserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: OSERDESE2/OSERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* oserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module oserdes_mem #(
parameter MODE_DDR="TRUE"
) (
input clk, // serial output clock
input clk_div, // oclk divided by 2, front aligned
input rst, // reset
input [((MODE_DDR=="TRUE")?3:1):0] din, // parallel data in
input [((MODE_DDR=="TRUE")?3:1):0] tin, // parallel tri-state in
output dout_dly, // data out to be connected to odelay input
output dout_iob, // data out to be connected directly to the output buffer
output tout_dly, // tristate out to be connected to odelay input
output tout_iob // tristate out to be connected directly to the tristate control of the output buffer
);
localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
localparam DATA_RATE= (MODE_DDR=="TRUE")?"DDR":"SDR";
localparam integer DATA_WIDTH= (MODE_DDR=="TRUE")?4:2;
localparam integer DDR3_DATA= (MODE_DDR=="TRUE")?1:0;
/*
Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
go directly. Luckily the active time for DQ/DQS may be extended (there is at least 1 full clock period
between READ and WRITE DQS active (more for DQ), so extending write preamble and postabmble by 1/2 period
seems to be OK.
*/
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
OSERDESE2 #(
.DATA_RATE_OQ (DATA_RATE),
.DATA_RATE_TQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (DATA_WIDTH),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 ((MODE_DDR=="TRUE")?din[2]:1'b0),
.D4 ((MODE_DDR=="TRUE")?din[3]:1'b0),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 ((MODE_DDR=="TRUE")?tin[2]:1'b0),
.T4 ((MODE_DDR=="TRUE")?tin[3]:1'b0),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN ()
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
OSERDESE1 #(
.DATA_RATE_OQ (DATA_RATE),
.DATA_RATE_TQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.DDR3_DATA (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3"
.ODELAY_USED (0), // 1 available only for MEMORY_DDR3
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (DATA_WIDTH)
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 ((MODE_DDR=="TRUE")?din[2]:1'b0),
.D4 ((MODE_DDR=="TRUE")?din[3]:1'b0),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 ((MODE_DDR=="TRUE")?tin[2]:1'b0),
.T4 ((MODE_DDR=="TRUE")?tin[3]:1'b0),
.TCE (1'b1),
// not in OSERDES2E:
.WC (1'b0),
.OCBEXTEND (),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.ODV (1'b0)
);
`endif
endmodule