/*******************************************************************************
 * File: x393_map.h
 * Date: 2016-03-29  
 * Author: auto-generated file, see x393_export_c.py
 * Description: Sorted hardware addresses map
 *******************************************************************************/
#define X393_MCNTRL_DLY_SET                              0x40000080 // Set all pre-programmed delays
// RESERVED: 0x3 DWORDs
#define X393_MCNTRL_CMDA_DIS                             0x40000090 // Disable DDR3 memory command/address lines
#define X393_MCNTRL_CMDA_EN                              0x40000094 // Enable DDR3 memory command/address lines
#define X393_MCNTRL_SDRST_DIS                            0x40000098 // Disable DDR3 memory reset
#define X393_MCNTRL_SDRST_EN                             0x4000009c // Enable DDR3 memory reset
#define X393_MCNTRL_CKE_DIS                              0x400000a0 // Disable DDR3 memory CKE
#define X393_MCNTRL_CKE_EN                               0x400000a4 // Enable DDR3 memory CKE
// RESERVED: 0x6 DWORDs
#define X393_MCNTRL_DIS                                  0x400000c0 // Disable DDR3 memory controller
#define X393_MCNTRL_EN                                   0x400000c4 // Enable DDR3 memory controller
#define X393_MCNTRL_REFRESH_DIS                          0x400000c8 // Disable DDR3 memory refresh
#define X393_MCNTRL_REFRESH_EN                           0x400000cc // Enable DDR3 memory refresh
// RESERVED: 0x1c DWORDs
#define X393_MCNTRL_DQS_DQM_PATT                         0x40000140 // Setup DQS and DQM patterns, data type: x393_mcntr_dqs_dqm_patt_t (rw)
#define X393_MCNTRL_DQ_DQS_TRI                           0x40000144 // Setup DQS and DQ on/off sequence, data type: x393_mcntr_dqs_dqm_tri_t (rw)
#define X393_MCNTRL_WBUF_DLY                             0x40000148 // Set write buffer delay, data type: x393_wbuf_dly_t (rw)
#define X393_MCONTR_TOP_16BIT_STATUS_CNTRL               0x4000014c // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCONTR_PHY_STATUS_CNTRL                     0x40000150 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
// RESERVED: 0xb DWORDs
#define X393_MCNTRL_ARBITER_PRIORITY__0                  0x40000180 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__1                  0x40000184 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__2                  0x40000188 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__3                  0x4000018c // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__4                  0x40000190 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__5                  0x40000194 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__6                  0x40000198 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__7                  0x4000019c // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__8                  0x400001a0 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__9                  0x400001a4 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__10                 0x400001a8 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__11                 0x400001ac // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__12                 0x400001b0 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__13                 0x400001b4 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__14                 0x400001b8 // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_ARBITER_PRIORITY__15                 0x400001bc // Set memory arbiter priority (currently r/w, may become just wo), data type: x393_arbite_pri_t (rw)
#define X393_MCNTRL_CHN_EN                               0x400001c0 // Enable/disable memory channels (currently r/w, may become just wo), data type: x393_mcntr_chn_en_t (rw)
// RESERVED: 0xf DWORDs
#define X393_MCNTRL_DQ_ODLY0__0                          0x40000200 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__1                          0x40000204 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__2                          0x40000208 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__3                          0x4000020c // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__4                          0x40000210 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__5                          0x40000214 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__6                          0x40000218 // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY0__7                          0x4000021c // Lane0 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_ODLY0                            0x40000220 // Lane0 DQS output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DM_ODLY0                             0x40000224 // Lane0 DM output delay , data type: x393_dly_t (rw)
// RESERVED: 0x6 DWORDs
#define X393_MCNTRL_DQ_IDLY0__0                          0x40000240 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__1                          0x40000244 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__2                          0x40000248 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__3                          0x4000024c // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__4                          0x40000250 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__5                          0x40000254 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__6                          0x40000258 // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0__7                          0x4000025c // Lane0 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_IDLY0                            0x40000260 // Lane0 DQS input delay , data type: x393_dly_t (rw)
// RESERVED: 0x7 DWORDs
#define X393_MCNTRL_DQ_ODLY1__0                          0x40000280 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__1                          0x40000284 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__2                          0x40000288 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__3                          0x4000028c // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__4                          0x40000290 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__5                          0x40000294 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__6                          0x40000298 // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1__7                          0x4000029c // Lane1 DQ output delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_ODLY1                            0x400002a0 // Lane1 DQS output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DM_ODLY1                             0x400002a4 // Lane1 DM output delay , data type: x393_dly_t (rw)
// RESERVED: 0x6 DWORDs
#define X393_MCNTRL_DQ_IDLY1__0                          0x400002c0 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__1                          0x400002c4 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__2                          0x400002c8 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__3                          0x400002cc // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__4                          0x400002d0 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__5                          0x400002d4 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__6                          0x400002d8 // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1__7                          0x400002dc // Lane1 DQ input delays , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_IDLY1                            0x400002e0 // Lane1 DQS input delay , data type: x393_dly_t (rw)
// RESERVED: 0x7 DWORDs
#define X393_MCNTRL_CMDA_ODLY__0                         0x40000300 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__1                         0x40000304 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__2                         0x40000308 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__3                         0x4000030c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__4                         0x40000310 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__5                         0x40000314 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__6                         0x40000318 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__7                         0x4000031c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__8                         0x40000320 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__9                         0x40000324 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__10                        0x40000328 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__11                        0x4000032c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__12                        0x40000330 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__13                        0x40000334 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__14                        0x40000338 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__15                        0x4000033c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__16                        0x40000340 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__17                        0x40000344 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__18                        0x40000348 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__19                        0x4000034c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__20                        0x40000350 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__21                        0x40000354 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__22                        0x40000358 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__23                        0x4000035c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__24                        0x40000360 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__25                        0x40000364 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__26                        0x40000368 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__27                        0x4000036c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__28                        0x40000370 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__29                        0x40000374 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__30                        0x40000378 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__31                        0x4000037c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_PHASE                                0x40000380 // Clock phase, data type: x393_dly_t (rw)
// RESERVED: 0x13 DWORDs
#define X393_MCNTRL_TEST01_CHN2_MODE                     0x400003d0 // Set command for test01 channel 2, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN2_STATUS_CNTRL             0x400003d4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_TEST01_CHN3_MODE                     0x400003d8 // Set command for test01 channel 3, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN3_STATUS_CNTRL             0x400003dc // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_TEST01_CHN4_MODE                     0x400003e0 // Set command for test01 channel 4, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN4_STATUS_CNTRL             0x400003e4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x6 DWORDs
#define X393_MCNTRL_PS_EN_RST                            0x40000400 // Set PS PIO enable and reset, data type: x393_ps_pio_en_rst_t (wo)
#define X393_MCNTRL_PS_CMD                               0x40000404 // Set PS PIO commands, data type: x393_ps_pio_cmd_t (wo)
#define X393_MCNTRL_PS_STATUS_CNTRL                      0x40000408 // Set PS PIO status control register (status update mode), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x1d DWORDs
#define X393_MEMBRIDGE_SCANLINE_MODE                     0x40000480 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MEMBRIDGE_SCANLINE_STATUS_CNTRL             0x40000484 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MEMBRIDGE_SCANLINE_STARTADDR                0x40000488 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_SIZE               0x4000048c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_LAST               0x40000490 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_FULL_WIDTH         0x40000494 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MEMBRIDGE_SCANLINE_WINDOW_WH                0x40000498 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MEMBRIDGE_SCANLINE_WINDOW_X0Y0              0x4000049c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MEMBRIDGE_SCANLINE_STARTXY                  0x400004a0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_MCNTRL_CHN3_SCANLINE_MODE                   0x400004c0 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_STATUS_CNTRL           0x400004c4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN3_SCANLINE_STARTADDR              0x400004c8 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_SIZE             0x400004cc // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_LAST             0x400004d0 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_FULL_WIDTH       0x400004d4 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_WINDOW_WH              0x400004d8 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_WINDOW_X0Y0            0x400004dc // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_STARTXY                0x400004e0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_MCNTRL_CHN2_TILED_MODE                      0x40000500 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN2_TILED_STATUS_CNTRL              0x40000504 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN2_TILED_STARTADDR                 0x40000508 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_SIZE                0x4000050c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_LAST                0x40000510 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_FULL_WIDTH          0x40000514 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN2_TILED_WINDOW_WH                 0x40000518 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN2_TILED_WINDOW_X0Y0               0x4000051c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN2_TILED_STARTXY                   0x40000520 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_MCNTRL_CHN2_TILED_TILE_WHS                  0x40000524 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0x6 DWORDs
#define X393_MCNTRL_CHN4_TILED_MODE                      0x40000540 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN4_TILED_STATUS_CNTRL              0x40000544 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN4_TILED_STARTADDR                 0x40000548 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_SIZE                0x4000054c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_LAST                0x40000550 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_FULL_WIDTH          0x40000554 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN4_TILED_WINDOW_WH                 0x40000558 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN4_TILED_WINDOW_X0Y0               0x4000055c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN4_TILED_STARTXY                   0x40000560 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_MCNTRL_CHN4_TILED_TILE_WHS                  0x40000564 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0xa6 DWORDs
#define X393_MEMBRIDGE_CTRL                              0x40000800 // Issue membridge command, data type: x393_membridge_cmd_t (wo)
#define X393_MEMBRIDGE_STATUS_CNTRL                      0x40000804 // Set membridge status control register, data type: x393_status_ctrl_t (rw)
#define X393_MEMBRIDGE_LO_ADDR64                         0x40000808 // start address of the system memory range in QWORDs (4 LSBs==0), data type: u29_t (wo)
#define X393_MEMBRIDGE_SIZE64                            0x4000080c // size of the system memory range in QWORDs (4 LSBs==0), rolls over, data type: u29_t (wo)
#define X393_MEMBRIDGE_START64                           0x40000810 // start of transfer offset to system memory range in QWORDs (4 LSBs==0), data type: u29_t (wo)
#define X393_MEMBRIDGE_LEN64                             0x40000814 // Full length of transfer in QWORDs, data type: u29_t (wo)
#define X393_MEMBRIDGE_WIDTH64                           0x40000818 // Frame width in QWORDs (last xfer in each line may be partial), data type: u29_t (wo)
#define X393_MEMBRIDGE_MODE                              0x4000081c // AXI cache mode, data type: x393_membridge_mode_t (wo)
// RESERVED: 0x1f8 DWORDs
#define X393_SENS_MODE__0                                0x40001000 // Write sensor channel mode, data type: x393_sens_mode_t (wo)
// RESERVED: 0x1 DWORD
#define X393_SENSI2C_CTRL__0                             0x40001008 // Control sensor i2c, write i2c LUT, data type: x393_i2c_ctltbl_t (wo)
#define X393_SENSI2C_STATUS_CTRL__0                      0x4000100c // Setup sensor i2c status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x2 DWORDs
#define X393_SENS_SYNC_MULT__0                           0x40001018 // Configure frames combining, data type: x393_sens_sync_mult_t (wo)
#define X393_SENS_SYNC_LATE__0                           0x4000101c // Configure frame sync delay, data type: x393_sens_sync_late_t (wo)
#define X393_SENSIO_CTRL__0                              0x40001020 // Configure sensor I/O port, data type: x393_sensio_ctl_t (wo)
#define X393_SENSIO_STATUS_CNTRL__0                      0x40001024 // Set status control for SENSIO module, data type: x393_status_ctrl_t (rw)
#define X393_SENSIO_JTAG__0                              0x40001028 // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS), data type: x393_sensio_jpag_t (wo)
#define X393_SENSIO_WIDTH__0                             0x4000102c // Set sensor line in pixels (0 - use line sync from the sensor), data type: x393_sensio_width_t (rw)
#define X393_SENSIO_TIM0__0                              0x40001030 // Sensor port i/o timing configuration, register 0, data type: x393_sensio_tim0_t (rw)
#define X393_SENSIO_TIM1__0                              0x40001034 // Sensor port i/o timing configuration, register 1, data type: x393_sensio_tim1_t (rw)
#define X393_SENSIO_TIM2__0                              0x40001038 // Sensor port i/o timing configuration, register 2, data type: x393_sensio_tim2_t (rw)
#define X393_SENSIO_TIM3__0                              0x4000103c // Sensor port i/o timing configuration, register 3, data type: x393_sensio_tim3_t (rw)
#define X393_SENSI2C_ABS__0__0                           0x40001040 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__1                           0x40001044 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__2                           0x40001048 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__3                           0x4000104c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__4                           0x40001050 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__5                           0x40001054 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__6                           0x40001058 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__7                           0x4000105c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__8                           0x40001060 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__9                           0x40001064 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__10                          0x40001068 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__11                          0x4000106c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__12                          0x40001070 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__13                          0x40001074 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__14                          0x40001078 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__0__15                          0x4000107c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__0                           0x40001080 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__1                           0x40001084 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__2                           0x40001088 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__3                           0x4000108c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__4                           0x40001090 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__5                           0x40001094 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__6                           0x40001098 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__7                           0x4000109c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__8                           0x400010a0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__9                           0x400010a4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__10                          0x400010a8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__11                          0x400010ac // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__12                          0x400010b0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__13                          0x400010b4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__14                          0x400010b8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__0__15                          0x400010bc // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_HISTOGRAM_LT0__0                            0x400010c0 // Specify histogram 0 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH0__0                            0x400010c4 // Specify histogram 0 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT1__0                            0x400010c8 // Specify histogram 1 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH1__0                            0x400010cc // Specify histogram 1 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT2__0                            0x400010d0 // Specify histogram 2 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH2__0                            0x400010d4 // Specify histogram 2 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT3__0                            0x400010d8 // Specify histogram 3 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH3__0                            0x400010dc // Specify histogram 3 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_SENS_GAMMA_CTRL__0                          0x400010e0 // Gamma module control, data type: x393_gamma_ctl_t (rw)
#define X393_SENS_GAMMA_TBL__0                           0x400010e4 // Write sensor gamma table address/data (with autoincrement), data type: x393_gamma_tbl_t (wo)
#define X393_SENS_GAMMA_HEIGHT01M1__0                    0x400010e8 // Gamma module subframes 0,1 heights minus 1, data type: x393_gamma_height01m1_t (rw)
#define X393_SENS_GAMMA_HEIGHT2M1__0                     0x400010ec // Gamma module subframe  2 height minus 1, data type: x393_gamma_height2m1_t (rw)
#define X393_LENS_HEIGHT0_M1__0                          0x400010f0 // Subframe 0 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT1_M1__0                          0x400010f4 // Subframe 1 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT2_M1__0                          0x400010f8 // Subframe 2 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_CORR_CNH_ADDR_DATA__0                  0x400010fc // Combined address/data to write lens vignetting correction coefficients, data type: x393_lens_corr_t (wo)
#define X393_SENS_MODE__1                                0x40001100 // Write sensor channel mode, data type: x393_sens_mode_t (wo)
// RESERVED: 0x1 DWORD
#define X393_SENSI2C_CTRL__1                             0x40001108 // Control sensor i2c, write i2c LUT, data type: x393_i2c_ctltbl_t (wo)
#define X393_SENSI2C_STATUS_CTRL__1                      0x4000110c // Setup sensor i2c status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x2 DWORDs
#define X393_SENS_SYNC_MULT__1                           0x40001118 // Configure frames combining, data type: x393_sens_sync_mult_t (wo)
#define X393_SENS_SYNC_LATE__1                           0x4000111c // Configure frame sync delay, data type: x393_sens_sync_late_t (wo)
#define X393_SENSIO_CTRL__1                              0x40001120 // Configure sensor I/O port, data type: x393_sensio_ctl_t (wo)
#define X393_SENSIO_STATUS_CNTRL__1                      0x40001124 // Set status control for SENSIO module, data type: x393_status_ctrl_t (rw)
#define X393_SENSIO_JTAG__1                              0x40001128 // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS), data type: x393_sensio_jpag_t (wo)
#define X393_SENSIO_WIDTH__1                             0x4000112c // Set sensor line in pixels (0 - use line sync from the sensor), data type: x393_sensio_width_t (rw)
#define X393_SENSIO_TIM0__1                              0x40001130 // Sensor port i/o timing configuration, register 0, data type: x393_sensio_tim0_t (rw)
#define X393_SENSIO_TIM1__1                              0x40001134 // Sensor port i/o timing configuration, register 1, data type: x393_sensio_tim1_t (rw)
#define X393_SENSIO_TIM2__1                              0x40001138 // Sensor port i/o timing configuration, register 2, data type: x393_sensio_tim2_t (rw)
#define X393_SENSIO_TIM3__1                              0x4000113c // Sensor port i/o timing configuration, register 3, data type: x393_sensio_tim3_t (rw)
#define X393_SENSI2C_ABS__1__0                           0x40001140 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__1                           0x40001144 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__2                           0x40001148 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__3                           0x4000114c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__4                           0x40001150 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__5                           0x40001154 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__6                           0x40001158 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__7                           0x4000115c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__8                           0x40001160 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__9                           0x40001164 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__10                          0x40001168 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__11                          0x4000116c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__12                          0x40001170 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__13                          0x40001174 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__14                          0x40001178 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__1__15                          0x4000117c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__0                           0x40001180 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__1                           0x40001184 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__2                           0x40001188 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__3                           0x4000118c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__4                           0x40001190 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__5                           0x40001194 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__6                           0x40001198 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__7                           0x4000119c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__8                           0x400011a0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__9                           0x400011a4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__10                          0x400011a8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__11                          0x400011ac // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__12                          0x400011b0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__13                          0x400011b4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__14                          0x400011b8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__1__15                          0x400011bc // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_HISTOGRAM_LT0__1                            0x400011c0 // Specify histogram 0 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH0__1                            0x400011c4 // Specify histogram 0 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT1__1                            0x400011c8 // Specify histogram 1 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH1__1                            0x400011cc // Specify histogram 1 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT2__1                            0x400011d0 // Specify histogram 2 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH2__1                            0x400011d4 // Specify histogram 2 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT3__1                            0x400011d8 // Specify histogram 3 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH3__1                            0x400011dc // Specify histogram 3 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_SENS_GAMMA_CTRL__1                          0x400011e0 // Gamma module control, data type: x393_gamma_ctl_t (rw)
#define X393_SENS_GAMMA_TBL__1                           0x400011e4 // Write sensor gamma table address/data (with autoincrement), data type: x393_gamma_tbl_t (wo)
#define X393_SENS_GAMMA_HEIGHT01M1__1                    0x400011e8 // Gamma module subframes 0,1 heights minus 1, data type: x393_gamma_height01m1_t (rw)
#define X393_SENS_GAMMA_HEIGHT2M1__1                     0x400011ec // Gamma module subframe  2 height minus 1, data type: x393_gamma_height2m1_t (rw)
#define X393_LENS_HEIGHT0_M1__1                          0x400011f0 // Subframe 0 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT1_M1__1                          0x400011f4 // Subframe 1 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT2_M1__1                          0x400011f8 // Subframe 2 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_CORR_CNH_ADDR_DATA__1                  0x400011fc // Combined address/data to write lens vignetting correction coefficients, data type: x393_lens_corr_t (wo)
#define X393_SENS_MODE__2                                0x40001200 // Write sensor channel mode, data type: x393_sens_mode_t (wo)
// RESERVED: 0x1 DWORD
#define X393_SENSI2C_CTRL__2                             0x40001208 // Control sensor i2c, write i2c LUT, data type: x393_i2c_ctltbl_t (wo)
#define X393_SENSI2C_STATUS_CTRL__2                      0x4000120c // Setup sensor i2c status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x2 DWORDs
#define X393_SENS_SYNC_MULT__2                           0x40001218 // Configure frames combining, data type: x393_sens_sync_mult_t (wo)
#define X393_SENS_SYNC_LATE__2                           0x4000121c // Configure frame sync delay, data type: x393_sens_sync_late_t (wo)
#define X393_SENSIO_CTRL__2                              0x40001220 // Configure sensor I/O port, data type: x393_sensio_ctl_t (wo)
#define X393_SENSIO_STATUS_CNTRL__2                      0x40001224 // Set status control for SENSIO module, data type: x393_status_ctrl_t (rw)
#define X393_SENSIO_JTAG__2                              0x40001228 // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS), data type: x393_sensio_jpag_t (wo)
#define X393_SENSIO_WIDTH__2                             0x4000122c // Set sensor line in pixels (0 - use line sync from the sensor), data type: x393_sensio_width_t (rw)
#define X393_SENSIO_TIM0__2                              0x40001230 // Sensor port i/o timing configuration, register 0, data type: x393_sensio_tim0_t (rw)
#define X393_SENSIO_TIM1__2                              0x40001234 // Sensor port i/o timing configuration, register 1, data type: x393_sensio_tim1_t (rw)
#define X393_SENSIO_TIM2__2                              0x40001238 // Sensor port i/o timing configuration, register 2, data type: x393_sensio_tim2_t (rw)
#define X393_SENSIO_TIM3__2                              0x4000123c // Sensor port i/o timing configuration, register 3, data type: x393_sensio_tim3_t (rw)
#define X393_SENSI2C_ABS__2__0                           0x40001240 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__1                           0x40001244 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__2                           0x40001248 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__3                           0x4000124c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__4                           0x40001250 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__5                           0x40001254 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__6                           0x40001258 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__7                           0x4000125c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__8                           0x40001260 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__9                           0x40001264 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__10                          0x40001268 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__11                          0x4000126c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__12                          0x40001270 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__13                          0x40001274 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__14                          0x40001278 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__2__15                          0x4000127c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__0                           0x40001280 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__1                           0x40001284 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__2                           0x40001288 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__3                           0x4000128c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__4                           0x40001290 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__5                           0x40001294 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__6                           0x40001298 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__7                           0x4000129c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__8                           0x400012a0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__9                           0x400012a4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__10                          0x400012a8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__11                          0x400012ac // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__12                          0x400012b0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__13                          0x400012b4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__14                          0x400012b8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__2__15                          0x400012bc // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_HISTOGRAM_LT0__2                            0x400012c0 // Specify histogram 0 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH0__2                            0x400012c4 // Specify histogram 0 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT1__2                            0x400012c8 // Specify histogram 1 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH1__2                            0x400012cc // Specify histogram 1 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT2__2                            0x400012d0 // Specify histogram 2 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH2__2                            0x400012d4 // Specify histogram 2 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT3__2                            0x400012d8 // Specify histogram 3 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH3__2                            0x400012dc // Specify histogram 3 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_SENS_GAMMA_CTRL__2                          0x400012e0 // Gamma module control, data type: x393_gamma_ctl_t (rw)
#define X393_SENS_GAMMA_TBL__2                           0x400012e4 // Write sensor gamma table address/data (with autoincrement), data type: x393_gamma_tbl_t (wo)
#define X393_SENS_GAMMA_HEIGHT01M1__2                    0x400012e8 // Gamma module subframes 0,1 heights minus 1, data type: x393_gamma_height01m1_t (rw)
#define X393_SENS_GAMMA_HEIGHT2M1__2                     0x400012ec // Gamma module subframe  2 height minus 1, data type: x393_gamma_height2m1_t (rw)
#define X393_LENS_HEIGHT0_M1__2                          0x400012f0 // Subframe 0 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT1_M1__2                          0x400012f4 // Subframe 1 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT2_M1__2                          0x400012f8 // Subframe 2 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_CORR_CNH_ADDR_DATA__2                  0x400012fc // Combined address/data to write lens vignetting correction coefficients, data type: x393_lens_corr_t (wo)
#define X393_SENS_MODE__3                                0x40001300 // Write sensor channel mode, data type: x393_sens_mode_t (wo)
// RESERVED: 0x1 DWORD
#define X393_SENSI2C_CTRL__3                             0x40001308 // Control sensor i2c, write i2c LUT, data type: x393_i2c_ctltbl_t (wo)
#define X393_SENSI2C_STATUS_CTRL__3                      0x4000130c // Setup sensor i2c status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x2 DWORDs
#define X393_SENS_SYNC_MULT__3                           0x40001318 // Configure frames combining, data type: x393_sens_sync_mult_t (wo)
#define X393_SENS_SYNC_LATE__3                           0x4000131c // Configure frame sync delay, data type: x393_sens_sync_late_t (wo)
#define X393_SENSIO_CTRL__3                              0x40001320 // Configure sensor I/O port, data type: x393_sensio_ctl_t (wo)
#define X393_SENSIO_STATUS_CNTRL__3                      0x40001324 // Set status control for SENSIO module, data type: x393_status_ctrl_t (rw)
#define X393_SENSIO_JTAG__3                              0x40001328 // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS), data type: x393_sensio_jpag_t (wo)
#define X393_SENSIO_WIDTH__3                             0x4000132c // Set sensor line in pixels (0 - use line sync from the sensor), data type: x393_sensio_width_t (rw)
#define X393_SENSIO_TIM0__3                              0x40001330 // Sensor port i/o timing configuration, register 0, data type: x393_sensio_tim0_t (rw)
#define X393_SENSIO_TIM1__3                              0x40001334 // Sensor port i/o timing configuration, register 1, data type: x393_sensio_tim1_t (rw)
#define X393_SENSIO_TIM2__3                              0x40001338 // Sensor port i/o timing configuration, register 2, data type: x393_sensio_tim2_t (rw)
#define X393_SENSIO_TIM3__3                              0x4000133c // Sensor port i/o timing configuration, register 3, data type: x393_sensio_tim3_t (rw)
#define X393_SENSI2C_ABS__3__0                           0x40001340 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__1                           0x40001344 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__2                           0x40001348 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__3                           0x4000134c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__4                           0x40001350 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__5                           0x40001354 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__6                           0x40001358 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__7                           0x4000135c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__8                           0x40001360 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__9                           0x40001364 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__10                          0x40001368 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__11                          0x4000136c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__12                          0x40001370 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__13                          0x40001374 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__14                          0x40001378 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_ABS__3__15                          0x4000137c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__0                           0x40001380 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__1                           0x40001384 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__2                           0x40001388 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__3                           0x4000138c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__4                           0x40001390 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__5                           0x40001394 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__6                           0x40001398 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__7                           0x4000139c // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__8                           0x400013a0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__9                           0x400013a4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__10                          0x400013a8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__11                          0x400013ac // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__12                          0x400013b0 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__13                          0x400013b4 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__14                          0x400013b8 // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_SENSI2C_REL__3__15                          0x400013bc // Write sensor i2c sequencer, data type: u32 (wo)
#define X393_HISTOGRAM_LT0__3                            0x400013c0 // Specify histogram 0 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH0__3                            0x400013c4 // Specify histogram 0 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT1__3                            0x400013c8 // Specify histogram 1 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH1__3                            0x400013cc // Specify histogram 1 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT2__3                            0x400013d0 // Specify histogram 2 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH2__3                            0x400013d4 // Specify histogram 2 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT3__3                            0x400013d8 // Specify histogram 3 left/top, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH3__3                            0x400013dc // Specify histogram 3 width/height, data type: x393_hist_width_height_m1_t (rw)
#define X393_SENS_GAMMA_CTRL__3                          0x400013e0 // Gamma module control, data type: x393_gamma_ctl_t (rw)
#define X393_SENS_GAMMA_TBL__3                           0x400013e4 // Write sensor gamma table address/data (with autoincrement), data type: x393_gamma_tbl_t (wo)
#define X393_SENS_GAMMA_HEIGHT01M1__3                    0x400013e8 // Gamma module subframes 0,1 heights minus 1, data type: x393_gamma_height01m1_t (rw)
#define X393_SENS_GAMMA_HEIGHT2M1__3                     0x400013ec // Gamma module subframe  2 height minus 1, data type: x393_gamma_height2m1_t (rw)
#define X393_LENS_HEIGHT0_M1__3                          0x400013f0 // Subframe 0 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT1_M1__3                          0x400013f4 // Subframe 1 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT2_M1__3                          0x400013f8 // Subframe 2 height minus 1, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_CORR_CNH_ADDR_DATA__3                  0x400013fc // Combined address/data to write lens vignetting correction coefficients, data type: x393_lens_corr_t (wo)
#define X393_HIST_SAXI_ADDR__0                           0x40001400 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__1                           0x40001404 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__2                           0x40001408 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__3                           0x4000140c // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__4                           0x40001410 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__5                           0x40001414 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__6                           0x40001418 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__7                           0x4000141c // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__8                           0x40001420 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__9                           0x40001424 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__10                          0x40001428 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__11                          0x4000142c // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__12                          0x40001430 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__13                          0x40001434 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__14                          0x40001438 // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_ADDR__15                          0x4000143c // Histogram DMA addresses (in 4096 byte pages), data type: x393_hist_saxi_addr_t (rw)
#define X393_HIST_SAXI_MODE                              0x40001440 // Histogram DMA operation mode, data type: x393_hist_saxi_mode_t (rw)
// RESERVED: 0xef DWORDs
#define X393_CMPRS_CONTROL_REG__0                        0x40001800 // Program compressor channel operation mode, data type: x393_cmprs_mode_t (wo)
#define X393_CMPRS_STATUS__0                             0x40001804 // Setup compressor status report mode, data type: x393_status_ctrl_t (rw)
#define X393_CMPRS_FORMAT__0                             0x40001808 // Compressor frame format, data type: x393_cmprs_frame_format_t (rw)
#define X393_CMPRS_COLOR_SATURATION__0                   0x4000180c // Compressor color saturation, data type: x393_cmprs_colorsat_t (rw)
#define X393_CMPRS_CORING_MODE__0                        0x40001810 // Select coring mode, data type: x393_cmprs_coring_mode_t (rw)
#define X393_CMPRS_INTERRUPTS__0                         0x40001814 // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable), data type: x393_cmprs_interrupts_t (wo)
#define X393_CMPRS_TABLES_DATA__0                        0x40001818 // Compressor tables data, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS__0                     0x4000181c // Compressor tables type/address, data type: x393_cmprs_table_addr_t (wo)
// RESERVED: 0x8 DWORDs
#define X393_CMPRS_CONTROL_REG__1                        0x40001840 // Program compressor channel operation mode, data type: x393_cmprs_mode_t (wo)
#define X393_CMPRS_STATUS__1                             0x40001844 // Setup compressor status report mode, data type: x393_status_ctrl_t (rw)
#define X393_CMPRS_FORMAT__1                             0x40001848 // Compressor frame format, data type: x393_cmprs_frame_format_t (rw)
#define X393_CMPRS_COLOR_SATURATION__1                   0x4000184c // Compressor color saturation, data type: x393_cmprs_colorsat_t (rw)
#define X393_CMPRS_CORING_MODE__1                        0x40001850 // Select coring mode, data type: x393_cmprs_coring_mode_t (rw)
#define X393_CMPRS_INTERRUPTS__1                         0x40001854 // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable), data type: x393_cmprs_interrupts_t (wo)
#define X393_CMPRS_TABLES_DATA__1                        0x40001858 // Compressor tables data, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS__1                     0x4000185c // Compressor tables type/address, data type: x393_cmprs_table_addr_t (wo)
// RESERVED: 0x8 DWORDs
#define X393_CMPRS_CONTROL_REG__2                        0x40001880 // Program compressor channel operation mode, data type: x393_cmprs_mode_t (wo)
#define X393_CMPRS_STATUS__2                             0x40001884 // Setup compressor status report mode, data type: x393_status_ctrl_t (rw)
#define X393_CMPRS_FORMAT__2                             0x40001888 // Compressor frame format, data type: x393_cmprs_frame_format_t (rw)
#define X393_CMPRS_COLOR_SATURATION__2                   0x4000188c // Compressor color saturation, data type: x393_cmprs_colorsat_t (rw)
#define X393_CMPRS_CORING_MODE__2                        0x40001890 // Select coring mode, data type: x393_cmprs_coring_mode_t (rw)
#define X393_CMPRS_INTERRUPTS__2                         0x40001894 // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable), data type: x393_cmprs_interrupts_t (wo)
#define X393_CMPRS_TABLES_DATA__2                        0x40001898 // Compressor tables data, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS__2                     0x4000189c // Compressor tables type/address, data type: x393_cmprs_table_addr_t (wo)
// RESERVED: 0x8 DWORDs
#define X393_CMPRS_CONTROL_REG__3                        0x400018c0 // Program compressor channel operation mode, data type: x393_cmprs_mode_t (wo)
#define X393_CMPRS_STATUS__3                             0x400018c4 // Setup compressor status report mode, data type: x393_status_ctrl_t (rw)
#define X393_CMPRS_FORMAT__3                             0x400018c8 // Compressor frame format, data type: x393_cmprs_frame_format_t (rw)
#define X393_CMPRS_COLOR_SATURATION__3                   0x400018cc // Compressor color saturation, data type: x393_cmprs_colorsat_t (rw)
#define X393_CMPRS_CORING_MODE__3                        0x400018d0 // Select coring mode, data type: x393_cmprs_coring_mode_t (rw)
#define X393_CMPRS_INTERRUPTS__3                         0x400018d4 // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable), data type: x393_cmprs_interrupts_t (wo)
#define X393_CMPRS_TABLES_DATA__3                        0x400018d8 // Compressor tables data, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS__3                     0x400018dc // Compressor tables type/address, data type: x393_cmprs_table_addr_t (wo)
// RESERVED: 0x8 DWORDs
#define X393_AFIMUX0_EN                                  0x40001900 // AFI MUX 0 global/port run/pause control, data type: x393_afimux_en_t (wo)
#define X393_AFIMUX0_RST                                 0x40001904 // AFI MUX 0 per-port resets, data type: x393_afimux_rst_t (rw)
#define X393_AFIMUX0_REPORT_MODE                         0x40001908 // AFI MUX 0 readout pointer report mode, data type: x393_afimux_report_t (wo)
// RESERVED: 0x1 DWORD
#define X393_AFIMUX0_STATUS_CONTROL                      0x40001910 // AFI MUX 0 status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x3 DWORDs
#define X393_AFIMUX0_SA__0                               0x40001920 // AFI MUX 0 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX0_SA__1                               0x40001924 // AFI MUX 0 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX0_SA__2                               0x40001928 // AFI MUX 0 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX0_SA__3                               0x4000192c // AFI MUX 0 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX0_LEN__0                              0x40001930 // AFI MUX 0 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX0_LEN__1                              0x40001934 // AFI MUX 0 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX0_LEN__2                              0x40001938 // AFI MUX 0 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX0_LEN__3                              0x4000193c // AFI MUX 0 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX1_EN                                  0x40001940 // AFI MUX 1 global/port run/pause control, data type: x393_afimux_en_t (wo)
#define X393_AFIMUX1_RST                                 0x40001944 // AFI MUX 1 per-port resets, data type: x393_afimux_rst_t (rw)
#define X393_AFIMUX1_REPORT_MODE                         0x40001948 // AFI MUX 1 readout pointer report mode, data type: x393_afimux_report_t (wo)
// RESERVED: 0x1 DWORD
#define X393_AFIMUX1_STATUS_CONTROL                      0x40001950 // AFI MUX 1 status report mode, data type: x393_status_ctrl_t (rw)
// RESERVED: 0x3 DWORDs
#define X393_AFIMUX1_SA__0                               0x40001960 // AFI MUX 1 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX1_SA__1                               0x40001964 // AFI MUX 1 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX1_SA__2                               0x40001968 // AFI MUX 1 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX1_SA__3                               0x4000196c // AFI MUX 1 DMA buffer start address in 32-byte blocks, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX1_LEN__0                              0x40001970 // AFI MUX 1 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX1_LEN__1                              0x40001974 // AFI MUX 1 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX1_LEN__2                              0x40001978 // AFI MUX 1 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
#define X393_AFIMUX1_LEN__3                              0x4000197c // AFI MUX 1 DMA buffer length in 32-byte blocks, data type: x393_afimux_len_t (rw)
// RESERVED: 0x20 DWORDs
#define X393_SENS_MCNTRL_SCANLINE_MODE__0                0x40001a00 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL__0        0x40001a04 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_SCANLINE_STARTADDR__0           0x40001a08 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_SIZE__0          0x40001a0c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_LAST__0          0x40001a10 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH__0    0x40001a14 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_WH__0           0x40001a18 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0__0         0x40001a1c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STARTXY__0             0x40001a20 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_SENS_MCNTRL_SCANLINE_MODE__1                0x40001a40 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL__1        0x40001a44 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_SCANLINE_STARTADDR__1           0x40001a48 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_SIZE__1          0x40001a4c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_LAST__1          0x40001a50 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH__1    0x40001a54 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_WH__1           0x40001a58 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0__1         0x40001a5c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STARTXY__1             0x40001a60 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_SENS_MCNTRL_SCANLINE_MODE__2                0x40001a80 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL__2        0x40001a84 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_SCANLINE_STARTADDR__2           0x40001a88 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_SIZE__2          0x40001a8c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_LAST__2          0x40001a90 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH__2    0x40001a94 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_WH__2           0x40001a98 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0__2         0x40001a9c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STARTXY__2             0x40001aa0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_SENS_MCNTRL_SCANLINE_MODE__3                0x40001ac0 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL__3        0x40001ac4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_SCANLINE_STARTADDR__3           0x40001ac8 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_SIZE__3          0x40001acc // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_LAST__3          0x40001ad0 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH__3    0x40001ad4 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_WH__3           0x40001ad8 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0__3         0x40001adc // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STARTXY__3             0x40001ae0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// RESERVED: 0x7 DWORDs
#define X393_SENS_MCNTRL_TILED_MODE__0                   0x40001b00 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_TILED_STATUS_CNTRL__0           0x40001b04 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_TILED_STARTADDR__0              0x40001b08 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_SIZE__0             0x40001b0c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_LAST__0             0x40001b10 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_FULL_WIDTH__0       0x40001b14 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_WH__0              0x40001b18 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_X0Y0__0            0x40001b1c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_TILED_STARTXY__0                0x40001b20 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_SENS_MCNTRL_TILED_TILE_WHS__0               0x40001b24 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0x6 DWORDs
#define X393_SENS_MCNTRL_TILED_MODE__1                   0x40001b40 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_TILED_STATUS_CNTRL__1           0x40001b44 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_TILED_STARTADDR__1              0x40001b48 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_SIZE__1             0x40001b4c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_LAST__1             0x40001b50 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_FULL_WIDTH__1       0x40001b54 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_WH__1              0x40001b58 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_X0Y0__1            0x40001b5c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_TILED_STARTXY__1                0x40001b60 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_SENS_MCNTRL_TILED_TILE_WHS__1               0x40001b64 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0x6 DWORDs
#define X393_SENS_MCNTRL_TILED_MODE__2                   0x40001b80 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_TILED_STATUS_CNTRL__2           0x40001b84 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_TILED_STARTADDR__2              0x40001b88 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_SIZE__2             0x40001b8c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_LAST__2             0x40001b90 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_FULL_WIDTH__2       0x40001b94 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_WH__2              0x40001b98 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_X0Y0__2            0x40001b9c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_TILED_STARTXY__2                0x40001ba0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_SENS_MCNTRL_TILED_TILE_WHS__2               0x40001ba4 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0x6 DWORDs
#define X393_SENS_MCNTRL_TILED_MODE__3                   0x40001bc0 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_TILED_STATUS_CNTRL__3           0x40001bc4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_TILED_STARTADDR__3              0x40001bc8 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_SIZE__3             0x40001bcc // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_LAST__3             0x40001bd0 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_FULL_WIDTH__3       0x40001bd4 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_WH__3              0x40001bd8 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_X0Y0__3            0x40001bdc // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_TILED_STARTXY__3                0x40001be0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_SENS_MCNTRL_TILED_TILE_WHS__3               0x40001be4 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// RESERVED: 0x6 DWORDs
#define X393_GPIO_SET_PINS                               0x40001c00 // State of the GPIO pins and seq. number, data type: x393_gpio_set_pins_t (wo)
#define X393_GPIO_STATUS_CONTROL                         0x40001c04 // GPIO status control mode, data type: x393_status_ctrl_t (rw)
#define X393_CMDSEQMUX_STATUS_CTRL                       0x40001c08 // CMDSEQMUX status control mode (status provides current frame numbers), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x1 DWORD
#define X393_RTC_USEC                                    0x40001c10 // RTC microseconds, data type: x393_rtc_usec_t (rw)
#define X393_RTC_SEC_SET                                 0x40001c14 // RTC seconds and set clock, data type: x393_rtc_sec_t (rw)
#define X393_RTC_CORR                                    0x40001c18 // RTC correction (+/- 1/256 full scale), data type: x393_rtc_corr_t (rw)
#define X393_RTC_SET_STATUS                              0x40001c1c // RTC status control mode, write makes a snapshot to be read out, data type: x393_status_ctrl_t (rw)
#define X393_CAMSYNC_MODE                                0x40001c20 // CAMSYNC mode, data type: x393_camsync_mode_t (wo)
#define X393_CAMSYNC_TRIG_SRC                            0x40001c24 // CAMSYNC trigger source, data type: x393_camsync_io_t (wo)
#define X393_CAMSYNC_TRIG_DST                            0x40001c28 // CAMSYNC trigger destination, data type: x393_camsync_io_t (wo)
#define X393_CAMSYNC_TRIG_PERIOD                         0x40001c2c // CAMSYNC trigger period, data type: u32 (rw)
#define X393_CAMSYNC_TRIG_DELAY__0                       0x40001c30 // CAMSYNC trigger delay, data type: u32 (rw)
#define X393_CAMSYNC_TRIG_DELAY__1                       0x40001c34 // CAMSYNC trigger delay, data type: u32 (rw)
#define X393_CAMSYNC_TRIG_DELAY__2                       0x40001c38 // CAMSYNC trigger delay, data type: u32 (rw)
#define X393_CAMSYNC_TRIG_DELAY__3                       0x40001c3c // CAMSYNC trigger delay, data type: u32 (rw)
#define X393_DEBUG_SHIFT                                 0x40001c40 // Debug ring shift ring by 32 bits, data type: u32 (wo)
#define X393_DEBUG_LOAD                                  0x40001c44 // Debug ring copy shift register to/from tested modules
#define X393_DEBUG_STATUS_CTRL                           0x40001c48 // Debug ring status generation - set to auto(3) if used, data type: x393_status_ctrl_t (rw)
// RESERVED: 0xd DWORDs
#define X393_LOGGER_DATA                                 0x40001c80 // Logger register write data, data type: x393_logger_data_t (wo)
#define X393_LOGGER_ADDRESS                              0x40001c84 // Logger register write page/address, data type: x393_logger_address_t (wo)
#define X393_LOGGER_STATUS_CTRL                          0x40001c88 // Logger status configuration (to report sample number), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x5 DWORDs
#define X393_MULTICLK_CTRL                               0x40001ca0 // MULTI_CLK reset and power down control, data type: x393_multiclk_ctl_t (rw)
#define X393_MULTICLK_STATUS_CTRL                        0x40001ca4 // MULTI_CLK status generation (do not use or do not set auto), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x6 DWORDs
#define X393_MULT_SAXI_BUF_ADDRESS__0                    0x40001cc0 // MULT_SAXI buffer start address in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_LEN__0                        0x40001cc4 // MULT_SAXI buffer length in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_ADDRESS__1                    0x40001cc8 // MULT_SAXI buffer start address in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_LEN__1                        0x40001ccc // MULT_SAXI buffer length in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_ADDRESS__2                    0x40001cd0 // MULT_SAXI buffer start address in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_LEN__2                        0x40001cd4 // MULT_SAXI buffer length in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_ADDRESS__3                    0x40001cd8 // MULT_SAXI buffer start address in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_LEN__3                        0x40001cdc // MULT_SAXI buffer length in DWORDS, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_STATUS_CTRL                       0x40001ce0 // MULT_SAXI status control mode (status provides current DWORD pointer), data type: x393_status_ctrl_t (rw)
// RESERVED: 0x47 DWORDs
#define X393_CMDFRAMESEQ_ABS__0__0                       0x40001e00 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__1                       0x40001e04 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__2                       0x40001e08 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__3                       0x40001e0c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__4                       0x40001e10 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__5                       0x40001e14 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__6                       0x40001e18 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__7                       0x40001e1c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__8                       0x40001e20 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__9                       0x40001e24 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__10                      0x40001e28 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__11                      0x40001e2c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__12                      0x40001e30 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__13                      0x40001e34 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__14                      0x40001e38 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__0__15                      0x40001e3c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__0                       0x40001e40 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__1                       0x40001e44 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__2                       0x40001e48 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__3                       0x40001e4c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__4                       0x40001e50 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__5                       0x40001e54 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__6                       0x40001e58 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__7                       0x40001e5c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__8                       0x40001e60 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__9                       0x40001e64 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__10                      0x40001e68 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__11                      0x40001e6c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__12                      0x40001e70 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__13                      0x40001e74 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__0__14                      0x40001e78 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_CTRL__0                         0x40001e7c // CMDFRAMESEQ control register, data type: x393_cmdframeseq_mode_t (wo)
#define X393_CMDFRAMESEQ_ABS__1__0                       0x40001e80 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__1                       0x40001e84 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__2                       0x40001e88 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__3                       0x40001e8c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__4                       0x40001e90 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__5                       0x40001e94 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__6                       0x40001e98 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__7                       0x40001e9c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__8                       0x40001ea0 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__9                       0x40001ea4 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__10                      0x40001ea8 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__11                      0x40001eac // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__12                      0x40001eb0 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__13                      0x40001eb4 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__14                      0x40001eb8 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__1__15                      0x40001ebc // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__0                       0x40001ec0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__1                       0x40001ec4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__2                       0x40001ec8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__3                       0x40001ecc // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__4                       0x40001ed0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__5                       0x40001ed4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__6                       0x40001ed8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__7                       0x40001edc // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__8                       0x40001ee0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__9                       0x40001ee4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__10                      0x40001ee8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__11                      0x40001eec // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__12                      0x40001ef0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__13                      0x40001ef4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__1__14                      0x40001ef8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_CTRL__1                         0x40001efc // CMDFRAMESEQ control register, data type: x393_cmdframeseq_mode_t (wo)
#define X393_CMDFRAMESEQ_ABS__2__0                       0x40001f00 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__1                       0x40001f04 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__2                       0x40001f08 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__3                       0x40001f0c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__4                       0x40001f10 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__5                       0x40001f14 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__6                       0x40001f18 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__7                       0x40001f1c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__8                       0x40001f20 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__9                       0x40001f24 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__10                      0x40001f28 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__11                      0x40001f2c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__12                      0x40001f30 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__13                      0x40001f34 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__14                      0x40001f38 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__2__15                      0x40001f3c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__0                       0x40001f40 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__1                       0x40001f44 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__2                       0x40001f48 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__3                       0x40001f4c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__4                       0x40001f50 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__5                       0x40001f54 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__6                       0x40001f58 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__7                       0x40001f5c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__8                       0x40001f60 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__9                       0x40001f64 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__10                      0x40001f68 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__11                      0x40001f6c // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__12                      0x40001f70 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__13                      0x40001f74 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__2__14                      0x40001f78 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_CTRL__2                         0x40001f7c // CMDFRAMESEQ control register, data type: x393_cmdframeseq_mode_t (wo)
#define X393_CMDFRAMESEQ_ABS__3__0                       0x40001f80 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__1                       0x40001f84 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__2                       0x40001f88 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__3                       0x40001f8c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__4                       0x40001f90 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__5                       0x40001f94 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__6                       0x40001f98 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__7                       0x40001f9c // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__8                       0x40001fa0 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__9                       0x40001fa4 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__10                      0x40001fa8 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__11                      0x40001fac // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__12                      0x40001fb0 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__13                      0x40001fb4 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__14                      0x40001fb8 // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_ABS__3__15                      0x40001fbc // CMDFRAMESEQ absolute frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__0                       0x40001fc0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__1                       0x40001fc4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__2                       0x40001fc8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__3                       0x40001fcc // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__4                       0x40001fd0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__5                       0x40001fd4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__6                       0x40001fd8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__7                       0x40001fdc // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__8                       0x40001fe0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__9                       0x40001fe4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__10                      0x40001fe8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__11                      0x40001fec // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__12                      0x40001ff0 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__13                      0x40001ff4 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL__3__14                      0x40001ff8 // CMDFRAMESEQ relative frame address/command, data type: u32 (wo)
#define X393_CMDFRAMESEQ_CTRL__3                         0x40001ffc // CMDFRAMESEQ control register, data type: x393_cmdframeseq_mode_t (wo)
#define X393_MCONTR_PHY_STATUS                           0x40002000 // Status register for MCNTRL PHY, data type: x393_status_mcntrl_phy_t (ro)
#define X393_MCONTR_TOP_STATUS                           0x40002004 // Status register for MCNTRL requests, data type: x393_status_mcntrl_top_t (ro)
#define X393_MCNTRL_PS_STATUS                            0x40002008 // Status register for MCNTRL software R/W, data type: x393_status_mcntrl_ps_t (ro)
// RESERVED: 0x1 DWORD
#define X393_MCNTRL_CHN1_STATUS                          0x40002010 // Status register for MCNTRL CHN1 (membridge), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN2_STATUS                          0x40002014 // Status register for MCNTRL CHN2 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN3_STATUS                          0x40002018 // Status register for MCNTRL CHN3 (scanline), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN4_STATUS                          0x4000201c // Status register for MCNTRL CHN4 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
// RESERVED: 0x10 DWORDs
#define X393_AFIMUX0_STATUS__0                           0x40002060 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX0_STATUS__1                           0x40002064 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX0_STATUS__2                           0x40002068 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX0_STATUS__3                           0x4000206c // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX1_STATUS__0                           0x40002070 // Status of the AFI MUX 1 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX1_STATUS__1                           0x40002074 // Status of the AFI MUX 1 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX1_STATUS__2                           0x40002078 // Status of the AFI MUX 1 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX1_STATUS__3                           0x4000207c // Status of the AFI MUX 1 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_SENSI2C_STATUS__0                           0x40002080 // Status of the sensors i2c, data type: x393_status_sens_i2c_t (ro)
#define X393_SENSIO_STATUS__0                            0x40002084 // Status of the sensor ports I/O pins, data type: x393_status_sens_io_t (ro)
#define X393_SENSI2C_STATUS__1                           0x40002088 // Status of the sensors i2c, data type: x393_status_sens_i2c_t (ro)
#define X393_SENSIO_STATUS__1                            0x4000208c // Status of the sensor ports I/O pins, data type: x393_status_sens_io_t (ro)
#define X393_SENSI2C_STATUS__2                           0x40002090 // Status of the sensors i2c, data type: x393_status_sens_i2c_t (ro)
#define X393_SENSIO_STATUS__2                            0x40002094 // Status of the sensor ports I/O pins, data type: x393_status_sens_io_t (ro)
#define X393_SENSI2C_STATUS__3                           0x40002098 // Status of the sensors i2c, data type: x393_status_sens_i2c_t (ro)
#define X393_SENSIO_STATUS__3                            0x4000209c // Status of the sensor ports I/O pins, data type: x393_status_sens_io_t (ro)
// RESERVED: 0x8 DWORDs
#define X393_GPIO_STATUS                                 0x400020c0 // State of the GPIO pins and seq. number, data type: x393_gpio_status_t (ro)
#define X393_RTC_STATUS                                  0x400020c4 // RTC status reg, data type: x393_rtc_status_t (ro)
#define X393_RTC_STATUS_SEC                              0x400020c8 // RTC snapshot seconds, data type: x393_rtc_sec_t (ro)
#define X393_RTC_STATUS_USEC                             0x400020cc // RTC snapshot microseconds, data type: x393_rtc_usec_t (ro)
#define X393_MULT_SAXI_STATUS__0                         0x400020d0 // MULT_SAXI current DWORD pointer, data type: x393_mult_saxi_al_t (ro)
#define X393_MULT_SAXI_STATUS__1                         0x400020d4 // MULT_SAXI current DWORD pointer, data type: x393_mult_saxi_al_t (ro)
#define X393_MULT_SAXI_STATUS__2                         0x400020d8 // MULT_SAXI current DWORD pointer, data type: x393_mult_saxi_al_t (ro)
#define X393_MULT_SAXI_STATUS__3                         0x400020dc // MULT_SAXI current DWORD pointer, data type: x393_mult_saxi_al_t (ro)
#define X393_CMDSEQMUX_STATUS                            0x400020e0 // CMDSEQMUX status data (frame numbers and interrupts, data type: x393_cmdseqmux_status_t (ro)
#define X393_LOGGER_STATUS                               0x400020e4 // Logger status data (sequence number), data type: x393_logger_status_t (ro)
#define X393_MULTICLK_STATUS                             0x400020e8 // MULTI_CLK lock and toggle state, data type: x393_multiclk_status_t (ro)
#define X393_MEMBRIDGE_STATUS                            0x400020ec // Status register for membridge, data type: x393_status_membridge_t (ro)
// RESERVED: 0x1 DWORD
#define X393_TEST01_CHN2_STATUS                          0x400020f4 // Status register for test channel 2, data type: x393_status_mcntrl_testchn_t (ro)
#define X393_TEST01_CHN3_STATUS                          0x400020f8 // Status register for test channel 3, data type: x393_status_mcntrl_testchn_t (ro)
#define X393_TEST01_CHN4_STATUS                          0x400020fc // Status register for test channel 4, data type: x393_status_mcntrl_testchn_t (ro)
// RESERVED: 0xbc DWORDs
#define X393_DEBUG_STATUS                                0x400023f0 // Debug read status (watch sequence number), data type: x393_debug_status_t (ro)
#define X393_DEBUG_READ                                  0x400023f4 // Debug read DWORD form ring register, data type: u32 (ro)

