pax_global_header 0000666 0000000 0000000 00000000064 12327044266 0014520 g ustar 00root root 0000000 0000000 52 comment=313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/ 0000775 0000000 0000000 00000000000 12327044266 0017544 5 ustar 00root root 0000000 0000000 x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/.project 0000664 0000000 0000000 00000002575 12327044266 0021224 0 ustar 00root root 0000000 0000000
eddr3
com.elphel.vdt.veditor.simulateBuilder
com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand
echo 'Clean'
com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder
0
com.elphel.vdt.veditor.simulateBuilder.00000000Default.command
echo 'No Build Configuration Specified'
com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable
true
com.elphel.vdt.veditor.simulateBuilder.00000000Default.name
Default
com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser
com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder
com.elphel.vdt.veditor.HdlNature
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/.settings/ 0000775 0000000 0000000 00000000000 12327044266 0021462 5 ustar 00root root 0000000 0000000 x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/.settings/com.elphel.vdt.prefs 0000664 0000000 0000000 00000000227 12327044266 0025346 0 ustar 00root root 0000000 0000000 com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/ 0000775 0000000 0000000 00000000000 12327044266 0020344 5 ustar 00root root 0000000 0000000 x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/ 0000775 0000000 0000000 00000000000 12327044266 0021315 5 ustar 00root root 0000000 0000000 x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/idelay_ctrl.v 0000664 0000000 0000000 00000002410 12327044266 0023774 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_ctrl
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYCTRL wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_ctrl.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_ctrl
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY"
) (
input refclk,
input rst,
output rdy
);
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYCTRL idelay_ctrl_i(
.RDY(rdy),
.REFCLK(refclk),
.RST(rst));
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/idelay_fine_pipe.v 0000664 0000000 0000000 00000005025 12327044266 0024773 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_DATAIN_INVERTED(1'b0),
.IS_IDATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
idelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.DATAIN(1'b0),
.IDATAIN(data_in),
.IFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/iserdes_mem.v 0000664 0000000 0000000 00000013651 12327044266 0024006 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: iserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: ISERDESE2/ISERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* iserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* iserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module iserdes_mem(
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
input oclk_div, // oclk divided by 2, front aligned
input rst, // reset
input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
input ddly, // serial input from idelay
output [3:0] dout
);
parameter IOBDELAY = "IFD"; // "NONE", "IBUF", "IFD", "BOTH"
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIVP (), // used with phasers, source-sync
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OCLKB (!oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
ISERDESE1 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`endif
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/odelay_fine_pipe.v 0000664 0000000 0000000 00000004763 12327044266 0025011 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: odelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: ODELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* odelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module odelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.ODELAY_TYPE("VAR_LOAD_PIPE"),
.ODELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_ODATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
odelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.CLKIN(1'b0),
.ODATAIN(data_in),
.OFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/phy/wrap/oserdes_mem.v 0000664 0000000 0000000 00000013661 12327044266 0024015 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: oserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: OSERDESE2/OSERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* oserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module oserdes_mem(
input clk, // serial output clock
input clk_div, // oclk divided by 2, front aligned
input rst, // reset
input [3:0] din, // parallel data in
input [3:0] tin, // parallel tri-state in
output dout_dly, // data out to be connected to odelay input
output dout_iob, // data out to be connected directly to the output buffer
output tout_dly, // tristate out to be connected to odelay input
output tout_iob // tristate out to be connected directly to the tristate control of the output buffer
);
/*
Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
go directly. Luckily the active time for DQ/DQS may be extended (there is at least 1 full clock period
between READ and WRITE DQS active (more for DQ), so extending write preamble and postabmble by 1/2 period
seems to be OK.
*/
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 (din[2]),
.D4 (din[3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 (tin[2]),
.T4 (tin[3]),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN ()
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.DDR3_DATA (1), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3"
.ODELAY_USED (0), // 1 available only for MEMORY_DDR3
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4)
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 (din[2]),
.D4 (din[3]),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 (tin[2]),
.T4 (tin[3]),
.TCE (1'b1),
// not in OSERDES2E:
.WC (1'b0),
.OCBEXTEND (),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.ODV (1'b0)
);
`endif
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ 0000775 0000000 0000000 00000000000 12327044266 0021233 5 ustar 00root root 0000000 0000000 x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/AND2B1L.v 0000664 0000000 0000000 00000002741 12327044266 0022411 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.i (L.40)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Latch used as 2-input AND Gate
// /___/ /\ Filename : AND2B1L.v
// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009
// \___\/\___\
//
// Revision:
// 04/01/08 - Initial version.
// 04/14/09 - Invert SRI not DI (CR517897)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AND2B1L #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_SRI_INVERTED = 1'b0
)(
output O,
input DI,
input SRI
);
tri0 GSR = glbl.GSR;
wire o_out, sri_b;
wire SRI_in;
assign O = (GSR) ? 0 : o_out;
not A0 (sri_b, SRI_in);
and A1 (o_out, sri_b, DI);
assign SRI_in = IS_SRI_INVERTED ^ SRI;
`ifdef XIL_TIMING
specify
(DI => O) = (0:0:0, 0:0:0);
(SRI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/AUTOBUF.v 0000664 0000000 0000000 00000003241 12327044266 0022527 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AUTOBUF.v,v 1.2 2008/09/04 22:14:49 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BIBUF.v 0000664 0000000 0000000 00000001531 12327044266 0022251 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.1
// \ \ Description : Xilinx Simulation Library Component
// / / Bi-Directional IO
// /___/ /\ Filename : BIBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BIBUF (PAD, IO);
inout PAD;
inout IO;
wire PAD_io;
wire IO_io;
assign #10 PAD_io = PAD;
assign #10 IO_io = IO;
assign (weak1, weak0) IO = PAD_io;
assign (weak1, weak0) PAD = IO_io;
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BITSLICE_CONTROL.v 0000664 0000000 0000000 00000132243 12327044266 0024025 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : BITSLICE_CONTROL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BITSLICE_CONTROL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CTRL_CLK = "EXTERNAL",
parameter DIV_MODE = "DIV2",
parameter EN_CLK_TO_EXT_NORTH = "DISABLE",
parameter EN_CLK_TO_EXT_SOUTH = "DISABLE",
parameter EN_DYN_ODLY_MODE = "FALSE",
parameter EN_OTHER_NCLK = "FALSE",
parameter EN_OTHER_PCLK = "FALSE",
parameter IDLY_VT_TRACK = "TRUE",
parameter INV_RXCLK = "FALSE",
parameter ODLY_VT_TRACK = "TRUE",
parameter QDLY_VT_TRACK = "TRUE",
parameter [5:0] READ_IDLE_COUNT = 6'h00,
parameter REFCLK_SRC = "PLLCLK",
parameter integer ROUNDING_FACTOR = 16,
parameter RXGATE_EXTEND = "FALSE",
parameter RX_CLK_PHASE_N = "SHIFT_0",
parameter RX_CLK_PHASE_P = "SHIFT_0",
parameter RX_GATING = "DISABLE",
parameter SELF_CALIBRATE = "ENABLE",
parameter SERIAL_MODE = "FALSE",
parameter TX_GATING = "DISABLE"
)(
output BISC_START_OUT,
output BISC_STOP_OUT,
output CLK_TO_EXT_NORTH,
output CLK_TO_EXT_SOUTH,
output DLY_RDY,
output [6:0] DYN_DCI,
output NCLK_NIBBLE_OUT,
output PCLK_NIBBLE_OUT,
output [15:0] RIU_RD_DATA,
output RIU_VALID,
output [23:0] RX_BIT_CTRL_OUT0,
output [23:0] RX_BIT_CTRL_OUT1,
output [23:0] RX_BIT_CTRL_OUT2,
output [23:0] RX_BIT_CTRL_OUT3,
output [23:0] RX_BIT_CTRL_OUT4,
output [23:0] RX_BIT_CTRL_OUT5,
output [23:0] RX_BIT_CTRL_OUT6,
output [26:0] TX_BIT_CTRL_OUT0,
output [26:0] TX_BIT_CTRL_OUT1,
output [26:0] TX_BIT_CTRL_OUT2,
output [26:0] TX_BIT_CTRL_OUT3,
output [26:0] TX_BIT_CTRL_OUT4,
output [26:0] TX_BIT_CTRL_OUT5,
output [26:0] TX_BIT_CTRL_OUT6,
output [34:0] TX_BIT_CTRL_OUT_TRI,
output VTC_RDY,
input BISC_START_IN,
input BISC_STOP_IN,
input CLK_FROM_EXT,
input EN_VTC,
input NCLK_NIBBLE_IN,
input PCLK_NIBBLE_IN,
input [3:0] PHY_RDCS0,
input [3:0] PHY_RDCS1,
input [3:0] PHY_RDEN,
input [3:0] PHY_WRCS0,
input [3:0] PHY_WRCS1,
input PLL_CLK,
input REFCLK,
input [5:0] RIU_ADDR,
input RIU_CLK,
input RIU_NIBBLE_SEL,
input [15:0] RIU_WR_DATA,
input RIU_WR_EN,
input RST,
input [34:0] RX_BIT_CTRL_IN0,
input [34:0] RX_BIT_CTRL_IN1,
input [34:0] RX_BIT_CTRL_IN2,
input [34:0] RX_BIT_CTRL_IN3,
input [34:0] RX_BIT_CTRL_IN4,
input [34:0] RX_BIT_CTRL_IN5,
input [34:0] RX_BIT_CTRL_IN6,
input [3:0] TBYTE_IN,
input [29:0] TX_BIT_CTRL_IN0,
input [29:0] TX_BIT_CTRL_IN1,
input [29:0] TX_BIT_CTRL_IN2,
input [29:0] TX_BIT_CTRL_IN3,
input [29:0] TX_BIT_CTRL_IN4,
input [29:0] TX_BIT_CTRL_IN5,
input [29:0] TX_BIT_CTRL_IN6,
input [10:0] TX_BIT_CTRL_IN_TRI
);
// define constants
localparam MODULE_NAME = "BITSLICE_CONTROL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [64:1] CTRL_CLK_REG = CTRL_CLK;
localparam [32:1] DIV_MODE_REG = DIV_MODE;
localparam [56:1] EN_CLK_TO_EXT_NORTH_REG = EN_CLK_TO_EXT_NORTH;
localparam [56:1] EN_CLK_TO_EXT_SOUTH_REG = EN_CLK_TO_EXT_SOUTH;
localparam [40:1] EN_DYN_ODLY_MODE_REG = EN_DYN_ODLY_MODE;
localparam [40:1] EN_OTHER_NCLK_REG = EN_OTHER_NCLK;
localparam [40:1] EN_OTHER_PCLK_REG = EN_OTHER_PCLK;
localparam [40:1] IDLY_VT_TRACK_REG = IDLY_VT_TRACK;
localparam [40:1] INV_RXCLK_REG = INV_RXCLK;
localparam [40:1] ODLY_VT_TRACK_REG = ODLY_VT_TRACK;
localparam [40:1] QDLY_VT_TRACK_REG = QDLY_VT_TRACK;
localparam [5:0] READ_IDLE_COUNT_REG = READ_IDLE_COUNT;
localparam [48:1] REFCLK_SRC_REG = REFCLK_SRC;
localparam [7:0] ROUNDING_FACTOR_REG = ROUNDING_FACTOR;
localparam [40:1] RXGATE_EXTEND_REG = RXGATE_EXTEND;
localparam [64:1] RX_CLK_PHASE_N_REG = RX_CLK_PHASE_N;
localparam [64:1] RX_CLK_PHASE_P_REG = RX_CLK_PHASE_P;
localparam [56:1] RX_GATING_REG = RX_GATING;
localparam [56:1] SELF_CALIBRATE_REG = SELF_CALIBRATE;
localparam [40:1] SERIAL_MODE_REG = SERIAL_MODE;
localparam [56:1] TX_GATING_REG = TX_GATING;
`endif
localparam [56:1] CONTROL_DLY_TEST_EN_REG = "DISABLE";
localparam [40:1] DC_ADJ_EN_REG = "FALSE";
localparam [12:0] DLY_RNK0_REG = 13'h0000;
localparam [12:0] DLY_RNK1_REG = 13'h0000;
localparam [12:0] DLY_RNK2_REG = 13'h0000;
localparam [12:0] DLY_RNK3_REG = 13'h0000;
localparam [2:0] FDLY_REG = 3'b000;
localparam [2:0] FDLY_RES_REG = 3'b000;
localparam [7:0] INCDEC_CRSE_REG = 8'h08;
localparam [9:0] MON_REG = 10'h000;
localparam [8:0] NQTR_REG = 9'h000;
localparam [8:0] PQTR_REG = 9'h000;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BITSLICE_CONTROL_dr.v"
`endif
wire BISC_START_OUT_out;
wire BISC_STOP_OUT_out;
wire CLK_TO_EXT_NORTH_out;
wire CLK_TO_EXT_SOUTH_out;
wire DLY_RDY_out;
wire DLY_TEST_OUT_out;
wire LOCAL_DIV_CLK_out;
wire MASTER_PD_OUT_out;
wire NCLK_NIBBLE_OUT_out;
wire PCLK_NIBBLE_OUT_out;
wire RIU_VALID_out;
wire VTC_RDY_out;
wire [15:0] RIU_RD_DATA_out;
wire [23:0] RX_BIT_CTRL_OUT0_out;
wire [23:0] RX_BIT_CTRL_OUT1_out;
wire [23:0] RX_BIT_CTRL_OUT2_out;
wire [23:0] RX_BIT_CTRL_OUT3_out;
wire [23:0] RX_BIT_CTRL_OUT4_out;
wire [23:0] RX_BIT_CTRL_OUT5_out;
wire [23:0] RX_BIT_CTRL_OUT6_out;
wire [26:0] TX_BIT_CTRL_OUT0_out;
wire [26:0] TX_BIT_CTRL_OUT1_out;
wire [26:0] TX_BIT_CTRL_OUT2_out;
wire [26:0] TX_BIT_CTRL_OUT3_out;
wire [26:0] TX_BIT_CTRL_OUT4_out;
wire [26:0] TX_BIT_CTRL_OUT5_out;
wire [26:0] TX_BIT_CTRL_OUT6_out;
wire [34:0] TX_BIT_CTRL_OUT_TRI_out;
wire [6:0] DYN_DCI_out;
wire BISC_START_OUT_delay;
wire BISC_STOP_OUT_delay;
wire CLK_TO_EXT_NORTH_delay;
wire CLK_TO_EXT_SOUTH_delay;
wire DLY_RDY_delay;
wire NCLK_NIBBLE_OUT_delay;
wire PCLK_NIBBLE_OUT_delay;
wire RIU_VALID_delay;
wire VTC_RDY_delay;
wire [15:0] RIU_RD_DATA_delay;
wire [23:0] RX_BIT_CTRL_OUT0_delay;
wire [23:0] RX_BIT_CTRL_OUT1_delay;
wire [23:0] RX_BIT_CTRL_OUT2_delay;
wire [23:0] RX_BIT_CTRL_OUT3_delay;
wire [23:0] RX_BIT_CTRL_OUT4_delay;
wire [23:0] RX_BIT_CTRL_OUT5_delay;
wire [23:0] RX_BIT_CTRL_OUT6_delay;
wire [26:0] TX_BIT_CTRL_OUT0_delay;
wire [26:0] TX_BIT_CTRL_OUT1_delay;
wire [26:0] TX_BIT_CTRL_OUT2_delay;
wire [26:0] TX_BIT_CTRL_OUT3_delay;
wire [26:0] TX_BIT_CTRL_OUT4_delay;
wire [26:0] TX_BIT_CTRL_OUT5_delay;
wire [26:0] TX_BIT_CTRL_OUT6_delay;
wire [34:0] TX_BIT_CTRL_OUT_TRI_delay;
wire [6:0] DYN_DCI_delay;
wire BISC_START_IN_in;
wire BISC_STOP_IN_in;
wire CLK_FROM_EXT_in;
wire CLK_STOP_in;
wire DLY_TEST_IN_in;
wire EN_VTC_in;
wire NCLK_NIBBLE_IN_in;
wire PCLK_NIBBLE_IN_in;
wire PLL_CLK_in;
wire REFCLK_in;
wire RIU_CLK_in;
wire RIU_NIBBLE_SEL_in;
wire RIU_WR_EN_in;
wire RST_in;
wire SCAN_INT_in;
wire [10:0] TX_BIT_CTRL_IN_TRI_in;
wire [15:0] RIU_WR_DATA_in;
wire [29:0] TX_BIT_CTRL_IN0_in;
wire [29:0] TX_BIT_CTRL_IN1_in;
wire [29:0] TX_BIT_CTRL_IN2_in;
wire [29:0] TX_BIT_CTRL_IN3_in;
wire [29:0] TX_BIT_CTRL_IN4_in;
wire [29:0] TX_BIT_CTRL_IN5_in;
wire [29:0] TX_BIT_CTRL_IN6_in;
wire [34:0] RX_BIT_CTRL_IN0_in;
wire [34:0] RX_BIT_CTRL_IN1_in;
wire [34:0] RX_BIT_CTRL_IN2_in;
wire [34:0] RX_BIT_CTRL_IN3_in;
wire [34:0] RX_BIT_CTRL_IN4_in;
wire [34:0] RX_BIT_CTRL_IN5_in;
wire [34:0] RX_BIT_CTRL_IN6_in;
wire [3:0] PHY_RDCS0_in;
wire [3:0] PHY_RDCS1_in;
wire [3:0] PHY_RDEN_in;
wire [3:0] PHY_WRCS0_in;
wire [3:0] PHY_WRCS1_in;
wire [3:0] TBYTE_IN_in;
wire [5:0] RIU_ADDR_in;
wire BISC_START_IN_delay;
wire BISC_STOP_IN_delay;
wire CLK_FROM_EXT_delay;
wire EN_VTC_delay;
wire NCLK_NIBBLE_IN_delay;
wire PCLK_NIBBLE_IN_delay;
wire PLL_CLK_delay;
wire REFCLK_delay;
wire RIU_CLK_delay;
wire RIU_NIBBLE_SEL_delay;
wire RIU_WR_EN_delay;
wire RST_delay;
wire [10:0] TX_BIT_CTRL_IN_TRI_delay;
wire [15:0] RIU_WR_DATA_delay;
wire [29:0] TX_BIT_CTRL_IN0_delay;
wire [29:0] TX_BIT_CTRL_IN1_delay;
wire [29:0] TX_BIT_CTRL_IN2_delay;
wire [29:0] TX_BIT_CTRL_IN3_delay;
wire [29:0] TX_BIT_CTRL_IN4_delay;
wire [29:0] TX_BIT_CTRL_IN5_delay;
wire [29:0] TX_BIT_CTRL_IN6_delay;
wire [34:0] RX_BIT_CTRL_IN0_delay;
wire [34:0] RX_BIT_CTRL_IN1_delay;
wire [34:0] RX_BIT_CTRL_IN2_delay;
wire [34:0] RX_BIT_CTRL_IN3_delay;
wire [34:0] RX_BIT_CTRL_IN4_delay;
wire [34:0] RX_BIT_CTRL_IN5_delay;
wire [34:0] RX_BIT_CTRL_IN6_delay;
wire [3:0] PHY_RDCS0_delay;
wire [3:0] PHY_RDCS1_delay;
wire [3:0] PHY_RDEN_delay;
wire [3:0] PHY_WRCS0_delay;
wire [3:0] PHY_WRCS1_delay;
wire [3:0] TBYTE_IN_delay;
wire [5:0] RIU_ADDR_delay;
assign #(out_delay) BISC_START_OUT = BISC_START_OUT_delay;
assign #(out_delay) BISC_STOP_OUT = BISC_STOP_OUT_delay;
assign #(out_delay) CLK_TO_EXT_NORTH = CLK_TO_EXT_NORTH_delay;
assign #(out_delay) CLK_TO_EXT_SOUTH = CLK_TO_EXT_SOUTH_delay;
assign #(out_delay) DLY_RDY = DLY_RDY_delay;
assign #(out_delay) DYN_DCI = DYN_DCI_delay;
assign #(out_delay) NCLK_NIBBLE_OUT = NCLK_NIBBLE_OUT_delay;
assign #(out_delay) PCLK_NIBBLE_OUT = PCLK_NIBBLE_OUT_delay;
assign #(out_delay) RIU_RD_DATA = RIU_RD_DATA_delay;
assign #(out_delay) RIU_VALID = RIU_VALID_delay;
assign #(out_delay) RX_BIT_CTRL_OUT0 = RX_BIT_CTRL_OUT0_delay;
assign #(out_delay) RX_BIT_CTRL_OUT1 = RX_BIT_CTRL_OUT1_delay;
assign #(out_delay) RX_BIT_CTRL_OUT2 = RX_BIT_CTRL_OUT2_delay;
assign #(out_delay) RX_BIT_CTRL_OUT3 = RX_BIT_CTRL_OUT3_delay;
assign #(out_delay) RX_BIT_CTRL_OUT4 = RX_BIT_CTRL_OUT4_delay;
assign #(out_delay) RX_BIT_CTRL_OUT5 = RX_BIT_CTRL_OUT5_delay;
assign #(out_delay) RX_BIT_CTRL_OUT6 = RX_BIT_CTRL_OUT6_delay;
assign #(out_delay) TX_BIT_CTRL_OUT0 = TX_BIT_CTRL_OUT0_delay;
assign #(out_delay) TX_BIT_CTRL_OUT1 = TX_BIT_CTRL_OUT1_delay;
assign #(out_delay) TX_BIT_CTRL_OUT2 = TX_BIT_CTRL_OUT2_delay;
assign #(out_delay) TX_BIT_CTRL_OUT3 = TX_BIT_CTRL_OUT3_delay;
assign #(out_delay) TX_BIT_CTRL_OUT4 = TX_BIT_CTRL_OUT4_delay;
assign #(out_delay) TX_BIT_CTRL_OUT5 = TX_BIT_CTRL_OUT5_delay;
assign #(out_delay) TX_BIT_CTRL_OUT6 = TX_BIT_CTRL_OUT6_delay;
assign #(out_delay) TX_BIT_CTRL_OUT_TRI = TX_BIT_CTRL_OUT_TRI_delay;
assign #(out_delay) VTC_RDY = VTC_RDY_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) RIU_CLK_delay = RIU_CLK;
assign #(in_delay) CLK_FROM_EXT_delay = CLK_FROM_EXT;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) PHY_RDCS0_delay = PHY_RDCS0;
assign #(in_delay) PHY_RDCS1_delay = PHY_RDCS1;
assign #(in_delay) PHY_RDEN_delay = PHY_RDEN;
assign #(in_delay) PHY_WRCS0_delay = PHY_WRCS0;
assign #(in_delay) PHY_WRCS1_delay = PHY_WRCS1;
assign #(in_delay) PLL_CLK_delay = PLL_CLK;
assign #(in_delay) RIU_ADDR_delay = RIU_ADDR;
assign #(in_delay) RIU_NIBBLE_SEL_delay = RIU_NIBBLE_SEL;
assign #(in_delay) RIU_WR_DATA_delay = RIU_WR_DATA;
assign #(in_delay) RIU_WR_EN_delay = RIU_WR_EN;
assign #(in_delay) RST_delay = RST;
assign #(in_delay) RX_BIT_CTRL_IN0_delay = RX_BIT_CTRL_IN0;
assign #(in_delay) RX_BIT_CTRL_IN1_delay = RX_BIT_CTRL_IN1;
assign #(in_delay) RX_BIT_CTRL_IN2_delay = RX_BIT_CTRL_IN2;
assign #(in_delay) RX_BIT_CTRL_IN3_delay = RX_BIT_CTRL_IN3;
assign #(in_delay) RX_BIT_CTRL_IN4_delay = RX_BIT_CTRL_IN4;
assign #(in_delay) RX_BIT_CTRL_IN5_delay = RX_BIT_CTRL_IN5;
assign #(in_delay) RX_BIT_CTRL_IN6_delay = RX_BIT_CTRL_IN6;
assign #(in_delay) TBYTE_IN_delay = TBYTE_IN;
assign #(in_delay) TX_BIT_CTRL_IN0_delay = TX_BIT_CTRL_IN0;
assign #(in_delay) TX_BIT_CTRL_IN1_delay = TX_BIT_CTRL_IN1;
assign #(in_delay) TX_BIT_CTRL_IN2_delay = TX_BIT_CTRL_IN2;
assign #(in_delay) TX_BIT_CTRL_IN3_delay = TX_BIT_CTRL_IN3;
assign #(in_delay) TX_BIT_CTRL_IN4_delay = TX_BIT_CTRL_IN4;
assign #(in_delay) TX_BIT_CTRL_IN5_delay = TX_BIT_CTRL_IN5;
assign #(in_delay) TX_BIT_CTRL_IN6_delay = TX_BIT_CTRL_IN6;
assign #(in_delay) TX_BIT_CTRL_IN_TRI_delay = TX_BIT_CTRL_IN_TRI;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) REFCLK_delay = REFCLK;
assign #(in_delay) BISC_START_IN_delay = BISC_START_IN;
assign #(in_delay) BISC_STOP_IN_delay = BISC_STOP_IN;
assign #(in_delay) NCLK_NIBBLE_IN_delay = NCLK_NIBBLE_IN;
assign #(in_delay) PCLK_NIBBLE_IN_delay = PCLK_NIBBLE_IN;
assign BISC_START_OUT_delay = BISC_START_OUT_out;
assign BISC_STOP_OUT_delay = BISC_STOP_OUT_out;
assign CLK_TO_EXT_NORTH_delay = CLK_TO_EXT_NORTH_out;
assign CLK_TO_EXT_SOUTH_delay = CLK_TO_EXT_SOUTH_out;
assign DLY_RDY_delay = DLY_RDY_out;
assign DYN_DCI_delay = DYN_DCI_out;
assign NCLK_NIBBLE_OUT_delay = NCLK_NIBBLE_OUT_out;
assign PCLK_NIBBLE_OUT_delay = PCLK_NIBBLE_OUT_out;
assign RIU_RD_DATA_delay = RIU_RD_DATA_out;
assign RIU_VALID_delay = RIU_VALID_out;
assign RX_BIT_CTRL_OUT0_delay = RX_BIT_CTRL_OUT0_out;
assign RX_BIT_CTRL_OUT1_delay = RX_BIT_CTRL_OUT1_out;
assign RX_BIT_CTRL_OUT2_delay = RX_BIT_CTRL_OUT2_out;
assign RX_BIT_CTRL_OUT3_delay = RX_BIT_CTRL_OUT3_out;
assign RX_BIT_CTRL_OUT4_delay = RX_BIT_CTRL_OUT4_out;
assign RX_BIT_CTRL_OUT5_delay = RX_BIT_CTRL_OUT5_out;
assign RX_BIT_CTRL_OUT6_delay = RX_BIT_CTRL_OUT6_out;
assign TX_BIT_CTRL_OUT0_delay = TX_BIT_CTRL_OUT0_out;
assign TX_BIT_CTRL_OUT1_delay = TX_BIT_CTRL_OUT1_out;
assign TX_BIT_CTRL_OUT2_delay = TX_BIT_CTRL_OUT2_out;
assign TX_BIT_CTRL_OUT3_delay = TX_BIT_CTRL_OUT3_out;
assign TX_BIT_CTRL_OUT4_delay = TX_BIT_CTRL_OUT4_out;
assign TX_BIT_CTRL_OUT5_delay = TX_BIT_CTRL_OUT5_out;
assign TX_BIT_CTRL_OUT6_delay = TX_BIT_CTRL_OUT6_out;
assign TX_BIT_CTRL_OUT_TRI_delay = TX_BIT_CTRL_OUT_TRI_out;
assign VTC_RDY_delay = VTC_RDY_out;
assign BISC_START_IN_in = BISC_START_IN_delay;
assign BISC_STOP_IN_in = BISC_STOP_IN_delay;
assign CLK_FROM_EXT_in = CLK_FROM_EXT_delay;
assign EN_VTC_in = EN_VTC_delay;
assign NCLK_NIBBLE_IN_in = NCLK_NIBBLE_IN_delay;
assign PCLK_NIBBLE_IN_in = PCLK_NIBBLE_IN_delay;
assign PHY_RDCS0_in = PHY_RDCS0_delay;
assign PHY_RDCS1_in = PHY_RDCS1_delay;
assign PHY_RDEN_in = PHY_RDEN_delay;
assign PHY_WRCS0_in = PHY_WRCS0_delay;
assign PHY_WRCS1_in = PHY_WRCS1_delay;
assign PLL_CLK_in = PLL_CLK_delay;
assign REFCLK_in = REFCLK_delay;
assign RIU_ADDR_in = RIU_ADDR_delay;
assign RIU_CLK_in = RIU_CLK_delay;
assign RIU_NIBBLE_SEL_in = RIU_NIBBLE_SEL_delay;
assign RIU_WR_DATA_in = RIU_WR_DATA_delay;
assign RIU_WR_EN_in = RIU_WR_EN_delay;
assign RST_in = RST_delay;
assign RX_BIT_CTRL_IN0_in = RX_BIT_CTRL_IN0_delay;
assign RX_BIT_CTRL_IN1_in = RX_BIT_CTRL_IN1_delay;
assign RX_BIT_CTRL_IN2_in = RX_BIT_CTRL_IN2_delay;
assign RX_BIT_CTRL_IN3_in = RX_BIT_CTRL_IN3_delay;
assign RX_BIT_CTRL_IN4_in = RX_BIT_CTRL_IN4_delay;
assign RX_BIT_CTRL_IN5_in = RX_BIT_CTRL_IN5_delay;
assign RX_BIT_CTRL_IN6_in = RX_BIT_CTRL_IN6_delay;
assign TBYTE_IN_in = TBYTE_IN_delay;
assign TX_BIT_CTRL_IN0_in = TX_BIT_CTRL_IN0_delay;
assign TX_BIT_CTRL_IN1_in = TX_BIT_CTRL_IN1_delay;
assign TX_BIT_CTRL_IN2_in = TX_BIT_CTRL_IN2_delay;
assign TX_BIT_CTRL_IN3_in = TX_BIT_CTRL_IN3_delay;
assign TX_BIT_CTRL_IN4_in = TX_BIT_CTRL_IN4_delay;
assign TX_BIT_CTRL_IN5_in = TX_BIT_CTRL_IN5_delay;
assign TX_BIT_CTRL_IN6_in = TX_BIT_CTRL_IN6_delay;
assign TX_BIT_CTRL_IN_TRI_in = TX_BIT_CTRL_IN_TRI_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((CTRL_CLK_REG != "EXTERNAL") &&
(CTRL_CLK_REG != "INTERNAL")) begin
$display("Attribute Syntax Error : The attribute CTRL_CLK on %s instance %m is set to %s. Legal values for this attribute are EXTERNAL or INTERNAL.", MODULE_NAME, CTRL_CLK_REG);
attr_err = 1'b1;
end
if ((DIV_MODE_REG != "DIV2") &&
(DIV_MODE_REG != "DIV4")) begin
$display("Attribute Syntax Error : The attribute DIV_MODE on %s instance %m is set to %s. Legal values for this attribute are DIV2 or DIV4.", MODULE_NAME, DIV_MODE_REG);
attr_err = 1'b1;
end
if ((EN_CLK_TO_EXT_NORTH_REG != "DISABLE") &&
(EN_CLK_TO_EXT_NORTH_REG != "ENABLE")) begin
$display("Attribute Syntax Error : The attribute EN_CLK_TO_EXT_NORTH on %s instance %m is set to %s. Legal values for this attribute are DISABLE or ENABLE.", MODULE_NAME, EN_CLK_TO_EXT_NORTH_REG);
attr_err = 1'b1;
end
if ((EN_CLK_TO_EXT_SOUTH_REG != "DISABLE") &&
(EN_CLK_TO_EXT_SOUTH_REG != "ENABLE")) begin
$display("Attribute Syntax Error : The attribute EN_CLK_TO_EXT_SOUTH on %s instance %m is set to %s. Legal values for this attribute are DISABLE or ENABLE.", MODULE_NAME, EN_CLK_TO_EXT_SOUTH_REG);
attr_err = 1'b1;
end
if ((EN_DYN_ODLY_MODE_REG != "FALSE") &&
(EN_DYN_ODLY_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_DYN_ODLY_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_DYN_ODLY_MODE_REG);
attr_err = 1'b1;
end
if ((EN_OTHER_NCLK_REG != "FALSE") &&
(EN_OTHER_NCLK_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_OTHER_NCLK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_OTHER_NCLK_REG);
attr_err = 1'b1;
end
if ((EN_OTHER_PCLK_REG != "FALSE") &&
(EN_OTHER_PCLK_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_OTHER_PCLK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_OTHER_PCLK_REG);
attr_err = 1'b1;
end
if ((IDLY_VT_TRACK_REG != "TRUE") &&
(IDLY_VT_TRACK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute IDLY_VT_TRACK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IDLY_VT_TRACK_REG);
attr_err = 1'b1;
end
if ((INV_RXCLK_REG != "FALSE") &&
(INV_RXCLK_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute INV_RXCLK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, INV_RXCLK_REG);
attr_err = 1'b1;
end
if ((ODLY_VT_TRACK_REG != "TRUE") &&
(ODLY_VT_TRACK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute ODLY_VT_TRACK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ODLY_VT_TRACK_REG);
attr_err = 1'b1;
end
if ((QDLY_VT_TRACK_REG != "TRUE") &&
(QDLY_VT_TRACK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute QDLY_VT_TRACK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, QDLY_VT_TRACK_REG);
attr_err = 1'b1;
end
if ((REFCLK_SRC_REG != "PLLCLK") &&
(REFCLK_SRC_REG != "REFCLK")) begin
$display("Attribute Syntax Error : The attribute REFCLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PLLCLK or REFCLK.", MODULE_NAME, REFCLK_SRC_REG);
attr_err = 1'b1;
end
if ((ROUNDING_FACTOR_REG != 16) &&
(ROUNDING_FACTOR_REG != 2) &&
(ROUNDING_FACTOR_REG != 4) &&
(ROUNDING_FACTOR_REG != 8) &&
(ROUNDING_FACTOR_REG != 32) &&
(ROUNDING_FACTOR_REG != 64) &&
(ROUNDING_FACTOR_REG != 128)) begin
$display("Attribute Syntax Error : The attribute ROUNDING_FACTOR on %s instance %m is set to %d. Legal values for this attribute are 2 to 128.", MODULE_NAME, ROUNDING_FACTOR_REG, 16);
attr_err = 1'b1;
end
if ((RXGATE_EXTEND_REG != "FALSE") &&
(RXGATE_EXTEND_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXGATE_EXTEND on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXGATE_EXTEND_REG);
attr_err = 1'b1;
end
if ((RX_CLK_PHASE_N_REG != "SHIFT_0") &&
(RX_CLK_PHASE_N_REG != "SHIFT_90")) begin
$display("Attribute Syntax Error : The attribute RX_CLK_PHASE_N on %s instance %m is set to %s. Legal values for this attribute are SHIFT_0 or SHIFT_90.", MODULE_NAME, RX_CLK_PHASE_N_REG);
attr_err = 1'b1;
end
if ((RX_CLK_PHASE_P_REG != "SHIFT_0") &&
(RX_CLK_PHASE_P_REG != "SHIFT_90")) begin
$display("Attribute Syntax Error : The attribute RX_CLK_PHASE_P on %s instance %m is set to %s. Legal values for this attribute are SHIFT_0 or SHIFT_90.", MODULE_NAME, RX_CLK_PHASE_P_REG);
attr_err = 1'b1;
end
if ((RX_GATING_REG != "DISABLE") &&
(RX_GATING_REG != "ENABLE")) begin
$display("Attribute Syntax Error : The attribute RX_GATING on %s instance %m is set to %s. Legal values for this attribute are DISABLE or ENABLE.", MODULE_NAME, RX_GATING_REG);
attr_err = 1'b1;
end
if ((SELF_CALIBRATE_REG != "ENABLE") &&
(SELF_CALIBRATE_REG != "DISABLE")) begin
$display("Attribute Syntax Error : The attribute SELF_CALIBRATE on %s instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", MODULE_NAME, SELF_CALIBRATE_REG);
attr_err = 1'b1;
end
if ((SERIAL_MODE_REG != "FALSE") &&
(SERIAL_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SERIAL_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SERIAL_MODE_REG);
attr_err = 1'b1;
end
if ((TX_GATING_REG != "DISABLE") &&
(TX_GATING_REG != "ENABLE")) begin
$display("Attribute Syntax Error : The attribute TX_GATING on %s instance %m is set to %s. Legal values for this attribute are DISABLE or ENABLE.", MODULE_NAME, TX_GATING_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CLK_STOP_in = 1'b1; // tie off
assign DLY_TEST_IN_in = 1'b0; // tie off
assign SCAN_INT_in = 1'b1; // tie off
SIP_BITSLICE_CONTROL SIP_BITSLICE_CONTROL_INST (
.CONTROL_DLY_TEST_EN (CONTROL_DLY_TEST_EN_REG),
.CTRL_CLK (CTRL_CLK_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DIV_MODE (DIV_MODE_REG),
.DLY_RNK0 (DLY_RNK0_REG),
.DLY_RNK1 (DLY_RNK1_REG),
.DLY_RNK2 (DLY_RNK2_REG),
.DLY_RNK3 (DLY_RNK3_REG),
.EN_CLK_TO_EXT_NORTH (EN_CLK_TO_EXT_NORTH_REG),
.EN_CLK_TO_EXT_SOUTH (EN_CLK_TO_EXT_SOUTH_REG),
.EN_DYN_ODLY_MODE (EN_DYN_ODLY_MODE_REG),
.EN_OTHER_NCLK (EN_OTHER_NCLK_REG),
.EN_OTHER_PCLK (EN_OTHER_PCLK_REG),
.FDLY (FDLY_REG),
.FDLY_RES (FDLY_RES_REG),
.IDLY_VT_TRACK (IDLY_VT_TRACK_REG),
.INCDEC_CRSE (INCDEC_CRSE_REG),
.INV_RXCLK (INV_RXCLK_REG),
.MON (MON_REG),
.NQTR (NQTR_REG),
.ODLY_VT_TRACK (ODLY_VT_TRACK_REG),
.PQTR (PQTR_REG),
.QDLY_VT_TRACK (QDLY_VT_TRACK_REG),
.READ_IDLE_COUNT (READ_IDLE_COUNT_REG),
.REFCLK_SRC (REFCLK_SRC_REG),
.ROUNDING_FACTOR (ROUNDING_FACTOR_REG),
.RXGATE_EXTEND (RXGATE_EXTEND_REG),
.RX_CLK_PHASE_N (RX_CLK_PHASE_N_REG),
.RX_CLK_PHASE_P (RX_CLK_PHASE_P_REG),
.RX_GATING (RX_GATING_REG),
.SELF_CALIBRATE (SELF_CALIBRATE_REG),
.SERIAL_MODE (SERIAL_MODE_REG),
.TX_GATING (TX_GATING_REG),
.BISC_START_OUT (BISC_START_OUT_out),
.BISC_STOP_OUT (BISC_STOP_OUT_out),
.CLK_TO_EXT_NORTH (CLK_TO_EXT_NORTH_out),
.CLK_TO_EXT_SOUTH (CLK_TO_EXT_SOUTH_out),
.DLY_RDY (DLY_RDY_out),
.DLY_TEST_OUT (DLY_TEST_OUT_out),
.DYN_DCI (DYN_DCI_out),
.LOCAL_DIV_CLK (LOCAL_DIV_CLK_out),
.MASTER_PD_OUT (MASTER_PD_OUT_out),
.NCLK_NIBBLE_OUT (NCLK_NIBBLE_OUT_out),
.PCLK_NIBBLE_OUT (PCLK_NIBBLE_OUT_out),
.RIU_RD_DATA (RIU_RD_DATA_out),
.RIU_VALID (RIU_VALID_out),
.RX_BIT_CTRL_OUT0 (RX_BIT_CTRL_OUT0_out),
.RX_BIT_CTRL_OUT1 (RX_BIT_CTRL_OUT1_out),
.RX_BIT_CTRL_OUT2 (RX_BIT_CTRL_OUT2_out),
.RX_BIT_CTRL_OUT3 (RX_BIT_CTRL_OUT3_out),
.RX_BIT_CTRL_OUT4 (RX_BIT_CTRL_OUT4_out),
.RX_BIT_CTRL_OUT5 (RX_BIT_CTRL_OUT5_out),
.RX_BIT_CTRL_OUT6 (RX_BIT_CTRL_OUT6_out),
.TX_BIT_CTRL_OUT0 (TX_BIT_CTRL_OUT0_out),
.TX_BIT_CTRL_OUT1 (TX_BIT_CTRL_OUT1_out),
.TX_BIT_CTRL_OUT2 (TX_BIT_CTRL_OUT2_out),
.TX_BIT_CTRL_OUT3 (TX_BIT_CTRL_OUT3_out),
.TX_BIT_CTRL_OUT4 (TX_BIT_CTRL_OUT4_out),
.TX_BIT_CTRL_OUT5 (TX_BIT_CTRL_OUT5_out),
.TX_BIT_CTRL_OUT6 (TX_BIT_CTRL_OUT6_out),
.TX_BIT_CTRL_OUT_TRI (TX_BIT_CTRL_OUT_TRI_out),
.VTC_RDY (VTC_RDY_out),
.BISC_START_IN (BISC_START_IN_in),
.BISC_STOP_IN (BISC_STOP_IN_in),
.CLK_FROM_EXT (CLK_FROM_EXT_in),
.CLK_STOP (CLK_STOP_in),
.DLY_TEST_IN (DLY_TEST_IN_in),
.EN_VTC (EN_VTC_in),
.NCLK_NIBBLE_IN (NCLK_NIBBLE_IN_in),
.PCLK_NIBBLE_IN (PCLK_NIBBLE_IN_in),
.PHY_RDCS0 (PHY_RDCS0_in),
.PHY_RDCS1 (PHY_RDCS1_in),
.PHY_RDEN (PHY_RDEN_in),
.PHY_WRCS0 (PHY_WRCS0_in),
.PHY_WRCS1 (PHY_WRCS1_in),
.PLL_CLK (PLL_CLK_in),
.REFCLK (REFCLK_in),
.RIU_ADDR (RIU_ADDR_in),
.RIU_CLK (RIU_CLK_in),
.RIU_NIBBLE_SEL (RIU_NIBBLE_SEL_in),
.RIU_WR_DATA (RIU_WR_DATA_in),
.RIU_WR_EN (RIU_WR_EN_in),
.RST (RST_in),
.RX_BIT_CTRL_IN0 (RX_BIT_CTRL_IN0_in),
.RX_BIT_CTRL_IN1 (RX_BIT_CTRL_IN1_in),
.RX_BIT_CTRL_IN2 (RX_BIT_CTRL_IN2_in),
.RX_BIT_CTRL_IN3 (RX_BIT_CTRL_IN3_in),
.RX_BIT_CTRL_IN4 (RX_BIT_CTRL_IN4_in),
.RX_BIT_CTRL_IN5 (RX_BIT_CTRL_IN5_in),
.RX_BIT_CTRL_IN6 (RX_BIT_CTRL_IN6_in),
.SCAN_INT (SCAN_INT_in),
.TBYTE_IN (TBYTE_IN_in),
.TX_BIT_CTRL_IN0 (TX_BIT_CTRL_IN0_in),
.TX_BIT_CTRL_IN1 (TX_BIT_CTRL_IN1_in),
.TX_BIT_CTRL_IN2 (TX_BIT_CTRL_IN2_in),
.TX_BIT_CTRL_IN3 (TX_BIT_CTRL_IN3_in),
.TX_BIT_CTRL_IN4 (TX_BIT_CTRL_IN4_in),
.TX_BIT_CTRL_IN5 (TX_BIT_CTRL_IN5_in),
.TX_BIT_CTRL_IN6 (TX_BIT_CTRL_IN6_in),
.TX_BIT_CTRL_IN_TRI (TX_BIT_CTRL_IN_TRI_in),
.GSR (glblGSR)
);
specify
(CLK_FROM_EXT *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(CLK_FROM_EXT => CLK_TO_EXT_NORTH) = (0:0:0, 0:0:0);
(CLK_FROM_EXT => CLK_TO_EXT_SOUTH) = (0:0:0, 0:0:0);
(CLK_FROM_EXT => NCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(CLK_FROM_EXT => PCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(NCLK_NIBBLE_IN *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(PCLK_NIBBLE_IN *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(PLL_CLK *> DYN_DCI) = (0:0:0, 0:0:0);
(PLL_CLK *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT0) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT1) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT2) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT3) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT4) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT5) = (0:0:0, 0:0:0);
(PLL_CLK *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT0) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT1) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT2) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT3) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT4) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT5) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(PLL_CLK *> TX_BIT_CTRL_OUT_TRI) = (0:0:0, 0:0:0);
(PLL_CLK => CLK_TO_EXT_NORTH) = (0:0:0, 0:0:0);
(PLL_CLK => CLK_TO_EXT_SOUTH) = (0:0:0, 0:0:0);
(PLL_CLK => DLY_RDY) = (0:0:0, 0:0:0);
(PLL_CLK => NCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(PLL_CLK => PCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(PLL_CLK => RIU_VALID) = (0:0:0, 0:0:0);
(PLL_CLK => VTC_RDY) = (0:0:0, 0:0:0);
(RIU_CLK *> DYN_DCI) = (0:0:0, 0:0:0);
(RIU_CLK *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT0) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT1) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT2) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT3) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT4) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT5) = (0:0:0, 0:0:0);
(RIU_CLK *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT0) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT1) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT2) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT3) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT4) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT5) = (0:0:0, 0:0:0);
(RIU_CLK *> TX_BIT_CTRL_OUT_TRI) = (0:0:0, 0:0:0);
(RIU_CLK => CLK_TO_EXT_NORTH) = (0:0:0, 0:0:0);
(RIU_CLK => CLK_TO_EXT_SOUTH) = (0:0:0, 0:0:0);
(RIU_CLK => DLY_RDY) = (0:0:0, 0:0:0);
(RIU_CLK => NCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(RIU_CLK => PCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(RIU_CLK => RIU_VALID) = (0:0:0, 0:0:0);
(RIU_CLK => VTC_RDY) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> CLK_TO_EXT_NORTH) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> CLK_TO_EXT_SOUTH) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> NCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> PCLK_NIBBLE_OUT) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN0 *> RX_BIT_CTRL_OUT6) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN1 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN2 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN3 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN4 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN5 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN6 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN0 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN1 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN2 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN3 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN4 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN5 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN6 *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN_TRI *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(negedge RST *> (DYN_DCI +: 0)) = (0:0:0, 0:0:0);
(negedge RST *> (RIU_RD_DATA +: 0)) = (0:0:0, 0:0:0);
(negedge RST => (CLK_TO_EXT_NORTH +: 0)) = (0:0:0, 0:0:0);
(negedge RST => (CLK_TO_EXT_SOUTH +: 0)) = (0:0:0, 0:0:0);
(negedge RST => (DLY_RDY +: 0)) = (0:0:0, 0:0:0);
(negedge RST => (RIU_VALID +: 0)) = (0:0:0, 0:0:0);
(negedge RST => (VTC_RDY +: 0)) = (0:0:0, 0:0:0);
(posedge RST *> (RIU_RD_DATA +: 0)) = (0:0:0, 0:0:0);
(posedge RST => (CLK_TO_EXT_NORTH +: 0)) = (0:0:0, 0:0:0);
(posedge RST => (CLK_TO_EXT_SOUTH +: 0)) = (0:0:0, 0:0:0);
(posedge RST => (RIU_VALID +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK_FROM_EXT, 0:0:0, notifier);
$period (negedge PLL_CLK, 0:0:0, notifier);
$period (negedge RIU_CLK, 0:0:0, notifier);
$period (posedge CLK_FROM_EXT, 0:0:0, notifier);
$period (posedge PLL_CLK, 0:0:0, notifier);
$period (posedge RIU_CLK, 0:0:0, notifier);
$recrem ( negedge CLK_FROM_EXT, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$recrem ( negedge CLK_FROM_EXT, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$recrem ( negedge PLL_CLK, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$recrem ( negedge PLL_CLK, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$recrem ( negedge RST, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_FROM_EXT_delay);
$recrem ( negedge RST, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_FROM_EXT_delay);
$recrem ( negedge RX_BIT_CTRL_IN0, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, CLK_FROM_EXT_delay);
$recrem ( negedge RX_BIT_CTRL_IN0, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, PLL_CLK_delay);
$recrem ( negedge RX_BIT_CTRL_IN0, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, CLK_FROM_EXT_delay);
$recrem ( negedge RX_BIT_CTRL_IN0, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, PLL_CLK_delay);
$recrem ( posedge CLK_FROM_EXT, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$recrem ( posedge CLK_FROM_EXT, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$recrem ( posedge PLL_CLK, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$recrem ( posedge PLL_CLK, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$recrem ( posedge RST, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_FROM_EXT_delay);
$recrem ( posedge RST, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_FROM_EXT_delay);
$recrem ( posedge RX_BIT_CTRL_IN0, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, CLK_FROM_EXT_delay);
$recrem ( posedge RX_BIT_CTRL_IN0, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, PLL_CLK_delay);
$recrem ( posedge RX_BIT_CTRL_IN0, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, CLK_FROM_EXT_delay);
$recrem ( posedge RX_BIT_CTRL_IN0, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN0_delay, PLL_CLK_delay);
$setuphold (negedge CLK_FROM_EXT, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$setuphold (negedge CLK_FROM_EXT, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$setuphold (negedge PLL_CLK, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$setuphold (negedge PLL_CLK, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$setuphold (posedge CLK_FROM_EXT, negedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$setuphold (posedge CLK_FROM_EXT, posedge PLL_CLK, 0:0:0, 0:0:0, notifier,,, CLK_FROM_EXT_delay, PLL_CLK_delay);
$setuphold (posedge PLL_CLK, negedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$setuphold (posedge PLL_CLK, negedge EN_VTC, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, EN_VTC_delay);
$setuphold (posedge PLL_CLK, negedge PHY_RDCS0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDCS0_delay);
$setuphold (posedge PLL_CLK, negedge PHY_RDCS1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDCS1_delay);
$setuphold (posedge PLL_CLK, negedge PHY_RDEN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDEN_delay);
$setuphold (posedge PLL_CLK, negedge PHY_WRCS0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_WRCS0_delay);
$setuphold (posedge PLL_CLK, negedge PHY_WRCS1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_WRCS1_delay);
$setuphold (posedge PLL_CLK, negedge RIU_ADDR, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_ADDR_delay);
$setuphold (posedge PLL_CLK, negedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_NIBBLE_SEL_delay);
$setuphold (posedge PLL_CLK, negedge RIU_WR_DATA, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_WR_DATA_delay);
$setuphold (posedge PLL_CLK, negedge RIU_WR_EN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_WR_EN_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN0_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN1_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN2_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN3_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN4_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN5_delay);
$setuphold (posedge PLL_CLK, negedge RX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN6_delay);
$setuphold (posedge PLL_CLK, negedge TBYTE_IN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TBYTE_IN_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN0_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN1_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN2_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN3_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN4_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN5_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN6_delay);
$setuphold (posedge PLL_CLK, negedge TX_BIT_CTRL_IN_TRI, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN_TRI_delay);
$setuphold (posedge PLL_CLK, posedge CLK_FROM_EXT, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, CLK_FROM_EXT_delay);
$setuphold (posedge PLL_CLK, posedge EN_VTC, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, EN_VTC_delay);
$setuphold (posedge PLL_CLK, posedge PHY_RDCS0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDCS0_delay);
$setuphold (posedge PLL_CLK, posedge PHY_RDCS1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDCS1_delay);
$setuphold (posedge PLL_CLK, posedge PHY_RDEN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_RDEN_delay);
$setuphold (posedge PLL_CLK, posedge PHY_WRCS0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_WRCS0_delay);
$setuphold (posedge PLL_CLK, posedge PHY_WRCS1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, PHY_WRCS1_delay);
$setuphold (posedge PLL_CLK, posedge RIU_ADDR, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_ADDR_delay);
$setuphold (posedge PLL_CLK, posedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_NIBBLE_SEL_delay);
$setuphold (posedge PLL_CLK, posedge RIU_WR_DATA, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_WR_DATA_delay);
$setuphold (posedge PLL_CLK, posedge RIU_WR_EN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RIU_WR_EN_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN0_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN1_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN2_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN3_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN4_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN5_delay);
$setuphold (posedge PLL_CLK, posedge RX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, RX_BIT_CTRL_IN6_delay);
$setuphold (posedge PLL_CLK, posedge TBYTE_IN, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TBYTE_IN_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN0_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN1_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN2_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN3_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN4_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN5_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN6_delay);
$setuphold (posedge PLL_CLK, posedge TX_BIT_CTRL_IN_TRI, 0:0:0, 0:0:0, notifier,,, PLL_CLK_delay, TX_BIT_CTRL_IN_TRI_delay);
$setuphold (posedge RIU_CLK, negedge EN_VTC, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, EN_VTC_delay);
$setuphold (posedge RIU_CLK, negedge RIU_ADDR, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_ADDR_delay);
$setuphold (posedge RIU_CLK, negedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_NIBBLE_SEL_delay);
$setuphold (posedge RIU_CLK, negedge RIU_WR_DATA, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_WR_DATA_delay);
$setuphold (posedge RIU_CLK, negedge RIU_WR_EN, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_WR_EN_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN0_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN1_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN2_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN3_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN4_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN5_delay);
$setuphold (posedge RIU_CLK, negedge RX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN6_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN0_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN1_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN2_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN3_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN4_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN5_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN6_delay);
$setuphold (posedge RIU_CLK, negedge TX_BIT_CTRL_IN_TRI, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN_TRI_delay);
$setuphold (posedge RIU_CLK, posedge EN_VTC, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, EN_VTC_delay);
$setuphold (posedge RIU_CLK, posedge RIU_ADDR, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_ADDR_delay);
$setuphold (posedge RIU_CLK, posedge RIU_NIBBLE_SEL, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_NIBBLE_SEL_delay);
$setuphold (posedge RIU_CLK, posedge RIU_WR_DATA, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_WR_DATA_delay);
$setuphold (posedge RIU_CLK, posedge RIU_WR_EN, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RIU_WR_EN_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN0_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN1_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN2_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN3_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN4_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN5_delay);
$setuphold (posedge RIU_CLK, posedge RX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, RX_BIT_CTRL_IN6_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN0, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN0_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN1, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN1_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN2, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN2_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN3, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN3_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN4, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN4_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN5, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN5_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN6, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN6_delay);
$setuphold (posedge RIU_CLK, posedge TX_BIT_CTRL_IN_TRI, 0:0:0, 0:0:0, notifier,,, RIU_CLK_delay, TX_BIT_CTRL_IN_TRI_delay);
$width (negedge CLK_FROM_EXT, 0:0:0, 0, notifier);
$width (negedge PLL_CLK, 0:0:0, 0, notifier);
$width (negedge RIU_CLK, 0:0:0, 0, notifier);
$width (posedge CLK_FROM_EXT, 0:0:0, 0, notifier);
$width (posedge PLL_CLK, 0:0:0, 0, notifier);
$width (posedge RIU_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BSCANE2.v 0000664 0000000 0000000 00000010102 12327044266 0022431 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Boundary Scan Logic Control Circuit for VIRTEX7
// /___/ /\ Filename : BSCANE2.v
// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010
// \___\/\___\
//
// Revision:
// 02/08/10 - Initial version.
// 06/10/11 - CR 613789.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 11/13/13 - Update default value of JTAG_CHAIN to 1 (CR 759814).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BSCANE2 (
CAPTURE,
DRCK,
RESET,
RUNTEST,
SEL,
SHIFT,
TCK,
TDI,
TMS,
UPDATE,
TDO
);
parameter DISABLE_JTAG = "FALSE";
parameter integer JTAG_CHAIN = 1;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CAPTURE;
output DRCK;
output RESET;
output RUNTEST;
output SEL;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO;
reg SEL_zd;
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
//--####################################################################
//--##### Initialization ###
//--####################################################################
initial begin
//-------- JTAG_CHAIN
if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin
$display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN);
$finish;
end
end
//--####################################################################
//--##### Jtag_select ###
//--####################################################################
always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin
if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL;
else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL;
else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL;
else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL;
end
//--####################################################################
//--####################################################################
//--##### USER_TDO ###
//--####################################################################
always@(TDO) begin
if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO;
else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO;
else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO;
else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO;
end
//--####################################################################
//--##### Output ###
//--####################################################################
assign CAPTURE = glbl.JTAG_CAPTURE_GLBL;
assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL)
||
(SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL)
||
(SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL));
assign RESET = glbl.JTAG_RESET_GLBL;
assign RUNTEST = glbl.JTAG_RUNTEST_GLBL;
assign SEL = SEL_zd;
assign SHIFT = glbl.JTAG_SHIFT_GLBL;
assign TDI = glbl.JTAG_TDI_GLBL;
assign TCK = glbl.JTAG_TCK_GLBL;
assign TMS = glbl.JTAG_TMS_GLBL;
assign UPDATE = glbl.JTAG_UPDATE_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUF.v 0000664 0000000 0000000 00000002244 12327044266 0022040 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / General Purpose Buffer
// /___/ /\ Filename : BUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUF (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFCE_LEAF.v 0000664 0000000 0000000 00000010041 12327044266 0023031 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_LEAF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_LEAF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_LEAF_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFCE_ROW.v 0000664 0000000 0000000 00000010534 12327044266 0023000 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_ROW.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_ROW #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_ROW";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_ROW_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
(CE *> O) = (0:0:0, 0:0:0);
(I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFG.v 0000664 0000000 0000000 00000002365 12327044266 0022153 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Global Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFG (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFGCE.v 0000664 0000000 0000000 00000010706 12327044266 0022361 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFGCE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCE_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // Unisim
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
`endif
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
(CE *> O) = (0:0:0, 0:0:0);
(I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFGCE_DIV.v 0000664 0000000 0000000 00000020034 12327044266 0023056 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer with Divide
// /___/ /\ Filename : BUFGCE_DIV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 04/30/12 - Initial version.
// 02/28/13 - 703678 - update BUFGCE_DIVIDE attribute type.
// 06/20/13 - 723918 - Add latch on CE to match HW
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE_DIV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer BUFGCE_DIVIDE = 1,
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input CLR,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE_DIV";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
`ifndef XIL_DR
localparam BUFGCE_DIVIDE_REG = BUFGCE_DIVIDE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire BUFGCE_DIVIDE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_CLR_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCE_DIV_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire CLR_in;
wire I_in;
wire CE_delay;
wire CLR_delay;
wire I_delay;
integer clk_count=1, first_toggle_count=1, second_toggle_count=1;
reg first_rise, first_half_period;
reg o_out_divide = 0;
wire i_ce, i_inv;
reg ce_en;
// input output assignments
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) I_delay = I;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CLR_delay = CLR;
`endif // `ifndef XIL_TIMING
assign O_delay = O_out;
assign CE_in = CE_delay ^ IS_CE_INVERTED_BIN;
assign CLR_in = CLR_delay ^ IS_CLR_INVERTED_BIN;
assign I_in = I_delay ^ IS_I_INVERTED_BIN;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign BUFGCE_DIVIDE_BIN = BUFGCE_DIVIDE_REG;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((BUFGCE_DIVIDE_REG < 1) && (BUFGCE_DIVIDE_REG > 8)) // decimal
begin
$display("Attribute Syntax Error : The attribute BUFGCE_DIVIDE on %s instance %m is set to %d. Legal values for this attribute are 1 to 8.", MODULE_NAME, BUFGCE_DIVIDE_REG);
attr_err = 1'b1;
end
if ((IS_CE_INVERTED_REG != 1'b0) && (IS_CE_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLR_INVERTED_REG != 1'b0) && (IS_CLR_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_CLR_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLR_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG != 1'b0) && (IS_I_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
case (BUFGCE_DIVIDE_REG)
1 : begin
first_toggle_count = 1;
second_toggle_count = 1;
end
2 : begin
first_toggle_count = 2;
second_toggle_count = 2;
end
3 : begin
first_toggle_count = 2;
second_toggle_count = 4;
end
4 : begin
first_toggle_count = 4;
second_toggle_count = 4;
end
5 : begin
first_toggle_count = 4;
second_toggle_count = 6;
end
6 : begin
first_toggle_count = 6;
second_toggle_count = 6;
end
7 : begin
first_toggle_count = 6;
second_toggle_count = 8;
end
8 : begin
first_toggle_count = 8;
second_toggle_count = 8;
end
endcase // case(BUFGCE_DIV)
if (attr_err == 1'b1) $finish;
end
always begin
if (glblGSR == 1'b1) begin
assign o_out_divide = 1'b0;
assign clk_count = 0;
assign first_rise = 1'b1;
assign first_half_period = 1'b0;
end
else if (glblGSR == 1'b0) begin
deassign o_out_divide;
deassign clk_count;
deassign first_rise;
deassign first_half_period;
end
@(glblGSR);
end
assign i_inv = ~I_in;
always @(glblGSR, CLR_in, I_in, CE_in)
begin
if(glblGSR || CLR_in)
ce_en <= 1'b0;
else if (~I_in)
ce_en <= CE_in;
end
assign i_ce = I_in & ce_en;
always @(i_ce or posedge glblGSR or posedge CLR_in) begin
if (first_toggle_count == 1) begin
o_out_divide = i_ce;
end
else begin
if(CLR_in == 1'b1 || glblGSR == 1'b1) begin
o_out_divide = 1'b0;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b1;
end
else if(CLR_in == 1'b0 && glblGSR == 1'b0) begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b0;
end
else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin
o_out_divide = ~o_out_divide;
clk_count = 1;
first_half_period = 1'b1;
end
else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin
o_out_divide = ~o_out_divide;
clk_count = 1;
first_half_period = 1'b0;
end
else if (first_rise == 1'b0) begin
clk_count = clk_count + 1;
end
end
end
end
// assign O_out = (period_toggle == 0) ? I_in : o_out_divide;
assign O_out = o_out_divide;
specify
( CLR *> O) = (0:0:0, 0:0:0);
( I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$recrem ( negedge CLR, negedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( negedge CLR, posedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( posedge CLR, negedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( posedge CLR, posedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
// not needed ?
$setuphold (negedge I, negedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (negedge I, posedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (posedge I, negedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (posedge I, posedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFGCTRL.v 0000664 0000000 0000000 00000033545 12327044266 0022644 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : BUFGCTRL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 723696 - dynamic register change
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCTRL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE0_INVERTED = 1'b0,
parameter [0:0] IS_CE1_INVERTED = 1'b0,
parameter [0:0] IS_I0_INVERTED = 1'b0,
parameter [0:0] IS_I1_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0,
parameter [0:0] IS_S0_INVERTED = 1'b0,
parameter [0:0] IS_S1_INVERTED = 1'b0,
parameter PRESELECT_I0 = "FALSE",
parameter PRESELECT_I1 = "FALSE"
)(
output O,
input CE0,
input CE1,
input I0,
input I1,
input IGNORE0,
input IGNORE1,
input S0,
input S1
);
// define constants
localparam MODULE_NAME = "BUFGCTRL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam INIT_OUT_0 = 0;
localparam INIT_OUT_1 = 1;
localparam PRESELECT_I0_FALSE = 0;
localparam PRESELECT_I0_TRUE = 1;
localparam PRESELECT_I1_FALSE = 0;
localparam PRESELECT_I1_TRUE = 1;
`ifndef XIL_DR
localparam [0:0] INIT_OUT_REG = INIT_OUT;
localparam [0:0] IS_CE0_INVERTED_REG = IS_CE0_INVERTED;
localparam [0:0] IS_CE1_INVERTED_REG = IS_CE1_INVERTED;
localparam [0:0] IS_I0_INVERTED_REG = IS_I0_INVERTED;
localparam [0:0] IS_I1_INVERTED_REG = IS_I1_INVERTED;
localparam [0:0] IS_IGNORE0_INVERTED_REG = IS_IGNORE0_INVERTED;
localparam [0:0] IS_IGNORE1_INVERTED_REG = IS_IGNORE1_INVERTED;
localparam [0:0] IS_S0_INVERTED_REG = IS_S0_INVERTED;
localparam [0:0] IS_S1_INVERTED_REG = IS_S1_INVERTED;
localparam [40:1] PRESELECT_I0_REG = PRESELECT_I0;
localparam [40:1] PRESELECT_I1_REG = PRESELECT_I1;
`endif
wire INIT_OUT_BIN;
wire IS_CE0_INVERTED_BIN;
wire IS_CE1_INVERTED_BIN;
wire IS_I0_INVERTED_BIN;
wire IS_I1_INVERTED_BIN;
wire IS_IGNORE0_INVERTED_BIN;
wire IS_IGNORE1_INVERTED_BIN;
wire IS_S0_INVERTED_BIN;
wire IS_S1_INVERTED_BIN;
wire PRESELECT_I0_BIN;
wire PRESELECT_I1_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCTRL_dr.v"
`endif
wire O_delay;
wire CE0_in;
wire CE1_in;
wire I0_in;
wire I1_in;
wire IGNORE0_in;
wire IGNORE1_in;
wire S0_in;
wire S1_in;
wire CE0_delay;
wire CE1_delay;
wire I0_delay;
wire I1_delay;
wire IGNORE0_delay;
wire IGNORE1_delay;
wire S0_delay;
wire S1_delay;
reg O_out;
reg q0, q1;
reg q0_enable, q1_enable;
reg task_input_ce0, task_input_ce1, task_input_i0;
reg task_input_i1, task_input_ignore0, task_input_ignore1;
reg task_input_gsr, task_input_s0, task_input_s1;
wire I0t, I1t;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE0_delay = CE0;
assign #(in_delay) CE1_delay = CE1;
assign #(in_delay) I0_delay = I0;
assign #(in_delay) I1_delay = I1;
assign #(in_delay) IGNORE0_delay = IGNORE0;
assign #(in_delay) IGNORE1_delay = IGNORE1;
assign #(in_delay) S0_delay = S0;
assign #(in_delay) S1_delay = S1;
assign O_delay = O_out;
assign CE0_in = IS_CE0_INVERTED_BIN ^ CE0_delay;
assign CE1_in = IS_CE1_INVERTED_BIN ^ CE1_delay;
assign I0_in = IS_I0_INVERTED_BIN ^ I0_delay;
assign I1_in = IS_I1_INVERTED_BIN ^ I1_delay;
assign IGNORE0_in = IS_IGNORE0_INVERTED_BIN ^ IGNORE0_delay;
assign IGNORE1_in = IS_IGNORE1_INVERTED_BIN ^ IGNORE1_delay;
assign S0_in = IS_S0_INVERTED_BIN ^ S0_delay;
assign S1_in = IS_S1_INVERTED_BIN ^ S1_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign INIT_OUT_BIN = INIT_OUT_REG;
assign IS_CE0_INVERTED_BIN = IS_CE0_INVERTED_REG;
assign IS_CE1_INVERTED_BIN = IS_CE1_INVERTED_REG;
assign IS_I0_INVERTED_BIN = IS_I0_INVERTED_REG;
assign IS_I1_INVERTED_BIN = IS_I1_INVERTED_REG;
assign IS_IGNORE0_INVERTED_BIN = IS_IGNORE0_INVERTED_REG;
assign IS_IGNORE1_INVERTED_BIN = IS_IGNORE1_INVERTED_REG;
assign IS_S0_INVERTED_BIN = IS_S0_INVERTED_REG;
assign IS_S1_INVERTED_BIN = IS_S1_INVERTED_REG;
assign PRESELECT_I0_BIN =
(PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE :
(PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE :
PRESELECT_I0_FALSE;
assign PRESELECT_I1_BIN =
(PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE :
(PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE :
PRESELECT_I1_FALSE;
always @ (trig_attr) begin
#1;
if ((PRESELECT_I0_REG != "FALSE") && (PRESELECT_I0_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PRESELECT_I0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PRESELECT_I0_REG);
attr_err = 1'b1;
end
if ((PRESELECT_I1_REG != "FALSE") && (PRESELECT_I1_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PRESELECT_I1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PRESELECT_I1_REG);
attr_err = 1'b1;
end
// *** both preselects can not be 1 simultaneously.
if ((PRESELECT_I0_REG == "TRUE") && (PRESELECT_I1_REG == "TRUE")) begin
$display("Attribute Syntax Error : The attributes PRESELECT_I0 and PRESELECT_I1 on BUFGCTRL instance %m should not be set to TRUE simultaneously.");
attr_err = 1'b1;
end
if ((INIT_OUT_REG != 0) && (INIT_OUT_REG != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_OUT on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, INIT_OUT_REG);
attr_err = 1'b1;
end
if ((IS_CE0_INVERTED_REG != 1'b0) && (IS_CE0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CE0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CE1_INVERTED_REG != 1'b0) && (IS_CE1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CE1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I0_INVERTED_REG != 1'b0) && (IS_I0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_I0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I1_INVERTED_REG != 1'b0) && (IS_I1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_I1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_IGNORE0_INVERTED_REG != 1'b0) && (IS_IGNORE0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_IGNORE0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_IGNORE0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_IGNORE1_INVERTED_REG != 1'b0) && (IS_IGNORE1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_IGNORE1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_IGNORE1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_S0_INVERTED_REG != 1'b0) && (IS_S0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_S0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_S0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_S1_INVERTED_REG != 1'b0) && (IS_S1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_S1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_S1_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
// *** Start here
assign I0t = INIT_OUT_BIN ^ I0_in;
assign I1t = INIT_OUT_BIN ^ I1_in;
// *** Input enable for i1
always @(IGNORE1_in or I1t or S1_in or glblGSR or q0 or PRESELECT_I1_BIN) begin
if (glblGSR == 1)
q1_enable <= PRESELECT_I1_BIN;
else if (glblGSR == 0) begin
if ((I1t == 0) && (IGNORE1_in == 0))
q1_enable <= q1_enable;
else if ((I1t == 1) || (IGNORE1_in == 1))
q1_enable <= (~q0 && S1_in);
end
end
// *** Output q1 for i1
always @(q1_enable or CE1_in or I1t or IGNORE1_in or glblGSR or PRESELECT_I1_BIN) begin
if (glblGSR == 1)
q1 <= PRESELECT_I1_BIN;
else if (glblGSR == 0) begin
if ((I1t == 1)&& (IGNORE1_in == 0))
q1 <= q1;
else if ((I1t == 0) || (IGNORE1_in == 1))
q1 <= (CE1_in && q1_enable);
end
end
// *** input enable for i0
always @(IGNORE0_in or I0t or S0_in or glblGSR or q1 or PRESELECT_I0_BIN) begin
if (glblGSR == 1)
q0_enable <= PRESELECT_I0_BIN;
else if (glblGSR == 0) begin
if ((I0t == 0) && (IGNORE0_in == 0))
q0_enable <= q0_enable;
else if ((I0t == 1) || (IGNORE0_in == 1))
q0_enable <= (~q1 && S0_in);
end
end
// *** Output q0 for i0
always @(q0_enable or CE0_in or I0t or IGNORE0_in or glblGSR or PRESELECT_I0_BIN) begin
if (glblGSR == 1)
q0 <= PRESELECT_I0_BIN;
else if (glblGSR == 0) begin
if ((I0t == 1) && (IGNORE0_in == 0))
q0 <= q0;
else if ((I0t == 0) || (IGNORE0_in == 1))
q0 <= (CE0_in && q0_enable);
end
end
always @(q0 or q1 or I0t or I1t) begin
case ({q1, q0})
2'b01: O_out = I0_in;
2'b10: O_out = I1_in;
2'b00: O_out = INIT_OUT_BIN;
2'b11: begin
q0 = 1'bx;
q1 = 1'bx;
q0_enable = 1'bx;
q1_enable = 1'bx;
O_out = 1'bx;
end
endcase
end
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
$setuphold (posedge I0, posedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, negedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, posedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, negedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, posedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, negedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, posedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, negedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, posedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, negedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, posedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, negedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, posedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, negedge CE0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, posedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, negedge CE1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, posedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, negedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, posedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, negedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, posedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, negedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, posedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, negedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, posedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, negedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, posedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, negedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, posedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, negedge S0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, posedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, negedge S1, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I1, posedge I0, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I0, posedge I1, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I1, negedge I0, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I0, negedge I1, 0:0:0, 0:0:0, notifier);
$period (posedge I0, 0:0:0, notifier);
$period (posedge I1, 0:0:0, notifier);
$width (posedge I0, 0:0:0, 0, notifier);
$width (negedge I0, 0:0:0, 0, notifier);
$width (posedge I1, 0:0:0, 0, notifier);
$width (negedge I1, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFGP.v 0000664 0000000 0000000 00000002333 12327044266 0022266 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Primary Global Buffer for Driving Clocks or Long Lines
// /___/ /\ Filename : BUFGP.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFGP (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFG_GT.v 0000664 0000000 0000000 00000016261 12327044266 0022545 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer with Divide
// /___/ /\ Filename : BUFG_GT.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/20/13 - Initial version.
// 05/06/13 - 716311 - match with hardware
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFG_GT #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_CLR_INVERTED = 1'b0
)(
output O,
input CE,
input CEMASK,
input CLR,
input CLRMASK,
input [2:0] DIV,
input I
);
// define constants
localparam MODULE_NAME = "BUFG_GT";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
`endif
wire IS_CLR_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFG_GT_dr.v"
`endif
wire O_out;
wire O_delay;
wire CEMASK_in;
wire CE_in;
wire CLRMASK_in;
wire CLR_in;
wire I_in;
wire [2:0] DIV_in;
wire CEMASK_delay;
wire CE_delay;
wire CLRMASK_delay;
wire CLR_delay;
wire I_delay;
wire [2:0] DIV_delay;
integer clk_count=1, first_toggle_count=1, second_toggle_count=1;
reg first_rise, first_half_period;
reg O_out_gl = 0;
wire i_ce, i_inv, clr_inv;
wire ce_masked, clrmask_inv, clr_masked;
reg ce_en;
reg ce_sync1, ce_sync, clr_sync1, clr_sync;
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) I_delay = I;
assign #(in_delay) CEMASK_delay = CEMASK;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CLRMASK_delay = CLRMASK;
assign #(in_delay) DIV_delay = DIV;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) CLR_delay = CLR;
assign O_delay = O_out;
assign CEMASK_in = CEMASK_delay;
assign CE_in = CE_delay;
assign CLRMASK_in = CLRMASK_delay;
assign CLR_in = CLR_delay ^ IS_CLR_INVERTED_BIN;
assign DIV_in = DIV_delay;
assign I_in = I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((IS_CLR_INVERTED_REG != 1'b0) && (IS_CLR_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLR_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLR_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always@(DIV_in)
begin
case (DIV_in)
3'b000 : begin
first_toggle_count = 1;
second_toggle_count = 1;
end
3'b001 : begin
first_toggle_count = 2;
second_toggle_count = 2;
end
3'b010 : begin
first_toggle_count = 2;
second_toggle_count = 4;
end
3'b011 : begin
first_toggle_count = 4;
second_toggle_count = 4;
end
3'b100 : begin
first_toggle_count = 4;
second_toggle_count = 6;
end
3'b101 : begin
first_toggle_count = 6;
second_toggle_count = 6;
end
3'b110 : begin
first_toggle_count = 6;
second_toggle_count = 8;
end
3'b111 : begin
first_toggle_count = 8;
second_toggle_count = 8;
end
endcase // case(BUFG_GT)
end //
always
begin
if (glblGSR == 1'b1) begin
assign O_out_gl = 1'b0;
assign clk_count = 0;
assign first_rise = 1'b1;
assign first_half_period = 1'b0;
end
else if (glblGSR == 1'b0) begin
deassign O_out_gl;
deassign clk_count;
deassign first_rise;
deassign first_half_period;
end
@(glblGSR);
end
always @(posedge I_in, negedge glblGSR)
begin
if (glblGSR == 1'b1)
begin
ce_sync1 <= 1'b0;
ce_sync <= 1'b0;
end
else
begin
ce_sync1 <= CE_in;
ce_sync <= ce_sync1;
end
end
assign clr_inv = ~CLR_in;
always @(posedge I_in, negedge clr_inv)
begin
if(~clr_inv)
begin
clr_sync1 <= 1'b0;
clr_sync <= 1'b0;
end
else
{clr_sync, clr_sync1} <= {clr_sync1, 1'b1};
end
assign clr_out = ~clr_sync;
assign i_inv = ~I_in;
assign clrmask_inv = ~CLRMASK_in;
assign ce_masked = ce_sync | CEMASK_in;
assign clr_masked = clr_out & clrmask_inv;
always @(i_inv, glblGSR, ce_masked, clr_masked)
begin
if (glblGSR || clr_masked)
ce_en <= 1'b0;
else if (i_inv)
ce_en <= ce_masked;
end
assign i_ce = I_in & ce_en;
always @(i_ce or posedge glblGSR or posedge clr_masked) begin
if (first_toggle_count == 1) begin
O_out_gl = i_ce;
end
else begin
if(clr_masked == 1'b1 || glblGSR == 1'b1) begin
O_out_gl = 1'b0;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b1;
end
else if(clr_masked == 1'b0 && glblGSR == 1'b0) begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
O_out_gl = 1'b1;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b0;
end
else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin
O_out_gl = ~O_out_gl;
clk_count = 1;
first_half_period = 1'b1;
end
else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin
O_out_gl = ~O_out_gl;
clk_count = 1;
first_half_period = 1'b0;
end
else if (first_rise == 1'b0) begin
clk_count = clk_count + 1;
end
end
end
end
assign #1 O_out = O_out_gl;
specify
( CLR *> O) = (0:0:0, 0:0:0);
( CLRMASK *> O) = (0:0:0, 0:0:0);
( I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$recrem ( negedge CLRMASK, posedge I, 0:0:0, 0:0:0);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CEMASK, 0:0:0, 0:0:0, notifier,,, I_delay, CEMASK_delay);
$setuphold (posedge I, negedge CLRMASK, 0:0:0, 0:0:0, notifier,,, I_delay, CLRMASK_delay);
$setuphold (posedge I, negedge DIV, 0:0:0, 0:0:0, notifier,,, I_delay, DIV_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFH.v 0000664 0000000 0000000 00000002370 12327044266 0022150 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/BUFH.v,v 1.3 2008/11/11 21:41:06 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / H Clock Buffer
// /___/ /\ Filename : BUFH.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 09//9/08 - Change to use BUFHCE according to yaml.
// 11/11/08 - Change to not use BUFHCE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFH (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFHCE.v 0000664 0000000 0000000 00000007102 12327044266 0022356 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / H Clock Buffer with Active High Enable
// /___/ /\ Filename : BUFHCE.v
// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 09/19/08 - Add GSR
// 10/19/08 - Recoding to same as BUFGCE according to hardware.
// 11/15/10 - Add CE_TYPE attribute (CR578114)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/24/12 - 661573 - Remove 100 ps delay
// 10/12/12 - 681696 - fix preselect behavior.
// 10/30/12 - 684744 - match mapping with ISE.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module BUFHCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire del_I, delCE;
wire NCE, o_bufg_o, o_bufg1_o;
reg CE_TYPE_BINARY;
reg INIT_OUT_BINARY;
reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;
initial begin
case (CE_TYPE)
"SYNC" : CE_TYPE_BINARY = 1'b0;
"ASYNC" : CE_TYPE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CE_TYPE on BUFHCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
$finish;
end
endcase
if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
INIT_OUT_BINARY = INIT_OUT;
else begin
$display("Attribute Syntax Error : The Attribute INIT_OUT on BUFHCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT);
$finish;
end
end
BUFGCTRL bufgctrl0_inst (.O(o_bufg_o),
.CE0(~NCE),
.CE1(NCE),
.I0(del_I),
.I1(1'b0),
.IGNORE0(CE_TYPE_BINARY),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1));
defparam bufgctrl0_inst.INIT_OUT = 1'b0;
defparam bufgctrl0_inst.PRESELECT_I0 = "TRUE";
defparam bufgctrl0_inst.PRESELECT_I1 = "FALSE";
INV I1 (.I(delCE ^ IS_CE_INVERTED_BIN),
.O(NCE));
BUFGCTRL bufgctrl1_inst (.O(o_bufg1_o),
.CE0(~NCE),
.CE1(NCE),
.I0(del_I),
.I1(1'b1),
.IGNORE0(CE_TYPE_BINARY),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1));
defparam bufgctrl1_inst.INIT_OUT = 1'b0;
defparam bufgctrl1_inst.PRESELECT_I0 = "TRUE";
defparam bufgctrl1_inst.PRESELECT_I1 = "FALSE";
assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;
`ifndef XIL_TIMING
assign del_I = I;
assign delCE = CE;
`endif
specify
(I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFIO.v 0000664 0000000 0000000 00000002412 12327044266 0022265 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFIO.v,v 1.4 2007/06/01 22:41:59 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Local Clock Buffer for I/O
// /___/ /\ Filename : BUFIO.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/30/07 - change timescale to 1ps/1ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFIO (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`timescale 1 ps / 1 ps
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFMR.v 0000664 0000000 0000000 00000002101 12327044266 0022267 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/fuji/BUFMR.v,v 1.1 2009/12/21 21:08:16 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMR.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMR (
O,
I
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFMRCE.v 0000664 0000000 0000000 00000005724 12327044266 0022515 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFMRCE.v,v 1.1 2010/04/28 21:43:11 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMRCE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMRCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
wire NCE, o_bufg_o, o_bufg1_o;
reg CE_TYPE_BINARY;
reg INIT_OUT_BINARY;
reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire O_OUT;
wire delay_CE;
wire delay_I;
initial begin
case (CE_TYPE)
"SYNC" : CE_TYPE_BINARY = 1'b0;
"ASYNC" : CE_TYPE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CE_TYPE on BUFMRCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
$finish;
end
endcase
if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
INIT_OUT_BINARY = INIT_OUT;
else begin
$display("Attribute Syntax Error : The Attribute INIT_OUT on BUFMRCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT);
$finish;
end
end
BUFGCTRL #(.INIT_OUT(1'b0), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B1
(.O(o_bufg_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b0), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
INV I1 (.I(delay_CE ^ IS_CE_INVERTED_BIN), .O(NCE));
BUFGCTRL #(.INIT_OUT(1'b1), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B2
(.O(o_bufg1_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_CE = CE;
`endif
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/BUFR.v 0000664 0000000 0000000 00000015543 12327044266 0022170 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFR.v,v 1.6 2011/08/09 22:45:10 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock
// latency for Virtex 4 and none for Rainier
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to FUJI (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change FUJI to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "VIRTEX4";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
$finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
$finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(CLR => O) = (0:0:0, 0:0:0);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/CAPTUREE2.v 0000664 0000000 0000000 00000003617 12327044266 0022723 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/CAPTUREE2.v,v 1.1 2010/05/27 18:53:42 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : CAPTUREE2.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 05/09/12 - removed GSR reference (CR 659430).
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CAPTUREE2 (
CAP,
CLK
);
parameter ONESHOT = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
input CAP;
input CLK;
reg [0:0] ONESHOT_BINARY;
reg notifier;
wire CAP_IN;
wire CLK_IN;
wire CAP_INDELAY;
wire CLK_INDELAY;
initial begin
case (ONESHOT)
"TRUE" : ONESHOT_BINARY = 1'b1;
"FALSE" : ONESHOT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ONESHOT on CAPTUREE2 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ONESHOT);
$finish;
end
endcase
end
buf B_CAP (CAP_IN, CAP);
buf B_CLK (CLK_IN, CLK);
specify
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
$setuphold (posedge CLK, posedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/CARRY4.v 0000664 0000000 0000000 00000012450 12327044266 0022370 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY4.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/11/05 - Initial version.
// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752)
// 05/31/05 - Change pin order, remove connection check for CYINIT and CI.
// 12/21/05 - Add timing path.
// 04/13/06 - Add full timing path for DI to O (CR228786)
// 06/04/07 - Add wire definition.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CARRY4 (CO, O, CI, CYINIT, DI, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
wire [3:0] di_in, s_in, o_out, co_out;
wire ci_or_cyinit;
wire ci_in, cyinit_in;
pulldown P1 (CI);
pulldown P2 (CYINIT);
assign ci_in = CI;
assign cyinit_in = CYINIT;
assign di_in = DI;
assign s_in = S;
assign O = o_out;
assign CO = co_out;
assign o_out = s_in ^ {co_out[2:0], ci_or_cyinit};
assign co_out[0] = s_in[0] ? ci_or_cyinit : di_in[0];
assign co_out[1] = s_in[1] ? co_out[0] : di_in[1];
assign co_out[2] = s_in[2] ? co_out[1] : di_in[2];
assign co_out[3] = s_in[3] ? co_out[2] : di_in[3];
assign ci_or_cyinit = ci_in | cyinit_in;
`ifdef XIL_TIMING
specify
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CYINIT => O[0]) = (0:0:0, 0:0:0);
(CYINIT => O[1]) = (0:0:0, 0:0:0);
(CYINIT => O[2]) = (0:0:0, 0:0:0);
(CYINIT => O[3]) = (0:0:0, 0:0:0);
(CYINIT => CO[0]) = (0:0:0, 0:0:0);
(CYINIT => CO[1]) = (0:0:0, 0:0:0);
(CYINIT => CO[2]) = (0:0:0, 0:0:0);
(CYINIT => CO[3]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[1] => O[0]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[2] => O[0]) = (0:0:0, 0:0:0);
(S[2] => O[1]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[3] => O[0]) = (0:0:0, 0:0:0);
(S[3] => O[1]) = (0:0:0, 0:0:0);
(S[3] => O[2]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => CO[0]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => CO[0]) = (0:0:0, 0:0:0);
(S[2] => CO[1]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => CO[0]) = (0:0:0, 0:0:0);
(S[3] => CO[1]) = (0:0:0, 0:0:0);
(S[3] => CO[2]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[0]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[0]) = (0:0:0, 0:0:0);
(DI[2] => CO[1]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[0]) = (0:0:0, 0:0:0);
(DI[3] => CO[1]) = (0:0:0, 0:0:0);
(DI[3] => CO[2]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => O[0]) = (0:0:0, 0:0:0);
(DI[1] => O[1]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => O[0]) = (0:0:0, 0:0:0);
(DI[2] => O[1]) = (0:0:0, 0:0:0);
(DI[2] => O[2]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[3] => O[0]) = (0:0:0, 0:0:0);
(DI[3] => O[1]) = (0:0:0, 0:0:0);
(DI[3] => O[2]) = (0:0:0, 0:0:0);
(DI[3] => O[3]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/CARRY8.v 0000664 0000000 0000000 00000036767 12327044266 0022415 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY8.v
// \ \ / \
// \___\/\__ \
//
// Revision:
// 09/26/12 - Initial functional version.
// 05/24/13 - Add CARRY_TYPE, CI_TOP
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CARRY8 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CARRY_TYPE = "SINGLE_CY8"
)(
output [7:0] CO,
output [7:0] O,
input CI,
input CI_TOP,
input [7:0] DI,
input [7:0] S
);
// define constants
localparam MODULE_NAME = "CARRY8";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam [0:0] CARRY_TYPE_DUAL_CY4 = 1'b1;
localparam [0:0] CARRY_TYPE_SINGLE_CY8 = 1'b0;
`ifndef XIL_DR
localparam [80:1] CARRY_TYPE_REG = CARRY_TYPE;
`endif
wire CARRY_TYPE_BIN;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "CARRY8_dr.v"
`endif
wire [7:0] CO_out;
wire [7:0] O_out;
wire [7:0] CO_delay;
wire [7:0] O_delay;
wire CI_TOP_in;
wire CI_in;
wire [7:0] DI_in;
wire [7:0] S_in;
wire CI_TOP_delay;
wire CI_delay;
wire [7:0] DI_delay;
wire [7:0] S_delay;
wire [7:0] CO_fb;
wire select_top;
// input output assignments
assign #(out_delay) CO = CO_delay;
assign #(out_delay) O = O_delay;
assign #(in_delay) CI_TOP_delay = CI_TOP;
assign #(in_delay) CI_delay = CI;
assign #(in_delay) DI_delay = DI;
assign #(in_delay) S_delay = S;
assign CO_delay = CO_out;
assign O_delay = O_out;
assign select_top = (CARRY_TYPE_BIN == CARRY_TYPE_DUAL_CY4);
assign CI_TOP_in = ((CI_TOP !== 1'bz) && (select_top & CI_TOP_delay)) | (~select_top & CO_out[3]);
assign CI_in = (CI !== 1'bz) && CI_delay;
assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7];
assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6];
assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5];
assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4];
assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3];
assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2];
assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1];
assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0];
assign S_in[7] = (S[7] !== 1'bz) && S_delay[7];
assign S_in[6] = (S[6] !== 1'bz) && S_delay[6];
assign S_in[5] = (S[5] !== 1'bz) && S_delay[5];
assign S_in[4] = (S[4] !== 1'bz) && S_delay[4];
assign S_in[3] = (S[3] !== 1'bz) && S_delay[3];
assign S_in[2] = (S[2] !== 1'bz) && S_delay[2];
assign S_in[1] = (S[1] !== 1'bz) && S_delay[1];
assign S_in[0] = (S[0] !== 1'bz) && S_delay[0];
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CARRY_TYPE_BIN =
(CARRY_TYPE_REG == "SINGLE_CY8") ? CARRY_TYPE_SINGLE_CY8 :
(CARRY_TYPE_REG == "DUAL_CY4") ? CARRY_TYPE_DUAL_CY4 :
CARRY_TYPE_SINGLE_CY8;
always @ (trig_attr) begin
#1;
if ((CARRY_TYPE_REG != "SINGLE_CY8") && (CARRY_TYPE_REG != "DUAL_CY4")) // string
begin
$display("Attribute Syntax Error : The attribute CARRY_TYPE on %s instance %m is set to %s. Legal values for this attribute are SINGLE_CY8 or DUAL_CY4.", MODULE_NAME, CARRY_TYPE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CO_fb = {CO_out[6:4], CI_TOP_in, CO_out[2:0], CI_in};
assign O_out = S_in ^ CO_fb;
assign CO_out = (S_in & CO_fb) | (~S_in & DI_in);
`ifdef XIL_TIMING
specify
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CI => O[4]) = (0:0:0, 0:0:0);
(CI => O[5]) = (0:0:0, 0:0:0);
(CI => O[6]) = (0:0:0, 0:0:0);
(CI => O[7]) = (0:0:0, 0:0:0);
(CI_TOP => O[4]) = (0:0:0, 0:0:0);
(CI_TOP => O[5]) = (0:0:0, 0:0:0);
(CI_TOP => O[6]) = (0:0:0, 0:0:0);
(CI_TOP => O[7]) = (0:0:0, 0:0:0);
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CI => CO[4]) = (0:0:0, 0:0:0);
(CI => CO[5]) = (0:0:0, 0:0:0);
(CI => CO[6]) = (0:0:0, 0:0:0);
(CI => CO[7]) = (0:0:0, 0:0:0);
(CI_TOP => CO[4]) = (0:0:0, 0:0:0);
(CI_TOP => CO[5]) = (0:0:0, 0:0:0);
(CI_TOP => CO[6]) = (0:0:0, 0:0:0);
(CI_TOP => CO[7]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[0] => O[4]) = (0:0:0, 0:0:0);
(DI[0] => O[5]) = (0:0:0, 0:0:0);
(DI[0] => O[6]) = (0:0:0, 0:0:0);
(DI[0] => O[7]) = (0:0:0, 0:0:0);
(DI[1] => O[0]) = (0:0:0, 0:0:0);
(DI[1] => O[1]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => O[4]) = (0:0:0, 0:0:0);
(DI[1] => O[5]) = (0:0:0, 0:0:0);
(DI[1] => O[6]) = (0:0:0, 0:0:0);
(DI[1] => O[7]) = (0:0:0, 0:0:0);
(DI[2] => O[0]) = (0:0:0, 0:0:0);
(DI[2] => O[1]) = (0:0:0, 0:0:0);
(DI[2] => O[2]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => O[4]) = (0:0:0, 0:0:0);
(DI[2] => O[5]) = (0:0:0, 0:0:0);
(DI[2] => O[6]) = (0:0:0, 0:0:0);
(DI[2] => O[7]) = (0:0:0, 0:0:0);
(DI[3] => O[0]) = (0:0:0, 0:0:0);
(DI[3] => O[1]) = (0:0:0, 0:0:0);
(DI[3] => O[2]) = (0:0:0, 0:0:0);
(DI[3] => O[3]) = (0:0:0, 0:0:0);
(DI[3] => O[4]) = (0:0:0, 0:0:0);
(DI[3] => O[5]) = (0:0:0, 0:0:0);
(DI[3] => O[6]) = (0:0:0, 0:0:0);
(DI[3] => O[7]) = (0:0:0, 0:0:0);
(DI[4] => O[0]) = (0:0:0, 0:0:0);
(DI[4] => O[1]) = (0:0:0, 0:0:0);
(DI[4] => O[2]) = (0:0:0, 0:0:0);
(DI[4] => O[3]) = (0:0:0, 0:0:0);
(DI[4] => O[4]) = (0:0:0, 0:0:0);
(DI[4] => O[5]) = (0:0:0, 0:0:0);
(DI[4] => O[6]) = (0:0:0, 0:0:0);
(DI[4] => O[7]) = (0:0:0, 0:0:0);
(DI[5] => O[0]) = (0:0:0, 0:0:0);
(DI[5] => O[1]) = (0:0:0, 0:0:0);
(DI[5] => O[2]) = (0:0:0, 0:0:0);
(DI[5] => O[3]) = (0:0:0, 0:0:0);
(DI[5] => O[4]) = (0:0:0, 0:0:0);
(DI[5] => O[5]) = (0:0:0, 0:0:0);
(DI[5] => O[6]) = (0:0:0, 0:0:0);
(DI[5] => O[7]) = (0:0:0, 0:0:0);
(DI[6] => O[0]) = (0:0:0, 0:0:0);
(DI[6] => O[1]) = (0:0:0, 0:0:0);
(DI[6] => O[2]) = (0:0:0, 0:0:0);
(DI[6] => O[3]) = (0:0:0, 0:0:0);
(DI[6] => O[4]) = (0:0:0, 0:0:0);
(DI[6] => O[5]) = (0:0:0, 0:0:0);
(DI[6] => O[6]) = (0:0:0, 0:0:0);
(DI[6] => O[7]) = (0:0:0, 0:0:0);
(DI[7] => O[0]) = (0:0:0, 0:0:0);
(DI[7] => O[1]) = (0:0:0, 0:0:0);
(DI[7] => O[2]) = (0:0:0, 0:0:0);
(DI[7] => O[3]) = (0:0:0, 0:0:0);
(DI[7] => O[4]) = (0:0:0, 0:0:0);
(DI[7] => O[5]) = (0:0:0, 0:0:0);
(DI[7] => O[6]) = (0:0:0, 0:0:0);
(DI[7] => O[7]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[4]) = (0:0:0, 0:0:0);
(DI[0] => CO[5]) = (0:0:0, 0:0:0);
(DI[0] => CO[6]) = (0:0:0, 0:0:0);
(DI[0] => CO[7]) = (0:0:0, 0:0:0);
(DI[1] => CO[0]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[4]) = (0:0:0, 0:0:0);
(DI[1] => CO[5]) = (0:0:0, 0:0:0);
(DI[1] => CO[6]) = (0:0:0, 0:0:0);
(DI[1] => CO[7]) = (0:0:0, 0:0:0);
(DI[2] => CO[0]) = (0:0:0, 0:0:0);
(DI[2] => CO[1]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[4]) = (0:0:0, 0:0:0);
(DI[2] => CO[5]) = (0:0:0, 0:0:0);
(DI[2] => CO[6]) = (0:0:0, 0:0:0);
(DI[2] => CO[7]) = (0:0:0, 0:0:0);
(DI[3] => CO[0]) = (0:0:0, 0:0:0);
(DI[3] => CO[1]) = (0:0:0, 0:0:0);
(DI[3] => CO[2]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[4]) = (0:0:0, 0:0:0);
(DI[3] => CO[5]) = (0:0:0, 0:0:0);
(DI[3] => CO[6]) = (0:0:0, 0:0:0);
(DI[3] => CO[7]) = (0:0:0, 0:0:0);
(DI[4] => CO[0]) = (0:0:0, 0:0:0);
(DI[4] => CO[1]) = (0:0:0, 0:0:0);
(DI[4] => CO[2]) = (0:0:0, 0:0:0);
(DI[4] => CO[3]) = (0:0:0, 0:0:0);
(DI[4] => CO[4]) = (0:0:0, 0:0:0);
(DI[4] => CO[5]) = (0:0:0, 0:0:0);
(DI[4] => CO[6]) = (0:0:0, 0:0:0);
(DI[4] => CO[7]) = (0:0:0, 0:0:0);
(DI[5] => CO[0]) = (0:0:0, 0:0:0);
(DI[5] => CO[1]) = (0:0:0, 0:0:0);
(DI[5] => CO[2]) = (0:0:0, 0:0:0);
(DI[5] => CO[3]) = (0:0:0, 0:0:0);
(DI[5] => CO[4]) = (0:0:0, 0:0:0);
(DI[5] => CO[5]) = (0:0:0, 0:0:0);
(DI[5] => CO[6]) = (0:0:0, 0:0:0);
(DI[5] => CO[7]) = (0:0:0, 0:0:0);
(DI[6] => CO[0]) = (0:0:0, 0:0:0);
(DI[6] => CO[1]) = (0:0:0, 0:0:0);
(DI[6] => CO[2]) = (0:0:0, 0:0:0);
(DI[6] => CO[3]) = (0:0:0, 0:0:0);
(DI[6] => CO[4]) = (0:0:0, 0:0:0);
(DI[6] => CO[5]) = (0:0:0, 0:0:0);
(DI[6] => CO[6]) = (0:0:0, 0:0:0);
(DI[6] => CO[7]) = (0:0:0, 0:0:0);
(DI[7] => CO[0]) = (0:0:0, 0:0:0);
(DI[7] => CO[1]) = (0:0:0, 0:0:0);
(DI[7] => CO[2]) = (0:0:0, 0:0:0);
(DI[7] => CO[3]) = (0:0:0, 0:0:0);
(DI[7] => CO[4]) = (0:0:0, 0:0:0);
(DI[7] => CO[5]) = (0:0:0, 0:0:0);
(DI[7] => CO[6]) = (0:0:0, 0:0:0);
(DI[7] => CO[7]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[0] => O[4]) = (0:0:0, 0:0:0);
(S[0] => O[5]) = (0:0:0, 0:0:0);
(S[0] => O[6]) = (0:0:0, 0:0:0);
(S[0] => O[7]) = (0:0:0, 0:0:0);
(S[1] => O[0]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[1] => O[4]) = (0:0:0, 0:0:0);
(S[1] => O[5]) = (0:0:0, 0:0:0);
(S[1] => O[6]) = (0:0:0, 0:0:0);
(S[1] => O[7]) = (0:0:0, 0:0:0);
(S[2] => O[0]) = (0:0:0, 0:0:0);
(S[2] => O[1]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[2] => O[4]) = (0:0:0, 0:0:0);
(S[2] => O[5]) = (0:0:0, 0:0:0);
(S[2] => O[6]) = (0:0:0, 0:0:0);
(S[2] => O[7]) = (0:0:0, 0:0:0);
(S[3] => O[0]) = (0:0:0, 0:0:0);
(S[3] => O[1]) = (0:0:0, 0:0:0);
(S[3] => O[2]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
(S[3] => O[4]) = (0:0:0, 0:0:0);
(S[3] => O[5]) = (0:0:0, 0:0:0);
(S[3] => O[6]) = (0:0:0, 0:0:0);
(S[3] => O[7]) = (0:0:0, 0:0:0);
(S[4] => O[0]) = (0:0:0, 0:0:0);
(S[4] => O[1]) = (0:0:0, 0:0:0);
(S[4] => O[2]) = (0:0:0, 0:0:0);
(S[4] => O[3]) = (0:0:0, 0:0:0);
(S[4] => O[4]) = (0:0:0, 0:0:0);
(S[4] => O[5]) = (0:0:0, 0:0:0);
(S[4] => O[6]) = (0:0:0, 0:0:0);
(S[4] => O[7]) = (0:0:0, 0:0:0);
(S[5] => O[0]) = (0:0:0, 0:0:0);
(S[5] => O[1]) = (0:0:0, 0:0:0);
(S[5] => O[2]) = (0:0:0, 0:0:0);
(S[5] => O[3]) = (0:0:0, 0:0:0);
(S[5] => O[4]) = (0:0:0, 0:0:0);
(S[5] => O[5]) = (0:0:0, 0:0:0);
(S[5] => O[6]) = (0:0:0, 0:0:0);
(S[5] => O[7]) = (0:0:0, 0:0:0);
(S[6] => O[0]) = (0:0:0, 0:0:0);
(S[6] => O[1]) = (0:0:0, 0:0:0);
(S[6] => O[2]) = (0:0:0, 0:0:0);
(S[6] => O[3]) = (0:0:0, 0:0:0);
(S[6] => O[4]) = (0:0:0, 0:0:0);
(S[6] => O[5]) = (0:0:0, 0:0:0);
(S[6] => O[6]) = (0:0:0, 0:0:0);
(S[6] => O[7]) = (0:0:0, 0:0:0);
(S[7] => O[0]) = (0:0:0, 0:0:0);
(S[7] => O[1]) = (0:0:0, 0:0:0);
(S[7] => O[2]) = (0:0:0, 0:0:0);
(S[7] => O[3]) = (0:0:0, 0:0:0);
(S[7] => O[4]) = (0:0:0, 0:0:0);
(S[7] => O[5]) = (0:0:0, 0:0:0);
(S[7] => O[6]) = (0:0:0, 0:0:0);
(S[7] => O[7]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[0] => CO[4]) = (0:0:0, 0:0:0);
(S[0] => CO[5]) = (0:0:0, 0:0:0);
(S[0] => CO[6]) = (0:0:0, 0:0:0);
(S[0] => CO[7]) = (0:0:0, 0:0:0);
(S[1] => CO[0]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => CO[4]) = (0:0:0, 0:0:0);
(S[1] => CO[5]) = (0:0:0, 0:0:0);
(S[1] => CO[6]) = (0:0:0, 0:0:0);
(S[1] => CO[7]) = (0:0:0, 0:0:0);
(S[2] => CO[0]) = (0:0:0, 0:0:0);
(S[2] => CO[1]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => CO[4]) = (0:0:0, 0:0:0);
(S[2] => CO[5]) = (0:0:0, 0:0:0);
(S[2] => CO[6]) = (0:0:0, 0:0:0);
(S[2] => CO[7]) = (0:0:0, 0:0:0);
(S[3] => CO[0]) = (0:0:0, 0:0:0);
(S[3] => CO[1]) = (0:0:0, 0:0:0);
(S[3] => CO[2]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => CO[4]) = (0:0:0, 0:0:0);
(S[3] => CO[5]) = (0:0:0, 0:0:0);
(S[3] => CO[6]) = (0:0:0, 0:0:0);
(S[3] => CO[7]) = (0:0:0, 0:0:0);
(S[4] => CO[0]) = (0:0:0, 0:0:0);
(S[4] => CO[1]) = (0:0:0, 0:0:0);
(S[4] => CO[2]) = (0:0:0, 0:0:0);
(S[4] => CO[3]) = (0:0:0, 0:0:0);
(S[4] => CO[4]) = (0:0:0, 0:0:0);
(S[4] => CO[5]) = (0:0:0, 0:0:0);
(S[4] => CO[6]) = (0:0:0, 0:0:0);
(S[4] => CO[7]) = (0:0:0, 0:0:0);
(S[5] => CO[0]) = (0:0:0, 0:0:0);
(S[5] => CO[1]) = (0:0:0, 0:0:0);
(S[5] => CO[2]) = (0:0:0, 0:0:0);
(S[5] => CO[3]) = (0:0:0, 0:0:0);
(S[5] => CO[4]) = (0:0:0, 0:0:0);
(S[5] => CO[5]) = (0:0:0, 0:0:0);
(S[5] => CO[6]) = (0:0:0, 0:0:0);
(S[5] => CO[7]) = (0:0:0, 0:0:0);
(S[6] => CO[0]) = (0:0:0, 0:0:0);
(S[6] => CO[1]) = (0:0:0, 0:0:0);
(S[6] => CO[2]) = (0:0:0, 0:0:0);
(S[6] => CO[3]) = (0:0:0, 0:0:0);
(S[6] => CO[4]) = (0:0:0, 0:0:0);
(S[6] => CO[5]) = (0:0:0, 0:0:0);
(S[6] => CO[6]) = (0:0:0, 0:0:0);
(S[6] => CO[7]) = (0:0:0, 0:0:0);
(S[7] => CO[0]) = (0:0:0, 0:0:0);
(S[7] => CO[1]) = (0:0:0, 0:0:0);
(S[7] => CO[2]) = (0:0:0, 0:0:0);
(S[7] => CO[3]) = (0:0:0, 0:0:0);
(S[7] => CO[4]) = (0:0:0, 0:0:0);
(S[7] => CO[5]) = (0:0:0, 0:0:0);
(S[7] => CO[6]) = (0:0:0, 0:0:0);
(S[7] => CO[7]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/CFGLUT5.v 0000664 0000000 0000000 00000006326 12327044266 0022502 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : CFGLUT5.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
// \___\/\___\
//
// Revision:
// 12/27/05 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/13/13 - add IS_CLK_INVERTED
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CFGLUT5 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output CDO,
output O5,
output O6,
input I4,
input I3,
input I2,
input I1,
input I0,
input CDI,
input CE,
input CLK
);
reg [31:0] data;
wire [4:0] addr;
wire CDI_dly, CE_dly, CLK_dly;
wire CDI_in, CE_in, CLK_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr = {I4, I3, I2, I1, I0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
data <= #100 {data[30:0], CDI_in};
assign O6 = data[addr[4:0]];
assign O5 = data[addr[3:0]];
assign CDO = data[31];
`ifndef XIL_TIMING
assign CDI_dly = CDI;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign CDI_in = CDI_dly;
assign CE_in = CE_dly;
`ifdef XIL_TIMING
specify
(I0 => O5) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
(I0 => CDO) = (0:0:0, 0:0:0);
(I1 => CDO) = (0:0:0, 0:0:0);
(I2 => CDO) = (0:0:0, 0:0:0);
(I3 => CDO) = (0:0:0, 0:0:0);
(I4 => CDO) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$period (posedge CLK, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$period (negedge CLK, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/CMAC.v 0000664 0000000 0000000 00000363602 12327044266 0022137 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : CMAC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CMAC #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CTL_PTP_TRANSPCLK_MODE = "FALSE",
parameter CTL_RX_CHECK_ACK = "TRUE",
parameter CTL_RX_CHECK_PREAMBLE = "FALSE",
parameter CTL_RX_CHECK_SFD = "FALSE",
parameter CTL_RX_DELETE_FCS = "TRUE",
parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808,
parameter CTL_RX_FORWARD_CONTROL = "FALSE",
parameter CTL_RX_IGNORE_FCS = "FALSE",
parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580,
parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40,
parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001,
parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF,
parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF,
parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000,
parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000,
parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001,
parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001,
parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000,
parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000,
parameter CTL_RX_PROCESS_LFI = "FALSE",
parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF,
parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00,
parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100,
parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600,
parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00,
parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00,
parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200,
parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500,
parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200,
parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300,
parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800,
parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500,
parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00,
parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700,
parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400,
parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600,
parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00,
parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900,
parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900,
parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900,
parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400,
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE",
parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001,
parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001,
parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808,
parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808,
parameter CTL_TX_FCS_INS_ENABLE = "TRUE",
parameter CTL_TX_IGNORE_FCS = "FALSE",
parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001,
parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001,
parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE",
parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1,
parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000,
parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000,
parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF,
parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00,
parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100,
parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600,
parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00,
parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00,
parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200,
parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500,
parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200,
parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300,
parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800,
parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500,
parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00,
parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700,
parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400,
parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600,
parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00,
parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900,
parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900,
parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900,
parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400,
parameter TEST_MODE_PIN_CHAR = "FALSE"
)(
output [15:0] DRP_DO,
output DRP_RDY,
output [127:0] RX_DATAOUT0,
output [127:0] RX_DATAOUT1,
output [127:0] RX_DATAOUT2,
output [127:0] RX_DATAOUT3,
output RX_ENAOUT0,
output RX_ENAOUT1,
output RX_ENAOUT2,
output RX_ENAOUT3,
output RX_EOPOUT0,
output RX_EOPOUT1,
output RX_EOPOUT2,
output RX_EOPOUT3,
output RX_ERROUT0,
output RX_ERROUT1,
output RX_ERROUT2,
output RX_ERROUT3,
output [6:0] RX_LANE_ALIGNER_FILL_0,
output [6:0] RX_LANE_ALIGNER_FILL_1,
output [6:0] RX_LANE_ALIGNER_FILL_10,
output [6:0] RX_LANE_ALIGNER_FILL_11,
output [6:0] RX_LANE_ALIGNER_FILL_12,
output [6:0] RX_LANE_ALIGNER_FILL_13,
output [6:0] RX_LANE_ALIGNER_FILL_14,
output [6:0] RX_LANE_ALIGNER_FILL_15,
output [6:0] RX_LANE_ALIGNER_FILL_16,
output [6:0] RX_LANE_ALIGNER_FILL_17,
output [6:0] RX_LANE_ALIGNER_FILL_18,
output [6:0] RX_LANE_ALIGNER_FILL_19,
output [6:0] RX_LANE_ALIGNER_FILL_2,
output [6:0] RX_LANE_ALIGNER_FILL_3,
output [6:0] RX_LANE_ALIGNER_FILL_4,
output [6:0] RX_LANE_ALIGNER_FILL_5,
output [6:0] RX_LANE_ALIGNER_FILL_6,
output [6:0] RX_LANE_ALIGNER_FILL_7,
output [6:0] RX_LANE_ALIGNER_FILL_8,
output [6:0] RX_LANE_ALIGNER_FILL_9,
output [3:0] RX_MTYOUT0,
output [3:0] RX_MTYOUT1,
output [3:0] RX_MTYOUT2,
output [3:0] RX_MTYOUT3,
output [4:0] RX_PTP_PCSLANE_OUT,
output [79:0] RX_PTP_TSTAMP_OUT,
output RX_SOPOUT0,
output RX_SOPOUT1,
output RX_SOPOUT2,
output RX_SOPOUT3,
output STAT_RX_ALIGNED,
output STAT_RX_ALIGNED_ERR,
output [6:0] STAT_RX_BAD_CODE,
output [3:0] STAT_RX_BAD_FCS,
output STAT_RX_BAD_PREAMBLE,
output STAT_RX_BAD_SFD,
output STAT_RX_BIP_ERR_0,
output STAT_RX_BIP_ERR_1,
output STAT_RX_BIP_ERR_10,
output STAT_RX_BIP_ERR_11,
output STAT_RX_BIP_ERR_12,
output STAT_RX_BIP_ERR_13,
output STAT_RX_BIP_ERR_14,
output STAT_RX_BIP_ERR_15,
output STAT_RX_BIP_ERR_16,
output STAT_RX_BIP_ERR_17,
output STAT_RX_BIP_ERR_18,
output STAT_RX_BIP_ERR_19,
output STAT_RX_BIP_ERR_2,
output STAT_RX_BIP_ERR_3,
output STAT_RX_BIP_ERR_4,
output STAT_RX_BIP_ERR_5,
output STAT_RX_BIP_ERR_6,
output STAT_RX_BIP_ERR_7,
output STAT_RX_BIP_ERR_8,
output STAT_RX_BIP_ERR_9,
output [19:0] STAT_RX_BLOCK_LOCK,
output STAT_RX_BROADCAST,
output [3:0] STAT_RX_FRAGMENT,
output [3:0] STAT_RX_FRAMING_ERR_0,
output [3:0] STAT_RX_FRAMING_ERR_1,
output [3:0] STAT_RX_FRAMING_ERR_10,
output [3:0] STAT_RX_FRAMING_ERR_11,
output [3:0] STAT_RX_FRAMING_ERR_12,
output [3:0] STAT_RX_FRAMING_ERR_13,
output [3:0] STAT_RX_FRAMING_ERR_14,
output [3:0] STAT_RX_FRAMING_ERR_15,
output [3:0] STAT_RX_FRAMING_ERR_16,
output [3:0] STAT_RX_FRAMING_ERR_17,
output [3:0] STAT_RX_FRAMING_ERR_18,
output [3:0] STAT_RX_FRAMING_ERR_19,
output [3:0] STAT_RX_FRAMING_ERR_2,
output [3:0] STAT_RX_FRAMING_ERR_3,
output [3:0] STAT_RX_FRAMING_ERR_4,
output [3:0] STAT_RX_FRAMING_ERR_5,
output [3:0] STAT_RX_FRAMING_ERR_6,
output [3:0] STAT_RX_FRAMING_ERR_7,
output [3:0] STAT_RX_FRAMING_ERR_8,
output [3:0] STAT_RX_FRAMING_ERR_9,
output STAT_RX_FRAMING_ERR_VALID_0,
output STAT_RX_FRAMING_ERR_VALID_1,
output STAT_RX_FRAMING_ERR_VALID_10,
output STAT_RX_FRAMING_ERR_VALID_11,
output STAT_RX_FRAMING_ERR_VALID_12,
output STAT_RX_FRAMING_ERR_VALID_13,
output STAT_RX_FRAMING_ERR_VALID_14,
output STAT_RX_FRAMING_ERR_VALID_15,
output STAT_RX_FRAMING_ERR_VALID_16,
output STAT_RX_FRAMING_ERR_VALID_17,
output STAT_RX_FRAMING_ERR_VALID_18,
output STAT_RX_FRAMING_ERR_VALID_19,
output STAT_RX_FRAMING_ERR_VALID_2,
output STAT_RX_FRAMING_ERR_VALID_3,
output STAT_RX_FRAMING_ERR_VALID_4,
output STAT_RX_FRAMING_ERR_VALID_5,
output STAT_RX_FRAMING_ERR_VALID_6,
output STAT_RX_FRAMING_ERR_VALID_7,
output STAT_RX_FRAMING_ERR_VALID_8,
output STAT_RX_FRAMING_ERR_VALID_9,
output STAT_RX_GOT_SIGNAL_OS,
output STAT_RX_HI_BER,
output STAT_RX_INRANGEERR,
output STAT_RX_INTERNAL_LOCAL_FAULT,
output STAT_RX_JABBER,
output [7:0] STAT_RX_LANE0_VLM_BIP7,
output STAT_RX_LANE0_VLM_BIP7_VALID,
output STAT_RX_LOCAL_FAULT,
output [19:0] STAT_RX_MF_ERR,
output [19:0] STAT_RX_MF_LEN_ERR,
output [19:0] STAT_RX_MF_REPEAT_ERR,
output STAT_RX_MISALIGNED,
output STAT_RX_MULTICAST,
output STAT_RX_OVERSIZE,
output STAT_RX_PACKET_1024_1518_BYTES,
output STAT_RX_PACKET_128_255_BYTES,
output STAT_RX_PACKET_1519_1522_BYTES,
output STAT_RX_PACKET_1523_1548_BYTES,
output STAT_RX_PACKET_1549_2047_BYTES,
output STAT_RX_PACKET_2048_4095_BYTES,
output STAT_RX_PACKET_256_511_BYTES,
output STAT_RX_PACKET_4096_8191_BYTES,
output STAT_RX_PACKET_512_1023_BYTES,
output STAT_RX_PACKET_64_BYTES,
output STAT_RX_PACKET_65_127_BYTES,
output STAT_RX_PACKET_8192_9215_BYTES,
output STAT_RX_PACKET_BAD_FCS,
output STAT_RX_PACKET_LARGE,
output [3:0] STAT_RX_PACKET_SMALL,
output STAT_RX_PAUSE,
output [15:0] STAT_RX_PAUSE_QUANTA0,
output [15:0] STAT_RX_PAUSE_QUANTA1,
output [15:0] STAT_RX_PAUSE_QUANTA2,
output [15:0] STAT_RX_PAUSE_QUANTA3,
output [15:0] STAT_RX_PAUSE_QUANTA4,
output [15:0] STAT_RX_PAUSE_QUANTA5,
output [15:0] STAT_RX_PAUSE_QUANTA6,
output [15:0] STAT_RX_PAUSE_QUANTA7,
output [15:0] STAT_RX_PAUSE_QUANTA8,
output [8:0] STAT_RX_PAUSE_REQ,
output [8:0] STAT_RX_PAUSE_VALID,
output STAT_RX_RECEIVED_LOCAL_FAULT,
output STAT_RX_REMOTE_FAULT,
output STAT_RX_STATUS,
output [3:0] STAT_RX_STOMPED_FCS,
output [19:0] STAT_RX_SYNCED,
output [19:0] STAT_RX_SYNCED_ERR,
output [2:0] STAT_RX_TEST_PATTERN_MISMATCH,
output STAT_RX_TOOLONG,
output [7:0] STAT_RX_TOTAL_BYTES,
output [13:0] STAT_RX_TOTAL_GOOD_BYTES,
output STAT_RX_TOTAL_GOOD_PACKETS,
output [3:0] STAT_RX_TOTAL_PACKETS,
output STAT_RX_TRUNCATED,
output [3:0] STAT_RX_UNDERSIZE,
output STAT_RX_UNICAST,
output STAT_RX_USER_PAUSE,
output STAT_RX_VLAN,
output [19:0] STAT_RX_VL_DEMUXED,
output [4:0] STAT_RX_VL_NUMBER_0,
output [4:0] STAT_RX_VL_NUMBER_1,
output [4:0] STAT_RX_VL_NUMBER_10,
output [4:0] STAT_RX_VL_NUMBER_11,
output [4:0] STAT_RX_VL_NUMBER_12,
output [4:0] STAT_RX_VL_NUMBER_13,
output [4:0] STAT_RX_VL_NUMBER_14,
output [4:0] STAT_RX_VL_NUMBER_15,
output [4:0] STAT_RX_VL_NUMBER_16,
output [4:0] STAT_RX_VL_NUMBER_17,
output [4:0] STAT_RX_VL_NUMBER_18,
output [4:0] STAT_RX_VL_NUMBER_19,
output [4:0] STAT_RX_VL_NUMBER_2,
output [4:0] STAT_RX_VL_NUMBER_3,
output [4:0] STAT_RX_VL_NUMBER_4,
output [4:0] STAT_RX_VL_NUMBER_5,
output [4:0] STAT_RX_VL_NUMBER_6,
output [4:0] STAT_RX_VL_NUMBER_7,
output [4:0] STAT_RX_VL_NUMBER_8,
output [4:0] STAT_RX_VL_NUMBER_9,
output STAT_TX_BAD_FCS,
output STAT_TX_BROADCAST,
output STAT_TX_FRAME_ERROR,
output STAT_TX_LOCAL_FAULT,
output STAT_TX_MULTICAST,
output STAT_TX_PACKET_1024_1518_BYTES,
output STAT_TX_PACKET_128_255_BYTES,
output STAT_TX_PACKET_1519_1522_BYTES,
output STAT_TX_PACKET_1523_1548_BYTES,
output STAT_TX_PACKET_1549_2047_BYTES,
output STAT_TX_PACKET_2048_4095_BYTES,
output STAT_TX_PACKET_256_511_BYTES,
output STAT_TX_PACKET_4096_8191_BYTES,
output STAT_TX_PACKET_512_1023_BYTES,
output STAT_TX_PACKET_64_BYTES,
output STAT_TX_PACKET_65_127_BYTES,
output STAT_TX_PACKET_8192_9215_BYTES,
output STAT_TX_PACKET_LARGE,
output STAT_TX_PACKET_SMALL,
output STAT_TX_PAUSE,
output [8:0] STAT_TX_PAUSE_VALID,
output STAT_TX_PTP_FIFO_READ_ERROR,
output STAT_TX_PTP_FIFO_WRITE_ERROR,
output [6:0] STAT_TX_TOTAL_BYTES,
output [13:0] STAT_TX_TOTAL_GOOD_BYTES,
output STAT_TX_TOTAL_GOOD_PACKETS,
output STAT_TX_TOTAL_PACKETS,
output STAT_TX_UNICAST,
output STAT_TX_USER_PAUSE,
output STAT_TX_VLAN,
output TX_OVFOUT,
output [4:0] TX_PTP_PCSLANE_OUT,
output [79:0] TX_PTP_TSTAMP_OUT,
output [15:0] TX_PTP_TSTAMP_TAG_OUT,
output TX_PTP_TSTAMP_VALID_OUT,
output TX_RDYOUT,
output [15:0] TX_SERDES_ALT_DATA0,
output [15:0] TX_SERDES_ALT_DATA1,
output [15:0] TX_SERDES_ALT_DATA2,
output [15:0] TX_SERDES_ALT_DATA3,
output [63:0] TX_SERDES_DATA0,
output [63:0] TX_SERDES_DATA1,
output [63:0] TX_SERDES_DATA2,
output [63:0] TX_SERDES_DATA3,
output [31:0] TX_SERDES_DATA4,
output [31:0] TX_SERDES_DATA5,
output [31:0] TX_SERDES_DATA6,
output [31:0] TX_SERDES_DATA7,
output [31:0] TX_SERDES_DATA8,
output [31:0] TX_SERDES_DATA9,
output TX_UNFOUT,
input CTL_CAUI4_MODE,
input CTL_RX_CHECK_ETYPE_GCP,
input CTL_RX_CHECK_ETYPE_GPP,
input CTL_RX_CHECK_ETYPE_PCP,
input CTL_RX_CHECK_ETYPE_PPP,
input CTL_RX_CHECK_MCAST_GCP,
input CTL_RX_CHECK_MCAST_GPP,
input CTL_RX_CHECK_MCAST_PCP,
input CTL_RX_CHECK_MCAST_PPP,
input CTL_RX_CHECK_OPCODE_GCP,
input CTL_RX_CHECK_OPCODE_GPP,
input CTL_RX_CHECK_OPCODE_PCP,
input CTL_RX_CHECK_OPCODE_PPP,
input CTL_RX_CHECK_SA_GCP,
input CTL_RX_CHECK_SA_GPP,
input CTL_RX_CHECK_SA_PCP,
input CTL_RX_CHECK_SA_PPP,
input CTL_RX_CHECK_UCAST_GCP,
input CTL_RX_CHECK_UCAST_GPP,
input CTL_RX_CHECK_UCAST_PCP,
input CTL_RX_CHECK_UCAST_PPP,
input CTL_RX_ENABLE,
input CTL_RX_ENABLE_GCP,
input CTL_RX_ENABLE_GPP,
input CTL_RX_ENABLE_PCP,
input CTL_RX_ENABLE_PPP,
input CTL_RX_FORCE_RESYNC,
input [8:0] CTL_RX_PAUSE_ACK,
input [8:0] CTL_RX_PAUSE_ENABLE,
input [79:0] CTL_RX_SYSTEMTIMERIN,
input CTL_RX_TEST_PATTERN,
input CTL_TX_ENABLE,
input CTL_TX_LANE0_VLM_BIP7_OVERRIDE,
input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE,
input [8:0] CTL_TX_PAUSE_ENABLE,
input [15:0] CTL_TX_PAUSE_QUANTA0,
input [15:0] CTL_TX_PAUSE_QUANTA1,
input [15:0] CTL_TX_PAUSE_QUANTA2,
input [15:0] CTL_TX_PAUSE_QUANTA3,
input [15:0] CTL_TX_PAUSE_QUANTA4,
input [15:0] CTL_TX_PAUSE_QUANTA5,
input [15:0] CTL_TX_PAUSE_QUANTA6,
input [15:0] CTL_TX_PAUSE_QUANTA7,
input [15:0] CTL_TX_PAUSE_QUANTA8,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8,
input [8:0] CTL_TX_PAUSE_REQ,
input CTL_TX_PTP_VLANE_ADJUST_MODE,
input CTL_TX_RESEND_PAUSE,
input CTL_TX_SEND_IDLE,
input CTL_TX_SEND_RFI,
input [79:0] CTL_TX_SYSTEMTIMERIN,
input CTL_TX_TEST_PATTERN,
input [9:0] DRP_ADDR,
input DRP_CLK,
input [15:0] DRP_DI,
input DRP_EN,
input DRP_WE,
input RX_CLK,
input RX_RESET,
input [15:0] RX_SERDES_ALT_DATA0,
input [15:0] RX_SERDES_ALT_DATA1,
input [15:0] RX_SERDES_ALT_DATA2,
input [15:0] RX_SERDES_ALT_DATA3,
input [9:0] RX_SERDES_CLK,
input [63:0] RX_SERDES_DATA0,
input [63:0] RX_SERDES_DATA1,
input [63:0] RX_SERDES_DATA2,
input [63:0] RX_SERDES_DATA3,
input [31:0] RX_SERDES_DATA4,
input [31:0] RX_SERDES_DATA5,
input [31:0] RX_SERDES_DATA6,
input [31:0] RX_SERDES_DATA7,
input [31:0] RX_SERDES_DATA8,
input [31:0] RX_SERDES_DATA9,
input [9:0] RX_SERDES_RESET,
input TX_CLK,
input [127:0] TX_DATAIN0,
input [127:0] TX_DATAIN1,
input [127:0] TX_DATAIN2,
input [127:0] TX_DATAIN3,
input TX_ENAIN0,
input TX_ENAIN1,
input TX_ENAIN2,
input TX_ENAIN3,
input TX_EOPIN0,
input TX_EOPIN1,
input TX_EOPIN2,
input TX_EOPIN3,
input TX_ERRIN0,
input TX_ERRIN1,
input TX_ERRIN2,
input TX_ERRIN3,
input [3:0] TX_MTYIN0,
input [3:0] TX_MTYIN1,
input [3:0] TX_MTYIN2,
input [3:0] TX_MTYIN3,
input [1:0] TX_PTP_1588OP_IN,
input [15:0] TX_PTP_CHKSUM_OFFSET_IN,
input [63:0] TX_PTP_RXTSTAMP_IN,
input [15:0] TX_PTP_TAG_FIELD_IN,
input [15:0] TX_PTP_TSTAMP_OFFSET_IN,
input TX_PTP_UPD_CHKSUM_IN,
input TX_RESET,
input TX_SOPIN0,
input TX_SOPIN1,
input TX_SOPIN2,
input TX_SOPIN3
);
// define constants
localparam MODULE_NAME = "CMAC";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [40:1] CTL_PTP_TRANSPCLK_MODE_REG = CTL_PTP_TRANSPCLK_MODE;
localparam [40:1] CTL_RX_CHECK_ACK_REG = CTL_RX_CHECK_ACK;
localparam [40:1] CTL_RX_CHECK_PREAMBLE_REG = CTL_RX_CHECK_PREAMBLE;
localparam [40:1] CTL_RX_CHECK_SFD_REG = CTL_RX_CHECK_SFD;
localparam [40:1] CTL_RX_DELETE_FCS_REG = CTL_RX_DELETE_FCS;
localparam [15:0] CTL_RX_ETYPE_GCP_REG = CTL_RX_ETYPE_GCP;
localparam [15:0] CTL_RX_ETYPE_GPP_REG = CTL_RX_ETYPE_GPP;
localparam [15:0] CTL_RX_ETYPE_PCP_REG = CTL_RX_ETYPE_PCP;
localparam [15:0] CTL_RX_ETYPE_PPP_REG = CTL_RX_ETYPE_PPP;
localparam [40:1] CTL_RX_FORWARD_CONTROL_REG = CTL_RX_FORWARD_CONTROL;
localparam [40:1] CTL_RX_IGNORE_FCS_REG = CTL_RX_IGNORE_FCS;
localparam [14:0] CTL_RX_MAX_PACKET_LEN_REG = CTL_RX_MAX_PACKET_LEN;
localparam [7:0] CTL_RX_MIN_PACKET_LEN_REG = CTL_RX_MIN_PACKET_LEN;
localparam [15:0] CTL_RX_OPCODE_GPP_REG = CTL_RX_OPCODE_GPP;
localparam [15:0] CTL_RX_OPCODE_MAX_GCP_REG = CTL_RX_OPCODE_MAX_GCP;
localparam [15:0] CTL_RX_OPCODE_MAX_PCP_REG = CTL_RX_OPCODE_MAX_PCP;
localparam [15:0] CTL_RX_OPCODE_MIN_GCP_REG = CTL_RX_OPCODE_MIN_GCP;
localparam [15:0] CTL_RX_OPCODE_MIN_PCP_REG = CTL_RX_OPCODE_MIN_PCP;
localparam [15:0] CTL_RX_OPCODE_PPP_REG = CTL_RX_OPCODE_PPP;
localparam [47:0] CTL_RX_PAUSE_DA_MCAST_REG = CTL_RX_PAUSE_DA_MCAST;
localparam [47:0] CTL_RX_PAUSE_DA_UCAST_REG = CTL_RX_PAUSE_DA_UCAST;
localparam [47:0] CTL_RX_PAUSE_SA_REG = CTL_RX_PAUSE_SA;
localparam [40:1] CTL_RX_PROCESS_LFI_REG = CTL_RX_PROCESS_LFI;
localparam [15:0] CTL_RX_VL_LENGTH_MINUS1_REG = CTL_RX_VL_LENGTH_MINUS1;
localparam [63:0] CTL_RX_VL_MARKER_ID0_REG = CTL_RX_VL_MARKER_ID0;
localparam [63:0] CTL_RX_VL_MARKER_ID1_REG = CTL_RX_VL_MARKER_ID1;
localparam [63:0] CTL_RX_VL_MARKER_ID10_REG = CTL_RX_VL_MARKER_ID10;
localparam [63:0] CTL_RX_VL_MARKER_ID11_REG = CTL_RX_VL_MARKER_ID11;
localparam [63:0] CTL_RX_VL_MARKER_ID12_REG = CTL_RX_VL_MARKER_ID12;
localparam [63:0] CTL_RX_VL_MARKER_ID13_REG = CTL_RX_VL_MARKER_ID13;
localparam [63:0] CTL_RX_VL_MARKER_ID14_REG = CTL_RX_VL_MARKER_ID14;
localparam [63:0] CTL_RX_VL_MARKER_ID15_REG = CTL_RX_VL_MARKER_ID15;
localparam [63:0] CTL_RX_VL_MARKER_ID16_REG = CTL_RX_VL_MARKER_ID16;
localparam [63:0] CTL_RX_VL_MARKER_ID17_REG = CTL_RX_VL_MARKER_ID17;
localparam [63:0] CTL_RX_VL_MARKER_ID18_REG = CTL_RX_VL_MARKER_ID18;
localparam [63:0] CTL_RX_VL_MARKER_ID19_REG = CTL_RX_VL_MARKER_ID19;
localparam [63:0] CTL_RX_VL_MARKER_ID2_REG = CTL_RX_VL_MARKER_ID2;
localparam [63:0] CTL_RX_VL_MARKER_ID3_REG = CTL_RX_VL_MARKER_ID3;
localparam [63:0] CTL_RX_VL_MARKER_ID4_REG = CTL_RX_VL_MARKER_ID4;
localparam [63:0] CTL_RX_VL_MARKER_ID5_REG = CTL_RX_VL_MARKER_ID5;
localparam [63:0] CTL_RX_VL_MARKER_ID6_REG = CTL_RX_VL_MARKER_ID6;
localparam [63:0] CTL_RX_VL_MARKER_ID7_REG = CTL_RX_VL_MARKER_ID7;
localparam [63:0] CTL_RX_VL_MARKER_ID8_REG = CTL_RX_VL_MARKER_ID8;
localparam [63:0] CTL_RX_VL_MARKER_ID9_REG = CTL_RX_VL_MARKER_ID9;
localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR;
localparam [47:0] CTL_TX_DA_GPP_REG = CTL_TX_DA_GPP;
localparam [47:0] CTL_TX_DA_PPP_REG = CTL_TX_DA_PPP;
localparam [15:0] CTL_TX_ETHERTYPE_GPP_REG = CTL_TX_ETHERTYPE_GPP;
localparam [15:0] CTL_TX_ETHERTYPE_PPP_REG = CTL_TX_ETHERTYPE_PPP;
localparam [40:1] CTL_TX_FCS_INS_ENABLE_REG = CTL_TX_FCS_INS_ENABLE;
localparam [40:1] CTL_TX_IGNORE_FCS_REG = CTL_TX_IGNORE_FCS;
localparam [15:0] CTL_TX_OPCODE_GPP_REG = CTL_TX_OPCODE_GPP;
localparam [15:0] CTL_TX_OPCODE_PPP_REG = CTL_TX_OPCODE_PPP;
localparam [40:1] CTL_TX_PTP_1STEP_ENABLE_REG = CTL_TX_PTP_1STEP_ENABLE;
localparam [10:0] CTL_TX_PTP_LATENCY_ADJUST_REG = CTL_TX_PTP_LATENCY_ADJUST;
localparam [47:0] CTL_TX_SA_GPP_REG = CTL_TX_SA_GPP;
localparam [47:0] CTL_TX_SA_PPP_REG = CTL_TX_SA_PPP;
localparam [15:0] CTL_TX_VL_LENGTH_MINUS1_REG = CTL_TX_VL_LENGTH_MINUS1;
localparam [63:0] CTL_TX_VL_MARKER_ID0_REG = CTL_TX_VL_MARKER_ID0;
localparam [63:0] CTL_TX_VL_MARKER_ID1_REG = CTL_TX_VL_MARKER_ID1;
localparam [63:0] CTL_TX_VL_MARKER_ID10_REG = CTL_TX_VL_MARKER_ID10;
localparam [63:0] CTL_TX_VL_MARKER_ID11_REG = CTL_TX_VL_MARKER_ID11;
localparam [63:0] CTL_TX_VL_MARKER_ID12_REG = CTL_TX_VL_MARKER_ID12;
localparam [63:0] CTL_TX_VL_MARKER_ID13_REG = CTL_TX_VL_MARKER_ID13;
localparam [63:0] CTL_TX_VL_MARKER_ID14_REG = CTL_TX_VL_MARKER_ID14;
localparam [63:0] CTL_TX_VL_MARKER_ID15_REG = CTL_TX_VL_MARKER_ID15;
localparam [63:0] CTL_TX_VL_MARKER_ID16_REG = CTL_TX_VL_MARKER_ID16;
localparam [63:0] CTL_TX_VL_MARKER_ID17_REG = CTL_TX_VL_MARKER_ID17;
localparam [63:0] CTL_TX_VL_MARKER_ID18_REG = CTL_TX_VL_MARKER_ID18;
localparam [63:0] CTL_TX_VL_MARKER_ID19_REG = CTL_TX_VL_MARKER_ID19;
localparam [63:0] CTL_TX_VL_MARKER_ID2_REG = CTL_TX_VL_MARKER_ID2;
localparam [63:0] CTL_TX_VL_MARKER_ID3_REG = CTL_TX_VL_MARKER_ID3;
localparam [63:0] CTL_TX_VL_MARKER_ID4_REG = CTL_TX_VL_MARKER_ID4;
localparam [63:0] CTL_TX_VL_MARKER_ID5_REG = CTL_TX_VL_MARKER_ID5;
localparam [63:0] CTL_TX_VL_MARKER_ID6_REG = CTL_TX_VL_MARKER_ID6;
localparam [63:0] CTL_TX_VL_MARKER_ID7_REG = CTL_TX_VL_MARKER_ID7;
localparam [63:0] CTL_TX_VL_MARKER_ID8_REG = CTL_TX_VL_MARKER_ID8;
localparam [63:0] CTL_TX_VL_MARKER_ID9_REG = CTL_TX_VL_MARKER_ID9;
localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "CMAC_dr.v"
`endif
wire DRP_RDY_out;
wire RX_ENAOUT0_out;
wire RX_ENAOUT1_out;
wire RX_ENAOUT2_out;
wire RX_ENAOUT3_out;
wire RX_EOPOUT0_out;
wire RX_EOPOUT1_out;
wire RX_EOPOUT2_out;
wire RX_EOPOUT3_out;
wire RX_ERROUT0_out;
wire RX_ERROUT1_out;
wire RX_ERROUT2_out;
wire RX_ERROUT3_out;
wire RX_SOPOUT0_out;
wire RX_SOPOUT1_out;
wire RX_SOPOUT2_out;
wire RX_SOPOUT3_out;
wire STAT_RX_ALIGNED_ERR_out;
wire STAT_RX_ALIGNED_out;
wire STAT_RX_BAD_PREAMBLE_out;
wire STAT_RX_BAD_SFD_out;
wire STAT_RX_BIP_ERR_0_out;
wire STAT_RX_BIP_ERR_10_out;
wire STAT_RX_BIP_ERR_11_out;
wire STAT_RX_BIP_ERR_12_out;
wire STAT_RX_BIP_ERR_13_out;
wire STAT_RX_BIP_ERR_14_out;
wire STAT_RX_BIP_ERR_15_out;
wire STAT_RX_BIP_ERR_16_out;
wire STAT_RX_BIP_ERR_17_out;
wire STAT_RX_BIP_ERR_18_out;
wire STAT_RX_BIP_ERR_19_out;
wire STAT_RX_BIP_ERR_1_out;
wire STAT_RX_BIP_ERR_2_out;
wire STAT_RX_BIP_ERR_3_out;
wire STAT_RX_BIP_ERR_4_out;
wire STAT_RX_BIP_ERR_5_out;
wire STAT_RX_BIP_ERR_6_out;
wire STAT_RX_BIP_ERR_7_out;
wire STAT_RX_BIP_ERR_8_out;
wire STAT_RX_BIP_ERR_9_out;
wire STAT_RX_BROADCAST_out;
wire STAT_RX_FRAMING_ERR_VALID_0_out;
wire STAT_RX_FRAMING_ERR_VALID_10_out;
wire STAT_RX_FRAMING_ERR_VALID_11_out;
wire STAT_RX_FRAMING_ERR_VALID_12_out;
wire STAT_RX_FRAMING_ERR_VALID_13_out;
wire STAT_RX_FRAMING_ERR_VALID_14_out;
wire STAT_RX_FRAMING_ERR_VALID_15_out;
wire STAT_RX_FRAMING_ERR_VALID_16_out;
wire STAT_RX_FRAMING_ERR_VALID_17_out;
wire STAT_RX_FRAMING_ERR_VALID_18_out;
wire STAT_RX_FRAMING_ERR_VALID_19_out;
wire STAT_RX_FRAMING_ERR_VALID_1_out;
wire STAT_RX_FRAMING_ERR_VALID_2_out;
wire STAT_RX_FRAMING_ERR_VALID_3_out;
wire STAT_RX_FRAMING_ERR_VALID_4_out;
wire STAT_RX_FRAMING_ERR_VALID_5_out;
wire STAT_RX_FRAMING_ERR_VALID_6_out;
wire STAT_RX_FRAMING_ERR_VALID_7_out;
wire STAT_RX_FRAMING_ERR_VALID_8_out;
wire STAT_RX_FRAMING_ERR_VALID_9_out;
wire STAT_RX_GOT_SIGNAL_OS_out;
wire STAT_RX_HI_BER_out;
wire STAT_RX_INRANGEERR_out;
wire STAT_RX_INTERNAL_LOCAL_FAULT_out;
wire STAT_RX_JABBER_out;
wire STAT_RX_LANE0_VLM_BIP7_VALID_out;
wire STAT_RX_LOCAL_FAULT_out;
wire STAT_RX_MISALIGNED_out;
wire STAT_RX_MULTICAST_out;
wire STAT_RX_OVERSIZE_out;
wire STAT_RX_PACKET_1024_1518_BYTES_out;
wire STAT_RX_PACKET_128_255_BYTES_out;
wire STAT_RX_PACKET_1519_1522_BYTES_out;
wire STAT_RX_PACKET_1523_1548_BYTES_out;
wire STAT_RX_PACKET_1549_2047_BYTES_out;
wire STAT_RX_PACKET_2048_4095_BYTES_out;
wire STAT_RX_PACKET_256_511_BYTES_out;
wire STAT_RX_PACKET_4096_8191_BYTES_out;
wire STAT_RX_PACKET_512_1023_BYTES_out;
wire STAT_RX_PACKET_64_BYTES_out;
wire STAT_RX_PACKET_65_127_BYTES_out;
wire STAT_RX_PACKET_8192_9215_BYTES_out;
wire STAT_RX_PACKET_BAD_FCS_out;
wire STAT_RX_PACKET_LARGE_out;
wire STAT_RX_PAUSE_out;
wire STAT_RX_RECEIVED_LOCAL_FAULT_out;
wire STAT_RX_REMOTE_FAULT_out;
wire STAT_RX_STATUS_out;
wire STAT_RX_TOOLONG_out;
wire STAT_RX_TOTAL_GOOD_PACKETS_out;
wire STAT_RX_TRUNCATED_out;
wire STAT_RX_UNICAST_out;
wire STAT_RX_USER_PAUSE_out;
wire STAT_RX_VLAN_out;
wire STAT_TX_BAD_FCS_out;
wire STAT_TX_BROADCAST_out;
wire STAT_TX_FRAME_ERROR_out;
wire STAT_TX_LOCAL_FAULT_out;
wire STAT_TX_MULTICAST_out;
wire STAT_TX_PACKET_1024_1518_BYTES_out;
wire STAT_TX_PACKET_128_255_BYTES_out;
wire STAT_TX_PACKET_1519_1522_BYTES_out;
wire STAT_TX_PACKET_1523_1548_BYTES_out;
wire STAT_TX_PACKET_1549_2047_BYTES_out;
wire STAT_TX_PACKET_2048_4095_BYTES_out;
wire STAT_TX_PACKET_256_511_BYTES_out;
wire STAT_TX_PACKET_4096_8191_BYTES_out;
wire STAT_TX_PACKET_512_1023_BYTES_out;
wire STAT_TX_PACKET_64_BYTES_out;
wire STAT_TX_PACKET_65_127_BYTES_out;
wire STAT_TX_PACKET_8192_9215_BYTES_out;
wire STAT_TX_PACKET_LARGE_out;
wire STAT_TX_PACKET_SMALL_out;
wire STAT_TX_PAUSE_out;
wire STAT_TX_PTP_FIFO_READ_ERROR_out;
wire STAT_TX_PTP_FIFO_WRITE_ERROR_out;
wire STAT_TX_TOTAL_GOOD_PACKETS_out;
wire STAT_TX_TOTAL_PACKETS_out;
wire STAT_TX_UNICAST_out;
wire STAT_TX_USER_PAUSE_out;
wire STAT_TX_VLAN_out;
wire TX_OVFOUT_out;
wire TX_PTP_TSTAMP_VALID_OUT_out;
wire TX_RDYOUT_out;
wire TX_UNFOUT_out;
wire [127:0] RX_DATAOUT0_out;
wire [127:0] RX_DATAOUT1_out;
wire [127:0] RX_DATAOUT2_out;
wire [127:0] RX_DATAOUT3_out;
wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_out;
wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_out;
wire [15:0] DRP_DO_out;
wire [15:0] STAT_RX_PAUSE_QUANTA0_out;
wire [15:0] STAT_RX_PAUSE_QUANTA1_out;
wire [15:0] STAT_RX_PAUSE_QUANTA2_out;
wire [15:0] STAT_RX_PAUSE_QUANTA3_out;
wire [15:0] STAT_RX_PAUSE_QUANTA4_out;
wire [15:0] STAT_RX_PAUSE_QUANTA5_out;
wire [15:0] STAT_RX_PAUSE_QUANTA6_out;
wire [15:0] STAT_RX_PAUSE_QUANTA7_out;
wire [15:0] STAT_RX_PAUSE_QUANTA8_out;
wire [15:0] TX_PTP_TSTAMP_TAG_OUT_out;
wire [15:0] TX_SERDES_ALT_DATA0_out;
wire [15:0] TX_SERDES_ALT_DATA1_out;
wire [15:0] TX_SERDES_ALT_DATA2_out;
wire [15:0] TX_SERDES_ALT_DATA3_out;
wire [194:0] SCAN_OUT_out;
wire [19:0] STAT_RX_BLOCK_LOCK_out;
wire [19:0] STAT_RX_MF_ERR_out;
wire [19:0] STAT_RX_MF_LEN_ERR_out;
wire [19:0] STAT_RX_MF_REPEAT_ERR_out;
wire [19:0] STAT_RX_SYNCED_ERR_out;
wire [19:0] STAT_RX_SYNCED_out;
wire [19:0] STAT_RX_VL_DEMUXED_out;
wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_out;
wire [31:0] TX_SERDES_DATA4_out;
wire [31:0] TX_SERDES_DATA5_out;
wire [31:0] TX_SERDES_DATA6_out;
wire [31:0] TX_SERDES_DATA7_out;
wire [31:0] TX_SERDES_DATA8_out;
wire [31:0] TX_SERDES_DATA9_out;
wire [3:0] RX_MTYOUT0_out;
wire [3:0] RX_MTYOUT1_out;
wire [3:0] RX_MTYOUT2_out;
wire [3:0] RX_MTYOUT3_out;
wire [3:0] STAT_RX_BAD_FCS_out;
wire [3:0] STAT_RX_FRAGMENT_out;
wire [3:0] STAT_RX_FRAMING_ERR_0_out;
wire [3:0] STAT_RX_FRAMING_ERR_10_out;
wire [3:0] STAT_RX_FRAMING_ERR_11_out;
wire [3:0] STAT_RX_FRAMING_ERR_12_out;
wire [3:0] STAT_RX_FRAMING_ERR_13_out;
wire [3:0] STAT_RX_FRAMING_ERR_14_out;
wire [3:0] STAT_RX_FRAMING_ERR_15_out;
wire [3:0] STAT_RX_FRAMING_ERR_16_out;
wire [3:0] STAT_RX_FRAMING_ERR_17_out;
wire [3:0] STAT_RX_FRAMING_ERR_18_out;
wire [3:0] STAT_RX_FRAMING_ERR_19_out;
wire [3:0] STAT_RX_FRAMING_ERR_1_out;
wire [3:0] STAT_RX_FRAMING_ERR_2_out;
wire [3:0] STAT_RX_FRAMING_ERR_3_out;
wire [3:0] STAT_RX_FRAMING_ERR_4_out;
wire [3:0] STAT_RX_FRAMING_ERR_5_out;
wire [3:0] STAT_RX_FRAMING_ERR_6_out;
wire [3:0] STAT_RX_FRAMING_ERR_7_out;
wire [3:0] STAT_RX_FRAMING_ERR_8_out;
wire [3:0] STAT_RX_FRAMING_ERR_9_out;
wire [3:0] STAT_RX_PACKET_SMALL_out;
wire [3:0] STAT_RX_STOMPED_FCS_out;
wire [3:0] STAT_RX_TOTAL_PACKETS_out;
wire [3:0] STAT_RX_UNDERSIZE_out;
wire [4:0] RX_PTP_PCSLANE_OUT_out;
wire [4:0] STAT_RX_VL_NUMBER_0_out;
wire [4:0] STAT_RX_VL_NUMBER_10_out;
wire [4:0] STAT_RX_VL_NUMBER_11_out;
wire [4:0] STAT_RX_VL_NUMBER_12_out;
wire [4:0] STAT_RX_VL_NUMBER_13_out;
wire [4:0] STAT_RX_VL_NUMBER_14_out;
wire [4:0] STAT_RX_VL_NUMBER_15_out;
wire [4:0] STAT_RX_VL_NUMBER_16_out;
wire [4:0] STAT_RX_VL_NUMBER_17_out;
wire [4:0] STAT_RX_VL_NUMBER_18_out;
wire [4:0] STAT_RX_VL_NUMBER_19_out;
wire [4:0] STAT_RX_VL_NUMBER_1_out;
wire [4:0] STAT_RX_VL_NUMBER_2_out;
wire [4:0] STAT_RX_VL_NUMBER_3_out;
wire [4:0] STAT_RX_VL_NUMBER_4_out;
wire [4:0] STAT_RX_VL_NUMBER_5_out;
wire [4:0] STAT_RX_VL_NUMBER_6_out;
wire [4:0] STAT_RX_VL_NUMBER_7_out;
wire [4:0] STAT_RX_VL_NUMBER_8_out;
wire [4:0] STAT_RX_VL_NUMBER_9_out;
wire [4:0] TX_PTP_PCSLANE_OUT_out;
wire [63:0] TX_SERDES_DATA0_out;
wire [63:0] TX_SERDES_DATA1_out;
wire [63:0] TX_SERDES_DATA2_out;
wire [63:0] TX_SERDES_DATA3_out;
wire [6:0] RX_LANE_ALIGNER_FILL_0_out;
wire [6:0] RX_LANE_ALIGNER_FILL_10_out;
wire [6:0] RX_LANE_ALIGNER_FILL_11_out;
wire [6:0] RX_LANE_ALIGNER_FILL_12_out;
wire [6:0] RX_LANE_ALIGNER_FILL_13_out;
wire [6:0] RX_LANE_ALIGNER_FILL_14_out;
wire [6:0] RX_LANE_ALIGNER_FILL_15_out;
wire [6:0] RX_LANE_ALIGNER_FILL_16_out;
wire [6:0] RX_LANE_ALIGNER_FILL_17_out;
wire [6:0] RX_LANE_ALIGNER_FILL_18_out;
wire [6:0] RX_LANE_ALIGNER_FILL_19_out;
wire [6:0] RX_LANE_ALIGNER_FILL_1_out;
wire [6:0] RX_LANE_ALIGNER_FILL_2_out;
wire [6:0] RX_LANE_ALIGNER_FILL_3_out;
wire [6:0] RX_LANE_ALIGNER_FILL_4_out;
wire [6:0] RX_LANE_ALIGNER_FILL_5_out;
wire [6:0] RX_LANE_ALIGNER_FILL_6_out;
wire [6:0] RX_LANE_ALIGNER_FILL_7_out;
wire [6:0] RX_LANE_ALIGNER_FILL_8_out;
wire [6:0] RX_LANE_ALIGNER_FILL_9_out;
wire [6:0] STAT_RX_BAD_CODE_out;
wire [6:0] STAT_TX_TOTAL_BYTES_out;
wire [79:0] RX_PTP_TSTAMP_OUT_out;
wire [79:0] TX_PTP_TSTAMP_OUT_out;
wire [7:0] STAT_RX_LANE0_VLM_BIP7_out;
wire [7:0] STAT_RX_TOTAL_BYTES_out;
wire [8:0] STAT_RX_PAUSE_REQ_out;
wire [8:0] STAT_RX_PAUSE_VALID_out;
wire [8:0] STAT_TX_PAUSE_VALID_out;
wire DRP_RDY_delay;
wire RX_ENAOUT0_delay;
wire RX_ENAOUT1_delay;
wire RX_ENAOUT2_delay;
wire RX_ENAOUT3_delay;
wire RX_EOPOUT0_delay;
wire RX_EOPOUT1_delay;
wire RX_EOPOUT2_delay;
wire RX_EOPOUT3_delay;
wire RX_ERROUT0_delay;
wire RX_ERROUT1_delay;
wire RX_ERROUT2_delay;
wire RX_ERROUT3_delay;
wire RX_SOPOUT0_delay;
wire RX_SOPOUT1_delay;
wire RX_SOPOUT2_delay;
wire RX_SOPOUT3_delay;
wire STAT_RX_ALIGNED_ERR_delay;
wire STAT_RX_ALIGNED_delay;
wire STAT_RX_BAD_PREAMBLE_delay;
wire STAT_RX_BAD_SFD_delay;
wire STAT_RX_BIP_ERR_0_delay;
wire STAT_RX_BIP_ERR_10_delay;
wire STAT_RX_BIP_ERR_11_delay;
wire STAT_RX_BIP_ERR_12_delay;
wire STAT_RX_BIP_ERR_13_delay;
wire STAT_RX_BIP_ERR_14_delay;
wire STAT_RX_BIP_ERR_15_delay;
wire STAT_RX_BIP_ERR_16_delay;
wire STAT_RX_BIP_ERR_17_delay;
wire STAT_RX_BIP_ERR_18_delay;
wire STAT_RX_BIP_ERR_19_delay;
wire STAT_RX_BIP_ERR_1_delay;
wire STAT_RX_BIP_ERR_2_delay;
wire STAT_RX_BIP_ERR_3_delay;
wire STAT_RX_BIP_ERR_4_delay;
wire STAT_RX_BIP_ERR_5_delay;
wire STAT_RX_BIP_ERR_6_delay;
wire STAT_RX_BIP_ERR_7_delay;
wire STAT_RX_BIP_ERR_8_delay;
wire STAT_RX_BIP_ERR_9_delay;
wire STAT_RX_BROADCAST_delay;
wire STAT_RX_FRAMING_ERR_VALID_0_delay;
wire STAT_RX_FRAMING_ERR_VALID_10_delay;
wire STAT_RX_FRAMING_ERR_VALID_11_delay;
wire STAT_RX_FRAMING_ERR_VALID_12_delay;
wire STAT_RX_FRAMING_ERR_VALID_13_delay;
wire STAT_RX_FRAMING_ERR_VALID_14_delay;
wire STAT_RX_FRAMING_ERR_VALID_15_delay;
wire STAT_RX_FRAMING_ERR_VALID_16_delay;
wire STAT_RX_FRAMING_ERR_VALID_17_delay;
wire STAT_RX_FRAMING_ERR_VALID_18_delay;
wire STAT_RX_FRAMING_ERR_VALID_19_delay;
wire STAT_RX_FRAMING_ERR_VALID_1_delay;
wire STAT_RX_FRAMING_ERR_VALID_2_delay;
wire STAT_RX_FRAMING_ERR_VALID_3_delay;
wire STAT_RX_FRAMING_ERR_VALID_4_delay;
wire STAT_RX_FRAMING_ERR_VALID_5_delay;
wire STAT_RX_FRAMING_ERR_VALID_6_delay;
wire STAT_RX_FRAMING_ERR_VALID_7_delay;
wire STAT_RX_FRAMING_ERR_VALID_8_delay;
wire STAT_RX_FRAMING_ERR_VALID_9_delay;
wire STAT_RX_GOT_SIGNAL_OS_delay;
wire STAT_RX_HI_BER_delay;
wire STAT_RX_INRANGEERR_delay;
wire STAT_RX_INTERNAL_LOCAL_FAULT_delay;
wire STAT_RX_JABBER_delay;
wire STAT_RX_LANE0_VLM_BIP7_VALID_delay;
wire STAT_RX_LOCAL_FAULT_delay;
wire STAT_RX_MISALIGNED_delay;
wire STAT_RX_MULTICAST_delay;
wire STAT_RX_OVERSIZE_delay;
wire STAT_RX_PACKET_1024_1518_BYTES_delay;
wire STAT_RX_PACKET_128_255_BYTES_delay;
wire STAT_RX_PACKET_1519_1522_BYTES_delay;
wire STAT_RX_PACKET_1523_1548_BYTES_delay;
wire STAT_RX_PACKET_1549_2047_BYTES_delay;
wire STAT_RX_PACKET_2048_4095_BYTES_delay;
wire STAT_RX_PACKET_256_511_BYTES_delay;
wire STAT_RX_PACKET_4096_8191_BYTES_delay;
wire STAT_RX_PACKET_512_1023_BYTES_delay;
wire STAT_RX_PACKET_64_BYTES_delay;
wire STAT_RX_PACKET_65_127_BYTES_delay;
wire STAT_RX_PACKET_8192_9215_BYTES_delay;
wire STAT_RX_PACKET_BAD_FCS_delay;
wire STAT_RX_PACKET_LARGE_delay;
wire STAT_RX_PAUSE_delay;
wire STAT_RX_RECEIVED_LOCAL_FAULT_delay;
wire STAT_RX_REMOTE_FAULT_delay;
wire STAT_RX_STATUS_delay;
wire STAT_RX_TOOLONG_delay;
wire STAT_RX_TOTAL_GOOD_PACKETS_delay;
wire STAT_RX_TRUNCATED_delay;
wire STAT_RX_UNICAST_delay;
wire STAT_RX_USER_PAUSE_delay;
wire STAT_RX_VLAN_delay;
wire STAT_TX_BAD_FCS_delay;
wire STAT_TX_BROADCAST_delay;
wire STAT_TX_FRAME_ERROR_delay;
wire STAT_TX_LOCAL_FAULT_delay;
wire STAT_TX_MULTICAST_delay;
wire STAT_TX_PACKET_1024_1518_BYTES_delay;
wire STAT_TX_PACKET_128_255_BYTES_delay;
wire STAT_TX_PACKET_1519_1522_BYTES_delay;
wire STAT_TX_PACKET_1523_1548_BYTES_delay;
wire STAT_TX_PACKET_1549_2047_BYTES_delay;
wire STAT_TX_PACKET_2048_4095_BYTES_delay;
wire STAT_TX_PACKET_256_511_BYTES_delay;
wire STAT_TX_PACKET_4096_8191_BYTES_delay;
wire STAT_TX_PACKET_512_1023_BYTES_delay;
wire STAT_TX_PACKET_64_BYTES_delay;
wire STAT_TX_PACKET_65_127_BYTES_delay;
wire STAT_TX_PACKET_8192_9215_BYTES_delay;
wire STAT_TX_PACKET_LARGE_delay;
wire STAT_TX_PACKET_SMALL_delay;
wire STAT_TX_PAUSE_delay;
wire STAT_TX_PTP_FIFO_READ_ERROR_delay;
wire STAT_TX_PTP_FIFO_WRITE_ERROR_delay;
wire STAT_TX_TOTAL_GOOD_PACKETS_delay;
wire STAT_TX_TOTAL_PACKETS_delay;
wire STAT_TX_UNICAST_delay;
wire STAT_TX_USER_PAUSE_delay;
wire STAT_TX_VLAN_delay;
wire TX_OVFOUT_delay;
wire TX_PTP_TSTAMP_VALID_OUT_delay;
wire TX_RDYOUT_delay;
wire TX_UNFOUT_delay;
wire [127:0] RX_DATAOUT0_delay;
wire [127:0] RX_DATAOUT1_delay;
wire [127:0] RX_DATAOUT2_delay;
wire [127:0] RX_DATAOUT3_delay;
wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_delay;
wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_delay;
wire [15:0] DRP_DO_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA0_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA1_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA2_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA3_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA4_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA5_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA6_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA7_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA8_delay;
wire [15:0] TX_PTP_TSTAMP_TAG_OUT_delay;
wire [15:0] TX_SERDES_ALT_DATA0_delay;
wire [15:0] TX_SERDES_ALT_DATA1_delay;
wire [15:0] TX_SERDES_ALT_DATA2_delay;
wire [15:0] TX_SERDES_ALT_DATA3_delay;
wire [19:0] STAT_RX_BLOCK_LOCK_delay;
wire [19:0] STAT_RX_MF_ERR_delay;
wire [19:0] STAT_RX_MF_LEN_ERR_delay;
wire [19:0] STAT_RX_MF_REPEAT_ERR_delay;
wire [19:0] STAT_RX_SYNCED_ERR_delay;
wire [19:0] STAT_RX_SYNCED_delay;
wire [19:0] STAT_RX_VL_DEMUXED_delay;
wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_delay;
wire [31:0] TX_SERDES_DATA4_delay;
wire [31:0] TX_SERDES_DATA5_delay;
wire [31:0] TX_SERDES_DATA6_delay;
wire [31:0] TX_SERDES_DATA7_delay;
wire [31:0] TX_SERDES_DATA8_delay;
wire [31:0] TX_SERDES_DATA9_delay;
wire [3:0] RX_MTYOUT0_delay;
wire [3:0] RX_MTYOUT1_delay;
wire [3:0] RX_MTYOUT2_delay;
wire [3:0] RX_MTYOUT3_delay;
wire [3:0] STAT_RX_BAD_FCS_delay;
wire [3:0] STAT_RX_FRAGMENT_delay;
wire [3:0] STAT_RX_FRAMING_ERR_0_delay;
wire [3:0] STAT_RX_FRAMING_ERR_10_delay;
wire [3:0] STAT_RX_FRAMING_ERR_11_delay;
wire [3:0] STAT_RX_FRAMING_ERR_12_delay;
wire [3:0] STAT_RX_FRAMING_ERR_13_delay;
wire [3:0] STAT_RX_FRAMING_ERR_14_delay;
wire [3:0] STAT_RX_FRAMING_ERR_15_delay;
wire [3:0] STAT_RX_FRAMING_ERR_16_delay;
wire [3:0] STAT_RX_FRAMING_ERR_17_delay;
wire [3:0] STAT_RX_FRAMING_ERR_18_delay;
wire [3:0] STAT_RX_FRAMING_ERR_19_delay;
wire [3:0] STAT_RX_FRAMING_ERR_1_delay;
wire [3:0] STAT_RX_FRAMING_ERR_2_delay;
wire [3:0] STAT_RX_FRAMING_ERR_3_delay;
wire [3:0] STAT_RX_FRAMING_ERR_4_delay;
wire [3:0] STAT_RX_FRAMING_ERR_5_delay;
wire [3:0] STAT_RX_FRAMING_ERR_6_delay;
wire [3:0] STAT_RX_FRAMING_ERR_7_delay;
wire [3:0] STAT_RX_FRAMING_ERR_8_delay;
wire [3:0] STAT_RX_FRAMING_ERR_9_delay;
wire [3:0] STAT_RX_PACKET_SMALL_delay;
wire [3:0] STAT_RX_STOMPED_FCS_delay;
wire [3:0] STAT_RX_TOTAL_PACKETS_delay;
wire [3:0] STAT_RX_UNDERSIZE_delay;
wire [4:0] RX_PTP_PCSLANE_OUT_delay;
wire [4:0] STAT_RX_VL_NUMBER_0_delay;
wire [4:0] STAT_RX_VL_NUMBER_10_delay;
wire [4:0] STAT_RX_VL_NUMBER_11_delay;
wire [4:0] STAT_RX_VL_NUMBER_12_delay;
wire [4:0] STAT_RX_VL_NUMBER_13_delay;
wire [4:0] STAT_RX_VL_NUMBER_14_delay;
wire [4:0] STAT_RX_VL_NUMBER_15_delay;
wire [4:0] STAT_RX_VL_NUMBER_16_delay;
wire [4:0] STAT_RX_VL_NUMBER_17_delay;
wire [4:0] STAT_RX_VL_NUMBER_18_delay;
wire [4:0] STAT_RX_VL_NUMBER_19_delay;
wire [4:0] STAT_RX_VL_NUMBER_1_delay;
wire [4:0] STAT_RX_VL_NUMBER_2_delay;
wire [4:0] STAT_RX_VL_NUMBER_3_delay;
wire [4:0] STAT_RX_VL_NUMBER_4_delay;
wire [4:0] STAT_RX_VL_NUMBER_5_delay;
wire [4:0] STAT_RX_VL_NUMBER_6_delay;
wire [4:0] STAT_RX_VL_NUMBER_7_delay;
wire [4:0] STAT_RX_VL_NUMBER_8_delay;
wire [4:0] STAT_RX_VL_NUMBER_9_delay;
wire [4:0] TX_PTP_PCSLANE_OUT_delay;
wire [63:0] TX_SERDES_DATA0_delay;
wire [63:0] TX_SERDES_DATA1_delay;
wire [63:0] TX_SERDES_DATA2_delay;
wire [63:0] TX_SERDES_DATA3_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_0_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_10_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_11_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_12_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_13_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_14_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_15_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_16_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_17_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_18_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_19_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_1_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_2_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_3_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_4_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_5_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_6_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_7_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_8_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_9_delay;
wire [6:0] STAT_RX_BAD_CODE_delay;
wire [6:0] STAT_TX_TOTAL_BYTES_delay;
wire [79:0] RX_PTP_TSTAMP_OUT_delay;
wire [79:0] TX_PTP_TSTAMP_OUT_delay;
wire [7:0] STAT_RX_LANE0_VLM_BIP7_delay;
wire [7:0] STAT_RX_TOTAL_BYTES_delay;
wire [8:0] STAT_RX_PAUSE_REQ_delay;
wire [8:0] STAT_RX_PAUSE_VALID_delay;
wire [8:0] STAT_TX_PAUSE_VALID_delay;
wire CTL_CAUI4_MODE_in;
wire CTL_RX_CHECK_ETYPE_GCP_in;
wire CTL_RX_CHECK_ETYPE_GPP_in;
wire CTL_RX_CHECK_ETYPE_PCP_in;
wire CTL_RX_CHECK_ETYPE_PPP_in;
wire CTL_RX_CHECK_MCAST_GCP_in;
wire CTL_RX_CHECK_MCAST_GPP_in;
wire CTL_RX_CHECK_MCAST_PCP_in;
wire CTL_RX_CHECK_MCAST_PPP_in;
wire CTL_RX_CHECK_OPCODE_GCP_in;
wire CTL_RX_CHECK_OPCODE_GPP_in;
wire CTL_RX_CHECK_OPCODE_PCP_in;
wire CTL_RX_CHECK_OPCODE_PPP_in;
wire CTL_RX_CHECK_SA_GCP_in;
wire CTL_RX_CHECK_SA_GPP_in;
wire CTL_RX_CHECK_SA_PCP_in;
wire CTL_RX_CHECK_SA_PPP_in;
wire CTL_RX_CHECK_UCAST_GCP_in;
wire CTL_RX_CHECK_UCAST_GPP_in;
wire CTL_RX_CHECK_UCAST_PCP_in;
wire CTL_RX_CHECK_UCAST_PPP_in;
wire CTL_RX_ENABLE_GCP_in;
wire CTL_RX_ENABLE_GPP_in;
wire CTL_RX_ENABLE_PCP_in;
wire CTL_RX_ENABLE_PPP_in;
wire CTL_RX_ENABLE_in;
wire CTL_RX_FORCE_RESYNC_in;
wire CTL_RX_TEST_PATTERN_in;
wire CTL_TX_ENABLE_in;
wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in;
wire CTL_TX_PTP_VLANE_ADJUST_MODE_in;
wire CTL_TX_RESEND_PAUSE_in;
wire CTL_TX_SEND_IDLE_in;
wire CTL_TX_SEND_RFI_in;
wire CTL_TX_TEST_PATTERN_in;
wire DRP_CLK_in;
wire DRP_EN_in;
wire DRP_WE_in;
wire RX_CLK_in;
wire RX_RESET_in;
wire SCAN_EN_N_in;
wire TEST_MODE_N_in;
wire TEST_RESET_in;
wire TX_CLK_in;
wire TX_ENAIN0_in;
wire TX_ENAIN1_in;
wire TX_ENAIN2_in;
wire TX_ENAIN3_in;
wire TX_EOPIN0_in;
wire TX_EOPIN1_in;
wire TX_EOPIN2_in;
wire TX_EOPIN3_in;
wire TX_ERRIN0_in;
wire TX_ERRIN1_in;
wire TX_ERRIN2_in;
wire TX_ERRIN3_in;
wire TX_PTP_UPD_CHKSUM_IN_in;
wire TX_RESET_in;
wire TX_SOPIN0_in;
wire TX_SOPIN1_in;
wire TX_SOPIN2_in;
wire TX_SOPIN3_in;
wire [127:0] TX_DATAIN0_in;
wire [127:0] TX_DATAIN1_in;
wire [127:0] TX_DATAIN2_in;
wire [127:0] TX_DATAIN3_in;
wire [15:0] CTL_TX_PAUSE_QUANTA0_in;
wire [15:0] CTL_TX_PAUSE_QUANTA1_in;
wire [15:0] CTL_TX_PAUSE_QUANTA2_in;
wire [15:0] CTL_TX_PAUSE_QUANTA3_in;
wire [15:0] CTL_TX_PAUSE_QUANTA4_in;
wire [15:0] CTL_TX_PAUSE_QUANTA5_in;
wire [15:0] CTL_TX_PAUSE_QUANTA6_in;
wire [15:0] CTL_TX_PAUSE_QUANTA7_in;
wire [15:0] CTL_TX_PAUSE_QUANTA8_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_in;
wire [15:0] DRP_DI_in;
wire [15:0] RX_SERDES_ALT_DATA0_in;
wire [15:0] RX_SERDES_ALT_DATA1_in;
wire [15:0] RX_SERDES_ALT_DATA2_in;
wire [15:0] RX_SERDES_ALT_DATA3_in;
wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_in;
wire [15:0] TX_PTP_TAG_FIELD_IN_in;
wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_in;
wire [194:0] SCAN_IN_in;
wire [1:0] TX_PTP_1588OP_IN_in;
wire [31:0] RX_SERDES_DATA4_in;
wire [31:0] RX_SERDES_DATA5_in;
wire [31:0] RX_SERDES_DATA6_in;
wire [31:0] RX_SERDES_DATA7_in;
wire [31:0] RX_SERDES_DATA8_in;
wire [31:0] RX_SERDES_DATA9_in;
wire [3:0] TX_MTYIN0_in;
wire [3:0] TX_MTYIN1_in;
wire [3:0] TX_MTYIN2_in;
wire [3:0] TX_MTYIN3_in;
wire [63:0] RX_SERDES_DATA0_in;
wire [63:0] RX_SERDES_DATA1_in;
wire [63:0] RX_SERDES_DATA2_in;
wire [63:0] RX_SERDES_DATA3_in;
wire [63:0] TX_PTP_RXTSTAMP_IN_in;
wire [79:0] CTL_RX_SYSTEMTIMERIN_in;
wire [79:0] CTL_TX_SYSTEMTIMERIN_in;
wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in;
wire [8:0] CTL_RX_PAUSE_ACK_in;
wire [8:0] CTL_RX_PAUSE_ENABLE_in;
wire [8:0] CTL_TX_PAUSE_ENABLE_in;
wire [8:0] CTL_TX_PAUSE_REQ_in;
wire [9:0] DRP_ADDR_in;
wire [9:0] RX_SERDES_CLK_in;
wire [9:0] RX_SERDES_RESET_in;
wire CTL_CAUI4_MODE_delay;
wire CTL_RX_CHECK_ETYPE_GCP_delay;
wire CTL_RX_CHECK_ETYPE_GPP_delay;
wire CTL_RX_CHECK_ETYPE_PCP_delay;
wire CTL_RX_CHECK_ETYPE_PPP_delay;
wire CTL_RX_CHECK_MCAST_GCP_delay;
wire CTL_RX_CHECK_MCAST_GPP_delay;
wire CTL_RX_CHECK_MCAST_PCP_delay;
wire CTL_RX_CHECK_MCAST_PPP_delay;
wire CTL_RX_CHECK_OPCODE_GCP_delay;
wire CTL_RX_CHECK_OPCODE_GPP_delay;
wire CTL_RX_CHECK_OPCODE_PCP_delay;
wire CTL_RX_CHECK_OPCODE_PPP_delay;
wire CTL_RX_CHECK_SA_GCP_delay;
wire CTL_RX_CHECK_SA_GPP_delay;
wire CTL_RX_CHECK_SA_PCP_delay;
wire CTL_RX_CHECK_SA_PPP_delay;
wire CTL_RX_CHECK_UCAST_GCP_delay;
wire CTL_RX_CHECK_UCAST_GPP_delay;
wire CTL_RX_CHECK_UCAST_PCP_delay;
wire CTL_RX_CHECK_UCAST_PPP_delay;
wire CTL_RX_ENABLE_GCP_delay;
wire CTL_RX_ENABLE_GPP_delay;
wire CTL_RX_ENABLE_PCP_delay;
wire CTL_RX_ENABLE_PPP_delay;
wire CTL_RX_ENABLE_delay;
wire CTL_RX_FORCE_RESYNC_delay;
wire CTL_RX_TEST_PATTERN_delay;
wire CTL_TX_ENABLE_delay;
wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay;
wire CTL_TX_PTP_VLANE_ADJUST_MODE_delay;
wire CTL_TX_RESEND_PAUSE_delay;
wire CTL_TX_SEND_IDLE_delay;
wire CTL_TX_SEND_RFI_delay;
wire CTL_TX_TEST_PATTERN_delay;
wire DRP_CLK_delay;
wire DRP_EN_delay;
wire DRP_WE_delay;
wire RX_CLK_delay;
wire RX_RESET_delay;
wire TX_CLK_delay;
wire TX_ENAIN0_delay;
wire TX_ENAIN1_delay;
wire TX_ENAIN2_delay;
wire TX_ENAIN3_delay;
wire TX_EOPIN0_delay;
wire TX_EOPIN1_delay;
wire TX_EOPIN2_delay;
wire TX_EOPIN3_delay;
wire TX_ERRIN0_delay;
wire TX_ERRIN1_delay;
wire TX_ERRIN2_delay;
wire TX_ERRIN3_delay;
wire TX_PTP_UPD_CHKSUM_IN_delay;
wire TX_RESET_delay;
wire TX_SOPIN0_delay;
wire TX_SOPIN1_delay;
wire TX_SOPIN2_delay;
wire TX_SOPIN3_delay;
wire [127:0] TX_DATAIN0_delay;
wire [127:0] TX_DATAIN1_delay;
wire [127:0] TX_DATAIN2_delay;
wire [127:0] TX_DATAIN3_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA0_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA1_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA2_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA3_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA4_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA5_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA6_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA7_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA8_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_delay;
wire [15:0] DRP_DI_delay;
wire [15:0] RX_SERDES_ALT_DATA0_delay;
wire [15:0] RX_SERDES_ALT_DATA1_delay;
wire [15:0] RX_SERDES_ALT_DATA2_delay;
wire [15:0] RX_SERDES_ALT_DATA3_delay;
wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_delay;
wire [15:0] TX_PTP_TAG_FIELD_IN_delay;
wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_delay;
wire [1:0] TX_PTP_1588OP_IN_delay;
wire [31:0] RX_SERDES_DATA4_delay;
wire [31:0] RX_SERDES_DATA5_delay;
wire [31:0] RX_SERDES_DATA6_delay;
wire [31:0] RX_SERDES_DATA7_delay;
wire [31:0] RX_SERDES_DATA8_delay;
wire [31:0] RX_SERDES_DATA9_delay;
wire [3:0] TX_MTYIN0_delay;
wire [3:0] TX_MTYIN1_delay;
wire [3:0] TX_MTYIN2_delay;
wire [3:0] TX_MTYIN3_delay;
wire [63:0] RX_SERDES_DATA0_delay;
wire [63:0] RX_SERDES_DATA1_delay;
wire [63:0] RX_SERDES_DATA2_delay;
wire [63:0] RX_SERDES_DATA3_delay;
wire [63:0] TX_PTP_RXTSTAMP_IN_delay;
wire [79:0] CTL_RX_SYSTEMTIMERIN_delay;
wire [79:0] CTL_TX_SYSTEMTIMERIN_delay;
wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay;
wire [8:0] CTL_RX_PAUSE_ACK_delay;
wire [8:0] CTL_RX_PAUSE_ENABLE_delay;
wire [8:0] CTL_TX_PAUSE_ENABLE_delay;
wire [8:0] CTL_TX_PAUSE_REQ_delay;
wire [9:0] DRP_ADDR_delay;
wire [9:0] RX_SERDES_CLK_delay;
wire [9:0] RX_SERDES_RESET_delay;
assign #(out_delay) DRP_DO = DRP_DO_delay;
assign #(out_delay) DRP_RDY = DRP_RDY_delay;
assign #(out_delay) RX_DATAOUT0 = RX_DATAOUT0_delay;
assign #(out_delay) RX_DATAOUT1 = RX_DATAOUT1_delay;
assign #(out_delay) RX_DATAOUT2 = RX_DATAOUT2_delay;
assign #(out_delay) RX_DATAOUT3 = RX_DATAOUT3_delay;
assign #(out_delay) RX_ENAOUT0 = RX_ENAOUT0_delay;
assign #(out_delay) RX_ENAOUT1 = RX_ENAOUT1_delay;
assign #(out_delay) RX_ENAOUT2 = RX_ENAOUT2_delay;
assign #(out_delay) RX_ENAOUT3 = RX_ENAOUT3_delay;
assign #(out_delay) RX_EOPOUT0 = RX_EOPOUT0_delay;
assign #(out_delay) RX_EOPOUT1 = RX_EOPOUT1_delay;
assign #(out_delay) RX_EOPOUT2 = RX_EOPOUT2_delay;
assign #(out_delay) RX_EOPOUT3 = RX_EOPOUT3_delay;
assign #(out_delay) RX_ERROUT0 = RX_ERROUT0_delay;
assign #(out_delay) RX_ERROUT1 = RX_ERROUT1_delay;
assign #(out_delay) RX_ERROUT2 = RX_ERROUT2_delay;
assign #(out_delay) RX_ERROUT3 = RX_ERROUT3_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_0 = RX_LANE_ALIGNER_FILL_0_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_1 = RX_LANE_ALIGNER_FILL_1_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_10 = RX_LANE_ALIGNER_FILL_10_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_11 = RX_LANE_ALIGNER_FILL_11_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_12 = RX_LANE_ALIGNER_FILL_12_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_13 = RX_LANE_ALIGNER_FILL_13_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_14 = RX_LANE_ALIGNER_FILL_14_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_15 = RX_LANE_ALIGNER_FILL_15_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_16 = RX_LANE_ALIGNER_FILL_16_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_17 = RX_LANE_ALIGNER_FILL_17_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_18 = RX_LANE_ALIGNER_FILL_18_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_19 = RX_LANE_ALIGNER_FILL_19_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_2 = RX_LANE_ALIGNER_FILL_2_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_3 = RX_LANE_ALIGNER_FILL_3_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_4 = RX_LANE_ALIGNER_FILL_4_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_5 = RX_LANE_ALIGNER_FILL_5_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_6 = RX_LANE_ALIGNER_FILL_6_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_7 = RX_LANE_ALIGNER_FILL_7_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_8 = RX_LANE_ALIGNER_FILL_8_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_9 = RX_LANE_ALIGNER_FILL_9_delay;
assign #(out_delay) RX_MTYOUT0 = RX_MTYOUT0_delay;
assign #(out_delay) RX_MTYOUT1 = RX_MTYOUT1_delay;
assign #(out_delay) RX_MTYOUT2 = RX_MTYOUT2_delay;
assign #(out_delay) RX_MTYOUT3 = RX_MTYOUT3_delay;
assign #(out_delay) RX_PTP_PCSLANE_OUT = RX_PTP_PCSLANE_OUT_delay;
assign #(out_delay) RX_PTP_TSTAMP_OUT = RX_PTP_TSTAMP_OUT_delay;
assign #(out_delay) RX_SOPOUT0 = RX_SOPOUT0_delay;
assign #(out_delay) RX_SOPOUT1 = RX_SOPOUT1_delay;
assign #(out_delay) RX_SOPOUT2 = RX_SOPOUT2_delay;
assign #(out_delay) RX_SOPOUT3 = RX_SOPOUT3_delay;
assign #(out_delay) STAT_RX_ALIGNED = STAT_RX_ALIGNED_delay;
assign #(out_delay) STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_delay;
assign #(out_delay) STAT_RX_BAD_CODE = STAT_RX_BAD_CODE_delay;
assign #(out_delay) STAT_RX_BAD_FCS = STAT_RX_BAD_FCS_delay;
assign #(out_delay) STAT_RX_BAD_PREAMBLE = STAT_RX_BAD_PREAMBLE_delay;
assign #(out_delay) STAT_RX_BAD_SFD = STAT_RX_BAD_SFD_delay;
assign #(out_delay) STAT_RX_BIP_ERR_0 = STAT_RX_BIP_ERR_0_delay;
assign #(out_delay) STAT_RX_BIP_ERR_1 = STAT_RX_BIP_ERR_1_delay;
assign #(out_delay) STAT_RX_BIP_ERR_10 = STAT_RX_BIP_ERR_10_delay;
assign #(out_delay) STAT_RX_BIP_ERR_11 = STAT_RX_BIP_ERR_11_delay;
assign #(out_delay) STAT_RX_BIP_ERR_12 = STAT_RX_BIP_ERR_12_delay;
assign #(out_delay) STAT_RX_BIP_ERR_13 = STAT_RX_BIP_ERR_13_delay;
assign #(out_delay) STAT_RX_BIP_ERR_14 = STAT_RX_BIP_ERR_14_delay;
assign #(out_delay) STAT_RX_BIP_ERR_15 = STAT_RX_BIP_ERR_15_delay;
assign #(out_delay) STAT_RX_BIP_ERR_16 = STAT_RX_BIP_ERR_16_delay;
assign #(out_delay) STAT_RX_BIP_ERR_17 = STAT_RX_BIP_ERR_17_delay;
assign #(out_delay) STAT_RX_BIP_ERR_18 = STAT_RX_BIP_ERR_18_delay;
assign #(out_delay) STAT_RX_BIP_ERR_19 = STAT_RX_BIP_ERR_19_delay;
assign #(out_delay) STAT_RX_BIP_ERR_2 = STAT_RX_BIP_ERR_2_delay;
assign #(out_delay) STAT_RX_BIP_ERR_3 = STAT_RX_BIP_ERR_3_delay;
assign #(out_delay) STAT_RX_BIP_ERR_4 = STAT_RX_BIP_ERR_4_delay;
assign #(out_delay) STAT_RX_BIP_ERR_5 = STAT_RX_BIP_ERR_5_delay;
assign #(out_delay) STAT_RX_BIP_ERR_6 = STAT_RX_BIP_ERR_6_delay;
assign #(out_delay) STAT_RX_BIP_ERR_7 = STAT_RX_BIP_ERR_7_delay;
assign #(out_delay) STAT_RX_BIP_ERR_8 = STAT_RX_BIP_ERR_8_delay;
assign #(out_delay) STAT_RX_BIP_ERR_9 = STAT_RX_BIP_ERR_9_delay;
assign #(out_delay) STAT_RX_BLOCK_LOCK = STAT_RX_BLOCK_LOCK_delay;
assign #(out_delay) STAT_RX_BROADCAST = STAT_RX_BROADCAST_delay;
assign #(out_delay) STAT_RX_FRAGMENT = STAT_RX_FRAGMENT_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_0 = STAT_RX_FRAMING_ERR_0_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_1 = STAT_RX_FRAMING_ERR_1_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_10 = STAT_RX_FRAMING_ERR_10_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_11 = STAT_RX_FRAMING_ERR_11_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_12 = STAT_RX_FRAMING_ERR_12_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_13 = STAT_RX_FRAMING_ERR_13_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_14 = STAT_RX_FRAMING_ERR_14_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_15 = STAT_RX_FRAMING_ERR_15_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_16 = STAT_RX_FRAMING_ERR_16_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_17 = STAT_RX_FRAMING_ERR_17_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_18 = STAT_RX_FRAMING_ERR_18_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_19 = STAT_RX_FRAMING_ERR_19_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_2 = STAT_RX_FRAMING_ERR_2_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_3 = STAT_RX_FRAMING_ERR_3_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_4 = STAT_RX_FRAMING_ERR_4_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_5 = STAT_RX_FRAMING_ERR_5_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_6 = STAT_RX_FRAMING_ERR_6_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_7 = STAT_RX_FRAMING_ERR_7_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_8 = STAT_RX_FRAMING_ERR_8_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_9 = STAT_RX_FRAMING_ERR_9_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_0 = STAT_RX_FRAMING_ERR_VALID_0_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_1 = STAT_RX_FRAMING_ERR_VALID_1_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_10 = STAT_RX_FRAMING_ERR_VALID_10_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_11 = STAT_RX_FRAMING_ERR_VALID_11_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_12 = STAT_RX_FRAMING_ERR_VALID_12_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_13 = STAT_RX_FRAMING_ERR_VALID_13_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_14 = STAT_RX_FRAMING_ERR_VALID_14_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_15 = STAT_RX_FRAMING_ERR_VALID_15_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_16 = STAT_RX_FRAMING_ERR_VALID_16_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_17 = STAT_RX_FRAMING_ERR_VALID_17_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_18 = STAT_RX_FRAMING_ERR_VALID_18_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_19 = STAT_RX_FRAMING_ERR_VALID_19_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_2 = STAT_RX_FRAMING_ERR_VALID_2_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_3 = STAT_RX_FRAMING_ERR_VALID_3_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_4 = STAT_RX_FRAMING_ERR_VALID_4_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_5 = STAT_RX_FRAMING_ERR_VALID_5_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_6 = STAT_RX_FRAMING_ERR_VALID_6_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_7 = STAT_RX_FRAMING_ERR_VALID_7_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_8 = STAT_RX_FRAMING_ERR_VALID_8_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_9 = STAT_RX_FRAMING_ERR_VALID_9_delay;
assign #(out_delay) STAT_RX_GOT_SIGNAL_OS = STAT_RX_GOT_SIGNAL_OS_delay;
assign #(out_delay) STAT_RX_HI_BER = STAT_RX_HI_BER_delay;
assign #(out_delay) STAT_RX_INRANGEERR = STAT_RX_INRANGEERR_delay;
assign #(out_delay) STAT_RX_INTERNAL_LOCAL_FAULT = STAT_RX_INTERNAL_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_JABBER = STAT_RX_JABBER_delay;
assign #(out_delay) STAT_RX_LANE0_VLM_BIP7 = STAT_RX_LANE0_VLM_BIP7_delay;
assign #(out_delay) STAT_RX_LANE0_VLM_BIP7_VALID = STAT_RX_LANE0_VLM_BIP7_VALID_delay;
assign #(out_delay) STAT_RX_LOCAL_FAULT = STAT_RX_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_MF_ERR = STAT_RX_MF_ERR_delay;
assign #(out_delay) STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_delay;
assign #(out_delay) STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_delay;
assign #(out_delay) STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_delay;
assign #(out_delay) STAT_RX_MULTICAST = STAT_RX_MULTICAST_delay;
assign #(out_delay) STAT_RX_OVERSIZE = STAT_RX_OVERSIZE_delay;
assign #(out_delay) STAT_RX_PACKET_1024_1518_BYTES = STAT_RX_PACKET_1024_1518_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_128_255_BYTES = STAT_RX_PACKET_128_255_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1519_1522_BYTES = STAT_RX_PACKET_1519_1522_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1523_1548_BYTES = STAT_RX_PACKET_1523_1548_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1549_2047_BYTES = STAT_RX_PACKET_1549_2047_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_2048_4095_BYTES = STAT_RX_PACKET_2048_4095_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_256_511_BYTES = STAT_RX_PACKET_256_511_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_4096_8191_BYTES = STAT_RX_PACKET_4096_8191_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_512_1023_BYTES = STAT_RX_PACKET_512_1023_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_64_BYTES = STAT_RX_PACKET_64_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_65_127_BYTES = STAT_RX_PACKET_65_127_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_8192_9215_BYTES = STAT_RX_PACKET_8192_9215_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_BAD_FCS = STAT_RX_PACKET_BAD_FCS_delay;
assign #(out_delay) STAT_RX_PACKET_LARGE = STAT_RX_PACKET_LARGE_delay;
assign #(out_delay) STAT_RX_PACKET_SMALL = STAT_RX_PACKET_SMALL_delay;
assign #(out_delay) STAT_RX_PAUSE = STAT_RX_PAUSE_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA0 = STAT_RX_PAUSE_QUANTA0_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA1 = STAT_RX_PAUSE_QUANTA1_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA2 = STAT_RX_PAUSE_QUANTA2_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA3 = STAT_RX_PAUSE_QUANTA3_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA4 = STAT_RX_PAUSE_QUANTA4_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA5 = STAT_RX_PAUSE_QUANTA5_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA6 = STAT_RX_PAUSE_QUANTA6_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA7 = STAT_RX_PAUSE_QUANTA7_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA8 = STAT_RX_PAUSE_QUANTA8_delay;
assign #(out_delay) STAT_RX_PAUSE_REQ = STAT_RX_PAUSE_REQ_delay;
assign #(out_delay) STAT_RX_PAUSE_VALID = STAT_RX_PAUSE_VALID_delay;
assign #(out_delay) STAT_RX_RECEIVED_LOCAL_FAULT = STAT_RX_RECEIVED_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_REMOTE_FAULT = STAT_RX_REMOTE_FAULT_delay;
assign #(out_delay) STAT_RX_STATUS = STAT_RX_STATUS_delay;
assign #(out_delay) STAT_RX_STOMPED_FCS = STAT_RX_STOMPED_FCS_delay;
assign #(out_delay) STAT_RX_SYNCED = STAT_RX_SYNCED_delay;
assign #(out_delay) STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_delay;
assign #(out_delay) STAT_RX_TEST_PATTERN_MISMATCH = STAT_RX_TEST_PATTERN_MISMATCH_delay;
assign #(out_delay) STAT_RX_TOOLONG = STAT_RX_TOOLONG_delay;
assign #(out_delay) STAT_RX_TOTAL_BYTES = STAT_RX_TOTAL_BYTES_delay;
assign #(out_delay) STAT_RX_TOTAL_GOOD_BYTES = STAT_RX_TOTAL_GOOD_BYTES_delay;
assign #(out_delay) STAT_RX_TOTAL_GOOD_PACKETS = STAT_RX_TOTAL_GOOD_PACKETS_delay;
assign #(out_delay) STAT_RX_TOTAL_PACKETS = STAT_RX_TOTAL_PACKETS_delay;
assign #(out_delay) STAT_RX_TRUNCATED = STAT_RX_TRUNCATED_delay;
assign #(out_delay) STAT_RX_UNDERSIZE = STAT_RX_UNDERSIZE_delay;
assign #(out_delay) STAT_RX_UNICAST = STAT_RX_UNICAST_delay;
assign #(out_delay) STAT_RX_USER_PAUSE = STAT_RX_USER_PAUSE_delay;
assign #(out_delay) STAT_RX_VLAN = STAT_RX_VLAN_delay;
assign #(out_delay) STAT_RX_VL_DEMUXED = STAT_RX_VL_DEMUXED_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_0 = STAT_RX_VL_NUMBER_0_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_1 = STAT_RX_VL_NUMBER_1_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_10 = STAT_RX_VL_NUMBER_10_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_11 = STAT_RX_VL_NUMBER_11_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_12 = STAT_RX_VL_NUMBER_12_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_13 = STAT_RX_VL_NUMBER_13_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_14 = STAT_RX_VL_NUMBER_14_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_15 = STAT_RX_VL_NUMBER_15_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_16 = STAT_RX_VL_NUMBER_16_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_17 = STAT_RX_VL_NUMBER_17_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_18 = STAT_RX_VL_NUMBER_18_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_19 = STAT_RX_VL_NUMBER_19_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_2 = STAT_RX_VL_NUMBER_2_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_3 = STAT_RX_VL_NUMBER_3_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_4 = STAT_RX_VL_NUMBER_4_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_5 = STAT_RX_VL_NUMBER_5_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_6 = STAT_RX_VL_NUMBER_6_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_7 = STAT_RX_VL_NUMBER_7_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_8 = STAT_RX_VL_NUMBER_8_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_9 = STAT_RX_VL_NUMBER_9_delay;
assign #(out_delay) STAT_TX_BAD_FCS = STAT_TX_BAD_FCS_delay;
assign #(out_delay) STAT_TX_BROADCAST = STAT_TX_BROADCAST_delay;
assign #(out_delay) STAT_TX_FRAME_ERROR = STAT_TX_FRAME_ERROR_delay;
assign #(out_delay) STAT_TX_LOCAL_FAULT = STAT_TX_LOCAL_FAULT_delay;
assign #(out_delay) STAT_TX_MULTICAST = STAT_TX_MULTICAST_delay;
assign #(out_delay) STAT_TX_PACKET_1024_1518_BYTES = STAT_TX_PACKET_1024_1518_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_128_255_BYTES = STAT_TX_PACKET_128_255_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1519_1522_BYTES = STAT_TX_PACKET_1519_1522_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1523_1548_BYTES = STAT_TX_PACKET_1523_1548_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1549_2047_BYTES = STAT_TX_PACKET_1549_2047_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_2048_4095_BYTES = STAT_TX_PACKET_2048_4095_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_256_511_BYTES = STAT_TX_PACKET_256_511_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_4096_8191_BYTES = STAT_TX_PACKET_4096_8191_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_512_1023_BYTES = STAT_TX_PACKET_512_1023_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_64_BYTES = STAT_TX_PACKET_64_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_65_127_BYTES = STAT_TX_PACKET_65_127_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_8192_9215_BYTES = STAT_TX_PACKET_8192_9215_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_LARGE = STAT_TX_PACKET_LARGE_delay;
assign #(out_delay) STAT_TX_PACKET_SMALL = STAT_TX_PACKET_SMALL_delay;
assign #(out_delay) STAT_TX_PAUSE = STAT_TX_PAUSE_delay;
assign #(out_delay) STAT_TX_PAUSE_VALID = STAT_TX_PAUSE_VALID_delay;
assign #(out_delay) STAT_TX_PTP_FIFO_READ_ERROR = STAT_TX_PTP_FIFO_READ_ERROR_delay;
assign #(out_delay) STAT_TX_PTP_FIFO_WRITE_ERROR = STAT_TX_PTP_FIFO_WRITE_ERROR_delay;
assign #(out_delay) STAT_TX_TOTAL_BYTES = STAT_TX_TOTAL_BYTES_delay;
assign #(out_delay) STAT_TX_TOTAL_GOOD_BYTES = STAT_TX_TOTAL_GOOD_BYTES_delay;
assign #(out_delay) STAT_TX_TOTAL_GOOD_PACKETS = STAT_TX_TOTAL_GOOD_PACKETS_delay;
assign #(out_delay) STAT_TX_TOTAL_PACKETS = STAT_TX_TOTAL_PACKETS_delay;
assign #(out_delay) STAT_TX_UNICAST = STAT_TX_UNICAST_delay;
assign #(out_delay) STAT_TX_USER_PAUSE = STAT_TX_USER_PAUSE_delay;
assign #(out_delay) STAT_TX_VLAN = STAT_TX_VLAN_delay;
assign #(out_delay) TX_OVFOUT = TX_OVFOUT_delay;
assign #(out_delay) TX_PTP_PCSLANE_OUT = TX_PTP_PCSLANE_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_OUT = TX_PTP_TSTAMP_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_TAG_OUT = TX_PTP_TSTAMP_TAG_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_VALID_OUT = TX_PTP_TSTAMP_VALID_OUT_delay;
assign #(out_delay) TX_RDYOUT = TX_RDYOUT_delay;
assign #(out_delay) TX_SERDES_ALT_DATA0 = TX_SERDES_ALT_DATA0_delay;
assign #(out_delay) TX_SERDES_ALT_DATA1 = TX_SERDES_ALT_DATA1_delay;
assign #(out_delay) TX_SERDES_ALT_DATA2 = TX_SERDES_ALT_DATA2_delay;
assign #(out_delay) TX_SERDES_ALT_DATA3 = TX_SERDES_ALT_DATA3_delay;
assign #(out_delay) TX_SERDES_DATA0 = TX_SERDES_DATA0_delay;
assign #(out_delay) TX_SERDES_DATA1 = TX_SERDES_DATA1_delay;
assign #(out_delay) TX_SERDES_DATA2 = TX_SERDES_DATA2_delay;
assign #(out_delay) TX_SERDES_DATA3 = TX_SERDES_DATA3_delay;
assign #(out_delay) TX_SERDES_DATA4 = TX_SERDES_DATA4_delay;
assign #(out_delay) TX_SERDES_DATA5 = TX_SERDES_DATA5_delay;
assign #(out_delay) TX_SERDES_DATA6 = TX_SERDES_DATA6_delay;
assign #(out_delay) TX_SERDES_DATA7 = TX_SERDES_DATA7_delay;
assign #(out_delay) TX_SERDES_DATA8 = TX_SERDES_DATA8_delay;
assign #(out_delay) TX_SERDES_DATA9 = TX_SERDES_DATA9_delay;
assign #(out_delay) TX_UNFOUT = TX_UNFOUT_delay;
// inputs with no timing checks
assign #(inclk_delay) DRP_CLK_delay = DRP_CLK;
assign #(inclk_delay) RX_CLK_delay = RX_CLK;
assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK;
assign #(inclk_delay) TX_CLK_delay = TX_CLK;
assign #(in_delay) CTL_CAUI4_MODE_delay = CTL_CAUI4_MODE;
assign #(in_delay) CTL_RX_CHECK_ETYPE_GCP_delay = CTL_RX_CHECK_ETYPE_GCP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_GPP_delay = CTL_RX_CHECK_ETYPE_GPP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_PCP_delay = CTL_RX_CHECK_ETYPE_PCP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_PPP_delay = CTL_RX_CHECK_ETYPE_PPP;
assign #(in_delay) CTL_RX_CHECK_MCAST_GCP_delay = CTL_RX_CHECK_MCAST_GCP;
assign #(in_delay) CTL_RX_CHECK_MCAST_GPP_delay = CTL_RX_CHECK_MCAST_GPP;
assign #(in_delay) CTL_RX_CHECK_MCAST_PCP_delay = CTL_RX_CHECK_MCAST_PCP;
assign #(in_delay) CTL_RX_CHECK_MCAST_PPP_delay = CTL_RX_CHECK_MCAST_PPP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_GCP_delay = CTL_RX_CHECK_OPCODE_GCP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_GPP_delay = CTL_RX_CHECK_OPCODE_GPP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_PCP_delay = CTL_RX_CHECK_OPCODE_PCP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_PPP_delay = CTL_RX_CHECK_OPCODE_PPP;
assign #(in_delay) CTL_RX_CHECK_SA_GCP_delay = CTL_RX_CHECK_SA_GCP;
assign #(in_delay) CTL_RX_CHECK_SA_GPP_delay = CTL_RX_CHECK_SA_GPP;
assign #(in_delay) CTL_RX_CHECK_SA_PCP_delay = CTL_RX_CHECK_SA_PCP;
assign #(in_delay) CTL_RX_CHECK_SA_PPP_delay = CTL_RX_CHECK_SA_PPP;
assign #(in_delay) CTL_RX_CHECK_UCAST_GCP_delay = CTL_RX_CHECK_UCAST_GCP;
assign #(in_delay) CTL_RX_CHECK_UCAST_GPP_delay = CTL_RX_CHECK_UCAST_GPP;
assign #(in_delay) CTL_RX_CHECK_UCAST_PCP_delay = CTL_RX_CHECK_UCAST_PCP;
assign #(in_delay) CTL_RX_CHECK_UCAST_PPP_delay = CTL_RX_CHECK_UCAST_PPP;
assign #(in_delay) CTL_RX_ENABLE_GCP_delay = CTL_RX_ENABLE_GCP;
assign #(in_delay) CTL_RX_ENABLE_GPP_delay = CTL_RX_ENABLE_GPP;
assign #(in_delay) CTL_RX_ENABLE_PCP_delay = CTL_RX_ENABLE_PCP;
assign #(in_delay) CTL_RX_ENABLE_PPP_delay = CTL_RX_ENABLE_PPP;
assign #(in_delay) CTL_RX_ENABLE_delay = CTL_RX_ENABLE;
assign #(in_delay) CTL_RX_FORCE_RESYNC_delay = CTL_RX_FORCE_RESYNC;
assign #(in_delay) CTL_RX_PAUSE_ACK_delay = CTL_RX_PAUSE_ACK;
assign #(in_delay) CTL_RX_PAUSE_ENABLE_delay = CTL_RX_PAUSE_ENABLE;
assign #(in_delay) CTL_RX_SYSTEMTIMERIN_delay = CTL_RX_SYSTEMTIMERIN;
assign #(in_delay) CTL_RX_TEST_PATTERN_delay = CTL_RX_TEST_PATTERN;
assign #(in_delay) CTL_TX_ENABLE_delay = CTL_TX_ENABLE;
assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
assign #(in_delay) CTL_TX_PAUSE_ENABLE_delay = CTL_TX_PAUSE_ENABLE;
assign #(in_delay) CTL_TX_PAUSE_QUANTA0_delay = CTL_TX_PAUSE_QUANTA0;
assign #(in_delay) CTL_TX_PAUSE_QUANTA1_delay = CTL_TX_PAUSE_QUANTA1;
assign #(in_delay) CTL_TX_PAUSE_QUANTA2_delay = CTL_TX_PAUSE_QUANTA2;
assign #(in_delay) CTL_TX_PAUSE_QUANTA3_delay = CTL_TX_PAUSE_QUANTA3;
assign #(in_delay) CTL_TX_PAUSE_QUANTA4_delay = CTL_TX_PAUSE_QUANTA4;
assign #(in_delay) CTL_TX_PAUSE_QUANTA5_delay = CTL_TX_PAUSE_QUANTA5;
assign #(in_delay) CTL_TX_PAUSE_QUANTA6_delay = CTL_TX_PAUSE_QUANTA6;
assign #(in_delay) CTL_TX_PAUSE_QUANTA7_delay = CTL_TX_PAUSE_QUANTA7;
assign #(in_delay) CTL_TX_PAUSE_QUANTA8_delay = CTL_TX_PAUSE_QUANTA8;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER0_delay = CTL_TX_PAUSE_REFRESH_TIMER0;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER1_delay = CTL_TX_PAUSE_REFRESH_TIMER1;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER2_delay = CTL_TX_PAUSE_REFRESH_TIMER2;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER3_delay = CTL_TX_PAUSE_REFRESH_TIMER3;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER4_delay = CTL_TX_PAUSE_REFRESH_TIMER4;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER5_delay = CTL_TX_PAUSE_REFRESH_TIMER5;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER6_delay = CTL_TX_PAUSE_REFRESH_TIMER6;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER7_delay = CTL_TX_PAUSE_REFRESH_TIMER7;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER8_delay = CTL_TX_PAUSE_REFRESH_TIMER8;
assign #(in_delay) CTL_TX_PAUSE_REQ_delay = CTL_TX_PAUSE_REQ;
assign #(in_delay) CTL_TX_PTP_VLANE_ADJUST_MODE_delay = CTL_TX_PTP_VLANE_ADJUST_MODE;
assign #(in_delay) CTL_TX_RESEND_PAUSE_delay = CTL_TX_RESEND_PAUSE;
assign #(in_delay) CTL_TX_SEND_IDLE_delay = CTL_TX_SEND_IDLE;
assign #(in_delay) CTL_TX_SEND_RFI_delay = CTL_TX_SEND_RFI;
assign #(in_delay) CTL_TX_SYSTEMTIMERIN_delay = CTL_TX_SYSTEMTIMERIN;
assign #(in_delay) CTL_TX_TEST_PATTERN_delay = CTL_TX_TEST_PATTERN;
assign #(in_delay) DRP_ADDR_delay = DRP_ADDR;
assign #(in_delay) DRP_DI_delay = DRP_DI;
assign #(in_delay) DRP_EN_delay = DRP_EN;
assign #(in_delay) DRP_WE_delay = DRP_WE;
assign #(in_delay) RX_RESET_delay = RX_RESET;
assign #(in_delay) RX_SERDES_ALT_DATA0_delay = RX_SERDES_ALT_DATA0;
assign #(in_delay) RX_SERDES_ALT_DATA1_delay = RX_SERDES_ALT_DATA1;
assign #(in_delay) RX_SERDES_ALT_DATA2_delay = RX_SERDES_ALT_DATA2;
assign #(in_delay) RX_SERDES_ALT_DATA3_delay = RX_SERDES_ALT_DATA3;
assign #(in_delay) RX_SERDES_DATA0_delay = RX_SERDES_DATA0;
assign #(in_delay) RX_SERDES_DATA1_delay = RX_SERDES_DATA1;
assign #(in_delay) RX_SERDES_DATA2_delay = RX_SERDES_DATA2;
assign #(in_delay) RX_SERDES_DATA3_delay = RX_SERDES_DATA3;
assign #(in_delay) RX_SERDES_DATA4_delay = RX_SERDES_DATA4;
assign #(in_delay) RX_SERDES_DATA5_delay = RX_SERDES_DATA5;
assign #(in_delay) RX_SERDES_DATA6_delay = RX_SERDES_DATA6;
assign #(in_delay) RX_SERDES_DATA7_delay = RX_SERDES_DATA7;
assign #(in_delay) RX_SERDES_DATA8_delay = RX_SERDES_DATA8;
assign #(in_delay) RX_SERDES_DATA9_delay = RX_SERDES_DATA9;
assign #(in_delay) RX_SERDES_RESET_delay = RX_SERDES_RESET;
assign #(in_delay) TX_DATAIN0_delay = TX_DATAIN0;
assign #(in_delay) TX_DATAIN1_delay = TX_DATAIN1;
assign #(in_delay) TX_DATAIN2_delay = TX_DATAIN2;
assign #(in_delay) TX_DATAIN3_delay = TX_DATAIN3;
assign #(in_delay) TX_ENAIN0_delay = TX_ENAIN0;
assign #(in_delay) TX_ENAIN1_delay = TX_ENAIN1;
assign #(in_delay) TX_ENAIN2_delay = TX_ENAIN2;
assign #(in_delay) TX_ENAIN3_delay = TX_ENAIN3;
assign #(in_delay) TX_EOPIN0_delay = TX_EOPIN0;
assign #(in_delay) TX_EOPIN1_delay = TX_EOPIN1;
assign #(in_delay) TX_EOPIN2_delay = TX_EOPIN2;
assign #(in_delay) TX_EOPIN3_delay = TX_EOPIN3;
assign #(in_delay) TX_ERRIN0_delay = TX_ERRIN0;
assign #(in_delay) TX_ERRIN1_delay = TX_ERRIN1;
assign #(in_delay) TX_ERRIN2_delay = TX_ERRIN2;
assign #(in_delay) TX_ERRIN3_delay = TX_ERRIN3;
assign #(in_delay) TX_MTYIN0_delay = TX_MTYIN0;
assign #(in_delay) TX_MTYIN1_delay = TX_MTYIN1;
assign #(in_delay) TX_MTYIN2_delay = TX_MTYIN2;
assign #(in_delay) TX_MTYIN3_delay = TX_MTYIN3;
assign #(in_delay) TX_PTP_1588OP_IN_delay = TX_PTP_1588OP_IN;
assign #(in_delay) TX_PTP_CHKSUM_OFFSET_IN_delay = TX_PTP_CHKSUM_OFFSET_IN;
assign #(in_delay) TX_PTP_RXTSTAMP_IN_delay = TX_PTP_RXTSTAMP_IN;
assign #(in_delay) TX_PTP_TAG_FIELD_IN_delay = TX_PTP_TAG_FIELD_IN;
assign #(in_delay) TX_PTP_TSTAMP_OFFSET_IN_delay = TX_PTP_TSTAMP_OFFSET_IN;
assign #(in_delay) TX_PTP_UPD_CHKSUM_IN_delay = TX_PTP_UPD_CHKSUM_IN;
assign #(in_delay) TX_RESET_delay = TX_RESET;
assign #(in_delay) TX_SOPIN0_delay = TX_SOPIN0;
assign #(in_delay) TX_SOPIN1_delay = TX_SOPIN1;
assign #(in_delay) TX_SOPIN2_delay = TX_SOPIN2;
assign #(in_delay) TX_SOPIN3_delay = TX_SOPIN3;
assign DRP_DO_delay = DRP_DO_out;
assign DRP_RDY_delay = DRP_RDY_out;
assign RX_DATAOUT0_delay = RX_DATAOUT0_out;
assign RX_DATAOUT1_delay = RX_DATAOUT1_out;
assign RX_DATAOUT2_delay = RX_DATAOUT2_out;
assign RX_DATAOUT3_delay = RX_DATAOUT3_out;
assign RX_ENAOUT0_delay = RX_ENAOUT0_out;
assign RX_ENAOUT1_delay = RX_ENAOUT1_out;
assign RX_ENAOUT2_delay = RX_ENAOUT2_out;
assign RX_ENAOUT3_delay = RX_ENAOUT3_out;
assign RX_EOPOUT0_delay = RX_EOPOUT0_out;
assign RX_EOPOUT1_delay = RX_EOPOUT1_out;
assign RX_EOPOUT2_delay = RX_EOPOUT2_out;
assign RX_EOPOUT3_delay = RX_EOPOUT3_out;
assign RX_ERROUT0_delay = RX_ERROUT0_out;
assign RX_ERROUT1_delay = RX_ERROUT1_out;
assign RX_ERROUT2_delay = RX_ERROUT2_out;
assign RX_ERROUT3_delay = RX_ERROUT3_out;
assign RX_LANE_ALIGNER_FILL_0_delay = RX_LANE_ALIGNER_FILL_0_out;
assign RX_LANE_ALIGNER_FILL_10_delay = RX_LANE_ALIGNER_FILL_10_out;
assign RX_LANE_ALIGNER_FILL_11_delay = RX_LANE_ALIGNER_FILL_11_out;
assign RX_LANE_ALIGNER_FILL_12_delay = RX_LANE_ALIGNER_FILL_12_out;
assign RX_LANE_ALIGNER_FILL_13_delay = RX_LANE_ALIGNER_FILL_13_out;
assign RX_LANE_ALIGNER_FILL_14_delay = RX_LANE_ALIGNER_FILL_14_out;
assign RX_LANE_ALIGNER_FILL_15_delay = RX_LANE_ALIGNER_FILL_15_out;
assign RX_LANE_ALIGNER_FILL_16_delay = RX_LANE_ALIGNER_FILL_16_out;
assign RX_LANE_ALIGNER_FILL_17_delay = RX_LANE_ALIGNER_FILL_17_out;
assign RX_LANE_ALIGNER_FILL_18_delay = RX_LANE_ALIGNER_FILL_18_out;
assign RX_LANE_ALIGNER_FILL_19_delay = RX_LANE_ALIGNER_FILL_19_out;
assign RX_LANE_ALIGNER_FILL_1_delay = RX_LANE_ALIGNER_FILL_1_out;
assign RX_LANE_ALIGNER_FILL_2_delay = RX_LANE_ALIGNER_FILL_2_out;
assign RX_LANE_ALIGNER_FILL_3_delay = RX_LANE_ALIGNER_FILL_3_out;
assign RX_LANE_ALIGNER_FILL_4_delay = RX_LANE_ALIGNER_FILL_4_out;
assign RX_LANE_ALIGNER_FILL_5_delay = RX_LANE_ALIGNER_FILL_5_out;
assign RX_LANE_ALIGNER_FILL_6_delay = RX_LANE_ALIGNER_FILL_6_out;
assign RX_LANE_ALIGNER_FILL_7_delay = RX_LANE_ALIGNER_FILL_7_out;
assign RX_LANE_ALIGNER_FILL_8_delay = RX_LANE_ALIGNER_FILL_8_out;
assign RX_LANE_ALIGNER_FILL_9_delay = RX_LANE_ALIGNER_FILL_9_out;
assign RX_MTYOUT0_delay = RX_MTYOUT0_out;
assign RX_MTYOUT1_delay = RX_MTYOUT1_out;
assign RX_MTYOUT2_delay = RX_MTYOUT2_out;
assign RX_MTYOUT3_delay = RX_MTYOUT3_out;
assign RX_PTP_PCSLANE_OUT_delay = RX_PTP_PCSLANE_OUT_out;
assign RX_PTP_TSTAMP_OUT_delay = RX_PTP_TSTAMP_OUT_out;
assign RX_SOPOUT0_delay = RX_SOPOUT0_out;
assign RX_SOPOUT1_delay = RX_SOPOUT1_out;
assign RX_SOPOUT2_delay = RX_SOPOUT2_out;
assign RX_SOPOUT3_delay = RX_SOPOUT3_out;
assign STAT_RX_ALIGNED_ERR_delay = STAT_RX_ALIGNED_ERR_out;
assign STAT_RX_ALIGNED_delay = STAT_RX_ALIGNED_out;
assign STAT_RX_BAD_CODE_delay = STAT_RX_BAD_CODE_out;
assign STAT_RX_BAD_FCS_delay = STAT_RX_BAD_FCS_out;
assign STAT_RX_BAD_PREAMBLE_delay = STAT_RX_BAD_PREAMBLE_out;
assign STAT_RX_BAD_SFD_delay = STAT_RX_BAD_SFD_out;
assign STAT_RX_BIP_ERR_0_delay = STAT_RX_BIP_ERR_0_out;
assign STAT_RX_BIP_ERR_10_delay = STAT_RX_BIP_ERR_10_out;
assign STAT_RX_BIP_ERR_11_delay = STAT_RX_BIP_ERR_11_out;
assign STAT_RX_BIP_ERR_12_delay = STAT_RX_BIP_ERR_12_out;
assign STAT_RX_BIP_ERR_13_delay = STAT_RX_BIP_ERR_13_out;
assign STAT_RX_BIP_ERR_14_delay = STAT_RX_BIP_ERR_14_out;
assign STAT_RX_BIP_ERR_15_delay = STAT_RX_BIP_ERR_15_out;
assign STAT_RX_BIP_ERR_16_delay = STAT_RX_BIP_ERR_16_out;
assign STAT_RX_BIP_ERR_17_delay = STAT_RX_BIP_ERR_17_out;
assign STAT_RX_BIP_ERR_18_delay = STAT_RX_BIP_ERR_18_out;
assign STAT_RX_BIP_ERR_19_delay = STAT_RX_BIP_ERR_19_out;
assign STAT_RX_BIP_ERR_1_delay = STAT_RX_BIP_ERR_1_out;
assign STAT_RX_BIP_ERR_2_delay = STAT_RX_BIP_ERR_2_out;
assign STAT_RX_BIP_ERR_3_delay = STAT_RX_BIP_ERR_3_out;
assign STAT_RX_BIP_ERR_4_delay = STAT_RX_BIP_ERR_4_out;
assign STAT_RX_BIP_ERR_5_delay = STAT_RX_BIP_ERR_5_out;
assign STAT_RX_BIP_ERR_6_delay = STAT_RX_BIP_ERR_6_out;
assign STAT_RX_BIP_ERR_7_delay = STAT_RX_BIP_ERR_7_out;
assign STAT_RX_BIP_ERR_8_delay = STAT_RX_BIP_ERR_8_out;
assign STAT_RX_BIP_ERR_9_delay = STAT_RX_BIP_ERR_9_out;
assign STAT_RX_BLOCK_LOCK_delay = STAT_RX_BLOCK_LOCK_out;
assign STAT_RX_BROADCAST_delay = STAT_RX_BROADCAST_out;
assign STAT_RX_FRAGMENT_delay = STAT_RX_FRAGMENT_out;
assign STAT_RX_FRAMING_ERR_0_delay = STAT_RX_FRAMING_ERR_0_out;
assign STAT_RX_FRAMING_ERR_10_delay = STAT_RX_FRAMING_ERR_10_out;
assign STAT_RX_FRAMING_ERR_11_delay = STAT_RX_FRAMING_ERR_11_out;
assign STAT_RX_FRAMING_ERR_12_delay = STAT_RX_FRAMING_ERR_12_out;
assign STAT_RX_FRAMING_ERR_13_delay = STAT_RX_FRAMING_ERR_13_out;
assign STAT_RX_FRAMING_ERR_14_delay = STAT_RX_FRAMING_ERR_14_out;
assign STAT_RX_FRAMING_ERR_15_delay = STAT_RX_FRAMING_ERR_15_out;
assign STAT_RX_FRAMING_ERR_16_delay = STAT_RX_FRAMING_ERR_16_out;
assign STAT_RX_FRAMING_ERR_17_delay = STAT_RX_FRAMING_ERR_17_out;
assign STAT_RX_FRAMING_ERR_18_delay = STAT_RX_FRAMING_ERR_18_out;
assign STAT_RX_FRAMING_ERR_19_delay = STAT_RX_FRAMING_ERR_19_out;
assign STAT_RX_FRAMING_ERR_1_delay = STAT_RX_FRAMING_ERR_1_out;
assign STAT_RX_FRAMING_ERR_2_delay = STAT_RX_FRAMING_ERR_2_out;
assign STAT_RX_FRAMING_ERR_3_delay = STAT_RX_FRAMING_ERR_3_out;
assign STAT_RX_FRAMING_ERR_4_delay = STAT_RX_FRAMING_ERR_4_out;
assign STAT_RX_FRAMING_ERR_5_delay = STAT_RX_FRAMING_ERR_5_out;
assign STAT_RX_FRAMING_ERR_6_delay = STAT_RX_FRAMING_ERR_6_out;
assign STAT_RX_FRAMING_ERR_7_delay = STAT_RX_FRAMING_ERR_7_out;
assign STAT_RX_FRAMING_ERR_8_delay = STAT_RX_FRAMING_ERR_8_out;
assign STAT_RX_FRAMING_ERR_9_delay = STAT_RX_FRAMING_ERR_9_out;
assign STAT_RX_FRAMING_ERR_VALID_0_delay = STAT_RX_FRAMING_ERR_VALID_0_out;
assign STAT_RX_FRAMING_ERR_VALID_10_delay = STAT_RX_FRAMING_ERR_VALID_10_out;
assign STAT_RX_FRAMING_ERR_VALID_11_delay = STAT_RX_FRAMING_ERR_VALID_11_out;
assign STAT_RX_FRAMING_ERR_VALID_12_delay = STAT_RX_FRAMING_ERR_VALID_12_out;
assign STAT_RX_FRAMING_ERR_VALID_13_delay = STAT_RX_FRAMING_ERR_VALID_13_out;
assign STAT_RX_FRAMING_ERR_VALID_14_delay = STAT_RX_FRAMING_ERR_VALID_14_out;
assign STAT_RX_FRAMING_ERR_VALID_15_delay = STAT_RX_FRAMING_ERR_VALID_15_out;
assign STAT_RX_FRAMING_ERR_VALID_16_delay = STAT_RX_FRAMING_ERR_VALID_16_out;
assign STAT_RX_FRAMING_ERR_VALID_17_delay = STAT_RX_FRAMING_ERR_VALID_17_out;
assign STAT_RX_FRAMING_ERR_VALID_18_delay = STAT_RX_FRAMING_ERR_VALID_18_out;
assign STAT_RX_FRAMING_ERR_VALID_19_delay = STAT_RX_FRAMING_ERR_VALID_19_out;
assign STAT_RX_FRAMING_ERR_VALID_1_delay = STAT_RX_FRAMING_ERR_VALID_1_out;
assign STAT_RX_FRAMING_ERR_VALID_2_delay = STAT_RX_FRAMING_ERR_VALID_2_out;
assign STAT_RX_FRAMING_ERR_VALID_3_delay = STAT_RX_FRAMING_ERR_VALID_3_out;
assign STAT_RX_FRAMING_ERR_VALID_4_delay = STAT_RX_FRAMING_ERR_VALID_4_out;
assign STAT_RX_FRAMING_ERR_VALID_5_delay = STAT_RX_FRAMING_ERR_VALID_5_out;
assign STAT_RX_FRAMING_ERR_VALID_6_delay = STAT_RX_FRAMING_ERR_VALID_6_out;
assign STAT_RX_FRAMING_ERR_VALID_7_delay = STAT_RX_FRAMING_ERR_VALID_7_out;
assign STAT_RX_FRAMING_ERR_VALID_8_delay = STAT_RX_FRAMING_ERR_VALID_8_out;
assign STAT_RX_FRAMING_ERR_VALID_9_delay = STAT_RX_FRAMING_ERR_VALID_9_out;
assign STAT_RX_GOT_SIGNAL_OS_delay = STAT_RX_GOT_SIGNAL_OS_out;
assign STAT_RX_HI_BER_delay = STAT_RX_HI_BER_out;
assign STAT_RX_INRANGEERR_delay = STAT_RX_INRANGEERR_out;
assign STAT_RX_INTERNAL_LOCAL_FAULT_delay = STAT_RX_INTERNAL_LOCAL_FAULT_out;
assign STAT_RX_JABBER_delay = STAT_RX_JABBER_out;
assign STAT_RX_LANE0_VLM_BIP7_VALID_delay = STAT_RX_LANE0_VLM_BIP7_VALID_out;
assign STAT_RX_LANE0_VLM_BIP7_delay = STAT_RX_LANE0_VLM_BIP7_out;
assign STAT_RX_LOCAL_FAULT_delay = STAT_RX_LOCAL_FAULT_out;
assign STAT_RX_MF_ERR_delay = STAT_RX_MF_ERR_out;
assign STAT_RX_MF_LEN_ERR_delay = STAT_RX_MF_LEN_ERR_out;
assign STAT_RX_MF_REPEAT_ERR_delay = STAT_RX_MF_REPEAT_ERR_out;
assign STAT_RX_MISALIGNED_delay = STAT_RX_MISALIGNED_out;
assign STAT_RX_MULTICAST_delay = STAT_RX_MULTICAST_out;
assign STAT_RX_OVERSIZE_delay = STAT_RX_OVERSIZE_out;
assign STAT_RX_PACKET_1024_1518_BYTES_delay = STAT_RX_PACKET_1024_1518_BYTES_out;
assign STAT_RX_PACKET_128_255_BYTES_delay = STAT_RX_PACKET_128_255_BYTES_out;
assign STAT_RX_PACKET_1519_1522_BYTES_delay = STAT_RX_PACKET_1519_1522_BYTES_out;
assign STAT_RX_PACKET_1523_1548_BYTES_delay = STAT_RX_PACKET_1523_1548_BYTES_out;
assign STAT_RX_PACKET_1549_2047_BYTES_delay = STAT_RX_PACKET_1549_2047_BYTES_out;
assign STAT_RX_PACKET_2048_4095_BYTES_delay = STAT_RX_PACKET_2048_4095_BYTES_out;
assign STAT_RX_PACKET_256_511_BYTES_delay = STAT_RX_PACKET_256_511_BYTES_out;
assign STAT_RX_PACKET_4096_8191_BYTES_delay = STAT_RX_PACKET_4096_8191_BYTES_out;
assign STAT_RX_PACKET_512_1023_BYTES_delay = STAT_RX_PACKET_512_1023_BYTES_out;
assign STAT_RX_PACKET_64_BYTES_delay = STAT_RX_PACKET_64_BYTES_out;
assign STAT_RX_PACKET_65_127_BYTES_delay = STAT_RX_PACKET_65_127_BYTES_out;
assign STAT_RX_PACKET_8192_9215_BYTES_delay = STAT_RX_PACKET_8192_9215_BYTES_out;
assign STAT_RX_PACKET_BAD_FCS_delay = STAT_RX_PACKET_BAD_FCS_out;
assign STAT_RX_PACKET_LARGE_delay = STAT_RX_PACKET_LARGE_out;
assign STAT_RX_PACKET_SMALL_delay = STAT_RX_PACKET_SMALL_out;
assign STAT_RX_PAUSE_QUANTA0_delay = STAT_RX_PAUSE_QUANTA0_out;
assign STAT_RX_PAUSE_QUANTA1_delay = STAT_RX_PAUSE_QUANTA1_out;
assign STAT_RX_PAUSE_QUANTA2_delay = STAT_RX_PAUSE_QUANTA2_out;
assign STAT_RX_PAUSE_QUANTA3_delay = STAT_RX_PAUSE_QUANTA3_out;
assign STAT_RX_PAUSE_QUANTA4_delay = STAT_RX_PAUSE_QUANTA4_out;
assign STAT_RX_PAUSE_QUANTA5_delay = STAT_RX_PAUSE_QUANTA5_out;
assign STAT_RX_PAUSE_QUANTA6_delay = STAT_RX_PAUSE_QUANTA6_out;
assign STAT_RX_PAUSE_QUANTA7_delay = STAT_RX_PAUSE_QUANTA7_out;
assign STAT_RX_PAUSE_QUANTA8_delay = STAT_RX_PAUSE_QUANTA8_out;
assign STAT_RX_PAUSE_REQ_delay = STAT_RX_PAUSE_REQ_out;
assign STAT_RX_PAUSE_VALID_delay = STAT_RX_PAUSE_VALID_out;
assign STAT_RX_PAUSE_delay = STAT_RX_PAUSE_out;
assign STAT_RX_RECEIVED_LOCAL_FAULT_delay = STAT_RX_RECEIVED_LOCAL_FAULT_out;
assign STAT_RX_REMOTE_FAULT_delay = STAT_RX_REMOTE_FAULT_out;
assign STAT_RX_STATUS_delay = STAT_RX_STATUS_out;
assign STAT_RX_STOMPED_FCS_delay = STAT_RX_STOMPED_FCS_out;
assign STAT_RX_SYNCED_ERR_delay = STAT_RX_SYNCED_ERR_out;
assign STAT_RX_SYNCED_delay = STAT_RX_SYNCED_out;
assign STAT_RX_TEST_PATTERN_MISMATCH_delay = STAT_RX_TEST_PATTERN_MISMATCH_out;
assign STAT_RX_TOOLONG_delay = STAT_RX_TOOLONG_out;
assign STAT_RX_TOTAL_BYTES_delay = STAT_RX_TOTAL_BYTES_out;
assign STAT_RX_TOTAL_GOOD_BYTES_delay = STAT_RX_TOTAL_GOOD_BYTES_out;
assign STAT_RX_TOTAL_GOOD_PACKETS_delay = STAT_RX_TOTAL_GOOD_PACKETS_out;
assign STAT_RX_TOTAL_PACKETS_delay = STAT_RX_TOTAL_PACKETS_out;
assign STAT_RX_TRUNCATED_delay = STAT_RX_TRUNCATED_out;
assign STAT_RX_UNDERSIZE_delay = STAT_RX_UNDERSIZE_out;
assign STAT_RX_UNICAST_delay = STAT_RX_UNICAST_out;
assign STAT_RX_USER_PAUSE_delay = STAT_RX_USER_PAUSE_out;
assign STAT_RX_VLAN_delay = STAT_RX_VLAN_out;
assign STAT_RX_VL_DEMUXED_delay = STAT_RX_VL_DEMUXED_out;
assign STAT_RX_VL_NUMBER_0_delay = STAT_RX_VL_NUMBER_0_out;
assign STAT_RX_VL_NUMBER_10_delay = STAT_RX_VL_NUMBER_10_out;
assign STAT_RX_VL_NUMBER_11_delay = STAT_RX_VL_NUMBER_11_out;
assign STAT_RX_VL_NUMBER_12_delay = STAT_RX_VL_NUMBER_12_out;
assign STAT_RX_VL_NUMBER_13_delay = STAT_RX_VL_NUMBER_13_out;
assign STAT_RX_VL_NUMBER_14_delay = STAT_RX_VL_NUMBER_14_out;
assign STAT_RX_VL_NUMBER_15_delay = STAT_RX_VL_NUMBER_15_out;
assign STAT_RX_VL_NUMBER_16_delay = STAT_RX_VL_NUMBER_16_out;
assign STAT_RX_VL_NUMBER_17_delay = STAT_RX_VL_NUMBER_17_out;
assign STAT_RX_VL_NUMBER_18_delay = STAT_RX_VL_NUMBER_18_out;
assign STAT_RX_VL_NUMBER_19_delay = STAT_RX_VL_NUMBER_19_out;
assign STAT_RX_VL_NUMBER_1_delay = STAT_RX_VL_NUMBER_1_out;
assign STAT_RX_VL_NUMBER_2_delay = STAT_RX_VL_NUMBER_2_out;
assign STAT_RX_VL_NUMBER_3_delay = STAT_RX_VL_NUMBER_3_out;
assign STAT_RX_VL_NUMBER_4_delay = STAT_RX_VL_NUMBER_4_out;
assign STAT_RX_VL_NUMBER_5_delay = STAT_RX_VL_NUMBER_5_out;
assign STAT_RX_VL_NUMBER_6_delay = STAT_RX_VL_NUMBER_6_out;
assign STAT_RX_VL_NUMBER_7_delay = STAT_RX_VL_NUMBER_7_out;
assign STAT_RX_VL_NUMBER_8_delay = STAT_RX_VL_NUMBER_8_out;
assign STAT_RX_VL_NUMBER_9_delay = STAT_RX_VL_NUMBER_9_out;
assign STAT_TX_BAD_FCS_delay = STAT_TX_BAD_FCS_out;
assign STAT_TX_BROADCAST_delay = STAT_TX_BROADCAST_out;
assign STAT_TX_FRAME_ERROR_delay = STAT_TX_FRAME_ERROR_out;
assign STAT_TX_LOCAL_FAULT_delay = STAT_TX_LOCAL_FAULT_out;
assign STAT_TX_MULTICAST_delay = STAT_TX_MULTICAST_out;
assign STAT_TX_PACKET_1024_1518_BYTES_delay = STAT_TX_PACKET_1024_1518_BYTES_out;
assign STAT_TX_PACKET_128_255_BYTES_delay = STAT_TX_PACKET_128_255_BYTES_out;
assign STAT_TX_PACKET_1519_1522_BYTES_delay = STAT_TX_PACKET_1519_1522_BYTES_out;
assign STAT_TX_PACKET_1523_1548_BYTES_delay = STAT_TX_PACKET_1523_1548_BYTES_out;
assign STAT_TX_PACKET_1549_2047_BYTES_delay = STAT_TX_PACKET_1549_2047_BYTES_out;
assign STAT_TX_PACKET_2048_4095_BYTES_delay = STAT_TX_PACKET_2048_4095_BYTES_out;
assign STAT_TX_PACKET_256_511_BYTES_delay = STAT_TX_PACKET_256_511_BYTES_out;
assign STAT_TX_PACKET_4096_8191_BYTES_delay = STAT_TX_PACKET_4096_8191_BYTES_out;
assign STAT_TX_PACKET_512_1023_BYTES_delay = STAT_TX_PACKET_512_1023_BYTES_out;
assign STAT_TX_PACKET_64_BYTES_delay = STAT_TX_PACKET_64_BYTES_out;
assign STAT_TX_PACKET_65_127_BYTES_delay = STAT_TX_PACKET_65_127_BYTES_out;
assign STAT_TX_PACKET_8192_9215_BYTES_delay = STAT_TX_PACKET_8192_9215_BYTES_out;
assign STAT_TX_PACKET_LARGE_delay = STAT_TX_PACKET_LARGE_out;
assign STAT_TX_PACKET_SMALL_delay = STAT_TX_PACKET_SMALL_out;
assign STAT_TX_PAUSE_VALID_delay = STAT_TX_PAUSE_VALID_out;
assign STAT_TX_PAUSE_delay = STAT_TX_PAUSE_out;
assign STAT_TX_PTP_FIFO_READ_ERROR_delay = STAT_TX_PTP_FIFO_READ_ERROR_out;
assign STAT_TX_PTP_FIFO_WRITE_ERROR_delay = STAT_TX_PTP_FIFO_WRITE_ERROR_out;
assign STAT_TX_TOTAL_BYTES_delay = STAT_TX_TOTAL_BYTES_out;
assign STAT_TX_TOTAL_GOOD_BYTES_delay = STAT_TX_TOTAL_GOOD_BYTES_out;
assign STAT_TX_TOTAL_GOOD_PACKETS_delay = STAT_TX_TOTAL_GOOD_PACKETS_out;
assign STAT_TX_TOTAL_PACKETS_delay = STAT_TX_TOTAL_PACKETS_out;
assign STAT_TX_UNICAST_delay = STAT_TX_UNICAST_out;
assign STAT_TX_USER_PAUSE_delay = STAT_TX_USER_PAUSE_out;
assign STAT_TX_VLAN_delay = STAT_TX_VLAN_out;
assign TX_OVFOUT_delay = TX_OVFOUT_out;
assign TX_PTP_PCSLANE_OUT_delay = TX_PTP_PCSLANE_OUT_out;
assign TX_PTP_TSTAMP_OUT_delay = TX_PTP_TSTAMP_OUT_out;
assign TX_PTP_TSTAMP_TAG_OUT_delay = TX_PTP_TSTAMP_TAG_OUT_out;
assign TX_PTP_TSTAMP_VALID_OUT_delay = TX_PTP_TSTAMP_VALID_OUT_out;
assign TX_RDYOUT_delay = TX_RDYOUT_out;
assign TX_SERDES_ALT_DATA0_delay = TX_SERDES_ALT_DATA0_out;
assign TX_SERDES_ALT_DATA1_delay = TX_SERDES_ALT_DATA1_out;
assign TX_SERDES_ALT_DATA2_delay = TX_SERDES_ALT_DATA2_out;
assign TX_SERDES_ALT_DATA3_delay = TX_SERDES_ALT_DATA3_out;
assign TX_SERDES_DATA0_delay = TX_SERDES_DATA0_out;
assign TX_SERDES_DATA1_delay = TX_SERDES_DATA1_out;
assign TX_SERDES_DATA2_delay = TX_SERDES_DATA2_out;
assign TX_SERDES_DATA3_delay = TX_SERDES_DATA3_out;
assign TX_SERDES_DATA4_delay = TX_SERDES_DATA4_out;
assign TX_SERDES_DATA5_delay = TX_SERDES_DATA5_out;
assign TX_SERDES_DATA6_delay = TX_SERDES_DATA6_out;
assign TX_SERDES_DATA7_delay = TX_SERDES_DATA7_out;
assign TX_SERDES_DATA8_delay = TX_SERDES_DATA8_out;
assign TX_SERDES_DATA9_delay = TX_SERDES_DATA9_out;
assign TX_UNFOUT_delay = TX_UNFOUT_out;
assign CTL_CAUI4_MODE_in = CTL_CAUI4_MODE_delay;
assign CTL_RX_CHECK_ETYPE_GCP_in = CTL_RX_CHECK_ETYPE_GCP_delay;
assign CTL_RX_CHECK_ETYPE_GPP_in = CTL_RX_CHECK_ETYPE_GPP_delay;
assign CTL_RX_CHECK_ETYPE_PCP_in = CTL_RX_CHECK_ETYPE_PCP_delay;
assign CTL_RX_CHECK_ETYPE_PPP_in = CTL_RX_CHECK_ETYPE_PPP_delay;
assign CTL_RX_CHECK_MCAST_GCP_in = CTL_RX_CHECK_MCAST_GCP_delay;
assign CTL_RX_CHECK_MCAST_GPP_in = CTL_RX_CHECK_MCAST_GPP_delay;
assign CTL_RX_CHECK_MCAST_PCP_in = CTL_RX_CHECK_MCAST_PCP_delay;
assign CTL_RX_CHECK_MCAST_PPP_in = CTL_RX_CHECK_MCAST_PPP_delay;
assign CTL_RX_CHECK_OPCODE_GCP_in = CTL_RX_CHECK_OPCODE_GCP_delay;
assign CTL_RX_CHECK_OPCODE_GPP_in = CTL_RX_CHECK_OPCODE_GPP_delay;
assign CTL_RX_CHECK_OPCODE_PCP_in = CTL_RX_CHECK_OPCODE_PCP_delay;
assign CTL_RX_CHECK_OPCODE_PPP_in = CTL_RX_CHECK_OPCODE_PPP_delay;
assign CTL_RX_CHECK_SA_GCP_in = CTL_RX_CHECK_SA_GCP_delay;
assign CTL_RX_CHECK_SA_GPP_in = CTL_RX_CHECK_SA_GPP_delay;
assign CTL_RX_CHECK_SA_PCP_in = CTL_RX_CHECK_SA_PCP_delay;
assign CTL_RX_CHECK_SA_PPP_in = CTL_RX_CHECK_SA_PPP_delay;
assign CTL_RX_CHECK_UCAST_GCP_in = CTL_RX_CHECK_UCAST_GCP_delay;
assign CTL_RX_CHECK_UCAST_GPP_in = CTL_RX_CHECK_UCAST_GPP_delay;
assign CTL_RX_CHECK_UCAST_PCP_in = CTL_RX_CHECK_UCAST_PCP_delay;
assign CTL_RX_CHECK_UCAST_PPP_in = CTL_RX_CHECK_UCAST_PPP_delay;
assign CTL_RX_ENABLE_GCP_in = CTL_RX_ENABLE_GCP_delay;
assign CTL_RX_ENABLE_GPP_in = CTL_RX_ENABLE_GPP_delay;
assign CTL_RX_ENABLE_PCP_in = CTL_RX_ENABLE_PCP_delay;
assign CTL_RX_ENABLE_PPP_in = CTL_RX_ENABLE_PPP_delay;
assign CTL_RX_ENABLE_in = CTL_RX_ENABLE_delay;
assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay;
assign CTL_RX_PAUSE_ACK_in = CTL_RX_PAUSE_ACK_delay;
assign CTL_RX_PAUSE_ENABLE_in = CTL_RX_PAUSE_ENABLE_delay;
assign CTL_RX_SYSTEMTIMERIN_in = CTL_RX_SYSTEMTIMERIN_delay;
assign CTL_RX_TEST_PATTERN_in = CTL_RX_TEST_PATTERN_delay;
assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay;
assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay;
assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay;
assign CTL_TX_PAUSE_ENABLE_in = CTL_TX_PAUSE_ENABLE_delay;
assign CTL_TX_PAUSE_QUANTA0_in = CTL_TX_PAUSE_QUANTA0_delay;
assign CTL_TX_PAUSE_QUANTA1_in = CTL_TX_PAUSE_QUANTA1_delay;
assign CTL_TX_PAUSE_QUANTA2_in = CTL_TX_PAUSE_QUANTA2_delay;
assign CTL_TX_PAUSE_QUANTA3_in = CTL_TX_PAUSE_QUANTA3_delay;
assign CTL_TX_PAUSE_QUANTA4_in = CTL_TX_PAUSE_QUANTA4_delay;
assign CTL_TX_PAUSE_QUANTA5_in = CTL_TX_PAUSE_QUANTA5_delay;
assign CTL_TX_PAUSE_QUANTA6_in = CTL_TX_PAUSE_QUANTA6_delay;
assign CTL_TX_PAUSE_QUANTA7_in = CTL_TX_PAUSE_QUANTA7_delay;
assign CTL_TX_PAUSE_QUANTA8_in = CTL_TX_PAUSE_QUANTA8_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER0_in = CTL_TX_PAUSE_REFRESH_TIMER0_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER1_in = CTL_TX_PAUSE_REFRESH_TIMER1_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER2_in = CTL_TX_PAUSE_REFRESH_TIMER2_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER3_in = CTL_TX_PAUSE_REFRESH_TIMER3_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER4_in = CTL_TX_PAUSE_REFRESH_TIMER4_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER5_in = CTL_TX_PAUSE_REFRESH_TIMER5_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER6_in = CTL_TX_PAUSE_REFRESH_TIMER6_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER7_in = CTL_TX_PAUSE_REFRESH_TIMER7_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER8_in = CTL_TX_PAUSE_REFRESH_TIMER8_delay;
assign CTL_TX_PAUSE_REQ_in = CTL_TX_PAUSE_REQ_delay;
assign CTL_TX_PTP_VLANE_ADJUST_MODE_in = CTL_TX_PTP_VLANE_ADJUST_MODE_delay;
assign CTL_TX_RESEND_PAUSE_in = CTL_TX_RESEND_PAUSE_delay;
assign CTL_TX_SEND_IDLE_in = CTL_TX_SEND_IDLE_delay;
assign CTL_TX_SEND_RFI_in = CTL_TX_SEND_RFI_delay;
assign CTL_TX_SYSTEMTIMERIN_in = CTL_TX_SYSTEMTIMERIN_delay;
assign CTL_TX_TEST_PATTERN_in = CTL_TX_TEST_PATTERN_delay;
assign DRP_ADDR_in = DRP_ADDR_delay;
assign DRP_CLK_in = DRP_CLK_delay;
assign DRP_DI_in = DRP_DI_delay;
assign DRP_EN_in = DRP_EN_delay;
assign DRP_WE_in = DRP_WE_delay;
assign RX_CLK_in = RX_CLK_delay;
assign RX_RESET_in = RX_RESET_delay;
assign RX_SERDES_ALT_DATA0_in = RX_SERDES_ALT_DATA0_delay;
assign RX_SERDES_ALT_DATA1_in = RX_SERDES_ALT_DATA1_delay;
assign RX_SERDES_ALT_DATA2_in = RX_SERDES_ALT_DATA2_delay;
assign RX_SERDES_ALT_DATA3_in = RX_SERDES_ALT_DATA3_delay;
assign RX_SERDES_CLK_in = RX_SERDES_CLK_delay;
assign RX_SERDES_DATA0_in = RX_SERDES_DATA0_delay;
assign RX_SERDES_DATA1_in = RX_SERDES_DATA1_delay;
assign RX_SERDES_DATA2_in = RX_SERDES_DATA2_delay;
assign RX_SERDES_DATA3_in = RX_SERDES_DATA3_delay;
assign RX_SERDES_DATA4_in = RX_SERDES_DATA4_delay;
assign RX_SERDES_DATA5_in = RX_SERDES_DATA5_delay;
assign RX_SERDES_DATA6_in = RX_SERDES_DATA6_delay;
assign RX_SERDES_DATA7_in = RX_SERDES_DATA7_delay;
assign RX_SERDES_DATA8_in = RX_SERDES_DATA8_delay;
assign RX_SERDES_DATA9_in = RX_SERDES_DATA9_delay;
assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay;
assign TX_CLK_in = TX_CLK_delay;
assign TX_DATAIN0_in = TX_DATAIN0_delay;
assign TX_DATAIN1_in = TX_DATAIN1_delay;
assign TX_DATAIN2_in = TX_DATAIN2_delay;
assign TX_DATAIN3_in = TX_DATAIN3_delay;
assign TX_ENAIN0_in = TX_ENAIN0_delay;
assign TX_ENAIN1_in = TX_ENAIN1_delay;
assign TX_ENAIN2_in = TX_ENAIN2_delay;
assign TX_ENAIN3_in = TX_ENAIN3_delay;
assign TX_EOPIN0_in = TX_EOPIN0_delay;
assign TX_EOPIN1_in = TX_EOPIN1_delay;
assign TX_EOPIN2_in = TX_EOPIN2_delay;
assign TX_EOPIN3_in = TX_EOPIN3_delay;
assign TX_ERRIN0_in = TX_ERRIN0_delay;
assign TX_ERRIN1_in = TX_ERRIN1_delay;
assign TX_ERRIN2_in = TX_ERRIN2_delay;
assign TX_ERRIN3_in = TX_ERRIN3_delay;
assign TX_MTYIN0_in = TX_MTYIN0_delay;
assign TX_MTYIN1_in = TX_MTYIN1_delay;
assign TX_MTYIN2_in = TX_MTYIN2_delay;
assign TX_MTYIN3_in = TX_MTYIN3_delay;
assign TX_PTP_1588OP_IN_in = TX_PTP_1588OP_IN_delay;
assign TX_PTP_CHKSUM_OFFSET_IN_in = TX_PTP_CHKSUM_OFFSET_IN_delay;
assign TX_PTP_RXTSTAMP_IN_in = TX_PTP_RXTSTAMP_IN_delay;
assign TX_PTP_TAG_FIELD_IN_in = TX_PTP_TAG_FIELD_IN_delay;
assign TX_PTP_TSTAMP_OFFSET_IN_in = TX_PTP_TSTAMP_OFFSET_IN_delay;
assign TX_PTP_UPD_CHKSUM_IN_in = TX_PTP_UPD_CHKSUM_IN_delay;
assign TX_RESET_in = TX_RESET_delay;
assign TX_SOPIN0_in = TX_SOPIN0_delay;
assign TX_SOPIN1_in = TX_SOPIN1_delay;
assign TX_SOPIN2_in = TX_SOPIN2_delay;
assign TX_SOPIN3_in = TX_SOPIN3_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((CTL_PTP_TRANSPCLK_MODE_REG != "FALSE") &&
(CTL_PTP_TRANSPCLK_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_PTP_TRANSPCLK_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_PTP_TRANSPCLK_MODE_REG);
attr_err = 1'b1;
end
if ((CTL_RX_CHECK_ACK_REG != "TRUE") &&
(CTL_RX_CHECK_ACK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_CHECK_ACK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CTL_RX_CHECK_ACK_REG);
attr_err = 1'b1;
end
if ((CTL_RX_CHECK_PREAMBLE_REG != "FALSE") &&
(CTL_RX_CHECK_PREAMBLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_CHECK_PREAMBLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_RX_CHECK_PREAMBLE_REG);
attr_err = 1'b1;
end
if ((CTL_RX_CHECK_SFD_REG != "FALSE") &&
(CTL_RX_CHECK_SFD_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_CHECK_SFD on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_RX_CHECK_SFD_REG);
attr_err = 1'b1;
end
if ((CTL_RX_DELETE_FCS_REG != "TRUE") &&
(CTL_RX_DELETE_FCS_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_DELETE_FCS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CTL_RX_DELETE_FCS_REG);
attr_err = 1'b1;
end
if ((CTL_RX_FORWARD_CONTROL_REG != "FALSE") &&
(CTL_RX_FORWARD_CONTROL_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_FORWARD_CONTROL on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_RX_FORWARD_CONTROL_REG);
attr_err = 1'b1;
end
if ((CTL_RX_IGNORE_FCS_REG != "FALSE") &&
(CTL_RX_IGNORE_FCS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_IGNORE_FCS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_RX_IGNORE_FCS_REG);
attr_err = 1'b1;
end
if ((CTL_RX_PROCESS_LFI_REG != "FALSE") &&
(CTL_RX_PROCESS_LFI_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_PROCESS_LFI on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_RX_PROCESS_LFI_REG);
attr_err = 1'b1;
end
if ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(CTL_TEST_MODE_PIN_CHAR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_TEST_MODE_PIN_CHAR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if ((CTL_TX_FCS_INS_ENABLE_REG != "TRUE") &&
(CTL_TX_FCS_INS_ENABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CTL_TX_FCS_INS_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CTL_TX_FCS_INS_ENABLE_REG);
attr_err = 1'b1;
end
if ((CTL_TX_IGNORE_FCS_REG != "FALSE") &&
(CTL_TX_IGNORE_FCS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_TX_IGNORE_FCS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_TX_IGNORE_FCS_REG);
attr_err = 1'b1;
end
if ((CTL_TX_PTP_1STEP_ENABLE_REG != "FALSE") &&
(CTL_TX_PTP_1STEP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_TX_PTP_1STEP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_TX_PTP_1STEP_ENABLE_REG);
attr_err = 1'b1;
end
if ((TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(TEST_MODE_PIN_CHAR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TEST_MODE_PIN_CHAR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign SCAN_EN_N_in = 1'b1; // tie off
assign SCAN_IN_in = 195'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign TEST_MODE_N_in = 1'b1; // tie off
assign TEST_RESET_in = 1'b1; // tie off
SIP_CMAC SIP_CMAC_INST (
.CTL_PTP_TRANSPCLK_MODE (CTL_PTP_TRANSPCLK_MODE_REG),
.CTL_RX_CHECK_ACK (CTL_RX_CHECK_ACK_REG),
.CTL_RX_CHECK_PREAMBLE (CTL_RX_CHECK_PREAMBLE_REG),
.CTL_RX_CHECK_SFD (CTL_RX_CHECK_SFD_REG),
.CTL_RX_DELETE_FCS (CTL_RX_DELETE_FCS_REG),
.CTL_RX_ETYPE_GCP (CTL_RX_ETYPE_GCP_REG),
.CTL_RX_ETYPE_GPP (CTL_RX_ETYPE_GPP_REG),
.CTL_RX_ETYPE_PCP (CTL_RX_ETYPE_PCP_REG),
.CTL_RX_ETYPE_PPP (CTL_RX_ETYPE_PPP_REG),
.CTL_RX_FORWARD_CONTROL (CTL_RX_FORWARD_CONTROL_REG),
.CTL_RX_IGNORE_FCS (CTL_RX_IGNORE_FCS_REG),
.CTL_RX_MAX_PACKET_LEN (CTL_RX_MAX_PACKET_LEN_REG),
.CTL_RX_MIN_PACKET_LEN (CTL_RX_MIN_PACKET_LEN_REG),
.CTL_RX_OPCODE_GPP (CTL_RX_OPCODE_GPP_REG),
.CTL_RX_OPCODE_MAX_GCP (CTL_RX_OPCODE_MAX_GCP_REG),
.CTL_RX_OPCODE_MAX_PCP (CTL_RX_OPCODE_MAX_PCP_REG),
.CTL_RX_OPCODE_MIN_GCP (CTL_RX_OPCODE_MIN_GCP_REG),
.CTL_RX_OPCODE_MIN_PCP (CTL_RX_OPCODE_MIN_PCP_REG),
.CTL_RX_OPCODE_PPP (CTL_RX_OPCODE_PPP_REG),
.CTL_RX_PAUSE_DA_MCAST (CTL_RX_PAUSE_DA_MCAST_REG),
.CTL_RX_PAUSE_DA_UCAST (CTL_RX_PAUSE_DA_UCAST_REG),
.CTL_RX_PAUSE_SA (CTL_RX_PAUSE_SA_REG),
.CTL_RX_PROCESS_LFI (CTL_RX_PROCESS_LFI_REG),
.CTL_RX_VL_LENGTH_MINUS1 (CTL_RX_VL_LENGTH_MINUS1_REG),
.CTL_RX_VL_MARKER_ID0 (CTL_RX_VL_MARKER_ID0_REG),
.CTL_RX_VL_MARKER_ID1 (CTL_RX_VL_MARKER_ID1_REG),
.CTL_RX_VL_MARKER_ID10 (CTL_RX_VL_MARKER_ID10_REG),
.CTL_RX_VL_MARKER_ID11 (CTL_RX_VL_MARKER_ID11_REG),
.CTL_RX_VL_MARKER_ID12 (CTL_RX_VL_MARKER_ID12_REG),
.CTL_RX_VL_MARKER_ID13 (CTL_RX_VL_MARKER_ID13_REG),
.CTL_RX_VL_MARKER_ID14 (CTL_RX_VL_MARKER_ID14_REG),
.CTL_RX_VL_MARKER_ID15 (CTL_RX_VL_MARKER_ID15_REG),
.CTL_RX_VL_MARKER_ID16 (CTL_RX_VL_MARKER_ID16_REG),
.CTL_RX_VL_MARKER_ID17 (CTL_RX_VL_MARKER_ID17_REG),
.CTL_RX_VL_MARKER_ID18 (CTL_RX_VL_MARKER_ID18_REG),
.CTL_RX_VL_MARKER_ID19 (CTL_RX_VL_MARKER_ID19_REG),
.CTL_RX_VL_MARKER_ID2 (CTL_RX_VL_MARKER_ID2_REG),
.CTL_RX_VL_MARKER_ID3 (CTL_RX_VL_MARKER_ID3_REG),
.CTL_RX_VL_MARKER_ID4 (CTL_RX_VL_MARKER_ID4_REG),
.CTL_RX_VL_MARKER_ID5 (CTL_RX_VL_MARKER_ID5_REG),
.CTL_RX_VL_MARKER_ID6 (CTL_RX_VL_MARKER_ID6_REG),
.CTL_RX_VL_MARKER_ID7 (CTL_RX_VL_MARKER_ID7_REG),
.CTL_RX_VL_MARKER_ID8 (CTL_RX_VL_MARKER_ID8_REG),
.CTL_RX_VL_MARKER_ID9 (CTL_RX_VL_MARKER_ID9_REG),
.CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG),
.CTL_TX_DA_GPP (CTL_TX_DA_GPP_REG),
.CTL_TX_DA_PPP (CTL_TX_DA_PPP_REG),
.CTL_TX_ETHERTYPE_GPP (CTL_TX_ETHERTYPE_GPP_REG),
.CTL_TX_ETHERTYPE_PPP (CTL_TX_ETHERTYPE_PPP_REG),
.CTL_TX_FCS_INS_ENABLE (CTL_TX_FCS_INS_ENABLE_REG),
.CTL_TX_IGNORE_FCS (CTL_TX_IGNORE_FCS_REG),
.CTL_TX_OPCODE_GPP (CTL_TX_OPCODE_GPP_REG),
.CTL_TX_OPCODE_PPP (CTL_TX_OPCODE_PPP_REG),
.CTL_TX_PTP_1STEP_ENABLE (CTL_TX_PTP_1STEP_ENABLE_REG),
.CTL_TX_PTP_LATENCY_ADJUST (CTL_TX_PTP_LATENCY_ADJUST_REG),
.CTL_TX_SA_GPP (CTL_TX_SA_GPP_REG),
.CTL_TX_SA_PPP (CTL_TX_SA_PPP_REG),
.CTL_TX_VL_LENGTH_MINUS1 (CTL_TX_VL_LENGTH_MINUS1_REG),
.CTL_TX_VL_MARKER_ID0 (CTL_TX_VL_MARKER_ID0_REG),
.CTL_TX_VL_MARKER_ID1 (CTL_TX_VL_MARKER_ID1_REG),
.CTL_TX_VL_MARKER_ID10 (CTL_TX_VL_MARKER_ID10_REG),
.CTL_TX_VL_MARKER_ID11 (CTL_TX_VL_MARKER_ID11_REG),
.CTL_TX_VL_MARKER_ID12 (CTL_TX_VL_MARKER_ID12_REG),
.CTL_TX_VL_MARKER_ID13 (CTL_TX_VL_MARKER_ID13_REG),
.CTL_TX_VL_MARKER_ID14 (CTL_TX_VL_MARKER_ID14_REG),
.CTL_TX_VL_MARKER_ID15 (CTL_TX_VL_MARKER_ID15_REG),
.CTL_TX_VL_MARKER_ID16 (CTL_TX_VL_MARKER_ID16_REG),
.CTL_TX_VL_MARKER_ID17 (CTL_TX_VL_MARKER_ID17_REG),
.CTL_TX_VL_MARKER_ID18 (CTL_TX_VL_MARKER_ID18_REG),
.CTL_TX_VL_MARKER_ID19 (CTL_TX_VL_MARKER_ID19_REG),
.CTL_TX_VL_MARKER_ID2 (CTL_TX_VL_MARKER_ID2_REG),
.CTL_TX_VL_MARKER_ID3 (CTL_TX_VL_MARKER_ID3_REG),
.CTL_TX_VL_MARKER_ID4 (CTL_TX_VL_MARKER_ID4_REG),
.CTL_TX_VL_MARKER_ID5 (CTL_TX_VL_MARKER_ID5_REG),
.CTL_TX_VL_MARKER_ID6 (CTL_TX_VL_MARKER_ID6_REG),
.CTL_TX_VL_MARKER_ID7 (CTL_TX_VL_MARKER_ID7_REG),
.CTL_TX_VL_MARKER_ID8 (CTL_TX_VL_MARKER_ID8_REG),
.CTL_TX_VL_MARKER_ID9 (CTL_TX_VL_MARKER_ID9_REG),
.TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG),
.DRP_DO (DRP_DO_out),
.DRP_RDY (DRP_RDY_out),
.RX_DATAOUT0 (RX_DATAOUT0_out),
.RX_DATAOUT1 (RX_DATAOUT1_out),
.RX_DATAOUT2 (RX_DATAOUT2_out),
.RX_DATAOUT3 (RX_DATAOUT3_out),
.RX_ENAOUT0 (RX_ENAOUT0_out),
.RX_ENAOUT1 (RX_ENAOUT1_out),
.RX_ENAOUT2 (RX_ENAOUT2_out),
.RX_ENAOUT3 (RX_ENAOUT3_out),
.RX_EOPOUT0 (RX_EOPOUT0_out),
.RX_EOPOUT1 (RX_EOPOUT1_out),
.RX_EOPOUT2 (RX_EOPOUT2_out),
.RX_EOPOUT3 (RX_EOPOUT3_out),
.RX_ERROUT0 (RX_ERROUT0_out),
.RX_ERROUT1 (RX_ERROUT1_out),
.RX_ERROUT2 (RX_ERROUT2_out),
.RX_ERROUT3 (RX_ERROUT3_out),
.RX_LANE_ALIGNER_FILL_0 (RX_LANE_ALIGNER_FILL_0_out),
.RX_LANE_ALIGNER_FILL_1 (RX_LANE_ALIGNER_FILL_1_out),
.RX_LANE_ALIGNER_FILL_10 (RX_LANE_ALIGNER_FILL_10_out),
.RX_LANE_ALIGNER_FILL_11 (RX_LANE_ALIGNER_FILL_11_out),
.RX_LANE_ALIGNER_FILL_12 (RX_LANE_ALIGNER_FILL_12_out),
.RX_LANE_ALIGNER_FILL_13 (RX_LANE_ALIGNER_FILL_13_out),
.RX_LANE_ALIGNER_FILL_14 (RX_LANE_ALIGNER_FILL_14_out),
.RX_LANE_ALIGNER_FILL_15 (RX_LANE_ALIGNER_FILL_15_out),
.RX_LANE_ALIGNER_FILL_16 (RX_LANE_ALIGNER_FILL_16_out),
.RX_LANE_ALIGNER_FILL_17 (RX_LANE_ALIGNER_FILL_17_out),
.RX_LANE_ALIGNER_FILL_18 (RX_LANE_ALIGNER_FILL_18_out),
.RX_LANE_ALIGNER_FILL_19 (RX_LANE_ALIGNER_FILL_19_out),
.RX_LANE_ALIGNER_FILL_2 (RX_LANE_ALIGNER_FILL_2_out),
.RX_LANE_ALIGNER_FILL_3 (RX_LANE_ALIGNER_FILL_3_out),
.RX_LANE_ALIGNER_FILL_4 (RX_LANE_ALIGNER_FILL_4_out),
.RX_LANE_ALIGNER_FILL_5 (RX_LANE_ALIGNER_FILL_5_out),
.RX_LANE_ALIGNER_FILL_6 (RX_LANE_ALIGNER_FILL_6_out),
.RX_LANE_ALIGNER_FILL_7 (RX_LANE_ALIGNER_FILL_7_out),
.RX_LANE_ALIGNER_FILL_8 (RX_LANE_ALIGNER_FILL_8_out),
.RX_LANE_ALIGNER_FILL_9 (RX_LANE_ALIGNER_FILL_9_out),
.RX_MTYOUT0 (RX_MTYOUT0_out),
.RX_MTYOUT1 (RX_MTYOUT1_out),
.RX_MTYOUT2 (RX_MTYOUT2_out),
.RX_MTYOUT3 (RX_MTYOUT3_out),
.RX_PTP_PCSLANE_OUT (RX_PTP_PCSLANE_OUT_out),
.RX_PTP_TSTAMP_OUT (RX_PTP_TSTAMP_OUT_out),
.RX_SOPOUT0 (RX_SOPOUT0_out),
.RX_SOPOUT1 (RX_SOPOUT1_out),
.RX_SOPOUT2 (RX_SOPOUT2_out),
.RX_SOPOUT3 (RX_SOPOUT3_out),
.SCAN_OUT (SCAN_OUT_out),
.STAT_RX_ALIGNED (STAT_RX_ALIGNED_out),
.STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out),
.STAT_RX_BAD_CODE (STAT_RX_BAD_CODE_out),
.STAT_RX_BAD_FCS (STAT_RX_BAD_FCS_out),
.STAT_RX_BAD_PREAMBLE (STAT_RX_BAD_PREAMBLE_out),
.STAT_RX_BAD_SFD (STAT_RX_BAD_SFD_out),
.STAT_RX_BIP_ERR_0 (STAT_RX_BIP_ERR_0_out),
.STAT_RX_BIP_ERR_1 (STAT_RX_BIP_ERR_1_out),
.STAT_RX_BIP_ERR_10 (STAT_RX_BIP_ERR_10_out),
.STAT_RX_BIP_ERR_11 (STAT_RX_BIP_ERR_11_out),
.STAT_RX_BIP_ERR_12 (STAT_RX_BIP_ERR_12_out),
.STAT_RX_BIP_ERR_13 (STAT_RX_BIP_ERR_13_out),
.STAT_RX_BIP_ERR_14 (STAT_RX_BIP_ERR_14_out),
.STAT_RX_BIP_ERR_15 (STAT_RX_BIP_ERR_15_out),
.STAT_RX_BIP_ERR_16 (STAT_RX_BIP_ERR_16_out),
.STAT_RX_BIP_ERR_17 (STAT_RX_BIP_ERR_17_out),
.STAT_RX_BIP_ERR_18 (STAT_RX_BIP_ERR_18_out),
.STAT_RX_BIP_ERR_19 (STAT_RX_BIP_ERR_19_out),
.STAT_RX_BIP_ERR_2 (STAT_RX_BIP_ERR_2_out),
.STAT_RX_BIP_ERR_3 (STAT_RX_BIP_ERR_3_out),
.STAT_RX_BIP_ERR_4 (STAT_RX_BIP_ERR_4_out),
.STAT_RX_BIP_ERR_5 (STAT_RX_BIP_ERR_5_out),
.STAT_RX_BIP_ERR_6 (STAT_RX_BIP_ERR_6_out),
.STAT_RX_BIP_ERR_7 (STAT_RX_BIP_ERR_7_out),
.STAT_RX_BIP_ERR_8 (STAT_RX_BIP_ERR_8_out),
.STAT_RX_BIP_ERR_9 (STAT_RX_BIP_ERR_9_out),
.STAT_RX_BLOCK_LOCK (STAT_RX_BLOCK_LOCK_out),
.STAT_RX_BROADCAST (STAT_RX_BROADCAST_out),
.STAT_RX_FRAGMENT (STAT_RX_FRAGMENT_out),
.STAT_RX_FRAMING_ERR_0 (STAT_RX_FRAMING_ERR_0_out),
.STAT_RX_FRAMING_ERR_1 (STAT_RX_FRAMING_ERR_1_out),
.STAT_RX_FRAMING_ERR_10 (STAT_RX_FRAMING_ERR_10_out),
.STAT_RX_FRAMING_ERR_11 (STAT_RX_FRAMING_ERR_11_out),
.STAT_RX_FRAMING_ERR_12 (STAT_RX_FRAMING_ERR_12_out),
.STAT_RX_FRAMING_ERR_13 (STAT_RX_FRAMING_ERR_13_out),
.STAT_RX_FRAMING_ERR_14 (STAT_RX_FRAMING_ERR_14_out),
.STAT_RX_FRAMING_ERR_15 (STAT_RX_FRAMING_ERR_15_out),
.STAT_RX_FRAMING_ERR_16 (STAT_RX_FRAMING_ERR_16_out),
.STAT_RX_FRAMING_ERR_17 (STAT_RX_FRAMING_ERR_17_out),
.STAT_RX_FRAMING_ERR_18 (STAT_RX_FRAMING_ERR_18_out),
.STAT_RX_FRAMING_ERR_19 (STAT_RX_FRAMING_ERR_19_out),
.STAT_RX_FRAMING_ERR_2 (STAT_RX_FRAMING_ERR_2_out),
.STAT_RX_FRAMING_ERR_3 (STAT_RX_FRAMING_ERR_3_out),
.STAT_RX_FRAMING_ERR_4 (STAT_RX_FRAMING_ERR_4_out),
.STAT_RX_FRAMING_ERR_5 (STAT_RX_FRAMING_ERR_5_out),
.STAT_RX_FRAMING_ERR_6 (STAT_RX_FRAMING_ERR_6_out),
.STAT_RX_FRAMING_ERR_7 (STAT_RX_FRAMING_ERR_7_out),
.STAT_RX_FRAMING_ERR_8 (STAT_RX_FRAMING_ERR_8_out),
.STAT_RX_FRAMING_ERR_9 (STAT_RX_FRAMING_ERR_9_out),
.STAT_RX_FRAMING_ERR_VALID_0 (STAT_RX_FRAMING_ERR_VALID_0_out),
.STAT_RX_FRAMING_ERR_VALID_1 (STAT_RX_FRAMING_ERR_VALID_1_out),
.STAT_RX_FRAMING_ERR_VALID_10 (STAT_RX_FRAMING_ERR_VALID_10_out),
.STAT_RX_FRAMING_ERR_VALID_11 (STAT_RX_FRAMING_ERR_VALID_11_out),
.STAT_RX_FRAMING_ERR_VALID_12 (STAT_RX_FRAMING_ERR_VALID_12_out),
.STAT_RX_FRAMING_ERR_VALID_13 (STAT_RX_FRAMING_ERR_VALID_13_out),
.STAT_RX_FRAMING_ERR_VALID_14 (STAT_RX_FRAMING_ERR_VALID_14_out),
.STAT_RX_FRAMING_ERR_VALID_15 (STAT_RX_FRAMING_ERR_VALID_15_out),
.STAT_RX_FRAMING_ERR_VALID_16 (STAT_RX_FRAMING_ERR_VALID_16_out),
.STAT_RX_FRAMING_ERR_VALID_17 (STAT_RX_FRAMING_ERR_VALID_17_out),
.STAT_RX_FRAMING_ERR_VALID_18 (STAT_RX_FRAMING_ERR_VALID_18_out),
.STAT_RX_FRAMING_ERR_VALID_19 (STAT_RX_FRAMING_ERR_VALID_19_out),
.STAT_RX_FRAMING_ERR_VALID_2 (STAT_RX_FRAMING_ERR_VALID_2_out),
.STAT_RX_FRAMING_ERR_VALID_3 (STAT_RX_FRAMING_ERR_VALID_3_out),
.STAT_RX_FRAMING_ERR_VALID_4 (STAT_RX_FRAMING_ERR_VALID_4_out),
.STAT_RX_FRAMING_ERR_VALID_5 (STAT_RX_FRAMING_ERR_VALID_5_out),
.STAT_RX_FRAMING_ERR_VALID_6 (STAT_RX_FRAMING_ERR_VALID_6_out),
.STAT_RX_FRAMING_ERR_VALID_7 (STAT_RX_FRAMING_ERR_VALID_7_out),
.STAT_RX_FRAMING_ERR_VALID_8 (STAT_RX_FRAMING_ERR_VALID_8_out),
.STAT_RX_FRAMING_ERR_VALID_9 (STAT_RX_FRAMING_ERR_VALID_9_out),
.STAT_RX_GOT_SIGNAL_OS (STAT_RX_GOT_SIGNAL_OS_out),
.STAT_RX_HI_BER (STAT_RX_HI_BER_out),
.STAT_RX_INRANGEERR (STAT_RX_INRANGEERR_out),
.STAT_RX_INTERNAL_LOCAL_FAULT (STAT_RX_INTERNAL_LOCAL_FAULT_out),
.STAT_RX_JABBER (STAT_RX_JABBER_out),
.STAT_RX_LANE0_VLM_BIP7 (STAT_RX_LANE0_VLM_BIP7_out),
.STAT_RX_LANE0_VLM_BIP7_VALID (STAT_RX_LANE0_VLM_BIP7_VALID_out),
.STAT_RX_LOCAL_FAULT (STAT_RX_LOCAL_FAULT_out),
.STAT_RX_MF_ERR (STAT_RX_MF_ERR_out),
.STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out),
.STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out),
.STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out),
.STAT_RX_MULTICAST (STAT_RX_MULTICAST_out),
.STAT_RX_OVERSIZE (STAT_RX_OVERSIZE_out),
.STAT_RX_PACKET_1024_1518_BYTES (STAT_RX_PACKET_1024_1518_BYTES_out),
.STAT_RX_PACKET_128_255_BYTES (STAT_RX_PACKET_128_255_BYTES_out),
.STAT_RX_PACKET_1519_1522_BYTES (STAT_RX_PACKET_1519_1522_BYTES_out),
.STAT_RX_PACKET_1523_1548_BYTES (STAT_RX_PACKET_1523_1548_BYTES_out),
.STAT_RX_PACKET_1549_2047_BYTES (STAT_RX_PACKET_1549_2047_BYTES_out),
.STAT_RX_PACKET_2048_4095_BYTES (STAT_RX_PACKET_2048_4095_BYTES_out),
.STAT_RX_PACKET_256_511_BYTES (STAT_RX_PACKET_256_511_BYTES_out),
.STAT_RX_PACKET_4096_8191_BYTES (STAT_RX_PACKET_4096_8191_BYTES_out),
.STAT_RX_PACKET_512_1023_BYTES (STAT_RX_PACKET_512_1023_BYTES_out),
.STAT_RX_PACKET_64_BYTES (STAT_RX_PACKET_64_BYTES_out),
.STAT_RX_PACKET_65_127_BYTES (STAT_RX_PACKET_65_127_BYTES_out),
.STAT_RX_PACKET_8192_9215_BYTES (STAT_RX_PACKET_8192_9215_BYTES_out),
.STAT_RX_PACKET_BAD_FCS (STAT_RX_PACKET_BAD_FCS_out),
.STAT_RX_PACKET_LARGE (STAT_RX_PACKET_LARGE_out),
.STAT_RX_PACKET_SMALL (STAT_RX_PACKET_SMALL_out),
.STAT_RX_PAUSE (STAT_RX_PAUSE_out),
.STAT_RX_PAUSE_QUANTA0 (STAT_RX_PAUSE_QUANTA0_out),
.STAT_RX_PAUSE_QUANTA1 (STAT_RX_PAUSE_QUANTA1_out),
.STAT_RX_PAUSE_QUANTA2 (STAT_RX_PAUSE_QUANTA2_out),
.STAT_RX_PAUSE_QUANTA3 (STAT_RX_PAUSE_QUANTA3_out),
.STAT_RX_PAUSE_QUANTA4 (STAT_RX_PAUSE_QUANTA4_out),
.STAT_RX_PAUSE_QUANTA5 (STAT_RX_PAUSE_QUANTA5_out),
.STAT_RX_PAUSE_QUANTA6 (STAT_RX_PAUSE_QUANTA6_out),
.STAT_RX_PAUSE_QUANTA7 (STAT_RX_PAUSE_QUANTA7_out),
.STAT_RX_PAUSE_QUANTA8 (STAT_RX_PAUSE_QUANTA8_out),
.STAT_RX_PAUSE_REQ (STAT_RX_PAUSE_REQ_out),
.STAT_RX_PAUSE_VALID (STAT_RX_PAUSE_VALID_out),
.STAT_RX_RECEIVED_LOCAL_FAULT (STAT_RX_RECEIVED_LOCAL_FAULT_out),
.STAT_RX_REMOTE_FAULT (STAT_RX_REMOTE_FAULT_out),
.STAT_RX_STATUS (STAT_RX_STATUS_out),
.STAT_RX_STOMPED_FCS (STAT_RX_STOMPED_FCS_out),
.STAT_RX_SYNCED (STAT_RX_SYNCED_out),
.STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out),
.STAT_RX_TEST_PATTERN_MISMATCH (STAT_RX_TEST_PATTERN_MISMATCH_out),
.STAT_RX_TOOLONG (STAT_RX_TOOLONG_out),
.STAT_RX_TOTAL_BYTES (STAT_RX_TOTAL_BYTES_out),
.STAT_RX_TOTAL_GOOD_BYTES (STAT_RX_TOTAL_GOOD_BYTES_out),
.STAT_RX_TOTAL_GOOD_PACKETS (STAT_RX_TOTAL_GOOD_PACKETS_out),
.STAT_RX_TOTAL_PACKETS (STAT_RX_TOTAL_PACKETS_out),
.STAT_RX_TRUNCATED (STAT_RX_TRUNCATED_out),
.STAT_RX_UNDERSIZE (STAT_RX_UNDERSIZE_out),
.STAT_RX_UNICAST (STAT_RX_UNICAST_out),
.STAT_RX_USER_PAUSE (STAT_RX_USER_PAUSE_out),
.STAT_RX_VLAN (STAT_RX_VLAN_out),
.STAT_RX_VL_DEMUXED (STAT_RX_VL_DEMUXED_out),
.STAT_RX_VL_NUMBER_0 (STAT_RX_VL_NUMBER_0_out),
.STAT_RX_VL_NUMBER_1 (STAT_RX_VL_NUMBER_1_out),
.STAT_RX_VL_NUMBER_10 (STAT_RX_VL_NUMBER_10_out),
.STAT_RX_VL_NUMBER_11 (STAT_RX_VL_NUMBER_11_out),
.STAT_RX_VL_NUMBER_12 (STAT_RX_VL_NUMBER_12_out),
.STAT_RX_VL_NUMBER_13 (STAT_RX_VL_NUMBER_13_out),
.STAT_RX_VL_NUMBER_14 (STAT_RX_VL_NUMBER_14_out),
.STAT_RX_VL_NUMBER_15 (STAT_RX_VL_NUMBER_15_out),
.STAT_RX_VL_NUMBER_16 (STAT_RX_VL_NUMBER_16_out),
.STAT_RX_VL_NUMBER_17 (STAT_RX_VL_NUMBER_17_out),
.STAT_RX_VL_NUMBER_18 (STAT_RX_VL_NUMBER_18_out),
.STAT_RX_VL_NUMBER_19 (STAT_RX_VL_NUMBER_19_out),
.STAT_RX_VL_NUMBER_2 (STAT_RX_VL_NUMBER_2_out),
.STAT_RX_VL_NUMBER_3 (STAT_RX_VL_NUMBER_3_out),
.STAT_RX_VL_NUMBER_4 (STAT_RX_VL_NUMBER_4_out),
.STAT_RX_VL_NUMBER_5 (STAT_RX_VL_NUMBER_5_out),
.STAT_RX_VL_NUMBER_6 (STAT_RX_VL_NUMBER_6_out),
.STAT_RX_VL_NUMBER_7 (STAT_RX_VL_NUMBER_7_out),
.STAT_RX_VL_NUMBER_8 (STAT_RX_VL_NUMBER_8_out),
.STAT_RX_VL_NUMBER_9 (STAT_RX_VL_NUMBER_9_out),
.STAT_TX_BAD_FCS (STAT_TX_BAD_FCS_out),
.STAT_TX_BROADCAST (STAT_TX_BROADCAST_out),
.STAT_TX_FRAME_ERROR (STAT_TX_FRAME_ERROR_out),
.STAT_TX_LOCAL_FAULT (STAT_TX_LOCAL_FAULT_out),
.STAT_TX_MULTICAST (STAT_TX_MULTICAST_out),
.STAT_TX_PACKET_1024_1518_BYTES (STAT_TX_PACKET_1024_1518_BYTES_out),
.STAT_TX_PACKET_128_255_BYTES (STAT_TX_PACKET_128_255_BYTES_out),
.STAT_TX_PACKET_1519_1522_BYTES (STAT_TX_PACKET_1519_1522_BYTES_out),
.STAT_TX_PACKET_1523_1548_BYTES (STAT_TX_PACKET_1523_1548_BYTES_out),
.STAT_TX_PACKET_1549_2047_BYTES (STAT_TX_PACKET_1549_2047_BYTES_out),
.STAT_TX_PACKET_2048_4095_BYTES (STAT_TX_PACKET_2048_4095_BYTES_out),
.STAT_TX_PACKET_256_511_BYTES (STAT_TX_PACKET_256_511_BYTES_out),
.STAT_TX_PACKET_4096_8191_BYTES (STAT_TX_PACKET_4096_8191_BYTES_out),
.STAT_TX_PACKET_512_1023_BYTES (STAT_TX_PACKET_512_1023_BYTES_out),
.STAT_TX_PACKET_64_BYTES (STAT_TX_PACKET_64_BYTES_out),
.STAT_TX_PACKET_65_127_BYTES (STAT_TX_PACKET_65_127_BYTES_out),
.STAT_TX_PACKET_8192_9215_BYTES (STAT_TX_PACKET_8192_9215_BYTES_out),
.STAT_TX_PACKET_LARGE (STAT_TX_PACKET_LARGE_out),
.STAT_TX_PACKET_SMALL (STAT_TX_PACKET_SMALL_out),
.STAT_TX_PAUSE (STAT_TX_PAUSE_out),
.STAT_TX_PAUSE_VALID (STAT_TX_PAUSE_VALID_out),
.STAT_TX_PTP_FIFO_READ_ERROR (STAT_TX_PTP_FIFO_READ_ERROR_out),
.STAT_TX_PTP_FIFO_WRITE_ERROR (STAT_TX_PTP_FIFO_WRITE_ERROR_out),
.STAT_TX_TOTAL_BYTES (STAT_TX_TOTAL_BYTES_out),
.STAT_TX_TOTAL_GOOD_BYTES (STAT_TX_TOTAL_GOOD_BYTES_out),
.STAT_TX_TOTAL_GOOD_PACKETS (STAT_TX_TOTAL_GOOD_PACKETS_out),
.STAT_TX_TOTAL_PACKETS (STAT_TX_TOTAL_PACKETS_out),
.STAT_TX_UNICAST (STAT_TX_UNICAST_out),
.STAT_TX_USER_PAUSE (STAT_TX_USER_PAUSE_out),
.STAT_TX_VLAN (STAT_TX_VLAN_out),
.TX_OVFOUT (TX_OVFOUT_out),
.TX_PTP_PCSLANE_OUT (TX_PTP_PCSLANE_OUT_out),
.TX_PTP_TSTAMP_OUT (TX_PTP_TSTAMP_OUT_out),
.TX_PTP_TSTAMP_TAG_OUT (TX_PTP_TSTAMP_TAG_OUT_out),
.TX_PTP_TSTAMP_VALID_OUT (TX_PTP_TSTAMP_VALID_OUT_out),
.TX_RDYOUT (TX_RDYOUT_out),
.TX_SERDES_ALT_DATA0 (TX_SERDES_ALT_DATA0_out),
.TX_SERDES_ALT_DATA1 (TX_SERDES_ALT_DATA1_out),
.TX_SERDES_ALT_DATA2 (TX_SERDES_ALT_DATA2_out),
.TX_SERDES_ALT_DATA3 (TX_SERDES_ALT_DATA3_out),
.TX_SERDES_DATA0 (TX_SERDES_DATA0_out),
.TX_SERDES_DATA1 (TX_SERDES_DATA1_out),
.TX_SERDES_DATA2 (TX_SERDES_DATA2_out),
.TX_SERDES_DATA3 (TX_SERDES_DATA3_out),
.TX_SERDES_DATA4 (TX_SERDES_DATA4_out),
.TX_SERDES_DATA5 (TX_SERDES_DATA5_out),
.TX_SERDES_DATA6 (TX_SERDES_DATA6_out),
.TX_SERDES_DATA7 (TX_SERDES_DATA7_out),
.TX_SERDES_DATA8 (TX_SERDES_DATA8_out),
.TX_SERDES_DATA9 (TX_SERDES_DATA9_out),
.TX_UNFOUT (TX_UNFOUT_out),
.CTL_CAUI4_MODE (CTL_CAUI4_MODE_in),
.CTL_RX_CHECK_ETYPE_GCP (CTL_RX_CHECK_ETYPE_GCP_in),
.CTL_RX_CHECK_ETYPE_GPP (CTL_RX_CHECK_ETYPE_GPP_in),
.CTL_RX_CHECK_ETYPE_PCP (CTL_RX_CHECK_ETYPE_PCP_in),
.CTL_RX_CHECK_ETYPE_PPP (CTL_RX_CHECK_ETYPE_PPP_in),
.CTL_RX_CHECK_MCAST_GCP (CTL_RX_CHECK_MCAST_GCP_in),
.CTL_RX_CHECK_MCAST_GPP (CTL_RX_CHECK_MCAST_GPP_in),
.CTL_RX_CHECK_MCAST_PCP (CTL_RX_CHECK_MCAST_PCP_in),
.CTL_RX_CHECK_MCAST_PPP (CTL_RX_CHECK_MCAST_PPP_in),
.CTL_RX_CHECK_OPCODE_GCP (CTL_RX_CHECK_OPCODE_GCP_in),
.CTL_RX_CHECK_OPCODE_GPP (CTL_RX_CHECK_OPCODE_GPP_in),
.CTL_RX_CHECK_OPCODE_PCP (CTL_RX_CHECK_OPCODE_PCP_in),
.CTL_RX_CHECK_OPCODE_PPP (CTL_RX_CHECK_OPCODE_PPP_in),
.CTL_RX_CHECK_SA_GCP (CTL_RX_CHECK_SA_GCP_in),
.CTL_RX_CHECK_SA_GPP (CTL_RX_CHECK_SA_GPP_in),
.CTL_RX_CHECK_SA_PCP (CTL_RX_CHECK_SA_PCP_in),
.CTL_RX_CHECK_SA_PPP (CTL_RX_CHECK_SA_PPP_in),
.CTL_RX_CHECK_UCAST_GCP (CTL_RX_CHECK_UCAST_GCP_in),
.CTL_RX_CHECK_UCAST_GPP (CTL_RX_CHECK_UCAST_GPP_in),
.CTL_RX_CHECK_UCAST_PCP (CTL_RX_CHECK_UCAST_PCP_in),
.CTL_RX_CHECK_UCAST_PPP (CTL_RX_CHECK_UCAST_PPP_in),
.CTL_RX_ENABLE (CTL_RX_ENABLE_in),
.CTL_RX_ENABLE_GCP (CTL_RX_ENABLE_GCP_in),
.CTL_RX_ENABLE_GPP (CTL_RX_ENABLE_GPP_in),
.CTL_RX_ENABLE_PCP (CTL_RX_ENABLE_PCP_in),
.CTL_RX_ENABLE_PPP (CTL_RX_ENABLE_PPP_in),
.CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in),
.CTL_RX_PAUSE_ACK (CTL_RX_PAUSE_ACK_in),
.CTL_RX_PAUSE_ENABLE (CTL_RX_PAUSE_ENABLE_in),
.CTL_RX_SYSTEMTIMERIN (CTL_RX_SYSTEMTIMERIN_in),
.CTL_RX_TEST_PATTERN (CTL_RX_TEST_PATTERN_in),
.CTL_TX_ENABLE (CTL_TX_ENABLE_in),
.CTL_TX_LANE0_VLM_BIP7_OVERRIDE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in),
.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in),
.CTL_TX_PAUSE_ENABLE (CTL_TX_PAUSE_ENABLE_in),
.CTL_TX_PAUSE_QUANTA0 (CTL_TX_PAUSE_QUANTA0_in),
.CTL_TX_PAUSE_QUANTA1 (CTL_TX_PAUSE_QUANTA1_in),
.CTL_TX_PAUSE_QUANTA2 (CTL_TX_PAUSE_QUANTA2_in),
.CTL_TX_PAUSE_QUANTA3 (CTL_TX_PAUSE_QUANTA3_in),
.CTL_TX_PAUSE_QUANTA4 (CTL_TX_PAUSE_QUANTA4_in),
.CTL_TX_PAUSE_QUANTA5 (CTL_TX_PAUSE_QUANTA5_in),
.CTL_TX_PAUSE_QUANTA6 (CTL_TX_PAUSE_QUANTA6_in),
.CTL_TX_PAUSE_QUANTA7 (CTL_TX_PAUSE_QUANTA7_in),
.CTL_TX_PAUSE_QUANTA8 (CTL_TX_PAUSE_QUANTA8_in),
.CTL_TX_PAUSE_REFRESH_TIMER0 (CTL_TX_PAUSE_REFRESH_TIMER0_in),
.CTL_TX_PAUSE_REFRESH_TIMER1 (CTL_TX_PAUSE_REFRESH_TIMER1_in),
.CTL_TX_PAUSE_REFRESH_TIMER2 (CTL_TX_PAUSE_REFRESH_TIMER2_in),
.CTL_TX_PAUSE_REFRESH_TIMER3 (CTL_TX_PAUSE_REFRESH_TIMER3_in),
.CTL_TX_PAUSE_REFRESH_TIMER4 (CTL_TX_PAUSE_REFRESH_TIMER4_in),
.CTL_TX_PAUSE_REFRESH_TIMER5 (CTL_TX_PAUSE_REFRESH_TIMER5_in),
.CTL_TX_PAUSE_REFRESH_TIMER6 (CTL_TX_PAUSE_REFRESH_TIMER6_in),
.CTL_TX_PAUSE_REFRESH_TIMER7 (CTL_TX_PAUSE_REFRESH_TIMER7_in),
.CTL_TX_PAUSE_REFRESH_TIMER8 (CTL_TX_PAUSE_REFRESH_TIMER8_in),
.CTL_TX_PAUSE_REQ (CTL_TX_PAUSE_REQ_in),
.CTL_TX_PTP_VLANE_ADJUST_MODE (CTL_TX_PTP_VLANE_ADJUST_MODE_in),
.CTL_TX_RESEND_PAUSE (CTL_TX_RESEND_PAUSE_in),
.CTL_TX_SEND_IDLE (CTL_TX_SEND_IDLE_in),
.CTL_TX_SEND_RFI (CTL_TX_SEND_RFI_in),
.CTL_TX_SYSTEMTIMERIN (CTL_TX_SYSTEMTIMERIN_in),
.CTL_TX_TEST_PATTERN (CTL_TX_TEST_PATTERN_in),
.DRP_ADDR (DRP_ADDR_in),
.DRP_CLK (DRP_CLK_in),
.DRP_DI (DRP_DI_in),
.DRP_EN (DRP_EN_in),
.DRP_WE (DRP_WE_in),
.RX_CLK (RX_CLK_in),
.RX_RESET (RX_RESET_in),
.RX_SERDES_ALT_DATA0 (RX_SERDES_ALT_DATA0_in),
.RX_SERDES_ALT_DATA1 (RX_SERDES_ALT_DATA1_in),
.RX_SERDES_ALT_DATA2 (RX_SERDES_ALT_DATA2_in),
.RX_SERDES_ALT_DATA3 (RX_SERDES_ALT_DATA3_in),
.RX_SERDES_CLK (RX_SERDES_CLK_in),
.RX_SERDES_DATA0 (RX_SERDES_DATA0_in),
.RX_SERDES_DATA1 (RX_SERDES_DATA1_in),
.RX_SERDES_DATA2 (RX_SERDES_DATA2_in),
.RX_SERDES_DATA3 (RX_SERDES_DATA3_in),
.RX_SERDES_DATA4 (RX_SERDES_DATA4_in),
.RX_SERDES_DATA5 (RX_SERDES_DATA5_in),
.RX_SERDES_DATA6 (RX_SERDES_DATA6_in),
.RX_SERDES_DATA7 (RX_SERDES_DATA7_in),
.RX_SERDES_DATA8 (RX_SERDES_DATA8_in),
.RX_SERDES_DATA9 (RX_SERDES_DATA9_in),
.RX_SERDES_RESET (RX_SERDES_RESET_in),
.SCAN_EN_N (SCAN_EN_N_in),
.SCAN_IN (SCAN_IN_in),
.TEST_MODE_N (TEST_MODE_N_in),
.TEST_RESET (TEST_RESET_in),
.TX_CLK (TX_CLK_in),
.TX_DATAIN0 (TX_DATAIN0_in),
.TX_DATAIN1 (TX_DATAIN1_in),
.TX_DATAIN2 (TX_DATAIN2_in),
.TX_DATAIN3 (TX_DATAIN3_in),
.TX_ENAIN0 (TX_ENAIN0_in),
.TX_ENAIN1 (TX_ENAIN1_in),
.TX_ENAIN2 (TX_ENAIN2_in),
.TX_ENAIN3 (TX_ENAIN3_in),
.TX_EOPIN0 (TX_EOPIN0_in),
.TX_EOPIN1 (TX_EOPIN1_in),
.TX_EOPIN2 (TX_EOPIN2_in),
.TX_EOPIN3 (TX_EOPIN3_in),
.TX_ERRIN0 (TX_ERRIN0_in),
.TX_ERRIN1 (TX_ERRIN1_in),
.TX_ERRIN2 (TX_ERRIN2_in),
.TX_ERRIN3 (TX_ERRIN3_in),
.TX_MTYIN0 (TX_MTYIN0_in),
.TX_MTYIN1 (TX_MTYIN1_in),
.TX_MTYIN2 (TX_MTYIN2_in),
.TX_MTYIN3 (TX_MTYIN3_in),
.TX_PTP_1588OP_IN (TX_PTP_1588OP_IN_in),
.TX_PTP_CHKSUM_OFFSET_IN (TX_PTP_CHKSUM_OFFSET_IN_in),
.TX_PTP_RXTSTAMP_IN (TX_PTP_RXTSTAMP_IN_in),
.TX_PTP_TAG_FIELD_IN (TX_PTP_TAG_FIELD_IN_in),
.TX_PTP_TSTAMP_OFFSET_IN (TX_PTP_TSTAMP_OFFSET_IN_in),
.TX_PTP_UPD_CHKSUM_IN (TX_PTP_UPD_CHKSUM_IN_in),
.TX_RESET (TX_RESET_in),
.TX_SOPIN0 (TX_SOPIN0_in),
.TX_SOPIN1 (TX_SOPIN1_in),
.TX_SOPIN2 (TX_SOPIN2_in),
.TX_SOPIN3 (TX_SOPIN3_in),
.GSR (glblGSR)
);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DCIRESET.v 0000664 0000000 0000000 00000003346 12327044266 0022632 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Reset for DCI State Machine
// /___/ /\ Filename : DCIRESET.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DCIRESET (LOCKED, RST);
output LOCKED;
input RST;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
time sample_rising, sample_falling;
always @(RST)
begin
if (RST)
sample_rising = $time;
else if (!RST)
sample_falling = $time;
if (sample_falling - sample_rising < 100000)
$display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
if (sample_rising - sample_falling < 100000)
$display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
end // always @ (RST)
assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1;
`ifdef XIL_TIMING
specify
(RST => LOCKED) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DCM_ADV.v 0000664 0000000 0000000 00000161173 12327044266 0022530 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DCM_ADV.v,v 1.4 2004/03/31 22:39:41 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.50)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Digital Clock Manager with Advanced Features
// /___/ /\ Filename : DCM_ADV.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/11/05 - Remove GSR pin; Add LOC parameter.
// 03/23/04 - Initial version.
// 04/11/05 - Add parameter DFS_OSCILLATOR_MODE to support R.
// 04/22/05 - Change DRP set clkfx M/D value effected on RST=1, not rising
// edge. (CR 206731)
// 05/11/05 - Add parameter DCM_AUTOCALIBRATION (CR 208095).
// - Add clkin alignment check control to remove the glitch when
// clkin stopped. (CR207409).
// 05/19/05 - Add initial to all clock outputs. (CR 208380).
// 05/25/05 - Seperate clock_second_pos and neg to another process due to
// wait caused unreset. Set fb_delay_found after fb_delay computed.
// (CR 208771)
// 07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465).
// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190).
// 12/02/05 - Add warning for un-used DRP address use. (CR 221885)
// 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795)
// 01/06/06 - Remove GSR from 3 cycle check. (223099).
// 01/12/06 - Remove GSR from reset logic. (223099).
// 01/12/06 - Add rst_in to period_div and period_ps block to handle clkin frequency
// change case. (CR 221989).
// 01/26/06 - Remove $finish from DRP Warning and change invalid to unsupported
// address. (CR 224743)
// Add reset to maximum period check module (CR224287).
// 02/28/06 - Add SIM_DEVICE generic to support V5 and V4 M and D for CLKFX (BT#1003).
// Add integer and real to parameter declaration.
// 03/10/06 - Add wire declaration for lock_period_dly signal (CR 227126)
// 08/10/06 - Set PSDONE to 0 when CLKOUT_PHASE_SHIFT=FIXED (CR 227018).
// 03/07/07 - Change DRP CLKFX Multiplier to bit 15 to 8 and Divider to bit 7 to 0.
// (CR 435600).
// 04/06/07 - Enable the clock out in clock low time after reset in model
// clock_divide_by_2 (CR 437471).
// 06/04/07 - Add wire declaration for internal signals, Remove buf from unisim.
// 09/20/07 - Use 1.5 factor for clock stopped check when CLKIN divide by 2 set(CR446707).
// 11/01/07 - Add DRP DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE read/write support (CR435651)
// 12/20/07 - Add DRP CLKIN_DIVIDE_BY_2 read/write support (CR457282)
// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858).
// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893).
// 03/11/08 - Not check clock lost when negative edge period smaller than positive edge
// period in dcm_adv_clock_lost module (CR469499).
// 03/12/08 - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858).
// 07/08/08 - Use clkin_div instead of period to generate lock_period_dly (CR476425)
// 10/02/08 - Reset ps_kick_off_cmd after phase shifting (CR490447)
// 03/09/11 - set period and period_fx to 0 when rst (CR595385)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
`define CLKFX_MULTIPLY_ADDR 80
`define CLKFX_DIVIDE_ADDR 82
`define PHASE_SHIFT_ADDR 85
`define PHASE_SHIFT_KICK_OFF_ADDR 17
`define DCM_DEFAULT_STATUS_ADDR 0
`define DFS_FREQ_MODE_ADDR 65
`define DLL_FREQ_MODE_ADDR 81
`define CLKIN_DIV_BY2_ADDR 68
module DCM_ADV (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
DO,
DRDY,
LOCKED,
PSDONE,
CLKFB,
CLKIN,
DADDR,
DCLK,
DEN,
DI,
DWE,
PSCLK,
PSEN,
PSINCDEC,
RST
);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0; // non-simulatable
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DCM_AUTOCALIBRATION = "TRUE";
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; // non-simulatable
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hF0F0; // non-simulatable
parameter integer MAXPERCLKIN = 1000000; // non-modifiable simulation parameter
parameter integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter
parameter integer PHASE_SHIFT = 0;
parameter integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter
parameter integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter
parameter SIM_DEVICE ="VIRTEX4";
parameter LOC = "UNPLACED";
parameter STARTUP_WAIT = "FALSE"; // non-simulatable
localparam DFS_OSCILLATOR_MODE = "PHASE_FREQ_LOCK";
output CLK0;
output CLK180;
output CLK270;
output CLK2X180;
output CLK2X;
output CLK90;
output CLKDV;
output CLKFX180;
output CLKFX;
output DRDY;
output LOCKED;
output PSDONE;
output [15:0] DO;
input CLKFB;
input CLKIN;
input DCLK;
input DEN;
input DWE;
input PSCLK;
input PSEN;
input PSINCDEC;
tri0 GSR = glbl.GSR;
input RST;
input [15:0] DI;
input [6:0] DADDR;
reg CLK0;
reg CLK180;
reg CLK270;
reg CLK2X180;
reg CLK2X;
reg CLK90;
reg CLKDV;
reg CLKFX180;
reg CLKFX;
wire [15:0] di_in;
wire [6:0] daddr_in;
wire clkfb_in, clkin_in, dssen_in;
wire psclk_in, psen_in, psincdec_in, rst_in, gsr_in, rst_input ;
wire locked_out_out;
wire dwe_in, den_in, dclk_in, clkin_lost_out, clkfx_lost_out, clkfb_lost_out;
reg rst_flag;
reg clk0_out;
reg clk2x_out, clkdv_out;
reg clkfx_out, locked_out, psdone_out, ps_overflow_out;
reg clkfx_out_avg, clkfx_out_ph;
reg ps_lock;
reg drdy_out;
wire [15:0] do_out;
reg [15:0] do_out_s, do_out_drp, do_out_drp1;
reg do_stat_en;
reg [6:0] daddr_in_lat;
reg valid_daddr;
reg [1:0] clkfb_type;
reg [8:0] divide_type;
reg clkin_type_i;
wire clkin_type;
reg [2:0] ps_type;
reg [3:0] deskew_adjust_mode;
wire dfs_mode_type;
reg dfs_mode_type_i;
wire [1:0] dll_mode_type;
reg [1:0] dll_mode_type_i;
reg sim_device_type;
reg clk1x_type;
integer ps_in, ps_min, ps_max;
integer ps_in_ps, ps_in_psdrp, ps_in_curr;
integer ps_delay_ps, ps_delay_drp;
integer clkdv_cnt;
reg lock_period, lock_delay, lock_clkin, lock_clkfb;
reg [1:0] lock_out;
reg lock_out1_neg;
reg lock_fb, lock_ps, lock_ps_dly;
reg fb_delay_found;
reg clock_stopped;
reg clkin_chkin, clkfb_chkin;
wire chk_enable, chk_rst;
wire clkin_div;
wire locked_out_tmp;
wire lock_period_pulse;
reg lock_period_dly;
reg clkin_ps;
reg clkin_fb;
time FINE_SHIFT_RANGE;
time ps_delay;
time delay_edge;
time clkin_period [2:0];
time period, period_50, period_25, period_25_rm;
time period_div;
time period_orig;
time period_stop_ck;
time period_ps;
time clkout_delay;
time fb_delay;
time period_fx, remain_fx;
time period_fxtmp, period_fxavg;
time period_dv_high, period_dv_low;
time cycle_jitter, period_jitter;
time clkin_div_edge, clkin_ps_edge, clkin_edge;
time tap_delay_step;
reg clkin_window, clkfb_window;
reg [2:0] rst_reg;
reg [12:0] numerator, denominator, gcd;
reg [23:0] i, n, d, p;
reg first_time_locked;
reg en_status;
reg [1521:0] mem_drp;
reg drp_lock;
reg drp_lock1;
reg ps_drp_lock, ps_drp_lock_tmp, ps_drp_lock_tmp1;
integer ps_drp, ps_in_drp;
reg ps_kick_off_cmd;
reg single_step_lock, single_step_lock_tmp, single_step_done;
integer clkfx_multiply_drp, clkfx_divide_drp;
reg [7:0] clkfx_m_reg, clkfx_d_reg;
reg [15:0] clkfx_md_reg, dfs_mode_reg, dll_mode_reg, clkin_div2_reg;
reg inc_dec;
real clock_stopped_factor;
reg notifier;
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the DCM_ADV, the simulator resolution must be set to 1ps or smaller.");
$finish;
end
end
initial begin
case (CLKDV_DIVIDE)
1.5 : divide_type = 'd3;
2.0 : divide_type = 'd4;
2.5 : divide_type = 'd5;
3.0 : divide_type = 'd6;
3.5 : divide_type = 'd7;
4.0 : divide_type = 'd8;
4.5 : divide_type = 'd9;
5.0 : divide_type = 'd10;
5.5 : divide_type = 'd11;
6.0 : divide_type = 'd12;
6.5 : divide_type = 'd13;
7.0 : divide_type = 'd14;
7.5 : divide_type = 'd15;
8.0 : divide_type = 'd16;
9.0 : divide_type = 'd18;
10.0 : divide_type = 'd20;
11.0 : divide_type = 'd22;
12.0 : divide_type = 'd24;
13.0 : divide_type = 'd26;
14.0 : divide_type = 'd28;
15.0 : divide_type = 'd30;
16.0 : divide_type = 'd32;
default : begin
$display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_ADV instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE);
$finish;
end
endcase
// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
// if ((CLKFX_DIVIDE <= 0) || (4096 < CLKFX_DIVIDE)) begin
// $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 4096.", CLKFX_DIVIDE);
// $finish;
// end
// else
if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin
$display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE);
$finish;
end
// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
// if ((CLKFX_MULTIPLY <= 1) || (4096 < CLKFX_MULTIPLY)) begin
// $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 4096.", CLKFX_MULTIPLY);
// $finish;
// end
// else
if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin
$display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY);
$finish;
end
case (CLKIN_DIVIDE_BY_2)
"FALSE" : begin
clkin_type_i = 0;
clock_stopped_factor = 2.0;
end
"TRUE" : begin
clkin_type_i = 1;
clock_stopped_factor = 1.5;
end
default : begin
$display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2);
$finish;
end
endcase
case (CLKOUT_PHASE_SHIFT)
"NONE" : begin
ps_in = 0 + 256;
ps_type = 3'b000;
end
"FIXED" : begin
ps_in = PHASE_SHIFT + 256;
ps_max = 255 + 256;
ps_min = -255 + 256;
ps_type = 3'b001;
if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" )
FINE_SHIFT_RANGE = 10000;
else
FINE_SHIFT_RANGE = 7000;
if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin
$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT);
$display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT);
$finish;
end
end
"VARIABLE_POSITIVE" : begin
ps_in = PHASE_SHIFT + 256;
ps_max = 255 + 256;
ps_min = 0 + 256;
ps_type = 3'b011;
if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" )
FINE_SHIFT_RANGE = 10000;
else
FINE_SHIFT_RANGE = 7000;
if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 255)) begin
$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are 0 ... 255.", PHASE_SHIFT);
$display("Error : PHASE_SHIFT = %d is not 0 ... 255.", PHASE_SHIFT);
$finish;
end
end
"VARIABLE_CENTER" : begin
ps_in = PHASE_SHIFT + 256;
ps_max = 255 + 256;
ps_min = -255 + 256;
ps_type = 3'b100;
if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" )
FINE_SHIFT_RANGE = 5000;
else
FINE_SHIFT_RANGE = 3500;
if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin
$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT);
$display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT);
$finish;
end
end
"DIRECT" : begin
ps_in = PHASE_SHIFT;
ps_max = 1023;
ps_min = 0;
ps_type = 3'b101;
if (DCM_PERFORMANCE_MODE == "MAX_RANGE")
begin
tap_delay_step = 18;
FINE_SHIFT_RANGE = 10000;
end
else
begin
tap_delay_step = 11;
FINE_SHIFT_RANGE = 7000;
end
if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 1023)) begin
$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute is 0 to 1023.", PHASE_SHIFT);
$display("Error : PHASE_SHIFT = %d is not 0 to 1023.", PHASE_SHIFT);
$finish;
end
end
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_PHASE_SHIFT on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT.", CLKOUT_PHASE_SHIFT);
$finish;
end
endcase
ps_in_curr = ps_in;
ps_in_ps = ps_in;
ps_in_psdrp = ps_in;
case (CLK_FEEDBACK)
"NONE" : begin
clkfb_type = 0;
$display("Attribute CLK_FEEDBACK is set to value NONE.");
$display("In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN");
end
"1X" : clkfb_type = 1;
default : begin
$display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK);
$finish;
end
endcase
case (DCM_PERFORMANCE_MODE)
"MAX_SPEED" : ;
"MAX_RANGE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute DCM_PERFORMANCE_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are MAX_SPEED or MAX_RANGE.", DCM_PERFORMANCE_MODE);
$finish;
end
endcase
case (DESKEW_ADJUST)
"SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 0;
"SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11;
"0" : deskew_adjust_mode = 0;
"1" : deskew_adjust_mode = 1;
"2" : deskew_adjust_mode = 2;
"3" : deskew_adjust_mode = 3;
"4" : deskew_adjust_mode = 4;
"5" : deskew_adjust_mode = 5;
"6" : deskew_adjust_mode = 6;
"7" : deskew_adjust_mode = 7;
"8" : deskew_adjust_mode = 8;
"9" : deskew_adjust_mode = 9;
"10" : deskew_adjust_mode = 10;
"11" : deskew_adjust_mode = 11;
"12" : deskew_adjust_mode = 12;
"13" : deskew_adjust_mode = 13;
"14" : deskew_adjust_mode = 14;
"15" : deskew_adjust_mode = 15;
"16" : deskew_adjust_mode = 16;
"17" : deskew_adjust_mode = 17;
"18" : deskew_adjust_mode = 18;
"19" : deskew_adjust_mode = 19;
"20" : deskew_adjust_mode = 20;
"21" : deskew_adjust_mode = 21;
"22" : deskew_adjust_mode = 22;
"23" : deskew_adjust_mode = 23;
"24" : deskew_adjust_mode = 24;
"25" : deskew_adjust_mode = 25;
"26" : deskew_adjust_mode = 26;
"27" : deskew_adjust_mode = 27;
"28" : deskew_adjust_mode = 28;
"29" : deskew_adjust_mode = 29;
"30" : deskew_adjust_mode = 30;
"31" : deskew_adjust_mode = 31;
default : begin
$display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_ADV instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST);
$finish;
end
endcase
case (DFS_FREQUENCY_MODE)
"HIGH" : dfs_mode_type_i = 1;
"LOW" : dfs_mode_type_i = 0;
default : begin
$display(" Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE);
$finish;
end
endcase
period_jitter = SIM_CLKIN_PERIOD_JITTER;
cycle_jitter = SIM_CLKIN_CYCLE_JITTER;
case (DLL_FREQUENCY_MODE)
"HIGH" : dll_mode_type_i = 2'b11;
"LOW" : dll_mode_type_i = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE);
$finish;
end
endcase
case (FACTORY_JF)
16'hF0F0 : ;
default :
$display("Attribute Syntax Warning : The attribute FACTORY_JF on DCM_ADV instance %m is set to %h. Legal value is F0F0.", FACTORY_JF);
endcase
case (DUTY_CYCLE_CORRECTION)
"FALSE" : if (SIM_DEVICE=="VIRTEX4") clk1x_type = 0; else clk1x_type = 1;
"TRUE" : clk1x_type = 1;
default : begin
$display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
$finish;
end
endcase
case (STARTUP_WAIT)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
$finish;
end
endcase
case (DCM_AUTOCALIBRATION)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DCM_AUTOCALIBRATION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DCM_AUTOCALIBRATION);
$finish;
end
endcase
case (SIM_DEVICE)
"VIRTEX5" : sim_device_type = 1;
"VIRTEX4" : sim_device_type = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV instance %m is set to %s. Legal values for this attribute are VIRTEX5 or VIRTEX4.", SIM_DEVICE);
$finish;
end
endcase
end
//
// input wire delays
//
buf b_LOCKED (LOCKED, locked_out_out);
buf b_PSDONE (PSDONE, psdone_out);
buf b_DO0 (DO[0], do_out[0]);
buf b_DO1 (DO[1], do_out[1]);
buf b_DO2 (DO[2], do_out[2]);
buf b_DO3 (DO[3], do_out[3]);
buf b_DO4 (DO[4], do_out[4]);
buf b_DO5 (DO[5], do_out[5]);
buf b_DO6 (DO[6], do_out[6]);
buf b_DO7 (DO[7], do_out[7]);
buf b_DO8 (DO[8], do_out[8]);
buf b_DO9 (DO[9], do_out[9]);
buf b_DO10 (DO[10], do_out[10]);
buf b_DO11 (DO[11], do_out[11]);
buf b_DO12 (DO[12], do_out[12]);
buf b_DO13 (DO[13], do_out[13]);
buf b_DO14 (DO[14], do_out[14]);
buf b_DO15 (DO[15], do_out[15]);
buf b_DRDY (DRDY, drdy_out);
buf b_CLKIN (clkin_in, CLKIN);
buf b_CLKFB (clkfb_in, CLKFB);
buf b_PSCLK (psclk_in, PSCLK);
buf b_PSEN (psen_in, PSEN);
buf b_PSINCDEC (psincdec_in, PSINCDEC);
buf b_GSR (gsr_in, GSR);
buf b_RST (rst_input, RST);
buf b_DADDR0 (daddr_in[0], DADDR[0]);
buf b_DADDR1 (daddr_in[1], DADDR[1]);
buf b_DADDR2 (daddr_in[2], DADDR[2]);
buf b_DADDR3 (daddr_in[3], DADDR[3]);
buf b_DADDR4 (daddr_in[4], DADDR[4]);
buf b_DADDR5 (daddr_in[5], DADDR[5]);
buf b_DADDR6 (daddr_in[6], DADDR[6]);
buf b_DI0 (di_in[0], DI[0]);
buf b_DI1 (di_in[1], DI[1]);
buf b_DI2 (di_in[2], DI[2]);
buf b_DI3 (di_in[3], DI[3]);
buf b_DI4 (di_in[4], DI[4]);
buf b_DI5 (di_in[5], DI[5]);
buf b_DI6 (di_in[6], DI[6]);
buf b_DI7 (di_in[7], DI[7]);
buf b_DI8 (di_in[8], DI[8]);
buf b_DI9 (di_in[9], DI[9]);
buf b_DI10 (di_in[10], DI[10]);
buf b_DI11 (di_in[11], DI[11]);
buf b_DI12 (di_in[12], DI[12]);
buf b_DI13 (di_in[13], DI[13]);
buf b_DI14 (di_in[14], DI[14]);
buf b_DI15 (di_in[15], DI[15]);
buf b_DWE (dwe_in, DWE);
buf b_DEN (den_in, DEN);
buf b_DCLK (dclk_in, DCLK);
assign rst_in = rst_input;
dcm_adv_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in);
dcm_adv_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
dcm_adv_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in);
dcm_adv_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in);
dcm_adv_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in);
dcm_adv_clock_lost i_clkfb_lost (CLKFB, first_time_locked, clkfb_lost_out, rst_in);
always @(clkin_div)
clkin_ps <= #(ps_delay) clkin_div;
always @(clkin_ps or lock_fb)
clkin_fb = clkin_ps & lock_fb;
always @(posedge clkin_fb or posedge chk_rst)
if (chk_rst)
clkin_chkin <= 0;
else
clkin_chkin <= 1;
always @(posedge clkfb_in or posedge chk_rst)
if (chk_rst)
clkfb_chkin <= 0;
else
clkfb_chkin <= 1;
assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0;
assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 &&
lock_ps ==1 && lock_fb ==1 ) ? 1 : 0;
always @(posedge clkin_div or posedge rst_in)
if (rst_in) begin
period_div <= 0;
clkin_div_edge <= 0;
end
else
if ( clkin_div == 1) begin
clkin_div_edge <= $time;
if (($time - clkin_div_edge) <= (1.5 * period_div))
period_div <= $time - clkin_div_edge;
else if ((period_div == 0) && (clkin_div_edge != 0))
period_div <= $time - clkin_div_edge;
end
always @(posedge clkin_ps or posedge rst_in)
if (rst_in) begin
period_ps <= 0;
clkin_ps_edge <= 0;
end
else
if (clkin_ps==1) begin
clkin_ps_edge <= $time;
if (($time - clkin_ps_edge) <= (1.5 * period_ps))
period_ps <= $time - clkin_ps_edge;
else if ((period_ps == 0) && (clkin_ps_edge != 0))
period_ps <= $time - clkin_ps_edge;
end
always @(posedge clkin_ps) begin
lock_ps <= lock_period;
lock_ps_dly <= lock_ps;
lock_fb <= lock_ps_dly;
end
always @(period or fb_delay)
if (fb_delay ==0)
clkout_delay = 0;
else
clkout_delay = period - fb_delay;
//
// generate master reset signal
//
always @(posedge clkin_in) begin
rst_reg[0] <= rst_input;
rst_reg[1] <= rst_reg[0] & rst_input;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_input;
end
reg rst_tmp1, rst_tmp2;
initial
begin
rst_tmp1 = 0;
rst_tmp2 = 0;
rst_flag = 0;
end
always @(rst_input)
begin
if (rst_input)
rst_flag = 0;
rst_tmp1 = rst_input;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin
rst_flag = 1;
$display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles.");
end
end
rst_tmp2 = rst_tmp1;
end
initial begin
CLK0 = 0;
CLK2X =0;
CLK2X180 = 0;
CLK90 = 0;
CLK180 =0;
CLK270 = 0;
CLKDV = 0;
CLKFX = 0;
CLKFX180 =0;
clk0_out = 0;
clk2x_out = 0;
clkdv_cnt = 0;
clkdv_out = 0;
clkfb_window = 0;
clkfx_out = 0;
clkfx_out_avg = 0;
clkfx_out_ph = 0;
clkin_div_edge = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
period = 0;
clkin_ps_edge = 0;
clkin_window = 0;
clkout_delay = 0;
clock_stopped = 1;
fb_delay = 0;
fb_delay_found = 0;
lock_clkfb = 0;
lock_clkin = 0;
lock_delay = 0;
lock_fb = 0;
lock_out = 2'b00;
lock_out1_neg = 0;
lock_period = 0;
lock_period_dly = 0;
lock_ps = 0;
lock_ps_dly = 0;
locked_out = 0;
period = 0;
period_div = 0;
period_fx = 0;
period_fxavg = 0;
period_orig = 0;
period_stop_ck = 0;
period_ps = 0;
delay_edge = 0;
psdone_out = 0;
ps_delay = 0;
ps_lock = 0;
inc_dec = 0;
ps_overflow_out = 0;
ps_delay_ps = 0;
ps_delay_drp = 0;
rst_reg = 3'b000;
numerator = CLKFX_MULTIPLY;
denominator = CLKFX_DIVIDE;
clkfx_multiply_drp = CLKFX_MULTIPLY;
clkfx_divide_drp = CLKFX_DIVIDE;
clkfx_m_reg = CLKFX_MULTIPLY;
clkfx_d_reg = CLKFX_DIVIDE;
clkfx_md_reg = {clkfx_m_reg, clkfx_d_reg};
gcd = 1;
drdy_out = 0;
do_out_drp = 16'h0000;
do_out_drp1 = 16'h0000;
do_out_s = 16'h0000;
valid_daddr = 0;
first_time_locked = 0;
en_status = 0;
drp_lock = 0;
ps_drp = 0;
ps_kick_off_cmd = 0;
single_step_lock = 0;
single_step_lock_tmp = 0;
single_step_done = 0;
ps_drp_lock = 0;
ps_drp_lock_tmp = 0;
clkin_chkin = 0;
clkfb_chkin = 0;
dfs_mode_reg = {13'bxxxxxxxxxxxxx, dfs_mode_type_i, 2'bxx};
dll_mode_reg = {12'bxxxxxxxxxxxx, dll_mode_type_i, 2'bxx};
clkin_div2_reg = {5'bxxxxx, clkin_type_i, 10'bxxxxxxxxxx};
do_stat_en = 1;
end
assign dfs_mode_type = dfs_mode_reg[2];
assign dll_mode_type = dll_mode_reg[3:2];
assign clkin_type = clkin_div2_reg[10];
//
// phase shift parameters
//
always @(posedge lock_period) begin
if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100)) begin
if (PHASE_SHIFT > 0) begin
if ((ps_in * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) begin
$display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, PHASE_SHIFT * period_orig/ 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0);
$finish;
end
end
else if (PHASE_SHIFT < 0) begin
if ((period_orig > FINE_SHIFT_RANGE) &&
((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) begin
$display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, -(PHASE_SHIFT) * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0);
$finish;
end
end
end
else if (ps_type == 3'b101) begin
if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) begin
$display(" Phase shift Error : Allowed phase shift range on instance %m is between 0 to %d. ", FINE_SHIFT_RANGE / tap_delay_step);
$finish;
end
end
end
always @(posedge lock_period_pulse or posedge rst_in or ps_delay_ps or ps_delay_drp or ps_in_ps
or ps_in_psdrp)
if (rst_in) begin
ps_delay <= 0;
ps_in_curr <= ps_in;
end
else if (lock_period_pulse) begin
if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100))
ps_delay <= (ps_in * period_div / 256);
else if (ps_type == 3'b101)
ps_delay <= ps_in * tap_delay_step;
end
else begin
if (((ps_type == 3'b011) || (ps_type == 3'b100) ) )
begin
ps_in_curr = ps_in_ps;
ps_delay = (ps_in_ps * period_div / 256);
end
else if ((ps_type == 3'b101) && (ps_lock==1))
begin
ps_in_curr = ps_in_ps;
ps_delay = ps_in_ps * tap_delay_step;
end
else if ((ps_type == 3'b101) && (ps_drp_lock==1))
begin
ps_in_curr = ps_in_psdrp;
ps_delay = ps_delay_drp;
end
end
always @(posedge psclk_in or posedge rst_in)
if (rst_in) begin
ps_in_ps <= ps_in;
ps_overflow_out <= 0;
// ps_delay_ps <= 0;
end
else begin
if ((ps_type == 3'b011) || (ps_type == 3'b100) ) begin
if (psen_in)
if (ps_lock == 1)
$display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift.");
else
if (psincdec_in == 1) begin
if (ps_in_ps == ps_max)
ps_overflow_out <= 1;
else if (((ps_in_ps + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE)
ps_overflow_out <= 1;
else begin
ps_in_ps <= ps_in_ps + 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
else if (psincdec_in == 0) begin
if (ps_in_ps == ps_min)
ps_overflow_out <= 1;
else if ((period_orig > FINE_SHIFT_RANGE) &&
(((ps_in_ps - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE))
ps_overflow_out <= 1;
else begin
ps_in_ps <= ps_in_ps - 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
end
if (ps_type == 3'b101) begin
if (psen_in == 1) begin
if (ps_lock == 1) begin
$display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ");
end
else
begin
if (psincdec_in == 1) begin
if (ps_in_curr == ps_max)
ps_overflow_out <= 1;
else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE)
ps_overflow_out <= 1;
else
begin
ps_in_ps <= ps_in_curr + 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
else if (psincdec_in == 0) begin
if (ps_in_curr == ps_min)
ps_overflow_out <= 1;
else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE)
ps_overflow_out <= 1;
else
begin
ps_in_ps <= ps_in_curr - 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
end
end
end
if ( psdone_out == 1)
ps_lock <= 0;
end
always @(posedge clkin_ps or posedge rst_in)
if (rst_in) begin
single_step_lock <= 0;
ps_in_psdrp <= ps_in;
ps_delay_drp <= 0;
end
else begin
if (ps_type == 3'b101) begin
if (ps_drp_lock == 1) begin
if (inc_dec == 1) begin
if (ps_in_curr < ps_in_drp) begin
if (single_step_lock == 0)
begin
single_step_lock <= 1;
ps_in_psdrp <= ps_in_curr + 1;
ps_delay_drp <= ps_delay + tap_delay_step;
end
end
else if (ps_in_curr == ps_in_drp)
ps_drp_lock <= 0;
end
else if (inc_dec == 0) begin
if (ps_in_curr > ps_in_drp) begin
if (single_step_lock == 0)
begin
single_step_lock <= 1;
ps_in_psdrp <= ps_in_curr - 1;
ps_delay_drp <= ps_delay - tap_delay_step;
end
end
else if (ps_in_psdrp == ps_in_drp)
ps_drp_lock <= 0;
end
end
if ( single_step_lock_tmp == 1)
single_step_lock <= 0;
if (ps_drp_lock_tmp == 1)
ps_drp_lock <= 1;
end
end
always @( single_step_lock or clkin_ps)
begin
@( posedge single_step_lock)
@( posedge clkin_ps)
@( posedge clkin_ps)
@( posedge clkin_ps)
single_step_lock_tmp <= 1;
@( posedge clkin_ps)
single_step_lock_tmp <= 0;
end
always @( ps_kick_off_cmd or dclk_in or clkin_in or ps_drp_lock )
begin
@(posedge ps_kick_off_cmd)
@( posedge dclk_in)
@( posedge dclk_in)
@( posedge clkin_in)
@( posedge clkin_in)
@( posedge clkin_in)
@( posedge clkin_in)
@( posedge clkin_in)
ps_drp_lock_tmp <= 1;
@( posedge ps_drp_lock)
ps_drp_lock_tmp <= 0;
end
always @(posedge ps_lock or negedge ps_drp_lock )
if (ps_type != 3'b000 || ps_type != 3'b001) begin
@(posedge clkin_ps)
@(posedge clkin_ps)
@(posedge clkin_ps)
@(posedge clkin_ps)
@(posedge psclk_in)
@(posedge psclk_in)
begin
psdone_out = 1;
@(posedge psclk_in);
psdone_out = 0;
end
end
//
// determine clock period
//
always @(period_orig)
period_stop_ck = period_orig * clock_stopped_factor;
always @(posedge clkin_div or negedge clkin_div or posedge rst_in)
if ( rst_in == 1)
begin
clkin_period[0] <= 0;
clkin_period[1] <= 0;
clkin_period[2] <= 0;
clkin_edge <= 0;
end
else
if (clkin_div == 1) begin
clkin_edge <= $time;
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
if (clkin_edge != 0)
clkin_period[0] <= $time - clkin_edge;
end
else if (clkin_div == 0)
if (lock_period == 1) begin
if (100000000 < clkin_period[0]/1000)
begin
end
// else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin
else if ((period_stop_ck <= clkin_period[0]) && (clock_stopped == 0)) begin
clkin_period[0] <= clkin_period[1];
end
end
//
// evaluate_clock_period process
//
always @(negedge clkin_div or posedge rst_in)
if (rst_in == 1) begin
lock_period <= 0;
clock_stopped <= 1;
period_fxtmp <= 0;
period <= 0;
period_orig <= 0;
end
else begin
if (lock_period == 1'b0) begin
if ((clkin_period[0] != 0) &&
(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
lock_period <= 1;
period_orig <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
period_fxtmp <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
period <= clkin_period[0];
end
end
else if (lock_period == 1'b1) begin
if (100000000 < (clkin_period[0] / 1000)) begin
$display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 10000, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
// else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
else if ((period_stop_ck <= clkin_period[0]) && clock_stopped == 1'b0) begin
// clkin_period[0] = clkin_period[1];
clock_stopped <= 1'b1;
end
else if ((clkin_period[0] < period_orig - period_jitter) ||
(period_orig + period_jitter < clkin_period[0])) begin
$display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
$display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else begin
period <= clkin_period[0];
clock_stopped <= 1'b0;
period_fxtmp <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
end
end
end
always @(posedge clkin_div or posedge rst_in)
if (rst_in)
lock_period_dly <= 0;
else
lock_period_dly <= lock_period;
// assign #(period_50) lock_period_dly = lock_period;
assign lock_period_pulse = (lock_period==1 && lock_period_dly==0) ? 1 : 0;
//
// determine clock delay
//
//always @(posedge lock_period or posedge rst_in) begin
always @(posedge lock_ps_dly or posedge rst_in)
if (rst_in) begin
fb_delay <= 0;
fb_delay_found <= 0;
end
else begin
if (lock_period && clkfb_type != 0) begin
if (clkfb_type == 1) begin
@(posedge CLK0 or rst_in)
delay_edge = $time;
end
else if (clkfb_type == 2) begin
@(posedge CLK2X or rst_in)
delay_edge = $time;
end
@(posedge clkfb_in or rst_in) begin
fb_delay <= ($time - delay_edge) % period_orig;
fb_delay_found <= 1;
end
end
end
//
// determine feedback lock
//
always @(posedge clkfb_in or posedge rst_in) begin
if (rst_in)
clkfb_window <= 0;
else begin
#0 clkfb_window <= 1;
#cycle_jitter clkfb_window <= 0;
end
end
always @(posedge clkin_fb or posedge rst_in) begin
if (rst_in)
clkin_window <= 0;
else begin
#0 clkin_window <= 1;
#cycle_jitter clkin_window <= 0;
end
end
always @(posedge clkin_fb or posedge rst_in) begin
if (rst_in)
lock_clkin <= 0;
else begin
#1
if ((clkfb_window && fb_delay_found ) || (clkin_lost_out == 1'b0 && lock_out[0]==1'b1))
lock_clkin <= 1;
else
if (chk_enable ==1 && ps_lock == 0)
lock_clkin <= 0;
end
end
always @(posedge clkfb_in or posedge rst_in) begin
if (rst_in)
lock_clkfb <= 0;
else begin
#1
if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b0 && lock_out[0]==1'b1))
lock_clkfb <= 1;
else
if (chk_enable ==1 && ps_lock == 0)
lock_clkfb <= 0;
end
end
always @(negedge clkin_fb or posedge rst_in) begin
if (rst_in)
lock_delay <= 0;
else
lock_delay <= lock_clkin || lock_clkfb;
end
//
// generate lock signal
//
assign locked_out_out = (rst_flag) ? 1'bx : locked_out;
always @(posedge clkin_ps or posedge rst_in)
if (rst_in) begin
lock_out <= 2'b00;
locked_out <=0;
end
else begin
if (clkfb_type == 0)
lock_out[0] <= lock_period;
else
lock_out[0] <= lock_period & lock_delay & lock_fb;
lock_out[1] <= lock_out[0];
locked_out <= lock_out[1];
end
always @(negedge clkin_ps or posedge rst_in)
if (rst_in)
lock_out1_neg <= 0;
else
lock_out1_neg <= lock_out[1];
//
// generate the clk1x_out
//
always @(period) begin
period_25 = period /4;
period_50 = 2 * period_25;
end
always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
if (rst_in)
clk0_out <= 0;
else if (clkin_ps ==1)
if (clk1x_type==1 && lock_out[0]) begin
clk0_out <= 1;
#(period_50);
clk0_out <= 0;
end
else
clk0_out <= 1;
else if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0] ==1 && lock_out[1] == 0)))
clk0_out <= 0;
//
// generate the clk2x_out
//
always @(posedge clkin_ps or posedge rst_in )
if (rst_in)
clk2x_out <= 0;
else begin
clk2x_out <= 1;
#(period_25)
clk2x_out <= 0;
if (lock_out[0]) begin
#(period_25);
clk2x_out <= 1;
#(period_25);
clk2x_out <= 0;
end
else begin
#(period_50);
end
end
//
// generate the clkdv_out
//
always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
if (rst_in) begin
clkdv_out <= 1'b0;
clkdv_cnt <= 0;
end
else
if (lock_out1_neg) begin
if (clkdv_cnt >= divide_type -1)
clkdv_cnt <= 0;
else
clkdv_cnt <= clkdv_cnt + 1;
if (clkdv_cnt < divide_type /2)
clkdv_out <= 1'b1;
else
if ( (divide_type[0] == 1'b1) && dll_mode_type == 2'b00)
clkdv_out <= #(period/4) 1'b0;
else
clkdv_out <= 1'b0;
end
//
//determine_clkfx_divide_multiply
//
always @( rst_in or clkfx_multiply_drp or clkfx_divide_drp)
begin
if (rst_in == 1 ) begin
numerator = clkfx_multiply_drp;
denominator = clkfx_divide_drp;
end
end
//
// generate fx output signal
//
always @(lock_period or period_fxtmp or denominator or numerator )
if (lock_period == 1'b1)
period_fxavg = (period_fxtmp * denominator) / (numerator * 2);
//always @(lock_period or period or denominator or numerator )
always @(lock_ps or period or denominator or numerator or rst_in)
if (rst_in == 1'b1) begin
period_fx = 0;
remain_fx = 0;
end
else begin
if (lock_ps == 1'b1) begin
period_fx = (period * denominator) / (numerator * 2);
remain_fx = (period * denominator) % (numerator * 2);
end
end
always @(clkfx_out_avg or clkfx_out_ph)
if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
clkfx_out = clkfx_out_avg;
else
clkfx_out = clkfx_out_ph;
always @(locked_out or posedge rst_in or clkfx_out_avg )
if (rst_in == 1)
clkfx_out_avg <= 0;
else if (locked_out == 1)
if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
clkfx_out_avg <= #(period_fxavg) ~clkfx_out_avg;
always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in)
if (rst_in == 1)
clkfx_out_ph = 0;
else if (clkin_lost_out == 1'b1 ) begin
if (locked_out == 1)
@(negedge rst_reg[2]);
end
else
if (lock_out[1] == 1 && DFS_OSCILLATOR_MODE == "PHASE_FREQ_LOCK") begin
if (lock_out[1] == 1 ) begin
clkfx_out_ph = 1'b1;
for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin
#(period_fx);
if (p < remain_fx)
#1;
clkfx_out_ph = !clkfx_out_ph;
end
if (period_fx > (period / 2)) begin
#(period_fx - (period / 2));
end
end
end
//
// detect_first_time_locked
//
always @(posedge locked_out)
if (first_time_locked == 0)
first_time_locked <= 1;
always @(ps_overflow_out or clkin_lost_out or clkfx_lost_out or
clkfb_lost_out or en_status)
if ( en_status != 1)
do_out_s[3:0] = 4'b0;
else
begin
do_out_s[0] = ps_overflow_out;
do_out_s[1] = clkin_lost_out;
do_out_s[2] = clkfx_lost_out;
do_out_s[3] = clkfb_lost_out;
end
assign do_out = (do_stat_en == 0) ? do_out_drp1 : do_out_s;
always @(posedge rst_in or posedge LOCKED)
if (rst_in == 1)
en_status <= 0;
else
en_status <= 1;
//
// drp process
//
always @(posedge dclk_in or posedge gsr_in)
if (gsr_in == 1) begin
drp_lock <= 0;
ps_in_drp <= 0;
ps_kick_off_cmd <= 0;
do_out_drp <= 16'b0;
do_out_drp1 <= 16'b0;
do_stat_en <= 1;
drdy_out <= 0;
end
else begin
valid_daddr = addr_is_valid(daddr_in);
if (DEN == 1) begin
if (drp_lock == 1)
$display(" Warning : DEN is high at DCM_ADV instance %m at time %t. Please wait for DRDY signal before next read/write operation through DRP. ", $time);
else begin
drp_lock <= 1;
if (DWE == 0 && sim_device_type == 1 ) begin
if (daddr_in == `DCM_DEFAULT_STATUS_ADDR)
do_stat_en <= 1;
else begin
do_stat_en <= 0;
if (daddr_in == `DFS_FREQ_MODE_ADDR)
do_out_drp <= dfs_mode_reg;
else if (daddr_in == `DLL_FREQ_MODE_ADDR)
do_out_drp <= dll_mode_reg;
else if (daddr_in == `CLKFX_MULTIPLY_ADDR)
do_out_drp <= clkfx_md_reg;
else if (daddr_in == `CLKIN_DIV_BY2_ADDR)
do_out_drp <= clkin_div2_reg;
else
do_out_drp <= 16'b0;
end
end
if (DWE == 1) begin
if (valid_daddr) begin
if (daddr_in == `CLKFX_MULTIPLY_ADDR) begin
if (sim_device_type == 1) begin
clkfx_divide_drp <= di_in[7:0] + 1;
clkfx_multiply_drp <= di_in[15:8] + 1;
clkfx_md_reg <= di_in;
end
else
clkfx_multiply_drp <= di_in[4:0] + 1;
end
else if (daddr_in == `CLKFX_DIVIDE_ADDR && sim_device_type == 0) begin
clkfx_divide_drp <= di_in[4:0] + 1;
end
else if (daddr_in == `PHASE_SHIFT_ADDR) begin
ps_drp <= di_in[10:0];
end
else if (daddr_in == `PHASE_SHIFT_KICK_OFF_ADDR) begin
if (ps_kick_off_cmd == 0) begin
ps_kick_off_cmd <= 1;
ps_in_drp <= ps_drp;
if (ps_in < ps_drp)
inc_dec <= 1;
else if (ps_in > ps_drp)
inc_dec <= 0;
end
end
else if (daddr_in == `DFS_FREQ_MODE_ADDR && sim_device_type == 1) begin
dfs_mode_reg <= di_in;
end
else if (daddr_in == `DLL_FREQ_MODE_ADDR && sim_device_type == 1) begin
dll_mode_reg <= di_in;
end
else if (daddr_in == `CLKIN_DIV_BY2_ADDR && sim_device_type == 1) begin
clkin_div2_reg <= di_in;
end
else
$display(" Warning : Address DADDR=%b is unsupported at DCM_ADV instance %m at time %t. ", daddr_in, $time);
end
end
end
end
if ( drp_lock == 1)
drp_lock1 <= 1;
if ( drp_lock1 == 1) begin
drp_lock <= 0;
drp_lock1 <= 0;
drdy_out <= 1;
do_out_drp1 <= do_out_drp;
do_out_drp <= 16'b0;
end
if (drdy_out == 1) begin
drdy_out <= 0;
do_out_drp1 <= 16'b0;
end
if (ps_drp_lock_tmp1 == 1) begin
if (ps_kick_off_cmd == 1)
ps_kick_off_cmd <= 0;
end
end
always @(negedge ps_drp_lock) begin
@(posedge dclk_in)
ps_drp_lock_tmp1 <= 1;
@(posedge dclk_in)
ps_drp_lock_tmp1 <= 0;
end
function addr_is_valid;
input [6:0] daddr_funcin;
begin
addr_is_valid = 1;
for (i=0; i<=6; i=i+1)
if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
addr_is_valid = 0;
end
endfunction
// end process drp;
//
// drive_drdy_out process
//
//always @(drp_lock or dclk_in or gsr_in)
// @(negedge drp_lock)
// @(posedge dclk_in) begin
// if (gsr_in == 0)
// drdy_out = 1;
// @(posedge dclk_in)
// drdy_out = 0;
// end
//
// generate all output signal
//
always @(rst_in)
if (rst_in) begin
assign CLK0 = 0;
assign CLK90 = 0;
assign CLK180 = 0;
assign CLK270 = 0;
assign CLK2X = 0;
assign CLK2X180 =0;
assign CLKDV = 0;
assign CLKFX = 0;
assign CLKFX180 = 0;
end
else begin
deassign CLK0;
deassign CLK90;
deassign CLK180;
deassign CLK270;
deassign CLK2X;
deassign CLK2X180;
deassign CLKDV;
deassign CLKFX;
deassign CLKFX180;
end
always @(clk0_out) begin
CLK0 <= #(clkout_delay) clk0_out;
CLK90 <= #(clkout_delay + period / 4) clk0_out;
CLK180 <= #(clkout_delay + period / 2) clk0_out;
CLK270 <= #(clkout_delay + period / 4) ~clk0_out;
end
always @(clk2x_out) begin
CLK2X <= #(clkout_delay) clk2x_out;
CLK2X180 <= #(clkout_delay) ~clk2x_out ;
end
always @(clkdv_out)
CLKDV <= #(clkout_delay) clkdv_out;
always @(clkfx_out )
CLKFX <= #(clkout_delay) clkfx_out;
always @( clkfx_out or first_time_locked or locked_out) begin
if ( ~first_time_locked)
CLKFX180 <= 0;
else
CLKFX180 <= #(clkout_delay) ~clkfx_out;
end
specify
(CLKIN => LOCKED) = (100:100:100, 100:100:100);
(DCLK => DO[0]) = (100:100:100, 100:100:100);
(DCLK => DO[10]) = (100:100:100, 100:100:100);
(DCLK => DO[11]) = (100:100:100, 100:100:100);
(DCLK => DO[12]) = (100:100:100, 100:100:100);
(DCLK => DO[13]) = (100:100:100, 100:100:100);
(DCLK => DO[14]) = (100:100:100, 100:100:100);
(DCLK => DO[15]) = (100:100:100, 100:100:100);
(DCLK => DO[1]) = (100:100:100, 100:100:100);
(DCLK => DO[2]) = (100:100:100, 100:100:100);
(DCLK => DO[3]) = (100:100:100, 100:100:100);
(DCLK => DO[4]) = (100:100:100, 100:100:100);
(DCLK => DO[5]) = (100:100:100, 100:100:100);
(DCLK => DO[6]) = (100:100:100, 100:100:100);
(DCLK => DO[7]) = (100:100:100, 100:100:100);
(DCLK => DO[8]) = (100:100:100, 100:100:100);
(DCLK => DO[9]) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(PSCLK => PSDONE) = (100:100:100, 100:100:100);
$period (posedge CLKIN, 1111);
$period (posedge PSCLK, 1111);
$setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PSCLK, 0:0:0, 0, notifier);
$width (negedge PSCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
endmodule
//////////////////////////////////////////////////////
module dcm_adv_clock_divide_by_2 (clock, clock_type, clock_out, rst);
input clock;
input clock_type;
input rst;
output clock_out;
reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
wire clk_src;
initial begin
clock_out = 1'b0;
clock_div2 = 1'b0;
end
always @(posedge clock)
clock_div2 <= ~clock_div2;
always @(posedge clock) begin
rst_reg[0] <= rst;
rst_reg[1] <= rst_reg[0] & rst;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst;
end
assign clk_src = (clock_type) ? clock_div2 : clock;
always @(clk_src or rst or rst_reg)
if (rst == 1'b0)
clock_out = clk_src;
else if (rst == 1'b1) begin
clock_out = 1'b0;
@(negedge rst_reg[2]);
if (clk_src == 1'b1)
@(negedge clk_src);
end
endmodule
module dcm_adv_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock )
begin
clock_edge <= $time;
clock_period <= $time - clock_edge;
if (clock_period > maximum_period && rst == 0 ) begin
$display(" Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
end
end
endmodule
module dcm_adv_clock_lost (clock, enable, lost, rst);
input clock;
input enable;
input rst;
output lost;
reg lost_r, lost_f, lost;
time clock_edge, clock_edge_neg;
time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win;
time period_chk_win;
integer clock_low, clock_high;
integer clock_posedge, clock_negedge;
integer clock_second_pos, clock_second_neg;
initial begin
clock_edge = 0;
clock_edge_neg = 0;
clock_high = 0;
clock_low = 0;
lost_r = 0;
lost_f = 0;
period = 0;
period_neg = 0;
period_tmp = 0;
period_tmp_win = 0;
period_neg_tmp = 0;
period_neg_tmp_win = 0;
period_chk_win = 0;
clock_posedge = 0;
clock_negedge = 0;
clock_second_pos = 0;
clock_second_neg = 0;
end
always @(posedge clock or negedge clock or posedge rst)
if (rst) begin
clock_second_pos <= 0;
clock_second_neg <= 0;
end
else if (clock)
clock_second_pos <= 1;
else if (~clock)
clock_second_neg <= 1;
always @(posedge clock or posedge rst)
if (rst) begin
period <= 0;
end
else begin
clock_edge <= $time;
period_tmp = $time - clock_edge;
if (period != 0 && (period_tmp <= period_tmp_win))
period <= period_tmp;
else if (period != 0 && (period_tmp > period_tmp_win))
period <= 0;
else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1)
period <= period_tmp;
end
always @(period) begin
period_tmp_win = 1.5 * period;
period_chk_win = (period * 9.1) / 10;
end
always @(negedge clock or posedge rst)
if (rst)
period_neg <= 0;
else begin
clock_edge_neg <= $time;
period_neg_tmp = $time - clock_edge_neg;
if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win))
period_neg <= period_neg_tmp;
else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win))
period_neg <= 0;
else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1)
period_neg <= period_neg_tmp;
end
always @(period_neg)
period_neg_tmp_win = 1.5 * period_neg;
always @(posedge clock or posedge rst)
if (rst)
lost_r <= 0;
else
if (enable == 1 && clock_second_pos == 1) begin
#1;
if ( period != 0)
lost_r <= 0;
#(period_chk_win)
if ((clock_low != 1) && (clock_posedge != 1) && rst == 0 )
lost_r <= 1;
end
always @(negedge clock or posedge rst)
if (rst==1) begin
lost_f <= 0;
end
else begin
if (enable == 1 && clock_second_neg == 1) begin
if ( period != 0)
lost_f <= 0;
#(period_chk_win)
if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg))
lost_f <= 1;
end
end
always @( lost_r or lost_f or enable)
if (enable == 1)
lost = lost_r | lost_f;
else
lost = 0;
always @(posedge clock or negedge clock or posedge rst)
if (rst==1) begin
clock_low <= 0;
clock_high <= 0;
clock_posedge <= 0;
clock_negedge <= 0;
end
else
if (clock ==1) begin
clock_low <= 0;
clock_high <= 1;
clock_posedge <= 0;
clock_negedge <= 1;
end
else if (clock == 0) begin
clock_low <= 1;
clock_high <= 0;
clock_posedge <= 1;
clock_negedge <= 0;
end
endmodule
`endcelldefine x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DCM_SP.v 0000664 0000000 0000000 00000111031 12327044266 0022424 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/DCM_SP.v,v 1.5 2004/03/31 22:46:10 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.73)
// \ \ Description : Xilinx Function Simulation Library Component
// / / Digital Clock Manager
// /___/ /\ Filename : DCM_SP.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 02/28/06 - Initial version.
// 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789).
// 06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283).
// 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns).
// Give warning not support initial phase shifting for variable phase shifting.
// (CR 235216).
// 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722).
// 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
// 04/06/07 - Enable the clock out in clock low time after reset in model
// clock_divide_by_2 (CR 437471).
// 07/10/07 - Remove modulaton of ps_delay_md for none and fixed delay type (CR441155)
// 08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628).
// 01/22/08 - Add () to ps_in * period_in of ps_delay_md calculation (CR466293).
// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858).
// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893)
// 03/20/08 - Not check clock lost when negative edge period smaller than positive
// edge period in dcm_sp_clock_lost module (CR469499).
// - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858).
// 05/13/08 - Change min input clock freq from 1.0Mhz to 0.2Mhz (CR467770)
// 07/16/08 - remove condition for lock_out[0] when 2x feedback (CR476637).
// 04/20/09 - Delay LOCKED (CR518620)
// 12/03/09 - Add STATUS[5]=CLKFX STATUS[7]=CLKIN (CR538362)
// 08/10/11 - change ps_max_range (CR618799).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DCM_SP (
CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS,
CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0; // non-simulatable
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DSS_MODE = "NONE"; // non-simulatable
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080; // non-simulatable
parameter integer MAXPERCLKIN = 5000000; // non-modifiable simulation parameter
parameter integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter
parameter integer PHASE_SHIFT = 0;
parameter integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter
parameter integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter
parameter STARTUP_WAIT = "FALSE"; // non-simulatable
parameter LOC = "UNPLACED";
localparam PS_STEP = 25;
input CLKFB, CLKIN, DSSEN;
input PSCLK, PSEN, PSINCDEC, RST;
output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output [7:0] STATUS;
reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
reg CLKDV, CLKFX, CLKFX180;
wire clkin_lost_out, clkfx_lost_out;
wire locked_out_out;
wire clkfb_in, clkin_in, dssen_in;
wire psclk_in, psen_in, psincdec_in, rst_in;
reg clk0_out;
reg clk2x_out, clkdv_out;
reg clkfx_out, clkfx180_en;
reg rst_flag;
reg locked_out, psdone_out, ps_overflow_out, ps_lock;
reg locked_out0;
reg locked_out_dly;
reg clkfb_div, clkfb_chk, clkfb_div_en;
integer clkdv_cnt;
reg [1:0] clkfb_type;
reg [8:0] divide_type;
reg clkin_type;
reg [1:0] ps_type;
reg [3:0] deskew_adjust_mode;
reg dfs_mode_type;
reg dll_mode_type;
reg clk1x_type;
integer ps_in;
reg lock_period, lock_delay, lock_clkin, lock_clkfb;
reg first_time_locked;
reg en_status;
reg ps_overflow_out_ext;
reg clkin_lost_out_ext;
reg clkfx_lost_out_ext;
reg [1:0] lock_out;
reg lock_out1_neg;
reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp;
reg fb_delay_found;
reg clock_stopped;
reg clkin_chkin, clkfb_chkin;
wire chk_enable, chk_rst;
wire clkin_div;
wire lock_period_pulse;
wire lock_period_dly, lock_period_dly1;
reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag;
reg clkin_fb;
time FINE_SHIFT_RANGE;
//time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range;
integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range;
integer ps_delay_last;
integer ps_acc;
time clkin_edge;
time clkin_div_edge;
time clkin_ps_edge;
time delay_edge;
time clkin_period [2:0];
time period, period_50, period_25;
integer period_int, period_int2, period_int3, period_ps_tmp;
time period_div;
integer period_orig_int;
time period_orig1;
time period_orig;
time period_ps;
time clkout_delay;
time fb_delay;
time period_fx, remain_fx;
time period_dv_high, period_dv_low;
time cycle_jitter, period_jitter;
reg clkin_window, clkfb_window;
reg [2:0] rst_reg;
reg [12:0] numerator, denominator, gcd;
reg [23:0] i, n, d, p;
reg notifier;
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller.");
$finish;
end
end
initial begin
case (CLKDV_DIVIDE)
1.5 : divide_type = 'd3;
2.0 : divide_type = 'd4;
2.5 : divide_type = 'd5;
3.0 : divide_type = 'd6;
3.5 : divide_type = 'd7;
4.0 : divide_type = 'd8;
4.5 : divide_type = 'd9;
5.0 : divide_type = 'd10;
5.5 : divide_type = 'd11;
6.0 : divide_type = 'd12;
6.5 : divide_type = 'd13;
7.0 : divide_type = 'd14;
7.5 : divide_type = 'd15;
8.0 : divide_type = 'd16;
9.0 : divide_type = 'd18;
10.0 : divide_type = 'd20;
11.0 : divide_type = 'd22;
12.0 : divide_type = 'd24;
13.0 : divide_type = 'd26;
14.0 : divide_type = 'd28;
15.0 : divide_type = 'd30;
16.0 : divide_type = 'd32;
default : begin
$display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE);
$finish;
end
endcase
if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin
$display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE);
$finish;
end
if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin
$display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY);
$finish;
end
case (CLKIN_DIVIDE_BY_2)
"false" : clkin_type = 0;
"FALSE" : clkin_type = 0;
"true" : clkin_type = 1;
"TRUE" : clkin_type = 1;
default : begin
$display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2);
$finish;
end
endcase
case (CLKOUT_PHASE_SHIFT)
"NONE" : begin
ps_in = 256;
ps_type = 2'b0;
end
"none" : begin
ps_in = 256;
ps_type = 2'b0;
end
"FIXED" : begin
ps_in = PHASE_SHIFT + 256;
ps_type = 2'b01;
end
"fixed" : begin
ps_in = PHASE_SHIFT + 256;
ps_type = 2'b01;
end
"VARIABLE" : begin
ps_in = PHASE_SHIFT + 256;
ps_type = 2'b10;
end
"variable" : begin
ps_in = PHASE_SHIFT + 256;
ps_type = 2'b10;
if (PHASE_SHIFT != 0)
$display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT);
end
default : begin
$display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT);
$finish;
end
endcase
case (CLK_FEEDBACK)
"none" : clkfb_type = 2'b00;
"NONE" : clkfb_type = 2'b00;
"1x" : clkfb_type = 2'b01;
"1X" : clkfb_type = 2'b01;
"2x" : clkfb_type = 2'b10;
"2X" : clkfb_type = 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK);
$finish;
end
endcase
case (DESKEW_ADJUST)
"source_synchronous" : deskew_adjust_mode = 8;
"SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8;
"system_synchronous" : deskew_adjust_mode = 11;
"SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11;
"0" : deskew_adjust_mode = 0;
"1" : deskew_adjust_mode = 1;
"2" : deskew_adjust_mode = 2;
"3" : deskew_adjust_mode = 3;
"4" : deskew_adjust_mode = 4;
"5" : deskew_adjust_mode = 5;
"6" : deskew_adjust_mode = 6;
"7" : deskew_adjust_mode = 7;
"8" : deskew_adjust_mode = 8;
"9" : deskew_adjust_mode = 9;
"10" : deskew_adjust_mode = 10;
"11" : deskew_adjust_mode = 11;
"12" : deskew_adjust_mode = 12;
"13" : deskew_adjust_mode = 13;
"14" : deskew_adjust_mode = 14;
"15" : deskew_adjust_mode = 15;
default : begin
$display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST);
$finish;
end
endcase
case (DFS_FREQUENCY_MODE)
"high" : dfs_mode_type = 1;
"HIGH" : dfs_mode_type = 1;
"low" : dfs_mode_type = 0;
"LOW" : dfs_mode_type = 0;
default : begin
$display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE);
$finish;
end
endcase
period_jitter = SIM_CLKIN_PERIOD_JITTER;
cycle_jitter = SIM_CLKIN_CYCLE_JITTER;
case (DLL_FREQUENCY_MODE)
"high" : dll_mode_type = 1;
"HIGH" : dll_mode_type = 1;
"low" : dll_mode_type = 0;
"LOW" : dll_mode_type = 0;
default : begin
$display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE);
$finish;
end
endcase
if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin
$display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s. CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK);
$finish;
end
case (DSS_MODE)
"none" : ;
"NONE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute is NONE.", DSS_MODE);
$finish;
end
endcase
case (DUTY_CYCLE_CORRECTION)
"false" : clk1x_type = 0;
"FALSE" : clk1x_type = 0;
"true" : clk1x_type = 1;
"TRUE" : clk1x_type = 1;
default : begin
$display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
$finish;
end
endcase
if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin
$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT);
$display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT);
$finish;
end
case (STARTUP_WAIT)
"false" : ;
"FALSE" : ;
"true" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
$finish;
end
endcase
end
//
// fx parameters
//
initial begin
gcd = 1;
for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin
if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0))
gcd = i;
end
numerator = CLKFX_MULTIPLY / gcd;
denominator = CLKFX_DIVIDE / gcd;
end
//
// input wire delays
//
buf b_clkin (clkin_in, CLKIN);
buf b_clkfb (clkfb_in, CLKFB);
buf b_dssen (dssen_in, DSSEN);
buf b_psclk (psclk_in, PSCLK);
buf b_psen (psen_in, PSEN);
buf b_psincdec (psincdec_in, PSINCDEC);
buf b_rst (rst_in, RST);
buf b_LOCKED (LOCKED, locked_out_out);
buf b_PSDONE (PSDONE, psdone_out);
buf b_ps_overflow (STATUS[0], ps_overflow_out_ext);
buf b_clkin_lost (STATUS[1], clkin_lost_out_ext);
buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext);
buf b_sts_5 (STATUS[5], clkfx_out);
buf b_sts_7 (STATUS[7], clkin_in);
assign STATUS[4:3] = 2'b0;
assign STATUS[6] = 1'b0;
dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in);
dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in);
dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in);
dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in);
always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out)
if (rst_in == 1 || en_status == 0) begin
ps_overflow_out_ext = 0;
clkin_lost_out_ext = 0;
clkfx_lost_out_ext = 0;
end
else
begin
ps_overflow_out_ext = ps_overflow_out;
clkin_lost_out_ext = clkin_lost_out;
clkfx_lost_out_ext = clkfx_lost_out;
end
always @(posedge rst_in or posedge LOCKED)
if (rst_in == 1)
en_status <= 0;
else
en_status <= 1;
always @(clkin_div)
clkin_ps_tmp <= #(ps_delay_md) clkin_div;
always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win)
if (clkin_ps_mkup_win)
clkin_ps = clkin_ps_mkup;
else
clkin_ps = clkin_ps_tmp;
always @(ps_delay_last or period_int or ps_delay) begin
period_int2 = 2 * period_int;
period_int3 = 3 * period_int;
if ((ps_delay_last >= period_int && ps_delay < period_int) ||
(ps_delay_last >= period_int2 && ps_delay < period_int2) ||
(ps_delay_last >= period_int3 && ps_delay < period_int3))
clkin_ps_mkup_flag = 1;
else
clkin_ps_mkup_flag = 0;
end
always @(posedge clkin_div or negedge clkin_div) begin
if (ps_type == 2'b10) begin
if ((ps_delay_last > 0 && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin
if (clkin_div) begin
clkin_ps_mkup_win <= 1;
clkin_ps_mkup <= 1;
#1;
@(negedge clkin_div) begin
clkin_ps_mkup_win <= 1;
clkin_ps_mkup <= 0;
end
end
else begin
clkin_ps_mkup_win <= 0;
clkin_ps_mkup <= 0;
#1;
@(posedge clkin_div) begin
clkin_ps_mkup_win <= 1;
clkin_ps_mkup <= 1;
end
@(negedge clkin_div) begin
clkin_ps_mkup_win <= 1;
clkin_ps_mkup <= 0;
end
end
end
else begin
clkin_ps_mkup_win <= 0;
clkin_ps_mkup <= 0;
end
ps_delay_last <= ps_delay;
end
end
always @(clkin_ps or lock_fb)
clkin_fb = clkin_ps & lock_fb;
always @(negedge clkfb_in or posedge rst_in)
if (rst_in)
clkfb_div_en <= 0;
else
if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps)
clkfb_div_en <= 1;
always @(posedge clkfb_in or posedge rst_in)
if (rst_in)
clkfb_div <= 0;
else
if (clkfb_div_en )
clkfb_div <= ~clkfb_div;
always @(clkfb_in or clkfb_div )
if (clkfb_type == 2'b10 )
clkfb_chk = clkfb_div;
else
clkfb_chk = clkfb_in & lock_fb_dly;
always @(posedge clkin_fb or posedge chk_rst)
if (chk_rst)
clkin_chkin <= 0;
else
clkin_chkin <= 1;
always @(posedge clkfb_chk or posedge chk_rst)
if (chk_rst)
clkfb_chkin <= 0;
else
clkfb_chkin <= 1;
assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0;
assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 &&
lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0;
always @(posedge clkin_div or posedge rst_in)
if (rst_in) begin
period_div <= 0;
clkin_div_edge <= 0;
end
else
if ( clkin_div ==1 ) begin
clkin_div_edge <= $time;
if (($time - clkin_div_edge) <= (1.5 * period_div))
period_div <= $time - clkin_div_edge;
else if ((period_div == 0) && (clkin_div_edge != 0))
period_div <= $time - clkin_div_edge;
end
always @(posedge clkin_ps or posedge rst_in)
if (rst_in) begin
period_ps <= 0;
clkin_ps_edge <= 0;
end
else
if (clkin_ps == 1 ) begin
clkin_ps_edge <= $time;
if (($time - clkin_ps_edge) <= (1.5 * period_ps))
period_ps <= $time - clkin_ps_edge;
else if ((period_ps == 0) && (clkin_ps_edge != 0))
period_ps <= $time - clkin_ps_edge;
end
always @(posedge clkin_ps) begin
lock_ps <= lock_period;
lock_ps_dly <= lock_ps;
lock_fb <= lock_ps_dly;
lock_fb_dly_tmp <= lock_fb;
end
always @(negedge clkin_ps or posedge rst_in)
if (rst_in)
lock_fb_dly <= 1'b0;
else
lock_fb_dly <= #(period * 0.75) lock_fb_dly_tmp;
always @(period or fb_delay or posedge rst_in)
if (rst_in)
clkout_delay = 0;
else begin
if (fb_delay == 0)
clkout_delay = 0;
else
clkout_delay = period - fb_delay;
end
//
// generate master reset signal
//
always @(posedge clkin_in) begin
rst_reg[0] <= rst_in;
rst_reg[1] <= rst_reg[0] & rst_in;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in;
end
reg rst_tmp1, rst_tmp2;
initial
begin
rst_tmp1 = 0;
rst_tmp2 = 0;
rst_flag = 0;
end
always @(rst_in)
begin
if (rst_in)
rst_flag = 0;
rst_tmp1 = rst_in;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin
rst_flag = 1;
$display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles.");
end
end
rst_tmp2 = rst_tmp1;
end
initial begin
CLK0 = 0;
CLK180 = 0;
CLK270 = 0;
CLK2X = 0;
CLK2X180 = 0;
CLK90 = 0;
CLKDV = 0;
CLKFX = 0;
CLKFX180 = 0;
clk0_out = 0;
clk2x_out = 0;
clkdv_out = 0;
clkdv_cnt = 0;
clkfb_window = 0;
clkfx_out = 0;
clkfx180_en = 0;
clkin_div_edge = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_edge = 0;
clkin_ps_edge = 0;
clkin_window = 0;
clkout_delay = 0;
clock_stopped = 1;
fb_delay = 0;
fb_delay_found = 0;
lock_clkfb = 0;
lock_clkin = 0;
lock_delay = 0;
lock_fb = 0;
lock_fb_dly = 0;
lock_out = 2'b00;
lock_out1_neg = 0;
lock_period = 0;
lock_ps = 0;
lock_ps_dly = 0;
locked_out = 0;
locked_out0 = 0;
locked_out_dly = 0;
period = 0;
period_int = 0;
period_int2 = 0;
period_int3 = 0;
period_div = 0;
period_fx = 0;
period_orig = 0;
period_orig_int = 0;
period_ps = 0;
psdone_out = 0;
ps_delay = 0;
ps_delay_md = 0;
ps_delay_init = 0;
ps_acc = 0;
ps_delay_all = 0;
ps_lock = 0;
ps_overflow_out = 0;
ps_overflow_out_ext = 0;
clkin_lost_out_ext = 0;
clkfx_lost_out_ext = 0;
rst_reg = 3'b000;
first_time_locked = 0;
en_status = 0;
clkfb_div = 0;
clkin_chkin = 0;
clkfb_chkin = 0;
clkin_ps_mkup = 0;
clkin_ps_mkup_win = 0;
clkin_ps_mkup_flag = 0;
ps_delay_last = 0;
clkin_ps_tmp = 0;
end
// RST less than 3 cycles, lock = x
assign locked_out_out = (rst_flag) ? 1'bx : locked_out_dly;
always @(locked_out)
locked_out_dly <= #clkout_delay locked_out;
//
// detect_first_time_locked
//
always @(posedge locked_out)
if (first_time_locked == 0)
first_time_locked <= 1;
//
// phase shift parameters
//
always @(posedge lock_period)
ps_delay_init <= ps_in * period_orig /256;
always @(period) begin
period_int = period;
if (clkin_type==1)
period_ps_tmp = 2 * period;
else
period_ps_tmp = period;
if (period_ps_tmp > 3000) begin
if (period_ps_tmp > 16667)
ps_max_range = (10 * (period_ps_tmp - 3000))/1000;
else
ps_max_range = (15 * (period_ps_tmp - 3000))/1000;
end
else
ps_max_range = 0;
end
always @(ps_delay or rst_in or period_int or fb_delay_found)
if ( rst_in)
ps_delay_md = 0;
else if (fb_delay_found) begin
if (ps_type == 2'b10)
ps_delay_md = period_int + ps_delay % period_int;
else
ps_delay_md = period_int + (ps_in * period_int) /256;
end
always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse)
if (rst_in) begin
ps_delay <= 0;
ps_overflow_out <= 0;
ps_acc <= 0;
end
else if (lock_period_pulse)
ps_delay <= ps_delay_init;
else begin
if (ps_type == 2'b10)
if (psen_in) begin
if (ps_lock == 1)
$display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift.");
else if (lock_ps) begin
if (psincdec_in == 1) begin
if (ps_acc > ps_max_range)
ps_overflow_out <= 1;
else begin
ps_delay <= ps_delay + PS_STEP;
ps_acc <= ps_acc + 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
else if (psincdec_in == 0) begin
if (ps_acc < -ps_max_range)
ps_overflow_out <= 1;
else begin
ps_delay <= ps_delay - PS_STEP;
ps_acc <= ps_acc - 1;
ps_overflow_out <= 0;
end
ps_lock <= 1;
end
end
end
if (psdone_out)
ps_lock <= 0;
end
always @(posedge ps_lock) begin
@(posedge clkin_ps);
@(posedge psclk_in);
@(posedge psclk_in);
@(posedge psclk_in)
psdone_out <= 1;
@(posedge psclk_in)
psdone_out <= 0;
// ps_lock <= 0;
end
//
// determine clock period
//
always @(posedge clkin_div or negedge clkin_div or posedge rst_in)
if (rst_in == 1) begin
clkin_period[0] <= 0;
clkin_period[1] <= 0;
clkin_period[2] <= 0;
clkin_edge <= 0;
end
else
if (clkin_div == 1) begin
clkin_edge <= $time;
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
if (clkin_edge != 0)
clkin_period[0] <= $time - clkin_edge;
end
else if (clkin_div == 0)
if (lock_period == 1)
if (100000000 < clkin_period[0]/1000)
begin
end
else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin
clkin_period[0] <= clkin_period[1];
end
always @(negedge clkin_div or posedge rst_in)
if (rst_in == 1) begin
lock_period <= 0;
clock_stopped <= 1;
end
else begin
if (lock_period == 1'b0) begin
if ((clkin_period[0] != 0) &&
(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
lock_period <= 1;
period_orig <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
period <= clkin_period[0];
end
end
else if (lock_period == 1'b1) begin
if (100000000 < (clkin_period[0] / 1000)) begin
$display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
clock_stopped <= 1'b1;
end
else if ((clkin_period[0] < period_orig - period_jitter) ||
(period_orig + period_jitter < clkin_period[0])) begin
$display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
$display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else begin
period <= clkin_period[0];
clock_stopped <= 1'b0;
end
end
end
assign #1 lock_period_dly1 = lock_period;
assign #(period_50) lock_period_dly = lock_period_dly1;
assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0;
//
// determine clock delay
//
assign lock_out_fbd = lock_out[0];
always @(posedge lock_out_fbd or posedge rst_in)
if (rst_in) begin
fb_delay <= 0;
fb_delay_found <= 0;
end
else begin
if ( clkfb_type != 2'b00 && fb_delay_found == 0) begin
if (clkfb_type == 2'b01) begin
@(posedge CLK0 or rst_in)
delay_edge = $time;
end
else if (clkfb_type == 2'b10) begin
@(posedge CLK2X or rst_in)
delay_edge = $time;
end
@(posedge clkfb_in or rst_in) begin
if (clkfb_type == 2'b10) begin
period_orig1 = period_orig / 2;
fb_delay <= ($time - delay_edge) % period_orig1;
end
else
fb_delay <= ($time - delay_edge) % period_orig;
fb_delay_found <= 1;
end
end
end
//
// determine feedback lock
//
always @(posedge clkfb_chk or posedge rst_in)
if (rst_in)
clkfb_window <= 0;
else begin
clkfb_window <= 1;
#cycle_jitter clkfb_window <= 0;
end
always @(posedge clkin_fb or posedge rst_in)
if (rst_in)
clkin_window <= 0;
else begin
clkin_window <= 1;
#cycle_jitter clkin_window <= 0;
end
always @(posedge clkin_fb or posedge rst_in)
if (rst_in)
lock_clkin <= 0;
else begin
#1
if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))
lock_clkin <= 1;
else
if (chk_enable==1 && ps_lock == 0)
lock_clkin <= 0;
end
always @(posedge clkfb_chk or posedge rst_in)
if (rst_in)
lock_clkfb <= 0;
else begin
#1
if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))
lock_clkfb <= 1;
else
if (chk_enable ==1 && ps_lock == 0)
lock_clkfb <= 0;
end
always @(negedge clkin_fb or posedge rst_in)
if (rst_in)
lock_delay <= 0;
else
lock_delay <= lock_clkin || lock_clkfb;
//
// generate lock signal
//
always @(posedge clkin_ps or posedge rst_in)
if (rst_in) begin
lock_out <= 2'b0;
locked_out <=0;
locked_out0 <=0;
end
else begin
lock_out[0] <= lock_period;
lock_out[1] <= lock_out[0];
if (lock_fb_dly_tmp == 1)
locked_out0 <= lock_out[1];
locked_out <= locked_out0;
end
always @(negedge clkin_ps or posedge rst_in)
if (rst_in)
lock_out1_neg <= 0;
else
// lock_out1_neg <= lock_out[1];
lock_out1_neg <= locked_out0;
//
// generate the clk1x_out
//
always @(period) begin
period_25 = period /4;
period_50 = 2 * period_25;
end
always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
if (rst_in)
clk0_out <= 0;
else
if (clkin_ps ==1)
if (clk1x_type==1 && lock_out[0]) begin
clk0_out <= 1;
#(period_50)
clk0_out <= 0;
end
else
clk0_out <= 1;
else
if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0)))
clk0_out <= 0;
//
// generate the clk2x_out
//
always @(posedge clkin_ps or posedge rst_in )
if (rst_in)
clk2x_out <= 0;
else begin
clk2x_out <= 1;
#(period_25)
clk2x_out <= 0;
if (lock_out[0]) begin
#(period_25);
clk2x_out <= 1;
#(period_25);
clk2x_out <= 0;
end
else begin
#(period_50);
end
end
//
// generate the clkdv_out
//
always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
if (rst_in) begin
clkdv_out <= 1'b0;
clkdv_cnt <= 0;
end
else
if (lock_out1_neg) begin
if (clkdv_cnt >= divide_type -1)
clkdv_cnt <= 0;
else
clkdv_cnt <= clkdv_cnt + 1;
if (clkdv_cnt < divide_type /2)
clkdv_out <= 1'b1;
else
if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0)
clkdv_out <= #(period_25) 1'b0;
else
clkdv_out <= 1'b0;
end
//
// generate fx output signal
//
always @(lock_period or period or denominator or numerator) begin
if (lock_period == 1'b1) begin
period_fx = (period * denominator) / (numerator * 2);
remain_fx = (period * denominator) % (numerator * 2);
end
end
always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in )
if (rst_in == 1)
clkfx_out = 1'b0;
else if (clkin_lost_out == 1'b1 ) begin
if (locked_out == 1)
@(negedge rst_reg[2]);
end
else
if (locked_out0 == 1) begin
clkfx_out = 1'b1;
for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin
#(period_fx);
if (p < remain_fx)
#1;
clkfx_out = !clkfx_out;
end
if (period_fx > (period_50)) begin
#(period_fx - (period_50));
end
end
//
// generate all output signal
//
always @(rst_in)
if (rst_in) begin
assign CLK0 = 0;
assign CLK90 = 0;
assign CLK180 = 0;
assign CLK270 = 0;
assign CLK2X = 0;
assign CLK2X180 =0;
assign CLKDV = 0;
assign CLKFX = 0;
assign CLKFX180 = 0;
end
else begin
deassign CLK0;
deassign CLK90;
deassign CLK180;
deassign CLK270;
deassign CLK2X;
deassign CLK2X180;
deassign CLKDV;
deassign CLKFX;
deassign CLKFX180;
end
always @(clk0_out) begin
CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00);
CLK90 <= #(clkout_delay + period_25) clk0_out && !dll_mode_type && (clkfb_type != 2'b00);
CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00);
CLK270 <= #(clkout_delay + period_25) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00);
end
always @(clk2x_out) begin
CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00);
CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00);
end
always @(clkdv_out)
CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00);
always @(clkfx_out )
CLKFX <= #(clkout_delay) clkfx_out;
always @( clkfx_out or first_time_locked or locked_out)
if ( ~first_time_locked)
CLKFX180 = 0;
else
CLKFX180 <= #(clkout_delay) ~clkfx_out;
specify
(CLKIN => LOCKED) = (100:100:100, 100:100:100);
(PSCLK => PSDONE) = (100:100:100, 100:100:100);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier);
$period (posedge CLKIN, 1111, notifier);
$period (posedge PSCLK, 1111, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PSCLK, 0:0:0, 0, notifier);
$width (negedge PSCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
endmodule
//////////////////////////////////////////////////////
module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst);
input clock;
input clock_type;
input rst;
output clock_out;
reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
wire clk_src;
initial begin
clock_out = 1'b0;
clock_div2 = 1'b0;
end
always @(posedge clock)
clock_div2 <= ~clock_div2;
always @(posedge clock) begin
rst_reg[0] <= rst;
rst_reg[1] <= rst_reg[0] & rst;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst;
end
assign clk_src = (clock_type) ? clock_div2 : clock;
always @(clk_src or rst or rst_reg)
if (rst == 1'b0)
clock_out = clk_src;
else if (rst == 1'b1) begin
clock_out = 1'b0;
@(negedge rst_reg[2]);
if (clk_src == 1'b1)
@(negedge clk_src);
end
endmodule
module dcm_sp_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
// clock_period <= $time - clock_edge;
clock_period = $time - clock_edge;
if (clock_period > maximum_period ) begin
if (rst == 0)
$display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
end
end
endmodule
module dcm_sp_clock_lost (clock, enable, lost, rst);
input clock;
input enable;
input rst;
output lost;
time clock_edge, clock_edge_neg;
time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win;
time period_chk_win;
integer clock_low, clock_high;
integer clock_posedge, clock_negedge;
integer clock_second_pos, clock_second_neg;
reg lost_r, lost_f, lost;
initial begin
clock_edge = 0;
clock_edge_neg = 0;
clock_high = 0;
clock_low = 0;
lost_r = 0;
lost_f = 0;
period = 0;
period_neg = 0;
period_tmp = 0;
period_tmp_win = 0;
period_neg_tmp = 0;
period_neg_tmp_win = 0;
period_chk_win = 0;
clock_posedge = 0;
clock_negedge = 0;
clock_second_pos = 0;
clock_second_neg = 0;
end
always @(posedge clock or posedge rst)
if (rst==1)
period <= 0;
else begin
clock_edge <= $time;
period_tmp = $time - clock_edge;
if (period != 0 && (period_tmp <= period_tmp_win))
period <= period_tmp;
else if (period != 0 && (period_tmp > period_tmp_win))
period <= 0;
else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1)
period <= period_tmp;
end
always @(period) begin
period_tmp_win = 1.5 * period;
period_chk_win = (period * 9.1) / 10;
end
always @(negedge clock or posedge rst)
if (rst)
period_neg <= 0;
else begin
clock_edge_neg <= $time;
period_neg_tmp = $time - clock_edge_neg;
if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win))
period_neg <= period_neg_tmp;
else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win))
period_neg <= 0;
else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1)
period_neg <= period_neg_tmp;
end
always @(period_neg)
period_neg_tmp_win = 1.5 * period_neg;
always @(posedge clock or posedge rst)
if (rst)
lost_r <= 0;
else
if (enable == 1 && clock_second_pos == 1) begin
#1;
if ( period != 0)
lost_r <= 0;
#(period_chk_win)
if ((clock_low != 1) && (clock_posedge != 1) && rst == 0)
lost_r <= 1;
end
always @(posedge clock or negedge clock or posedge rst)
if (rst) begin
clock_second_pos <= 0;
clock_second_neg <= 0;
end
else if (clock)
clock_second_pos <= 1;
else if (~clock)
clock_second_neg <= 1;
always @(negedge clock or posedge rst)
if (rst==1) begin
lost_f <= 0;
end
else begin
if (enable == 1 && clock_second_neg == 1) begin
if ( period != 0)
lost_f <= 0;
#(period_chk_win)
if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg))
lost_f <= 1;
end
end
always @( lost_r or lost_f or enable)
begin
if (enable == 1)
lost = lost_r | lost_f;
else
lost = 0;
end
always @(posedge clock or negedge clock or posedge rst)
if (rst==1) begin
clock_low <= 0;
clock_high <= 0;
clock_posedge <= 0;
clock_negedge <= 0;
end
else begin
if (clock ==1) begin
clock_low <= 0;
clock_high <= 1;
clock_posedge <= 0;
clock_negedge <= 1;
end
else if (clock == 0) begin
clock_low <= 1;
clock_high <= 0;
clock_posedge <= 1;
clock_negedge <= 0;
end
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DIFFINBUF.v 0000664 0000000 0000000 00000015336 12327044266 0022726 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DIFFINBUF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
output O_B,
input DIFF_IN_N,
input DIFF_IN_P,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "DIFFINBUF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam ISTANDARD_UNUSED = 0;
// `ifndef XIL_DR
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] ISTANDARD_REG = ISTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
// `endif
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire ISTANDARD_BIN;
wire [5:0] SIM_INPUT_BUFFER_OFFSET_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "DIFFINBUF_dr.v"
// `endif
reg O_B_out;
reg O_out;
reg O_OSC_in;
reg O_B_OSC_in;
wire O_B_delay;
wire O_delay;
wire DIFF_IN_N_in;
wire DIFF_IN_P_in;
wire VREF_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire DIFF_IN_N_delay;
wire DIFF_IN_P_delay;
wire VREF_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(out_delay) O_B = O_B_delay;
// inputs with no timing checks
assign #(in_delay) DIFF_IN_N_delay = DIFF_IN_N;
assign #(in_delay) DIFF_IN_P_delay = DIFF_IN_P;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_B_delay = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
assign DIFF_IN_N_in = DIFF_IN_N_delay;
assign DIFF_IN_P_in = DIFF_IN_P_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0) begin
O_OSC_in <= ~O_OSC_in;
O_B_OSC_in <= ~O_B_OSC_in;
end
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0) begin
O_OSC_in <= 1'bx;
O_B_OSC_in <= 1'bx;
end
end
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign ISTANDARD_BIN =
(ISTANDARD_REG == "UNUSED") ? ISTANDARD_UNUSED :
ISTANDARD_UNUSED;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
always @ (trig_attr) begin
#1;
if ((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((ISTANDARD_REG != "UNUSED") && (ISTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute ISTANDARD on %s instance %m is set to %s. Legal values for this attribute are UNUSED.", MODULE_NAME, ISTANDARD_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(DIFF_IN_P_in or DIFF_IN_N_in) begin
// if(IOB_TYPE_REG == "MASTER")
O_out <= DIFF_IN_P_in;
// else
O_B_out <= DIFF_IN_N_in;
end
specify
(DIFF_IN_N => O) = (0:0:0, 0:0:0);
(DIFF_IN_N => O_B) = (0:0:0, 0:0:0);
(DIFF_IN_P => O) = (0:0:0, 0:0:0);
(DIFF_IN_P => O_B) = (0:0:0, 0:0:0);
(OSC_EN *> O) = (0:0:0, 0:0:0);
(OSC_EN *> O_B) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DNA_PORT.v 0000664 0000000 0000000 00000005670 12327044266 0022700 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Device DNA Data Access Port
// /___/ /\ Filename : DNA_PORT.v
// \ \ / \ Timestamp : Mon Oct 10 14:55:34 PDT 2005
// \___\/\___\
//
// Revision:
// 10/10/05 - Initial version.
// 05/29/07 - Added wire declaration for internal signals
// 04/07/08 - CR 469973 -- Header Description fix
// 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE[56:55]
// 09/18/08 - CR 488646 -- added period check for simprim
// 10/28/08 - IR 494079 -- Shifting of dna_value is corrected to MSB first out
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/27/12 - Removed DRC warning for SIM_DNA_VALUE (CR 669726).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
parameter [56:0] SIM_DNA_VALUE = 57'h0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output DOUT;
input CLK, DIN, READ, SHIFT;
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 57;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
reg notifier;
wire clk_in, din_in, gsr_in, read_in, shift_in;
buf b_dout (DOUT, dout_out);
buf b_clk (clk_in, CLK);
buf b_din (din_in, DIN);
buf buf_gsr (gsr_in, GSR);
buf b_read (read_in, READ);
buf b_shift (shift_in, SHIFT);
// GSR has no effect
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE;
dout_out = 1'b1;
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
// IR 494079
// dna_val = {din_in, dna_val[MSB_DNA_BITS :1]};
dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in};
dout_out = dna_val[MSB_DNA_BITS];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // DNA_PORT
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DNA_PORTE2.v 0000664 0000000 0000000 00000006252 12327044266 0023064 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DNA_PORTE2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06/07/13 - Initial version.
// 08/27/13 - Added timing support.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//`celldefine
module DNA_PORTE2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000
)(
output DOUT,
input CLK,
input DIN,
input READ,
input SHIFT
);
reg [95:0] SIM_DNA_VALUE_reg = SIM_DNA_VALUE;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DNA_PORTE2_dr.v"
`endif
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 96;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire clk_in;
wire din_in;
wire read_in;
wire shift_in;
wire clk_delay;
wire din_delay;
wire read_delay;
wire shift_delay;
assign DOUT = dout_out;
`ifdef XIL_TIMING // inputs with timing checks
assign clk_in = clk_delay;
assign din_in = din_delay;
assign read_in = read_delay;
assign shift_in = shift_delay;
`endif // `ifdef XIL_TIMING
`ifndef XIL_TIMING // inputs with timing checks
assign clk_in = CLK;
assign din_in = DIN;
assign read_in = READ;
assign shift_in = SHIFT;
`endif // `ifndef XIL_TIMING
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE_reg;
dout_out = 1'b1;
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in};
dout_out = dna_val[MSB_DNA_BITS];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
//`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP48E1.v 0000664 0000000 0000000 00000264464 12327044266 0022432 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers
// /___/ /\ Filename : DSP48E1.v
// \ \ / \ Timestamp : Thu May 21 10:14:08 PDT 2009
// \___\/\___\
//
// Revision:
// 05/21/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/24/13 - add optinv
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DSP48E1 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer ACASCREG = 1,
parameter integer ADREG = 1,
parameter integer ALUMODEREG = 1,
parameter integer AREG = 1,
parameter AUTORESET_PATDET = "NO_RESET",
parameter A_INPUT = "DIRECT",
parameter integer BCASCREG = 1,
parameter integer BREG = 1,
parameter B_INPUT = "DIRECT",
parameter integer CARRYINREG = 1,
parameter integer CARRYINSELREG = 1,
parameter integer CREG = 1,
parameter integer DREG = 1,
parameter integer INMODEREG = 1,
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0,
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [4:0] IS_INMODE_INVERTED = 5'b0,
parameter [6:0] IS_OPMODE_INVERTED = 7'b0,
parameter [47:0] MASK = 48'h3FFFFFFFFFFF,
parameter integer MREG = 1,
parameter integer OPMODEREG = 1,
parameter [47:0] PATTERN = 48'h000000000000,
parameter integer PREG = 1,
parameter SEL_MASK = "MASK",
parameter SEL_PATTERN = "PATTERN",
parameter USE_DPORT = "FALSE",
parameter USE_MULT = "MULTIPLY",
parameter USE_PATTERN_DETECT = "NO_PATDET",
parameter USE_SIMD = "ONE48"
)(
output [29:0] ACOUT,
output [17:0] BCOUT,
output CARRYCASCOUT,
output [3:0] CARRYOUT,
output MULTSIGNOUT,
output OVERFLOW,
output [47:0] P,
output PATTERNBDETECT,
output PATTERNDETECT,
output [47:0] PCOUT,
output UNDERFLOW,
input [29:0] A,
input [29:0] ACIN,
input [3:0] ALUMODE,
input [17:0] B,
input [17:0] BCIN,
input [47:0] C,
input CARRYCASCIN,
input CARRYIN,
input [2:0] CARRYINSEL,
input CEA1,
input CEA2,
input CEAD,
input CEALUMODE,
input CEB1,
input CEB2,
input CEC,
input CECARRYIN,
input CECTRL,
input CED,
input CEINMODE,
input CEM,
input CEP,
input CLK,
input [24:0] D,
input [4:0] INMODE,
input MULTSIGNIN,
input [6:0] OPMODE,
input [47:0] PCIN,
input RSTA,
input RSTALLCARRYIN,
input RSTALUMODE,
input RSTB,
input RSTC,
input RSTCTRL,
input RSTD,
input RSTINMODE,
input RSTM,
input RSTP
);
// define constants
localparam MODULE_NAME = "DSP48E1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
tri0 GSR = glbl.GSR;
//------------------- constants -------------------------
localparam MAX_ACOUT = 30;
localparam MAX_BCOUT = 18;
localparam MAX_CARRYOUT = 4;
localparam MAX_P = 48;
localparam MAX_PCOUT = 48;
localparam MAX_A = 30;
localparam MAX_ACIN = 30;
localparam MAX_ALUMODE = 4;
localparam MAX_A_MULT = 25;
localparam MAX_B = 18;
localparam MAX_B_MULT = 18;
localparam MAX_BCIN = 18;
localparam MAX_C = 48;
localparam MAX_CARRYINSEL = 3;
localparam MAX_D = 25;
localparam MAX_INMODE = 5;
localparam MAX_OPMODE = 7;
localparam MAX_PCIN = 48;
localparam MAX_ALU_FULL = 48;
localparam MAX_ALU_HALF = 24;
localparam MAX_ALU_QUART = 12;
localparam MSB_ACOUT = MAX_ACOUT - 1;
localparam MSB_BCOUT = MAX_BCOUT - 1;
localparam MSB_CARRYOUT = MAX_CARRYOUT - 1;
localparam MSB_P = MAX_P - 1;
localparam MSB_PCOUT = MAX_PCOUT - 1;
localparam MSB_A = MAX_A - 1;
localparam MSB_ACIN = MAX_ACIN - 1;
localparam MSB_ALUMODE = MAX_ALUMODE - 1;
localparam MSB_A_MULT = MAX_A_MULT - 1;
localparam MSB_B = MAX_B - 1;
localparam MSB_B_MULT = MAX_B_MULT - 1;
localparam MSB_BCIN = MAX_BCIN - 1;
localparam MSB_C = MAX_C - 1;
localparam MSB_CARRYINSEL = MAX_CARRYINSEL - 1;
localparam MSB_D = MAX_D - 1;
localparam MSB_INMODE = MAX_INMODE - 1;
localparam MSB_OPMODE = MAX_OPMODE - 1;
localparam MSB_PCIN = MAX_PCIN - 1;
localparam MSB_ALU_FULL = MAX_ALU_FULL - 1;
localparam MSB_ALU_HALF = MAX_ALU_HALF - 1;
localparam MSB_ALU_QUART = MAX_ALU_QUART - 1;
localparam SHIFT_MUXZ = 17;
wire [3:0] IS_ALUMODE_INVERTED_BIN = IS_ALUMODE_INVERTED;
wire [0:0] IS_CARRYIN_INVERTED_BIN = IS_CARRYIN_INVERTED;
wire [0:0] IS_CLK_INVERTED_BIN = IS_CLK_INVERTED;
wire [4:0] IS_INMODE_INVERTED_BIN = IS_INMODE_INVERTED;
wire [6:0] IS_OPMODE_INVERTED_BIN = IS_OPMODE_INVERTED;
reg [29:0] a_o_mux, qa_o_mux, qa_o_reg1, qa_o_reg2, qacout_o_mux;
// new
reg [4:0] qinmode_o_mux, qinmode_o_reg;
// new
wire [24:0] a_preaddsub;
reg [17:0] b_o_mux, qb_o_mux, qb_o_reg1, qb_o_reg2, qbcout_o_mux;
reg [2:0] qcarryinsel_o_mux, qcarryinsel_o_reg1;
// new
reg [MSB_D:0] d_o_mux, qd_o_mux, qd_o_reg1;
reg [(MSB_A_MULT+MSB_B_MULT+1):0] qmult_o_mux, qmult_o_reg;
reg [47:0] qc_o_mux, qc_o_reg1;
reg [47:0] qp_o_mux, qp_o_reg1;
reg [47:0] qx_o_mux, qy_o_mux, qz_o_mux;
reg [6:0] qopmode_o_mux, qopmode_o_reg1;
reg notifier;
reg qcarryin_o_mux0, qcarryin_o_reg0, qcarryin_o_mux7, qcarryin_o_reg7;
reg qcarryin_o_mux, qcarryin_o_reg;
reg [3:0] qalumode_o_mux, qalumode_o_reg1;
reg invalid_opmode, opmode_valid_flag, ping_opmode_drc_check = 0;
// reg [47:0] alu_o;
wire [47:0] alu_o;
reg qmultsignout_o_reg, multsignout_o_mux;
wire multsignout_o_opmode;
reg [MAX_ALU_FULL:0] alu_full_tmp;
reg [MAX_ALU_HALF:0] alu_hlf1_tmp, alu_hlf2_tmp;
reg [MAX_ALU_QUART:0] alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp;
wire pdet_o_mux, pdetb_o_mux;
wire [47:0] the_pattern;
reg [47:0] the_mask = 0;
wire carrycascout_o;
reg carrycascout_o_reg = 0;
reg carrycascout_o_mux = 0;
// reg [3:0] carryout_o = 0;
// CR 577648
// reg [3:0] carryout_o_reg = 0;
// reg [3:0] carryout_o_mux = 0;
// CR 588861
reg [3:0] carryout_o_reg = 0;
reg [3:0] carryout_o_mux;
wire [3:0] carryout_x_o;
wire pdet_o, pdetb_o;
reg pdet_o_reg1, pdet_o_reg2, pdetb_o_reg1, pdetb_o_reg2;
wire overflow_o, underflow_o;
wire [(MSB_A_MULT+MSB_B_MULT+1):0] mult_o;
// new
wire [MSB_A_MULT:0] ad_addsub, ad_mult;
reg [MSB_A_MULT:0] qad_o_reg1, qad_o_mux;
wire [MSB_B_MULT:0] b_mult;
wire [MSB_A:0] a_in;
wire [MSB_ACIN:0] acin_in;
wire [MSB_B:0] b_in;
wire [MSB_BCIN:0] bcin_in;
wire [MSB_CARRYINSEL:0] carryinsel_in;
wire [MSB_PCIN:0] pcin_in, c_in;
wire [MSB_OPMODE:0] opmode_in;
wire [MSB_ALUMODE:0] alumode_in;
wire carryin_in;
wire carrycascin_in;
wire cep_in;
wire cea1_in;
wire cea2_in;
wire cealumode_in;
wire ceb1_in;
wire ceb2_in;
wire cec_in;
wire cead_in;
wire ced_in;
wire cecarryin_in;
wire cectrl_in;
wire ceinmode_in;
wire cem_in;
wire clk_in;
wire [MSB_D:0] d_in;
wire gsr_in;
wire [MSB_INMODE:0] inmode_in;
wire multsignin_in;
wire rstp_in;
wire rsta_in;
wire rstalumode_in;
wire rstb_in;
wire rstallcarryin_in;
wire rstc_in;
wire rstctrl_in;
wire rstd_in;
wire rstinmode_in;
wire rstm_in;
wire [MSB_A:0] a_dly;
wire [MSB_ACIN:0] acin_dly;
wire [MSB_B:0] b_dly;
wire [MSB_BCIN:0] bcin_dly;
wire [MSB_CARRYINSEL:0] carryinsel_dly;
wire [MSB_PCIN:0] pcin_dly, c_dly;
wire [MSB_OPMODE:0] opmode_dly;
wire [MSB_ALUMODE:0] alumode_dly;
wire carryin_dly;
wire carrycascin_dly;
wire cep_dly;
wire cea1_dly;
wire cea2_dly;
wire cealumode_dly;
wire ceb1_dly;
wire ceb2_dly;
wire cec_dly;
wire cead_dly;
wire ced_dly;
wire cecarryin_dly;
wire cectrl_dly;
wire ceinmode_dly;
wire cem_dly;
wire clk_dly;
wire [MSB_D:0] d_dly;
wire [MSB_INMODE:0] inmode_dly;
wire multsignin_dly;
wire rstp_dly;
wire rsta_dly;
wire rstalumode_dly;
wire rstb_dly;
wire rstallcarryin_dly;
wire rstc_dly;
wire rstctrl_dly;
wire rstd_dly;
wire rstinmode_dly;
wire rstm_dly;
wire nrsta;
wire nrstb;
wire nrstc;
wire nrstp;
wire nrstallcarryin;
wire nrstctrl;
wire cea12_enable;
wire ceb12_enable;
wire a_enable;
wire b_enable;
wire c_enable;
wire acin_enable;
wire bcin_enable;
wire carryin_enable;
wire CarryinSel_enable;
wire Opmode_enable;
wire pcin_enable;
//----------------------------------------------------------------------
//------------------------ Output Ports ------------------------------
//----------------------------------------------------------------------
buf b_acout_o[MSB_ACOUT:0] (ACOUT, qacout_o_mux);
buf b_bcout_o[MSB_BCOUT:0] (BCOUT, qbcout_o_mux);
buf b_carrycascout (CARRYCASCOUT, carrycascout_o_mux);
buf b_carryout[MSB_CARRYOUT:0] (CARRYOUT, carryout_x_o);
buf b_multsignout (MULTSIGNOUT, multsignout_o_mux);
buf b_overflow (OVERFLOW, overflow_o);
buf b_p_o[MSB_P:0] (P, qp_o_mux);
buf b_pcout_o[MSB_PCOUT:0] (PCOUT, qp_o_mux);
buf b_patterndetect (PATTERNDETECT, pdet_o_mux);
buf b_patternbdetect (PATTERNBDETECT, pdetb_o_mux);
buf b_underflow (UNDERFLOW, underflow_o);
//-----------------------------------------------------
//----------- Inputs --------------------------------
//-----------------------------------------------------
buf b_gsr (gsr_in, GSR);
`ifndef XIL_TIMING
assign a_dly = A;
assign acin_dly = ACIN;
assign alumode_dly = ALUMODE;
assign b_dly = B;
assign bcin_dly = BCIN;
assign c_dly = C;
assign carrycascin_dly = CARRYCASCIN;
assign carryin_dly = CARRYIN;
assign carryinsel_dly = CARRYINSEL;
assign cea1_dly = CEA1;
assign cea2_dly = CEA2;
assign cead_dly = CEAD;
assign cealumode_dly = CEALUMODE;
assign ceb1_dly = CEB1;
assign ceb2_dly = CEB2;
assign cec_dly = CEC;
assign cecarryin_dly = CECARRYIN;
assign cectrl_dly = CECTRL;
assign ced_dly = CED;
assign ceinmode_dly = CEINMODE;
assign cem_dly = CEM;
assign cep_dly = CEP;
assign clk_dly = CLK;
assign d_dly = D;
assign inmode_dly = INMODE;
assign multsignin_dly = MULTSIGNIN;
assign opmode_dly = OPMODE;
assign pcin_dly = PCIN;
assign rsta_dly = RSTA;
assign rstallcarryin_dly = RSTALLCARRYIN;
assign rstalumode_dly = RSTALUMODE;
assign rstb_dly = RSTB;
assign rstc_dly = RSTC;
assign rstctrl_dly = RSTCTRL;
assign rstd_dly = RSTD;
assign rstinmode_dly = RSTINMODE;
assign rstm_dly = RSTM;
assign rstp_dly = RSTP;
`endif // `ifndef XIL_TIMING
assign a_in = a_dly;
assign acin_in = acin_dly;
assign alumode_in = alumode_dly ^ IS_ALUMODE_INVERTED_BIN;
assign b_in = b_dly;
assign bcin_in = bcin_dly;
assign c_in = c_dly;
assign carrycascin_in = carrycascin_dly;
assign carryin_in = carryin_dly ^ IS_CARRYIN_INVERTED_BIN;
assign carryinsel_in = carryinsel_dly;
assign cea1_in = cea1_dly;
assign cea2_in = cea2_dly;
assign cead_in = cead_dly;
assign cealumode_in = cealumode_dly;
assign ceb1_in = ceb1_dly;
assign ceb2_in = ceb2_dly;
assign cec_in = cec_dly;
assign cecarryin_in = cecarryin_dly;
assign cectrl_in = cectrl_dly;
assign ced_in = ced_dly;
assign ceinmode_in = ceinmode_dly;
assign cem_in = cem_dly;
assign cep_in = cep_dly;
assign clk_in = clk_dly ^ IS_CLK_INVERTED_BIN;
assign d_in = d_dly;
assign inmode_in = inmode_dly ^ IS_INMODE_INVERTED_BIN;
assign multsignin_in = multsignin_dly;
assign opmode_in = opmode_dly ^ IS_OPMODE_INVERTED_BIN;
assign pcin_in = pcin_dly;
assign rsta_in = rsta_dly;
assign rstallcarryin_in = rstallcarryin_dly;
assign rstalumode_in = rstalumode_dly;
assign rstb_in = rstb_dly;
assign rstc_in = rstc_dly;
assign rstctrl_in = rstctrl_dly;
assign rstd_in = rstd_dly;
assign rstinmode_in = rstinmode_dly;
assign rstm_in = rstm_dly;
assign rstp_in = rstp_dly;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in) begin
assign qcarryin_o_reg0 = 1'b0;
assign qcarryinsel_o_reg1 = 3'b0;
assign qopmode_o_reg1 = 7'b0;
assign qalumode_o_reg1 = 4'b0;
assign qa_o_reg1 = 30'b0;
assign qa_o_reg2 = 30'b0;
assign qb_o_reg1 = 18'b0;
assign qb_o_reg2 = 18'b0;
assign qc_o_reg1 = 48'b0;
assign qp_o_reg1 = 48'b0;
assign qmult_o_reg = 36'b0;
assign pdet_o_reg1 = 1'b0;
assign pdet_o_reg2 = 1'b0;
assign pdetb_o_reg1 = 1'b0;
assign pdetb_o_reg2 = 1'b0;
// 577648 commented out the following line
// assign carryout_o_reg = 4'b0;
assign carrycascout_o_reg = 1'b0;
assign qmultsignout_o_reg = 1'b0;
assign qd_o_reg1 = 25'b0;
assign qad_o_reg1 = 25'b0;
assign qinmode_o_reg = 5'b0;
end
else begin
deassign qcarryin_o_reg0;
deassign qcarryinsel_o_reg1;
deassign qopmode_o_reg1;
deassign qalumode_o_reg1;
deassign qa_o_reg1;
deassign qa_o_reg2;
deassign qb_o_reg1;
deassign qb_o_reg2;
deassign qc_o_reg1;
deassign qp_o_reg1;
deassign qmult_o_reg;
deassign pdet_o_reg1;
deassign pdet_o_reg2;
deassign pdetb_o_reg1;
deassign pdetb_o_reg2;
// 577648 commented out the following line
// deassign carryout_o_reg;
deassign carrycascout_o_reg;
deassign qmultsignout_o_reg;
deassign qd_o_reg1;
deassign qad_o_reg1;
deassign qinmode_o_reg;
end
end
initial begin
opmode_valid_flag <= 1;
invalid_opmode <= 1;
//-------- A_INPUT check
case (A_INPUT)
"DIRECT", "CASCADE" : ;
default : begin
$display("Attribute Syntax Error : The attribute A_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", A_INPUT);
$finish;
end
endcase
//-------- ALUMODEREG check
case (ALUMODEREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute ALUMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ALUMODEREG);
$finish;
end
endcase
//-------- AREG check
case (AREG)
0, 1, 2 : ;
default : begin
$display("Attribute Syntax Error : The attribute AREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG);
$finish;
end
endcase
//-------- (ACASCREG) and (ACASCREG vs AREG) check
case (AREG)
0 : if(AREG != ACASCREG) begin
$display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 0 when attribute AREG = 0.", ACASCREG);
$finish;
end
1 : if(AREG != ACASCREG) begin
$display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 1 when attribute AREG = 1.", ACASCREG);
$finish;
end
2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin
$display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = 2.", ACASCREG);
$finish;
end
default : ;
endcase
//-------- B_INPUT check
case (B_INPUT)
"DIRECT", "CASCADE" : ;
default : begin
$display("Attribute Syntax Error : The attribute B_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT);
$finish;
end
endcase
//-------- BREG check
case (BREG)
0, 1, 2 : ;
default : begin
$display("Attribute Syntax Error : The attribute BREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG);
$finish;
end
endcase
//-------- (BCASCREG) and (BCASCREG vs BREG) check
case (BREG)
0 : if(BREG != BCASCREG) begin
$display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 0 when attribute BREG = 0.", BCASCREG);
$finish;
end
1 : if(BREG != BCASCREG) begin
$display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 1 when attribute BREG = 1.", BCASCREG);
$finish;
end
2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin
$display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to either 2 or 1 when attribute BREG = 2.", BCASCREG);
$finish;
end
default : ;
endcase
//-------- CARRYINREG check
case (CARRYINREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute CARRYINREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINREG);
$finish;
end
endcase
//-------- CARRYINSELREG check
case (CARRYINSELREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINSELREG);
$finish;
end
endcase
//-------- CREG check
case (CREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute CREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, or 1.", CREG);
$finish;
end
endcase
//-------- OPMODEREG check
case (OPMODEREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute OPMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", OPMODEREG);
$finish;
end
endcase
//-------- USE_MULT
case (USE_MULT)
"NONE", "MULTIPLY", "DYNAMIC" : ;
default : begin
$display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", USE_MULT);
$finish;
end
/*
"MULT" : if (MREG != 0) begin
$display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 0.", USE_MULT);
$finish;
end
"MULT_S" : if (MREG != 1) begin
$display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 1.", USE_MULT);
$finish;
end
default : begin
$display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are NONE, MULT or MULT_S.", USE_MULT);
$finish;
end
*/
endcase
//-------- USE_PATTERN_DETECT
case (USE_PATTERN_DETECT)
"PATDET", "NO_PATDET" : ;
default : begin
$display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATDET or NO_PATDET.", USE_PATTERN_DETECT);
$finish;
end
endcase
//-------- AUTORESET_PATDET check
case (AUTORESET_PATDET)
"NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" : ;
default : begin
$display("Attribute Syntax Error : The attribute AUTORESET_PATDET on DSP48E1 instance %m is set to %s. Legal values for this attribute are NO_RESET or RESET_MATCH or RESET_NOT_MATCH.", AUTORESET_PATDET);
$finish;
end
endcase
//-------- SEL_PATTERN check
case(SEL_PATTERN)
"PATTERN", "C" : ;
default : begin
$display("Attribute Syntax Error : The attribute SEL_PATTERN on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATTERN or C.", SEL_PATTERN);
$finish;
end
endcase
//-------- SEL_MASK check
case(SEL_MASK)
"MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" : ;
default : begin
$display("Attribute Syntax Error : The attribute SEL_MASK on DSP48E1 instance %m is set to %s. Legal values for this attribute are MASK or C or ROUNDING_MODE1 or ROUNDING_MODE2.", SEL_MASK);
$finish;
end
endcase
//-------- MREG check
case (MREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", MREG);
$finish;
end
endcase
//-------- PREG check
case (PREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute PREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", PREG);
$finish;
end
endcase
#100010 ping_opmode_drc_check <= 1;
//*********************************************************
//*** ADDITIONAL DRC
//*********************************************************
// CR 219407 -- (1)
// old ask vicv
/*
if((AUTORESET_PATTERN_DETECT == "TRUE") && (USE_PATTERN_DETECT == "NO_PATDET")) begin
$display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. ");
end
*/
//*********************************************************
//*** new attribute DRC
//*********************************************************
//-------- ADREG check
case (ADREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute ADREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ADREG);
$finish;
end
endcase
//-------- DREG check
case (DREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute DREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", DREG);
$finish;
end
endcase
//-------- INMODEREG check
case (INMODEREG)
0, 1 : ;
default : begin
$display("Attribute Syntax Error : The attribute INMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", INMODEREG);
$finish;
end
endcase
//-------- USE_DPORT
case (USE_DPORT)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute USE_DPORT on DSP48E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", USE_DPORT);
$finish;
end
endcase
end
//*********************************************************
//********** INMODE signal registering ************
//*********************************************************
// new
always @(posedge clk_in) begin
if (rstinmode_in)
qinmode_o_reg <= 5'b0;
else if (ceinmode_in)
qinmode_o_reg <= inmode_in;
end
generate
case (INMODEREG)
0: begin
always @(inmode_in)
qinmode_o_mux <= inmode_in;
end
1: begin
always @(qinmode_o_reg)
qinmode_o_mux <= qinmode_o_reg;
end
endcase
endgenerate
//*********************************************************
//*** Input register A with 2 level deep of registers
//*********************************************************
generate
case (A_INPUT)
"DIRECT" : always @(a_in) a_o_mux <= a_in;
"CASCADE" : always @(acin_in) a_o_mux <= acin_in;
endcase
endgenerate
generate
case (AREG)
1 : begin
always @(posedge clk_in) begin
if (rsta_in) begin
qa_o_reg1 <= 30'b0;
qa_o_reg2 <= 30'b0;
end
else begin
if (cea1_in)
qa_o_reg1 <= a_o_mux;
if (cea2_in)
qa_o_reg2 <= a_o_mux;
end
end
end
2 : begin
always @(posedge clk_in) begin
if (rsta_in) begin
qa_o_reg1 <= 30'b0;
qa_o_reg2 <= 30'b0;
end
else begin
if (cea1_in)
qa_o_reg1 <= a_o_mux;
if (cea2_in)
qa_o_reg2 <= qa_o_reg1;
end
end
end
endcase
endgenerate
generate
case (AREG)
0: always @(a_o_mux) qa_o_mux <= a_o_mux;
1,2 : always @(qa_o_reg2) qa_o_mux <= qa_o_reg2;
endcase
endgenerate
generate
case (ACASCREG)
1: always @(qa_o_mux or qa_o_reg1) begin
if(AREG == 2)
qacout_o_mux <= qa_o_reg1;
else
qacout_o_mux <= qa_o_mux;
end
0,2 : always @(qa_o_mux) qacout_o_mux <= qa_o_mux;
endcase
endgenerate
// new
assign a_preaddsub = qinmode_o_mux[1]? 25'b0:(qinmode_o_mux[0]?qa_o_reg1[24:0]:qa_o_mux[24:0]);
//*********************************************************
//*** Input register B with 2 level deep of registers
//*********************************************************
generate
case (B_INPUT)
"DIRECT" : always @(b_in) b_o_mux <= b_in;
"CASCADE" : always @(bcin_in) b_o_mux <= bcin_in;
endcase
endgenerate
generate
case (BREG)
1 : begin
always @(posedge clk_in) begin
if (rstb_in) begin
qb_o_reg1 <= 18'b0;
qb_o_reg2 <= 18'b0;
end
else begin
if (ceb1_in)
qb_o_reg1 <= b_o_mux;
if (ceb2_in)
qb_o_reg2 <= b_o_mux;
end
end
end
2 : begin
always @(posedge clk_in) begin
if (rstb_in) begin
qb_o_reg1 <= 18'b0;
qb_o_reg2 <= 18'b0;
end
else begin
if (ceb1_in)
qb_o_reg1 <= b_o_mux;
if (ceb2_in)
qb_o_reg2 <= qb_o_reg1;
end
end
end
endcase
endgenerate
generate
case (BREG)
0: always @(b_o_mux) qb_o_mux <= b_o_mux;
1,2 : always @(qb_o_reg2) qb_o_mux <= qb_o_reg2;
endcase
endgenerate
generate
case (BCASCREG)
1: always @(qb_o_mux or qb_o_reg1) begin
if(BREG == 2)
qbcout_o_mux <= qb_o_reg1;
else
qbcout_o_mux <= qb_o_mux;
end
0,2 : always @(qb_o_mux) qbcout_o_mux <= qb_o_mux;
endcase
endgenerate
// new
assign b_mult = qinmode_o_mux[4]?qb_o_reg1:qb_o_mux;
//*********************************************************
//*** Input register C with 1 level deep of register
//*********************************************************
always @(posedge clk_in) begin
if (rstc_in)
qc_o_reg1 <= 48'b0;
else if (cec_in)
qc_o_reg1 <= c_in;
end
generate
case (CREG)
0 : always @(c_in) qc_o_mux <= c_in;
1 : always @(qc_o_reg1) qc_o_mux <= qc_o_reg1;
endcase
endgenerate
// new
//*********************************************************
//*** Input register D with 1 level deep of register
//*********************************************************
always @(posedge clk_in) begin
if (rstd_in)
qd_o_reg1 <= 25'b0;
else if (ced_in)
qd_o_reg1 <= d_in;
end
generate
case (DREG)
0 : always @(d_in) qd_o_mux <= d_in;
1 : always @(qd_o_reg1) qd_o_mux <= qd_o_reg1;
endcase
endgenerate
//*********************************************************
//*** Preaddsub AD register with 1 level deep of register
//*********************************************************
// new
assign ad_addsub = qinmode_o_mux[3]?(-a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0)):(a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0));
always @(posedge clk_in) begin
if (rstd_in)
qad_o_reg1 <= 25'b0;
else if (cead_in)
qad_o_reg1 <= ad_addsub;
end
generate
case (ADREG)
0 : always @(ad_addsub) qad_o_mux <= ad_addsub;
1 : always @(qad_o_reg1) qad_o_mux <= qad_o_reg1;
endcase
endgenerate
/*------------------------------------------------- */
/*------------------------------------------------- */
assign ad_mult = (USE_DPORT=="TRUE")? qad_o_mux : a_preaddsub;
//*********************************************************
//*********************************************************
//*************** 25x18 Multiplier ***************
//*********************************************************
// 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE
// SIMD=FOUR12 and SIMD=TWO24
// Made mult_o to be "X"
always @(qopmode_o_mux) begin
if(qopmode_o_mux[3:0] == 4'b0101)
if((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))
$display("OPMODE Input Warning : The OPMODE[3:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", qopmode_o_mux[3:0], $time/1000.0);
end
assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))? 43'b0 : {{18{ad_mult[24]}}, ad_mult[24:0]} * {{25{b_mult[17]}}, b_mult};
always @(posedge clk_in) begin
if (rstm_in) begin
qmult_o_reg <= 18'b0;
end
else if (cem_in) begin
qmult_o_reg <= mult_o;
end
end
generate
case (MREG)
0 : always @(mult_o) qmult_o_mux <= mult_o;
1 : always @(qmult_o_reg) qmult_o_mux <= qmult_o_reg;
endcase
endgenerate
//*** X mux
// ask jmt
always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux[1:0] or qcarryinsel_o_mux) begin
case (qopmode_o_mux[1:0])
2'b00 : qx_o_mux <= 48'b0;
2'b01 : qx_o_mux <= {{5{qmult_o_mux[MSB_A_MULT + MSB_B_MULT + 1]}}, qmult_o_mux};
2'b10 : qx_o_mux <= qp_o_mux;
// new DRC
2'b11 : begin
if((USE_MULT == "MULTIPLY") && (
(AREG==0 && BREG==0 && MREG==0) ||
(AREG==0 && BREG==0 && PREG==0) ||
(MREG==0 && PREG==0)))
$display("OPMODE Input Warning : The OPMODE[1:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = MULTIPLY at %.3f ns. Please set USE_MULT to either NONE or DYNAMIC.", qopmode_o_mux[1:0], $time/1000.0);
else
qx_o_mux <= {qa_o_mux[MSB_A:0], qb_o_mux[MSB_B:0]};
end
default : begin
end
endcase
end
//*** Y mux
// 08-06-08
// IR 478378
wire [47:0] y_mac_cascd = (qopmode_o_mux[6:4] == 3'b100) ? {48{multsignin_in}} : {48{1'b1}};
always @(qc_o_mux or qopmode_o_mux[3:2] or qcarryinsel_o_mux or y_mac_cascd) begin
case (qopmode_o_mux[3:2])
2'b00 : qy_o_mux <= 48'b0;
2'b01 : qy_o_mux <= 48'b0;
// 08-06-08
2'b10 : qy_o_mux <= y_mac_cascd; // choose all ones or mult-sign-extend
2'b11 : qy_o_mux <= qc_o_mux;
default : begin
end
endcase
end
//*** Z mux
always @(qp_o_mux or qc_o_mux or pcin_in or qopmode_o_mux[6:4] or qcarryinsel_o_mux) begin
// ask jmt
casex (qopmode_o_mux[6:4])
3'b000 : qz_o_mux <= 48'b0;
3'b001 : qz_o_mux <= pcin_in;
3'b010 : qz_o_mux <= qp_o_mux;
3'b011 : qz_o_mux <= qc_o_mux;
3'b100 : qz_o_mux <= qp_o_mux;
3'b101 : qz_o_mux <= {{17{pcin_in[47]}}, pcin_in[47:17]};
// ask jmt
3'b11x : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]};
default : begin
end
endcase
end
//*** CarryInSel and OpMode with 1 level of register
always @(posedge clk_in) begin
if (rstctrl_in) begin
qcarryinsel_o_reg1 <= 3'b0;
qopmode_o_reg1 <= 7'b0;
end
else if (cectrl_in) begin
qcarryinsel_o_reg1 <= carryinsel_in;
qopmode_o_reg1 <= opmode_in;
end
end
generate
case (CARRYINSELREG)
0 : always @(carryinsel_in) qcarryinsel_o_mux <= carryinsel_in;
1 : always @(qcarryinsel_o_reg1) qcarryinsel_o_mux <= qcarryinsel_o_reg1;
endcase
endgenerate
//CR 219047 (3)
// always @(qcarryinsel_o_mux or multsignin_in or qopmode_o_mux) begin
// always @(carrycascin_in or multsignin_in or qopmode_o_mux) begin
always @(qcarryinsel_o_mux or carrycascin_in or multsignin_in or qopmode_o_mux) begin
if(qcarryinsel_o_mux == 3'b010) begin
if(!((multsignin_in === 1'bx) || ((qopmode_o_mux == 7'b1001000) && !(multsignin_in === 1'bx))
|| ((multsignin_in == 1'b0) && (carrycascin_in == 1'b0)))) begin
$display("DRC warning : CARRYCASCIN can only be used in the current DSP48E1 instance %m if the previous DSP48E1 is performing a two input ADD operation, or the current DSP48E1 is configured in the MAC extend opmode 7'b1001000 at %.3f ns.", $time);
end
end
end
/*
// old
// ask jmt
//CR 219047 (4)
always @(qcarryinsel_o_mux) begin
if((qcarryinsel_o_mux == 3'b110) && (MULTCARRYINREG != MREG)) begin
$display("Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E1 instance %m be set to the same value when using CARRYINSEL = 110 for multiply rounding.");
end
end
*/
generate
case (OPMODEREG)
0 : always @(opmode_in) qopmode_o_mux <= opmode_in;
1 : always @(qopmode_o_reg1) qopmode_o_mux <= qopmode_o_reg1;
endcase
endgenerate
//*** ALUMODE with 1 level of register
always @(posedge clk_in) begin
if (rstalumode_in)
qalumode_o_reg1 <= 4'b0;
else if (cealumode_in)
qalumode_o_reg1 <= alumode_in;
end
generate
case (ALUMODEREG)
0 : always @(alumode_in) qalumode_o_mux <= alumode_in;
1 : always @(qalumode_o_reg1) qalumode_o_mux <= qalumode_o_reg1;
endcase
endgenerate
//------------------------------------------------------------------
//*** DRC for OPMODE
//------------------------------------------------------------------
task deassign_xyz_mux;
begin
opmode_valid_flag = 1;
invalid_opmode = 1; // reset invalid opmode
end
endtask // deassign_xyz_mux
task display_invalid_opmode;
begin
if (invalid_opmode) begin
opmode_valid_flag = 0;
invalid_opmode = 0;
$display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0);
end
end
endtask // display_invalid_opmode
always @(ping_opmode_drc_check or qalumode_o_mux or qopmode_o_mux or qcarryinsel_o_mux ) begin
if ($time > 100000) begin // no check at first 100ns
case (qalumode_o_mux[3:2])
2'b00 :
//-- ARITHMETIC MODES DRC
case ({qopmode_o_mux, qcarryinsel_o_mux})
10'b0000000000 : deassign_xyz_mux;
10'b0000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0000011000 : deassign_xyz_mux;
10'b0000011010 : deassign_xyz_mux;
// CR 573535 10'b0000011100 : deassign_xyz_mux;
10'b0000011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0000101000 : deassign_xyz_mux;
10'b0001000000 : deassign_xyz_mux;
10'b0001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001011000 : deassign_xyz_mux;
10'b0001011010 : deassign_xyz_mux;
// CR 573535 10'b0001011100 : deassign_xyz_mux;
10'b0001011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001100000 : deassign_xyz_mux;
10'b0001100010 : deassign_xyz_mux;
// CR 573535 10'b0001100100 : deassign_xyz_mux;
10'b0001100100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0001111000 : deassign_xyz_mux;
10'b0001111010 : deassign_xyz_mux;
// CR 573535 10'b0001111100 : deassign_xyz_mux;
10'b0001111100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0010000000 : deassign_xyz_mux;
10'b0010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0010011000 : deassign_xyz_mux;
10'b0010011001 : deassign_xyz_mux;
10'b0010011011 : deassign_xyz_mux;
10'b0010101000 : deassign_xyz_mux;
10'b0010101001 : deassign_xyz_mux;
10'b0010101011 : deassign_xyz_mux;
10'b0010101110 : deassign_xyz_mux;
10'b0011000000 : deassign_xyz_mux;
10'b0011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011011000 : deassign_xyz_mux;
10'b0011011001 : deassign_xyz_mux;
10'b0011011011 : deassign_xyz_mux;
10'b0011100000 : deassign_xyz_mux;
10'b0011100001 : deassign_xyz_mux;
10'b0011100011 : deassign_xyz_mux;
10'b0011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0011111000 : deassign_xyz_mux;
10'b0011111001 : deassign_xyz_mux;
10'b0011111011 : deassign_xyz_mux;
10'b0100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110000000 : deassign_xyz_mux;
10'b0110000010 : deassign_xyz_mux;
// CR 573535 10'b0110000100 : deassign_xyz_mux;
10'b0110000100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110011000 : deassign_xyz_mux;
10'b0110011010 : deassign_xyz_mux;
// CR 573535 10'b0110011100 : deassign_xyz_mux;
10'b0110011100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0110101000 : deassign_xyz_mux;
10'b0110101110 : deassign_xyz_mux;
10'b0111000000 : deassign_xyz_mux;
10'b0111000010 : deassign_xyz_mux;
// CR 573535 10'b0111000100 : deassign_xyz_mux;
10'b0111000100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0111011000 : deassign_xyz_mux;
10'b0111100000 : deassign_xyz_mux;
10'b0111100010 : deassign_xyz_mux;
10'b0111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b0111111000 : deassign_xyz_mux;
10'b1001000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1010000000 : deassign_xyz_mux;
10'b1010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1010011000 : deassign_xyz_mux;
10'b1010011001 : deassign_xyz_mux;
10'b1010011011 : deassign_xyz_mux;
10'b1010101000 : deassign_xyz_mux;
10'b1010101001 : deassign_xyz_mux;
10'b1010101011 : deassign_xyz_mux;
10'b1010101110 : deassign_xyz_mux;
10'b1011000000 : deassign_xyz_mux;
10'b1011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011011000 : deassign_xyz_mux;
10'b1011011001 : deassign_xyz_mux;
10'b1011011011 : deassign_xyz_mux;
10'b1011100000 : deassign_xyz_mux;
10'b1011100001 : deassign_xyz_mux;
10'b1011100011 : deassign_xyz_mux;
10'b1011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1011111000 : deassign_xyz_mux;
10'b1011111001 : deassign_xyz_mux;
10'b1011111011 : deassign_xyz_mux;
10'b1100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
10'b1101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
default : begin
if (invalid_opmode) begin
opmode_valid_flag = 0;
invalid_opmode = 0;
// CR 444150
if( ({qopmode_o_mux, qcarryinsel_o_mux} == 10'b0000000010) && ((OPMODEREG==1) && (CARRYINSELREG ==0)) )
$display("DRC warning : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, in order to ensure that the simulation model will match the hardware behavior in all use cases.", CARRYINSELREG);
$display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE is invalid at %.3f ns. This warning may be due to a mismatch in the OPMODEREG and CARRYINSELREG attribute settings. It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value. ", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0);
end
end
endcase // case(OPMODE)
2'b01, 2'b11 :
//-- LOGIC MODES DRC
case (qopmode_o_mux)
7'b0000000 : deassign_xyz_mux;
7'b0000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0000011 : deassign_xyz_mux;
7'b0010000 : deassign_xyz_mux;
7'b0010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0010011 : deassign_xyz_mux;
7'b0100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0110000 : deassign_xyz_mux;
7'b0110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0110011 : deassign_xyz_mux;
7'b1010000 : deassign_xyz_mux;
7'b1010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1010011 : deassign_xyz_mux;
7'b1100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0001000 : deassign_xyz_mux;
7'b0001010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0001011 : deassign_xyz_mux;
7'b0011000 : deassign_xyz_mux;
7'b0011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0011011 : deassign_xyz_mux;
7'b0101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0111000 : deassign_xyz_mux;
7'b0111010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b0111011 : deassign_xyz_mux;
7'b1011000 : deassign_xyz_mux;
7'b1011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1011011 : deassign_xyz_mux;
7'b1101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
7'b1101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux;
default : begin
if (invalid_opmode) begin
opmode_valid_flag = 0;
invalid_opmode = 0;
$display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is invalid for LOGIC MODES at %.3f ns.", qopmode_o_mux, $time/1000.0);
end
end
endcase // case(OPMODE)
endcase // case(qalumode_o_mux)
end // if ($time > 100000)
end // always @ (qopmode_o_mux)
//--####################################################################
//--##### ALU #####
//--####################################################################
wire mult_cout = ~qp_o_mux[42];
reg [MSB_ALU_FULL:0] co;
reg [MSB_ALU_FULL:0] s;
wire [MSB_ALU_FULL:0] comux,smux;
wire [MSB_CARRYOUT:0] carryout_o_hw;
wire [MSB_CARRYOUT:0] carryout_o;
wire tmp_carrycascout_in;
always @ (qx_o_mux or qy_o_mux or qz_o_mux or qalumode_o_mux[0]) begin
if (qalumode_o_mux[0]) begin
co = ((qx_o_mux & qy_o_mux)|((~qz_o_mux) & qy_o_mux)|(qx_o_mux & (~qz_o_mux)));
s = (~qz_o_mux) ^ qx_o_mux ^ qy_o_mux;
end
else begin
co = ((qx_o_mux & qy_o_mux)|(qz_o_mux & qy_o_mux)|(qx_o_mux & qz_o_mux));
s = qz_o_mux ^ qx_o_mux ^ qy_o_mux;
end
end
assign comux = qalumode_o_mux[2] ? 0 : co;
assign smux = qalumode_o_mux[3] ? co : s;
// FINAL ADDER
wire [12:0] s0 = {comux[10:0],qcarryin_o_mux}+smux[11:0];
wire cout0 = (comux[11] + s0[12]);
assign carryout_o_hw[0] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout0 : cout0;
wire C1 = (USE_SIMD == "FOUR12") ? 1'b0 : s0[12];
wire co11_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[11];
wire [12:0] s1 = {comux[22:12],co11_lsb}+smux[23:12]+C1;
wire cout1 = (comux[23] + s1[12]);
assign carryout_o_hw[1] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout1 : cout1;
wire C2 = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? 1'b0 : s1[12];
wire co23_lsb = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ?
1'b0 : comux[23];
wire [12:0] s2 = {comux[34:24],co23_lsb}+smux[35:24]+C2;
wire cout2 = (comux[35] + s2[12]);
assign carryout_o_hw[2] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout2 : cout2;
wire C3 = (USE_SIMD == "FOUR12") ? 1'b0 : s2[12];
wire co35_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[35];
wire [13:0] s3 = {comux[47:36],co35_lsb}+smux[47:36]+C3;
wire cout3 = s3[12];
assign carryout_o_hw[3] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout3 : cout3;
wire cout4 = s3[13];
// assign carryout_o_hw[4] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout4 : cout4;
assign alu_o = qalumode_o_mux[1] ? ~{s3[11:0],s2[11:0],s1[11:0],s0[11:0]} :
{s3[11:0],s2[11:0],s1[11:0],s0[11:0]};
// COMPUTE CARRYCASCOUT
assign carrycascout_o = cout3;
// COMPUTE MULTSIGNOUT
// 08-06-08 assign multsignout_o_opmode = (qopmode_o_mux[3:0] === 4'b100) ? multsignin_in : ~qp_o_mux[42];
// IR 478378
assign multsignout_o_opmode = (qopmode_o_mux[6:4] === 3'b100) ? multsignin_in : qmult_o_mux[42];
// CR 523600 -- "X" carryout for multiply and logic operations
assign carryout_o[3] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : carryout_o_hw[3];
assign carryout_o[2] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[2] : 1'bx;
assign carryout_o[1] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_hw[1] : 1'bx;
assign carryout_o[0] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[0] : 1'bx;
//--########################### END ALU ################################
//*** CarryIn Mux and Register
//------- input 0
always @(posedge clk_in) begin
if (rstallcarryin_in)
qcarryin_o_reg0 <= 1'b0;
else if (cecarryin_in)
qcarryin_o_reg0 <= carryin_in;
end
generate
case (CARRYINREG)
0 : always @(carryin_in) qcarryin_o_mux0 <= carryin_in;
1 : always @(qcarryin_o_reg0) qcarryin_o_mux0 <= qcarryin_o_reg0;
endcase
endgenerate
//------- input 7
always @(posedge clk_in) begin
if (rstallcarryin_in)
qcarryin_o_reg7 <= 1'b0;
// old else if (cemultcarryin_in)
// new
else if (cem_in)
// IR 478377
qcarryin_o_reg7 <= ad_mult[24] ~^ b_mult[17]; // xnor
end
// always @(qa_o_mux[24] or qb_o_mux[17] or qcarryin_o_reg7) begin
always @(ad_mult[24] or b_mult[17] or qcarryin_o_reg7) begin
// old case (MULTCARRYINREG)
// new
case (MREG)
// IR 478377
0 : qcarryin_o_mux7 <= ad_mult[24] ~^ b_mult[17];
1 : qcarryin_o_mux7 <= qcarryin_o_reg7;
default : begin
$display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG);
$finish;
end
endcase
end
reg qcarryin_o_mux_tmp;
always @(qcarryin_o_mux0 or pcin_in[47] or carrycascin_in or carrycascout_o_mux or qp_o_mux[47] or qcarryin_o_mux7 or qcarryinsel_o_mux) begin
case (qcarryinsel_o_mux)
3'b000 : qcarryin_o_mux_tmp <= qcarryin_o_mux0;
3'b001 : qcarryin_o_mux_tmp <= ~pcin_in[47];
3'b010 : qcarryin_o_mux_tmp <= carrycascin_in;
3'b011 : qcarryin_o_mux_tmp <= pcin_in[47];
3'b100 : qcarryin_o_mux_tmp <= carrycascout_o_mux;
3'b101 : qcarryin_o_mux_tmp <= ~qp_o_mux[47];
3'b110 : qcarryin_o_mux_tmp <= qcarryin_o_mux7;
3'b111 : qcarryin_o_mux_tmp <= qp_o_mux[47];
default : begin
end
endcase
end
// disable carryin when performing logic operation
always @(qcarryin_o_mux_tmp or qalumode_o_mux[3:2]) begin
qcarryin_o_mux <= (qalumode_o_mux[3] || qalumode_o_mux[2]) ? 1'b0 : qcarryin_o_mux_tmp;
end
//--####################################################################
//--##### AUTORESET_PATDET #####
//--####################################################################
assign the_auto_reset_patdet = ((AUTORESET_PATDET == "RESET_MATCH") && pdet_o_reg1)
||
((AUTORESET_PATDET == "RESET_NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1));
//--####################################################################
//--##### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT and PCOUT ######
//--####################################################################
//*** register with 1 level of register
always @(posedge clk_in) begin
if(rstp_in || the_auto_reset_patdet)
begin
carryout_o_reg <= 4'b0;
carrycascout_o_reg <= 1'b0;
qmultsignout_o_reg <= 1'b0;
qp_o_reg1 <= 48'b0;
end
else if (cep_in) begin
carryout_o_reg <= carryout_o;
carrycascout_o_reg <= carrycascout_o;
qmultsignout_o_reg <= multsignout_o_opmode;
qp_o_reg1 <= alu_o;
end
end
generate
case (PREG)
0: begin
always @(carryout_o)
carryout_o_mux <= carryout_o;
always @(carrycascout_o)
carrycascout_o_mux <= carrycascout_o;
always @(multsignout_o_opmode)
multsignout_o_mux <= multsignout_o_opmode;
always @(alu_o)
qp_o_mux <= #1 alu_o;
end
1: begin
always @(carryout_o_reg)
carryout_o_mux <= carryout_o_reg;
always @(carrycascout_o_reg)
carrycascout_o_mux <= carrycascout_o_reg;
always @(qmultsignout_o_reg)
multsignout_o_mux <= qmultsignout_o_reg;
always @(qp_o_reg1)
qp_o_mux <= qp_o_reg1;
end
endcase
endgenerate
//CR 219047 (2)
// ask jmt whether i should comment this out
/*
always @(qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)] or qopmode_o_mux[3:0]) begin
if(qopmode_o_mux[3:0] == 4'b0101)
multsignout_o_opmode = qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)];
else
multsignout_o_opmode = 1'bx;
end
*/
// assign carryout_x_o[4] = carryout_o_mux[4];
// CR 510304 output X during multiply operation
assign carryout_x_o[3] = carryout_o_mux[3];
assign carryout_x_o[2] = (USE_SIMD == "FOUR12") ? carryout_o_mux[2] : 1'bx;
assign carryout_x_o[1] = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_mux[1] : 1'bx;
assign carryout_x_o[0] = (USE_SIMD == "FOUR12") ? carryout_o_mux[0] : 1'bx;
//--####################################################################
//--##### Pattern Detector #####
//--####################################################################
// new
// selet pattern
assign the_pattern = (SEL_PATTERN == "PATTERN") ? PATTERN : qc_o_mux;
// selet mask
always @(qc_o_mux) begin
case(SEL_MASK)
"MASK" : the_mask <= MASK;
"C" : the_mask <= qc_o_mux;
"ROUNDING_MODE1" : the_mask <= ~qc_o_mux << 1;
"ROUNDING_MODE2" : the_mask <= ~qc_o_mux << 2;
default : ;
endcase
end
//-- now do the pattern detection
assign pdet_o = &(~(the_pattern ^ alu_o) | the_mask);
assign pdetb_o = &((the_pattern ^ alu_o) | the_mask);
assign pdet_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdet_o_reg1 : pdet_o;
assign pdetb_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdetb_o_reg1 : pdetb_o;
//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW
always @(posedge clk_in) begin
if((rstp_in) || the_auto_reset_patdet)
begin
pdet_o_reg1 <= 1'b0;
pdet_o_reg2 <= 1'b0;
pdetb_o_reg1 <= 1'b0;
pdetb_o_reg2 <= 1'b0;
end
else if(cep_in)
begin
//-- the previous values are used in Underflow/Overflow
pdet_o_reg2 <= pdet_o_reg1;
pdet_o_reg1 <= pdet_o;
pdetb_o_reg2 <= pdetb_o_reg1;
pdetb_o_reg1 <= pdetb_o;
end
end
//--####################################################################
//--##### Underflow / Overflow #####
//--####################################################################
generate if ((USE_PATTERN_DETECT == "PATDET") || (PREG == 1))
begin
assign overflow_o = pdet_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1;
assign underflow_o = pdetb_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1;
end
else
begin
assign overflow_o = 1'bx;
assign underflow_o = 1'bx;
end
endgenerate
`ifndef XIL_TIMING
specify
(CLK *> ACOUT) = (100, 100);
(CLK *> BCOUT) = (100, 100);
(CLK *> CARRYCASCOUT) = (100, 100);
(CLK *> CARRYOUT) = (100, 100);
(CLK *> MULTSIGNOUT) = (100, 100);
(CLK *> OVERFLOW) = (100, 100);
(CLK *> P) = (100, 100);
(CLK *> PATTERNBDETECT) = (100, 100);
(CLK *> PATTERNDETECT) = (100, 100);
(CLK *> PCOUT) = (100, 100);
(CLK *> UNDERFLOW) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier) begin
qp_o_mux <= 48'bx;
qb_o_mux <= 18'bx;
end
not (nrsta, rsta_in);
not (nrstb, rstb_in);
not (nrstc, rstc_in);
not (nrstp, rstp_in);
not (nrstallcarryin, rstallcarryin_in);
not (nrstctrl, rstctrl_in);
not (nrstinmode, rstinmode_in);
not (nrstd, rstd_in);
assign cea12_enable = (((AREG == 1) && cea1_in) || ((AREG == 2) && (cea1_in || cea2_in))) ? 1'b1 : 1'b0;
assign ceb12_enable = (((BREG == 1) && ceb1_in) || ((BREG == 2) && (ceb1_in || ceb2_in))) ? 1'b1 : 1'b0;
assign a_enable = (A_INPUT == "DIRECT") && (cea12_enable) && nrsta ? 1'b1 : 1'b0;
assign b_enable = (B_INPUT == "DIRECT") && (ceb12_enable) && nrstb ? 1'b1 : 1'b0;
assign acin_enable = (A_INPUT == "CASCADE") && (cea12_enable) && nrsta ? 1'b1 : 1'b0;
assign bcin_enable = (B_INPUT == "CASCADE") && (ceb12_enable) && nrstb ? 1'b1 : 1'b0;
and (carryin_enable, cea12_enable, ceb12_enable , cecarryin_in, nrsta, nrstb, nrstallcarryin);
and (CarryinSel_enable, cea12_enable, ceb12_enable, nrsta, nrstb, nrstctrl);
and (Opmode_enable, cectrl_in, nrstctrl);
and (pcin_enable, cep_in, nrstp);
and (c_enable, cec_in, nrstc);
and (Inmode_enable, ceinmode_in, nrstinmode);
and (d_enable, ced_in, nrstd);
specify
(A *> ACOUT) = (0:0:0, 0:0:0);
(ACIN *> ACOUT) = (0:0:0, 0:0:0);
(CLK *> ACOUT) = (100:100:100, 100:100:100);
(B *> BCOUT) = (0:0:0, 0:0:0);
(BCIN *> BCOUT) = (0:0:0, 0:0:0);
(CLK *> BCOUT) = (100:100:100, 100:100:100);
(A *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(ACIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(ALUMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(B *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(BCIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(C *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(D *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(CARRYIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(CLK *> CARRYCASCOUT) = (100:100:100, 100:100:100);
(INMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(OPMODE *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(PCIN *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(A *> CARRYOUT) = (0:0:0, 0:0:0);
(ACIN *> CARRYOUT) = (0:0:0, 0:0:0);
(ALUMODE *> CARRYOUT) = (0:0:0, 0:0:0);
(B *> CARRYOUT) = (0:0:0, 0:0:0);
(BCIN *> CARRYOUT) = (0:0:0, 0:0:0);
(C *> CARRYOUT) = (0:0:0, 0:0:0);
(D *> CARRYOUT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> CARRYOUT) = (0:0:0, 0:0:0);
(CARRYIN *> CARRYOUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> CARRYOUT) = (0:0:0, 0:0:0);
(CLK *> CARRYOUT) = (100:100:100, 100:100:100);
(INMODE *> CARRYOUT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> CARRYOUT) = (0:0:0, 0:0:0);
(OPMODE *> CARRYOUT) = (0:0:0, 0:0:0);
(PCIN *> CARRYOUT) = (0:0:0, 0:0:0);
(A *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(ACIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(ALUMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(B *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(BCIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(C *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(D *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(CARRYIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(CLK *> MULTSIGNOUT) = (100:100:100, 100:100:100);
(INMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(OPMODE *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(PCIN *> MULTSIGNOUT) = (0:0:0, 0:0:0);
(A *> OVERFLOW) = (0:0:0, 0:0:0);
(ACIN *> OVERFLOW) = (0:0:0, 0:0:0);
(ALUMODE *> OVERFLOW) = (0:0:0, 0:0:0);
(B *> OVERFLOW) = (0:0:0, 0:0:0);
(BCIN *> OVERFLOW) = (0:0:0, 0:0:0);
(C *> OVERFLOW) = (0:0:0, 0:0:0);
(D *> OVERFLOW) = (0:0:0, 0:0:0);
(CARRYCASCIN *> OVERFLOW) = (0:0:0, 0:0:0);
(CARRYIN *> OVERFLOW) = (0:0:0, 0:0:0);
(CARRYINSEL *> OVERFLOW) = (0:0:0, 0:0:0);
(CLK *> OVERFLOW) = (100:100:100, 100:100:100);
(INMODE *> OVERFLOW) = (0:0:0, 0:0:0);
(MULTSIGNIN *> OVERFLOW) = (0:0:0, 0:0:0);
(OPMODE *> OVERFLOW) = (0:0:0, 0:0:0);
(PCIN *> OVERFLOW) = (0:0:0, 0:0:0);
(A *> P) = (0:0:0, 0:0:0);
(ACIN *> P) = (0:0:0, 0:0:0);
(ALUMODE *> P) = (0:0:0, 0:0:0);
(B *> P) = (0:0:0, 0:0:0);
(BCIN *> P) = (0:0:0, 0:0:0);
(C *> P) = (0:0:0, 0:0:0);
(D *> P) = (0:0:0, 0:0:0);
(CARRYCASCIN *> P) = (0:0:0, 0:0:0);
(CARRYIN *> P) = (0:0:0, 0:0:0);
(CARRYINSEL *> P) = (0:0:0, 0:0:0);
(CLK *> P) = (100:100:100, 100:100:100);
(INMODE *> P) = (0:0:0, 0:0:0);
(MULTSIGNIN *> P) = (0:0:0, 0:0:0);
(OPMODE *> P) = (0:0:0, 0:0:0);
(PCIN *> P) = (0:0:0, 0:0:0);
(A *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(ACIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(ALUMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(B *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(BCIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(C *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(D *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(CARRYIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(CARRYINSEL *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(CLK *> PATTERNBDETECT) = (100:100:100, 100:100:100);
(INMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(OPMODE *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(PCIN *> PATTERNBDETECT) = (0:0:0, 0:0:0);
(A *> PATTERNDETECT) = (0:0:0, 0:0:0);
(ACIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(ALUMODE *> PATTERNDETECT) = (0:0:0, 0:0:0);
(B *> PATTERNDETECT) = (0:0:0, 0:0:0);
(BCIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(C *> PATTERNDETECT) = (0:0:0, 0:0:0);
(D *> PATTERNDETECT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(CARRYIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(CARRYINSEL *> PATTERNDETECT) = (0:0:0, 0:0:0);
(CLK *> PATTERNDETECT) = (100:100:100, 100:100:100);
(INMODE *> PATTERNDETECT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(OPMODE *> PATTERNDETECT) = (0:0:0, 0:0:0);
(PCIN *> PATTERNDETECT) = (0:0:0, 0:0:0);
(A *> PCOUT) = (0:0:0, 0:0:0);
(ACIN *> PCOUT) = (0:0:0, 0:0:0);
(ALUMODE *> PCOUT) = (0:0:0, 0:0:0);
(B *> PCOUT) = (0:0:0, 0:0:0);
(BCIN *> PCOUT) = (0:0:0, 0:0:0);
(C *> PCOUT) = (0:0:0, 0:0:0);
(D *> PCOUT) = (0:0:0, 0:0:0);
(CARRYIN *> PCOUT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> PCOUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> PCOUT) = (0:0:0, 0:0:0);
(CLK *> PCOUT) = (100:100:100, 100:100:100);
(INMODE *> PCOUT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> PCOUT) = (0:0:0, 0:0:0);
(OPMODE *> PCOUT) = (0:0:0, 0:0:0);
(PCIN *> PCOUT) = (0:0:0, 0:0:0);
(A *> UNDERFLOW) = (0:0:0, 0:0:0);
(ACIN *> UNDERFLOW) = (0:0:0, 0:0:0);
(ALUMODE *> UNDERFLOW) = (0:0:0, 0:0:0);
(B *> UNDERFLOW) = (0:0:0, 0:0:0);
(BCIN *> UNDERFLOW) = (0:0:0, 0:0:0);
(C *> UNDERFLOW) = (0:0:0, 0:0:0);
(D *> UNDERFLOW) = (0:0:0, 0:0:0);
(CARRYCASCIN *> UNDERFLOW) = (0:0:0, 0:0:0);
(CARRYIN *> UNDERFLOW) = (0:0:0, 0:0:0);
(CARRYINSEL *> UNDERFLOW) = (0:0:0, 0:0:0);
(CLK *> UNDERFLOW) = (100:100:100, 100:100:100);
(INMODE *> UNDERFLOW) = (0:0:0, 0:0:0);
(MULTSIGNIN *> UNDERFLOW) = (0:0:0, 0:0:0);
(OPMODE *> UNDERFLOW) = (0:0:0, 0:0:0);
(PCIN *> UNDERFLOW) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge CEAD &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cead_dly);
$setuphold (posedge CLK, negedge CEAD &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cead_dly);
$setuphold (negedge CLK, posedge CEAD &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cead_dly);
$setuphold (negedge CLK, negedge CEAD &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cead_dly);
$setuphold (posedge CLK, posedge CED &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ced_dly);
$setuphold (posedge CLK, negedge CED &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ced_dly);
$setuphold (negedge CLK, posedge CED &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ced_dly);
$setuphold (negedge CLK, negedge CED &&& (rstd_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ced_dly);
$setuphold (posedge CLK, posedge CEINMODE &&& (rstinmode_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceinmode_dly);
$setuphold (posedge CLK, negedge CEINMODE &&& (rstinmode_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceinmode_dly);
$setuphold (negedge CLK, posedge CEINMODE &&& (rstinmode_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceinmode_dly);
$setuphold (negedge CLK, negedge CEINMODE &&& (rstinmode_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceinmode_dly);
$setuphold (posedge CLK, posedge D &&& (d_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, d_dly);
$setuphold (posedge CLK, negedge D &&& (d_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, d_dly);
$setuphold (negedge CLK, posedge D &&& (d_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, d_dly);
$setuphold (negedge CLK, negedge D &&& (d_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, d_dly);
$setuphold (posedge CLK, posedge INMODE &&& (Inmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, inmode_dly);
$setuphold (posedge CLK, negedge INMODE &&& (Inmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, inmode_dly);
$setuphold (negedge CLK, posedge INMODE &&& (Inmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, inmode_dly);
$setuphold (negedge CLK, negedge INMODE &&& (Inmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, inmode_dly);
$setuphold (posedge CLK, posedge RSTD &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstd_dly);
$setuphold (posedge CLK, negedge RSTD &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstd_dly);
$setuphold (negedge CLK, posedge RSTD &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstd_dly);
$setuphold (negedge CLK, negedge RSTD &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstd_dly);
$setuphold (posedge CLK, posedge RSTINMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstinmode_dly);
$setuphold (posedge CLK, negedge RSTINMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstinmode_dly);
$setuphold (negedge CLK, posedge RSTINMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstinmode_dly);
$setuphold (negedge CLK, negedge RSTINMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstinmode_dly);
$setuphold (posedge CLK, posedge OPMODE &&& (Opmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
$setuphold (posedge CLK, negedge OPMODE &&& (Opmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
$setuphold (negedge CLK, posedge OPMODE &&& (Opmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
$setuphold (negedge CLK, negedge OPMODE &&& (Opmode_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
// $setuphold (posedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
// $setuphold (posedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, opmode_dly);
$setuphold (posedge CLK, posedge PCIN &&& (pcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, pcin_dly);
$setuphold (posedge CLK, negedge PCIN &&& (pcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, pcin_dly);
$setuphold (negedge CLK, posedge PCIN &&& (pcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, pcin_dly);
$setuphold (negedge CLK, negedge PCIN &&& (pcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, pcin_dly);
$setuphold (posedge CLK, posedge A &&& (a_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, a_dly);
$setuphold (posedge CLK, negedge A &&& (a_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, a_dly);
$setuphold (negedge CLK, posedge A &&& (a_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, a_dly);
$setuphold (negedge CLK, negedge A &&& (a_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, a_dly);
$setuphold (posedge CLK, posedge ACIN &&& (acin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, acin_dly);
$setuphold (posedge CLK, negedge ACIN &&& (acin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, acin_dly);
$setuphold (negedge CLK, posedge ACIN &&& (acin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, acin_dly);
$setuphold (negedge CLK, negedge ACIN &&& (acin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, acin_dly);
$setuphold (posedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, alumode_dly);
$setuphold (posedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, alumode_dly);
$setuphold (negedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, alumode_dly);
$setuphold (negedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, alumode_dly);
$setuphold (posedge CLK, posedge B &&& (b_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, b_dly );
$setuphold (posedge CLK, negedge B &&& (b_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, b_dly);
$setuphold (negedge CLK, posedge B &&& (b_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, b_dly );
$setuphold (negedge CLK, negedge B &&& (b_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, b_dly);
$setuphold (posedge CLK, posedge BCIN &&& (bcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, bcin_dly);
$setuphold (posedge CLK, negedge BCIN &&& (bcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, bcin_dly);
$setuphold (negedge CLK, posedge BCIN &&& (bcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, bcin_dly);
$setuphold (negedge CLK, negedge BCIN &&& (bcin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, bcin_dly);
$setuphold (posedge CLK, posedge C &&& (c_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, c_dly);
$setuphold (posedge CLK, negedge C &&& (c_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, c_dly);
$setuphold (negedge CLK, posedge C &&& (c_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, c_dly);
$setuphold (negedge CLK, negedge C &&& (c_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, c_dly);
$setuphold (posedge CLK, posedge CARRYCASCIN, 0:0:0, 0:0:0, notifier, , , clk_dly, carrycascin_dly);
$setuphold (posedge CLK, negedge CARRYCASCIN, 0:0:0, 0:0:0, notifier, , , clk_dly, carrycascin_dly);
$setuphold (negedge CLK, posedge CARRYCASCIN, 0:0:0, 0:0:0, notifier, , , clk_dly, carrycascin_dly);
$setuphold (negedge CLK, negedge CARRYCASCIN, 0:0:0, 0:0:0, notifier, , , clk_dly, carrycascin_dly);
$setuphold (posedge CLK, posedge CARRYIN &&& (carryin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryin_dly);
$setuphold (posedge CLK, negedge CARRYIN &&& (carryin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryin_dly);
$setuphold (negedge CLK, posedge CARRYIN &&& (carryin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryin_dly);
$setuphold (negedge CLK, negedge CARRYIN &&& (carryin_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryin_dly);
$setuphold (posedge CLK, posedge CARRYINSEL &&& (CarryinSel_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryinsel_dly);
$setuphold (posedge CLK, negedge CARRYINSEL &&& (CarryinSel_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryinsel_dly);
$setuphold (negedge CLK, posedge CARRYINSEL &&& (CarryinSel_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryinsel_dly);
$setuphold (negedge CLK, negedge CARRYINSEL &&& (CarryinSel_enable!=0), 0:0:0, 0:0:0, notifier, , , clk_dly, carryinsel_dly);
$setuphold (posedge CLK, posedge CEA1 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea1_dly);
$setuphold (posedge CLK, negedge CEA1 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea1_dly);
$setuphold (negedge CLK, posedge CEA1 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea1_dly);
$setuphold (negedge CLK, negedge CEA1 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea1_dly);
$setuphold (posedge CLK, posedge CEA2 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea2_dly);
$setuphold (posedge CLK, negedge CEA2 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea2_dly);
$setuphold (negedge CLK, posedge CEA2 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea2_dly);
$setuphold (negedge CLK, negedge CEA2 &&& (rsta_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cea2_dly);
$setuphold (posedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, cealumode_dly);
$setuphold (posedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, cealumode_dly);
$setuphold (negedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, cealumode_dly);
$setuphold (negedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier, , , clk_dly, cealumode_dly);
$setuphold (posedge CLK, posedge CEB1 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb1_dly);
$setuphold (posedge CLK, negedge CEB1 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb1_dly);
$setuphold (negedge CLK, posedge CEB1 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb1_dly);
$setuphold (negedge CLK, negedge CEB1 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb1_dly);
$setuphold (posedge CLK, posedge CEB2 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb2_dly);
$setuphold (posedge CLK, negedge CEB2 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb2_dly);
$setuphold (negedge CLK, posedge CEB2 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb2_dly);
$setuphold (negedge CLK, negedge CEB2 &&& (rstb_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, ceb2_dly);
$setuphold (posedge CLK, posedge CEC &&& (rstc_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cec_dly);
$setuphold (posedge CLK, negedge CEC &&& (rstc_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cec_dly);
$setuphold (negedge CLK, posedge CEC &&& (rstc_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cec_dly);
$setuphold (negedge CLK, negedge CEC &&& (rstc_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cec_dly);
$setuphold (posedge CLK, posedge CECARRYIN &&& (rstallcarryin_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cecarryin_dly);
$setuphold (posedge CLK, negedge CECARRYIN &&& (rstallcarryin_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cecarryin_dly);
$setuphold (negedge CLK, posedge CECARRYIN &&& (rstallcarryin_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cecarryin_dly);
$setuphold (negedge CLK, negedge CECARRYIN &&& (rstallcarryin_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cecarryin_dly);
$setuphold (posedge CLK, posedge CECTRL &&& (rstctrl_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cectrl_dly);
$setuphold (posedge CLK, negedge CECTRL &&& (rstctrl_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cectrl_dly);
$setuphold (negedge CLK, posedge CECTRL &&& (rstctrl_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cectrl_dly);
$setuphold (negedge CLK, negedge CECTRL &&& (rstctrl_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cectrl_dly);
$setuphold (posedge CLK, posedge CEM &&& (rstm_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cem_dly);
$setuphold (posedge CLK, negedge CEM &&& (rstm_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cem_dly);
$setuphold (negedge CLK, posedge CEM &&& (rstm_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cem_dly);
$setuphold (negedge CLK, negedge CEM &&& (rstm_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cem_dly);
$setuphold (posedge CLK, posedge CEP &&& (rstp_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cep_dly);
$setuphold (posedge CLK, negedge CEP &&& (rstp_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cep_dly);
$setuphold (negedge CLK, posedge CEP &&& (rstp_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cep_dly);
$setuphold (negedge CLK, negedge CEP &&& (rstp_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, cep_dly);
$setuphold (posedge CLK, posedge MULTSIGNIN, 0:0:0, 0:0:0, notifier, , , clk_dly, multsignin_dly);
$setuphold (posedge CLK, negedge MULTSIGNIN, 0:0:0, 0:0:0, notifier, , , clk_dly, multsignin_dly);
$setuphold (negedge CLK, posedge MULTSIGNIN, 0:0:0, 0:0:0, notifier, , , clk_dly, multsignin_dly);
$setuphold (negedge CLK, negedge MULTSIGNIN, 0:0:0, 0:0:0, notifier, , , clk_dly, multsignin_dly);
$setuphold (posedge CLK, posedge RSTA &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rsta_dly);
$setuphold (posedge CLK, negedge RSTA &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rsta_dly);
$setuphold (negedge CLK, posedge RSTA &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rsta_dly);
$setuphold (negedge CLK, negedge RSTA &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rsta_dly);
$setuphold (posedge CLK, posedge RSTALLCARRYIN &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstallcarryin_dly);
$setuphold (posedge CLK, negedge RSTALLCARRYIN &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstallcarryin_dly);
$setuphold (negedge CLK, posedge RSTALLCARRYIN &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstallcarryin_dly);
$setuphold (negedge CLK, negedge RSTALLCARRYIN &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstallcarryin_dly);
$setuphold (posedge CLK, posedge RSTALUMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstalumode_dly);
$setuphold (posedge CLK, negedge RSTALUMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstalumode_dly);
$setuphold (negedge CLK, posedge RSTALUMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstalumode_dly);
$setuphold (negedge CLK, negedge RSTALUMODE &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstalumode_dly);
$setuphold (posedge CLK, posedge RSTB &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstb_dly);
$setuphold (posedge CLK, negedge RSTB &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstb_dly);
$setuphold (negedge CLK, posedge RSTB &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstb_dly);
$setuphold (negedge CLK, negedge RSTB &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstb_dly);
$setuphold (posedge CLK, posedge RSTC &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstc_dly);
$setuphold (posedge CLK, negedge RSTC &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstc_dly);
$setuphold (negedge CLK, posedge RSTC &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstc_dly);
$setuphold (negedge CLK, negedge RSTC &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstc_dly);
$setuphold (posedge CLK, posedge RSTCTRL &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstctrl_dly);
$setuphold (posedge CLK, negedge RSTCTRL &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstctrl_dly);
$setuphold (negedge CLK, posedge RSTCTRL &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstctrl_dly);
$setuphold (negedge CLK, negedge RSTCTRL &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstctrl_dly);
$setuphold (posedge CLK, posedge RSTM &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstm_dly);
$setuphold (posedge CLK, negedge RSTM &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstm_dly);
$setuphold (negedge CLK, posedge RSTM &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstm_dly);
$setuphold (negedge CLK, negedge RSTM &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstm_dly);
$setuphold (posedge CLK, posedge RSTP &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstp_dly);
$setuphold (posedge CLK, negedge RSTP &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstp_dly);
$setuphold (negedge CLK, posedge RSTP &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstp_dly);
$setuphold (negedge CLK, negedge RSTP &&& (gsr_in==0), 0:0:0, 0:0:0, notifier, , , clk_dly, rstp_dly);
$period (posedge CLK, 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // DSP48E1
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP48E2.v 0000664 0000000 0000000 00000200641 12327044266 0022416 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 27X18 Signed Multiplier Followed by Three-Input
// /___/ /\ Adder plus ALU with Pipeline Registers
// \ \ / \ Filename : DSP48E2.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/10/13 - 694456 - DIN_in/D_in connectivity issue
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 02/13/13 - PCIN_47A change from internal feedback to PCIN(47) pin
// 03/06/13 - 701316 - A_B_reg no clk when REG=0
// 04/03/13 - yaml update
// 04/08/13 - 710304 - AREG, BREG, ACASCREG and BCASCREG dynamic registers mis sized.
// 04/22/13 - 714213 - ACOUT, BCOUT wrong logic
// 04/22/13 - 713695 - Zero mult result on USE_SIMD
// 04/22/13 - 713617 - CARRYCASCOUT behaviour
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 04/23/13 - 713706 - change P_PDBK connection
// 05/07/13 - 716896 - AREG, BREG, ACASCREG and BCASCREG localparams mis sized.
// 05/07/13 - 716896 - ALUMODE/OPMODE_INV_REG mis sized
// 05/07/13 - 716896 - INMODE_INV_REG mis sized
// 05/07/13 - x_mac_cascd missing for sensitivity list.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP48E2
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ACASCREG = 1,
parameter integer ADREG = 1,
parameter integer ALUMODEREG = 1,
parameter AMULTSEL = "A",
parameter integer AREG = 1,
parameter AUTORESET_PATDET = "NO_RESET",
parameter AUTORESET_PRIORITY = "RESET",
parameter A_INPUT = "DIRECT",
parameter integer BCASCREG = 1,
parameter BMULTSEL = "B",
parameter integer BREG = 1,
parameter B_INPUT = "DIRECT",
parameter integer CARRYINREG = 1,
parameter integer CARRYINSELREG = 1,
parameter integer CREG = 1,
parameter integer DREG = 1,
parameter integer INMODEREG = 1,
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000,
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [4:0] IS_INMODE_INVERTED = 5'b00000,
parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000,
parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0,
parameter [0:0] IS_RSTA_INVERTED = 1'b0,
parameter [0:0] IS_RSTB_INVERTED = 1'b0,
parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0,
parameter [0:0] IS_RSTC_INVERTED = 1'b0,
parameter [0:0] IS_RSTD_INVERTED = 1'b0,
parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0,
parameter [0:0] IS_RSTM_INVERTED = 1'b0,
parameter [0:0] IS_RSTP_INVERTED = 1'b0,
parameter [47:0] MASK = 48'h3FFFFFFFFFFF,
parameter integer MREG = 1,
parameter integer OPMODEREG = 1,
parameter [47:0] PATTERN = 48'h000000000000,
parameter PREADDINSEL = "A",
parameter integer PREG = 1,
parameter [47:0] RND = 48'h000000000000,
parameter SEL_MASK = "MASK",
parameter SEL_PATTERN = "PATTERN",
parameter USE_MULT = "MULTIPLY",
parameter USE_PATTERN_DETECT = "NO_PATDET",
parameter USE_SIMD = "ONE48",
parameter USE_WIDEXOR = "FALSE",
parameter XORSIMD = "XOR24_48_96"
) (
output [29:0] ACOUT,
output [17:0] BCOUT,
output CARRYCASCOUT,
output [3:0] CARRYOUT,
output MULTSIGNOUT,
output OVERFLOW,
output [47:0] P,
output PATTERNBDETECT,
output PATTERNDETECT,
output [47:0] PCOUT,
output UNDERFLOW,
output [7:0] XOROUT,
input [29:0] A,
input [29:0] ACIN,
input [3:0] ALUMODE,
input [17:0] B,
input [17:0] BCIN,
input [47:0] C,
input CARRYCASCIN,
input CARRYIN,
input [2:0] CARRYINSEL,
input CEA1,
input CEA2,
input CEAD,
input CEALUMODE,
input CEB1,
input CEB2,
input CEC,
input CECARRYIN,
input CECTRL,
input CED,
input CEINMODE,
input CEM,
input CEP,
input CLK,
input [26:0] D,
input [4:0] INMODE,
input MULTSIGNIN,
input [8:0] OPMODE,
input [47:0] PCIN,
input RSTA,
input RSTALLCARRYIN,
input RSTALUMODE,
input RSTB,
input RSTC,
input RSTCTRL,
input RSTD,
input RSTINMODE,
input RSTM,
input RSTP
);
// define constants
localparam MODULE_NAME = "DSP48E2";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
// logic depends on ACASCREG, AREG encoding the same
localparam ACASCREG_0 = 1;
localparam ACASCREG_1 = 0;
localparam ACASCREG_2 = 2;
localparam ADREG_0 = 1;
localparam ADREG_1 = 0;
localparam ALUMODEREG_0 = 1;
localparam ALUMODEREG_1 = 0;
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam AREG_0 = 1;
localparam AREG_1 = 0;
localparam AREG_2 = 2;
localparam AUTORESET_PATDET_NO_RESET = 0;
localparam AUTORESET_PATDET_RESET_MATCH = 1;
localparam AUTORESET_PATDET_RESET_NOT_MATCH = 2;
localparam AUTORESET_PRIORITY_CEP = 1;
localparam AUTORESET_PRIORITY_RESET = 0;
localparam A_INPUT_CASCADE = 1;
localparam A_INPUT_DIRECT = 0;
localparam BCASCREG_0 = 1;
localparam BCASCREG_1 = 0;
localparam BCASCREG_2 = 2;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam BREG_0 = 1;
localparam BREG_1 = 0;
localparam BREG_2 = 2;
localparam B_INPUT_CASCADE = 1;
localparam B_INPUT_DIRECT = 0;
localparam CARRYINREG_0 = 1;
localparam CARRYINREG_1 = 0;
localparam CARRYINSELREG_0 = 1;
localparam CARRYINSELREG_1 = 0;
localparam CREG_0 = 1;
localparam CREG_1 = 0;
localparam DREG_0 = 1;
localparam DREG_1 = 0;
localparam INMODEREG_0 = 1;
localparam INMODEREG_1 = 0;
localparam MREG_0 = 1;
localparam MREG_1 = 0;
localparam OPMODEREG_0 = 1;
localparam OPMODEREG_1 = 0;
localparam PREADDINSEL_A = 0;
localparam PREADDINSEL_B = 1;
localparam PREG_0 = 1;
localparam PREG_1 = 0;
localparam SEL_MASK_C = 1;
localparam SEL_MASK_MASK = 0;
localparam SEL_MASK_ROUNDING_MODE1 = 2;
localparam SEL_MASK_ROUNDING_MODE2 = 3;
localparam SEL_PATTERN_C = 1;
localparam SEL_PATTERN_PATTERN = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
localparam USE_PATTERN_DETECT_NO_PATDET = 0;
localparam USE_PATTERN_DETECT_PATDET = 1;
localparam USE_SIMD_FOUR12 = 7;
localparam USE_SIMD_ONE48 = 0;
localparam USE_SIMD_TWO24 = 2;
// USE_SIMD uses bits from actual encodings
localparam USE_WIDEXOR_FALSE = 0;
localparam USE_WIDEXOR_TRUE = 1;
localparam XORSIMD_XOR12 = 1;
localparam XORSIMD_XOR24_48_96 = 0;
`ifndef XIL_DR
localparam [1:0] ACASCREG_REG = ACASCREG;
localparam [0:0] ADREG_REG = ADREG;
localparam [0:0] ALUMODEREG_REG = ALUMODEREG;
localparam [16:1] AMULTSEL_REG = AMULTSEL;
localparam [1:0] AREG_REG = AREG;
localparam [120:1] AUTORESET_PATDET_REG = AUTORESET_PATDET;
localparam [40:1] AUTORESET_PRIORITY_REG = AUTORESET_PRIORITY;
localparam [56:1] A_INPUT_REG = A_INPUT;
localparam [1:0] BCASCREG_REG = BCASCREG;
localparam [16:1] BMULTSEL_REG = BMULTSEL;
localparam [1:0] BREG_REG = BREG;
localparam [56:1] B_INPUT_REG = B_INPUT;
localparam [0:0] CARRYINREG_REG = CARRYINREG;
localparam [0:0] CARRYINSELREG_REG = CARRYINSELREG;
localparam [0:0] CREG_REG = CREG;
localparam [0:0] DREG_REG = DREG;
localparam [0:0] INMODEREG_REG = INMODEREG;
localparam [3:0] IS_ALUMODE_INVERTED_REG = IS_ALUMODE_INVERTED;
localparam [0:0] IS_CARRYIN_INVERTED_REG = IS_CARRYIN_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED;
localparam [8:0] IS_OPMODE_INVERTED_REG = IS_OPMODE_INVERTED;
localparam [0:0] IS_RSTALLCARRYIN_INVERTED_REG = IS_RSTALLCARRYIN_INVERTED;
localparam [0:0] IS_RSTALUMODE_INVERTED_REG = IS_RSTALUMODE_INVERTED;
localparam [0:0] IS_RSTA_INVERTED_REG = IS_RSTA_INVERTED;
localparam [0:0] IS_RSTB_INVERTED_REG = IS_RSTB_INVERTED;
localparam [0:0] IS_RSTCTRL_INVERTED_REG = IS_RSTCTRL_INVERTED;
localparam [0:0] IS_RSTC_INVERTED_REG = IS_RSTC_INVERTED;
localparam [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED;
localparam [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED;
localparam [0:0] IS_RSTM_INVERTED_REG = IS_RSTM_INVERTED;
localparam [0:0] IS_RSTP_INVERTED_REG = IS_RSTP_INVERTED;
localparam [47:0] MASK_REG = MASK;
localparam [0:0] MREG_REG = MREG;
localparam [0:0] OPMODEREG_REG = OPMODEREG;
localparam [47:0] PATTERN_REG = PATTERN;
localparam [8:1] PREADDINSEL_REG = PREADDINSEL;
localparam [0:0] PREG_REG = PREG;
localparam [47:0] RND_REG = RND;
localparam [112:1] SEL_MASK_REG = SEL_MASK;
localparam [56:1] SEL_PATTERN_REG = SEL_PATTERN;
localparam [64:1] USE_MULT_REG = USE_MULT;
localparam [72:1] USE_PATTERN_DETECT_REG = USE_PATTERN_DETECT;
localparam [48:1] USE_SIMD_REG = USE_SIMD;
localparam [40:1] USE_WIDEXOR_REG = USE_WIDEXOR;
localparam [88:1] XORSIMD_REG = XORSIMD;
`endif
wire [1:0] ACASCREG_BIN;
wire ADREG_BIN;
wire ALUMODEREG_BIN;
wire AMULTSEL_BIN;
wire [1:0] AREG_BIN;
wire [1:0] AUTORESET_PATDET_BIN;
wire AUTORESET_PRIORITY_BIN;
wire A_INPUT_BIN;
wire [1:0] BCASCREG_BIN;
wire BMULTSEL_BIN;
wire [1:0] BREG_BIN;
wire B_INPUT_BIN;
wire CARRYINREG_BIN;
wire CARRYINSELREG_BIN;
wire CREG_BIN;
wire DREG_BIN;
wire INMODEREG_BIN;
wire [3:0] IS_ALUMODE_INVERTED_BIN;
wire IS_CARRYIN_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire [4:0] IS_INMODE_INVERTED_BIN;
wire [8:0] IS_OPMODE_INVERTED_BIN;
wire IS_RSTALLCARRYIN_INVERTED_BIN;
wire IS_RSTALUMODE_INVERTED_BIN;
wire IS_RSTA_INVERTED_BIN;
wire IS_RSTB_INVERTED_BIN;
wire IS_RSTCTRL_INVERTED_BIN;
wire IS_RSTC_INVERTED_BIN;
wire IS_RSTD_INVERTED_BIN;
wire IS_RSTINMODE_INVERTED_BIN;
wire IS_RSTM_INVERTED_BIN;
wire IS_RSTP_INVERTED_BIN;
wire [47:0] MASK_BIN;
wire MREG_BIN;
wire OPMODEREG_BIN;
wire [47:0] PATTERN_BIN;
wire PREADDINSEL_BIN;
wire PREG_BIN;
wire [47:0] RND_BIN;
wire [1:0] SEL_MASK_BIN;
wire SEL_PATTERN_BIN;
wire [1:0] USE_MULT_BIN;
wire USE_PATTERN_DETECT_BIN;
wire [2:0] USE_SIMD_BIN;
wire USE_WIDEXOR_BIN;
wire XORSIMD_BIN;
tri0 glblGSR = glbl.GSR;
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP48E2_dr.v"
`endif
wire ADDSUB_out;
wire ALUMODE10_out;
wire AMULT26_out;
wire BMULT17_out;
wire CARRYCASCOUT_out;
wire CCOUT_FB_out;
wire INMODE_2_out;
wire MULTSIGN_ALU_out;
wire MULTSIGNOUT_out;
wire OVERFLOW_out;
wire PATTERN_B_DETECT_out;
wire PATTERN_DETECT_out;
wire P_FDBK_47_out;
wire UNDERFLOW_out;
wire [17:0] B2B1_out;
wire [17:0] B1_DATA_out;
wire [17:0] B2_DATA_out;
wire [17:0] BCOUT_out;
wire [17:0] B_ALU_out;
wire [26:0] A2A1_out;
wire [26:0] AD_DATA_out;
wire [26:0] D_DATA_out;
wire [26:0] AD_out;
wire [26:0] A1_DATA_out;
wire [26:0] A2_DATA_out;
wire [26:0] PREADD_AB_out;
wire [29:0] ACOUT_out;
wire [29:0] A_ALU_out;
wire [3:0] COUT_out;
wire [3:0] CARRYOUT_out;
wire [44:0] U_out;
wire [44:0] V_out;
wire [44:0] U_DATA_out;
wire [44:0] V_DATA_out;
wire [47:0] ALU_OUT_out;
wire [7:0] XOR_MX_out;
wire [47:0] C_DATA_out;
wire [47:0] PCOUT_out;
wire [47:0] P_FDBK_out;
wire [47:0] P_out;
wire [7:0] XOROUT_out;
wire ALUMODE10_delay;
wire ADDSUB_delay;
wire AMULT26_delay;
wire BMULT17_delay;
wire CARRYCASCOUT_delay;
wire CCOUT_FB_delay;
wire INMODE_2_delay;
wire MULTSIGN_ALU_delay;
wire MULTSIGNOUT_delay;
wire OVERFLOW_delay;
wire PATTERN_B_DETECT_delay;
wire PATTERN_DETECT_delay;
wire P_FDBK_47_delay;
wire UNDERFLOW_delay;
wire [17:0] B2B1_delay;
wire [17:0] B1_DATA_delay;
wire [17:0] B2_DATA_delay;
wire [17:0] BCOUT_delay;
wire [17:0] B_ALU_delay;
wire [26:0] A2A1_delay;
wire [26:0] AD_DATA_delay;
wire [26:0] D_DATA_delay;
wire [26:0] AD_delay;
wire [26:0] A1_DATA_delay;
wire [26:0] A2_DATA_delay;
wire [26:0] PREADD_AB_delay;
wire [29:0] ACOUT_delay;
wire [29:0] A_ALU_delay;
wire [3:0] COUT_delay;
wire [3:0] CARRYOUT_delay;
wire [44:0] U_delay;
wire [44:0] V_delay;
wire [44:0] U_DATA_delay;
wire [44:0] V_DATA_delay;
wire [47:0] ALU_OUT_delay;
wire [7:0] XOR_MX_delay;
wire [47:0] C_DATA_delay;
wire [47:0] PCOUT_delay;
wire [47:0] P_FDBK_delay;
wire [47:0] P_delay;
wire [7:0] XOROUT_delay;
wire AMULT26_in;
wire BMULT17_in;
wire ADDSUB_in;
wire ALUMODE10_in;
wire CARRYCASCIN_in;
wire CARRYIN_in;
wire CCOUT_in;
wire CEA1_in;
wire CEA2_in;
wire CEAD_in;
wire CEALUMODE_in;
wire CEB1_in;
wire CEB2_in;
wire CECARRYIN_in;
wire CECTRL_in;
wire CEC_in;
wire CED_in;
wire CEINMODE_in;
wire CEM_in;
wire CEP_in;
wire CLK_in;
wire INMODE_2_in;
wire MULTSIGNIN_in;
wire MULTSIGN_ALU_in;
wire P_FDBK_47_in;
wire RSTALLCARRYIN_in;
wire RSTALUMODE_in;
wire RSTA_in;
wire RSTB_in;
wire RSTCTRL_in;
wire RSTC_in;
wire RSTD_in;
wire RSTINMODE_in;
wire RSTM_in;
wire RSTP_in;
wire [17:0] B_ALU_in;
wire [29:0] A_ALU_in;
wire [17:0] B1_DATA_in;
wire [17:0] B2B1_in;
wire [17:0] B2_DATA_in;
wire [17:0] BCIN_in;
wire [17:0] B_in;
wire [26:0] A1_DATA_in;
wire [26:0] A2A1_in;
wire [26:0] AD_DATA_in;
wire [26:0] A2_DATA_in;
wire [26:0] AD_in;
wire [26:0] DIN_in;
wire [26:0] D_DATA_in;
wire [26:0] D_in;
wire [26:0] PREADD_AB_in;
wire [29:0] ACIN_in;
wire [29:0] A_in;
wire [2:0] CARRYINSEL_in;
wire [3:0] ALUMODE_in;
wire [3:0] COUT_in;
wire [44:0] U_in;
wire [44:0] V_in;
wire [44:0] U_DATA_in;
wire [44:0] V_DATA_in;
wire [47:0] ALU_OUT_in;
wire [47:0] C_DATA_in;
wire [47:0] C_in;
wire [47:0] PCIN_in;
wire [47:0] P_FDBK_in;
wire [4:0] INMODE_in;
wire [7:0] XOR_MX_in;
wire [8:0] OPMODE_in;
wire CARRYCASCIN_delay;
wire CARRYIN_delay;
wire CEA1_delay;
wire CEA2_delay;
wire CEAD_delay;
wire CEALUMODE_delay;
wire CEB1_delay;
wire CEB2_delay;
wire CECARRYIN_delay;
wire CECTRL_delay;
wire CEC_delay;
wire CED_delay;
wire CEINMODE_delay;
wire CEM_delay;
wire CEP_delay;
wire CLK_delay;
wire MULTSIGNIN_delay;
wire RSTALLCARRYIN_delay;
wire RSTALUMODE_delay;
wire RSTA_delay;
wire RSTB_delay;
wire RSTCTRL_delay;
wire RSTC_delay;
wire RSTD_delay;
wire RSTINMODE_delay;
wire RSTM_delay;
wire RSTP_delay;
wire [17:0] BCIN_delay;
wire [17:0] B_delay;
wire [26:0] D_delay;
wire [29:0] ACIN_delay;
wire [29:0] A_delay;
wire [2:0] CARRYINSEL_delay;
wire [3:0] ALUMODE_delay;
wire [47:0] C_delay;
wire [47:0] PCIN_delay;
wire [4:0] INMODE_delay;
wire [8:0] OPMODE_delay;
// DSP_ALU wires
localparam MAX_ALU_FULL = 48;
localparam MAX_CARRYOUT = 4;
wire CARRYIN_mux;
reg CARRYIN_reg = 1'b0;
wire [3:0] ALUMODE_mux;
reg [3:0] ALUMODE_reg = 4'b0;
wire [2:0] CARRYINSEL_mux;
reg [2:0] CARRYINSEL_reg = 3'b0;
wire [8:0] OPMODE_mux;
reg [8:0] OPMODE_reg = 9'b0;
// wire [47:0] ALU_OUT_tmp;
wire [47:0] alu_o;
// wire u_43_data;
wire [47:0] x_mac_cascd;
reg [47:0] wmux = 48'b0;
reg [47:0] xmux = 48'b0;
reg [47:0] ymux = 48'b0;
reg [47:0] zmux = 48'b0;
wire [47:0] z_optinv;
wire cin;
reg cin_b = 1'b0;
wire rst_carryin_g;
reg qmultcarryin = 1'b0;
wire c_mult;
wire ce_m_g;
wire d_carryin_int;
wire dr_carryin_int;
wire multcarryin_data;
reg invalid_opmode = 1'b1;
reg opmode_valid_flag_dal = 1'b1; // used in OPMODE DRC
reg ping_opmode_drc_check = 1'b0;
wire [MAX_ALU_FULL-1:0] co;
wire [MAX_ALU_FULL-1:0] s;
wire [MAX_ALU_FULL-1:0] comux;
wire [MAX_ALU_FULL-1:0] comux_w;
wire [MAX_ALU_FULL-1:0] comux4simd;
wire [MAX_ALU_FULL-1:0] smux;
wire [MAX_ALU_FULL-1:0] smux_w;
// wire [MAX_CARRYOUT-1:0] carryout_o_hw;
// wire [MAX_CARRYOUT-1:0] carryout_o;
wire [48:0] a_int;
wire [47:0] b_int;
wire [12:0] s0;
wire cout0;
wire intc1;
wire co12_lsb;
wire [12:0] s1;
wire cout1;
wire intc2;
wire co24_lsb;
wire [12:0] s2;
wire cout2;
wire intc3;
wire co36_lsb;
wire [13:0] s3;
wire cout3;
wire cout4;
wire xor_12a;
wire xor_12b;
wire xor_12c;
wire xor_12d;
wire xor_12e;
wire xor_12f;
wire xor_12g;
wire xor_12h;
wire xor_24a;
wire xor_24b;
wire xor_24c;
wire xor_24d;
wire xor_48a;
wire xor_48b;
wire xor_96;
wire cout_0;
wire cout_1;
wire cout_2;
wire cout_3;
wire mult_or_logic;
// DSP_A_B_DATA wires
wire [29:0] A_ACIN_mux;
wire [29:0] A1_reg_mux;
wire [29:0] A2_reg_mux;
reg [29:0] A1_reg = 30'b0;
reg [29:0] A2_reg = 30'b0;
wire [17:0] B_BCIN_mux;
wire [17:0] B1_reg_mux;
wire [17:0] B2_reg_mux;
reg [17:0] B1_reg = 18'b0;
reg [17:0] B2_reg = 18'b0;
wire CLK_areg1;
wire CLK_areg2;
wire CLK_breg1;
wire CLK_breg2;
// DSP_C_DATA wires
reg [47:0] C_reg = 48'b0;
wire CLK_creg;
// DSP_MULTIPLIER wires
wire [17:0] b_mult_mux;
wire [26:0] a_mult_mux;
wire [44:0] mult;
reg [43:0] ps_u_mask = 44'h55555555555;
reg [43:0] ps_v_mask = 44'haaaaaaaaaaa;
// DSP_M_DATA wires
reg [44:0] U_DATA_reg = 45'h100000000000;
reg [44:0] V_DATA_reg = 45'h100000000000;
wire CLK_mreg;
// DSP_OUTPUT wires
wire the_auto_reset_patdet;
wire auto_reset_pri;
// reg [47:0] the_mask = 0;
wire [47:0] the_mask;
wire [47:0] the_pattern;
reg opmode_valid_flag_dou = 1'b1; // TODO
// reg [3:0] COUT_reg = 4'b0xxx;
reg [3:0] COUT_reg = 4'b0000;
reg ALUMODE10_reg = 1'b0;
wire ALUMODE10_mux;
reg MULTSIGN_ALU_reg = 1'b0;
reg [47:0] ALU_OUT_reg = 48'b0;
reg [7:0] XOR_MX_reg = 8'b0;
wire pdet_o;
wire pdetb_o;
wire pdet_o_mux;
wire pdetb_o_mux;
wire overflow_data;
wire underflow_data;
reg pdet_o_reg1 = 1'b0;
reg pdet_o_reg2 = 1'b0;
reg pdetb_o_reg1 = 1'b0;
reg pdetb_o_reg2 = 1'b0;
wire CLK_preg;
// DSP_PREADD wires
wire [26:0] D_DATA_mux;
// DSP_PREADD_DATA wires
wire [26:0] a1a2_i_mux;
wire [17:0] b1b2_i_mux;
wire [4:0] INMODE_mux;
reg [4:0] INMODE_reg = 5'b0;
reg [26:0] AD_DATA_reg = 27'b0;
reg [26:0] D_DATA_reg = 27'b0;
wire CLK_inmode;
wire CLK_dreg;
wire CLK_adreg;
// input output assignments
assign #(out_delay) ACOUT = ACOUT_delay;
assign #(out_delay) BCOUT = BCOUT_delay;
assign #(out_delay) CARRYCASCOUT = CARRYCASCOUT_delay;
assign #(out_delay) CARRYOUT = CARRYOUT_delay;
assign #(out_delay) MULTSIGNOUT = MULTSIGNOUT_delay;
assign #(out_delay) OVERFLOW = OVERFLOW_delay;
assign #(out_delay) P = P_delay;
assign #(out_delay) PATTERNBDETECT = PATTERN_B_DETECT_delay;
assign #(out_delay) PATTERNDETECT = PATTERN_DETECT_delay;
assign #(out_delay) PCOUT = PCOUT_delay;
assign #(out_delay) UNDERFLOW = UNDERFLOW_delay;
assign #(out_delay) XOROUT = XOROUT_delay;
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) ACIN_delay = ACIN;
assign #(in_delay) ALUMODE_delay = ALUMODE;
assign #(in_delay) A_delay = A;
assign #(in_delay) BCIN_delay = BCIN;
assign #(in_delay) B_delay = B;
assign #(in_delay) CARRYINSEL_delay = CARRYINSEL;
assign #(in_delay) CARRYIN_delay = CARRYIN;
assign #(in_delay) CEA1_delay = CEA1;
assign #(in_delay) CEA2_delay = CEA2;
assign #(in_delay) CEAD_delay = CEAD;
assign #(in_delay) CEALUMODE_delay = CEALUMODE;
assign #(in_delay) CEB1_delay = CEB1;
assign #(in_delay) CEB2_delay = CEB2;
assign #(in_delay) CECARRYIN_delay = CECARRYIN;
assign #(in_delay) CECTRL_delay = CECTRL;
assign #(in_delay) CEC_delay = CEC;
assign #(in_delay) CED_delay = CED;
assign #(in_delay) CEINMODE_delay = CEINMODE;
assign #(in_delay) CEM_delay = CEM;
assign #(in_delay) CEP_delay = CEP;
assign #(in_delay) C_delay = C;
assign #(in_delay) D_delay = D;
assign #(in_delay) INMODE_delay = INMODE;
assign #(in_delay) OPMODE_delay = OPMODE;
assign #(in_delay) RSTALLCARRYIN_delay = RSTALLCARRYIN;
assign #(in_delay) RSTALUMODE_delay = RSTALUMODE;
assign #(in_delay) RSTA_delay = RSTA;
assign #(in_delay) RSTB_delay = RSTB;
assign #(in_delay) RSTCTRL_delay = RSTCTRL;
assign #(in_delay) RSTC_delay = RSTC;
assign #(in_delay) RSTD_delay = RSTD;
assign #(in_delay) RSTINMODE_delay = RSTINMODE;
assign #(in_delay) RSTM_delay = RSTM;
assign #(in_delay) RSTP_delay = RSTP;
assign #(in_delay) CARRYCASCIN_delay = CARRYCASCIN;
assign #(in_delay) MULTSIGNIN_delay = MULTSIGNIN;
assign #(in_delay) PCIN_delay = PCIN;
assign ALUMODE10_delay = ALUMODE10_out;
assign ALU_OUT_delay = ALU_OUT_out;
// assign COUT_delay = ((OPMODE_mux[3:0] == 4'b0101) || (ALUMODE_mux[3:2] != 2'b00)) ? 4'hx : COUT_out;
assign COUT_delay = COUT_out;
assign MULTSIGN_ALU_delay = MULTSIGN_ALU_out;
assign XOR_MX_delay = XOR_MX_out;
assign CCOUT_FB_delay = CCOUT_FB_out;
assign P_FDBK_delay = P_FDBK_out;
assign P_FDBK_47_delay = P_FDBK_47_out;
assign A2A1_delay = A2A1_out;
assign ADDSUB_delay = ADDSUB_out;
assign AMULT26_delay = AMULT26_out;
assign AD_DATA_delay = AD_DATA_out;
assign AD_delay = AD_out;
assign A1_DATA_delay = A1_DATA_out;
assign A2_DATA_delay = A2_DATA_out;
assign ACOUT_delay = ACOUT_out;
assign A_ALU_delay = A_ALU_out;
assign B1_DATA_delay = B1_DATA_out;
assign B2B1_delay = B2B1_out;
assign B2_DATA_delay = B2_DATA_out;
assign BCOUT_delay = BCOUT_out;
assign BMULT17_delay = BMULT17_out;
assign B_ALU_delay = B_ALU_out;
assign CARRYCASCOUT_delay = CARRYCASCOUT_out;
assign CARRYOUT_delay = CARRYOUT_out;
assign C_DATA_delay = C_DATA_out;
assign D_DATA_delay = D_DATA_out;
assign INMODE_2_delay = INMODE_2_out;
assign MULTSIGNOUT_delay = MULTSIGNOUT_out;
assign OVERFLOW_delay = OVERFLOW_out;
assign PATTERN_B_DETECT_delay = PATTERN_B_DETECT_out;
assign PATTERN_DETECT_delay = PATTERN_DETECT_out;
assign PCOUT_delay = PCOUT_out;
assign PREADD_AB_delay = PREADD_AB_out;
assign P_delay = P_out;
assign UNDERFLOW_delay = UNDERFLOW_out;
assign U_delay = U_out;
assign V_delay = V_out;
assign U_DATA_delay = U_DATA_out;
assign V_DATA_delay = V_DATA_out;
assign XOROUT_delay = XOROUT_out;
assign AMULT26_in = AMULT26_delay;
assign A_ALU_in = A_ALU_delay;
assign BMULT17_in = BMULT17_delay;
assign B_ALU_in = B_ALU_delay;
assign CCOUT_in = CCOUT_FB_delay;
assign P_FDBK_47_in = P_FDBK_47_delay;
assign P_FDBK_in = P_FDBK_delay;
assign U_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? U_DATA_delay : 45'h100000000000;
assign V_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? V_DATA_delay : 45'h100000000000;
assign ALUMODE10_in = ALUMODE10_delay;
assign #1 ALU_OUT_in = ALU_OUT_delay; // break 0 delay feedback
assign COUT_in = COUT_delay;
assign MULTSIGN_ALU_in = MULTSIGN_ALU_delay;
assign XOR_MX_in = XOR_MX_delay;
assign A2A1_in = A2A1_delay;
assign AD_DATA_in = AD_DATA_delay;
assign B2B1_in = B2B1_delay;
assign A1_DATA_in = A1_DATA_delay;
assign A2_DATA_in = A2_DATA_delay;
assign ACIN_in = ACIN_delay;
assign ADDSUB_in = ADDSUB_delay;
assign AD_in = AD_delay;
assign ALUMODE_in = ALUMODE_delay ^ IS_ALUMODE_INVERTED_BIN;
assign A_in = A_delay;
assign B1_DATA_in = B1_DATA_delay;
assign B2_DATA_in = B2_DATA_delay;
assign BCIN_in = BCIN_delay;
assign B_in = B_delay;
assign CARRYCASCIN_in = CARRYCASCIN_delay;
assign CARRYINSEL_in = CARRYINSEL_delay;
assign CARRYIN_in = CARRYIN_delay ^ IS_CARRYIN_INVERTED_BIN;
assign CEA1_in = CEA1_delay;
assign CEA2_in = CEA2_delay;
assign CEAD_in = CEAD_delay;
assign CEALUMODE_in = CEALUMODE_delay;
assign CEB1_in = CEB1_delay;
assign CEB2_in = CEB2_delay;
assign CECARRYIN_in = CECARRYIN_delay;
assign CECTRL_in = CECTRL_delay;
assign CEC_in = CEC_delay;
assign CED_in = CED_delay;
assign CEINMODE_in = CEINMODE_delay;
assign CEM_in = CEM_delay;
assign CEP_in = CEP_delay;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_areg1 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_areg2 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_breg1 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_breg2 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_creg = (CREG_BIN == CREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_mreg = (MREG_BIN == MREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_preg = (PREG_BIN == PREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_inmode = (INMODEREG_BIN == INMODEREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_dreg = (DREG_BIN == DREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_adreg = (ADREG_BIN == ADREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign C_DATA_in = C_DATA_delay;
assign C_in = C_delay;
assign DIN_in = D_delay;
assign D_DATA_in = D_DATA_delay;
assign D_in = D_delay;
assign INMODE_2_in = INMODE_2_delay;
assign INMODE_in = INMODE_delay ^ IS_INMODE_INVERTED_BIN;
assign MULTSIGNIN_in = MULTSIGNIN_delay;
assign OPMODE_in = OPMODE_delay ^ IS_OPMODE_INVERTED_BIN;
assign PCIN_in = PCIN_delay;
assign PREADD_AB_in = PREADD_AB_delay;
assign RSTALLCARRYIN_in = RSTALLCARRYIN_delay ^ IS_RSTALLCARRYIN_INVERTED_BIN;
assign RSTALUMODE_in = RSTALUMODE_delay ^ IS_RSTALUMODE_INVERTED_BIN;
assign RSTA_in = RSTA_delay ^ IS_RSTA_INVERTED_BIN;
assign RSTB_in = RSTB_delay ^ IS_RSTB_INVERTED_BIN;
assign RSTCTRL_in = RSTCTRL_delay ^ IS_RSTCTRL_INVERTED_BIN;
assign RSTC_in = RSTC_delay ^ IS_RSTC_INVERTED_BIN;
assign RSTD_in = RSTD_delay ^ IS_RSTD_INVERTED_BIN;
assign RSTINMODE_in = RSTINMODE_delay ^ IS_RSTINMODE_INVERTED_BIN;
assign RSTM_in = RSTM_delay ^ IS_RSTM_INVERTED_BIN;
assign RSTP_in = RSTP_delay ^ IS_RSTP_INVERTED_BIN;
assign U_in = U_delay;
assign V_in = V_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign ACASCREG_BIN =
(ACASCREG_REG == 1) ? ACASCREG_1 :
(ACASCREG_REG == 0) ? ACASCREG_0 :
(ACASCREG_REG == 2) ? ACASCREG_2 :
ACASCREG_1;
assign ADREG_BIN =
(ADREG_REG == 1) ? ADREG_1 :
(ADREG_REG == 0) ? ADREG_0 :
ADREG_1;
assign ALUMODEREG_BIN =
(ALUMODEREG_REG == 1) ? ALUMODEREG_1 :
(ALUMODEREG_REG == 0) ? ALUMODEREG_0 :
ALUMODEREG_1;
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign AREG_BIN =
(AREG_REG == 1) ? AREG_1 :
(AREG_REG == 0) ? AREG_0 :
(AREG_REG == 2) ? AREG_2 :
AREG_1;
assign AUTORESET_PATDET_BIN =
(AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET :
(AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH :
(AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH :
AUTORESET_PATDET_NO_RESET;
assign AUTORESET_PRIORITY_BIN =
(AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET :
(AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP :
AUTORESET_PRIORITY_RESET;
assign A_INPUT_BIN =
(A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT :
(A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE :
A_INPUT_DIRECT;
assign BCASCREG_BIN =
(BCASCREG_REG == 1) ? BCASCREG_1 :
(BCASCREG_REG == 0) ? BCASCREG_0 :
(BCASCREG_REG == 2) ? BCASCREG_2 :
BCASCREG_1;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign BREG_BIN =
(BREG_REG == 1) ? BREG_1 :
(BREG_REG == 0) ? BREG_0 :
(BREG_REG == 2) ? BREG_2 :
BREG_1;
assign B_INPUT_BIN =
(B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT :
(B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE :
B_INPUT_DIRECT;
assign CARRYINREG_BIN =
(CARRYINREG_REG == 1) ? CARRYINREG_1 :
(CARRYINREG_REG == 0) ? CARRYINREG_0 :
CARRYINREG_1;
assign CARRYINSELREG_BIN =
(CARRYINSELREG_REG == 1) ? CARRYINSELREG_1 :
(CARRYINSELREG_REG == 0) ? CARRYINSELREG_0 :
CARRYINSELREG_1;
assign CREG_BIN =
(CREG_REG == 1) ? CREG_1 :
(CREG_REG == 0) ? CREG_0 :
CREG_1;
assign DREG_BIN =
(DREG_REG == 1) ? DREG_1 :
(DREG_REG == 0) ? DREG_0 :
DREG_1;
assign INMODEREG_BIN =
(INMODEREG_REG == 1) ? INMODEREG_1 :
(INMODEREG_REG == 0) ? INMODEREG_0 :
INMODEREG_1;
assign IS_ALUMODE_INVERTED_BIN = IS_ALUMODE_INVERTED_REG;
assign IS_CARRYIN_INVERTED_BIN = IS_CARRYIN_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_INMODE_INVERTED_BIN = IS_INMODE_INVERTED_REG;
assign IS_OPMODE_INVERTED_BIN = IS_OPMODE_INVERTED_REG;
assign IS_RSTALLCARRYIN_INVERTED_BIN = IS_RSTALLCARRYIN_INVERTED_REG;
assign IS_RSTALUMODE_INVERTED_BIN = IS_RSTALUMODE_INVERTED_REG;
assign IS_RSTA_INVERTED_BIN = IS_RSTA_INVERTED_REG;
assign IS_RSTB_INVERTED_BIN = IS_RSTB_INVERTED_REG;
assign IS_RSTCTRL_INVERTED_BIN = IS_RSTCTRL_INVERTED_REG;
assign IS_RSTC_INVERTED_BIN = IS_RSTC_INVERTED_REG;
assign IS_RSTD_INVERTED_BIN = IS_RSTD_INVERTED_REG;
assign IS_RSTINMODE_INVERTED_BIN = IS_RSTINMODE_INVERTED_REG;
assign IS_RSTM_INVERTED_BIN = IS_RSTM_INVERTED_REG;
assign IS_RSTP_INVERTED_BIN = IS_RSTP_INVERTED_REG;
assign MASK_BIN = MASK_REG;
assign MREG_BIN =
(MREG_REG == 1) ? MREG_1 :
(MREG_REG == 0) ? MREG_0 :
MREG_1;
assign OPMODEREG_BIN =
(OPMODEREG_REG == 1) ? OPMODEREG_1 :
(OPMODEREG_REG == 0) ? OPMODEREG_0 :
OPMODEREG_1;
assign PATTERN_BIN = PATTERN_REG;
assign PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
assign PREG_BIN =
(PREG_REG == 1) ? PREG_1 :
(PREG_REG == 0) ? PREG_0 :
PREG_1;
assign RND_BIN = RND_REG;
assign SEL_MASK_BIN =
(SEL_MASK_REG == "MASK") ? SEL_MASK_MASK :
(SEL_MASK_REG == "C") ? SEL_MASK_C :
(SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 :
(SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 :
SEL_MASK_MASK;
assign SEL_PATTERN_BIN =
(SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN :
(SEL_PATTERN_REG == "C") ? SEL_PATTERN_C :
SEL_PATTERN_PATTERN;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
assign USE_PATTERN_DETECT_BIN =
(USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET :
(USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET :
USE_PATTERN_DETECT_NO_PATDET;
assign USE_SIMD_BIN =
(USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 :
(USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 :
(USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 :
USE_SIMD_ONE48;
assign USE_WIDEXOR_BIN =
(USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE :
(USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE :
USE_WIDEXOR_FALSE;
assign XORSIMD_BIN =
(XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 :
(XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 :
XORSIMD_XOR24_48_96;
always @ (trig_attr) begin
#1;
//-------- AMULTSEL check
if ((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute AMULTSEL on %s instance %m is set to %s. Legal values for this attribute are A or AD.", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
//-------- AUTORESET_PATDET check
if ((AUTORESET_PATDET_REG != "NO_RESET") &&
(AUTORESET_PATDET_REG != "RESET_MATCH") &&
(AUTORESET_PATDET_REG != "RESET_NOT_MATCH")) begin
$display("Attribute Syntax Error : The attribute AUTORESET_PATDET on %s instance %m is set to %s. Legal values for this attribute are NO_RESET, RESET_MATCH or RESET_NOT_MATCH.", MODULE_NAME, AUTORESET_PATDET_REG);
attr_err = 1'b1;
end
//-------- AUTORESET_PRIORITY check
if ((AUTORESET_PRIORITY_REG != "RESET") &&
(AUTORESET_PRIORITY_REG != "CEP")) begin
$display("Attribute Syntax Error : The attribute AUTORESET_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are RESET or CEP.", MODULE_NAME, AUTORESET_PRIORITY_REG);
attr_err = 1'b1;
end
//-------- A_INPUT check
if ((A_INPUT_REG != "DIRECT") &&
(A_INPUT_REG != "CASCADE")) begin
$display("Attribute Syntax Error : The attribute A_INPUT on %s instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", MODULE_NAME, A_INPUT_REG);
attr_err = 1'b1;
end
//-------- BMULTSEL check
if ((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute BMULTSEL on %s instance %m is set to %s. Legal values for this attribute are B or AD.", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
//-------- B_INPUT check
if ((B_INPUT_REG != "DIRECT") &&
(B_INPUT_REG != "CASCADE")) begin
$display("Attribute Syntax Error : The attribute B_INPUT on %s instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", MODULE_NAME, B_INPUT_REG);
attr_err = 1'b1;
end
//-------- PREADDINSEL check
if ((PREADDINSEL_REG != "A") &&
(PREADDINSEL_REG != "B")) begin
$display("Attribute Syntax Error : The attribute PREADDINSEL on %s instance %m is set to %s. Legal values for this attribute are A or B.", MODULE_NAME, PREADDINSEL_REG);
attr_err = 1'b1;
end
//-------- SEL_MASK check
if ((SEL_MASK_REG != "MASK") &&
(SEL_MASK_REG != "C") &&
(SEL_MASK_REG != "ROUNDING_MODE1") &&
(SEL_MASK_REG != "ROUNDING_MODE2")) begin
$display("Attribute Syntax Error : The attribute SEL_MASK on %s instance %m is set to %s. Legal values for this attribute are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2.", MODULE_NAME, SEL_MASK_REG);
attr_err = 1'b1;
end
//-------- SEL_PATTERN check
if ((SEL_PATTERN_REG != "PATTERN") &&
(SEL_PATTERN_REG != "C")) begin
$display("Attribute Syntax Error : The attribute SEL_PATTERN on %s instance %m is set to %s. Legal values for this attribute are PATTERN or C.", MODULE_NAME, SEL_PATTERN_REG);
attr_err = 1'b1;
end
//-------- USE_MULT check
if ((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE")) begin
$display("Attribute Syntax Error : The attribute USE_MULT on %s instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
//-------- USE_PATTERN_DETECT check
if ((USE_PATTERN_DETECT_REG != "NO_PATDET") &&
(USE_PATTERN_DETECT_REG != "PATDET")) begin
$display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on %s instance %m is set to %s. Legal values for this attribute are NO_PATDET or PATDET.", MODULE_NAME, USE_PATTERN_DETECT_REG);
attr_err = 1'b1;
end
//-------- USE_SIMD check
if ((USE_SIMD_REG != "ONE48") &&
(USE_SIMD_REG != "FOUR12") &&
(USE_SIMD_REG != "TWO24")) begin
$display("Attribute Syntax Error : The attribute USE_SIMD on %s instance %m is set to %s. Legal values for this attribute are ONE48, FOUR12 or TWO24.", MODULE_NAME, USE_SIMD_REG);
attr_err = 1'b1;
end
//-------- USE_WIDEXOR check
if ((USE_WIDEXOR_REG != "FALSE") &&
(USE_WIDEXOR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute USE_WIDEXOR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, USE_WIDEXOR_REG);
attr_err = 1'b1;
end
//-------- XORSIMD check
if ((XORSIMD_REG != "XOR24_48_96") &&
(XORSIMD_REG != "XOR12")) begin
$display("Attribute Syntax Error : The attribute XORSIMD on %s instance %m is set to %s. Legal values for this attribute are XOR24_48_96 or XOR12.", MODULE_NAME, XORSIMD_REG);
attr_err = 1'b1;
end
//-------- ACASCREG check
if ((ACASCREG_REG != 0) && (ACASCREG_REG != 1) && (ACASCREG_REG != 2))
begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, ACASCREG_REG);
attr_err = 1'b1;
end
//-------- ADREG check
if ((ADREG_REG != 0) && (ADREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute ADREG on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, ADREG_REG);
attr_err = 1'b1;
end
//-------- ALUMODEREG check
if ((ALUMODEREG_REG != 0) && (ALUMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute ALUMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, ALUMODEREG_REG);
attr_err = 1'b1;
end
//-------- ACASCREG vs AREG check
case (AREG_REG)
0, 1 : if(AREG_REG != ACASCREG_REG) begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. ACASCREG has to be set to %d when attribute AREG = %d.", MODULE_NAME, ACASCREG_REG, AREG_REG, AREG_REG);
attr_err = 1'b1;
end
2 : if(ACASCREG_REG == 0) begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = %d.", MODULE_NAME, ACASCREG_REG, AREG_REG);
attr_err = 1'b1;
end
default : begin
$display("Attribute Syntax Error : The attribute AREG on %s instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", MODULE_NAME, AREG_REG);
attr_err = 1'b1;
end
endcase
//-------- BCASCREG check
if ((BCASCREG_REG != 0) && (BCASCREG_REG != 1) && (BCASCREG_REG != 2))
begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, BCASCREG_REG);
attr_err = 1'b1;
end
//-------- BCASCREG vs BREG check
case (BREG_REG)
0, 1 : if(BREG_REG != BCASCREG_REG) begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. BCASCREG has to be set to %d when attribute BREG = %d.", MODULE_NAME, BCASCREG_REG, BREG_REG, BREG_REG);
attr_err = 1'b1;
end
2 : if(BCASCREG_REG == 0) begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. BCASCREG must be set to either 2 or 1 when attribute BREG = %d.", MODULE_NAME, BCASCREG_REG, BREG_REG);
attr_err = 1'b1;
end
default : begin
$display("Attribute Syntax Error : The attribute BREG on %s instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", MODULE_NAME, BREG_REG);
attr_err = 1'b1;
end
endcase
//-------- CARRYINREG check
if ((CARRYINREG_REG != 0) && (CARRYINREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CARRYINREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CARRYINREG_REG);
attr_err = 1'b1;
end
//-------- CARRYINSELREG check
if ((CARRYINSELREG_REG != 0) && (CARRYINSELREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CARRYINSELREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CARRYINSELREG_REG);
attr_err = 1'b1;
end
//-------- CREG check
if ((CREG_REG != 0) && (CREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CREG_REG);
attr_err = 1'b1;
end
//-------- DREG check
if ((DREG_REG != 0) && (DREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute DREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DREG_REG);
attr_err = 1'b1;
end
//-------- INMODEREG check
if ((INMODEREG_REG != 0) && (INMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute INMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, INMODEREG_REG);
attr_err = 1'b1;
end
//-------- MREG check
if ((MREG_REG != 0) && (MREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute MREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, MREG_REG);
attr_err = 1'b1;
end
//-------- OPMODEREG check
if ((OPMODEREG_REG != 0) && (OPMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute OPMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, OPMODEREG_REG);
attr_err = 1'b1;
end
//-------- PREG check
if ((PREG_REG != 0) && (PREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute PREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, PREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
// DSP_ALU
//*** GLOBAL hidden GSR pin
// always @(glblGSR) begin
// if (glblGSR) begin
// assign CARRYIN_reg = 1'b0;
// assign CARRYINSEL_reg = 3'b0;
// assign OPMODE_reg = 7'b0;
// assign ALUMODE_reg = 4'b0;
// end
// else begin
// deassign CARRYIN_reg;
// deassign CARRYINSEL_reg;
// deassign OPMODE_reg;
// deassign ALUMODE_reg;
// end
// end
//*** W mux
always @ (OPMODE_mux[8:7] or P_FDBK_in or RND_BIN or C_DATA_in)
case (OPMODE_mux[8:7])
2'b00 : wmux <= 48'b0;
2'b01 : wmux <= P_FDBK_in;
2'b10 : wmux <= RND_BIN;
2'b11 : wmux <= C_DATA_in;
default : wmux <= {48{1'bx}};
endcase
//*** X mux
// To support MAC-cascade add multsignin to bit 1 of X
assign x_mac_cascd = (OPMODE_mux[6:4] == 3'b100) ? {{46{1'b0}},MULTSIGNIN_in,1'b0} : {48{1'b0}};
always @(U_DATA_in or P_FDBK_in or A_ALU_in or B_ALU_in or OPMODE_mux[1:0] or x_mac_cascd)
case (OPMODE_mux[1:0])
2'b00 : xmux <= x_mac_cascd;
2'b01 : xmux <= {{3{U_DATA_in[44]}}, U_DATA_in};
2'b10 : xmux <= P_FDBK_in;
2'b11 : xmux <= {A_ALU_in, B_ALU_in};
default : xmux <= {48{1'bx}};
endcase
//*** Y mux
always @(OPMODE_mux[3:2] or V_DATA_in or C_DATA_in)
case (OPMODE_mux[3:2])
2'b00 : ymux <= 48'b0;
2'b01 : ymux <= {{3{1'b0}}, V_DATA_in};
2'b10 : ymux <= {48{1'b1}};
2'b11 : ymux <= C_DATA_in;
default : ymux <= {48{1'bx}};
endcase
//*** Z mux
always @(OPMODE_mux[6:4] or PCIN_in or P_FDBK_in or C_DATA_in or P_FDBK_47_in)
casex (OPMODE_mux[6:4])
3'b000 : zmux <= 48'b0;
3'b001 : zmux <= PCIN_in;
3'b010 : zmux <= P_FDBK_in;
3'b011 : zmux <= C_DATA_in;
3'b100 : zmux <= P_FDBK_in;
3'b101 : zmux <= {{9{PCIN_in[47]}}, {8{PCIN_in[47]}}, PCIN_in[47:17]};
3'b11x : zmux <= {{9{P_FDBK_47_in}}, {8{P_FDBK_in[47]}}, P_FDBK_in[47:17]};
default : zmux <= {48{1'bx}};
endcase
//*** CARRYINSEL and OPMODE with 1 level of register
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
OPMODE_reg <= 9'b0;
end
else if (CECTRL_in) begin
OPMODE_reg <= OPMODE_in;
end
end
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
CARRYINSEL_reg <= 3'b0;
end
else if (CECTRL_in) begin
CARRYINSEL_reg <= CARRYINSEL_in;
end
end
assign CARRYINSEL_mux = (CARRYINSELREG_BIN == CARRYINSELREG_1) ?
CARRYINSEL_reg : CARRYINSEL_in;
assign OPMODE_mux = (OPMODEREG_BIN == OPMODEREG_1) ?
OPMODE_reg : OPMODE_in;
always @(CARRYINSEL_mux or CARRYCASCIN_in or MULTSIGNIN_in or OPMODE_mux) begin
if(CARRYINSEL_mux == 3'b010) begin
if(!((MULTSIGNIN_in === 1'bx) ||
((OPMODE_mux == 9'b001001000) && !(MULTSIGNIN_in === 1'bx)) ||
((MULTSIGNIN_in == 1'b0) && (CARRYCASCIN_in == 1'b0)))) begin
$display("DRC warning : CARRYCASCIN can only be used in the current %s instance %m if the previous %s is performing a two input ADD operation, or the current %s is configured in the MAC extend opmode 7'b1001000 at %.3f ns.", MODULE_NAME, MODULE_NAME, MODULE_NAME, $time);
// CR 619940 -- Enhanced DRC warning
$display("DRC warning note : The simulation model does not know the placement of the %s slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the %s slices and ensure that these warnings are not being breached\n", MODULE_NAME, MODULE_NAME);
end
end
end
//*** ALUMODE with 1 level of register
always @(posedge CLK_in) begin
if (RSTALUMODE_in || glblGSR)
ALUMODE_reg <= 4'b0;
else if (CEALUMODE_in)
ALUMODE_reg <= ALUMODE_in;
end
assign ALUMODE_mux = (ALUMODEREG_BIN == ALUMODEREG_1) ? ALUMODE_reg :
ALUMODE_in;
//------------------------------------------------------------------
//*** DRC for OPMODE
//------------------------------------------------------------------
// needs PREG from output block
// ~2000 lines code - skip for now - copy/rework from DSP48E1.
//--####################################################################
//--##### ALU #####
//--####################################################################
// ADDSUB block - first stage of ALU develops sums and carries for Final Adder
// Invert Z for subtract operation using alumode<0>
assign z_optinv = {48{ALUMODE_mux[0]}} ^ zmux;
// Add W, X, Y, Z carry-save style; basically full adder logic below
assign co = ((xmux & ymux)|(z_optinv & ymux)|(xmux & z_optinv));
// s has a fan-out of 2 (1) FA with W (2) second leg of XOR tree
assign s = (z_optinv^xmux^ymux);
// Mux S and CO to do 2 operands logic operations
// S = produce XOR/XNOR, NOT functions
// CO = produce AND/NAND, OR/NOR functions
assign comux = ALUMODE_mux[2] ? 0 : co;
assign smux = ALUMODE_mux[3] ? co : s;
// Carry mux to handle SIMD mode
// SIMD must be used here since addition of W requires carry propogation
assign comux4simd = {
comux[47:36],
comux[35]&&~USE_SIMD_BIN[2],
comux[34:24],
comux[23]&&~USE_SIMD_BIN[1],
comux[22:12],
comux[11]&&~USE_SIMD_BIN[0],
comux[10:0]
};
// FA to combine W-mux with s and co
// comux must be shifted to properly reflect carry operation
assign smux_w = smux ^ {comux4simd[46:0],1'b0} ^ wmux;
assign comux_w = ((smux & {comux4simd[46:0],1'b0}) |
(wmux & {comux4simd[46:0],1'b0}) |
(smux & wmux));
// alumode10 indicates a subtraction, used to correct carryout polarity
assign ALUMODE10_out = (ALUMODE_mux[0] & ALUMODE_mux[1]);
// prepare data for Final Adder
// a[0] is in fact the cin bit, adder inputs: a[48:1], b[47:0], cin= a[0]
assign a_int = {comux_w, cin};
assign b_int = smux_w;
// FINAL ADDER - second stage develops final sums and carries
assign s0 = a_int[11:0] + b_int[11:0];
// invert if alumode10
assign cout0 = ALUMODE10_out ^ (a_int[12] ^ s0[12] ^ comux[11]);
// internal carry is zero'd out on mc_simd == 1
assign intc1 = ~USE_SIMD_BIN[0] && s0[12];
// next lsb is zero'd out on mc_simd == 1
assign co12_lsb = ~USE_SIMD_BIN[0] && a_int[12];
//
assign s1 = {a_int[23:13],co12_lsb} + b_int[23:12] + intc1;
assign cout1 = ALUMODE10_out ^ (a_int[24] ^ s1[12] ^ comux[23]);
assign intc2 = ~USE_SIMD_BIN[1] && s1[12];
assign co24_lsb = ~USE_SIMD_BIN[1] && a_int[24];
//
assign s2 = {a_int[35:25],co24_lsb} + b_int[35:24] + intc2;
assign cout2 = ALUMODE10_out ^ (a_int[36] ^ s2[12] ^ comux[35]);
assign intc3 = ~USE_SIMD_BIN[2] && s2[12];
assign co36_lsb = ~USE_SIMD_BIN[2] && a_int[36];
//
assign s3 = {a_int[48:37],co36_lsb} + {comux4simd[47],b_int[47:36]} + intc3;
assign cout3 = ALUMODE10_out ^ s3[12];
// Not gated with alumode10 since used to propogate carry in wide multiply
// (above is true in Fuji - need to revisit for Olympus)
assign cout4 = s3[13];
// Wide XOR
assign xor_12a = USE_WIDEXOR_BIN ? ^s[5:0] : 0;
assign xor_12b = USE_WIDEXOR_BIN ? ^s[11:6] : 0;
assign xor_12c = USE_WIDEXOR_BIN ? ^s[17:12] : 0;
assign xor_12d = USE_WIDEXOR_BIN ? ^s[23:18] : 0;
assign xor_12e = USE_WIDEXOR_BIN ? ^s[29:24] : 0;
assign xor_12f = USE_WIDEXOR_BIN ? ^s[35:30] : 0;
assign xor_12g = USE_WIDEXOR_BIN ? ^s[41:36] : 0;
assign xor_12h = USE_WIDEXOR_BIN ? ^s[47:42] : 0;
assign xor_24a = xor_12a ^ xor_12b;
assign xor_24b = xor_12c ^ xor_12d;
assign xor_24c = xor_12e ^ xor_12f;
assign xor_24d = xor_12g ^ xor_12h;
assign xor_48a = xor_24a ^ xor_24b;
assign xor_48b = xor_24c ^ xor_24d;
assign xor_96 = xor_48a ^ xor_48b;
// "X" carryout for multiply and logic operations
assign mult_or_logic = ((OPMODE_mux[3:0] == 4'b0101) ||
(ALUMODE_mux[3:2] != 2'b00));
// allow carrycascout to not X in output atom
// assign cout_3 = mult_or_logic ? 1'bx : cout3;
assign cout_3 = cout3;
assign cout_2 = mult_or_logic ? 1'bx : cout2;
assign cout_1 = mult_or_logic ? 1'bx : cout1;
assign cout_0 = mult_or_logic ? 1'bx : cout0;
// drive signals to Output Atom
// turn SIMD back on
// assign COUT_out[3] = cout_3;
// assign COUT_out[2] = cout_2;
// assign COUT_out[1] = cout_1;
// assign COUT_out[0] = cout_0;
// from E1
// restored functionality
assign COUT_out[3] = cout_3;
assign COUT_out[2] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_2 : 1'bx;
assign COUT_out[1] = (USE_SIMD_BIN != USE_SIMD_ONE48 ) ? cout_1 : 1'bx;
assign COUT_out[0] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_0 : 1'bx;
assign MULTSIGN_ALU_out = s3[13]; // from alu rtl but doesn't seem right
// from E1
// assign MULTSIGN_ALU_out = (OPMODE_mux[6:4] == 3'b100) ? MULTSIGNIN_in :
// V_43_DATA_in;
assign alu_o = {s3[11:0],s2[11:0],s1[11:0],s0[11:0]};
assign ALU_OUT_out = ~ALUMODE_mux[1] ? alu_o : ~alu_o;
assign XOR_MX_out[0] = XORSIMD_BIN ? xor_12a : xor_24a;
assign XOR_MX_out[1] = XORSIMD_BIN ? xor_12b : xor_48a;
assign XOR_MX_out[2] = XORSIMD_BIN ? xor_12c : xor_24b;
assign XOR_MX_out[3] = XORSIMD_BIN ? xor_12d : xor_96;
assign XOR_MX_out[4] = XORSIMD_BIN ? xor_12e : xor_24c;
assign XOR_MX_out[5] = XORSIMD_BIN ? xor_12f : xor_48b;
assign XOR_MX_out[6] = XORSIMD_BIN ? xor_12g : xor_24d;
assign XOR_MX_out[7] = xor_12h;
//--########################### END ALU ################################
//*** CarryIn Mux and Register
//------- input 0
always @(posedge CLK_in) begin
if (RSTALLCARRYIN_in || glblGSR)
CARRYIN_reg <= 1'b0;
else if (CECARRYIN_in)
CARRYIN_reg <= CARRYIN_in;
end
assign CARRYIN_mux = (CARRYINREG_BIN == CARRYINREG_1) ? CARRYIN_reg : CARRYIN_in;
// INTERNAL CARRYIN REGISTER
assign c_mult = !(AMULT26_in^BMULT17_in);
assign ce_m_g = CEM_in & ~glblGSR; // & gwe
assign rst_carryin_g = RSTALLCARRYIN_in & ~glblGSR; // & gwe
assign d_carryin_int = ce_m_g ? c_mult : qmultcarryin;
// rstallcarryin is injected through data path
assign dr_carryin_int = rst_carryin_g ? 0 : d_carryin_int;
always @(posedge CLK_in) begin
if (glblGSR)
qmultcarryin <= 1'b0;
else
qmultcarryin <= dr_carryin_int;
end
// bypass register mux
assign multcarryin_data = (MREG_BIN == MREG_1) ? qmultcarryin : c_mult;
always @(CARRYINSEL_mux or CARRYIN_mux or PCIN_in[47] or CARRYCASCIN_in or CCOUT_in or P_FDBK_in[47] or multcarryin_data) begin
case (CARRYINSEL_mux)
3'b000 : cin_b <= ~CARRYIN_mux;
3'b001 : cin_b <= PCIN_in[47];
3'b010 : cin_b <= ~CARRYCASCIN_in;
3'b011 : cin_b <= ~PCIN_in[47];
3'b100 : cin_b <= ~CCOUT_in;
3'b101 : cin_b <= P_FDBK_in[47];
3'b110 : cin_b <= ~multcarryin_data;
3'b111 : cin_b <= ~P_FDBK_in[47];
default : cin_b <= 1'bx;
endcase
end
// disable carryin when performing logic operation
assign cin = (ALUMODE_mux[3] || ALUMODE_mux[2]) ? 1'b0 : ~cin_b;
// DSP_A_B_DATA
//*********************************************************
//*** Input register A with 2 level deep of registers
//*********************************************************
assign A_ACIN_mux = (A_INPUT_BIN == A_INPUT_CASCADE) ? ACIN_in : A_in;
// assign CLK_areg1 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_in;
// assign CLK_areg2 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_in;
always @(posedge CLK_areg1) begin
if (RSTA_in || glblGSR) A1_reg <= 30'b0;
else if (CEA1_in) A1_reg <= A_ACIN_mux;
end
assign A1_reg_mux = (AREG_BIN == AREG_2) ? A1_reg : A_ACIN_mux;
always @(posedge CLK_areg2) begin
if (RSTA_in || glblGSR) A2_reg <= 30'b0;
else if (CEA2_in) A2_reg <= A1_reg_mux;
end
assign A2_reg_mux = (AREG_BIN == AREG_0) ? A1_reg_mux : A2_reg;
// assumes encoding the same for ACASCREG and AREG
assign ACOUT_out = (ACASCREG_BIN == AREG_BIN) ? A2_reg_mux : A1_reg;
assign A1_DATA_out = A1_reg[26:0];
assign A2_DATA_out = A2_reg_mux[26:0];
assign A_ALU_out = A2_reg_mux;
//*********************************************************
//*** Input register B with 2 level deep of registers
//*********************************************************
assign B_BCIN_mux = (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : B_in;
// assign CLK_breg1 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_in;
// assign CLK_breg2 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_in;
always @(posedge CLK_breg1) begin
if (RSTB_in || glblGSR) B1_reg <= 18'b0;
else if (CEB1_in) B1_reg <= B_BCIN_mux;
end
assign B1_reg_mux = (BREG_BIN == BREG_2) ? B1_reg : B_BCIN_mux;
always @(posedge CLK_breg2) begin
if (RSTB_in || glblGSR) B2_reg <= 18'b0;
else if (CEB2_in) B2_reg <= B1_reg_mux;
end
assign B2_reg_mux = (BREG_BIN == BREG_0) ? B1_reg_mux : B2_reg;
// assumes encoding the same for BCASCREG and BREG
assign BCOUT_out = (BCASCREG_BIN == BREG_BIN) ? B2_reg_mux : B1_reg;
assign B1_DATA_out = B1_reg;
assign B2_DATA_out = B2_reg_mux;
assign B_ALU_out = B2_reg_mux;
// DSP_C_DATA
//*********************************************************
//*** Input register C with 1 level deep of register
//*********************************************************
// assign CLK_creg = (CREG_BIN == CREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_creg) begin
if (RSTC_in || glblGSR) C_reg <= 48'b0;
else if (CEC_in) C_reg <= C_in;
end
assign C_DATA_out = (CREG_BIN == CREG_1) ? C_reg : C_in;
// DSP_MULTIPLIER
assign a_mult_mux = (AMULTSEL_BIN == AMULTSEL_A) ? A2A1_in : AD_DATA_in;
assign b_mult_mux = (BMULTSEL_BIN == BMULTSEL_B) ? B2B1_in : AD_DATA_in;
assign AMULT26_out = a_mult_mux[26];
assign BMULT17_out = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U_out = {1'b1, mult[43:0] & ps_u_mask};
assign V_out = {~mult[44], mult[43:0] & ps_v_mask};
assign mult = (USE_MULT_BIN == USE_MULT_NONE) ? 45'b0 :
({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
// DSP_M_DATA
//*********************************************************
//*** Multiplier outputs U, V with 1 level deep of register
//*********************************************************
assign U_DATA_out = (MREG_BIN == MREG_1) ? U_DATA_reg : U_in;
assign V_DATA_out = (MREG_BIN == MREG_1) ? V_DATA_reg : V_in;
// assign CLK_mreg = (MREG_BIN == MREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_mreg) begin
if (RSTM_in || glblGSR) begin
U_DATA_reg <= 45'h100000000000;
V_DATA_reg <= 45'h100000000000;
end
else if (CEM_in) begin
U_DATA_reg <= U_in;
V_DATA_reg <= V_in;
end
end
// DSP_OUTPUT
//--####################################################################
//--##### Pattern Detector #####
//--####################################################################
// select pattern
assign the_pattern = (SEL_PATTERN_BIN == SEL_PATTERN_PATTERN) ? PATTERN_BIN : C_DATA_in;
// select mask
assign the_mask = (SEL_MASK_BIN == SEL_MASK_C) ? C_DATA_in :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE1) ? {~(C_DATA_in[46:0]),1'b0} :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE2) ? {~(C_DATA_in[45:0]),2'b0} :
MASK_BIN; // default or (SEL_MASK_BIN == SEL_MASK_MASK)
// always @(C_DATA_in or SEL_MASK_BIN or MASK_BIN) begin
// case(SEL_MASK_BIN)
// SEL_MASK_MASK : the_mask <= MASK_BIN;
// SEL_MASK_C : the_mask <= C_DATA_in;
// SEL_MASK_ROUNDING_MODE1 : the_mask <= ~(C_DATA_in << 1);
// SEL_MASK_ROUNDING_MODE2 : the_mask <= ~(C_DATA_in << 2);
// default : the_mask <= MASK_BIN;
// endcase
// end
//-- now do the pattern detection
assign pdet_o = &(~(the_pattern ^ ALU_OUT_in) | the_mask);
assign pdetb_o = &( (the_pattern ^ ALU_OUT_in) | the_mask);
assign PATTERN_DETECT_out = opmode_valid_flag_dou ? pdet_o_mux : 1'bx;
assign PATTERN_B_DETECT_out = opmode_valid_flag_dou ? pdetb_o_mux : 1'bx;
// assign CLK_preg = (PREG_BIN == PREG_1) ? CLK_in : 1'b0;
//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW
always @(posedge CLK_preg) begin
if(RSTP_in || glblGSR || the_auto_reset_patdet)
begin
pdet_o_reg1 <= 1'b0;
pdet_o_reg2 <= 1'b0;
pdetb_o_reg1 <= 1'b0;
pdetb_o_reg2 <= 1'b0;
end
else if(CEP_in)
begin
//-- the previous values are used in Underflow/Overflow
pdet_o_reg2 <= pdet_o_reg1;
pdet_o_reg1 <= pdet_o;
pdetb_o_reg2 <= pdetb_o_reg1;
pdetb_o_reg1 <= pdetb_o;
end
end
assign pdet_o_mux = (PREG_BIN == PREG_1) ? pdet_o_reg1 : pdet_o;
assign pdetb_o_mux = (PREG_BIN == PREG_1) ? pdetb_o_reg1 : pdetb_o;
assign overflow_data = (PREG_BIN == PREG_1) ? pdet_o_reg2 : pdet_o;
assign underflow_data = (PREG_BIN == PREG_1) ? pdetb_o_reg2 : pdetb_o;
//--####################################################################
//--##### AUTORESET_PATDET #####
//--####################################################################
assign auto_reset_pri = (AUTORESET_PRIORITY_BIN == AUTORESET_PRIORITY_RESET) || CEP_in;
assign the_auto_reset_patdet =
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_MATCH) ?
auto_reset_pri && pdet_o_mux :
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_NOT_MATCH) ?
auto_reset_pri && overflow_data && ~pdet_o_mux : 1'b0; // NO_RESET
//--####################################################################
//--#### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT, PCOUT and XOROUT reg #####
//--####################################################################
//*** register with 1 level of register
always @(posedge CLK_preg) begin
if(RSTP_in || glblGSR || the_auto_reset_patdet) begin
// COUT_reg <= 4'b0xxx;
COUT_reg <= 4'b0000;
ALUMODE10_reg <= 1'b0;
MULTSIGN_ALU_reg <= 1'b0;
ALU_OUT_reg <= 48'b0;
XOR_MX_reg <= 8'b0;
end
else if (CEP_in) begin
COUT_reg <= COUT_in;
ALUMODE10_reg <= ALUMODE10_in;
MULTSIGN_ALU_reg <= MULTSIGN_ALU_in;
ALU_OUT_reg <= ALU_OUT_in;
XOR_MX_reg <= XOR_MX_in;
end
end
assign CARRYOUT_out = (PREG_BIN == PREG_1) ? COUT_reg : COUT_in;
assign MULTSIGNOUT_out = (PREG_BIN == PREG_1) ? MULTSIGN_ALU_reg : MULTSIGN_ALU_in;
assign P_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
assign ALUMODE10_mux = (PREG_BIN == PREG_1) ? ALUMODE10_reg : ALUMODE10_in;
assign XOROUT_out = (PREG_BIN == PREG_1) ? XOR_MX_reg : XOR_MX_in;
assign CCOUT_FB_out = ALUMODE10_reg ^ COUT_reg[3];
assign CARRYCASCOUT_out = ALUMODE10_mux ^ CARRYOUT_out[3];
// assign P_FDBK_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
// assign P_FDBK_47_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg[47] : ALU_OUT_in[47];
assign P_FDBK_out = ALU_OUT_reg;
assign P_FDBK_47_out = ALU_OUT_reg[47];
assign PCOUT_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
//--####################################################################
//--##### Underflow / Overflow #####
//--####################################################################
assign OVERFLOW_out = ((USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ||
(PREG_BIN == PREG_1)) ?
~pdet_o_mux && ~pdetb_o_mux && overflow_data : 1'bx;
assign UNDERFLOW_out = ((USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ||
(PREG_BIN == PREG_1)) ?
~pdet_o_mux && ~pdetb_o_mux && underflow_data : 1'bx;
// DSP_PREADD
//*********************************************************
//*** Preaddsub AD
//*********************************************************
assign D_DATA_mux = INMODE_2_in ? D_DATA_in : 27'b0;
assign AD_out = ADDSUB_in ? (D_DATA_mux - PREADD_AB_in) : (D_DATA_mux + PREADD_AB_in);
// DSP_PREADD_DATA
assign a1a2_i_mux = INMODE_mux[0] ? A1_DATA_in : A2_DATA_in;
assign b1b2_i_mux = INMODE_mux[4] ? B1_DATA_in : B2_DATA_in;
assign A2A1_out = ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) ? 27'b0 : a1a2_i_mux;
assign B2B1_out = ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) ? 18'b0 : b1b2_i_mux;
assign ADDSUB_out = INMODE_mux[3];
assign INMODE_2_out = INMODE_mux[2];
// assign PREADD_AB_out = PREADDINSEL_BIN ? {9'b0, B2B1_out} : A2A1_out;
assign PREADD_AB_out = PREADDINSEL_BIN ? {{9{B2B1_out[17]}}, B2B1_out} : A2A1_out;
//*********************************************************
//********** INMODE signal registering ************
//*********************************************************
// new
// assign CLK_inmode = (INMODEREG_BIN == INMODEREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_inmode) begin
if (RSTINMODE_in || glblGSR)
INMODE_reg <= 5'b0;
else if (CEINMODE_in)
INMODE_reg <= INMODE_in;
end
assign INMODE_mux = (INMODEREG_BIN == INMODEREG_1) ? INMODE_reg : INMODE_in;
//*********************************************************
//*** Input register D with 1 level deep of register
//*********************************************************
// assign CLK_dreg = (DREG_BIN == DREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_dreg) begin
if (RSTD_in || glblGSR) D_DATA_reg <= 27'b0;
else if (CED_in) D_DATA_reg <= DIN_in;
end
assign D_DATA_out = (DREG_BIN == DREG_1) ? D_DATA_reg : DIN_in;
//*********************************************************
//*** Input register AD with 1 level deep of register
//*********************************************************
// assign CLK_adreg = (ADREG_BIN == ADREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_adreg) begin
if (RSTD_in || glblGSR) AD_DATA_reg <= 27'b0;
else if (CEAD_in) AD_DATA_reg <= AD_in;
end
assign AD_DATA_out = (ADREG_BIN == ADREG_1) ? AD_DATA_reg : AD_in;
always @ (OPMODE_mux) begin
if (((OPMODE_mux[1:0] == 2'b11) && (USE_MULT_BIN == USE_MULT_MULTIPLY)) &&
((AREG_BIN==AREG_0 && BREG_BIN==BREG_0 && MREG_BIN==MREG_0) ||
(AREG_BIN==AREG_0 && BREG_BIN==BREG_0 && PREG_BIN==PREG_0) ||
(MREG_BIN==MREG_0 && PREG_BIN==PREG_0)))
$display("OPMODE Input Warning : The OPMODE[1:0] (%b) to %s instance %m is invalid when using attributes USE_MULT = MULTIPLY and (A, B and M) or (A, B and P) or (M and P) are not REGISTERED at time %.3f ns. Please set USE_MULT to either NONE or DYNAMIC or REGISTER one of each group. (A or B) and (M or P) will satisfy the requirement.", OPMODE_mux[1:0], MODULE_NAME, $time/1000.0);
if((OPMODE_mux[3:0] == 4'b0101) &&
((USE_MULT_BIN == USE_MULT_NONE) || (USE_SIMD_BIN != USE_SIMD_ONE48)))
$display("OPMODE Input Warning : The OPMODE[3:0] (%b) to %s instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", OPMODE_mux[3:0], MODULE_NAME, $time/1000.0);
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_ALU.v 0000664 0000000 0000000 00000104760 12327044266 0022561 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_ALU.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 04/22/13 - 713695 - Zero mult result on USE_SIMD
// 04/22/13 - 713617 - CARRYCASCOUT behaviour
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 05/07/13 - 716896 - ALUMODE/OPMODE_INV_REG mis sized
// 05/07/13 - x_mac_cascd missing for sensitivity list.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_ALU
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ALUMODEREG = 1,
parameter integer CARRYINREG = 1,
parameter integer CARRYINSELREG = 1,
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000,
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000,
parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0,
parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0,
parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0,
parameter integer MREG = 1,
parameter integer OPMODEREG = 1,
parameter [47:0] RND = 48'h000000000000,
parameter USE_SIMD = "ONE48",
parameter USE_WIDEXOR = "FALSE",
parameter XORSIMD = "XOR24_48_96"
) (
output ALUMODE10,
output [47:0] ALU_OUT,
output [3:0] COUT,
output MULTSIGN_ALU,
output [7:0] XOR_MX,
input [3:0] ALUMODE,
input AMULT26,
input [29:0] A_ALU,
input BMULT17,
input [17:0] B_ALU,
input CARRYCASCIN,
input CARRYIN,
input [2:0] CARRYINSEL,
input CCOUT,
input CEALUMODE,
input CECARRYIN,
input CECTRL,
input CEM,
input CLK,
input [47:0] C_DATA,
input MULTSIGNIN,
input [8:0] OPMODE,
input [47:0] PCIN,
input [47:0] P_FDBK,
input P_FDBK_47,
input RSTALLCARRYIN,
input RSTALUMODE,
input RSTCTRL,
input [44:0] U_DATA,
input [44:0] V_DATA
);
// define constants
localparam MODULE_NAME = "DSP_ALU";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam ALUMODEREG_0 = 1;
localparam ALUMODEREG_1 = 0;
localparam CARRYINREG_0 = 1;
localparam CARRYINREG_1 = 0;
localparam CARRYINSELREG_0 = 1;
localparam CARRYINSELREG_1 = 0;
localparam MREG_0 = 1;
localparam MREG_1 = 0;
localparam OPMODEREG_0 = 1;
localparam OPMODEREG_1 = 0;
localparam USE_SIMD_FOUR12 = 7;
localparam USE_SIMD_ONE48 = 0;
localparam USE_SIMD_TWO24 = 2;
// USE_SIMD uses bits from actual encodings
localparam USE_WIDEXOR_FALSE = 0;
localparam USE_WIDEXOR_TRUE = 1;
localparam XORSIMD_XOR12 = 1;
localparam XORSIMD_XOR24_48_96 = 0;
`ifndef XIL_DR
localparam [0:0] ALUMODEREG_REG = ALUMODEREG;
localparam [0:0] CARRYINREG_REG = CARRYINREG;
localparam [0:0] CARRYINSELREG_REG = CARRYINSELREG;
localparam [3:0] IS_ALUMODE_INVERTED_REG = IS_ALUMODE_INVERTED;
localparam [0:0] IS_CARRYIN_INVERTED_REG = IS_CARRYIN_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [8:0] IS_OPMODE_INVERTED_REG = IS_OPMODE_INVERTED;
localparam [0:0] IS_RSTALLCARRYIN_INVERTED_REG = IS_RSTALLCARRYIN_INVERTED;
localparam [0:0] IS_RSTALUMODE_INVERTED_REG = IS_RSTALUMODE_INVERTED;
localparam [0:0] IS_RSTCTRL_INVERTED_REG = IS_RSTCTRL_INVERTED;
localparam [0:0] MREG_REG = MREG;
localparam [0:0] OPMODEREG_REG = OPMODEREG;
localparam [47:0] RND_REG = RND;
localparam [48:1] USE_SIMD_REG = USE_SIMD;
localparam [40:1] USE_WIDEXOR_REG = USE_WIDEXOR;
localparam [88:1] XORSIMD_REG = XORSIMD;
`endif
wire ALUMODEREG_BIN;
wire CARRYINREG_BIN;
wire CARRYINSELREG_BIN;
wire [3:0] IS_ALUMODE_INVERTED_BIN;
wire IS_CARRYIN_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire [8:0] IS_OPMODE_INVERTED_BIN;
wire IS_RSTALLCARRYIN_INVERTED_BIN;
wire IS_RSTALUMODE_INVERTED_BIN;
wire IS_RSTCTRL_INVERTED_BIN;
wire MREG_BIN;
wire OPMODEREG_BIN;
wire [47:0] RND_BIN;
wire [2:0] USE_SIMD_BIN;
wire USE_WIDEXOR_BIN;
wire XORSIMD_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_ALU_dr.v"
`endif
wire ALUMODE10_out;
wire MULTSIGN_ALU_out;
wire [3:0] COUT_out;
wire [47:0] ALU_OUT_out;
wire [7:0] XOR_MX_out;
wire ALUMODE10_delay;
wire MULTSIGN_ALU_delay;
wire [3:0] COUT_delay;
wire [47:0] ALU_OUT_delay;
wire [7:0] XOR_MX_delay;
wire AMULT26_in;
wire BMULT17_in;
wire CARRYCASCIN_in;
wire CARRYIN_in;
wire CCOUT_in;
wire CEALUMODE_in;
wire CECARRYIN_in;
wire CECTRL_in;
wire CEM_in;
wire CLK_in;
wire MULTSIGNIN_in;
wire P_FDBK_47_in;
wire RSTALLCARRYIN_in;
wire RSTALUMODE_in;
wire RSTCTRL_in;
wire [17:0] B_ALU_in;
wire [29:0] A_ALU_in;
wire [2:0] CARRYINSEL_in;
wire [3:0] ALUMODE_in;
wire [44:0] U_DATA_in;
wire [44:0] V_DATA_in;
wire [47:0] C_DATA_in;
wire [47:0] PCIN_in;
wire [47:0] P_FDBK_in;
wire [8:0] OPMODE_in;
wire AMULT26_delay;
wire BMULT17_delay;
wire CARRYCASCIN_delay;
wire CARRYIN_delay;
wire CCOUT_delay;
wire CEALUMODE_delay;
wire CECARRYIN_delay;
wire CECTRL_delay;
wire CEM_delay;
wire CLK_delay;
wire MULTSIGNIN_delay;
wire P_FDBK_47_delay;
wire RSTALLCARRYIN_delay;
wire RSTALUMODE_delay;
wire RSTCTRL_delay;
wire [17:0] B_ALU_delay;
wire [29:0] A_ALU_delay;
wire [2:0] CARRYINSEL_delay;
wire [3:0] ALUMODE_delay;
wire [44:0] U_DATA_delay;
wire [44:0] V_DATA_delay;
wire [47:0] C_DATA_delay;
wire [47:0] PCIN_delay;
wire [47:0] P_FDBK_delay;
wire [8:0] OPMODE_delay;
localparam MAX_ALU_FULL = 48;
localparam MAX_CARRYOUT = 4;
wire CARRYIN_mux;
reg CARRYIN_reg = 1'b0;
wire [3:0] ALUMODE_mux;
reg [3:0] ALUMODE_reg = 4'b0;
wire [2:0] CARRYINSEL_mux;
reg [2:0] CARRYINSEL_reg = 3'b0;
wire [8:0] OPMODE_mux;
reg [8:0] OPMODE_reg = 9'b0;
// wire [47:0] ALU_OUT_tmp;
wire [47:0] alu_o;
// wire u_43_data;
wire [47:0] x_mac_cascd;
reg [47:0] wmux = 48'b0;
reg [47:0] xmux = 48'b0;
reg [47:0] ymux = 48'b0;
reg [47:0] zmux = 48'b0;
wire [47:0] z_optinv;
wire cin;
reg cin_b = 1'b0;
wire rst_carryin_g;
reg qmultcarryin = 1'b0;
wire c_mult;
wire ce_m_g;
wire d_carryin_int;
wire dr_carryin_int;
wire multcarryin_data;
reg invalid_opmode = 1'b1;
reg opmode_valid_flag_dal = 1'b1; // used in OPMODE DRC
reg ping_opmode_drc_check = 1'b0;
wire [MAX_ALU_FULL-1:0] co;
wire [MAX_ALU_FULL-1:0] s;
wire [MAX_ALU_FULL-1:0] comux;
wire [MAX_ALU_FULL-1:0] comux_w;
wire [MAX_ALU_FULL-1:0] comux4simd;
wire [MAX_ALU_FULL-1:0] smux;
wire [MAX_ALU_FULL-1:0] smux_w;
// wire [MAX_CARRYOUT-1:0] carryout_o_hw;
// wire [MAX_CARRYOUT-1:0] carryout_o;
wire [48:0] a_int;
wire [47:0] b_int;
wire [12:0] s0;
wire cout0;
wire intc1;
wire co12_lsb;
wire [12:0] s1;
wire cout1;
wire intc2;
wire co24_lsb;
wire [12:0] s2;
wire cout2;
wire intc3;
wire co36_lsb;
wire [13:0] s3;
wire cout3;
wire cout4;
wire xor_12a;
wire xor_12b;
wire xor_12c;
wire xor_12d;
wire xor_12e;
wire xor_12f;
wire xor_12g;
wire xor_12h;
wire xor_24a;
wire xor_24b;
wire xor_24c;
wire xor_24d;
wire xor_48a;
wire xor_48b;
wire xor_96;
wire cout_0;
wire cout_1;
wire cout_2;
wire cout_3;
wire mult_or_logic;
// input output assignments
assign #(out_delay) ALUMODE10 = ALUMODE10_delay;
assign #(out_delay) ALU_OUT = ALU_OUT_delay;
// assign #(out_delay) COUT = ((OPMODE_mux[3:0] == 4'b0101) || (ALUMODE_mux[3:2] != 2'b00)) ? 4'hx : COUT_delay;
assign #(out_delay) COUT = COUT_delay;
assign #(out_delay) MULTSIGN_ALU = MULTSIGN_ALU_delay;
assign #(out_delay) XOR_MX = XOR_MX_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) ALUMODE_delay = ALUMODE;
assign #(in_delay) AMULT26_delay = AMULT26;
assign #(in_delay) BMULT17_delay = BMULT17;
assign #(in_delay) CARRYINSEL_delay = CARRYINSEL;
assign #(in_delay) CARRYIN_delay = CARRYIN;
assign #(in_delay) CEALUMODE_delay = CEALUMODE;
assign #(in_delay) CECARRYIN_delay = CECARRYIN;
assign #(in_delay) CECTRL_delay = CECTRL;
assign #(in_delay) CEM_delay = CEM;
assign #(in_delay) OPMODE_delay = OPMODE;
assign #(in_delay) RSTALLCARRYIN_delay = RSTALLCARRYIN;
assign #(in_delay) RSTALUMODE_delay = RSTALUMODE;
assign #(in_delay) RSTCTRL_delay = RSTCTRL;
`endif
// inputs with no timing checks
assign #(in_delay) A_ALU_delay = A_ALU;
assign #(in_delay) B_ALU_delay = B_ALU;
assign #(in_delay) CARRYCASCIN_delay = CARRYCASCIN;
assign #(in_delay) CCOUT_delay = CCOUT;
assign #(in_delay) C_DATA_delay = C_DATA;
assign #(in_delay) MULTSIGNIN_delay = MULTSIGNIN;
assign #(in_delay) PCIN_delay = PCIN;
assign #(in_delay) P_FDBK_47_delay = P_FDBK_47;
assign #(in_delay) P_FDBK_delay = P_FDBK;
assign #(in_delay) U_DATA_delay = U_DATA;
assign #(in_delay) V_DATA_delay = V_DATA;
assign ALUMODE10_delay = ALUMODE10_out;
assign ALU_OUT_delay = ALU_OUT_out;
// assign COUT_delay = ((OPMODE_mux[3:0] == 4'b0101) || (ALUMODE_mux[3:2] != 2'b00)) ? 4'hx : COUT_out;
assign COUT_delay = COUT_out;
assign MULTSIGN_ALU_delay = MULTSIGN_ALU_out;
assign XOR_MX_delay = XOR_MX_out;
assign AMULT26_in = AMULT26_delay;
assign A_ALU_in = A_ALU_delay;
assign BMULT17_in = BMULT17_delay;
assign B_ALU_in = B_ALU_delay;
assign CCOUT_in = CCOUT_delay;
assign P_FDBK_47_in = P_FDBK_47_delay;
assign P_FDBK_in = P_FDBK_delay;
assign U_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? U_DATA_delay : 45'h100000000000;
assign V_DATA_in = (USE_SIMD_BIN == USE_SIMD_ONE48) ? V_DATA_delay : 45'h100000000000;
assign ALUMODE_in = ALUMODE_delay ^ IS_ALUMODE_INVERTED_BIN;
assign CARRYCASCIN_in = CARRYCASCIN_delay;
assign CARRYINSEL_in = CARRYINSEL_delay;
assign CARRYIN_in = CARRYIN_delay ^ IS_CARRYIN_INVERTED_BIN;
assign CEALUMODE_in = CEALUMODE_delay;
assign CECARRYIN_in = CECARRYIN_delay;
assign CECTRL_in = CECTRL_delay;
assign CEM_in = CEM_delay;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign C_DATA_in = C_DATA_delay;
assign MULTSIGNIN_in = MULTSIGNIN_delay;
assign OPMODE_in = OPMODE_delay ^ IS_OPMODE_INVERTED_BIN;
assign PCIN_in = PCIN_delay;
assign RSTALLCARRYIN_in = RSTALLCARRYIN_delay ^ IS_RSTALLCARRYIN_INVERTED_BIN;
assign RSTALUMODE_in = RSTALUMODE_delay ^ IS_RSTALUMODE_INVERTED_BIN;
assign RSTCTRL_in = RSTCTRL_delay ^ IS_RSTCTRL_INVERTED_BIN;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign ALUMODEREG_BIN =
(ALUMODEREG_REG == 1) ? ALUMODEREG_1 :
(ALUMODEREG_REG == 0) ? ALUMODEREG_0 :
ALUMODEREG_1;
assign CARRYINREG_BIN =
(CARRYINREG_REG == 1) ? CARRYINREG_1 :
(CARRYINREG_REG == 0) ? CARRYINREG_0 :
CARRYINREG_1;
assign CARRYINSELREG_BIN =
(CARRYINSELREG_REG == 1) ? CARRYINSELREG_1 :
(CARRYINSELREG_REG == 0) ? CARRYINSELREG_0 :
CARRYINSELREG_1;
assign IS_ALUMODE_INVERTED_BIN = IS_ALUMODE_INVERTED_REG;
assign IS_CARRYIN_INVERTED_BIN = IS_CARRYIN_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_OPMODE_INVERTED_BIN = IS_OPMODE_INVERTED_REG;
assign IS_RSTALLCARRYIN_INVERTED_BIN = IS_RSTALLCARRYIN_INVERTED_REG;
assign IS_RSTALUMODE_INVERTED_BIN = IS_RSTALUMODE_INVERTED_REG;
assign IS_RSTCTRL_INVERTED_BIN = IS_RSTCTRL_INVERTED_REG;
assign MREG_BIN =
(MREG_REG == 1) ? MREG_1 :
(MREG_REG == 0) ? MREG_0 :
MREG_1;
assign OPMODEREG_BIN =
(OPMODEREG_REG == 1) ? OPMODEREG_1 :
(OPMODEREG_REG == 0) ? OPMODEREG_0 :
OPMODEREG_1;
assign RND_BIN = RND_REG;
assign USE_SIMD_BIN =
(USE_SIMD_REG == "ONE48") ? USE_SIMD_ONE48 :
(USE_SIMD_REG == "FOUR12") ? USE_SIMD_FOUR12 :
(USE_SIMD_REG == "TWO24") ? USE_SIMD_TWO24 :
USE_SIMD_ONE48;
assign USE_WIDEXOR_BIN =
(USE_WIDEXOR_REG == "FALSE") ? USE_WIDEXOR_FALSE :
(USE_WIDEXOR_REG == "TRUE") ? USE_WIDEXOR_TRUE :
USE_WIDEXOR_FALSE;
assign XORSIMD_BIN =
(XORSIMD_REG == "XOR24_48_96") ? XORSIMD_XOR24_48_96 :
(XORSIMD_REG == "XOR12") ? XORSIMD_XOR12 :
XORSIMD_XOR24_48_96;
always @ (trig_attr) begin
#1;
//-------- USE_SIMD check
if ((USE_SIMD_REG != "ONE48") &&
(USE_SIMD_REG != "FOUR12") &&
(USE_SIMD_REG != "TWO24")) begin
$display("Attribute Syntax Error : The attribute USE_SIMD on %s instance %m is set to %s. Legal values for this attribute are ONE48, FOUR12 or TWO24.", MODULE_NAME, USE_SIMD_REG);
attr_err = 1'b1;
end
//-------- USE_WIDEXOR check
if ((USE_WIDEXOR_REG != "FALSE") &&
(USE_WIDEXOR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute USE_WIDEXOR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, USE_WIDEXOR_REG);
attr_err = 1'b1;
end
//-------- XORSIMD check
if ((XORSIMD_REG != "XOR24_48_96") &&
(XORSIMD_REG != "XOR12")) begin
$display("Attribute Syntax Error : The attribute XORSIMD on %s instance %m is set to %s. Legal values for this attribute are XOR24_48_96 or XOR12.", MODULE_NAME, XORSIMD_REG);
attr_err = 1'b1;
end
//-------- ALUMODEREG check
if ((ALUMODEREG_REG != 0) && (ALUMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute ALUMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, ALUMODEREG_REG);
attr_err = 1'b1;
end
//-------- CARRYINREG check
if ((CARRYINREG_REG != 0) && (CARRYINREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CARRYINREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CARRYINREG_REG);
attr_err = 1'b1;
end
//-------- CARRYINSELREG check
if ((CARRYINSELREG_REG != 0) && (CARRYINSELREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CARRYINSELREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CARRYINSELREG_REG);
attr_err = 1'b1;
end
//-------- MREG check
if ((MREG_REG != 0) && (MREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute MREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, MREG_REG);
attr_err = 1'b1;
end
//-------- OPMODEREG check
if ((OPMODEREG_REG != 0) && (OPMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute OPMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, OPMODEREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
//*** GLOBAL hidden GSR pin
// always @(glblGSR) begin
// if (glblGSR) begin
// assign CARRYIN_reg = 1'b0;
// assign CARRYINSEL_reg = 3'b0;
// assign OPMODE_reg = 7'b0;
// assign ALUMODE_reg = 4'b0;
// end
// else begin
// deassign CARRYIN_reg;
// deassign CARRYINSEL_reg;
// deassign OPMODE_reg;
// deassign ALUMODE_reg;
// end
// end
//*** W mux
always @ (OPMODE_mux[8:7] or P_FDBK_in or RND_BIN or C_DATA_in)
case (OPMODE_mux[8:7])
2'b00 : wmux <= 48'b0;
2'b01 : wmux <= P_FDBK_in;
2'b10 : wmux <= RND_BIN;
2'b11 : wmux <= C_DATA_in;
default : wmux <= {48{1'bx}};
endcase
//*** X mux
// To support MAC-cascade add multsignin to bit 1 of X
assign x_mac_cascd = (OPMODE_mux[6:4] == 3'b100) ? {{46{1'b0}},MULTSIGNIN_in,1'b0} : {48{1'b0}};
always @(U_DATA_in or P_FDBK_in or A_ALU_in or B_ALU_in or OPMODE_mux[1:0] or x_mac_cascd)
case (OPMODE_mux[1:0])
2'b00 : xmux <= x_mac_cascd;
2'b01 : xmux <= {{3{U_DATA_in[44]}}, U_DATA_in};
2'b10 : xmux <= P_FDBK_in;
2'b11 : xmux <= {A_ALU_in, B_ALU_in};
default : xmux <= {48{1'bx}};
endcase
//*** Y mux
always @(OPMODE_mux[3:2] or V_DATA_in or C_DATA_in)
case (OPMODE_mux[3:2])
2'b00 : ymux <= 48'b0;
2'b01 : ymux <= {{3{1'b0}}, V_DATA_in};
2'b10 : ymux <= {48{1'b1}};
2'b11 : ymux <= C_DATA_in;
default : ymux <= {48{1'bx}};
endcase
//*** Z mux
always @(OPMODE_mux[6:4] or PCIN_in or P_FDBK_in or C_DATA_in or P_FDBK_47_in)
casex (OPMODE_mux[6:4])
3'b000 : zmux <= 48'b0;
3'b001 : zmux <= PCIN_in;
3'b010 : zmux <= P_FDBK_in;
3'b011 : zmux <= C_DATA_in;
3'b100 : zmux <= P_FDBK_in;
3'b101 : zmux <= {{9{PCIN_in[47]}}, {8{PCIN_in[47]}}, PCIN_in[47:17]};
3'b11x : zmux <= {{9{P_FDBK_47_in}}, {8{P_FDBK_in[47]}}, P_FDBK_in[47:17]};
default : zmux <= {48{1'bx}};
endcase
//*** CARRYINSEL and OPMODE with 1 level of register
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
OPMODE_reg <= 9'b0;
end
else if (CECTRL_in) begin
OPMODE_reg <= OPMODE_in;
end
end
always @(posedge CLK_in) begin
if (RSTCTRL_in || glblGSR) begin
CARRYINSEL_reg <= 3'b0;
end
else if (CECTRL_in) begin
CARRYINSEL_reg <= CARRYINSEL_in;
end
end
assign CARRYINSEL_mux = (CARRYINSELREG_BIN == CARRYINSELREG_1) ?
CARRYINSEL_reg : CARRYINSEL_in;
assign OPMODE_mux = (OPMODEREG_BIN == OPMODEREG_1) ?
OPMODE_reg : OPMODE_in;
always @(CARRYINSEL_mux or CARRYCASCIN_in or MULTSIGNIN_in or OPMODE_mux) begin
if(CARRYINSEL_mux == 3'b010) begin
if(!((MULTSIGNIN_in === 1'bx) ||
((OPMODE_mux == 9'b001001000) && !(MULTSIGNIN_in === 1'bx)) ||
((MULTSIGNIN_in == 1'b0) && (CARRYCASCIN_in == 1'b0)))) begin
$display("DRC warning : CARRYCASCIN can only be used in the current %s instance %m if the previous %s is performing a two input ADD operation, or the current %s is configured in the MAC extend opmode 7'b1001000 at %.3f ns.", MODULE_NAME, MODULE_NAME, MODULE_NAME, $time);
// CR 619940 -- Enhanced DRC warning
$display("DRC warning note : The simulation model does not know the placement of the %s slices used, so it cannot fully confirm the above warning. It is necessary to view the placement of the %s slices and ensure that these warnings are not being breached\n", MODULE_NAME, MODULE_NAME);
end
end
end
//*** ALUMODE with 1 level of register
always @(posedge CLK_in) begin
if (RSTALUMODE_in || glblGSR)
ALUMODE_reg <= 4'b0;
else if (CEALUMODE_in)
ALUMODE_reg <= ALUMODE_in;
end
assign ALUMODE_mux = (ALUMODEREG_BIN == ALUMODEREG_1) ? ALUMODE_reg :
ALUMODE_in;
//------------------------------------------------------------------
//*** DRC for OPMODE
//------------------------------------------------------------------
// needs PREG from output block
// ~2000 lines code - skip for now - copy/rework from DSP48E1.
//--####################################################################
//--##### ALU #####
//--####################################################################
// ADDSUB block - first stage of ALU develops sums and carries for Final Adder
// Invert Z for subtract operation using alumode<0>
assign z_optinv = {48{ALUMODE_mux[0]}} ^ zmux;
// Add W, X, Y, Z carry-save style; basically full adder logic below
assign co = ((xmux & ymux)|(z_optinv & ymux)|(xmux & z_optinv));
// s has a fan-out of 2 (1) FA with W (2) second leg of XOR tree
assign s = (z_optinv^xmux^ymux);
// Mux S and CO to do 2 operands logic operations
// S = produce XOR/XNOR, NOT functions
// CO = produce AND/NAND, OR/NOR functions
assign comux = ALUMODE_mux[2] ? 0 : co;
assign smux = ALUMODE_mux[3] ? co : s;
// Carry mux to handle SIMD mode
// SIMD must be used here since addition of W requires carry propogation
assign comux4simd = {
comux[47:36],
comux[35]&&~USE_SIMD_BIN[2],
comux[34:24],
comux[23]&&~USE_SIMD_BIN[1],
comux[22:12],
comux[11]&&~USE_SIMD_BIN[0],
comux[10:0]
};
// FA to combine W-mux with s and co
// comux must be shifted to properly reflect carry operation
assign smux_w = smux ^ {comux4simd[46:0],1'b0} ^ wmux;
assign comux_w = ((smux & {comux4simd[46:0],1'b0}) |
(wmux & {comux4simd[46:0],1'b0}) |
(smux & wmux));
// alumode10 indicates a subtraction, used to correct carryout polarity
assign ALUMODE10_out = (ALUMODE_mux[0] & ALUMODE_mux[1]);
// prepare data for Final Adder
// a[0] is in fact the cin bit, adder inputs: a[48:1], b[47:0], cin= a[0]
assign a_int = {comux_w, cin};
assign b_int = smux_w;
// FINAL ADDER - second stage develops final sums and carries
assign s0 = a_int[11:0] + b_int[11:0];
// invert if alumode10
assign cout0 = ALUMODE10_out ^ (a_int[12] ^ s0[12] ^ comux[11]);
// internal carry is zero'd out on mc_simd == 1
assign intc1 = ~USE_SIMD_BIN[0] && s0[12];
// next lsb is zero'd out on mc_simd == 1
assign co12_lsb = ~USE_SIMD_BIN[0] && a_int[12];
//
assign s1 = {a_int[23:13],co12_lsb} + b_int[23:12] + intc1;
assign cout1 = ALUMODE10_out ^ (a_int[24] ^ s1[12] ^ comux[23]);
assign intc2 = ~USE_SIMD_BIN[1] && s1[12];
assign co24_lsb = ~USE_SIMD_BIN[1] && a_int[24];
//
assign s2 = {a_int[35:25],co24_lsb} + b_int[35:24] + intc2;
assign cout2 = ALUMODE10_out ^ (a_int[36] ^ s2[12] ^ comux[35]);
assign intc3 = ~USE_SIMD_BIN[2] && s2[12];
assign co36_lsb = ~USE_SIMD_BIN[2] && a_int[36];
//
assign s3 = {a_int[48:37],co36_lsb} + {comux4simd[47],b_int[47:36]} + intc3;
assign cout3 = ALUMODE10_out ^ s3[12];
// Not gated with alumode10 since used to propogate carry in wide multiply
// (above is true in Fuji - need to revisit for Olympus)
assign cout4 = s3[13];
// Wide XOR
assign xor_12a = USE_WIDEXOR_BIN ? ^s[5:0] : 0;
assign xor_12b = USE_WIDEXOR_BIN ? ^s[11:6] : 0;
assign xor_12c = USE_WIDEXOR_BIN ? ^s[17:12] : 0;
assign xor_12d = USE_WIDEXOR_BIN ? ^s[23:18] : 0;
assign xor_12e = USE_WIDEXOR_BIN ? ^s[29:24] : 0;
assign xor_12f = USE_WIDEXOR_BIN ? ^s[35:30] : 0;
assign xor_12g = USE_WIDEXOR_BIN ? ^s[41:36] : 0;
assign xor_12h = USE_WIDEXOR_BIN ? ^s[47:42] : 0;
assign xor_24a = xor_12a ^ xor_12b;
assign xor_24b = xor_12c ^ xor_12d;
assign xor_24c = xor_12e ^ xor_12f;
assign xor_24d = xor_12g ^ xor_12h;
assign xor_48a = xor_24a ^ xor_24b;
assign xor_48b = xor_24c ^ xor_24d;
assign xor_96 = xor_48a ^ xor_48b;
// "X" carryout for multiply and logic operations
assign mult_or_logic = ((OPMODE_mux[3:0] == 4'b0101) ||
(ALUMODE_mux[3:2] != 2'b00));
// allow carrycascout to not X in output atom
// assign cout_3 = mult_or_logic ? 1'bx : cout3;
assign cout_3 = cout3;
assign cout_2 = mult_or_logic ? 1'bx : cout2;
assign cout_1 = mult_or_logic ? 1'bx : cout1;
assign cout_0 = mult_or_logic ? 1'bx : cout0;
// drive signals to Output Atom
// turn SIMD back on
// assign COUT_out[3] = cout_3;
// assign COUT_out[2] = cout_2;
// assign COUT_out[1] = cout_1;
// assign COUT_out[0] = cout_0;
// from E1
// restored functionality
assign COUT_out[3] = cout_3;
assign COUT_out[2] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_2 : 1'bx;
assign COUT_out[1] = (USE_SIMD_BIN != USE_SIMD_ONE48 ) ? cout_1 : 1'bx;
assign COUT_out[0] = (USE_SIMD_BIN == USE_SIMD_FOUR12) ? cout_0 : 1'bx;
assign MULTSIGN_ALU_out = s3[13]; // from alu rtl but doesn't seem right
// from E1
// assign MULTSIGN_ALU_out = (OPMODE_mux[6:4] == 3'b100) ? MULTSIGNIN_in :
// V_43_DATA_in;
assign alu_o = {s3[11:0],s2[11:0],s1[11:0],s0[11:0]};
assign ALU_OUT_out = ~ALUMODE_mux[1] ? alu_o : ~alu_o;
assign XOR_MX_out[0] = XORSIMD_BIN ? xor_12a : xor_24a;
assign XOR_MX_out[1] = XORSIMD_BIN ? xor_12b : xor_48a;
assign XOR_MX_out[2] = XORSIMD_BIN ? xor_12c : xor_24b;
assign XOR_MX_out[3] = XORSIMD_BIN ? xor_12d : xor_96;
assign XOR_MX_out[4] = XORSIMD_BIN ? xor_12e : xor_24c;
assign XOR_MX_out[5] = XORSIMD_BIN ? xor_12f : xor_48b;
assign XOR_MX_out[6] = XORSIMD_BIN ? xor_12g : xor_24d;
assign XOR_MX_out[7] = xor_12h;
//--########################### END ALU ################################
//*** CarryIn Mux and Register
//------- input 0
always @(posedge CLK_in) begin
if (RSTALLCARRYIN_in || glblGSR)
CARRYIN_reg <= 1'b0;
else if (CECARRYIN_in)
CARRYIN_reg <= CARRYIN_in;
end
assign CARRYIN_mux = (CARRYINREG_BIN == CARRYINREG_1) ? CARRYIN_reg : CARRYIN_in;
// INTERNAL CARRYIN REGISTER
assign c_mult = !(AMULT26_in^BMULT17_in);
assign ce_m_g = CEM_in & ~glblGSR; // & gwe
assign rst_carryin_g = RSTALLCARRYIN_in & ~glblGSR; // & gwe
assign d_carryin_int = ce_m_g ? c_mult : qmultcarryin;
// rstallcarryin is injected through data path
assign dr_carryin_int = rst_carryin_g ? 0 : d_carryin_int;
always @(posedge CLK_in) begin
if (glblGSR)
qmultcarryin <= 1'b0;
else
qmultcarryin <= dr_carryin_int;
end
// bypass register mux
assign multcarryin_data = (MREG_BIN == MREG_1) ? qmultcarryin : c_mult;
always @(CARRYINSEL_mux or CARRYIN_mux or PCIN_in[47] or CARRYCASCIN_in or CCOUT_in or P_FDBK_in[47] or multcarryin_data) begin
case (CARRYINSEL_mux)
3'b000 : cin_b <= ~CARRYIN_mux;
3'b001 : cin_b <= PCIN_in[47];
3'b010 : cin_b <= ~CARRYCASCIN_in;
3'b011 : cin_b <= ~PCIN_in[47];
3'b100 : cin_b <= ~CCOUT_in;
3'b101 : cin_b <= P_FDBK_in[47];
3'b110 : cin_b <= ~multcarryin_data;
3'b111 : cin_b <= ~P_FDBK_in[47];
default : cin_b <= 1'bx;
endcase
end
// disable carryin when performing logic operation
assign cin = (ALUMODE_mux[3] || ALUMODE_mux[2]) ? 1'b0 : ~cin_b;
specify
(ALUMODE *> ALUMODE10) = (0:0:0, 0:0:0);
(ALUMODE *> ALU_OUT) = (0:0:0, 0:0:0);
(ALUMODE *> COUT) = (0:0:0, 0:0:0);
(ALUMODE *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(ALUMODE *> XOR_MX) = (0:0:0, 0:0:0);
(AMULT26 *> ALU_OUT) = (0:0:0, 0:0:0);
(AMULT26 *> COUT) = (0:0:0, 0:0:0);
(AMULT26 => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(A_ALU *> ALU_OUT) = (0:0:0, 0:0:0);
(A_ALU *> COUT) = (0:0:0, 0:0:0);
(A_ALU *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(A_ALU *> XOR_MX) = (0:0:0, 0:0:0);
(BMULT17 *> ALU_OUT) = (0:0:0, 0:0:0);
(BMULT17 *> COUT) = (0:0:0, 0:0:0);
(BMULT17 => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(B_ALU *> ALU_OUT) = (0:0:0, 0:0:0);
(B_ALU *> COUT) = (0:0:0, 0:0:0);
(B_ALU *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(B_ALU *> XOR_MX) = (0:0:0, 0:0:0);
(CARRYCASCIN *> ALU_OUT) = (0:0:0, 0:0:0);
(CARRYCASCIN *> COUT) = (0:0:0, 0:0:0);
(CARRYCASCIN => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(CARRYIN *> ALU_OUT) = (0:0:0, 0:0:0);
(CARRYIN *> COUT) = (0:0:0, 0:0:0);
(CARRYIN => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(CARRYINSEL *> ALU_OUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> COUT) = (0:0:0, 0:0:0);
(CARRYINSEL *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(CCOUT *> ALU_OUT) = (0:0:0, 0:0:0);
(CCOUT *> COUT) = (0:0:0, 0:0:0);
(CCOUT => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(CLK *> ALU_OUT) = (0:0:0, 0:0:0);
(CLK *> COUT) = (0:0:0, 0:0:0);
(CLK *> XOR_MX) = (0:0:0, 0:0:0);
(CLK => ALUMODE10) = (0:0:0, 0:0:0);
(CLK => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(C_DATA *> ALU_OUT) = (0:0:0, 0:0:0);
(C_DATA *> COUT) = (0:0:0, 0:0:0);
(C_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(C_DATA *> XOR_MX) = (0:0:0, 0:0:0);
(MULTSIGNIN *> ALU_OUT) = (0:0:0, 0:0:0);
(MULTSIGNIN *> COUT) = (0:0:0, 0:0:0);
(MULTSIGNIN => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(OPMODE *> ALU_OUT) = (0:0:0, 0:0:0);
(OPMODE *> COUT) = (0:0:0, 0:0:0);
(OPMODE *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(OPMODE *> XOR_MX) = (0:0:0, 0:0:0);
(PCIN *> ALU_OUT) = (0:0:0, 0:0:0);
(PCIN *> COUT) = (0:0:0, 0:0:0);
(PCIN *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(PCIN *> XOR_MX) = (0:0:0, 0:0:0);
(P_FDBK *> ALU_OUT) = (0:0:0, 0:0:0);
(P_FDBK *> COUT) = (0:0:0, 0:0:0);
(P_FDBK *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(P_FDBK *> XOR_MX) = (0:0:0, 0:0:0);
(P_FDBK_47 *> ALU_OUT) = (0:0:0, 0:0:0);
(P_FDBK_47 *> COUT) = (0:0:0, 0:0:0);
(P_FDBK_47 *> XOR_MX) = (0:0:0, 0:0:0);
(P_FDBK_47 => MULTSIGN_ALU) = (0:0:0, 0:0:0);
(U_DATA *> ALU_OUT) = (0:0:0, 0:0:0);
(U_DATA *> COUT) = (0:0:0, 0:0:0);
(U_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
(V_DATA *> ALU_OUT) = (0:0:0, 0:0:0);
(V_DATA *> COUT) = (0:0:0, 0:0:0);
(V_DATA *> MULTSIGN_ALU) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE_delay);
$setuphold (negedge CLK, negedge AMULT26, 0:0:0, 0:0:0, notifier,,, CLK_delay, AMULT26_delay);
$setuphold (negedge CLK, negedge BMULT17, 0:0:0, 0:0:0, notifier,,, CLK_delay, BMULT17_delay);
$setuphold (negedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYIN_delay);
$setuphold (negedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYINSEL_delay);
$setuphold (negedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEALUMODE_delay);
$setuphold (negedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECARRYIN_delay);
$setuphold (negedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECTRL_delay);
$setuphold (negedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (negedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, OPMODE_delay);
$setuphold (negedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALLCARRYIN_delay);
$setuphold (negedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALUMODE_delay);
$setuphold (negedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTCTRL_delay);
$setuphold (negedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE_delay);
$setuphold (negedge CLK, posedge AMULT26, 0:0:0, 0:0:0, notifier,,, CLK_delay, AMULT26_delay);
$setuphold (negedge CLK, posedge BMULT17, 0:0:0, 0:0:0, notifier,,, CLK_delay, BMULT17_delay);
$setuphold (negedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYIN_delay);
$setuphold (negedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYINSEL_delay);
$setuphold (negedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEALUMODE_delay);
$setuphold (negedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECARRYIN_delay);
$setuphold (negedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECTRL_delay);
$setuphold (negedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (negedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, OPMODE_delay);
$setuphold (negedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALLCARRYIN_delay);
$setuphold (negedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALUMODE_delay);
$setuphold (negedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTCTRL_delay);
$setuphold (posedge CLK, negedge ALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE_delay);
$setuphold (posedge CLK, negedge AMULT26, 0:0:0, 0:0:0, notifier,,, CLK_delay, AMULT26_delay);
$setuphold (posedge CLK, negedge BMULT17, 0:0:0, 0:0:0, notifier,,, CLK_delay, BMULT17_delay);
$setuphold (posedge CLK, negedge CARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYIN_delay);
$setuphold (posedge CLK, negedge CARRYINSEL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYINSEL_delay);
$setuphold (posedge CLK, negedge CEALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEALUMODE_delay);
$setuphold (posedge CLK, negedge CECARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECARRYIN_delay);
$setuphold (posedge CLK, negedge CECTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECTRL_delay);
$setuphold (posedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (posedge CLK, negedge OPMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, OPMODE_delay);
$setuphold (posedge CLK, negedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALLCARRYIN_delay);
$setuphold (posedge CLK, negedge RSTALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALUMODE_delay);
$setuphold (posedge CLK, negedge RSTCTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTCTRL_delay);
$setuphold (posedge CLK, posedge ALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE_delay);
$setuphold (posedge CLK, posedge AMULT26, 0:0:0, 0:0:0, notifier,,, CLK_delay, AMULT26_delay);
$setuphold (posedge CLK, posedge BMULT17, 0:0:0, 0:0:0, notifier,,, CLK_delay, BMULT17_delay);
$setuphold (posedge CLK, posedge CARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYIN_delay);
$setuphold (posedge CLK, posedge CARRYINSEL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CARRYINSEL_delay);
$setuphold (posedge CLK, posedge CEALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEALUMODE_delay);
$setuphold (posedge CLK, posedge CECARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECARRYIN_delay);
$setuphold (posedge CLK, posedge CECTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, CECTRL_delay);
$setuphold (posedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (posedge CLK, posedge OPMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, OPMODE_delay);
$setuphold (posedge CLK, posedge RSTALLCARRYIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALLCARRYIN_delay);
$setuphold (posedge CLK, posedge RSTALUMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTALUMODE_delay);
$setuphold (posedge CLK, posedge RSTCTRL, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTCTRL_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_A_B_DATA.v 0000664 0000000 0000000 00000042735 12327044266 0023355 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_A_B_DATA.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 03/06/13 - 701316 - A_B_reg no clk when REG=0
// 04/08/13 - 710304 - AREG, BREG, ACASCREG and BCASCREG dynamic registers mis sized.
// 04/22/13 - 714213 - ACOUT, BCOUT wrong logic
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 05/07/13 - 716896 - AREG, BREG, ACASCREG and BCASCREG localparams mis sized.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_A_B_DATA
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ACASCREG = 1,
parameter integer AREG = 1,
parameter A_INPUT = "DIRECT",
parameter integer BCASCREG = 1,
parameter integer BREG = 1,
parameter B_INPUT = "DIRECT",
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RSTA_INVERTED = 1'b0,
parameter [0:0] IS_RSTB_INVERTED = 1'b0
) (
output [26:0] A1_DATA,
output [26:0] A2_DATA,
output [29:0] ACOUT,
output [29:0] A_ALU,
output [17:0] B1_DATA,
output [17:0] B2_DATA,
output [17:0] BCOUT,
output [17:0] B_ALU,
input [29:0] A,
input [29:0] ACIN,
input [17:0] B,
input [17:0] BCIN,
input CEA1,
input CEA2,
input CEB1,
input CEB2,
input CLK,
input RSTA,
input RSTB
);
// define constants
localparam MODULE_NAME = "DSP_A_B_DATA";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
// logic depends on ACASCREG, AREG encoding the same
localparam ACASCREG_0 = 1;
localparam ACASCREG_1 = 0;
localparam ACASCREG_2 = 2;
localparam AREG_0 = 1;
localparam AREG_1 = 0;
localparam AREG_2 = 2;
localparam A_INPUT_CASCADE = 1;
localparam A_INPUT_DIRECT = 0;
localparam BCASCREG_0 = 1;
localparam BCASCREG_1 = 0;
localparam BCASCREG_2 = 2;
localparam BREG_0 = 1;
localparam BREG_1 = 0;
localparam BREG_2 = 2;
localparam B_INPUT_CASCADE = 1;
localparam B_INPUT_DIRECT = 0;
`ifndef XIL_DR
localparam [1:0] ACASCREG_REG = ACASCREG;
localparam [1:0] AREG_REG = AREG;
localparam [56:1] A_INPUT_REG = A_INPUT;
localparam [1:0] BCASCREG_REG = BCASCREG;
localparam [1:0] BREG_REG = BREG;
localparam [56:1] B_INPUT_REG = B_INPUT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RSTA_INVERTED_REG = IS_RSTA_INVERTED;
localparam [0:0] IS_RSTB_INVERTED_REG = IS_RSTB_INVERTED;
`endif
wire [1:0] ACASCREG_BIN;
wire [1:0] AREG_BIN;
wire A_INPUT_BIN;
wire [1:0] BCASCREG_BIN;
wire [1:0] BREG_BIN;
wire B_INPUT_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RSTA_INVERTED_BIN;
wire IS_RSTB_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_A_B_DATA_dr.v"
`endif
wire [17:0] B1_DATA_out;
wire [17:0] B2_DATA_out;
wire [17:0] BCOUT_out;
wire [17:0] B_ALU_out;
wire [26:0] A1_DATA_out;
wire [26:0] A2_DATA_out;
wire [29:0] ACOUT_out;
wire [29:0] A_ALU_out;
wire [17:0] B1_DATA_delay;
wire [17:0] B2_DATA_delay;
wire [17:0] BCOUT_delay;
wire [17:0] B_ALU_delay;
wire [26:0] A1_DATA_delay;
wire [26:0] A2_DATA_delay;
wire [29:0] ACOUT_delay;
wire [29:0] A_ALU_delay;
wire CEA1_in;
wire CEA2_in;
wire CEB1_in;
wire CEB2_in;
wire CLK_in;
wire RSTA_in;
wire RSTB_in;
wire [17:0] BCIN_in;
wire [17:0] B_in;
wire [29:0] ACIN_in;
wire [29:0] A_in;
wire CEA1_delay;
wire CEA2_delay;
wire CEB1_delay;
wire CEB2_delay;
wire CLK_delay;
wire RSTA_delay;
wire RSTB_delay;
wire [17:0] BCIN_delay;
wire [17:0] B_delay;
wire [29:0] ACIN_delay;
wire [29:0] A_delay;
wire [29:0] A_ACIN_mux;
wire [29:0] A1_reg_mux;
wire [29:0] A2_reg_mux;
reg [29:0] A1_reg = 30'b0;
reg [29:0] A2_reg = 30'b0;
wire [17:0] B_BCIN_mux;
wire [17:0] B1_reg_mux;
wire [17:0] B2_reg_mux;
reg [17:0] B1_reg = 18'b0;
reg [17:0] B2_reg = 18'b0;
wire CLK_areg1;
wire CLK_areg2;
wire CLK_breg1;
wire CLK_breg2;
// input output assignments
assign #(out_delay) A1_DATA = A1_DATA_delay;
assign #(out_delay) A2_DATA = A2_DATA_delay;
assign #(out_delay) ACOUT = ACOUT_delay;
assign #(out_delay) A_ALU = A_ALU_delay;
assign #(out_delay) B1_DATA = B1_DATA_delay;
assign #(out_delay) B2_DATA = B2_DATA_delay;
assign #(out_delay) BCOUT = BCOUT_delay;
assign #(out_delay) B_ALU = B_ALU_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) ACIN_delay = ACIN;
assign #(in_delay) A_delay = A;
assign #(in_delay) BCIN_delay = BCIN;
assign #(in_delay) B_delay = B;
assign #(in_delay) CEA1_delay = CEA1;
assign #(in_delay) CEA2_delay = CEA2;
assign #(in_delay) CEB1_delay = CEB1;
assign #(in_delay) CEB2_delay = CEB2;
assign #(in_delay) RSTA_delay = RSTA;
assign #(in_delay) RSTB_delay = RSTB;
`endif
assign A1_DATA_delay = A1_DATA_out;
assign A2_DATA_delay = A2_DATA_out;
assign ACOUT_delay = ACOUT_out;
assign A_ALU_delay = A_ALU_out;
assign B1_DATA_delay = B1_DATA_out;
assign B2_DATA_delay = B2_DATA_out;
assign BCOUT_delay = BCOUT_out;
assign B_ALU_delay = B_ALU_out;
assign ACIN_in = ACIN_delay;
assign A_in = A_delay;
assign BCIN_in = BCIN_delay;
assign B_in = B_delay;
assign CEA1_in = CEA1_delay;
assign CEA2_in = CEA2_delay;
assign CEB1_in = CEB1_delay;
assign CEB2_in = CEB2_delay;
assign CLK_areg1 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_areg2 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_breg1 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_breg2 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign RSTA_in = RSTA_delay ^ IS_RSTA_INVERTED_BIN;
assign RSTB_in = RSTB_delay ^ IS_RSTB_INVERTED_BIN;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign ACASCREG_BIN =
(ACASCREG_REG == 1) ? ACASCREG_1 :
(ACASCREG_REG == 0) ? ACASCREG_0 :
(ACASCREG_REG == 2) ? ACASCREG_2 :
ACASCREG_1;
assign AREG_BIN =
(AREG_REG == 1) ? AREG_1 :
(AREG_REG == 0) ? AREG_0 :
(AREG_REG == 2) ? AREG_2 :
AREG_1;
assign A_INPUT_BIN =
(A_INPUT_REG == "DIRECT") ? A_INPUT_DIRECT :
(A_INPUT_REG == "CASCADE") ? A_INPUT_CASCADE :
A_INPUT_DIRECT;
assign BCASCREG_BIN =
(BCASCREG_REG == 1) ? BCASCREG_1 :
(BCASCREG_REG == 0) ? BCASCREG_0 :
(BCASCREG_REG == 2) ? BCASCREG_2 :
BCASCREG_1;
assign BREG_BIN =
(BREG_REG == 1) ? BREG_1 :
(BREG_REG == 0) ? BREG_0 :
(BREG_REG == 2) ? BREG_2 :
BREG_1;
assign B_INPUT_BIN =
(B_INPUT_REG == "DIRECT") ? B_INPUT_DIRECT :
(B_INPUT_REG == "CASCADE") ? B_INPUT_CASCADE :
B_INPUT_DIRECT;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RSTA_INVERTED_BIN = IS_RSTA_INVERTED_REG;
assign IS_RSTB_INVERTED_BIN = IS_RSTB_INVERTED_REG;
always @ (trig_attr) begin
#1;
//-------- A_INPUT check
if ((A_INPUT_REG != "DIRECT") &&
(A_INPUT_REG != "CASCADE")) begin
$display("Attribute Syntax Error : The attribute A_INPUT on %s instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", MODULE_NAME, A_INPUT_REG);
attr_err = 1'b1;
end
//-------- B_INPUT check
if ((B_INPUT_REG != "DIRECT") &&
(B_INPUT_REG != "CASCADE")) begin
$display("Attribute Syntax Error : The attribute B_INPUT on %s instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", MODULE_NAME, B_INPUT_REG);
attr_err = 1'b1;
end
//-------- ACASCREG check
if ((ACASCREG_REG != 0) && (ACASCREG_REG != 1) && (ACASCREG_REG != 2))
begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, ACASCREG_REG);
attr_err = 1'b1;
end
//-------- ACASCREG vs AREG check
case (AREG_REG)
0, 1 : if(AREG_REG != ACASCREG_REG) begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. ACASCREG has to be set to %d when attribute AREG = %d.", MODULE_NAME, ACASCREG_REG, AREG_REG, AREG_REG);
attr_err = 1'b1;
end
2 : if(ACASCREG_REG == 0) begin
$display("Attribute Syntax Error : The attribute ACASCREG on %s instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = %d.", MODULE_NAME, ACASCREG_REG, AREG_REG);
attr_err = 1'b1;
end
default : begin
$display("Attribute Syntax Error : The attribute AREG on %s instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", MODULE_NAME, AREG_REG);
attr_err = 1'b1;
end
endcase
//-------- BCASCREG check
if ((BCASCREG_REG != 0) && (BCASCREG_REG != 1) && (BCASCREG_REG != 2))
begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, BCASCREG_REG);
attr_err = 1'b1;
end
//-------- BCASCREG vs BREG check
case (BREG_REG)
0, 1 : if(BREG_REG != BCASCREG_REG) begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. BCASCREG has to be set to %d when attribute BREG = %d.", MODULE_NAME, BCASCREG_REG, BREG_REG, BREG_REG);
attr_err = 1'b1;
end
2 : if(BCASCREG_REG == 0) begin
$display("Attribute Syntax Error : The attribute BCASCREG on %s instance %m is set to %d. BCASCREG must be set to either 2 or 1 when attribute BREG = %d.", MODULE_NAME, BCASCREG_REG, BREG_REG);
attr_err = 1'b1;
end
default : begin
$display("Attribute Syntax Error : The attribute BREG on %s instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", MODULE_NAME, BREG_REG);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) $finish;
end
//*********************************************************
//*** Input register A with 2 level deep of registers
//*********************************************************
assign A_ACIN_mux = (A_INPUT_BIN == A_INPUT_CASCADE) ? ACIN_in : A_in;
// assign CLK_areg1 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_in;
// assign CLK_areg2 = (AREG_BIN == AREG_0) ? 1'b0 : CLK_in;
always @(posedge CLK_areg1) begin
if (RSTA_in || glblGSR) A1_reg <= 30'b0;
else if (CEA1_in) A1_reg <= A_ACIN_mux;
end
assign A1_reg_mux = (AREG_BIN == AREG_2) ? A1_reg : A_ACIN_mux;
always @(posedge CLK_areg2) begin
if (RSTA_in || glblGSR) A2_reg <= 30'b0;
else if (CEA2_in) A2_reg <= A1_reg_mux;
end
assign A2_reg_mux = (AREG_BIN == AREG_0) ? A1_reg_mux : A2_reg;
// assumes encoding the same for ACASCREG and AREG
assign ACOUT_out = (ACASCREG_BIN == AREG_BIN) ? A2_reg_mux : A1_reg;
assign A1_DATA_out = A1_reg[26:0];
assign A2_DATA_out = A2_reg_mux[26:0];
assign A_ALU_out = A2_reg_mux;
//*********************************************************
//*** Input register B with 2 level deep of registers
//*********************************************************
assign B_BCIN_mux = (B_INPUT_BIN == B_INPUT_CASCADE) ? BCIN_in : B_in;
// assign CLK_breg1 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_in;
// assign CLK_breg2 = (BREG_BIN == BREG_0) ? 1'b0 : CLK_in;
always @(posedge CLK_breg1) begin
if (RSTB_in || glblGSR) B1_reg <= 18'b0;
else if (CEB1_in) B1_reg <= B_BCIN_mux;
end
assign B1_reg_mux = (BREG_BIN == BREG_2) ? B1_reg : B_BCIN_mux;
always @(posedge CLK_breg2) begin
if (RSTB_in || glblGSR) B2_reg <= 18'b0;
else if (CEB2_in) B2_reg <= B1_reg_mux;
end
assign B2_reg_mux = (BREG_BIN == BREG_0) ? B1_reg_mux : B2_reg;
// assumes encoding the same for BCASCREG and BREG
assign BCOUT_out = (BCASCREG_BIN == BREG_BIN) ? B2_reg_mux : B1_reg;
assign B1_DATA_out = B1_reg;
assign B2_DATA_out = B2_reg_mux;
assign B_ALU_out = B2_reg_mux;
specify
(A *> A2_DATA) = (0:0:0, 0:0:0);
(A *> ACOUT) = (0:0:0, 0:0:0);
(A *> A_ALU) = (0:0:0, 0:0:0);
(ACIN *> A2_DATA) = (0:0:0, 0:0:0);
(ACIN *> ACOUT) = (0:0:0, 0:0:0);
(ACIN *> A_ALU) = (0:0:0, 0:0:0);
(B *> B2_DATA) = (0:0:0, 0:0:0);
(B *> BCOUT) = (0:0:0, 0:0:0);
(B *> B_ALU) = (0:0:0, 0:0:0);
(BCIN *> B2_DATA) = (0:0:0, 0:0:0);
(BCIN *> BCOUT) = (0:0:0, 0:0:0);
(BCIN *> B_ALU) = (0:0:0, 0:0:0);
(CLK *> A1_DATA) = (0:0:0, 0:0:0);
(CLK *> A2_DATA) = (0:0:0, 0:0:0);
(CLK *> ACOUT) = (0:0:0, 0:0:0);
(CLK *> A_ALU) = (0:0:0, 0:0:0);
(CLK *> B1_DATA) = (0:0:0, 0:0:0);
(CLK *> B2_DATA) = (0:0:0, 0:0:0);
(CLK *> BCOUT) = (0:0:0, 0:0:0);
(CLK *> B_ALU) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge A, 0:0:0, 0:0:0, notifier,,, CLK_delay, A_delay);
$setuphold (negedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, ACIN_delay);
$setuphold (negedge CLK, negedge B, 0:0:0, 0:0:0, notifier,,, CLK_delay, B_delay);
$setuphold (negedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, BCIN_delay);
$setuphold (negedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA1_delay);
$setuphold (negedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA2_delay);
$setuphold (negedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB1_delay);
$setuphold (negedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB2_delay);
$setuphold (negedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTA_delay);
$setuphold (negedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTB_delay);
$setuphold (negedge CLK, posedge A, 0:0:0, 0:0:0, notifier,,, CLK_delay, A_delay);
$setuphold (negedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, ACIN_delay);
$setuphold (negedge CLK, posedge B, 0:0:0, 0:0:0, notifier,,, CLK_delay, B_delay);
$setuphold (negedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, BCIN_delay);
$setuphold (negedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA1_delay);
$setuphold (negedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA2_delay);
$setuphold (negedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB1_delay);
$setuphold (negedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB2_delay);
$setuphold (negedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTA_delay);
$setuphold (negedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTB_delay);
$setuphold (posedge CLK, negedge A, 0:0:0, 0:0:0, notifier,,, CLK_delay, A_delay);
$setuphold (posedge CLK, negedge ACIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, ACIN_delay);
$setuphold (posedge CLK, negedge B, 0:0:0, 0:0:0, notifier,,, CLK_delay, B_delay);
$setuphold (posedge CLK, negedge BCIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, BCIN_delay);
$setuphold (posedge CLK, negedge CEA1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA1_delay);
$setuphold (posedge CLK, negedge CEA2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA2_delay);
$setuphold (posedge CLK, negedge CEB1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB1_delay);
$setuphold (posedge CLK, negedge CEB2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB2_delay);
$setuphold (posedge CLK, negedge RSTA, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTA_delay);
$setuphold (posedge CLK, negedge RSTB, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTB_delay);
$setuphold (posedge CLK, posedge A, 0:0:0, 0:0:0, notifier,,, CLK_delay, A_delay);
$setuphold (posedge CLK, posedge ACIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, ACIN_delay);
$setuphold (posedge CLK, posedge B, 0:0:0, 0:0:0, notifier,,, CLK_delay, B_delay);
$setuphold (posedge CLK, posedge BCIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, BCIN_delay);
$setuphold (posedge CLK, posedge CEA1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA1_delay);
$setuphold (posedge CLK, posedge CEA2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEA2_delay);
$setuphold (posedge CLK, posedge CEB1, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB1_delay);
$setuphold (posedge CLK, posedge CEB2, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEB2_delay);
$setuphold (posedge CLK, posedge RSTA, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTA_delay);
$setuphold (posedge CLK, posedge RSTB, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTB_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_C_DATA.v 0000664 0000000 0000000 00000012340 12327044266 0023103 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_C_DATA.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_C_DATA
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CREG = 1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RSTC_INVERTED = 1'b0
) (
output [47:0] C_DATA,
input [47:0] C,
input CEC,
input CLK,
input RSTC
);
// define constants
localparam MODULE_NAME = "DSP_C_DATA";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CREG_0 = 1;
localparam CREG_1 = 0;
`ifndef XIL_DR
localparam [0:0] CREG_REG = CREG;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RSTC_INVERTED_REG = IS_RSTC_INVERTED;
`endif
wire CREG_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RSTC_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_C_DATA_dr.v"
`endif
wire [47:0] C_DATA_out;
wire [47:0] C_DATA_delay;
wire CEC_in;
wire CLK_in;
wire RSTC_in;
wire [47:0] C_in;
wire CEC_delay;
wire CLK_delay;
wire RSTC_delay;
wire [47:0] C_delay;
reg [47:0] C_reg = 48'b0;
wire CLK_creg;
// input output assignments
assign #(out_delay) C_DATA = C_DATA_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CEC_delay = CEC;
assign #(in_delay) C_delay = C;
assign #(in_delay) RSTC_delay = RSTC;
`endif
assign C_DATA_delay = C_DATA_out;
assign CEC_in = CEC_delay;
assign CLK_creg = (CREG_BIN == CREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign C_in = C_delay;
assign RSTC_in = RSTC_delay ^ IS_RSTC_INVERTED_BIN;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign CREG_BIN =
(CREG_REG == 1) ? CREG_1 :
(CREG_REG == 0) ? CREG_0 :
CREG_1;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RSTC_INVERTED_BIN = IS_RSTC_INVERTED_REG;
always @ (trig_attr) begin
#1;
//-------- CREG check
if ((CREG_REG != 0) && (CREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute CREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, CREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
//*********************************************************
//*** Input register C with 1 level deep of register
//*********************************************************
// assign CLK_creg = (CREG_BIN == CREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_creg) begin
if (RSTC_in || glblGSR) C_reg <= 48'b0;
else if (CEC_in) C_reg <= C_in;
end
assign C_DATA_out = (CREG_BIN == CREG_1) ? C_reg : C_in;
specify
(C *> C_DATA) = (0:0:0, 0:0:0);
(CLK *> C_DATA) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge CLK, negedge C, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_delay);
$setuphold (negedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEC_delay);
$setuphold (negedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTC_delay);
$setuphold (negedge CLK, posedge C, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_delay);
$setuphold (negedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEC_delay);
$setuphold (negedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTC_delay);
$setuphold (posedge CLK, negedge C, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_delay);
$setuphold (posedge CLK, negedge CEC, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEC_delay);
$setuphold (posedge CLK, negedge RSTC, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTC_delay);
$setuphold (posedge CLK, posedge C, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_delay);
$setuphold (posedge CLK, posedge CEC, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEC_delay);
$setuphold (posedge CLK, posedge RSTC, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTC_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_MULTIPLIER.v 0000664 0000000 0000000 00000013530 12327044266 0023620 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_MULTIPLIER.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_MULTIPLIER
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter USE_MULT = "MULTIPLY"
) (
output AMULT26,
output BMULT17,
output [44:0] U,
output [44:0] V,
input [26:0] A2A1,
input [26:0] AD_DATA,
input [17:0] B2B1
);
// define constants
localparam MODULE_NAME = "DSP_MULTIPLIER";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
`ifndef XIL_DR
localparam [16:1] AMULTSEL_REG = AMULTSEL;
localparam [16:1] BMULTSEL_REG = BMULTSEL;
localparam [64:1] USE_MULT_REG = USE_MULT;
`endif
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire [1:0] USE_MULT_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_MULTIPLIER_dr.v"
`endif
wire AMULT26_out;
wire BMULT17_out;
wire [44:0] U_out;
wire [44:0] V_out;
wire AMULT26_delay;
wire BMULT17_delay;
wire [44:0] U_delay;
wire [44:0] V_delay;
wire [17:0] B2B1_in;
wire [26:0] A2A1_in;
wire [26:0] AD_DATA_in;
wire [17:0] B2B1_delay;
wire [26:0] A2A1_delay;
wire [26:0] AD_DATA_delay;
wire [17:0] b_mult_mux;
wire [26:0] a_mult_mux;
wire [44:0] mult;
reg [43:0] ps_u_mask = 44'h55555555555;
reg [43:0] ps_v_mask = 44'haaaaaaaaaaa;
// input output assignments
assign #(out_delay) AMULT26 = AMULT26_delay;
assign #(out_delay) BMULT17 = BMULT17_delay;
assign #(out_delay) U = U_delay;
assign #(out_delay) V = V_delay;
// inputs with no timing checks
assign #(in_delay) A2A1_delay = A2A1;
assign #(in_delay) AD_DATA_delay = AD_DATA;
assign #(in_delay) B2B1_delay = B2B1;
assign AMULT26_delay = AMULT26_out;
assign BMULT17_delay = BMULT17_out;
assign U_delay = U_out;
assign V_delay = V_out;
assign A2A1_in = A2A1_delay;
assign AD_DATA_in = AD_DATA_delay;
assign B2B1_in = B2B1_delay;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
always @ (trig_attr) begin
#1;
//-------- AMULTSEL check
if ((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute AMULTSEL on %s instance %m is set to %s. Legal values for this attribute are A or AD.", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
//-------- BMULTSEL check
if ((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute BMULTSEL on %s instance %m is set to %s. Legal values for this attribute are B or AD.", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
//-------- USE_MULT check
if ((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE")) begin
$display("Attribute Syntax Error : The attribute USE_MULT on %s instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign a_mult_mux = (AMULTSEL_BIN == AMULTSEL_A) ? A2A1_in : AD_DATA_in;
assign b_mult_mux = (BMULTSEL_BIN == BMULTSEL_B) ? B2B1_in : AD_DATA_in;
assign AMULT26_out = a_mult_mux[26];
assign BMULT17_out = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U_out = {1'b1, mult[43:0] & ps_u_mask};
assign V_out = {~mult[44], mult[43:0] & ps_v_mask};
assign mult = (USE_MULT_BIN == USE_MULT_NONE) ? 45'b0 :
({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
specify
(A2A1 *> AMULT26) = (0:0:0, 0:0:0);
(A2A1 *> U) = (0:0:0, 0:0:0);
(A2A1 *> V) = (0:0:0, 0:0:0);
(AD_DATA *> AMULT26) = (0:0:0, 0:0:0);
(AD_DATA *> BMULT17) = (0:0:0, 0:0:0);
(AD_DATA *> U) = (0:0:0, 0:0:0);
(AD_DATA *> V) = (0:0:0, 0:0:0);
(B2B1 *> BMULT17) = (0:0:0, 0:0:0);
(B2B1 *> U) = (0:0:0, 0:0:0);
(B2B1 *> V) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_M_DATA.v 0000664 0000000 0000000 00000014410 12327044266 0023115 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_M_DATA.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 04/22/13 - 713695 - Zero mult result on USE_SIMD
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_M_DATA
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RSTM_INVERTED = 1'b0,
parameter integer MREG = 1
) (
output [44:0] U_DATA,
output [44:0] V_DATA,
input CEM,
input CLK,
input RSTM,
input [44:0] U,
input [44:0] V
);
// define constants
localparam MODULE_NAME = "DSP_M_DATA";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam MREG_0 = 1;
localparam MREG_1 = 0;
`ifndef XIL_DR
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RSTM_INVERTED_REG = IS_RSTM_INVERTED;
localparam [0:0] MREG_REG = MREG;
`endif
wire IS_CLK_INVERTED_BIN;
wire IS_RSTM_INVERTED_BIN;
wire MREG_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_M_DATA_dr.v"
`endif
wire [44:0] U_DATA_out;
wire [44:0] V_DATA_out;
wire [44:0] U_DATA_delay;
wire [44:0] V_DATA_delay;
wire CEM_in;
wire CLK_in;
wire RSTM_in;
wire [44:0] U_in;
wire [44:0] V_in;
wire CEM_delay;
wire CLK_delay;
wire RSTM_delay;
wire [44:0] U_delay;
wire [44:0] V_delay;
reg [44:0] U_DATA_reg = 45'h100000000000;
reg [44:0] V_DATA_reg = 45'h100000000000;
wire CLK_mreg;
// input output assignments
assign #(out_delay) U_DATA = U_DATA_delay;
assign #(out_delay) V_DATA = V_DATA_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CEM_delay = CEM;
assign #(in_delay) RSTM_delay = RSTM;
assign #(in_delay) U_delay = U;
assign #(in_delay) V_delay = V;
`endif
assign U_DATA_delay = U_DATA_out;
assign V_DATA_delay = V_DATA_out;
assign CEM_in = CEM_delay;
assign CLK_mreg = (MREG_BIN == MREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign RSTM_in = RSTM_delay ^ IS_RSTM_INVERTED_BIN;
assign U_in = U_delay;
assign V_in = V_delay;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RSTM_INVERTED_BIN = IS_RSTM_INVERTED_REG;
assign MREG_BIN =
(MREG_REG == 1) ? MREG_1 :
(MREG_REG == 0) ? MREG_0 :
MREG_1;
always @ (trig_attr) begin
#1;
//-------- MREG check
if ((MREG_REG != 0) && (MREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute MREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, MREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
//*********************************************************
//*** Multiplier outputs U, V with 1 level deep of register
//*********************************************************
assign U_DATA_out = (MREG_BIN == MREG_1) ? U_DATA_reg : U_in;
assign V_DATA_out = (MREG_BIN == MREG_1) ? V_DATA_reg : V_in;
// assign CLK_mreg = (MREG_BIN == MREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_mreg) begin
if (RSTM_in || glblGSR) begin
U_DATA_reg <= 45'h100000000000;
V_DATA_reg <= 45'h100000000000;
end
else if (CEM_in) begin
U_DATA_reg <= U_in;
V_DATA_reg <= V_in;
end
end
specify
(CLK *> U_DATA) = (0:0:0, 0:0:0);
(CLK *> V_DATA) = (0:0:0, 0:0:0);
(U *> U_DATA) = (0:0:0, 0:0:0);
(V *> V_DATA) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (negedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTM_delay);
$setuphold (negedge CLK, negedge U, 0:0:0, 0:0:0, notifier,,, CLK_delay, U_delay);
$setuphold (negedge CLK, negedge V, 0:0:0, 0:0:0, notifier,,, CLK_delay, V_delay);
$setuphold (negedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (negedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTM_delay);
$setuphold (negedge CLK, posedge U, 0:0:0, 0:0:0, notifier,,, CLK_delay, U_delay);
$setuphold (negedge CLK, posedge V, 0:0:0, 0:0:0, notifier,,, CLK_delay, V_delay);
$setuphold (posedge CLK, negedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (posedge CLK, negedge RSTM, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTM_delay);
$setuphold (posedge CLK, negedge U, 0:0:0, 0:0:0, notifier,,, CLK_delay, U_delay);
$setuphold (posedge CLK, negedge V, 0:0:0, 0:0:0, notifier,,, CLK_delay, V_delay);
$setuphold (posedge CLK, posedge CEM, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEM_delay);
$setuphold (posedge CLK, posedge RSTM, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTM_delay);
$setuphold (posedge CLK, posedge U, 0:0:0, 0:0:0, notifier,,, CLK_delay, U_delay);
$setuphold (posedge CLK, posedge V, 0:0:0, 0:0:0, notifier,,, CLK_delay, V_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_OUTPUT.v 0000664 0000000 0000000 00000052076 12327044266 0023202 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_OUTPUT.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 04/03/13 - yaml update
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 04/23/13 - 713706 - change P_PDBK connection
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_OUTPUT
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter AUTORESET_PATDET = "NO_RESET",
parameter AUTORESET_PRIORITY = "RESET",
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RSTP_INVERTED = 1'b0,
parameter [47:0] MASK = 48'h3FFFFFFFFFFF,
parameter [47:0] PATTERN = 48'h000000000000,
parameter integer PREG = 1,
parameter SEL_MASK = "MASK",
parameter SEL_PATTERN = "PATTERN",
parameter USE_PATTERN_DETECT = "NO_PATDET"
) (
output CARRYCASCOUT,
output [3:0] CARRYOUT,
output CCOUT_FB,
output MULTSIGNOUT,
output OVERFLOW,
output [47:0] P,
output PATTERN_B_DETECT,
output PATTERN_DETECT,
output [47:0] PCOUT,
output [47:0] P_FDBK,
output P_FDBK_47,
output UNDERFLOW,
output [7:0] XOROUT,
input ALUMODE10,
input [47:0] ALU_OUT,
input CEP,
input CLK,
input [3:0] COUT,
input [47:0] C_DATA,
input MULTSIGN_ALU,
input RSTP,
input [7:0] XOR_MX
);
// define constants
localparam MODULE_NAME = "DSP_OUTPUT";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam AUTORESET_PATDET_NO_RESET = 0;
localparam AUTORESET_PATDET_RESET_MATCH = 1;
localparam AUTORESET_PATDET_RESET_NOT_MATCH = 2;
localparam AUTORESET_PRIORITY_CEP = 1;
localparam AUTORESET_PRIORITY_RESET = 0;
localparam PREG_0 = 1;
localparam PREG_1 = 0;
localparam SEL_MASK_C = 1;
localparam SEL_MASK_MASK = 0;
localparam SEL_MASK_ROUNDING_MODE1 = 2;
localparam SEL_MASK_ROUNDING_MODE2 = 3;
localparam SEL_PATTERN_C = 1;
localparam SEL_PATTERN_PATTERN = 0;
localparam USE_PATTERN_DETECT_NO_PATDET = 0;
localparam USE_PATTERN_DETECT_PATDET = 1;
`ifndef XIL_DR
localparam [120:1] AUTORESET_PATDET_REG = AUTORESET_PATDET;
localparam [40:1] AUTORESET_PRIORITY_REG = AUTORESET_PRIORITY;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RSTP_INVERTED_REG = IS_RSTP_INVERTED;
localparam [47:0] MASK_REG = MASK;
localparam [47:0] PATTERN_REG = PATTERN;
localparam [0:0] PREG_REG = PREG;
localparam [112:1] SEL_MASK_REG = SEL_MASK;
localparam [56:1] SEL_PATTERN_REG = SEL_PATTERN;
localparam [72:1] USE_PATTERN_DETECT_REG = USE_PATTERN_DETECT;
`endif
wire [1:0] AUTORESET_PATDET_BIN;
wire AUTORESET_PRIORITY_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RSTP_INVERTED_BIN;
wire [47:0] MASK_BIN;
wire [47:0] PATTERN_BIN;
wire PREG_BIN;
wire [1:0] SEL_MASK_BIN;
wire SEL_PATTERN_BIN;
wire USE_PATTERN_DETECT_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_OUTPUT_dr.v"
`endif
wire CARRYCASCOUT_out;
wire CCOUT_FB_out;
wire MULTSIGNOUT_out;
wire OVERFLOW_out;
wire PATTERN_B_DETECT_out;
wire PATTERN_DETECT_out;
wire P_FDBK_47_out;
wire UNDERFLOW_out;
wire [3:0] CARRYOUT_out;
wire [47:0] PCOUT_out;
wire [47:0] P_FDBK_out;
wire [47:0] P_out;
wire [7:0] XOROUT_out;
wire CARRYCASCOUT_delay;
wire CCOUT_FB_delay;
wire MULTSIGNOUT_delay;
wire OVERFLOW_delay;
wire PATTERN_B_DETECT_delay;
wire PATTERN_DETECT_delay;
wire P_FDBK_47_delay;
wire UNDERFLOW_delay;
wire [3:0] CARRYOUT_delay;
wire [47:0] PCOUT_delay;
wire [47:0] P_FDBK_delay;
wire [47:0] P_delay;
wire [7:0] XOROUT_delay;
wire ALUMODE10_in;
wire CEP_in;
wire CLK_in;
wire MULTSIGN_ALU_in;
wire RSTP_in;
wire [3:0] COUT_in;
wire [47:0] ALU_OUT_in;
wire [47:0] C_DATA_in;
wire [7:0] XOR_MX_in;
wire ALUMODE10_delay;
wire CEP_delay;
wire CLK_delay;
wire MULTSIGN_ALU_delay;
wire RSTP_delay;
wire [3:0] COUT_delay;
wire [47:0] ALU_OUT_delay;
wire [47:0] C_DATA_delay;
wire [7:0] XOR_MX_delay;
wire the_auto_reset_patdet;
wire auto_reset_pri;
// reg [47:0] the_mask = 0;
wire [47:0] the_mask;
wire [47:0] the_pattern;
reg opmode_valid_flag_dou = 1'b1; // TODO
// reg [3:0] COUT_reg = 4'b0xxx;
reg [3:0] COUT_reg = 4'b0000;
reg ALUMODE10_reg = 1'b0;
wire ALUMODE10_mux;
reg MULTSIGN_ALU_reg = 1'b0;
reg [47:0] ALU_OUT_reg = 48'b0;
reg [7:0] XOR_MX_reg = 8'b0;
wire pdet_o;
wire pdetb_o;
wire pdet_o_mux;
wire pdetb_o_mux;
wire overflow_data;
wire underflow_data;
reg pdet_o_reg1 = 1'b0;
reg pdet_o_reg2 = 1'b0;
reg pdetb_o_reg1 = 1'b0;
reg pdetb_o_reg2 = 1'b0;
wire CLK_preg;
// input output assignments
assign #(out_delay) CARRYCASCOUT = CARRYCASCOUT_delay;
assign #(out_delay) CARRYOUT = CARRYOUT_delay;
assign #(out_delay) CCOUT_FB = CCOUT_FB_delay;
assign #(out_delay) MULTSIGNOUT = MULTSIGNOUT_delay;
assign #(out_delay) OVERFLOW = OVERFLOW_delay;
assign #(out_delay) P = P_delay;
assign #(out_delay) PATTERN_B_DETECT = PATTERN_B_DETECT_delay;
assign #(out_delay) PATTERN_DETECT = PATTERN_DETECT_delay;
assign #(out_delay) PCOUT = PCOUT_delay;
assign #(out_delay) P_FDBK = P_FDBK_delay;
assign #(out_delay) P_FDBK_47 = P_FDBK_47_delay;
assign #(out_delay) UNDERFLOW = UNDERFLOW_delay;
assign #(out_delay) XOROUT = XOROUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) ALUMODE10_delay = ALUMODE10;
assign #(in_delay) ALU_OUT_delay = ALU_OUT;
assign #(in_delay) CEP_delay = CEP;
assign #(in_delay) COUT_delay = COUT;
assign #(in_delay) C_DATA_delay = C_DATA;
assign #(in_delay) MULTSIGN_ALU_delay = MULTSIGN_ALU;
assign #(in_delay) RSTP_delay = RSTP;
assign #(in_delay) XOR_MX_delay = XOR_MX;
`endif
assign CCOUT_FB_delay = CCOUT_FB_out;
assign P_FDBK_delay = P_FDBK_out;
assign P_FDBK_47_delay = P_FDBK_47_out;
assign CARRYCASCOUT_delay = CARRYCASCOUT_out;
assign CARRYOUT_delay = CARRYOUT_out;
assign MULTSIGNOUT_delay = MULTSIGNOUT_out;
assign OVERFLOW_delay = OVERFLOW_out;
assign PATTERN_B_DETECT_delay = PATTERN_B_DETECT_out;
assign PATTERN_DETECT_delay = PATTERN_DETECT_out;
assign PCOUT_delay = PCOUT_out;
assign P_delay = P_out;
assign UNDERFLOW_delay = UNDERFLOW_out;
assign XOROUT_delay = XOROUT_out;
assign ALUMODE10_in = ALUMODE10_delay;
assign #1 ALU_OUT_in = ALU_OUT_delay; // break 0 delay feedback
assign COUT_in = COUT_delay;
assign MULTSIGN_ALU_in = MULTSIGN_ALU_delay;
assign XOR_MX_in = XOR_MX_delay;
assign CEP_in = CEP_delay;
assign CLK_preg = (PREG_BIN == PREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign C_DATA_in = C_DATA_delay;
assign RSTP_in = RSTP_delay ^ IS_RSTP_INVERTED_BIN;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign AUTORESET_PATDET_BIN =
(AUTORESET_PATDET_REG == "NO_RESET") ? AUTORESET_PATDET_NO_RESET :
(AUTORESET_PATDET_REG == "RESET_MATCH") ? AUTORESET_PATDET_RESET_MATCH :
(AUTORESET_PATDET_REG == "RESET_NOT_MATCH") ? AUTORESET_PATDET_RESET_NOT_MATCH :
AUTORESET_PATDET_NO_RESET;
assign AUTORESET_PRIORITY_BIN =
(AUTORESET_PRIORITY_REG == "RESET") ? AUTORESET_PRIORITY_RESET :
(AUTORESET_PRIORITY_REG == "CEP") ? AUTORESET_PRIORITY_CEP :
AUTORESET_PRIORITY_RESET;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RSTP_INVERTED_BIN = IS_RSTP_INVERTED_REG;
assign MASK_BIN = MASK_REG;
assign PATTERN_BIN = PATTERN_REG;
assign PREG_BIN =
(PREG_REG == 1) ? PREG_1 :
(PREG_REG == 0) ? PREG_0 :
PREG_1;
assign SEL_MASK_BIN =
(SEL_MASK_REG == "MASK") ? SEL_MASK_MASK :
(SEL_MASK_REG == "C") ? SEL_MASK_C :
(SEL_MASK_REG == "ROUNDING_MODE1") ? SEL_MASK_ROUNDING_MODE1 :
(SEL_MASK_REG == "ROUNDING_MODE2") ? SEL_MASK_ROUNDING_MODE2 :
SEL_MASK_MASK;
assign SEL_PATTERN_BIN =
(SEL_PATTERN_REG == "PATTERN") ? SEL_PATTERN_PATTERN :
(SEL_PATTERN_REG == "C") ? SEL_PATTERN_C :
SEL_PATTERN_PATTERN;
assign USE_PATTERN_DETECT_BIN =
(USE_PATTERN_DETECT_REG == "NO_PATDET") ? USE_PATTERN_DETECT_NO_PATDET :
(USE_PATTERN_DETECT_REG == "PATDET") ? USE_PATTERN_DETECT_PATDET :
USE_PATTERN_DETECT_NO_PATDET;
always @ (trig_attr) begin
#1;
//-------- AUTORESET_PATDET check
if ((AUTORESET_PATDET_REG != "NO_RESET") &&
(AUTORESET_PATDET_REG != "RESET_MATCH") &&
(AUTORESET_PATDET_REG != "RESET_NOT_MATCH")) begin
$display("Attribute Syntax Error : The attribute AUTORESET_PATDET on %s instance %m is set to %s. Legal values for this attribute are NO_RESET, RESET_MATCH or RESET_NOT_MATCH.", MODULE_NAME, AUTORESET_PATDET_REG);
attr_err = 1'b1;
end
//-------- AUTORESET_PRIORITY check
if ((AUTORESET_PRIORITY_REG != "RESET") &&
(AUTORESET_PRIORITY_REG != "CEP")) begin
$display("Attribute Syntax Error : The attribute AUTORESET_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are RESET or CEP.", MODULE_NAME, AUTORESET_PRIORITY_REG);
attr_err = 1'b1;
end
//-------- SEL_MASK check
if ((SEL_MASK_REG != "MASK") &&
(SEL_MASK_REG != "C") &&
(SEL_MASK_REG != "ROUNDING_MODE1") &&
(SEL_MASK_REG != "ROUNDING_MODE2")) begin
$display("Attribute Syntax Error : The attribute SEL_MASK on %s instance %m is set to %s. Legal values for this attribute are MASK, C, ROUNDING_MODE1 or ROUNDING_MODE2.", MODULE_NAME, SEL_MASK_REG);
attr_err = 1'b1;
end
//-------- SEL_PATTERN check
if ((SEL_PATTERN_REG != "PATTERN") &&
(SEL_PATTERN_REG != "C")) begin
$display("Attribute Syntax Error : The attribute SEL_PATTERN on %s instance %m is set to %s. Legal values for this attribute are PATTERN or C.", MODULE_NAME, SEL_PATTERN_REG);
attr_err = 1'b1;
end
//-------- USE_PATTERN_DETECT check
if ((USE_PATTERN_DETECT_REG != "NO_PATDET") &&
(USE_PATTERN_DETECT_REG != "PATDET")) begin
$display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on %s instance %m is set to %s. Legal values for this attribute are NO_PATDET or PATDET.", MODULE_NAME, USE_PATTERN_DETECT_REG);
attr_err = 1'b1;
end
//-------- PREG check
if ((PREG_REG != 0) && (PREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute PREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, PREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
//--####################################################################
//--##### Pattern Detector #####
//--####################################################################
// select pattern
assign the_pattern = (SEL_PATTERN_BIN == SEL_PATTERN_PATTERN) ? PATTERN_BIN : C_DATA_in;
// select mask
assign the_mask = (SEL_MASK_BIN == SEL_MASK_C) ? C_DATA_in :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE1) ? {~(C_DATA_in[46:0]),1'b0} :
(SEL_MASK_BIN == SEL_MASK_ROUNDING_MODE2) ? {~(C_DATA_in[45:0]),2'b0} :
MASK_BIN; // default or (SEL_MASK_BIN == SEL_MASK_MASK)
// always @(C_DATA_in or SEL_MASK_BIN or MASK_BIN) begin
// case(SEL_MASK_BIN)
// SEL_MASK_MASK : the_mask <= MASK_BIN;
// SEL_MASK_C : the_mask <= C_DATA_in;
// SEL_MASK_ROUNDING_MODE1 : the_mask <= ~(C_DATA_in << 1);
// SEL_MASK_ROUNDING_MODE2 : the_mask <= ~(C_DATA_in << 2);
// default : the_mask <= MASK_BIN;
// endcase
// end
//-- now do the pattern detection
assign pdet_o = &(~(the_pattern ^ ALU_OUT_in) | the_mask);
assign pdetb_o = &( (the_pattern ^ ALU_OUT_in) | the_mask);
assign PATTERN_DETECT_out = opmode_valid_flag_dou ? pdet_o_mux : 1'bx;
assign PATTERN_B_DETECT_out = opmode_valid_flag_dou ? pdetb_o_mux : 1'bx;
// assign CLK_preg = (PREG_BIN == PREG_1) ? CLK_in : 1'b0;
//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW
always @(posedge CLK_preg) begin
if(RSTP_in || glblGSR || the_auto_reset_patdet)
begin
pdet_o_reg1 <= 1'b0;
pdet_o_reg2 <= 1'b0;
pdetb_o_reg1 <= 1'b0;
pdetb_o_reg2 <= 1'b0;
end
else if(CEP_in)
begin
//-- the previous values are used in Underflow/Overflow
pdet_o_reg2 <= pdet_o_reg1;
pdet_o_reg1 <= pdet_o;
pdetb_o_reg2 <= pdetb_o_reg1;
pdetb_o_reg1 <= pdetb_o;
end
end
assign pdet_o_mux = (PREG_BIN == PREG_1) ? pdet_o_reg1 : pdet_o;
assign pdetb_o_mux = (PREG_BIN == PREG_1) ? pdetb_o_reg1 : pdetb_o;
assign overflow_data = (PREG_BIN == PREG_1) ? pdet_o_reg2 : pdet_o;
assign underflow_data = (PREG_BIN == PREG_1) ? pdetb_o_reg2 : pdetb_o;
//--####################################################################
//--##### AUTORESET_PATDET #####
//--####################################################################
assign auto_reset_pri = (AUTORESET_PRIORITY_BIN == AUTORESET_PRIORITY_RESET) || CEP_in;
assign the_auto_reset_patdet =
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_MATCH) ?
auto_reset_pri && pdet_o_mux :
(AUTORESET_PATDET_BIN == AUTORESET_PATDET_RESET_NOT_MATCH) ?
auto_reset_pri && overflow_data && ~pdet_o_mux : 1'b0; // NO_RESET
//--####################################################################
//--#### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT, PCOUT and XOROUT reg #####
//--####################################################################
//*** register with 1 level of register
always @(posedge CLK_preg) begin
if(RSTP_in || glblGSR || the_auto_reset_patdet) begin
// COUT_reg <= 4'b0xxx;
COUT_reg <= 4'b0000;
ALUMODE10_reg <= 1'b0;
MULTSIGN_ALU_reg <= 1'b0;
ALU_OUT_reg <= 48'b0;
XOR_MX_reg <= 8'b0;
end
else if (CEP_in) begin
COUT_reg <= COUT_in;
ALUMODE10_reg <= ALUMODE10_in;
MULTSIGN_ALU_reg <= MULTSIGN_ALU_in;
ALU_OUT_reg <= ALU_OUT_in;
XOR_MX_reg <= XOR_MX_in;
end
end
assign CARRYOUT_out = (PREG_BIN == PREG_1) ? COUT_reg : COUT_in;
assign MULTSIGNOUT_out = (PREG_BIN == PREG_1) ? MULTSIGN_ALU_reg : MULTSIGN_ALU_in;
assign P_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
assign ALUMODE10_mux = (PREG_BIN == PREG_1) ? ALUMODE10_reg : ALUMODE10_in;
assign XOROUT_out = (PREG_BIN == PREG_1) ? XOR_MX_reg : XOR_MX_in;
assign CCOUT_FB_out = ALUMODE10_reg ^ COUT_reg[3];
assign CARRYCASCOUT_out = ALUMODE10_mux ^ CARRYOUT_out[3];
// assign P_FDBK_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
// assign P_FDBK_47_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg[47] : ALU_OUT_in[47];
assign P_FDBK_out = ALU_OUT_reg;
assign P_FDBK_47_out = ALU_OUT_reg[47];
assign PCOUT_out = (PREG_BIN == PREG_1) ? ALU_OUT_reg : ALU_OUT_in;
//--####################################################################
//--##### Underflow / Overflow #####
//--####################################################################
assign OVERFLOW_out = ((USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ||
(PREG_BIN == PREG_1)) ?
~pdet_o_mux && ~pdetb_o_mux && overflow_data : 1'bx;
assign UNDERFLOW_out = ((USE_PATTERN_DETECT_BIN == USE_PATTERN_DETECT_PATDET) ||
(PREG_BIN == PREG_1)) ?
~pdet_o_mux && ~pdetb_o_mux && underflow_data : 1'bx;
specify
(ALUMODE10 => CARRYCASCOUT) = (0:0:0, 0:0:0);
(ALU_OUT *> P) = (0:0:0, 0:0:0);
(ALU_OUT *> PATTERN_B_DETECT) = (0:0:0, 0:0:0);
(ALU_OUT *> PATTERN_DETECT) = (0:0:0, 0:0:0);
(ALU_OUT *> PCOUT) = (0:0:0, 0:0:0);
(CLK *> CARRYOUT) = (0:0:0, 0:0:0);
(CLK *> P) = (0:0:0, 0:0:0);
(CLK *> PCOUT) = (0:0:0, 0:0:0);
(CLK *> P_FDBK) = (0:0:0, 0:0:0);
(CLK *> XOROUT) = (0:0:0, 0:0:0);
(CLK => CARRYCASCOUT) = (0:0:0, 0:0:0);
(CLK => CCOUT_FB) = (0:0:0, 0:0:0);
(CLK => MULTSIGNOUT) = (0:0:0, 0:0:0);
(CLK => OVERFLOW) = (0:0:0, 0:0:0);
(CLK => PATTERN_B_DETECT) = (0:0:0, 0:0:0);
(CLK => PATTERN_DETECT) = (0:0:0, 0:0:0);
(CLK => P_FDBK_47) = (0:0:0, 0:0:0);
(CLK => UNDERFLOW) = (0:0:0, 0:0:0);
(COUT *> CARRYCASCOUT) = (0:0:0, 0:0:0);
(COUT *> CARRYOUT) = (0:0:0, 0:0:0);
(C_DATA *> PATTERN_B_DETECT) = (0:0:0, 0:0:0);
(C_DATA *> PATTERN_DETECT) = (0:0:0, 0:0:0);
(MULTSIGN_ALU => MULTSIGNOUT) = (0:0:0, 0:0:0);
(XOR_MX *> XOROUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge ALUMODE10, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE10_delay);
$setuphold (negedge CLK, negedge ALU_OUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALU_OUT_delay);
$setuphold (negedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEP_delay);
$setuphold (negedge CLK, negedge COUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, COUT_delay);
$setuphold (negedge CLK, negedge C_DATA, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_DATA_delay);
$setuphold (negedge CLK, negedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier,,, CLK_delay, MULTSIGN_ALU_delay);
$setuphold (negedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTP_delay);
$setuphold (negedge CLK, negedge XOR_MX, 0:0:0, 0:0:0, notifier,,, CLK_delay, XOR_MX_delay);
$setuphold (negedge CLK, posedge ALUMODE10, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE10_delay);
$setuphold (negedge CLK, posedge ALU_OUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALU_OUT_delay);
$setuphold (negedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEP_delay);
$setuphold (negedge CLK, posedge COUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, COUT_delay);
$setuphold (negedge CLK, posedge C_DATA, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_DATA_delay);
$setuphold (negedge CLK, posedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier,,, CLK_delay, MULTSIGN_ALU_delay);
$setuphold (negedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTP_delay);
$setuphold (negedge CLK, posedge XOR_MX, 0:0:0, 0:0:0, notifier,,, CLK_delay, XOR_MX_delay);
$setuphold (posedge CLK, negedge ALUMODE10, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE10_delay);
$setuphold (posedge CLK, negedge ALU_OUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALU_OUT_delay);
$setuphold (posedge CLK, negedge CEP, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEP_delay);
$setuphold (posedge CLK, negedge COUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, COUT_delay);
$setuphold (posedge CLK, negedge C_DATA, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_DATA_delay);
$setuphold (posedge CLK, negedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier,,, CLK_delay, MULTSIGN_ALU_delay);
$setuphold (posedge CLK, negedge RSTP, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTP_delay);
$setuphold (posedge CLK, negedge XOR_MX, 0:0:0, 0:0:0, notifier,,, CLK_delay, XOR_MX_delay);
$setuphold (posedge CLK, posedge ALUMODE10, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALUMODE10_delay);
$setuphold (posedge CLK, posedge ALU_OUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, ALU_OUT_delay);
$setuphold (posedge CLK, posedge CEP, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEP_delay);
$setuphold (posedge CLK, posedge COUT, 0:0:0, 0:0:0, notifier,,, CLK_delay, COUT_delay);
$setuphold (posedge CLK, posedge C_DATA, 0:0:0, 0:0:0, notifier,,, CLK_delay, C_DATA_delay);
$setuphold (posedge CLK, posedge MULTSIGN_ALU, 0:0:0, 0:0:0, notifier,,, CLK_delay, MULTSIGN_ALU_delay);
$setuphold (posedge CLK, posedge RSTP, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTP_delay);
$setuphold (posedge CLK, posedge XOR_MX, 0:0:0, 0:0:0, notifier,,, CLK_delay, XOR_MX_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_PREADD.v 0000664 0000000 0000000 00000005223 12327044266 0023071 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_PREADD.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_PREADD
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [26:0] AD,
input ADDSUB,
input [26:0] D_DATA,
input INMODE2,
input [26:0] PREADD_AB
);
// define constants
localparam MODULE_NAME = "DSP_PREADD";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
tri0 glblGSR = glbl.GSR;
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_PREADD_dr.v"
`endif
wire [26:0] AD_out;
wire [26:0] AD_delay;
wire ADDSUB_in;
wire INMODE_2_in;
wire [26:0] D_DATA_in;
wire [26:0] PREADD_AB_in;
wire ADDSUB_delay;
wire INMODE_2_delay;
wire [26:0] D_DATA_delay;
wire [26:0] PREADD_AB_delay;
wire [26:0] D_DATA_mux;
// input output assignments
assign #(out_delay) AD = AD_delay;
// inputs with no timing checks
assign #(in_delay) ADDSUB_delay = ADDSUB;
assign #(in_delay) D_DATA_delay = D_DATA;
assign #(in_delay) INMODE_2_delay = INMODE2;
assign #(in_delay) PREADD_AB_delay = PREADD_AB;
assign AD_delay = AD_out;
assign ADDSUB_in = ADDSUB_delay;
assign D_DATA_in = D_DATA_delay;
assign INMODE_2_in = INMODE_2_delay;
assign PREADD_AB_in = PREADD_AB_delay;
//*********************************************************
//*** Preaddsub AD
//*********************************************************
assign D_DATA_mux = INMODE_2_in ? D_DATA_in : 27'b0;
assign AD_out = ADDSUB_in ? (D_DATA_mux - PREADD_AB_in) : (D_DATA_mux + PREADD_AB_in);
specify
(ADDSUB *> AD) = (0:0:0, 0:0:0);
(D_DATA *> AD) = (0:0:0, 0:0:0);
(INMODE2 *> AD) = (0:0:0, 0:0:0);
(PREADD_AB *> AD) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/DSP_PREADD_DATA.v 0000664 0000000 0000000 00000040424 12327044266 0023664 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\
// \ \ / \ Filename : DSP_PREADD_DATA.v
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 05/07/13 - 716896 - INMODE_INV_REG mis sized
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_PREADD_DATA
#(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ADREG = 1,
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter integer DREG = 1,
parameter integer INMODEREG = 1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [4:0] IS_INMODE_INVERTED = 5'b00000,
parameter [0:0] IS_RSTD_INVERTED = 1'b0,
parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0,
parameter PREADDINSEL = "A",
parameter USE_MULT = "MULTIPLY"
) (
output [26:0] A2A1,
output ADDSUB,
output [26:0] AD_DATA,
output [17:0] B2B1,
output [26:0] D_DATA,
output INMODE_2,
output [26:0] PREADD_AB,
input [26:0] A1_DATA,
input [26:0] A2_DATA,
input [26:0] AD,
input [17:0] B1_DATA,
input [17:0] B2_DATA,
input CEAD,
input CED,
input CEINMODE,
input CLK,
input [26:0] DIN,
input [4:0] INMODE,
input RSTD,
input RSTINMODE
);
// define constants
localparam MODULE_NAME = "DSP_PREADD_DATA";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam ADREG_0 = 1;
localparam ADREG_1 = 0;
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam DREG_0 = 1;
localparam DREG_1 = 0;
localparam INMODEREG_0 = 1;
localparam INMODEREG_1 = 0;
localparam PREADDINSEL_A = 0;
localparam PREADDINSEL_B = 1;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
`ifndef XIL_DR
localparam [0:0] ADREG_REG = ADREG;
localparam [16:1] AMULTSEL_REG = AMULTSEL;
localparam [16:1] BMULTSEL_REG = BMULTSEL;
localparam [0:0] DREG_REG = DREG;
localparam [0:0] INMODEREG_REG = INMODEREG;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED;
localparam [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED;
localparam [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED;
localparam [8:1] PREADDINSEL_REG = PREADDINSEL;
localparam [64:1] USE_MULT_REG = USE_MULT;
`endif
wire ADREG_BIN;
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire DREG_BIN;
wire INMODEREG_BIN;
wire IS_CLK_INVERTED_BIN;
wire [4:0] IS_INMODE_INVERTED_BIN;
wire IS_RSTD_INVERTED_BIN;
wire IS_RSTINMODE_INVERTED_BIN;
wire PREADDINSEL_BIN;
wire [1:0] USE_MULT_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_PREADD_DATA_dr.v"
`endif
wire ADDSUB_out;
wire INMODE_2_out;
wire [17:0] B2B1_out;
wire [26:0] A2A1_out;
wire [26:0] AD_DATA_out;
wire [26:0] D_DATA_out;
wire [26:0] PREADD_AB_out;
wire ADDSUB_delay;
wire INMODE_2_delay;
wire [17:0] B2B1_delay;
wire [26:0] A2A1_delay;
wire [26:0] AD_DATA_delay;
wire [26:0] D_DATA_delay;
wire [26:0] PREADD_AB_delay;
wire CEAD_in;
wire CED_in;
wire CEINMODE_in;
wire CLK_in;
wire RSTD_in;
wire RSTINMODE_in;
wire [17:0] B1_DATA_in;
wire [17:0] B2_DATA_in;
wire [26:0] A1_DATA_in;
wire [26:0] A2_DATA_in;
wire [26:0] AD_in;
wire [26:0] DIN_in;
wire [4:0] INMODE_in;
wire CEAD_delay;
wire CED_delay;
wire CEINMODE_delay;
wire CLK_delay;
wire RSTD_delay;
wire RSTINMODE_delay;
wire [17:0] B1_DATA_delay;
wire [17:0] B2_DATA_delay;
wire [26:0] A1_DATA_delay;
wire [26:0] A2_DATA_delay;
wire [26:0] AD_delay;
wire [26:0] DIN_delay;
wire [4:0] INMODE_delay;
wire [26:0] a1a2_i_mux;
wire [17:0] b1b2_i_mux;
wire [4:0] INMODE_mux;
reg [4:0] INMODE_reg = 5'b0;
reg [26:0] AD_DATA_reg = 27'b0;
reg [26:0] D_DATA_reg = 27'b0;
wire CLK_inmode;
wire CLK_dreg;
wire CLK_adreg;
// input output assignments
assign #(out_delay) A2A1 = A2A1_delay;
assign #(out_delay) ADDSUB = ADDSUB_delay;
assign #(out_delay) AD_DATA = AD_DATA_delay;
assign #(out_delay) B2B1 = B2B1_delay;
assign #(out_delay) D_DATA = D_DATA_delay;
assign #(out_delay) INMODE_2 = INMODE_2_delay;
assign #(out_delay) PREADD_AB = PREADD_AB_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) AD_delay = AD;
assign #(in_delay) CEAD_delay = CEAD;
assign #(in_delay) CED_delay = CED;
assign #(in_delay) CEINMODE_delay = CEINMODE;
assign #(in_delay) DIN_delay = DIN;
assign #(in_delay) INMODE_delay = INMODE;
assign #(in_delay) RSTD_delay = RSTD;
assign #(in_delay) RSTINMODE_delay = RSTINMODE;
`endif
// inputs with no timing checks
assign #(in_delay) A1_DATA_delay = A1_DATA;
assign #(in_delay) A2_DATA_delay = A2_DATA;
assign #(in_delay) B1_DATA_delay = B1_DATA;
assign #(in_delay) B2_DATA_delay = B2_DATA;
assign A2A1_delay = A2A1_out;
assign ADDSUB_delay = ADDSUB_out;
assign AD_DATA_delay = AD_DATA_out;
assign B2B1_delay = B2B1_out;
assign D_DATA_delay = D_DATA_out;
assign INMODE_2_delay = INMODE_2_out;
assign PREADD_AB_delay = PREADD_AB_out;
assign A1_DATA_in = A1_DATA_delay;
assign A2_DATA_in = A2_DATA_delay;
assign AD_in = AD_delay;
assign B1_DATA_in = B1_DATA_delay;
assign B2_DATA_in = B2_DATA_delay;
assign CEAD_in = CEAD_delay;
assign CED_in = CED_delay;
assign CEINMODE_in = CEINMODE_delay;
assign CLK_inmode = (INMODEREG_BIN == INMODEREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_dreg = (DREG_BIN == DREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CLK_adreg = (ADREG_BIN == ADREG_0) ? 1'b0 : CLK_delay ^ IS_CLK_INVERTED_BIN;
assign DIN_in = DIN_delay;
assign INMODE_in = INMODE_delay ^ IS_INMODE_INVERTED_BIN;
assign RSTD_in = RSTD_delay ^ IS_RSTD_INVERTED_BIN;
assign RSTINMODE_in = RSTINMODE_delay ^ IS_RSTINMODE_INVERTED_BIN;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
`endif
// $finish;
#1;
trig_attr = ~trig_attr;
end
assign ADREG_BIN =
(ADREG_REG == 1) ? ADREG_1 :
(ADREG_REG == 0) ? ADREG_0 :
ADREG_1;
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign DREG_BIN =
(DREG_REG == 1) ? DREG_1 :
(DREG_REG == 0) ? DREG_0 :
DREG_1;
assign INMODEREG_BIN =
(INMODEREG_REG == 1) ? INMODEREG_1 :
(INMODEREG_REG == 0) ? INMODEREG_0 :
INMODEREG_1;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_INMODE_INVERTED_BIN = IS_INMODE_INVERTED_REG;
assign IS_RSTD_INVERTED_BIN = IS_RSTD_INVERTED_REG;
assign IS_RSTINMODE_INVERTED_BIN = IS_RSTINMODE_INVERTED_REG;
assign PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
always @ (trig_attr) begin
#1;
//-------- AMULTSEL check
if ((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute AMULTSEL on %s instance %m is set to %s. Legal values for this attribute are A or AD.", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
//-------- BMULTSEL check
if ((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD")) begin
$display("Attribute Syntax Error : The attribute BMULTSEL on %s instance %m is set to %s. Legal values for this attribute are B or AD.", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
//-------- PREADDINSEL check
if ((PREADDINSEL_REG != "A") &&
(PREADDINSEL_REG != "B")) begin
$display("Attribute Syntax Error : The attribute PREADDINSEL on %s instance %m is set to %s. Legal values for this attribute are A or B.", MODULE_NAME, PREADDINSEL_REG);
attr_err = 1'b1;
end
//-------- USE_MULT check
if ((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE")) begin
$display("Attribute Syntax Error : The attribute USE_MULT on %s instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
//-------- ADREG check
if ((ADREG_REG != 0) && (ADREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute ADREG on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, ADREG_REG);
attr_err = 1'b1;
end
//-------- DREG check
if ((DREG_REG != 0) && (DREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute DREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DREG_REG);
attr_err = 1'b1;
end
//-------- INMODEREG check
if ((INMODEREG_REG != 0) && (INMODEREG_REG != 1))
begin
$display("Attribute Syntax Error : The attribute INMODEREG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, INMODEREG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign a1a2_i_mux = INMODE_mux[0] ? A1_DATA_in : A2_DATA_in;
assign b1b2_i_mux = INMODE_mux[4] ? B1_DATA_in : B2_DATA_in;
assign A2A1_out = ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) ? 27'b0 : a1a2_i_mux;
assign B2B1_out = ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) ? 18'b0 : b1b2_i_mux;
assign ADDSUB_out = INMODE_mux[3];
assign INMODE_2_out = INMODE_mux[2];
// assign PREADD_AB_out = PREADDINSEL_BIN ? {9'b0, B2B1_out} : A2A1_out;
assign PREADD_AB_out = PREADDINSEL_BIN ? {{9{B2B1_out[17]}}, B2B1_out} : A2A1_out;
//*********************************************************
//********** INMODE signal registering ************
//*********************************************************
// new
// assign CLK_inmode = (INMODEREG_BIN == INMODEREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_inmode) begin
if (RSTINMODE_in || glblGSR)
INMODE_reg <= 5'b0;
else if (CEINMODE_in)
INMODE_reg <= INMODE_in;
end
assign INMODE_mux = (INMODEREG_BIN == INMODEREG_1) ? INMODE_reg : INMODE_in;
//*********************************************************
//*** Input register D with 1 level deep of register
//*********************************************************
// assign CLK_dreg = (DREG_BIN == DREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_dreg) begin
if (RSTD_in || glblGSR) D_DATA_reg <= 27'b0;
else if (CED_in) D_DATA_reg <= DIN_in;
end
assign D_DATA_out = (DREG_BIN == DREG_1) ? D_DATA_reg : DIN_in;
//*********************************************************
//*** Input register AD with 1 level deep of register
//*********************************************************
// assign CLK_adreg = (ADREG_BIN == ADREG_1) ? CLK_in : 1'b0;
always @(posedge CLK_adreg) begin
if (RSTD_in || glblGSR) AD_DATA_reg <= 27'b0;
else if (CEAD_in) AD_DATA_reg <= AD_in;
end
assign AD_DATA_out = (ADREG_BIN == ADREG_1) ? AD_DATA_reg : AD_in;
specify
(A1_DATA *> A2A1) = (0:0:0, 0:0:0);
(A1_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(A2_DATA *> A2A1) = (0:0:0, 0:0:0);
(A2_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(AD *> AD_DATA) = (0:0:0, 0:0:0);
(B1_DATA *> B2B1) = (0:0:0, 0:0:0);
(B1_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(B2_DATA *> B2B1) = (0:0:0, 0:0:0);
(B2_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(CLK *> A2A1) = (0:0:0, 0:0:0);
(CLK *> AD_DATA) = (0:0:0, 0:0:0);
(CLK *> B2B1) = (0:0:0, 0:0:0);
(CLK *> D_DATA) = (0:0:0, 0:0:0);
(CLK *> PREADD_AB) = (0:0:0, 0:0:0);
(CLK => ADDSUB) = (0:0:0, 0:0:0);
(CLK => INMODE_2) = (0:0:0, 0:0:0);
(DIN *> D_DATA) = (0:0:0, 0:0:0);
(INMODE *> A2A1) = (0:0:0, 0:0:0);
(INMODE *> ADDSUB) = (0:0:0, 0:0:0);
(INMODE *> B2B1) = (0:0:0, 0:0:0);
(INMODE *> INMODE_2) = (0:0:0, 0:0:0);
(INMODE *> PREADD_AB) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge CLK, negedge AD, 0:0:0, 0:0:0, notifier,,, CLK_delay, AD_delay);
$setuphold (negedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEAD_delay);
$setuphold (negedge CLK, negedge CED, 0:0:0, 0:0:0, notifier,,, CLK_delay, CED_delay);
$setuphold (negedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEINMODE_delay);
$setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (negedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, INMODE_delay);
$setuphold (negedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTD_delay);
$setuphold (negedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTINMODE_delay);
$setuphold (negedge CLK, posedge AD, 0:0:0, 0:0:0, notifier,,, CLK_delay, AD_delay);
$setuphold (negedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEAD_delay);
$setuphold (negedge CLK, posedge CED, 0:0:0, 0:0:0, notifier,,, CLK_delay, CED_delay);
$setuphold (negedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEINMODE_delay);
$setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (negedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, INMODE_delay);
$setuphold (negedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTD_delay);
$setuphold (negedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTINMODE_delay);
$setuphold (posedge CLK, negedge AD, 0:0:0, 0:0:0, notifier,,, CLK_delay, AD_delay);
$setuphold (posedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEAD_delay);
$setuphold (posedge CLK, negedge CED, 0:0:0, 0:0:0, notifier,,, CLK_delay, CED_delay);
$setuphold (posedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEINMODE_delay);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (posedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, INMODE_delay);
$setuphold (posedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTD_delay);
$setuphold (posedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTINMODE_delay);
$setuphold (posedge CLK, posedge AD, 0:0:0, 0:0:0, notifier,,, CLK_delay, AD_delay);
$setuphold (posedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEAD_delay);
$setuphold (posedge CLK, posedge CED, 0:0:0, 0:0:0, notifier,,, CLK_delay, CED_delay);
$setuphold (posedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CEINMODE_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (posedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, INMODE_delay);
$setuphold (posedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTD_delay);
$setuphold (posedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier,,, CLK_delay, RSTINMODE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/EFUSE_USR.v 0000664 0000000 0000000 00000002134 12327044266 0023022 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/EFUSE_USR.v,v 1.1.72.1 2009/04/10 19:56:17 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description :
// / /
// /__/ /\ Filename : EFUSE_USR.v
// \ \ / \ Timestamp : Wed Mar 19 12:34:06 2008
// \__\/\__ \
//
// Revision:
// 03/19/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module EFUSE_USR (
EFUSEUSR
);
parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [31:0] EFUSEUSR;
assign EFUSEUSR = SIM_EFUSE_VALUE;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FDCE.v 0000664 0000000 0000000 00000015233 12327044266 0022127 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i
// \ \ Description : Xilinx Functional Simulation Library Component
// / / D Flip-Flop with Asynchronous Clear and Clock Enable
// /___/ /\ Filename : FDCE.v
// \ \ / \ Timestamp : Tue Aug 24 13:37:09 PDT 2010
// \___\/\___\
//
// Revision:
// 08/24/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input CLR,
input D
);
wire o_out;
wire D_dly, C_dly, CE_dly, CLR_dly;
wire D_in, C_in, CE_in, CLR_in;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire [0:0] IS_CLR_INVERTED_BIN;
wire [0:0] IS_C_INVERTED_BIN;
wire [0:0] IS_D_INVERTED_BIN;
`ifdef XIL_TIMING
wire ngsr, nrst, in_out;
wire in_clk_enable, ce_clk_enable, rst_clk_enable;
wire in_clk_enable1, ce_clk_enable1, rst_clk_enable1;
`endif
tri0 GSR = glbl.GSR;
assign Q = q_out;
`ifdef XIL_TIMING
not (nrst, CLR_in);
not (ngsr, GSR);
xor (in_out, D_in, Q);
and (in_clk_enable, ngsr, nrst, CE_in);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, CE_in, D_in);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or CLR_dly)
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
set_int = 0;
rst_int = CLR_dly ^ IS_CLR_INVERTED_BIN;
end
ffsrce_fdce (o_out, C_in, D_in, CE_in, set_int, rst_int, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign C_dly = C;
assign CE_dly = CE;
assign CLR_dly = CLR;
assign D_dly = D;
`endif
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED;
assign IS_C_INVERTED_BIN = IS_C_INVERTED;
assign IS_D_INVERTED_BIN = IS_D_INVERTED;
assign C_in = C_dly ^ IS_C_INVERTED_BIN;
assign CE_in = CE_dly;
assign CLR_in = CLR_dly ^ IS_CLR_INVERTED_BIN;
assign D_in = D_dly ^ IS_D_INVERTED_BIN;
specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(CLR => Q) = (0:0:0, 0:0:0);
(negedge CLR *> (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR *> (Q +: 0)) = (0:0:0, 0:0:0);
$setuphold (posedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$recrem (negedge CLR, posedge C &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,CLR_dly, C_dly);
$period (posedge C &&& CE, 0:0:0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$setuphold (negedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$recrem (negedge CLR, negedge C &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,CLR_dly, C_dly);
$recrem (posedge CLR, posedge C &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,CLR_dly, C_dly);
$recrem (posedge CLR, negedge C &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,CLR_dly, C_dly);
$period (negedge C &&& CE, 0:0:0, notifier);
$width (negedge CLR, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive ffsrce_fdce (q, clk, d, ce, set, rst, notifier);
output q; reg q;
input clk, d, ce, set, rst, notifier;
table
// clk d ce set rst notifier q q+;
? ? ? 1 0 ? : ? : 1;
? ? ? ? 1 ? : ? : 0;
(01) 0 1 0 0 ? : ? : 0;
(01) 1 1 0 0 ? : ? : 1;
(01) x 1 0 0 ? : ? : x;
(01) 0 x 0 0 ? : 0 : 0;
(01) 1 x 0 0 ? : 1 : 1;
(??) ? 0 ? ? ? : ? : -;
(1?) ? ? ? ? ? : ? : -;
(?0) ? ? ? ? ? : ? : -;
(01) 0 1 0 x ? : ? : 0;
(01) 1 1 x 0 ? : ? : 1;
? ? ? 0 (?x) ? : 0 : 0;
? ? ? (?x) 0 ? : 1 : 1;
(?1) 1 ? ? 0 ? : 1 : 1;
(?1) 0 ? 0 ? ? : 0 : 0;
(0?) 1 ? ? 0 ? : 1 : 1;
(0?) 0 ? 0 ? ? : 0 : 0;
? (??) ? ? ? ? : ? : -;
? ? (??) ? ? ? : ? : -;
? ? ? (?0) ? ? : ? : -;
? ? ? x (?0) ? : ? : x;
? ? ? 0 (?0) ? : ? : -;
? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FDPE.v 0000664 0000000 0000000 00000015254 12327044266 0022147 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i
// \ \ Description : Xilinx Functional Simulation Library Component
// / / D Flip-Flop with Asynchronous Preset and Clock Enable
// /___/ /\ Filename : FDPE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDPE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input PRE
);
wire o_out;
wire D_dly, C_dly, CE_dly, PRE_dly;
wire D_in, C_in, CE_in, PRE_in;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire [0:0] IS_C_INVERTED_BIN;
wire [0:0] IS_D_INVERTED_BIN;
wire [0:0] IS_PRE_INVERTED_BIN;
`ifdef XIL_TIMING
wire ni, ngsr, nset, in_out;
wire in_clk_enable, ce_clk_enable, set_clk_enable;
wire in_clk_enable1, ce_clk_enable1, set_clk_enable1;
`endif
tri0 GSR = glbl.GSR;
assign Q = q_out;
`ifdef XIL_TIMING
not (ni, D_in);
not (nset, PRE_in);
not (ngsr, GSR);
xor (in_out, D_in, Q);
and (in_clk_enable, ngsr, nset, CE_in);
and (ce_clk_enable, ngsr, nset, in_out);
and (set_clk_enable, ngsr, CE_in, ni);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign set_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : set_clk_enable;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or PRE_dly)
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
set_int = PRE_dly ^ IS_PRE_INVERTED_BIN;
rst_int = 0;
end
ffsrce_fdpe (o_out, C_in, D_in, CE_in, set_int, rst_int, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign C_dly = C;
assign CE_dly = CE;
assign D_dly = D;
assign PRE_dly = PRE;
`endif
assign IS_C_INVERTED_BIN = IS_C_INVERTED;
assign IS_D_INVERTED_BIN = IS_D_INVERTED;
assign IS_PRE_INVERTED_BIN = IS_PRE_INVERTED;
assign C_in = C_dly ^ IS_C_INVERTED_BIN;
assign CE_in = CE_dly;
assign D_in = D_dly ^ IS_D_INVERTED_BIN;
assign PRE_in = PRE_dly ^ IS_PRE_INVERTED_BIN;
specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(PRE => Q) = (0:0:0, 0:0:0);
(negedge PRE *> (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE *> (Q +: 1)) = (0:0:0, 0:0:0);
$setuphold (posedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$recrem (negedge PRE, posedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$period (posedge C &&& CE, 0:0:0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge PRE, 0:0:0, 0, notifier);
$setuphold (negedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$recrem (posedge PRE, posedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$recrem (negedge PRE, negedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$recrem (posedge PRE, negedge C &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,PRE_dly, C_dly);
$period (negedge C &&& CE, 0:0:0, notifier);
$width (negedge PRE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive ffsrce_fdpe (q, clk, d, ce, set, rst, notifier);
output q; reg q;
input clk, d, ce, set, rst, notifier;
table
// clk d ce set rst notifier q q+;
? ? ? 1 0 ? : ? : 1;
? ? ? ? 1 ? : ? : 0;
(01) 0 1 0 0 ? : ? : 0;
(01) 1 1 0 0 ? : ? : 1;
(01) x 1 0 0 ? : ? : x;
(01) 0 x 0 0 ? : 0 : 0;
(01) 1 x 0 0 ? : 1 : 1;
(??) ? 0 ? ? ? : ? : -;
(1?) ? ? ? ? ? : ? : -;
(?0) ? ? ? ? ? : ? : -;
(01) 0 1 0 x ? : ? : 0;
(01) 1 1 x 0 ? : ? : 1;
? ? ? 0 (?x) ? : 0 : 0;
? ? ? (?x) 0 ? : 1 : 1;
(?1) 1 ? ? 0 ? : 1 : 1;
(?1) 0 ? 0 ? ? : 0 : 0;
(0?) 1 ? ? 0 ? : 1 : 1;
(0?) 0 ? 0 ? ? : 0 : 0;
? (??) ? ? ? ? : ? : -;
? ? (??) ? ? ? : ? : -;
? ? ? (?0) ? ? : ? : -;
? ? ? x (?0) ? : ? : x;
? ? ? 0 (?0) ? : ? : -;
? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FDRE.v 0000664 0000000 0000000 00000027667 12327044266 0022164 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / D Flip-Flop with Synchronous Reset and Clock Enable
// /___/ /\ Filename : FDRE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDRE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_R_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input R
);
wire o_out;
wire D_dly, C_dly, CE_dly, R_dly;
wire D_in, CE_in, R_in;
wire IS_C_INVERTED_BIN;
wire IS_D_INVERTED_BIN;
wire IS_R_INVERTED_BIN;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
`ifdef XIL_TIMING
wire ngsr, nrst, in_out;
wire in_clk_enable, ce_clk_enable, rst_clk_enable;
wire in_clk_enable1, ce_clk_enable1, rst_clk_enable1;
`endif
tri0 GSR = glbl.GSR;
assign Q = q_out;
`ifdef XIL_TIMING
not (nrst, R_in);
not (ngsr, GSR);
xor (in_out, D_in, Q);
and (in_clk_enable, ngsr, nrst, CE_in);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, CE_in, D_in);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR)
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
set_int = 0;
rst_int = 0;
end
sffsrce_fdre (o_out, IS_C_INVERTED_BIN, C_dly, D_in, CE_in, set_int, rst_int, R_in, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign C_dly = C;
assign CE_dly = CE;
assign D_dly = D;
assign R_dly = R;
`endif
assign IS_C_INVERTED_BIN = IS_C_INVERTED;
assign IS_D_INVERTED_BIN = IS_D_INVERTED;
assign IS_R_INVERTED_BIN = IS_R_INVERTED;
assign D_in = D_dly ^ IS_D_INVERTED_BIN;
assign R_in = R_dly ^ IS_R_INVERTED_BIN;
assign CE_in = CE_dly;
specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$setuphold (posedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, posedge R &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,R_dly);
$setuphold (posedge C, negedge R &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,R_dly);
$period (posedge C &&& CE, 0:0:0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$setuphold (negedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, posedge R &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,R_dly);
$setuphold (negedge C, negedge R &&& (rst_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,R_dly);
$period (negedge C &&& CE, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive sffsrce_fdre (q, ici, clk, d, ce, set, rst, srst, notifier);
output q; reg q;
input ici, clk, d, ce, set, rst, srst, notifier;
table
// ici clk d ce set rst srst notifier q q+;
// straight clk
? ? ? ? 1 0 ? ? : ? : 1;
? ? ? ? ? 1 ? ? : ? : 0;
0 (01) ? ? 0 0 1 ? : ? : 0;
0 (x1) ? ? 0 0 1 ? : 0 : 0;
0 (x1) ? ? 0 0 1 ? : 1 : x;
0 (0x) ? ? 0 0 1 ? : 0 : 0;
0 (0x) ? ? 0 0 1 ? : 1 : x;
0 (01) 0 1 0 0 0 ? : ? : 0;
0 (01) 1 1 0 0 0 ? : ? : 1;
0 (01) x 1 0 0 0 ? : ? : x;
0 (01) 0 x 0 0 0 ? : 0 : 0;
0 (01) 1 x 0 0 0 ? : 1 : 1;
0 (??) ? 0 0 0 0 ? : ? : -;
0 (1?) ? ? 0 0 ? ? : ? : -;
0 (?0) ? ? 0 0 ? ? : ? : -;
0 (01) ? 0 0 0 x ? : 0 : 0;
0 (01) 0 1 0 0 x ? : ? : 0;
// 0 (01) ? 0 0 0 0 ? : 1 : 1;
// 0 (01) 1 1 0 0 0 ? : ? : 1;
0 (?1) ? 0 0 0 x ? : 0 : 0;
// 0 (?1) ? 0 0 0 0 ? : 1 : 1;
0 (0?) ? 0 0 0 x ? : 0 : 0;
// 0 (0?) ? 0 0 0 0 ? : 1 : 1;
0 (01) 0 ? 0 x 0 ? : 0 : 0;
0 (01) ? 0 0 x x ? : 0 : 0;
0 (01) 0 ? 0 x x ? : 0 : 0;
0 (01) ? ? 0 x 1 ? : ? : 0;
0 (01) 0 1 0 x ? ? : ? : 0;
0 (0?) 0 ? 0 x 0 ? : 0 : 0;
0 (0?) ? 0 0 x x ? : 0 : 0;
0 (0?) 0 ? 0 x x ? : 0 : 0;
0 (0?) ? ? 0 x 1 ? : 0 : 0;
0 (?1) 0 ? 0 x 0 ? : 0 : 0;
0 (?1) ? 0 0 x x ? : 0 : 0;
0 (?1) 0 ? 0 x x ? : 0 : 0;
0 (?1) ? ? 0 x 1 ? : 0 : 0;
0 (01) 1 ? x 0 0 ? : 1 : 1;
0 (01) ? 0 x 0 0 ? : 1 : 1;
// 0 (01) 1 ? x 0 0 ? : 1 : 1;
0 (01) 1 1 x 0 0 ? : ? : 1;
0 (0?) 1 ? x 0 0 ? : 1 : 1;
0 (0?) ? 0 x 0 0 ? : 1 : 1;
// 0 (0?) 1 ? x 0 0 ? : 1 : 1;
0 (?1) 1 ? x 0 0 ? : 1 : 1;
0 (?1) ? 0 x 0 0 ? : 1 : 1;
// 0 (?1) 1 ? x 0 0 ? : 1 : 1;
? ? ? ? 0 (?x) ? ? : 0 : 0;
? ? ? ? (?x) 0 ? ? : 1 : 1;
0 (?1) 1 ? ? 0 0 ? : 1 : 1;
0 (?1) 0 ? 0 ? ? ? : 0 : 0;
0 (0?) 1 ? ? 0 0 ? : 1 : 1;
0 (0?) 0 ? 0 ? ? ? : 0 : 0;
// inverted clk
1 (10) ? ? 0 0 1 ? : ? : 0;
1 (x0) ? ? 0 0 1 ? : 0 : 0;
1 (x0) ? ? 0 0 1 ? : 1 : x;
1 (1x) ? ? 0 0 1 ? : 0 : 0;
1 (1x) ? ? 0 0 1 ? : 1 : x;
1 (10) 0 1 0 0 0 ? : ? : 0;
1 (10) 1 1 0 0 0 ? : ? : 1;
1 (10) x 1 0 0 0 ? : ? : x;
1 (10) 0 x 0 0 0 ? : 0 : 0;
1 (10) 1 x 0 0 0 ? : 1 : 1;
1 (??) ? 0 0 0 0 ? : ? : -;
1 (0?) ? ? 0 0 ? ? : ? : -;
1 (?1) ? ? 0 0 ? ? : ? : -;
1 (10) ? 0 0 0 x ? : 0 : 0;
1 (10) 0 1 0 0 x ? : ? : 0;
// 1 (10) ? 0 0 0 0 ? : 1 : 1;
// 1 (10) 1 1 0 0 0 ? : ? : 1;
1 (?0) ? 0 0 0 x ? : 0 : 0;
// 1 (?0) ? 0 0 0 0 ? : 1 : 1;
1 (1?) ? 0 0 0 x ? : 0 : 0;
// 1 (1?) ? 0 0 0 0 ? : 1 : 1;
1 (10) 0 ? 0 x 0 ? : 0 : 0;
1 (10) ? 0 0 x x ? : 0 : 0;
1 (10) 0 ? 0 x x ? : 0 : 0;
1 (10) ? ? 0 x 1 ? : ? : 0;
1 (10) 0 1 0 x ? ? : ? : 0;
1 (1?) 0 ? 0 x 0 ? : 0 : 0;
1 (1?) ? 0 0 x x ? : 0 : 0;
1 (1?) 0 ? 0 x x ? : 0 : 0;
1 (1?) ? ? 0 x 1 ? : 0 : 0;
1 (?0) 0 ? 0 x 0 ? : 0 : 0;
1 (?0) ? 0 0 x x ? : 0 : 0;
1 (?0) 0 ? 0 x x ? : 0 : 0;
1 (?0) ? ? 0 x 1 ? : 0 : 0;
1 (10) 1 ? x 0 0 ? : 1 : 1;
1 (10) ? 0 x 0 0 ? : 1 : 1;
// 1 (10) 1 ? x 0 0 ? : 1 : 1;
1 (10) 1 1 x 0 0 ? : ? : 1;
1 (1?) 1 ? x 0 0 ? : 1 : 1;
1 (1?) ? 0 x 0 0 ? : 1 : 1;
// 1 (1?) 1 ? x 0 0 ? : 1 : 1;
1 (?0) 1 ? x 0 0 ? : 1 : 1;
1 (?0) ? 0 x 0 0 ? : 1 : 1;
// 1 (?0) 1 ? x 0 0 ? : 1 : 1;
1 (?0) 1 ? ? 0 0 ? : 1 : 1;
1 (?0) 0 ? 0 ? ? ? : 0 : 0;
1 (1?) 1 ? ? 0 0 ? : 1 : 1;
1 (1?) 0 ? 0 ? ? ? : 0 : 0;
// either
? ? (??) ? ? ? ? ? : ? : -;
? ? ? (??) ? ? ? ? : ? : -;
? ? ? ? (?0) ? ? ? : ? : -;
? ? ? ? x (?0) ? ? : ? : x;
? ? ? ? 0 (?0) ? ? : ? : -;
? ? ? ? ? ? (??) ? : ? : -;
? ? ? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FDSE.v 0000664 0000000 0000000 00000031121 12327044266 0022141 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / D Flip-Flop with Synchronous Reset and Set and Clock Enable
// /___/ /\ Filename : FDSE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDSE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_S_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input S
);
wire o_out;
wire D_dly, C_dly, CE_dly, S_dly;
wire D_in, C_in, CE_in, S_in;
wire IS_C_INVERTED_BIN;
wire IS_D_INVERTED_BIN;
wire IS_S_INVERTED_BIN;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
`ifdef XIL_TIMING
wire ni, ngsr, nset, in_out;
wire in_clk_enable, ce_clk_enable, set_clk_enable;
wire in_clk_enable1, ce_clk_enable1, set_clk_enable1;
`endif
tri0 GSR = glbl.GSR;
assign Q = q_out;
`ifdef XIL_TIMING
not (ni, D_in);
not (nset, S_in);
not (ngsr, GSR);
xor (in_out, D_in, Q);
and (in_clk_enable, ngsr, nset, CE_in);
and (ce_clk_enable, ngsr, nset, in_out);
and (set_clk_enable, ngsr, CE_in, ni);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign set_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : set_clk_enable;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR)
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
set_int = 0;
rst_int = 0;
end
sffsrce_fdse (o_out, IS_C_INVERTED_BIN, C_dly, D_in, CE_in, set_int, rst_int, S_in, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign C_dly = C;
assign CE_dly = CE;
assign D_dly = D;
assign S_dly = S;
`endif
assign IS_C_INVERTED_BIN = IS_C_INVERTED;
assign IS_D_INVERTED_BIN = IS_D_INVERTED;
assign IS_S_INVERTED_BIN = IS_S_INVERTED;
assign CE_in = CE_dly ;
assign D_in = D_dly ^ IS_D_INVERTED_BIN;
assign S_in = S_dly ^ IS_S_INVERTED_BIN;
specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$setuphold (posedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (posedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (posedge C, posedge S &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,S_dly);
$setuphold (posedge C, negedge S &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,S_dly);
$period (posedge C &&& CE, 0:0:0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$setuphold (negedge C, posedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, negedge CE &&& (ce_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,CE_dly);
$setuphold (negedge C, posedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, negedge D &&& (in_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,D_dly);
$setuphold (negedge C, posedge S &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,S_dly);
$setuphold (negedge C, negedge S &&& (set_clk_enable1!=0), 0:0:0, 0:0:0, notifier,,,C_dly,S_dly);
$period (negedge C &&& CE, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive sffsrce_fdse (q, ici, clk, d, ce, set, rst, sset, notifier);
output q; reg q;
input ici, clk, d, ce, set, rst, sset, notifier;
table
// ici clk d ce set rst sset notifier q q+;
//either
? ? ? ? 1 0 ? ? : ? : 1;
? ? ? ? ? 1 ? ? : ? : 0;
//straight clk
0 (01) ? ? 0 0 1 ? : ? : 1;
0 (x1) ? ? 0 0 1 ? : 1 : 1;
0 (x1) ? ? 0 0 1 ? : 0 : x;
0 (0x) ? ? 0 0 1 ? : 1 : 1;
0 (0x) ? ? 0 0 1 ? : 0 : x;
0 (01) 0 1 0 0 0 ? : ? : 0;
0 (01) 1 1 0 0 0 ? : ? : 1;
0 (01) x 1 0 0 0 ? : ? : x;
0 (01) 0 x 0 0 0 ? : 0 : 0;
0 (01) 1 x 0 0 0 ? : 1 : 1;
? (??) ? 0 0 0 0 ? : ? : -;
0 (1?) ? ? 0 0 ? ? : ? : -;
0 (?0) ? ? 0 0 ? ? : ? : -;
// 0 (01) ? 0 0 0 0 ? : 0 : 0;
// 0 (01) 0 1 0 0 0 ? : ? : 0;
0 (01) ? 0 0 0 x ? : 1 : 1;
0 (01) 1 1 0 0 x ? : ? : 1;
// 0 (?1) ? 0 0 0 0 ? : 0 : 0;
0 (?1) ? 0 0 0 x ? : 1 : 1;
// 0 (0?) ? 0 0 0 0 ? : 0 : 0;
0 (0?) ? 0 0 0 x ? : 1 : 1;
0 (01) 0 ? 0 x 0 ? : 0 : 0;
0 (01) ? 0 0 x 0 ? : 0 : 0;
// 0 (01) 0 ? 0 x 0 ? : 0 : 0;
0 (01) 0 1 0 x 0 ? : ? : 0;
0 (0?) 0 ? 0 x 0 ? : 0 : 0;
0 (0?) ? 0 0 x 0 ? : 0 : 0;
// 0 (0?) 0 ? 0 x 0 ? : 0 : 0;
0 (?1) 0 ? 0 x 0 ? : 0 : 0;
0 (?1) ? 0 0 x 0 ? : 0 : 0;
// 0 (?1) 0 ? 0 x 0 ? : 0 : 0;
0 (01) ? 0 x 0 x ? : 1 : 1;
0 (01) 1 ? x 0 x ? : 1 : 1;
0 (01) ? ? x 0 1 ? : ? : 1;
0 (01) 1 1 x 0 ? ? : ? : 1;
0 (0?) 1 ? x 0 0 ? : 1 : 1;
0 (0?) ? 0 x 0 x ? : 1 : 1;
0 (0?) 1 ? x 0 x ? : 1 : 1;
0 (0?) ? ? x 0 1 ? : 1 : 1;
0 (?1) 1 ? x 0 0 ? : 1 : 1;
0 (?1) ? 0 x 0 x ? : 1 : 1;
0 (?1) 1 ? x 0 x ? : 1 : 1;
0 (?1) ? ? x 0 1 ? : 1 : 1;
? ? ? ? 0 (?x) ? ? : 0 : 0;
? ? ? ? (?x) 0 ? ? : 1 : 1;
0 (?1) 1 ? ? 0 ? ? : 1 : 1;
0 (?1) 0 ? 0 ? 0 ? : 0 : 0;
0 (0?) 1 ? ? 0 ? ? : 1 : 1;
0 (0?) 0 ? 0 ? 0 ? : 0 : 0;
//inv clk
1 (10) ? ? 0 0 1 ? : ? : 1;
1 (x0) ? ? 0 0 1 ? : 1 : 1;
1 (x0) ? ? 0 0 1 ? : 0 : x;
1 (1x) ? ? 0 0 1 ? : 1 : 1;
1 (1x) ? ? 0 0 1 ? : 0 : x;
1 (10) 0 1 0 0 0 ? : ? : 0;
1 (10) 1 1 0 0 0 ? : ? : 1;
1 (10) x 1 0 0 0 ? : ? : x;
1 (10) 0 x 0 0 0 ? : 0 : 0;
1 (10) 1 x 0 0 0 ? : 1 : 1;
// ? (??) ? 0 0 0 0 ? : ? : -;
1 (0?) ? ? 0 0 ? ? : ? : -;
1 (?1) ? ? 0 0 ? ? : ? : -;
// 1 (10) ? 0 0 0 0 ? : 0 : 0;
// 1 (10) 0 1 0 0 0 ? : ? : 0;
1 (10) ? 0 0 0 x ? : 1 : 1;
1 (10) 1 1 0 0 x ? : ? : 1;
// 1 (?0) ? 0 0 0 0 ? : 0 : 0;
1 (?0) ? 0 0 0 x ? : 1 : 1;
// 1 (1?) ? 0 0 0 0 ? : 0 : 0;
1 (1?) ? 0 0 0 x ? : 1 : 1;
1 (10) 0 ? 0 x 0 ? : 0 : 0;
1 (10) ? 0 0 x 0 ? : 0 : 0;
// 1 (10) 0 ? 0 x 0 ? : 0 : 0;
1 (10) 0 1 0 x 0 ? : ? : 0;
1 (1?) 0 ? 0 x 0 ? : 0 : 0;
1 (1?) ? 0 0 x 0 ? : 0 : 0;
// 1 (1?) 0 ? 0 x 0 ? : 0 : 0;
1 (?0) 0 ? 0 x 0 ? : 0 : 0;
1 (?0) ? 0 0 x 0 ? : 0 : 0;
// 1 (?0) 0 ? 0 x 0 ? : 0 : 0;
1 (10) ? 0 x 0 x ? : 1 : 1;
1 (10) 1 ? x 0 x ? : 1 : 1;
1 (10) ? ? x 0 1 ? : ? : 1;
1 (10) 1 1 x 0 ? ? : ? : 1;
1 (1?) 1 ? x 0 0 ? : 1 : 1;
1 (1?) ? 0 x 0 x ? : 1 : 1;
1 (1?) 1 ? x 0 x ? : 1 : 1;
1 (1?) ? ? x 0 1 ? : 1 : 1;
1 (?0) 1 ? x 0 0 ? : 1 : 1;
1 (?0) ? 0 x 0 x ? : 1 : 1;
1 (?0) 1 ? x 0 x ? : 1 : 1;
1 (?0) ? ? x 0 1 ? : 1 : 1;
// ? ? ? ? 0 (?x) ? ? : 0 : 0;
// ? ? ? ? (?x) 0 ? ? : 1 : 1;
1 (?0) 1 ? ? 0 ? ? : 1 : 1;
1 (?0) 0 ? 0 ? 0 ? : 0 : 0;
1 (1?) 1 ? ? 0 ? ? : 1 : 1;
1 (1?) 0 ? 0 ? 0 ? : 0 : 0;
//either
? ? (??) ? ? ? ? ? : ? : -;
? ? ? (??) ? ? ? ? : ? : -;
? ? ? ? (?0) ? ? ? : ? : -;
? ? ? ? x (?0) ? ? : ? : x;
? ? ? ? 0 (?0) ? ? : ? : -;
? ? ? ? ? ? (??) ? : ? : -;
? ? ? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FIFO18E1.v 0000664 0000000 0000000 00000446040 12327044266 0022514 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2008 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 18K-Bit FIFO
// /___/ /\ Filename : FIFO18E1.v
// \ \ / \ Timestamp : Tue Mar 18 16:55:14 PDT 2008
// \___\/\___\
//
// Revision:
// 03/18/08 - Initial version.
// 07/10/08 - IR476500 Add INIT parameter support, sync with FIFO36 internal
// 08/22/08 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO18_36. (IR 479958)
// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware.
// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127).
// 04/29/09 - Fixed timing violation for asynchronous reset (CR 519016).
// 10/07/09 - Fixed reset behavior (CR 532794).
// 10/23/09 - Fixed RST and RSTREG (CR 537067).
// 06/30/10 - Updated RESET behavior and added SIM_DEVICE (CR 567515).
// 07/16/10 - Fixed RESET behavior during startup (CR 568626).
// 08/19/10 - Fixed RESET DRC during startup (CR 570708).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 12/02/10 - Added warning message for 7SERIES Aysnc mode (CR 584052).
// 12/07/10 - Error out if no reset before first use of the fifo (CR 583638).
// 01/12/11 - updated warning message for 7SERIES Aysnc mode (CR 589721).
// 05/11/11 - Fixed DO not suppose to be reseted when RST asserted (CR 586526).
// 05/26/11 - Update Aysnc fifo behavior (CR 599680).
// 06/06/11 - Fixed RST in standard mode (CR 613216).
// 06/07/11 - Update DRC equation for ALMOST_FULL_OFFSET (CR 611057).
// 06/09/11 - Fixed GSR behavior (CR 611989).
// 06/13/11 - Added setup/hold timing check for RST (CR 606107).
// 07/07/11 - Fixed Full flag (CR 615773).
// 08/26/11 - Fixed FULL and ALMOSTFULL during initial time (CR 622163).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/08/12 - Added DRC to check WREN/RDEN after RST deassertion (CR 644571).
// 05/16/12 - Added support of negative setup/hold/recovery/removal timing (CR 639991).
// 11/05/12 - Fixed full flag in async mode with sync clocks (CR 677254).
// 01/15/13 - Fixed index out of bound warnings for parity (CR 694713).
// 07/18/13 - Added invertible pins support (CR 715417).
// 08/01/13 - Fixed async mode with sync clocks (CR 728728).
// 10/31/13 - Fixed flags in async mode with sync clocks (CR 718734, 724006).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module FIFO18E1 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR,
DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO18";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter INIT = 36'h0;
parameter IS_RDCLK_INVERTED = 1'b0;
parameter IS_RDEN_INVERTED = 1'b0;
parameter IS_RSTREG_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_WRCLK_INVERTED = 1'b0;
parameter IS_WREN_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // XIL_TIMING
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL = 36'h0;
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [11:0] RDCOUNT;
output RDERR;
output [11:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
tri0 GSR = glbl.GSR;
wire dangle_out, dangle_out1, dangle_out1_1, dangle_out1_2;
wire [3:0] dangle_out4;
wire [7:0] dangle_out8;
wire [31:0] dangle_out32;
reg [11:0] wrcount_out, rdcount_out;
reg almostempty_out, almostfull_out, empty_out, full_out;
reg rderr_out, wrerr_out;
wire almostempty_wire, empty_wire, rderr_wire;
wire almostfull_wire, full_wire, wrerr_wire;
wire [11:0] wrcount_wire, rdcount_wire;
reg notifier, notifier_wrclk, notifier_rdclk;
reg [31:0] do_out;
reg [3:0] dop_out;
wire [31:0] do_wire;
wire [3:0] dop_wire;
reg finish_error = 0;
wire [31:0] di_in, DI_dly;
wire [3:0] dip_in, DIP_dly;
wire rdclk_in, rdclk_inv, RDCLK_dly;
wire rden_in, rden_inv, RDEN_dly;
wire regce_in, REGCE_dly;
wire rst_in, rst_inv, RST_dly;
wire rstreg_in, rstreg_inv, RSTREG_dly;
wire wrclk_in, wrclk_inv, WRCLK_dly;
wire wren_in, wren_inv, WREN_dly;
`ifdef XIL_TIMING
assign di_in = DI_dly;
assign dip_in = DIP_dly;
assign rdclk_inv = RDCLK_dly;
assign rden_inv = RDEN_dly;
assign regce_in = REGCE_dly;
assign rst_inv = RST_dly;
assign rstreg_inv = RSTREG_dly;
assign wrclk_inv = WRCLK_dly;
assign wren_inv = WREN_dly;
`endif // XIL_TIMING
`ifndef XIL_TIMING
assign di_in = DI; // XIL_TIMING
assign dip_in = DIP; // XIL_TIMING
assign rdclk_inv = RDCLK; // XIL_TIMING
assign rden_inv = RDEN; // XIL_TIMING
assign regce_in = REGCE; // XIL_TIMING
assign rst_inv = RST; // XIL_TIMING
assign rstreg_inv = RSTREG; // XIL_TIMING
assign wrclk_inv = WRCLK; // XIL_TIMING
assign wren_inv = WREN; // XIL_TIMING
`endif // `ifndef XIL_TIMING
assign rdclk_in = rdclk_inv ^ IS_RDCLK_INVERTED;
assign rden_in = rden_inv ^ IS_RDEN_INVERTED;
assign rstreg_in = rstreg_inv ^ IS_RSTREG_INVERTED;
assign rst_in = rst_inv ^ IS_RST_INVERTED;
assign wrclk_in = wrclk_inv ^ IS_WRCLK_INVERTED;
assign wren_in = wren_inv ^ IS_WREN_INVERTED;
initial begin
case (FIFO_MODE)
"FIFO18" : ;
"FIFO18_36" : if (DATA_WIDTH != 36) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 36 when attribute FIFO_MODE = FIFO18_36.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are FIFO18 or FIFO18_36.", FIFO_MODE);
finish_error = 1;
end
endcase // case(FIFO_MODE)
case (DATA_WIDTH)
4, 9, 18 : ;
36 : if (FIFO_MODE != "FIFO18_36") begin
$display("DRC Error : The attribute FIFO_MODE must be set to FIFO18_36 when attribute DATA_WIDTH = 36.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH);
finish_error = 1;
end
endcase
if (!((IS_RDCLK_INVERTED >= 1'b0) && (IS_RDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RDEN_INVERTED >= 1'b0) && (IS_RDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDEN_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RSTREG_INVERTED >= 1'b0) && (IS_RSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREG_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RST_INVERTED >= 1'b0) && (IS_RST_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RST_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WRCLK_INVERTED >= 1'b0) && (IS_WRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WRCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WREN_INVERTED >= 1'b0) && (IS_WREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WREN_INVERTED);
finish_error = 1'b1;
end
if (finish_error == 1)
$finish;
end // initial begin
// Matching HW
localparam init_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,INIT[35:34],INIT[17:16],INIT[33:18],INIT[15:0]} : {36'h0, INIT};
localparam srval_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,SRVAL[35:34],SRVAL[17:16],SRVAL[33:18],SRVAL[15:0]} : {36'h0, SRVAL};
FF18_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
.DATA_WIDTH(DATA_WIDTH),
.DO_REG(DO_REG),
.EN_SYN(EN_SYN),
.FIFO_MODE(FIFO_MODE),
.FIFO_SIZE(18),
.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
.INIT({36'h0,init_sdp}),
.SIM_DEVICE(SIM_DEVICE),
.SRVAL({36'h0,srval_sdp}))
INT_FIFO (.ALMOSTEMPTY(almostempty_wire),
.ALMOSTFULL(almostfull_wire),
.DBITERR(dangle_out),
.DI({32'b0,di_in}),
.DIP({4'b0,dip_in}),
.DO({dangle_out32,do_wire}),
.DOP({dangle_out4,dop_wire}),
.ECCPARITY(dangle_out8),
.EMPTY(empty_wire),
.FULL(full_wire),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDCLK(rdclk_in),
.RDCOUNT({dangle_out1,rdcount_wire}),
.RDEN(rden_in),
.RDERR(rderr_wire),
.REGCE(regce_in),
.RST(rst_in),
.RSTREG(rstreg_in),
.SBITERR(dangle_out1_2),
.WRCLK(wrclk_in),
.WRCOUNT({dangle_out1_1,wrcount_wire}),
.WREN(wren_in),
.WRERR(wrerr_wire));
//*** Timing Checks Start here
assign DO = do_out;
assign DOP = dop_out;
assign ALMOSTFULL = almostfull_out;
assign FULL = full_out;
assign WRERR = wrerr_out;
assign WRCOUNT = wrcount_out;
assign ALMOSTEMPTY = almostempty_out;
assign EMPTY = empty_out;
assign RDERR = rderr_out;
assign RDCOUNT = rdcount_out;
always @(almostfull_wire or wrclk_in) almostfull_out = almostfull_wire;
always @(full_wire or wrclk_in) full_out = full_wire;
always @(wrerr_wire or wrclk_in) wrerr_out = wrerr_wire;
always @(wrcount_wire or wrclk_in) wrcount_out = wrcount_wire;
always @(almostempty_wire or rdclk_in) almostempty_out = almostempty_wire;
always @(empty_wire or rdclk_in) empty_out = empty_wire;
always @(rderr_wire or rdclk_in) rderr_out = rderr_wire;
always @(rdcount_wire or rdclk_in) rdcount_out = rdcount_wire;
always @(do_wire or rdclk_in) do_out = do_wire;
always @(dop_wire or rdclk_in) dop_out = dop_wire;
`ifdef XIL_TIMING
always @(notifier) begin
do_out <= 32'bx;
dop_out <= 4'bx;
end
always @(notifier_wrclk) begin
almostfull_out <= 1'bx;
full_out <= 1'bx;
wrcount_out <= 12'bx;
wrerr_out <= 1'bx;
end
always @(notifier_rdclk) begin
almostempty_out <= 1'bx;
empty_out <= 1'bx;
rdcount_out <= 12'bx;
rderr_out <= 1'bx;
end
not (nrst, RST);
and (wren_enable, WREN, nrst);
`endif // `ifdef XIL_TIMING
specify
(RDCLK *> DO) = (100:100:100, 100:100:100);
(RDCLK *> DOP) = (100:100:100, 100:100:100);
(RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100);
(RDCLK => EMPTY) = (100:100:100, 100:100:100);
(RDCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(RDCLK => RDERR) = (100:100:100, 100:100:100);
(WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100);
(WRCLK => FULL) = (100:100:100, 100:100:100);
(WRCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(WRCLK => WRERR) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(RST => ALMOSTEMPTY) = (0:0:0, 0:0:0);
(RST => ALMOSTFULL) = (0:0:0, 0:0:0);
(RST => EMPTY) = (0:0:0, 0:0:0);
(RST => FULL) = (0:0:0, 0:0:0);
(RST *> RDCOUNT) = (0:0:0, 0:0:0);
(RST => RDERR) = (0:0:0, 0:0:0);
(RST *> WRCOUNT) = (0:0:0, 0:0:0);
(RST => WRERR) = (0:0:0, 0:0:0);
$setuphold (posedge RDCLK, negedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, posedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, negedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, posedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, negedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, posedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, negedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, posedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, negedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, posedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, posedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, negedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (posedge WRCLK, posedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, negedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, posedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, posedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, negedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, posedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$recrem (negedge RST, posedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk,,, RST_dly, RDCLK_dly);
$recrem (negedge RST, posedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk,,, RST_dly, WRCLK_dly);
$recrem (negedge RST, negedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk,,, RST_dly, RDCLK_dly);
$recrem (negedge RST, negedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk,,, RST_dly, WRCLK_dly);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // FIFO18E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. FIFO18E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module FF18_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR,
DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
output ALMOSTEMPTY;
output ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output SBITERR;
output [12:0] WRCOUNT;
output WRERR;
input [63:0] DI;
input [7:0] DIP;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
input GSR;
input INJECTDBITERR;
input INJECTSBITERR;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO36";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter EN_ECC_WRITE = "FALSE";
parameter EN_ECC_READ = "FALSE";
parameter INIT = 72'h0;
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL = 72'h0;
reg [63:0] do_in = 64'b0;
reg [63:0] do_out = 64'b0;
reg [63:0] do_outreg = 64'b0;
reg [63:0] do_out_mux = 64'b0;
wire [63:0] do_out_out;
reg [7:0] dop_in = 8'b0, dop_out = 8'b0;
wire [7:0] dop_out_out;
reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0;
reg almostempty_out = 1'b1, almostfull_out = 1'b0, empty_out = 1'b1;
reg full_out = 1'b0, rderr_out = 0, wrerr_out = 0;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [71:0] ecc_bit_position;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, dop_buf = 8'b0, dip_ecc, dip_int;
reg [63:0] do_buf = 64'b0, di_in_ecc_corrected;
reg [7:0] syndrome, dip_in_ecc_corrected;
wire [63:0] di_in;
wire [7:0] dip_in;
wire rdclk_in, rden_in, rst_in, rstreg_in, wrclk_in, wren_in;
wire regce_in, gsr_in;
wire injectdbiterr_in, injectsbiterr_in;
wire full_v3;
reg rden_reg, wren_reg;
reg fwft;
integer addr_limit, rd_prefetch = 0;
integer wr1_addr = 0;
integer viol_rst_rden = 0, viol_rst_wren = 0;
reg [3:0] rden_rdckreg = 4'b0, wren_wrckreg = 4'b0;
reg [12:0] rd_addr = 0;
reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0;
reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0;
reg wr1_flag = 0, awr_flag = 0;
reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111;
reg [3:0] full_int = 4'b0000;
reg [3:0] empty_ram = 4'b1111;
reg [8:0] i, j;
reg rst_tmp1 = 0, rst_tmp2 = 0;
reg [4:0] rst_rdckreg = 5'b0, rst_wrckreg = 5'b0;
reg rst_rdclk_flag = 0, rst_wrclk_flag = 0;
reg en_ecc_write_int, en_ecc_read_int, finish_error = 0;
reg [63:0] di_ecc_col;
reg first_rst_flag = 0;
reg rm1wp1_eq = 1'b0, rm1w_eq = 1'b0;
reg awr_flag_sync_1 = 0, awr_flag_sync_2 = 0;
integer after_rst_rdclk = 0, after_rst_wrclk = 0;
integer count_freq_rdclk = 0, count_freq_wrclk = 0;
integer roundup_int_period_rdclk_wrclk, roundup_int_period_wrclk_rdclk;
integer s7_roundup_int_period_rdclk_wrclk;
time rise_rdclk, period_rdclk, rise_wrclk, period_wrclk;
integer fwft_prefetch_flag = 1;
real real_period_rdclk, real_period_wrclk;
reg rst_trans_rden_1 = 1'b0, rst_trans_rden_2 = 1'b0;
reg rst_trans_wren_1 = 1'b0, rst_trans_wren_2 = 1'b0;
reg after_rst_rden_flag = 1'b0, after_rst_wren_flag = 1'b0, after_rst_x_flag = 1'b0;
time time_wrclk, time_rdclk;
reg sync_clk_async_mode = 1'b0;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameter is changed.
parameter integer FIFO_SIZE = 36;
// xilinx_internal_parameter off
localparam counter_width = (FIFO_SIZE == 36) ? ((DATA_WIDTH == 4) ? 12 :
(DATA_WIDTH == 9) ? 11 : (DATA_WIDTH == 18) ? 10 :
(DATA_WIDTH == 36) ? 9 : (DATA_WIDTH == 72) ? 8 : 12)
: ((DATA_WIDTH == 4) ? 11 : (DATA_WIDTH == 9) ? 10 :
(DATA_WIDTH == 18) ? 9 : (DATA_WIDTH == 36) ? 8 : 11);
reg [counter_width:0] rdcount_out = 13'b0, wr_addr = 13'b0;
reg [counter_width:0] ae_empty, ae_full;
reg [counter_width:0] rdcount_out_sync_3 = 13'h1fff, rdcount_out_sync_2 = 13'h1fff;
reg [counter_width:0] rdcount_out_sync_1 = 13'h1fff, rdcount_out_m1 = 13'h1fff;
reg [counter_width:0] wr_addr_sync_3 = 13'b0, wr_addr_sync_2 = 13'b0, wr_addr_sync_1 = 13'b0;
// Determinte memory size
localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0;
localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0;
localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0;
localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0;
localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0;
localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 :
(DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0;
localparam memp_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 1 :
(DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0;
reg [mem_width : 0] mem [mem_depth : 0];
reg [memp_width : 0] memp [memp_depth : 0];
reg sync;
// Input and output ports
assign di_in = DI;
assign dip_in = DIP;
assign DO = do_out_out;
assign DOP = dop_out_out;
assign rdclk_in = RDCLK;
assign regce_in = REGCE;
assign rden_in = RDEN;
assign rst_in = RST;
assign rstreg_in = RSTREG;
assign wrclk_in = WRCLK;
assign wren_in = WREN;
assign gsr_in = GSR;
assign ALMOSTEMPTY = almostempty_out;
assign ALMOSTFULL = almostfull_out;
assign EMPTY = empty_out;
assign FULL = full_out;
assign RDERR = rderr_out;
assign WRERR = wrerr_out;
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
assign RDCOUNT = rdcount_out_out;
assign WRCOUNT = wr_addr_out;
assign injectdbiterr_in = INJECTDBITERR;
assign injectsbiterr_in = INJECTSBITERR;
assign full_v3 = (rm1w_eq || (rm1wp1_eq && (wren_in && !full_out))) ? 1 : 0;
initial begin
// Determine address limit
case (DATA_WIDTH)
4 : begin
if (FIFO_SIZE == 36)
addr_limit = 8192;
else
addr_limit = 4096;
end
9 : begin
if (FIFO_SIZE == 36)
addr_limit = 4096;
else
addr_limit = 2048;
end
18 : begin
if (FIFO_SIZE == 36)
addr_limit = 2048;
else
addr_limit = 1024;
end
36 : begin
if (FIFO_SIZE == 36)
addr_limit = 1024;
else
addr_limit = 512;
end
72 : begin
addr_limit = 512;
end
default :
begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH);
finish_error = 1;
end
endcase
case (EN_SYN)
"FALSE" : sync = 0;
"TRUE" : sync = 1;
default : begin
$display("Attribute Syntax Error : The attribute EN_SYN on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN);
finish_error = 1;
end
endcase // case(EN_SYN)
case (FIRST_WORD_FALL_THROUGH)
"FALSE" : begin
fwft = 0;
if (EN_SYN == "FALSE") begin
ae_empty = ALMOST_EMPTY_OFFSET - 1;
ae_full = ALMOST_FULL_OFFSET;
end
else begin
ae_empty = ALMOST_EMPTY_OFFSET;
ae_full = ALMOST_FULL_OFFSET;
end
end
"TRUE" : begin
fwft = 1;
ae_empty = ALMOST_EMPTY_OFFSET - 2;
ae_full = ALMOST_FULL_OFFSET;
end
default : begin
$display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH);
finish_error = 1;
end
endcase
// DRC for fwft in sync mode
if (fwft == 1'b1 && EN_SYN == "TRUE") begin
$display("DRC Error : First word fall through is not supported in synchronous mode on FIFO18E1 instance %m.");
finish_error = 1;
end
if (EN_SYN == "FALSE" && DO_REG == 0) begin
$display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FIFO18E1 instance %m.");
finish_error = 1;
end
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int <= 1;
"FALSE" : en_ecc_write_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int <= 1;
"FALSE" : en_ecc_read_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FIFO18E1 is configured in the ECC mode.");
finish_error = 1;
end
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
$finish;
end // initial begin
// GSR and RST
always @(gsr_in)
if (gsr_in === 1'b1) begin
if (DO_REG == 1'b1 && sync == 1'b1) begin
assign do_out = INIT[0 +: mem_width+1];
assign dop_out = INIT[mem_width+1 +: memp_width+1];
assign do_outreg = INIT[0 +: mem_width+1];
assign dop_outreg = INIT[mem_width+1 +: memp_width+1];
assign do_in = INIT[0 +: mem_width+1];
assign dop_in = INIT[mem_width+1 +: memp_width+1];
assign do_buf = INIT[0 +: mem_width+1];
assign dop_buf = INIT[mem_width+1 +: memp_width+1];
end
else begin
assign do_out = 64'b0;
assign dop_out = 8'b0;
assign do_outreg = 64'b0;
assign dop_outreg = 8'b0;
assign do_in = 64'b0;
assign dop_in = 8'b0;
assign do_buf = 64'b0;
assign dop_buf = 8'b0;
end
end
else if (gsr_in === 1'b0) begin
deassign do_out;
deassign dop_out;
deassign do_outreg;
deassign dop_outreg;
deassign do_in;
deassign dop_in;
deassign do_buf;
deassign dop_buf;
end
always @(rst_in)
if (rst_in === 1'b1) begin
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'b1;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'b0;
assign empty_ram = 4'b1111;
assign empty_out = 1'b1;
assign full_int = 4'b0000;
assign full_out = 1'b0;
assign rdcount_out = 13'b0;
assign rdcount_out_out = 13'b0;
assign wr_addr_out = 13'b0;
assign rderr_out = 0;
assign wrerr_out = 0;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign wr_addr = 0;
assign wr1_addr = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'b1111111111111;
assign rdcount_out_m1 = 13'b1111111111111;
assign wr_addr_sync_3 = 13'b0;
end
else if (rst_in === 1'b0) begin
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign empty_out;
deassign full_int;
deassign full_out;
deassign rdcount_out;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign rderr_out;
deassign wrerr_out;
deassign rd_addr;
deassign rd_prefetch;
deassign wr_addr;
deassign wr1_addr;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end
// DRC
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
always @(posedge rdclk_in) begin
if (rst_in === 1'b1 && rden_in === 1'b1)
viol_rst_rden = 1;
if (rst_in === 1'b0)
rden_rdckreg[3:0] <= {rden_rdckreg[2:0], rden_in};
if (rden_rdckreg == 4'h0) begin
rst_rdckreg[0] <= rst_in;
rst_rdckreg[1] <= rst_rdckreg[0] & rst_in;
rst_rdckreg[2] <= rst_rdckreg[1] & rst_in;
end
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
if (rst_in === 1'b1 && wren_in === 1'b1)
viol_rst_wren = 1;
if (rst_in === 1'b0)
wren_wrckreg[3:0] <= {wren_wrckreg[2:0], wren_in};
if (wren_wrckreg == 4'h0) begin
rst_wrckreg[0] <= rst_in;
rst_wrckreg[1] <= rst_wrckreg[0] & rst_in;
rst_wrckreg[2] <= rst_wrckreg[1] & rst_in;
end
end // always @ (posedge wrclk_in)
always @(rst_in) begin
rst_tmp1 = rst_in;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
end
if (((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
end // if (rst_in == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rden_rdckreg = 4'h0;
wren_wrckreg = 4'h0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (rst_in)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge rst_in)
rst_trans_rden_1 = rst_in;
always @(negedge rst_in)
if (rst_trans_rden_1 == 1'b1)
rst_trans_rden_2 = ~rst_in;
always @(posedge rdclk_in) begin
if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) begin
after_rst_rdclk = after_rst_rdclk + 1;
if (rden_in === 1'b1 && after_rst_rdclk <= 2) begin
after_rst_rden_flag = 1'b1;
end
else if (after_rst_rdclk >= 3) begin
after_rst_rdclk = 0;
rst_trans_rden_1 = 1'b0;
rst_trans_rden_2 = 1'b0;
if (after_rst_rden_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RDEN must be low for at least two RDCLK clock cycles after RST deasserted.", $stime);
after_rst_rden_flag = 1'b0;
after_rst_x_flag = 1'b1;
end
end
end // if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1)
end // always @ (posedge rdclk_in)
always @(posedge rst_in)
rst_trans_wren_1 = rst_in;
always @(negedge rst_in)
if (rst_trans_wren_1 == 1'b1)
rst_trans_wren_2 = ~rst_in;
always @(posedge wrclk_in) begin
if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) begin
after_rst_wrclk = after_rst_wrclk + 1;
if (wren_in === 1'b1 && after_rst_wrclk <= 2) begin
after_rst_wren_flag = 1'b1;
end
else if (after_rst_wrclk >= 3) begin
after_rst_wrclk = 0;
rst_trans_wren_1 = 1'b0;
rst_trans_wren_2 = 1'b0;
if (after_rst_wren_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. WREN must be low for at least two WRCLK clock cycles after RST deasserted.", $stime);
after_rst_wren_flag = 1'b0;
after_rst_x_flag = 1'b1;
end
end
end // if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1)
end // always @ (posedge wrclk_in)
always @(posedge after_rst_x_flag or negedge rst_in) begin
if (after_rst_x_flag == 1'b1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
after_rst_x_flag = 1'b0;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (rst_in == 1'b0)
end // always @ (posedge after_rst_x_flag or negedge rst_in)
always @(posedge rdclk_in) begin
if (rst_in === 1'b1 && rden_in === 1'b1)
viol_rst_rden = 1;
if (rden_in === 1'b0 && rst_in === 1'b1) begin
rst_rdckreg[0] <= rst_in;
rst_rdckreg[1] <= rst_rdckreg[0] & rst_in;
rst_rdckreg[2] <= rst_rdckreg[1] & rst_in;
rst_rdckreg[3] <= rst_rdckreg[2] & rst_in;
rst_rdckreg[4] <= rst_rdckreg[3] & rst_in;
end
else if (rden_in === 1'b1 && rst_in === 1'b1) begin
rst_rdckreg <= 5'b0;
end
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
if (rst_in === 1'b1 && wren_in === 1'b1)
viol_rst_wren = 1;
if (wren_in === 1'b0 && rst_in === 1'b1) begin
rst_wrckreg[0] <= rst_in;
rst_wrckreg[1] <= rst_wrckreg[0] & rst_in;
rst_wrckreg[2] <= rst_wrckreg[1] & rst_in;
rst_wrckreg[3] <= rst_wrckreg[2] & rst_in;
rst_wrckreg[4] <= rst_wrckreg[3] & rst_in;
end
else if (wren_in === 1'b1 && rst_in === 1'b1) begin
rst_wrckreg <= 5'b0;
end
end // always @ (posedge wrclk_in)
always @(rst_in) begin
rst_tmp1 = rst_in;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[4] & rst_rdckreg[3] & rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five RDCLK clock cycles, and RDEN must be low before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
end
if (((rst_wrckreg[4] & rst_wrckreg[3] & rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (rst_in == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (rst_in)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// DRC
always @(posedge rden_in or negedge gsr_in)
@(posedge rdclk_in)
if (first_rst_flag == 0 && rden_in == 1'b1 && gsr_in == 1'b0) begin
$display("DRC Error : A RESET cycle must be observerd before the first use of the FIFO instance %m which occurs at time %t.", $time);
end
always @(posedge wren_in or negedge gsr_in)
@(posedge wrclk_in)
if (first_rst_flag == 0 && wren_in == 1'b1 && gsr_in == 1'b0) begin
$display("DRC Error : A RESET cycle must be observerd before the first use of the FIFO instance %m which occurs at time %t.", $time);
end
always @(posedge rdclk_in) begin
count_freq_rdclk = count_freq_rdclk + 1;
if (count_freq_rdclk == 100)
rise_rdclk = $time;
else if (count_freq_rdclk == 101) begin
period_rdclk = $time - rise_rdclk;
if (count_freq_wrclk >= 101 && rst_in === 1'b0 && gsr_in === 1'b0) begin
// Setup ranges for almostempty
if (period_rdclk == period_wrclk) begin
if (EN_SYN == "FALSE") begin
if (SIM_DEVICE == "7SERIES") begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 6)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 6);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
$finish;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 5);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
$finish;
end
end // else: !if(fwft == 1'b0)
end // if (SIM_DEVICE == "7SERIES")
else begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
$finish;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
$finish;
end
end // else: !if(fwft == 1'b0)
end // else: !if(SIM_DEVICE == "7SERIES")
end // if (EN_SYN == "FALSE")
else begin
if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2);
$finish;
end
if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2);
$finish;
end
end // else: !if(EN_SYN == "FALSE")
end // if (period_rdclk == period_wrclk)
else begin
real_period_rdclk = period_rdclk * 1.0;
real_period_wrclk = period_wrclk * 1.0;
roundup_int_period_rdclk_wrclk = (real_period_rdclk / real_period_wrclk) + 0.499;
roundup_int_period_wrclk_rdclk = (real_period_wrclk / real_period_rdclk) + 0.499;
s7_roundup_int_period_rdclk_wrclk = (4.0 * (real_period_rdclk / real_period_wrclk)) + 0.499;
if (SIM_DEVICE == "7SERIES") begin
if (ALMOST_FULL_OFFSET > (addr_limit - (s7_roundup_int_period_rdclk_wrclk + 6))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((roundup(4 * (WRCLK frequency / RDCLK frequency))) + 6)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
$finish;
end
end
else begin
if (ALMOST_FULL_OFFSET > (addr_limit - ((3 * roundup_int_period_wrclk_rdclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (RDCLK frequency / WRCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
$finish;
end
if (ALMOST_EMPTY_OFFSET > (addr_limit - ((3 * roundup_int_period_rdclk_wrclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (WRCLK frequency / RDCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_EMPTY_OFFSET);
$finish;
end
end // else: !if(SIM_DEVICE == "7SERIES")
end // else: !if(period_rdclk == period_wrclk)
count_freq_rdclk = 0;
count_freq_wrclk = 0;
end // if (count_freq_wrclk >= 101 && count_freq_rdclk >= 101 && rst_in === 1'b0 && gsr_in === 1'b0)
end // if (count_freq_rdclk == 101)
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
count_freq_wrclk = count_freq_wrclk + 1;
if (count_freq_wrclk == 100)
rise_wrclk = $time;
else if (count_freq_wrclk == 101) begin
period_wrclk = $time - rise_wrclk;
end
end // always @ (posedge wrclk_in)
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
// read clock
always @(posedge rdclk_in) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (rden_in == 1'b1) begin
if (empty_out == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (empty_out == 1'b0)
end // if (rden_in == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
if (wren_in == 1'b1) begin
empty_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
empty_out = 1'b1;
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
almostempty_out = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
almostfull_out = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rden_reg = rden_in;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[3];
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[2] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync == 1'b0)
end // always @ (posedge rdclk_in)
// Write clock
always @(posedge wrclk_in) begin
// DRC
if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (wren_in == 1'b1) begin
if (full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (full_out == 1'b0)
end // if (wren_in == 1'b1)
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
if (rden_in == 1'b1) begin
full_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
full_out = 1'b1;
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
almostempty_out = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
almostfull_out = 1'b1;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wren_reg = wren_in;
if (wren_reg == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_reg == 1'b1 && full_out == 1'b0)
if (rst_in === 1'b0) begin
wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || full_out == 1'b1)
full_out = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b0)
end // always @ (posedge wrclk_in)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge rdclk_in)
time_rdclk = $time;
always @(posedge wrclk_in)
time_wrclk = $time;
always @(time_rdclk or time_wrclk)
if ((time_rdclk - time_wrclk == 0 || time_wrclk - time_rdclk == 0) && $time != 0)
sync_clk_async_mode = 1'b1;
// read clock
always @(posedge rdclk_in) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (rden_in == 1'b1) begin
if (empty_out == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (empty_out == 1'b0)
end // if (rden_in == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
if (wren_in == 1'b1) begin
empty_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
empty_out = 1'b1;
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
almostempty_out = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
almostfull_out = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wr_addr_sync_3 = wr_addr_sync_2;
wr_addr_sync_2 = wr_addr_sync_1;
wr_addr_sync_1 = wr_addr;
awr_flag_sync_2 = awr_flag_sync_1;
awr_flag_sync_1 = awr_flag;
if (sync_clk_async_mode == 1'b1) begin
rden_reg = rden_in;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[3];
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[2] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync_clk_async_mode == 1'b1)
else begin
if (fwft == 1'b0) begin
if (rden_in == 1'b1 && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (rden_in == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_in == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr && rd_addr != rdcount_out) || (rst_in === 1'b1 && fwft_prefetch_flag == 1)) begin
fwft_prefetch_flag = 0;
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (rden_in == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[0];
if (wr_addr_sync_3 - rdcount_out <= ae_empty)
almostempty_int[0] = 1'b1;
else
almostempty_int[0] = 1'b0;
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr_sync_2) && (rdcount_flag == awr_flag_sync_2)) begin
empty_ram[0] = 1'b1;
end
else begin
empty_ram[0] = 1'b0;
end
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge rdclk_in)
// Write clock
always @(posedge wrclk_in) begin
// DRC
if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (wren_in == 1'b1) begin
if (full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (full_out == 1'b0)
end // if (wren_in == 1'b1)
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
if (rden_in == 1'b1) begin
full_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
full_out = 1'b1;
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
almostempty_out = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
almostfull_out = 1'b1;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rdcount_out_sync_3 = rdcount_out_sync_2;
rdcount_out_sync_2 = rdcount_out_sync_1;
rdcount_out_sync_1 = rdcount_out_m1;
if (sync_clk_async_mode == 1'b1) begin
wren_reg = wren_in;
if (wren_reg == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_reg == 1'b1 && full_out == 1'b0)
if (rst_in === 1'b0) begin
wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || full_out == 1'b1)
full_out = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
// fix for 724006
if (rdcount_out - 1 == wr_addr && (wren_reg == 1'b1 || full_out == 1'b1))
full_out = full_int[1];
end // if (rst_in === 1'b0)
end // if (sync_clk_async_mode == 1'b1)
else begin
if (wren_in == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#0;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_in == 1'b1 && full_out == 1'b0)
rm1w_eq = (rdcount_out_sync_2 == wr_addr) ? 1 : 0;
if (wr_addr + 1 == addr_limit) // wr_addr(FF) + 1 != 0
rm1wp1_eq = (rdcount_out_sync_2 == 0) ? 1 : 0;
else
rm1wp1_eq = (rdcount_out_sync_2 == wr_addr + 1) ? 1 : 0;
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[0];
if (rdcount_out_sync_3 - wr_addr <= ae_full)
almostfull_int[0] = 1'b1;
else
almostfull_int[0] = 1'b0;
full_out = full_v3;
//fwft prefetch
if (empty_out == 1'b1 && wren_in === 1'b1 && fwft_prefetch_flag == 0)
fwft_prefetch_flag = 1;
end // if (rst_in === 1'b0)
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge wrclk_in)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// output register
always @(do_out or dop_out or do_outreg or dop_outreg) begin
if (sync == 1)
case (DO_REG)
0 : begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end
1 : begin
do_out_mux = do_outreg;
dop_out_mux = dop_outreg;
end
default : begin
$display("Attribute Syntax Error : The attribute DO_REG on FIFO18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG);
$finish;
end
endcase
else begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end // else: !if(sync == 1)
end // always @ (do_out or dop_out or do_outreg or dop_outreg)
// matching HW behavior to X the unused output bits
assign do_out_out = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]}
: (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]}
: (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]}
: (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]}
: (DATA_WIDTH == 72) ? do_out_mux
: do_out_mux;
// matching HW behavior to X the unused output bits
assign dop_out_out = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]}
: (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]}
: (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]}
: (DATA_WIDTH == 72) ? dop_out_mux
: 8'bx;
// matching HW behavior to pull up the unused output bits
always @(wr_addr) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : wr_addr_out = {1'b1, wr_addr[11:0]};
9 : wr_addr_out = {2'b11, wr_addr[10:0]};
18 : wr_addr_out = {3'b111, wr_addr[9:0]};
36 : wr_addr_out = {4'hf, wr_addr[8:0]};
default : wr_addr_out = wr_addr;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : wr_addr_out = wr_addr;
9 : wr_addr_out = {1'b1, wr_addr[11:0]};
18 : wr_addr_out = {2'b11, wr_addr[10:0]};
36 : wr_addr_out = {3'b111, wr_addr[9:0]};
72 : wr_addr_out = {4'hf, wr_addr[8:0]};
default : wr_addr_out = wr_addr;
endcase // case(DATA_WIDTH)
end // always @ (wr_addr)
// matching HW behavior to pull up the unused output bits
always @(rdcount_out) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : rdcount_out_out = {1'b1, rdcount_out[11:0]};
9 : rdcount_out_out = {2'b11, rdcount_out[10:0]};
18 : rdcount_out_out = {3'b111, rdcount_out[9:0]};
36 : rdcount_out_out = {4'hf, rdcount_out[8:0]};
default : rdcount_out_out = rdcount_out;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : rdcount_out_out = rdcount_out;
9 : rdcount_out_out = {1'b1, rdcount_out[11:0]};
18 : rdcount_out_out = {2'b11, rdcount_out[10:0]};
36 : rdcount_out_out = {3'b111, rdcount_out[9:0]};
72 : rdcount_out_out = {4'hf, rdcount_out[8:0]};
default : rdcount_out_out = rdcount_out;
endcase // case(DATA_WIDTH)
end // always @ (rdcount_out)
endmodule
`endcelldefine
// end of FF18_INTERNAL_VLOG - Note: Not an user primitvie
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FIFO18E2.v 0000664 0000000 0000000 00000173243 12327044266 0022517 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : FIFO18E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 11/30/2012 - intial
// 12/12/2012 - yaml update, 691724 and 691715
// 02/07/2013 - 699628 - correction to DO_PIPELINED mode
// 02/28/2013 - update to keep in sync with RAMB models
// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC.
// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY
// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there.
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FIFO18E2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter FIRST_WORD_FALL_THROUGH = "FALSE",
parameter [35:0] INIT = 36'h000000000,
parameter [0:0] IS_RDCLK_INVERTED = 1'b0,
parameter [0:0] IS_RDEN_INVERTED = 1'b0,
parameter [0:0] IS_RSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter [0:0] IS_WRCLK_INVERTED = 1'b0,
parameter [0:0] IS_WREN_INVERTED = 1'b0,
parameter integer PROG_EMPTY_THRESH = 256,
parameter integer PROG_FULL_THRESH = 256,
parameter RDCOUNT_TYPE = "RAW_PNTR",
parameter integer READ_WIDTH = 4,
parameter REGISTER_MODE = "UNREGISTERED",
parameter RSTREG_PRIORITY = "RSTREG",
parameter SLEEP_ASYNC = "FALSE",
parameter [35:0] SRVAL = 36'h000000000,
parameter WRCOUNT_TYPE = "RAW_PNTR",
parameter integer WRITE_WIDTH = 4
)(
output [31:0] CASDOUT,
output [3:0] CASDOUTP,
output CASNXTEMPTY,
output CASPRVRDEN,
output [31:0] DOUT,
output [3:0] DOUTP,
output EMPTY,
output FULL,
output PROGEMPTY,
output PROGFULL,
output [12:0] RDCOUNT,
output RDERR,
output RDRSTBUSY,
output [12:0] WRCOUNT,
output WRERR,
output WRRSTBUSY,
input [31:0] CASDIN,
input [3:0] CASDINP,
input CASDOMUX,
input CASDOMUXEN,
input CASNXTRDEN,
input CASOREGIMUX,
input CASOREGIMUXEN,
input CASPRVEMPTY,
input [31:0] DIN,
input [3:0] DINP,
input RDCLK,
input RDEN,
input REGCE,
input RST,
input RSTREG,
input SLEEP,
input WRCLK,
input WREN
);
// define constants
localparam MODULE_NAME = "FIFO18E2";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
localparam integer ADDR_WIDTH = 14;
localparam integer INIT_WIDTH = 36;
localparam integer D_WIDTH = 32;
localparam integer DP_WIDTH = 4;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_depth = 16384;
localparam memp_depth = 2048;
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CASCADE_ORDER_PARALLEL = 4;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam FIRST_WORD_FALL_THROUGH_FALSE = 0;
localparam FIRST_WORD_FALL_THROUGH_TRUE = 1;
localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam RDCOUNT_TYPE_RAW_PNTR = 0;
localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam RDCOUNT_TYPE_SYNC_PNTR = 3;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_9 = 8;
localparam REGISTER_MODE_DO_PIPELINED = 1;
localparam REGISTER_MODE_REGISTERED = 2;
localparam REGISTER_MODE_UNREGISTERED = 0;
localparam RSTREG_PRIORITY_REGCE = 1;
localparam RSTREG_PRIORITY_RSTREG = 0;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam WRCOUNT_TYPE_RAW_PNTR = 0;
localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam WRCOUNT_TYPE_SYNC_PNTR = 3;
localparam WRITE_WIDTH_18 = 16;
localparam WRITE_WIDTH_36 = 32;
localparam WRITE_WIDTH_4 = 4;
localparam WRITE_WIDTH_9 = 8;
`ifndef XIL_DR
localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH;
localparam [35:0] INIT_REG = INIT;
localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED;
localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED;
localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED;
localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED;
localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH;
localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH;
localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE;
localparam [5:0] READ_WIDTH_REG = READ_WIDTH;
localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE;
localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [35:0] SRVAL_REG = SRVAL;
localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE;
localparam [5:0] WRITE_WIDTH_REG = WRITE_WIDTH;
`endif
wire [2:0] CASCADE_ORDER_A_BIN;
wire CLOCK_DOMAINS_BIN;
wire FIRST_WORD_FALL_THROUGH_BIN;
wire [INIT_WIDTH-1:0] INIT_BIN;
wire IS_RDCLK_INVERTED_BIN;
wire IS_RDEN_INVERTED_BIN;
wire IS_RSTREG_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire IS_WRCLK_INVERTED_BIN;
wire IS_WREN_INVERTED_BIN;
wire [12:0] PROG_EMPTY_THRESH_BIN;
wire [12:0] PROG_FULL_THRESH_BIN;
wire [1:0] RDCOUNT_TYPE_BIN;
wire [5:0] READ_WIDTH_A_BIN;
wire [1:0] REGISTER_MODE_BIN;
wire RSTREG_PRIORITY_BIN;
wire SLEEP_ASYNC_BIN;
wire [INIT_WIDTH-1:0] SRVAL_BIN;
wire [1:0] WRCOUNT_TYPE_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
reg trig_gsr = 1'b0;
tri0 glblGSR = glbl.GSR || trig_gsr;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "FIFO18E2_dr.v"
`endif
wire CASNXTEMPTY_out;
wire CASPRVRDEN_out;
wire EMPTY_out;
wire FULL_out;
reg PROGEMPTY_out = 1;
reg PROGFULL_out = 0;
reg RDERR_out;
wire RDRSTBUSY_out;
reg WRERR_out;
wire WRRSTBUSY_out;
wire [ADDR_WIDTH:0] RDCOUNT_out;
wire [ADDR_WIDTH:0] WRCOUNT_out;
wire [DP_WIDTH-1:0] CASDOUTP_out;
wire [D_WIDTH-1:0] CASDOUT_out;
wire [D_WIDTH-1:0] DOUT_out;
wire [DP_WIDTH-1:0] DOUTP_out;
wire CASNXTEMPTY_delay;
wire CASPRVRDEN_delay;
wire EMPTY_delay;
wire FULL_delay;
wire PROGEMPTY_delay;
wire PROGFULL_delay;
wire RDERR_delay;
wire RDRSTBUSY_delay;
wire WRERR_delay;
wire WRRSTBUSY_delay;
wire [ADDR_WIDTH:0] RDCOUNT_delay;
wire [ADDR_WIDTH:0] WRCOUNT_delay;
wire [D_WIDTH-1:0] CASDOUT_delay;
wire [D_WIDTH-1:0] DOUT_delay;
wire [DP_WIDTH-1:0] CASDOUTP_delay;
wire [DP_WIDTH-1:0] DOUTP_delay;
wire CASDOMUXEN_A_in;
wire CASDOMUXA_in;
// wire CASNXTRDEN_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXA_in;
wire CASPRVEMPTY_in;
wire RDCLK_in;
wire RDEN_in;
wire REGCE_in;
wire RSTREG_in;
wire RST_in;
wire SLEEP_in;
wire WRCLK_in;
wire WREN_in;
wire [D_WIDTH-1:0] CASDINA_in;
wire [D_WIDTH-1:0] DIN_in;
wire [DP_WIDTH-1:0] CASDINPA_in;
wire [DP_WIDTH-1:0] DINP_in;
wire CASDOMUXEN_delay;
wire CASDOMUX_delay;
wire CASNXTRDEN_delay;
wire CASOREGIMUXEN_delay;
wire CASOREGIMUX_delay;
wire CASPRVEMPTY_delay;
wire RDCLK_delay;
wire RDEN_delay;
wire REGCE_delay;
wire RSTREG_delay;
wire RST_delay;
wire SLEEP_delay;
wire WRCLK_delay;
wire WREN_delay;
wire [D_WIDTH-1:0] CASDIN_delay;
wire [D_WIDTH-1:0] DIN_delay;
wire [DP_WIDTH-1:0] CASDINP_delay;
wire [DP_WIDTH-1:0] DINP_delay;
// internal variables, signals, busses
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer wb=0;
integer rd_loops_a = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
reg INIT_MEM = 0;
integer rdcount_adj = 0;
integer wrcount_adj = 0;
integer wr_adj = 0;
wire RDEN_lat;
wire RDEN_reg;
reg fill_lat=0;
reg fill_reg=0;
wire SLEEP_int;
reg SLEEP_reg = 1'b0;
reg SLEEP_reg1 = 1'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
wire prog_empty;
reg ram_full_c = 0;
wire ram_empty;
reg ram_empty_i = 1;
reg ram_empty_c = 1;
reg o_lat_empty = 1;
reg o_reg_empty = 1;
wire [1:0] output_stages;
wire o_stages_full;
wire o_stages_empty;
reg o_stages_full_sync=0;
reg o_stages_full_sync1=0;
reg o_stages_full_sync2=0;
reg o_stages_full_sync3=0;
wire prog_full;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire mem_wr_clk_b;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_clk_a;
wire mem_rd_en_a;
wire mem_rst_a;
reg mem [0 : mem_depth-1];
reg [D_WIDTH-1 : 0] mem_rd_a;
wire [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
wire [D_WIDTH-1 : 0] mem_a_reg_mux;
wire [D_WIDTH-1 : 0] mem_a_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
wire [D_WIDTH-1 : 0] mem_a_out;
reg memp [0 : memp_depth - 1];
reg [DP_WIDTH-1 : 0] memp_rd_a;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
wire [DP_WIDTH-1 : 0] memp_a_reg_mux;
wire [DP_WIDTH-1 : 0] memp_a_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
wire [DP_WIDTH-1 : 0] memp_a_out;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr3 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd3 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0;
wire [ADDR_WIDTH-1:0] rd_addr_wr;
wire [ADDR_WIDTH-1:0] wr_addr_rd;
wire [ADDR_WIDTH:0] wr_simple_raw;
wire [ADDR_WIDTH:0] rd_simple_raw;
wire [ADDR_WIDTH-1:0] wr_simple;
wire [ADDR_WIDTH-1:0] rd_simple;
reg [ADDR_WIDTH-1:0] wr_simple_sync;
reg [ADDR_WIDTH-1:0] rd_simple_sync;
//reset logic variables
reg WRRST_int = 1'b0;
reg RST_sync = 1'b0;
reg WRRST_done = 1'b0;
reg WRRST_done1 = 1'b0;
reg WRRST_done2 = 1'b0;
wire RDRST_int;
reg RDRST_done = 1'b0;
reg RDRST_done1 = 1'b0;
reg RDRST_done2 = 1'b0;
wire WRRST_done_wr;
reg WRRST_in_sync_rd = 1'b0;
reg WRRST_in_sync_rd1 = 1'b0;
reg WRRSTBUSY_dly = 1'b0;
reg WRRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly = 1'b0;
reg RDRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly2 = 1'b0;
reg sdp_mode = 1'b1;
reg sdp_mode_wr = 1'b1;
reg sdp_mode_rd = 1'b1;
// full/empty variables
wire [ADDR_WIDTH-1:0] full_count;
wire [ADDR_WIDTH-1:0] full_count_masked;
wire [8:0] m_full;
wire [8:0] m_full_raw;
wire [5:0] n_empty;
wire [5:0] unr_ratio;
wire [ADDR_WIDTH+1:0] prog_full_val;
wire [ADDR_WIDTH+1:0] prog_empty_val;
reg ram_full_i;
wire ram_one_from_full;
wire ram_two_from_full;
wire ram_one_read_from_not_full;
wire [ADDR_WIDTH-1:0] empty_count;
wire ram_one_read_from_empty;
wire ram_one_write_from_not_empty;
reg en_clk_sync = 1'b0;
// input output assignments
assign #(out_delay) CASDOUT = CASDOUT_delay;
assign #(out_delay) CASDOUTP = CASDOUTP_delay;
assign #(out_delay) CASNXTEMPTY = CASNXTEMPTY_delay;
assign #(out_delay) CASPRVRDEN = CASPRVRDEN_delay;
assign #(out_delay) DOUT = DOUT_delay;
assign #(out_delay) DOUTP = DOUTP_delay;
assign #(out_delay) EMPTY = EMPTY_delay;
assign #(out_delay) FULL = FULL_delay;
assign #(out_delay) PROGEMPTY = PROGEMPTY_delay;
assign #(out_delay) PROGFULL = PROGFULL_delay;
assign #(out_delay) RDCOUNT = RDCOUNT_delay;
assign #(out_delay) RDERR = RDERR_delay;
assign #(out_delay) RDRSTBUSY = RDRSTBUSY_delay;
assign #(out_delay) WRCOUNT = WRCOUNT_delay;
assign #(out_delay) WRERR = WRERR_delay;
assign #(out_delay) WRRSTBUSY = WRRSTBUSY_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) RDCLK_delay = RDCLK;
assign #(inclk_delay) WRCLK_delay = WRCLK;
assign #(in_delay) CASDINP_delay = CASDINP;
assign #(in_delay) CASDIN_delay = CASDIN;
assign #(in_delay) CASDOMUXEN_delay = CASDOMUXEN;
assign #(in_delay) CASDOMUX_delay = CASDOMUX;
assign #(in_delay) CASNXTRDEN_delay = CASNXTRDEN;
assign #(in_delay) CASOREGIMUXEN_delay = CASOREGIMUXEN;
assign #(in_delay) CASOREGIMUX_delay = CASOREGIMUX;
assign #(in_delay) CASPRVEMPTY_delay = CASPRVEMPTY;
assign #(in_delay) DINP_delay = DINP;
assign #(in_delay) DIN_delay = DIN;
assign #(in_delay) RDEN_delay = RDEN;
assign #(in_delay) REGCE_delay = REGCE;
assign #(in_delay) RSTREG_delay = RSTREG;
assign #(in_delay) RST_delay = RST;
assign #(in_delay) SLEEP_delay = SLEEP;
assign #(in_delay) WREN_delay = WREN;
`endif // `ifndef XIL_TIMING
assign CASDOUTP_delay = CASDOUTP_out;
assign CASDOUT_delay = CASDOUT_out;
assign CASNXTEMPTY_delay = CASNXTEMPTY_out;
assign CASPRVRDEN_delay = CASPRVRDEN_out;
assign DOUTP_delay = DOUTP_out;
assign DOUT_delay = DOUT_out;
assign EMPTY_delay = EMPTY_out;
assign FULL_delay = FULL_out;
assign PROGEMPTY_delay = PROGEMPTY_out;
assign PROGFULL_delay = PROGFULL_out;
assign RDCOUNT_delay = RDCOUNT_out;
assign RDERR_delay = RDERR_out;
assign RDRSTBUSY_delay = RDRSTBUSY_out;
assign WRCOUNT_delay = WRCOUNT_out;
assign WRERR_delay = WRERR_out;
assign WRRSTBUSY_delay = WRRSTBUSY_out;
assign CASDINPA_in = CASDINP_delay;
assign CASDINA_in = CASDIN_delay;
assign CASDOMUXEN_A_in = CASDOMUXEN_delay;
assign CASDOMUXA_in = CASDOMUX_delay;
// assign CASNXTRDEN_in = CASNXTRDEN_delay;
assign CASOREGIMUXEN_A_in = CASOREGIMUXEN_delay;
assign CASOREGIMUXA_in = CASOREGIMUX_delay;
assign CASPRVEMPTY_in = CASPRVEMPTY_delay;
assign DINP_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_delay : DINP_delay;
assign DIN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ? CASDIN_delay : DIN_delay;
assign RDCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) && (en_clk_sync == 1'b1)) ?
WRCLK_delay ^ IS_WRCLK_INVERTED_BIN :
RDCLK_delay ^ IS_RDCLK_INVERTED_BIN;
assign RDEN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
CASNXTRDEN_delay : RDEN_delay ^ IS_RDEN_INVERTED_BIN;
assign REGCE_in = REGCE_delay;
assign RSTREG_in = RSTREG_delay ^ IS_RSTREG_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign SLEEP_in = SLEEP_delay;
assign WRCLK_in = WRCLK_delay ^ IS_WRCLK_INVERTED_BIN;
assign WREN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_delay || FULL_out) : WREN_delay ^ IS_WREN_INVERTED_BIN;
assign mem_rd_clk_a = RDCLK_in;
assign mem_wr_clk_b = WRCLK_in;
assign mem_wr_en_b = WREN_in && ~FULL_out && ~WRRSTBUSY_out;
assign mem_rd_en_a = RDEN_lat && ~ram_empty && ~RDRST_int;
assign mem_wr_b = DIN_in;
assign memp_wr_b = DINP_in;
initial begin
trig_attr <= #1 ~trig_attr;
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
(CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign FIRST_WORD_FALL_THROUGH_BIN =
(FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE :
(FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE :
FIRST_WORD_FALL_THROUGH_FALSE;
assign INIT_BIN = INIT_REG;
assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG;
assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG;
assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG;
assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG;
assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG;
assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG;
assign RDCOUNT_TYPE_BIN =
(RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR :
(RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT :
(RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT :
(RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR :
RDCOUNT_TYPE_RAW_PNTR;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_REG == 36) ? READ_WIDTH_A_36 :
READ_WIDTH_A_4;
assign REGISTER_MODE_BIN =
(REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED :
(REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED :
(REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED :
REGISTER_MODE_UNREGISTERED;
assign RSTREG_PRIORITY_BIN =
(RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG :
(RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE :
RSTREG_PRIORITY_RSTREG;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_BIN = SRVAL_REG;
assign WRCOUNT_TYPE_BIN =
(WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR :
(WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT :
(WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT :
(WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR :
WRCOUNT_TYPE_RAW_PNTR;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 :
(WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 :
(WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 :
(WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 :
WRITE_WIDTH_4;
always @ (trig_attr) begin
#1;
if ((CASCADE_ORDER_REG != "NONE") &&
(CASCADE_ORDER_REG != "FIRST") &&
(CASCADE_ORDER_REG != "LAST") &&
(CASCADE_ORDER_REG != "MIDDLE") &&
(CASCADE_ORDER_REG != "PARALLEL")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL.", MODULE_NAME, CASCADE_ORDER_REG);
attr_err = 1'b1;
end
if ((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON")) begin
$display("Attribute Syntax Error : The attribute CLOCK_DOMAINS on %s instance %m is set to %s. Legal values for this attribute are INDEPENDENT or COMMON.", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((FIRST_WORD_FALL_THROUGH_REG != "FALSE") &&
(FIRST_WORD_FALL_THROUGH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG);
attr_err = 1'b1;
end
if ((IS_RDCLK_INVERTED_REG < 1'b0) || (IS_RDCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RDCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RDEN_INVERTED_REG < 1'b0) || (IS_RDEN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RDEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREG_INVERTED_REG < 1'b0) || (IS_RSTREG_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREG_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_WRCLK_INVERTED_REG < 1'b0) || (IS_WRCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_WRCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_WREN_INVERTED_REG < 1'b0) || (IS_WREN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_WREN_INVERTED_REG);
attr_err = 1'b1;
end
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to 8191.", MODULE_NAME, PROG_EMPTY_THRESH_REG);
attr_err = 1'b1;
end
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to 8191.", MODULE_NAME, PROG_FULL_THRESH_REG);
attr_err = 1'b1;
end
if ((RDCOUNT_TYPE_REG != "RAW_PNTR") &&
(RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SYNC_PNTR")) begin
$display("Attribute Syntax Error : The attribute RDCOUNT_TYPE on %s instance %m is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR.", MODULE_NAME, RDCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_REG != 4) &&
(READ_WIDTH_REG != 9) &&
(READ_WIDTH_REG != 18) &&
(READ_WIDTH_REG != 36)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", MODULE_NAME, READ_WIDTH_REG);
attr_err = 1'b1;
end
if ((REGISTER_MODE_REG != "UNREGISTERED") &&
(REGISTER_MODE_REG != "DO_PIPELINED") &&
(REGISTER_MODE_REG != "REGISTERED")) begin
$display("Attribute Syntax Error : The attribute REGISTER_MODE on %s instance %m is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED.", MODULE_NAME, REGISTER_MODE_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_REG != "RSTREG") &&
(RSTREG_PRIORITY_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_REG);
attr_err = 1'b1;
end
if ((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SLEEP_ASYNC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((WRCOUNT_TYPE_REG != "RAW_PNTR") &&
(WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SYNC_PNTR")) begin
$display("Attribute Syntax Error : The attribute WRCOUNT_TYPE on %s instance %m is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR.", MODULE_NAME, WRCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_REG != 4) &&
(WRITE_WIDTH_REG != 9) &&
(WRITE_WIDTH_REG != 18) &&
(WRITE_WIDTH_REG != 36)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", MODULE_NAME, WRITE_WIDTH_REG);
attr_err = 1'b1;
end
case (READ_WIDTH_REG)
4 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/4)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/4);
attr_err = 1'b1;
end
end
9 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/8)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/8);
attr_err = 1'b1;
end
end
18 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/16)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/16);
attr_err = 1'b1;
end
end
36 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/32)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/32);
attr_err = 1'b1;
end
end
default : begin
$display("Attribute Syntax Error : The attribute READ_WIDTH on %s instance %m is out of range on PROG_EMPTY_THRESH check.", MODULE_NAME);
attr_err = 1'b1;
end
endcase
case (WRITE_WIDTH_REG)
4 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/4)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/4);
attr_err = 1'b1;
end
end
9 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/8)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/8);
attr_err = 1'b1;
end
end
18 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/16)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/16);
attr_err = 1'b1;
end
end
36 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/32)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/32);
attr_err = 1'b1;
end
end
default : begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH on %s instance %m is out of range on PROG_FULL_THRESH check.", MODULE_NAME);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) $finish;
end
assign output_stages =
((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b10 :
((REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 : 2'b01;
assign wr_addr_b_mask =
(WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
SLEEP_reg <= 1'b0;
SLEEP_reg1 <= 1'b0;
end
else begin
SLEEP_reg <= SLEEP_in;
SLEEP_reg1 <= SLEEP_reg;
end
end
assign SLEEP_int = (SLEEP_ASYNC_BIN == SLEEP_ASYNC_FALSE) ? SLEEP_reg : SLEEP_in;
assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg :
REGCE_in;
assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int :
(RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in :
(RSTREG_in && REGCE_A_int);
assign RDEN_lat = RDEN_in || fill_reg || fill_lat;
assign RDEN_reg = RDEN_in || fill_reg ;
assign DOUT_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINA_in : mem_a_mux ^ mem_rm_douta;
assign DOUTP_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINPA_in : memp_a_mux ^ memp_rm_douta;
assign mem_a_mux = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ?
mem_a_reg : mem_a_lat;
assign memp_a_mux = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ?
memp_a_reg : memp_a_lat;
assign INIT_A_int =
(READ_WIDTH_A_BIN == READ_WIDTH_A_9) ? {{4{INIT_BIN[8]}}, {4{INIT_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{2{INIT_BIN[17:16]}}, {2{INIT_BIN[15:0]}}} :
INIT_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN == READ_WIDTH_A_9) ? {{4{SRVAL_BIN[8]}}, {4{SRVAL_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18)? {{2{SRVAL_BIN[17:16]}}, {2{SRVAL_BIN[15:0]}}}:
SRVAL_BIN;
assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr;
assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd;
assign o_stages_empty =
(output_stages==2'b00) ? ram_empty :
(output_stages==2'b01) ? o_lat_empty :
o_reg_empty; // 2
assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync;
// cascade out
assign CASDOUT_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTP_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASNXTEMPTY_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
EMPTY_out : 1'b0;
assign CASPRVRDEN_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out) : 1'b0;
// start model internals
// integers / constants
always begin
if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b;
else wr_adj = 1;
@(wr_loops_b or rd_loops_a);
end
always begin
if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) ||
((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0)))
wrcount_adj = 1;
else if ((output_stages>1) ||
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE))
wrcount_adj = output_stages*wr_adj;
else
wrcount_adj = 0;
rdcount_adj = output_stages;
@(wr_adj or output_stages or wr_loops_b or rd_loops_a);
end
// reset logic
assign RDRSTBUSY_out = RDRST_int;
assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly;
assign mem_rst_a = RDRST_int;
// RST_in sampled by WRCLK cleared by WR done
always @ (posedge mem_wr_clk_b) begin
if (RST_in && ~RST_sync) begin
RST_sync <= 1'b1;
end
else if (WRRST_done) begin
RST_sync <= 1'b0;
end
end
assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done;
always @ (posedge mem_wr_clk_b) begin
if (RST_in && ~WRRSTBUSY_out) begin
WRRST_int <= #1 1'b1;
end
else if (WRRST_done_wr) begin
WRRST_int <= #1 1'b0;
end
end
// WRRST_int sampled by RDCLK twice => RDRST_int in CDI
assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd;
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
WRRST_in_sync_rd1 <= 1'b0;
WRRST_in_sync_rd <= 1'b0;
end
else begin
WRRST_in_sync_rd1 <= #1 WRRST_int;
WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1;
end
end
// 3 rdclks to be done RD side
always @ (posedge mem_rd_clk_a) begin
if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRST_done2 <= 1'b0;
RDRST_done1 <= 1'b0;
RDRST_done <= 1'b0;
end
else begin
RDRST_done2 <= RDRST_int;
RDRST_done1 <= RDRST_done2;
RDRST_done <= RDRST_done1;
end
end
// 3 wrclks to be done WR side after RDRST_done
always @ (posedge mem_wr_clk_b) begin
if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRST_done2 <= 1'b0;
WRRST_done1 <= 1'b0;
WRRST_done <= 1'b0;
end
else if (WRRST_int) begin
WRRST_done2 <= RDRST_done;
WRRST_done1 <= WRRST_done2;
WRRST_done <= WRRST_done1;
end
end
// bug fix
always @ (posedge mem_rd_clk_a) begin
if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRSTBUSY_dly2 <= 1'b0;
RDRSTBUSY_dly1 <= 1'b0;
RDRSTBUSY_dly <= 1'b0;
end
else begin
RDRSTBUSY_dly2 <= RDRST_int;
RDRSTBUSY_dly1 <= RDRSTBUSY_dly2;
RDRSTBUSY_dly <= RDRSTBUSY_dly1;
end
end
always @ (posedge mem_wr_clk_b) begin
if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRSTBUSY_dly1 <= 1'b0;
WRRSTBUSY_dly <= 1'b0;
end
else begin
WRRSTBUSY_dly1 <= RDRSTBUSY_dly;
WRRSTBUSY_dly <= WRRSTBUSY_dly1;
end
end
// cascade control
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
// output register
assign mem_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? CASDINA_in : mem_a_lat;
assign memp_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? CASDINPA_in : memp_a_lat;
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= mem_a_reg_mux;
memp_a_reg <= memp_a_reg_mux;
end
end
// RDCOUNT sync to RDCLK
assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0];
assign RDCOUNT_out = RDRST_int ? 1'b0 :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync/(rd_loops_a) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) ? rd_simple_sync/(rd_loops_a) + rdcount_adj :
(rd_addr_a/rd_loops_a);
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_simple_sync <= 0;
end
else begin
if (rd_simple == {ADDR_WIDTH-1{1'b0}}) begin
rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]};
end
else begin
rd_simple_sync <= rd_simple;
end
end
end
// WRCOUNT sync to WRCLK
assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr};
assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0];
assign WRCOUNT_out = WRRSTBUSY_out ? 1'b0 :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? (wr_addr_b/(wr_loops_b)) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? (wr_addr_rd/(wr_loops_b)) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync/(wr_loops_b) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync/(wr_loops_b) + wrcount_adj :
(wr_addr_b/wr_loops_b);
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_simple_sync <= 0;
end
else begin
wr_simple_sync <= wr_simple;
end
end
// with any output stage or FWFT fill the ouptut latch
// when ram not empty and o_latch empty
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_lat_empty <= 1;
end
else if (fill_lat == 1) begin
o_lat_empty <= 0;
end
else if ((ram_empty == 1) && RDEN_lat) begin
o_lat_empty <= 1;
end
end
always @ (negedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
fill_lat <= 0;
end
else if ((ram_empty == 0) && (o_lat_empty == 1) && (output_stages>0)) begin
fill_lat <= 1;
end
else begin
fill_lat <= 0;
end
end
// FWFT and
// REGISTERED fill the ouptut register when o_latch not empty.
// Empty on external read and prev stage also empty
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_reg_empty <= 1;
end
else if ((o_lat_empty == 0) && RDEN_reg) begin
o_reg_empty <= 0;
end
else if ((o_lat_empty == 1) && RDEN_reg) begin
o_reg_empty <= 1;
end
end
always @ (negedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
fill_reg <= 0;
end
else if ((o_lat_empty == 0) && (o_reg_empty == 1) &&
(output_stages==2)) begin
fill_reg <= 1;
end
else begin
fill_reg <= 0;
end
end
// read engine
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_a) begin
$display("DRC Error : READ on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (ra=0;ra> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if (mem_rd_en_a) begin
mem_a_lat <= mem_rd_a;
memp_a_lat <= memp_rd_a;
end
end
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_addr_a <= {ADDR_WIDTH-1{1'b0}};
rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_rd_en_a) begin
rd_addr_a <= rd_addr_a + rd_loops_a;
end
rd_addr_a_wr <= rd_addr_a;
wr_addr_sync_rd2 <= wr_addr_b_rd;
wr_addr_sync_rd1 <= wr_addr_sync_rd2;
wr_addr_sync_rd <= wr_addr_sync_rd1;
end
end
// write engine
always @ (posedge mem_wr_clk_b) begin
if (mem_wr_en_b) begin
if (SLEEP_in || SLEEP_int) begin
$display("DRC Error : WRITE on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
end
else begin
for (wb=0;wb WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}};
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR)
WRERR_out <= 1'b0;
else if (WREN_in && (FULL_out || WRRSTBUSY_out))
WRERR_out <= 1'b1;
else
WRERR_out <= 1'b0;
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_addr_b <= {ADDR_WIDTH-1{1'b0}};
wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}};
o_stages_full_sync2 <= 1'b0;
o_stages_full_sync1 <= 1'b0;
o_stages_full_sync <= 1'b0;
rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_wr_en_b) begin
wr_addr_b <= wr_addr_b + wr_loops_b;
end
wr_addr_b_rd <= wr_addr_b;
o_stages_full_sync2 <= ~o_stages_empty;
o_stages_full_sync1 <= o_stages_full_sync2;
o_stages_full_sync <= o_stages_full_sync1;
rd_addr_sync_wr2 <= rd_addr_a_wr;
rd_addr_sync_wr1 <= rd_addr_sync_wr2;
rd_addr_sync_wr <= rd_addr_sync_wr1;
end
end
// full flag
assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out));
assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full;
assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0;
assign m_full = ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b);
assign m_full_raw = ((output_stages>1) && o_stages_full) ? output_stages*rd_loops_a :
(output_stages==1 && o_stages_full) ? rd_loops_a : 0;
assign n_empty = output_stages;
assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a;
assign full_count_masked = full_count & wr_addr_b_mask;
assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b};
assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i;
// ram_full independent clocks is one_from_full common clocks
assign ram_one_from_full = ((full_count < 2*wr_loops_b) && (full_count > 0));
assign ram_two_from_full = ((full_count < 3*wr_loops_b) && (full_count > 0));
// when full common clocks, next read makes it not full
assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c);
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_c <= 1'b0;
end
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a < wr_loops_b)) &&
ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_rd_en_a && ram_one_read_from_not_full) begin
ram_full_c <= 1'b0;
end
else begin
ram_full_c <= ram_full_c;
end
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_i <= 1'b0;
end
else if (mem_wr_en_b && ram_two_from_full && ~ram_full_i) begin
ram_full_i <= 1'b1;
end
else if (~ram_one_from_full) begin
ram_full_i <= 1'b0;
end
else begin
ram_full_i <= ram_full_i;
end
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
PROGFULL_out <= 1'b0;
end
else begin
PROGFULL_out <= prog_full;
end
end
// empty flag
assign EMPTY_out = o_stages_empty;
assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i;
assign ram_one_read_from_empty = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty;
assign ram_one_write_from_not_empty = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a);
assign prog_empty = ((empty_count < prog_empty_val) || ram_empty) && ~FULL_out;
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_c <= 1'b1;
// RD only makes empty
else if (~mem_wr_en_b &&
mem_rd_en_a &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// RD and WR when one read from empty and RD more than WR makes empty
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a > wr_loops_b)) &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR
else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c))
ram_empty_c <= 1'b0;
else
ram_empty_c <= ram_empty_c;
end
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_i <= 1'b1;
else if (mem_rd_en_a && ram_one_read_from_empty) // RDEN_in ?
ram_empty_i <= 1'b1;
else if (empty_count < rd_loops_a)
ram_empty_i <= 1'b1;
else
ram_empty_i <= 1'b0;
end
assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a};
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
PROGEMPTY_out <= 1'b1;
else
PROGEMPTY_out <= prog_empty;
end
specify
( CASDIN *> CASDOUT) = (0:0:0, 0:0:0);
( CASDIN *> DOUT) = (0:0:0, 0:0:0);
( CASDINP *> CASDOUTP) = (0:0:0, 0:0:0);
( CASDINP *> DOUTP) = (0:0:0, 0:0:0);
( CASPRVEMPTY *> CASPRVRDEN) = (0:0:0, 0:0:0);
( RDCLK *> CASDOUT) = (0:0:0, 0:0:0);
( RDCLK *> CASDOUTP) = (0:0:0, 0:0:0);
( RDCLK *> CASNXTEMPTY) = (0:0:0, 0:0:0);
( RDCLK *> DOUT) = (0:0:0, 0:0:0);
( RDCLK *> DOUTP) = (0:0:0, 0:0:0);
( RDCLK *> EMPTY) = (0:0:0, 0:0:0);
( RDCLK *> PROGEMPTY) = (0:0:0, 0:0:0);
( RDCLK *> RDCOUNT) = (0:0:0, 0:0:0);
( RDCLK *> RDERR) = (0:0:0, 0:0:0);
( RDCLK *> RDRSTBUSY) = (0:0:0, 0:0:0);
( RDCLK *> WRCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> CASDOUT) = (0:0:0, 0:0:0);
( WRCLK *> CASDOUTP) = (0:0:0, 0:0:0);
( WRCLK *> CASPRVRDEN) = (0:0:0, 0:0:0);
( WRCLK *> DOUT) = (0:0:0, 0:0:0);
( WRCLK *> DOUTP) = (0:0:0, 0:0:0);
( WRCLK *> FULL) = (0:0:0, 0:0:0);
( WRCLK *> PROGFULL) = (0:0:0, 0:0:0);
( WRCLK *> RDCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> RDRSTBUSY) = (0:0:0, 0:0:0);
( WRCLK *> WRCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> WRERR) = (0:0:0, 0:0:0);
( WRCLK *> WRRSTBUSY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FIFO36E1.v 0000664 0000000 0000000 00000451370 12327044266 0022516 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2008 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 36K-Bit FIFO
// /___/ /\ Filename : FIFO36E1.v
// \ \ / \ Timestamp : Tue Mar 18 16:55:14 PDT 2008
// \___\/\___\
//
// Revision:
// 03/18/08 - Initial version.
// 07/10/08 - IR476500 Add INIT parameter support
// 08/08/08 - Updated ECC to match hardware. (IR 479250)
// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware.
// 09/02/08 - Fixed ECC mismatch with hardware. (IR 479250)
// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976).
// 01/30/09 - Fixed eccparity when reset (IR 501358).
// 03/17/09 - Undo IR 501358 (CR 511331).
// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127).
// 04/29/09 - Fixed timing violation for asynchronous reset (CR 519016).
// 10/07/09 - Fixed reset behavior (CR 532794).
// 10/23/09 - Fixed RST and RSTREG (CR 537067).
// 11/17/09 - Fixed ECCPARITY behavior during RST (CR 537360).
// 12/02/09 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO36_72 (CR 539776).
// 06/30/10 - Updated RESET behavior and added SIM_DEVICE (CR 567515).
// 07/09/10 - Fixed INJECTSBITERR and INJECTDBITERR behaviors (CR 565234).
// 07/16/10 - Fixed RESET behavior during startup (CR 568626).
// 08/19/10 - Fixed RESET DRC during startup (CR 570708).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 12/02/10 - Added warning message for 7SERIES Aysnc mode (CR 584052).
// 12/07/10 - Error out if no reset before first use of the fifo (CR 583638).
// 01/12/11 - updated warning message for 7SERIES Aysnc mode (CR 589721).
// 05/11/11 - Fixed DO not suppose to be reseted when RST asserted (CR 586526).
// 05/26/11 - Update Aysnc fifo behavior (CR 599680).
// 06/06/11 - Fixed RST in standard mode (CR 613216).
// 06/07/11 - Update DRC equation for ALMOST_FULL_OFFSET (CR 611057).
// 06/09/11 - Fixed GSR behavior (CR 611989).
// 06/13/11 - Added setup/hold timing check for RST (CR 606107).
// 07/07/11 - Fixed Full flag (CR 615773).
// 08/26/11 - Fixed FULL and ALMOSTFULL during initial time (CR 622163).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/08/12 - Added DRC to check WREN/RDEN after RST deassertion (CR 644571).
// 05/16/12 - Added support of negative setup/hold/recovery/removal timing (CR 639991).
// 11/05/12 - Fixed full flag in async mode with sync clocks (CR 677254).
// 01/15/13 - Fixed index out of bound warnings for parity (CR 694713).
// 07/18/13 - Added invertible pins support (CR 715417).
// 08/01/13 - Fixed async mode with sync clocks (CR 728728).
// 10/31/13 - Fixed flags in async mode with sync clocks (CR 718734, 724006).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module FIFO36E1 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR,
DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO36";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter INIT = 72'h0;
parameter IS_RDCLK_INVERTED = 1'b0;
parameter IS_RDEN_INVERTED = 1'b0;
parameter IS_RSTREG_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_WRCLK_INVERTED = 1'b0;
parameter IS_WREN_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // XIL_TIMING
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL = 72'h0;
output ALMOSTEMPTY;
output ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output SBITERR;
output [12:0] WRCOUNT;
output WRERR;
input [63:0] DI;
input [7:0] DIP;
input INJECTDBITERR;
input INJECTSBITERR;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
tri0 GSR = glbl.GSR;
reg [12:0] wrcount_out, rdcount_out;
reg almostempty_out, almostfull_out, empty_out, full_out;
reg rderr_out, wrerr_out;
wire almostempty_wire, empty_wire, rderr_wire;
wire almostfull_wire, full_wire, wrerr_wire;
wire [12:0] wrcount_wire, rdcount_wire;
reg notifier, notifier_wrclk, notifier_rdclk;
reg [63:0] do_out;
reg [7:0] dop_out;
wire [63:0] do_wire;
wire [7:0] dop_wire;
reg finish_error = 0;
wire [63:0] di_in, DI_dly;
wire [7:0] dip_in, DIP_dly;
wire injectdbiterr_in, INJECTDBITERR_dly;
wire injectsbiterr_in, INJECTSBITERR_dly;
wire rdclk_in, rdclk_inv, RDCLK_dly;
wire rden_in, rden_inv, RDEN_dly;
wire regce_in, REGCE_dly;
wire rst_in, rst_inv, RST_dly;
wire rstreg_in, rstreg_inv, RSTREG_dly;
wire wrclk_in, wrclk_inv, WRCLK_dly;
wire wren_in, wren_inv, WREN_dly;
`ifdef XIL_TIMING
assign di_in = DI_dly;
assign dip_in = DIP_dly;
assign injectdbiterr_in = INJECTDBITERR_dly;
assign injectsbiterr_in = INJECTSBITERR_dly;
assign rdclk_inv = RDCLK_dly;
assign rden_inv = RDEN_dly;
assign regce_in = REGCE_dly;
assign rst_inv = RST_dly;
assign rstreg_inv = RSTREG_dly;
assign wrclk_inv = WRCLK_dly;
assign wren_inv = WREN_dly;
`endif // XIL_TIMING
`ifndef XIL_TIMING
assign di_in = DI; // XIL_TIMING
assign dip_in = DIP; // XIL_TIMING
assign injectdbiterr_in = INJECTDBITERR; // XIL_TIMING
assign injectsbiterr_in = INJECTSBITERR; // XIL_TIMING
assign rdclk_inv = RDCLK; // XIL_TIMING
assign rden_inv = RDEN; // XIL_TIMING
assign regce_in = REGCE; // XIL_TIMING
assign rst_inv = RST; // XIL_TIMING
assign rstreg_inv = RSTREG; // XIL_TIMING
assign wrclk_inv = WRCLK; // XIL_TIMING
assign wren_inv = WREN; // XIL_TIMING
`endif // `ifndef XIL_TIMING
assign rdclk_in = rdclk_inv ^ IS_RDCLK_INVERTED;
assign rden_in = rden_inv ^ IS_RDEN_INVERTED;
assign rstreg_in = rstreg_inv ^ IS_RSTREG_INVERTED;
assign rst_in = rst_inv ^ IS_RST_INVERTED;
assign wrclk_in = wrclk_inv ^ IS_WRCLK_INVERTED;
assign wren_in = wren_inv ^ IS_WREN_INVERTED;
initial begin
case (FIFO_MODE)
"FIFO36" : ;
"FIFO36_72" : if (DATA_WIDTH != 72) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 72 when attribute FIFO_MODE = FIFO36_72.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are FIFO36 or FIFO36_72.", FIFO_MODE);
finish_error = 1;
end
endcase // case(FIFO_MODE)
case (DATA_WIDTH)
4, 9, 18, 36 : ;
72 : if (FIFO_MODE != "FIFO36_72") begin
$display("DRC Error : The attribute FIFO_MODE must be set to FIFO36_72 when attribute DATA_WIDTH = 72.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH);
finish_error = 1;
end
endcase
if (!((IS_RDCLK_INVERTED >= 1'b0) && (IS_RDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RDEN_INVERTED >= 1'b0) && (IS_RDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDEN_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RSTREG_INVERTED >= 1'b0) && (IS_RSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREG_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RST_INVERTED >= 1'b0) && (IS_RST_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RST_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WRCLK_INVERTED >= 1'b0) && (IS_WRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WRCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WREN_INVERTED >= 1'b0) && (IS_WREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on FIFO36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WREN_INVERTED);
finish_error = 1'b1;
end
if (finish_error == 1)
$finish;
end // initial begin
// Matching HW
localparam init_sdp = (FIFO_MODE == "FIFO36_72") ? {INIT[71:68],INIT[35:32],INIT[67:36],INIT[31:0]} : INIT;
localparam srval_sdp = (FIFO_MODE == "FIFO36_72") ? {SRVAL[71:68],SRVAL[35:32],SRVAL[67:36],SRVAL[31:0]} : SRVAL;
FF36_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
.DATA_WIDTH(DATA_WIDTH),
.DO_REG(DO_REG),
.EN_ECC_WRITE(EN_ECC_WRITE),
.EN_ECC_READ(EN_ECC_READ),
.EN_SYN(EN_SYN),
.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
.FIFO_MODE(FIFO_MODE),
.INIT(init_sdp),
.SIM_DEVICE(SIM_DEVICE),
.SRVAL(srval_sdp))
INT_FIFO (.ALMOSTEMPTY(almostempty_wire),
.ALMOSTFULL(almostfull_wire),
.DBITERR(DBITERR),
.DI(di_in),
.DIP(dip_in),
.DO(do_wire),
.DOP(dop_wire),
.ECCPARITY(ECCPARITY),
.EMPTY(empty_wire),
.FULL(full_wire),
.GSR(GSR),
.INJECTDBITERR(injectdbiterr_in),
.INJECTSBITERR(injectsbiterr_in),
.RDCLK(rdclk_in),
.RDCOUNT(rdcount_wire),
.RDEN(rden_in),
.RDERR(rderr_wire),
.REGCE(regce_in),
.RST(rst_in),
.RSTREG(rstreg_in),
.SBITERR(SBITERR),
.WRCLK(wrclk_in),
.WRCOUNT(wrcount_wire),
.WREN(wren_in),
.WRERR(wrerr_wire));
//*** Timing Checks Start here
assign DO = do_out;
assign DOP = dop_out;
assign ALMOSTFULL = almostfull_out;
assign FULL = full_out;
assign WRERR = wrerr_out;
assign WRCOUNT = wrcount_out;
assign ALMOSTEMPTY = almostempty_out;
assign EMPTY = empty_out;
assign RDERR = rderr_out;
assign RDCOUNT = rdcount_out;
always @(almostfull_wire or wrclk_in) almostfull_out = almostfull_wire;
always @(full_wire or wrclk_in) full_out = full_wire;
always @(wrerr_wire or wrclk_in) wrerr_out = wrerr_wire;
always @(wrcount_wire or wrclk_in) wrcount_out = wrcount_wire;
always @(almostempty_wire or rdclk_in) almostempty_out = almostempty_wire;
always @(empty_wire or rdclk_in) empty_out = empty_wire;
always @(rderr_wire or rdclk_in) rderr_out = rderr_wire;
always @(rdcount_wire or rdclk_in) rdcount_out = rdcount_wire;
always @(do_wire or rdclk_in) do_out = do_wire;
always @(dop_wire or rdclk_in) dop_out = dop_wire;
`ifdef XIL_TIMING
always @(notifier) begin
do_out <= 64'bx;
dop_out <= 8'bx;
end
always @(notifier_wrclk) begin
almostfull_out <= 1'bx;
full_out <= 1'bx;
wrcount_out <= 13'bx;
wrerr_out <= 1'bx;
end
always @(notifier_rdclk) begin
almostempty_out <= 1'bx;
empty_out <= 1'bx;
rdcount_out <= 13'bx;
rderr_out <= 1'bx;
end
not (nrst, RST);
and (wren_enable, WREN, nrst);
`endif // `ifdef XIL_TIMING
specify
(RDCLK *> DO) = (100:100:100, 100:100:100);
(RDCLK *> DOP) = (100:100:100, 100:100:100);
(RDCLK => DBITERR) = (100:100:100, 100:100:100);
(RDCLK => SBITERR) = (100:100:100, 100:100:100);
(RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100);
(RDCLK => EMPTY) = (100:100:100, 100:100:100);
(RDCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(RDCLK => RDERR) = (100:100:100, 100:100:100);
(WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100);
(WRCLK => FULL) = (100:100:100, 100:100:100);
(WRCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(WRCLK => WRERR) = (100:100:100, 100:100:100);
(WRCLK *> ECCPARITY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(RST => ALMOSTEMPTY) = (0:0:0, 0:0:0);
(RST => ALMOSTFULL) = (0:0:0, 0:0:0);
(RST => EMPTY) = (0:0:0, 0:0:0);
(RST => FULL) = (0:0:0, 0:0:0);
(RST *> RDCOUNT) = (0:0:0, 0:0:0);
(RST => RDERR) = (0:0:0, 0:0:0);
(RST *> WRCOUNT) = (0:0:0, 0:0:0);
(RST => WRERR) = (0:0:0, 0:0:0);
$setuphold (posedge RDCLK, negedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, posedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, negedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, posedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, negedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, posedge RDEN &&& (RST==0), 0:0:0, 0:0:0,,,, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, negedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,,, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, posedge RST, 0:0:0, 0:0:0,,,, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,,, RDCLK_dly, RSTREG_dly);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, negedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, posedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, posedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, negedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (posedge WRCLK, posedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (posedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTDBITERR_dly);
$setuphold (posedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTSBITERR_dly);
$setuphold (posedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTDBITERR_dly);
$setuphold (posedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTSBITERR_dly);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0,,,, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, negedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, posedge DIP &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, posedge DI &&& (wren_enable!=0), 0:0:0, 0:0:0,,,, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, negedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, posedge WREN &&& (RST==0), 0:0:0, 0:0:0,,,, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTDBITERR_dly);
$setuphold (negedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTSBITERR_dly);
$setuphold (negedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTDBITERR_dly);
$setuphold (negedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0,,,, WRCLK_dly, INJECTSBITERR_dly);
$recrem (negedge RST, posedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk,,, RST_dly, RDCLK_dly);
$recrem (negedge RST, posedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk,,, RST_dly, WRCLK_dly);
$recrem (negedge RST, negedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk,,, RST_dly, RDCLK_dly);
$recrem (negedge RST, negedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk,,, RST_dly, WRCLK_dly);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // FIFO36E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. FIFO36E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module FF36_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR,
DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
output ALMOSTEMPTY;
output ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output SBITERR;
output [12:0] WRCOUNT;
output WRERR;
input [63:0] DI;
input [7:0] DIP;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
input GSR;
input INJECTDBITERR;
input INJECTSBITERR;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO36";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter EN_ECC_WRITE = "FALSE";
parameter EN_ECC_READ = "FALSE";
parameter INIT = 72'h0;
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL = 72'h0;
reg [63:0] do_in = 64'b0;
reg [63:0] do_out = 64'b0;
reg [63:0] do_outreg = 64'b0;
reg [63:0] do_out_mux = 64'b0;
wire [63:0] do_out_out;
reg [7:0] dop_in = 8'b0, dop_out = 8'b0;
wire [7:0] dop_out_out;
reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0;
reg almostempty_out = 1'b1, almostfull_out = 1'b0, empty_out = 1'b1;
reg full_out = 1'b0, rderr_out = 0, wrerr_out = 0;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [71:0] ecc_bit_position;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, dop_buf = 8'b0, dip_ecc, dip_int;
reg [63:0] do_buf = 64'b0, di_in_ecc_corrected;
reg [7:0] syndrome, dip_in_ecc_corrected;
wire [63:0] di_in;
wire [7:0] dip_in;
wire rdclk_in, rden_in, rst_in, rstreg_in, wrclk_in, wren_in;
wire regce_in, gsr_in;
wire injectdbiterr_in, injectsbiterr_in;
wire full_v3;
reg rden_reg, wren_reg;
reg fwft;
integer addr_limit, rd_prefetch = 0;
integer wr1_addr = 0;
integer viol_rst_rden = 0, viol_rst_wren = 0;
reg [3:0] rden_rdckreg = 4'b0, wren_wrckreg = 4'b0;
reg [12:0] rd_addr = 0;
reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0;
reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0;
reg wr1_flag = 0, awr_flag = 0;
reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111;
reg [3:0] full_int = 4'b0000;
reg [3:0] empty_ram = 4'b1111;
reg [8:0] i, j;
reg rst_tmp1 = 0, rst_tmp2 = 0;
reg [4:0] rst_rdckreg = 5'b0, rst_wrckreg = 5'b0;
reg rst_rdclk_flag = 0, rst_wrclk_flag = 0;
reg en_ecc_write_int, en_ecc_read_int, finish_error = 0;
reg [63:0] di_ecc_col;
reg first_rst_flag = 0;
reg rm1wp1_eq = 1'b0, rm1w_eq = 1'b0;
reg awr_flag_sync_1 = 0, awr_flag_sync_2 = 0;
integer after_rst_rdclk = 0, after_rst_wrclk = 0;
integer count_freq_rdclk = 0, count_freq_wrclk = 0;
integer roundup_int_period_rdclk_wrclk, roundup_int_period_wrclk_rdclk;
integer s7_roundup_int_period_rdclk_wrclk;
time rise_rdclk, period_rdclk, rise_wrclk, period_wrclk;
integer fwft_prefetch_flag = 1;
real real_period_rdclk, real_period_wrclk;
reg rst_trans_rden_1 = 1'b0, rst_trans_rden_2 = 1'b0;
reg rst_trans_wren_1 = 1'b0, rst_trans_wren_2 = 1'b0;
reg after_rst_rden_flag = 1'b0, after_rst_wren_flag = 1'b0, after_rst_x_flag = 1'b0;
time time_wrclk, time_rdclk;
reg sync_clk_async_mode = 1'b0;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameter is changed.
parameter integer FIFO_SIZE = 36;
// xilinx_internal_parameter off
localparam counter_width = (FIFO_SIZE == 36) ? ((DATA_WIDTH == 4) ? 12 :
(DATA_WIDTH == 9) ? 11 : (DATA_WIDTH == 18) ? 10 :
(DATA_WIDTH == 36) ? 9 : (DATA_WIDTH == 72) ? 8 : 12)
: ((DATA_WIDTH == 4) ? 11 : (DATA_WIDTH == 9) ? 10 :
(DATA_WIDTH == 18) ? 9 : (DATA_WIDTH == 36) ? 8 : 11);
reg [counter_width:0] rdcount_out = 13'b0, wr_addr = 13'b0;
reg [counter_width:0] ae_empty, ae_full;
reg [counter_width:0] rdcount_out_sync_3 = 13'h1fff, rdcount_out_sync_2 = 13'h1fff;
reg [counter_width:0] rdcount_out_sync_1 = 13'h1fff, rdcount_out_m1 = 13'h1fff;
reg [counter_width:0] wr_addr_sync_3 = 13'b0, wr_addr_sync_2 = 13'b0, wr_addr_sync_1 = 13'b0;
// Determinte memory size
localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0;
localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0;
localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0;
localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0;
localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0;
localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 :
(DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0;
localparam memp_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 1 :
(DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0;
reg [mem_width : 0] mem [mem_depth : 0];
reg [memp_width : 0] memp [memp_depth : 0];
reg sync;
// Input and output ports
assign di_in = DI;
assign dip_in = DIP;
assign DO = do_out_out;
assign DOP = dop_out_out;
assign rdclk_in = RDCLK;
assign regce_in = REGCE;
assign rden_in = RDEN;
assign rst_in = RST;
assign rstreg_in = RSTREG;
assign wrclk_in = WRCLK;
assign wren_in = WREN;
assign gsr_in = GSR;
assign ALMOSTEMPTY = almostempty_out;
assign ALMOSTFULL = almostfull_out;
assign EMPTY = empty_out;
assign FULL = full_out;
assign RDERR = rderr_out;
assign WRERR = wrerr_out;
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
assign RDCOUNT = rdcount_out_out;
assign WRCOUNT = wr_addr_out;
assign injectdbiterr_in = INJECTDBITERR;
assign injectsbiterr_in = INJECTSBITERR;
assign full_v3 = (rm1w_eq || (rm1wp1_eq && (wren_in && !full_out))) ? 1 : 0;
initial begin
// Determine address limit
case (DATA_WIDTH)
4 : begin
if (FIFO_SIZE == 36)
addr_limit = 8192;
else
addr_limit = 4096;
end
9 : begin
if (FIFO_SIZE == 36)
addr_limit = 4096;
else
addr_limit = 2048;
end
18 : begin
if (FIFO_SIZE == 36)
addr_limit = 2048;
else
addr_limit = 1024;
end
36 : begin
if (FIFO_SIZE == 36)
addr_limit = 1024;
else
addr_limit = 512;
end
72 : begin
addr_limit = 512;
end
default :
begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH);
finish_error = 1;
end
endcase
case (EN_SYN)
"FALSE" : sync = 0;
"TRUE" : sync = 1;
default : begin
$display("Attribute Syntax Error : The attribute EN_SYN on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN);
finish_error = 1;
end
endcase // case(EN_SYN)
case (FIRST_WORD_FALL_THROUGH)
"FALSE" : begin
fwft = 0;
if (EN_SYN == "FALSE") begin
ae_empty = ALMOST_EMPTY_OFFSET - 1;
ae_full = ALMOST_FULL_OFFSET;
end
else begin
ae_empty = ALMOST_EMPTY_OFFSET;
ae_full = ALMOST_FULL_OFFSET;
end
end
"TRUE" : begin
fwft = 1;
ae_empty = ALMOST_EMPTY_OFFSET - 2;
ae_full = ALMOST_FULL_OFFSET;
end
default : begin
$display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH);
finish_error = 1;
end
endcase
// DRC for fwft in sync mode
if (fwft == 1'b1 && EN_SYN == "TRUE") begin
$display("DRC Error : First word fall through is not supported in synchronous mode on FIFO36E1 instance %m.");
finish_error = 1;
end
if (EN_SYN == "FALSE" && DO_REG == 0) begin
$display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FIFO36E1 instance %m.");
finish_error = 1;
end
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int <= 1;
"FALSE" : en_ecc_write_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int <= 1;
"FALSE" : en_ecc_read_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on FIFO36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FIFO36E1 is configured in the ECC mode.");
finish_error = 1;
end
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
$finish;
end // initial begin
// GSR and RST
always @(gsr_in)
if (gsr_in === 1'b1) begin
if (DO_REG == 1'b1 && sync == 1'b1) begin
assign do_out = INIT[0 +: mem_width+1];
assign dop_out = INIT[mem_width+1 +: memp_width+1];
assign do_outreg = INIT[0 +: mem_width+1];
assign dop_outreg = INIT[mem_width+1 +: memp_width+1];
assign do_in = INIT[0 +: mem_width+1];
assign dop_in = INIT[mem_width+1 +: memp_width+1];
assign do_buf = INIT[0 +: mem_width+1];
assign dop_buf = INIT[mem_width+1 +: memp_width+1];
end
else begin
assign do_out = 64'b0;
assign dop_out = 8'b0;
assign do_outreg = 64'b0;
assign dop_outreg = 8'b0;
assign do_in = 64'b0;
assign dop_in = 8'b0;
assign do_buf = 64'b0;
assign dop_buf = 8'b0;
end
end
else if (gsr_in === 1'b0) begin
deassign do_out;
deassign dop_out;
deassign do_outreg;
deassign dop_outreg;
deassign do_in;
deassign dop_in;
deassign do_buf;
deassign dop_buf;
end
always @(rst_in)
if (rst_in === 1'b1) begin
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'b1;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'b0;
assign empty_ram = 4'b1111;
assign empty_out = 1'b1;
assign full_int = 4'b0000;
assign full_out = 1'b0;
assign rdcount_out = 13'b0;
assign rdcount_out_out = 13'b0;
assign wr_addr_out = 13'b0;
assign rderr_out = 0;
assign wrerr_out = 0;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign wr_addr = 0;
assign wr1_addr = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'b1111111111111;
assign rdcount_out_m1 = 13'b1111111111111;
assign wr_addr_sync_3 = 13'b0;
end
else if (rst_in === 1'b0) begin
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign empty_out;
deassign full_int;
deassign full_out;
deassign rdcount_out;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign rderr_out;
deassign wrerr_out;
deassign rd_addr;
deassign rd_prefetch;
deassign wr_addr;
deassign wr1_addr;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end
// DRC
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
always @(posedge rdclk_in) begin
if (rst_in === 1'b1 && rden_in === 1'b1)
viol_rst_rden = 1;
if (rst_in === 1'b0)
rden_rdckreg[3:0] <= {rden_rdckreg[2:0], rden_in};
if (rden_rdckreg == 4'h0) begin
rst_rdckreg[0] <= rst_in;
rst_rdckreg[1] <= rst_rdckreg[0] & rst_in;
rst_rdckreg[2] <= rst_rdckreg[1] & rst_in;
end
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
if (rst_in === 1'b1 && wren_in === 1'b1)
viol_rst_wren = 1;
if (rst_in === 1'b0)
wren_wrckreg[3:0] <= {wren_wrckreg[2:0], wren_in};
if (wren_wrckreg == 4'h0) begin
rst_wrckreg[0] <= rst_in;
rst_wrckreg[1] <= rst_wrckreg[0] & rst_in;
rst_wrckreg[2] <= rst_wrckreg[1] & rst_in;
end
end // always @ (posedge wrclk_in)
always @(rst_in) begin
rst_tmp1 = rst_in;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
end
if (((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
end // if (rst_in == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rden_rdckreg = 4'h0;
wren_wrckreg = 4'h0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (rst_in)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge rst_in)
rst_trans_rden_1 = rst_in;
always @(negedge rst_in)
if (rst_trans_rden_1 == 1'b1)
rst_trans_rden_2 = ~rst_in;
always @(posedge rdclk_in) begin
if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) begin
after_rst_rdclk = after_rst_rdclk + 1;
if (rden_in === 1'b1 && after_rst_rdclk <= 2) begin
after_rst_rden_flag = 1'b1;
end
else if (after_rst_rdclk >= 3) begin
after_rst_rdclk = 0;
rst_trans_rden_1 = 1'b0;
rst_trans_rden_2 = 1'b0;
if (after_rst_rden_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RDEN must be low for at least two RDCLK clock cycles after RST deasserted.", $stime);
after_rst_rden_flag = 1'b0;
after_rst_x_flag = 1'b1;
end
end
end // if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1)
end // always @ (posedge rdclk_in)
always @(posedge rst_in)
rst_trans_wren_1 = rst_in;
always @(negedge rst_in)
if (rst_trans_wren_1 == 1'b1)
rst_trans_wren_2 = ~rst_in;
always @(posedge wrclk_in) begin
if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) begin
after_rst_wrclk = after_rst_wrclk + 1;
if (wren_in === 1'b1 && after_rst_wrclk <= 2) begin
after_rst_wren_flag = 1'b1;
end
else if (after_rst_wrclk >= 3) begin
after_rst_wrclk = 0;
rst_trans_wren_1 = 1'b0;
rst_trans_wren_2 = 1'b0;
if (after_rst_wren_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. WREN must be low for at least two WRCLK clock cycles after RST deasserted.", $stime);
after_rst_wren_flag = 1'b0;
after_rst_x_flag = 1'b1;
end
end
end // if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1)
end // always @ (posedge wrclk_in)
always @(posedge after_rst_x_flag or negedge rst_in) begin
if (after_rst_x_flag == 1'b1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
after_rst_x_flag = 1'b0;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (rst_in == 1'b0)
end // always @ (posedge after_rst_x_flag or negedge rst_in)
always @(posedge rdclk_in) begin
if (rst_in === 1'b1 && rden_in === 1'b1)
viol_rst_rden = 1;
if (rden_in === 1'b0 && rst_in === 1'b1) begin
rst_rdckreg[0] <= rst_in;
rst_rdckreg[1] <= rst_rdckreg[0] & rst_in;
rst_rdckreg[2] <= rst_rdckreg[1] & rst_in;
rst_rdckreg[3] <= rst_rdckreg[2] & rst_in;
rst_rdckreg[4] <= rst_rdckreg[3] & rst_in;
end
else if (rden_in === 1'b1 && rst_in === 1'b1) begin
rst_rdckreg <= 5'b0;
end
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
if (rst_in === 1'b1 && wren_in === 1'b1)
viol_rst_wren = 1;
if (wren_in === 1'b0 && rst_in === 1'b1) begin
rst_wrckreg[0] <= rst_in;
rst_wrckreg[1] <= rst_wrckreg[0] & rst_in;
rst_wrckreg[2] <= rst_wrckreg[1] & rst_in;
rst_wrckreg[3] <= rst_wrckreg[2] & rst_in;
rst_wrckreg[4] <= rst_wrckreg[3] & rst_in;
end
else if (wren_in === 1'b1 && rst_in === 1'b1) begin
rst_wrckreg <= 5'b0;
end
end // always @ (posedge wrclk_in)
always @(rst_in) begin
rst_tmp1 = rst_in;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[4] & rst_rdckreg[3] & rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five RDCLK clock cycles, and RDEN must be low before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
end
if (((rst_wrckreg[4] & rst_wrckreg[3] & rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
assign full_out = 1'bX;
assign empty_out = 1'bX;
assign rderr_out = 1'bX;
assign wrerr_out = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
assign rdcount_out_out = 13'bx;
assign wr_addr_out = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
assign almostempty_out = 1'bx;
assign almostfull_int = 4'b0000;
assign almostfull_out = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
end
else if (rst_in == 1'b0) begin
deassign full_out;
deassign empty_out;
deassign rderr_out;
deassign wrerr_out;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
deassign rdcount_out_out;
deassign wr_addr_out;
deassign wr1_addr;
deassign almostempty_int;
deassign almostempty_out;
deassign almostfull_int;
deassign almostfull_out;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (rst_in == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (rst_in)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// DRC
always @(posedge rden_in or negedge gsr_in)
@(posedge rdclk_in)
if (first_rst_flag == 0 && rden_in == 1'b1 && gsr_in == 1'b0) begin
$display("DRC Error : A RESET cycle must be observerd before the first use of the FIFO instance %m which occurs at time %t.", $time);
end
always @(posedge wren_in or negedge gsr_in)
@(posedge wrclk_in)
if (first_rst_flag == 0 && wren_in == 1'b1 && gsr_in == 1'b0) begin
$display("DRC Error : A RESET cycle must be observerd before the first use of the FIFO instance %m which occurs at time %t.", $time);
end
always @(posedge rdclk_in) begin
count_freq_rdclk = count_freq_rdclk + 1;
if (count_freq_rdclk == 100)
rise_rdclk = $time;
else if (count_freq_rdclk == 101) begin
period_rdclk = $time - rise_rdclk;
if (count_freq_wrclk >= 101 && rst_in === 1'b0 && gsr_in === 1'b0) begin
// Setup ranges for almostempty
if (period_rdclk == period_wrclk) begin
if (EN_SYN == "FALSE") begin
if (SIM_DEVICE == "7SERIES") begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 6)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 6);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
$finish;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 5);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
$finish;
end
end // else: !if(fwft == 1'b0)
end // if (SIM_DEVICE == "7SERIES")
else begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
$finish;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4);
$finish;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
$finish;
end
end // else: !if(fwft == 1'b0)
end // else: !if(SIM_DEVICE == "7SERIES")
end // if (EN_SYN == "FALSE")
else begin
if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2);
$finish;
end
if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2);
$finish;
end
end // else: !if(EN_SYN == "FALSE")
end // if (period_rdclk == period_wrclk)
else begin
real_period_rdclk = period_rdclk * 1.0;
real_period_wrclk = period_wrclk * 1.0;
roundup_int_period_rdclk_wrclk = (real_period_rdclk / real_period_wrclk) + 0.499;
roundup_int_period_wrclk_rdclk = (real_period_wrclk / real_period_rdclk) + 0.499;
s7_roundup_int_period_rdclk_wrclk = (4.0 * (real_period_rdclk / real_period_wrclk)) + 0.499;
if (SIM_DEVICE == "7SERIES") begin
if (ALMOST_FULL_OFFSET > (addr_limit - (s7_roundup_int_period_rdclk_wrclk + 6))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((roundup(4 * (WRCLK frequency / RDCLK frequency))) + 6)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
$finish;
end
end
else begin
if (ALMOST_FULL_OFFSET > (addr_limit - ((3 * roundup_int_period_wrclk_rdclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (RDCLK frequency / WRCLK frequency)) + 3)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
$finish;
end
if (ALMOST_EMPTY_OFFSET > (addr_limit - ((3 * roundup_int_period_rdclk_wrclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on FIFO36E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (WRCLK frequency / RDCLK frequency)) + 3)) when FIFO36E1 has different frequencies for RDCLK and WRCLK.", ALMOST_EMPTY_OFFSET);
$finish;
end
end // else: !if(SIM_DEVICE == "7SERIES")
end // else: !if(period_rdclk == period_wrclk)
count_freq_rdclk = 0;
count_freq_wrclk = 0;
end // if (count_freq_wrclk >= 101 && count_freq_rdclk >= 101 && rst_in === 1'b0 && gsr_in === 1'b0)
end // if (count_freq_rdclk == 101)
end // always @ (posedge rdclk_in)
always @(posedge wrclk_in) begin
count_freq_wrclk = count_freq_wrclk + 1;
if (count_freq_wrclk == 100)
rise_wrclk = $time;
else if (count_freq_wrclk == 101) begin
period_wrclk = $time - rise_wrclk;
end
end // always @ (posedge wrclk_in)
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
// read clock
always @(posedge rdclk_in) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (rden_in == 1'b1) begin
if (empty_out == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (empty_out == 1'b0)
end // if (rden_in == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
if (wren_in == 1'b1) begin
empty_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
empty_out = 1'b1;
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
almostempty_out = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
almostfull_out = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rden_reg = rden_in;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[3];
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[2] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync == 1'b0)
end // always @ (posedge rdclk_in)
// Write clock
always @(posedge wrclk_in) begin
// DRC
if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m.");
if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (wren_in == 1'b1) begin
if (full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (full_out == 1'b0)
end // if (wren_in == 1'b1)
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
if (rden_in == 1'b1) begin
full_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
full_out = 1'b1;
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
almostempty_out = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
almostfull_out = 1'b1;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wren_reg = wren_in;
if (wren_reg == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_reg == 1'b1 && full_out == 1'b0)
if (rst_in === 1'b0) begin
wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || full_out == 1'b1)
full_out = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b0)
end // always @ (posedge wrclk_in)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge rdclk_in)
time_rdclk = $time;
always @(posedge wrclk_in)
time_wrclk = $time;
always @(time_rdclk or time_wrclk)
if ((time_rdclk - time_wrclk == 0 || time_wrclk - time_rdclk == 0) && $time != 0)
sync_clk_async_mode = 1'b1;
// read clock
always @(posedge rdclk_in) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (rden_in == 1'b1) begin
if (empty_out == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (empty_out == 1'b0)
end // if (rden_in == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
if (wren_in == 1'b1) begin
empty_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
empty_out = 1'b1;
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
almostempty_out = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
almostfull_out = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wr_addr_sync_3 = wr_addr_sync_2;
wr_addr_sync_2 = wr_addr_sync_1;
wr_addr_sync_1 = wr_addr;
awr_flag_sync_2 = awr_flag_sync_1;
awr_flag_sync_1 = awr_flag;
if (sync_clk_async_mode == 1'b1) begin
rden_reg = rden_in;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[3];
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[2] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync_clk_async_mode == 1'b1)
else begin
if (fwft == 1'b0) begin
if (rden_in == 1'b1 && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (rden_in == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_in == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr && rd_addr != rdcount_out) || (rst_in === 1'b1 && fwft_prefetch_flag == 1)) begin
fwft_prefetch_flag = 0;
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (rden_in == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1);
almostempty_out = almostempty_int[0];
if (wr_addr_sync_3 - rdcount_out <= ae_empty)
almostempty_int[0] = 1'b1;
else
almostempty_int[0] = 1'b0;
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
empty_out = 1'b1;
end
else begin
empty_out = 1'b0;
end
end
if ((rdcount_out == wr_addr_sync_2) && (rdcount_flag == awr_flag_sync_2)) begin
empty_ram[0] = 1'b1;
end
else begin
empty_ram[0] = 1'b0;
end
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge rdclk_in)
// Write clock
always @(posedge wrclk_in) begin
// DRC
if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m.");
if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO36E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (wren_in == 1'b1) begin
if (full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (full_out == 1'b0)
end // if (wren_in == 1'b1)
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
if (rden_in == 1'b1) begin
full_out = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
full_out = 1'b1;
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
almostempty_out = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
almostfull_out = 1'b1;
end
end // if (rst_in === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rdcount_out_sync_3 = rdcount_out_sync_2;
rdcount_out_sync_2 = rdcount_out_sync_1;
rdcount_out_sync_1 = rdcount_out_m1;
if (sync_clk_async_mode == 1'b1) begin
wren_reg = wren_in;
if (wren_reg == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_reg == 1'b1 && full_out == 1'b0)
if (rst_in === 1'b0) begin
wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || full_out == 1'b1)
full_out = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
// fix for 724006
if (rdcount_out - 1 == wr_addr && (wren_reg == 1'b1 || full_out == 1'b1))
full_out = full_int[1];
end // if (rst_in === 1'b0)
end // if (sync_clk_async_mode == 1'b1)
else begin
if (wren_in == 1'b1 && full_out == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = dip_in; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (rst_in === 1'b0) begin
// injecting error
di_ecc_col = di_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#0;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (rst_in === 1'b0)
end // if (wren_in == 1'b1 && full_out == 1'b0)
rm1w_eq = (rdcount_out_sync_2 == wr_addr) ? 1 : 0;
if (wr_addr + 1 == addr_limit) // wr_addr(FF) + 1 != 0
rm1wp1_eq = (rdcount_out_sync_2 == 0) ? 1 : 0;
else
rm1wp1_eq = (rdcount_out_sync_2 == wr_addr + 1) ? 1 : 0;
if (rst_in === 1'b0) begin
wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1);
almostfull_out = almostfull_int[0];
if (rdcount_out_sync_3 - wr_addr <= ae_full)
almostfull_int[0] = 1'b1;
else
almostfull_int[0] = 1'b0;
full_out = full_v3;
//fwft prefetch
if (empty_out == 1'b1 && wren_in === 1'b1 && fwft_prefetch_flag == 0)
fwft_prefetch_flag = 1;
end // if (rst_in === 1'b0)
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge wrclk_in)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// output register
always @(do_out or dop_out or do_outreg or dop_outreg) begin
if (sync == 1)
case (DO_REG)
0 : begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end
1 : begin
do_out_mux = do_outreg;
dop_out_mux = dop_outreg;
end
default : begin
$display("Attribute Syntax Error : The attribute DO_REG on FIFO36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG);
$finish;
end
endcase
else begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end // else: !if(sync == 1)
end // always @ (do_out or dop_out or do_outreg or dop_outreg)
// matching HW behavior to X the unused output bits
assign do_out_out = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]}
: (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]}
: (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]}
: (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]}
: (DATA_WIDTH == 72) ? do_out_mux
: do_out_mux;
// matching HW behavior to X the unused output bits
assign dop_out_out = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]}
: (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]}
: (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]}
: (DATA_WIDTH == 72) ? dop_out_mux
: 8'bx;
// matching HW behavior to pull up the unused output bits
always @(wr_addr) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : wr_addr_out = {1'b1, wr_addr[11:0]};
9 : wr_addr_out = {2'b11, wr_addr[10:0]};
18 : wr_addr_out = {3'b111, wr_addr[9:0]};
36 : wr_addr_out = {4'hf, wr_addr[8:0]};
default : wr_addr_out = wr_addr;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : wr_addr_out = wr_addr;
9 : wr_addr_out = {1'b1, wr_addr[11:0]};
18 : wr_addr_out = {2'b11, wr_addr[10:0]};
36 : wr_addr_out = {3'b111, wr_addr[9:0]};
72 : wr_addr_out = {4'hf, wr_addr[8:0]};
default : wr_addr_out = wr_addr;
endcase // case(DATA_WIDTH)
end // always @ (wr_addr)
// matching HW behavior to pull up the unused output bits
always @(rdcount_out) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : rdcount_out_out = {1'b1, rdcount_out[11:0]};
9 : rdcount_out_out = {2'b11, rdcount_out[10:0]};
18 : rdcount_out_out = {3'b111, rdcount_out[9:0]};
36 : rdcount_out_out = {4'hf, rdcount_out[8:0]};
default : rdcount_out_out = rdcount_out;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : rdcount_out_out = rdcount_out;
9 : rdcount_out_out = {1'b1, rdcount_out[11:0]};
18 : rdcount_out_out = {2'b11, rdcount_out[10:0]};
36 : rdcount_out_out = {3'b111, rdcount_out[9:0]};
72 : rdcount_out_out = {4'hf, rdcount_out[8:0]};
default : rdcount_out_out = rdcount_out;
endcase // case(DATA_WIDTH)
end // always @ (rdcount_out)
endmodule
`endcelldefine
// end of FF36_INTERNAL_VLOG - Note: Not an user primitvie
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FIFO36E2.v 0000664 0000000 0000000 00000235464 12327044266 0022523 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : FIFO36E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 11/30/2012 - intial
// 12/12/2012 - yaml update, 691724 and 691715
// 02/07/2013 - 699628 - correction to DO_PIPELINED mode
// 02/28/2013 - update to keep in sync with RAMB models
// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC.
// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY
// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there.
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FIFO36E2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter EN_ECC_PIPE = "FALSE",
parameter EN_ECC_READ = "FALSE",
parameter EN_ECC_WRITE = "FALSE",
parameter FIRST_WORD_FALL_THROUGH = "FALSE",
parameter [71:0] INIT = 72'h000000000000000000,
parameter [0:0] IS_RDCLK_INVERTED = 1'b0,
parameter [0:0] IS_RDEN_INVERTED = 1'b0,
parameter [0:0] IS_RSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter [0:0] IS_WRCLK_INVERTED = 1'b0,
parameter [0:0] IS_WREN_INVERTED = 1'b0,
parameter integer PROG_EMPTY_THRESH = 256,
parameter integer PROG_FULL_THRESH = 256,
parameter RDCOUNT_TYPE = "RAW_PNTR",
parameter integer READ_WIDTH = 4,
parameter REGISTER_MODE = "UNREGISTERED",
parameter RSTREG_PRIORITY = "RSTREG",
parameter SLEEP_ASYNC = "FALSE",
parameter [71:0] SRVAL = 72'h000000000000000000,
parameter WRCOUNT_TYPE = "RAW_PNTR",
parameter integer WRITE_WIDTH = 4
)(
output [63:0] CASDOUT,
output [7:0] CASDOUTP,
output CASNXTEMPTY,
output CASPRVRDEN,
output DBITERR,
output [63:0] DOUT,
output [7:0] DOUTP,
output [7:0] ECCPARITY,
output EMPTY,
output FULL,
output PROGEMPTY,
output PROGFULL,
output [13:0] RDCOUNT,
output RDERR,
output RDRSTBUSY,
output SBITERR,
output [13:0] WRCOUNT,
output WRERR,
output WRRSTBUSY,
input [63:0] CASDIN,
input [7:0] CASDINP,
input CASDOMUX,
input CASDOMUXEN,
input CASNXTRDEN,
input CASOREGIMUX,
input CASOREGIMUXEN,
input CASPRVEMPTY,
input [63:0] DIN,
input [7:0] DINP,
input INJECTDBITERR,
input INJECTSBITERR,
input RDCLK,
input RDEN,
input REGCE,
input RST,
input RSTREG,
input SLEEP,
input WRCLK,
input WREN
);
// define constants
localparam MODULE_NAME = "FIFO36E2";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
localparam integer ADDR_WIDTH = 15;
localparam integer INIT_WIDTH = 72;
localparam integer D_WIDTH = 64;
localparam integer DP_WIDTH = 8;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_depth = 32768;
localparam memp_depth = 4096;
localparam encode = 1'b1;
localparam decode = 1'b0;
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CASCADE_ORDER_PARALLEL = 4;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam EN_ECC_PIPE_FALSE = 0;
localparam EN_ECC_PIPE_TRUE = 1;
localparam EN_ECC_READ_FALSE = 0;
localparam EN_ECC_READ_TRUE = 1;
localparam EN_ECC_WRITE_FALSE = 0;
localparam EN_ECC_WRITE_TRUE = 1;
localparam FIRST_WORD_FALL_THROUGH_FALSE = 0;
localparam FIRST_WORD_FALL_THROUGH_TRUE = 1;
localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam RDCOUNT_TYPE_RAW_PNTR = 0;
localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam RDCOUNT_TYPE_SYNC_PNTR = 3;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_72 = 64;
localparam READ_WIDTH_A_9 = 8;
localparam REGISTER_MODE_DO_PIPELINED = 1;
localparam REGISTER_MODE_REGISTERED = 2;
localparam REGISTER_MODE_UNREGISTERED = 0;
localparam RSTREG_PRIORITY_REGCE = 1;
localparam RSTREG_PRIORITY_RSTREG = 0;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam WRCOUNT_TYPE_RAW_PNTR = 0;
localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam WRCOUNT_TYPE_SYNC_PNTR = 3;
localparam WRITE_WIDTH_18 = 16;
localparam WRITE_WIDTH_36 = 32;
localparam WRITE_WIDTH_4 = 4;
localparam WRITE_WIDTH_72 = 64;
localparam WRITE_WIDTH_9 = 8;
`ifndef XIL_DR
localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE;
localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ;
localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE;
localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH;
localparam [71:0] INIT_REG = INIT;
localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED;
localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED;
localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED;
localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED;
localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH;
localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH;
localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE;
localparam [6:0] READ_WIDTH_REG = READ_WIDTH;
localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE;
localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [71:0] SRVAL_REG = SRVAL;
localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE;
localparam [6:0] WRITE_WIDTH_REG = WRITE_WIDTH;
`endif
wire [2:0] CASCADE_ORDER_A_BIN;
wire CLOCK_DOMAINS_BIN;
wire EN_ECC_PIPE_BIN;
wire EN_ECC_READ_BIN;
wire EN_ECC_WRITE_BIN;
wire FIRST_WORD_FALL_THROUGH_BIN;
wire [INIT_WIDTH-1:0] INIT_BIN;
wire IS_RDCLK_INVERTED_BIN;
wire IS_RDEN_INVERTED_BIN;
wire IS_RSTREG_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire IS_WRCLK_INVERTED_BIN;
wire IS_WREN_INVERTED_BIN;
wire [12:0] PROG_EMPTY_THRESH_BIN;
wire [12:0] PROG_FULL_THRESH_BIN;
wire [1:0] RDCOUNT_TYPE_BIN;
wire [6:0] READ_WIDTH_A_BIN;
wire [1:0] REGISTER_MODE_BIN;
wire RSTREG_PRIORITY_BIN;
wire SLEEP_ASYNC_BIN;
wire [INIT_WIDTH-1:0] SRVAL_BIN;
wire [1:0] WRCOUNT_TYPE_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
reg trig_gsr = 1'b0;
tri0 glblGSR = glbl.GSR || trig_gsr;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "FIFO36E2_dr.v"
`endif
wire CASNXTEMPTY_out;
wire CASPRVRDEN_out;
wire DBITERR_out;
wire EMPTY_out;
wire FULL_out;
reg PROGEMPTY_out = 1;
reg PROGFULL_out = 0;
reg RDERR_out;
wire RDRSTBUSY_out;
wire SBITERR_out;
reg WRERR_out;
wire WRRSTBUSY_out;
wire [ADDR_WIDTH:0] RDCOUNT_out;
wire [ADDR_WIDTH:0] WRCOUNT_out;
wire [DP_WIDTH-1:0] CASDOUTP_out;
wire [D_WIDTH-1:0] CASDOUT_out;
wire [D_WIDTH-1:0] DOUT_out;
wire [DP_WIDTH-1:0] DOUTP_out;
wire [DP_WIDTH-1:0] ECCPARITY_out;
wire CASNXTEMPTY_delay;
wire CASPRVRDEN_delay;
wire DBITERR_delay;
wire EMPTY_delay;
wire FULL_delay;
wire PROGEMPTY_delay;
wire PROGFULL_delay;
wire RDERR_delay;
wire RDRSTBUSY_delay;
wire SBITERR_delay;
wire WRERR_delay;
wire WRRSTBUSY_delay;
wire [ADDR_WIDTH:0] RDCOUNT_delay;
wire [ADDR_WIDTH:0] WRCOUNT_delay;
wire [D_WIDTH-1:0] CASDOUT_delay;
wire [D_WIDTH-1:0] DOUT_delay;
wire [DP_WIDTH-1:0] CASDOUTP_delay;
wire [DP_WIDTH-1:0] DOUTP_delay;
wire [DP_WIDTH-1:0] ECCPARITY_delay;
wire CASDOMUXEN_A_in;
wire CASDOMUXA_in;
// wire CASNXTRDEN_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXA_in;
wire CASPRVEMPTY_in;
wire INJECTDBITERR_in;
wire INJECTSBITERR_in;
wire RDCLK_in;
wire RDEN_in;
wire REGCE_in;
wire RSTREG_in;
wire RST_in;
wire SLEEP_in;
wire WRCLK_in;
wire WREN_in;
wire [D_WIDTH-1:0] CASDINA_in;
wire [D_WIDTH-1:0] DIN_in;
wire [DP_WIDTH-1:0] CASDINPA_in;
wire [DP_WIDTH-1:0] DINP_in;
wire CASDOMUXEN_delay;
wire CASDOMUX_delay;
wire CASNXTRDEN_delay;
wire CASOREGIMUXEN_delay;
wire CASOREGIMUX_delay;
wire CASPRVEMPTY_delay;
wire INJECTDBITERR_delay;
wire INJECTSBITERR_delay;
wire RDCLK_delay;
wire RDEN_delay;
wire REGCE_delay;
wire RSTREG_delay;
wire RST_delay;
wire SLEEP_delay;
wire WRCLK_delay;
wire WREN_delay;
wire [D_WIDTH-1:0] CASDIN_delay;
wire [D_WIDTH-1:0] DIN_delay;
wire [DP_WIDTH-1:0] CASDINP_delay;
wire [DP_WIDTH-1:0] DINP_delay;
// internal variables, signals, busses
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer wb=0;
integer rd_loops_a = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
reg INIT_MEM = 0;
integer rdcount_adj = 0;
integer wrcount_adj = 0;
integer wr_adj = 0;
wire RDEN_lat;
wire RDEN_reg;
reg fill_lat=0;
reg fill_reg=0;
wire RDEN_ecc;
reg fill_ecc=0;
wire SLEEP_int;
reg SLEEP_reg = 1'b0;
reg SLEEP_reg1 = 1'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
wire prog_empty;
reg ram_full_c = 0;
wire ram_empty;
reg ram_empty_i = 1;
reg ram_empty_c = 1;
reg o_lat_empty = 1;
reg o_reg_empty = 1;
reg o_ecc_empty = 1;
wire [1:0] output_stages;
reg [6:0] error_bit = 7'b0;
reg [DP_WIDTH-1:0] eccparity_reg = 8'h00;
wire o_stages_full;
wire o_stages_empty;
reg o_stages_full_sync=0;
reg o_stages_full_sync1=0;
reg o_stages_full_sync2=0;
reg o_stages_full_sync3=0;
wire prog_full;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire mem_wr_clk_b;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_clk_a;
wire mem_rd_en_a;
wire mem_rst_a;
reg mem [0 : mem_depth-1];
reg [D_WIDTH-1 : 0] mem_rd_a;
wire [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
wire [D_WIDTH-1 : 0] mem_a_reg_mux;
wire [D_WIDTH-1 : 0] mem_a_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
wire [D_WIDTH-1 : 0] mem_a_out;
reg [D_WIDTH-1 : 0] mem_a_pipe;
reg memp [0 : memp_depth - 1];
reg [DP_WIDTH-1 : 0] memp_rd_a;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
wire [DP_WIDTH-1 : 0] memp_a_reg_mux;
wire [DP_WIDTH-1 : 0] memp_a_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
wire [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH-1 : 0] memp_a_pipe;
wire dbit_int;
wire sbit_int;
reg dbit_lat = 0;
reg sbit_lat = 0;
reg dbit_pipe = 0;
reg sbit_pipe = 0;
reg dbit_reg = 0;
reg sbit_reg = 0;
wire [D_WIDTH-1 : 0] mem_a_ecc;
wire [D_WIDTH-1 : 0] mem_a_ecc_cor;
wire [DP_WIDTH-1 : 0] memp_a_ecc;
wire [DP_WIDTH-1 : 0] memp_a_ecc_cor;
wire dbit_ecc;
wire sbit_ecc;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr3 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd3 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0;
wire [ADDR_WIDTH-1:0] rd_addr_wr;
wire [ADDR_WIDTH-1:0] wr_addr_rd;
wire [ADDR_WIDTH:0] wr_simple_raw;
wire [ADDR_WIDTH:0] rd_simple_raw;
wire [ADDR_WIDTH-1:0] wr_simple;
wire [ADDR_WIDTH-1:0] rd_simple;
reg [ADDR_WIDTH-1:0] wr_simple_sync;
reg [ADDR_WIDTH-1:0] rd_simple_sync;
//reset logic variables
reg WRRST_int = 1'b0;
reg RST_sync = 1'b0;
reg WRRST_done = 1'b0;
reg WRRST_done1 = 1'b0;
reg WRRST_done2 = 1'b0;
wire RDRST_int;
reg RDRST_done = 1'b0;
reg RDRST_done1 = 1'b0;
reg RDRST_done2 = 1'b0;
wire WRRST_done_wr;
reg WRRST_in_sync_rd = 1'b0;
reg WRRST_in_sync_rd1 = 1'b0;
reg WRRSTBUSY_dly = 1'b0;
reg WRRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly = 1'b0;
reg RDRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly2 = 1'b0;
wire [7:0] synd_wr;
wire [7:0] synd_rd;
wire [7:0] synd_ecc;
wire wrclk_ecc_out;
reg sdp_mode = 1'b1;
reg sdp_mode_wr = 1'b1;
reg sdp_mode_rd = 1'b1;
// full/empty variables
wire [ADDR_WIDTH-1:0] full_count;
wire [ADDR_WIDTH-1:0] full_count_masked;
wire [8:0] m_full;
wire [8:0] m_full_raw;
wire [5:0] n_empty;
wire [5:0] unr_ratio;
wire [ADDR_WIDTH+1:0] prog_full_val;
wire [ADDR_WIDTH+1:0] prog_empty_val;
reg ram_full_i;
wire ram_one_from_full;
wire ram_two_from_full;
wire ram_one_read_from_not_full;
wire [ADDR_WIDTH-1:0] empty_count;
wire ram_one_read_from_empty;
wire ram_one_write_from_not_empty;
reg en_clk_sync = 1'b0;
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
// input output assignments
assign #(out_delay) CASDOUT = CASDOUT_delay;
assign #(out_delay) CASDOUTP = CASDOUTP_delay;
assign #(out_delay) CASNXTEMPTY = CASNXTEMPTY_delay;
assign #(out_delay) CASPRVRDEN = CASPRVRDEN_delay;
assign #(out_delay) DBITERR = DBITERR_delay;
assign #(out_delay) DOUT = DOUT_delay;
assign #(out_delay) DOUTP = DOUTP_delay;
assign #(out_delay) ECCPARITY = ECCPARITY_delay;
assign #(out_delay) EMPTY = EMPTY_delay;
assign #(out_delay) FULL = FULL_delay;
assign #(out_delay) PROGEMPTY = PROGEMPTY_delay;
assign #(out_delay) PROGFULL = PROGFULL_delay;
assign #(out_delay) RDCOUNT = RDCOUNT_delay;
assign #(out_delay) RDERR = RDERR_delay;
assign #(out_delay) RDRSTBUSY = RDRSTBUSY_delay;
assign #(out_delay) SBITERR = SBITERR_delay;
assign #(out_delay) WRCOUNT = WRCOUNT_delay;
assign #(out_delay) WRERR = WRERR_delay;
assign #(out_delay) WRRSTBUSY = WRRSTBUSY_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) RDCLK_delay = RDCLK;
assign #(inclk_delay) WRCLK_delay = WRCLK;
assign #(in_delay) CASDINP_delay = CASDINP;
assign #(in_delay) CASDIN_delay = CASDIN;
assign #(in_delay) CASDOMUXEN_delay = CASDOMUXEN;
assign #(in_delay) CASDOMUX_delay = CASDOMUX;
assign #(in_delay) CASNXTRDEN_delay = CASNXTRDEN;
assign #(in_delay) CASOREGIMUXEN_delay = CASOREGIMUXEN;
assign #(in_delay) CASOREGIMUX_delay = CASOREGIMUX;
assign #(in_delay) CASPRVEMPTY_delay = CASPRVEMPTY;
assign #(in_delay) DINP_delay = DINP;
assign #(in_delay) DIN_delay = DIN;
assign #(in_delay) INJECTDBITERR_delay = INJECTDBITERR;
assign #(in_delay) INJECTSBITERR_delay = INJECTSBITERR;
assign #(in_delay) RDEN_delay = RDEN;
assign #(in_delay) REGCE_delay = REGCE;
assign #(in_delay) RSTREG_delay = RSTREG;
assign #(in_delay) RST_delay = RST;
assign #(in_delay) SLEEP_delay = SLEEP;
assign #(in_delay) WREN_delay = WREN;
`endif // `ifndef XIL_TIMING
assign CASDOUTP_delay = CASDOUTP_out;
assign CASDOUT_delay = CASDOUT_out;
assign CASNXTEMPTY_delay = CASNXTEMPTY_out;
assign CASPRVRDEN_delay = CASPRVRDEN_out;
assign DBITERR_delay = DBITERR_out;
assign DOUTP_delay = DOUTP_out;
assign DOUT_delay = DOUT_out;
assign ECCPARITY_delay = ECCPARITY_out;
assign EMPTY_delay = EMPTY_out;
assign FULL_delay = FULL_out;
assign PROGEMPTY_delay = PROGEMPTY_out;
assign PROGFULL_delay = PROGFULL_out;
assign RDCOUNT_delay = RDCOUNT_out;
assign RDERR_delay = RDERR_out;
assign RDRSTBUSY_delay = RDRSTBUSY_out;
assign SBITERR_delay = SBITERR_out;
assign WRCOUNT_delay = WRCOUNT_out;
assign WRERR_delay = WRERR_out;
assign WRRSTBUSY_delay = WRRSTBUSY_out;
assign CASDINPA_in = CASDINP_delay;
assign CASDINA_in = CASDIN_delay;
assign CASDOMUXEN_A_in = CASDOMUXEN_delay;
assign CASDOMUXA_in = CASDOMUX_delay;
// assign CASNXTRDEN_in = CASNXTRDEN_delay;
assign CASOREGIMUXEN_A_in = CASOREGIMUXEN_delay;
assign CASOREGIMUXA_in = CASOREGIMUX_delay;
assign CASPRVEMPTY_in = CASPRVEMPTY_delay;
assign DINP_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_delay : DINP_delay;
assign DIN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ? CASDIN_delay : DIN_delay;
assign INJECTDBITERR_in = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTDBITERR_delay;
assign INJECTSBITERR_in = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTSBITERR_delay || INJECTDBITERR_delay;
assign RDCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) && (en_clk_sync == 1'b1)) ?
WRCLK_delay ^ IS_WRCLK_INVERTED_BIN :
RDCLK_delay ^ IS_RDCLK_INVERTED_BIN;
assign RDEN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
CASNXTRDEN_delay : RDEN_delay ^ IS_RDEN_INVERTED_BIN;
assign REGCE_in = REGCE_delay;
assign RSTREG_in = RSTREG_delay ^ IS_RSTREG_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign SLEEP_in = SLEEP_delay;
assign WRCLK_in = WRCLK_delay ^ IS_WRCLK_INVERTED_BIN;
assign WREN_in = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_delay || FULL_out) : WREN_delay ^ IS_WREN_INVERTED_BIN;
assign mem_rd_clk_a = RDCLK_in;
assign mem_wr_clk_b = WRCLK_in;
assign mem_wr_en_b = WREN_in && ~FULL_out && ~WRRSTBUSY_out;
assign mem_rd_en_a = RDEN_lat && ~ram_empty && ~RDRST_int;
wire [35:0] bit_err_pat;
assign bit_err_pat = INJECTDBITERR_in ? 36'h400000004 : INJECTSBITERR_in ? 36'h000000004 : 36'h0;
assign mem_wr_b = DIN_in ^ {bit_err_pat, 28'h0};
assign memp_wr_b = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr : DINP_in;
initial begin
trig_attr <= #1 ~trig_attr;
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
(CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign EN_ECC_PIPE_BIN =
(EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE :
(EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE :
EN_ECC_PIPE_FALSE;
assign EN_ECC_READ_BIN =
(EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE :
(EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE :
EN_ECC_READ_FALSE;
assign EN_ECC_WRITE_BIN =
(EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE :
(EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE :
EN_ECC_WRITE_FALSE;
assign FIRST_WORD_FALL_THROUGH_BIN =
(FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE :
(FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE :
FIRST_WORD_FALL_THROUGH_FALSE;
assign INIT_BIN = INIT_REG;
assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG;
assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG;
assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG;
assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG;
assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG;
assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG;
assign RDCOUNT_TYPE_BIN =
(RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR :
(RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT :
(RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT :
(RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR :
RDCOUNT_TYPE_RAW_PNTR;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_REG == 36) ? READ_WIDTH_A_36 :
(READ_WIDTH_REG == 72) ? READ_WIDTH_A_72 :
READ_WIDTH_A_4;
assign REGISTER_MODE_BIN =
(REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED :
(REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED :
(REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED :
REGISTER_MODE_UNREGISTERED;
assign RSTREG_PRIORITY_BIN =
(RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG :
(RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE :
RSTREG_PRIORITY_RSTREG;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_BIN = SRVAL_REG;
assign WRCOUNT_TYPE_BIN =
(WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR :
(WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT :
(WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT :
(WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR :
WRCOUNT_TYPE_RAW_PNTR;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 :
(WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 :
(WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 :
(WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 :
(WRITE_WIDTH_REG == 72) ? WRITE_WIDTH_72 :
WRITE_WIDTH_4;
always @ (trig_attr) begin
#1;
if ((CASCADE_ORDER_REG != "NONE") &&
(CASCADE_ORDER_REG != "FIRST") &&
(CASCADE_ORDER_REG != "LAST") &&
(CASCADE_ORDER_REG != "MIDDLE") &&
(CASCADE_ORDER_REG != "PARALLEL")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL.", MODULE_NAME, CASCADE_ORDER_REG);
attr_err = 1'b1;
end
if ((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON")) begin
$display("Attribute Syntax Error : The attribute CLOCK_DOMAINS on %s instance %m is set to %s. Legal values for this attribute are INDEPENDENT or COMMON.", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((EN_ECC_PIPE_REG != "FALSE") &&
(EN_ECC_PIPE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_PIPE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_PIPE_REG);
attr_err = 1'b1;
end
if ((EN_ECC_READ_REG != "FALSE") &&
(EN_ECC_READ_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_READ_REG);
attr_err = 1'b1;
end
if ((EN_ECC_WRITE_REG != "FALSE") &&
(EN_ECC_WRITE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_WRITE_REG);
attr_err = 1'b1;
end
if ((FIRST_WORD_FALL_THROUGH_REG != "FALSE") &&
(FIRST_WORD_FALL_THROUGH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG);
attr_err = 1'b1;
end
if ((IS_RDCLK_INVERTED_REG < 1'b0) || (IS_RDCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RDCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RDEN_INVERTED_REG < 1'b0) || (IS_RDEN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RDEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREG_INVERTED_REG < 1'b0) || (IS_RSTREG_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREG_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_WRCLK_INVERTED_REG < 1'b0) || (IS_WRCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_WRCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_WREN_INVERTED_REG < 1'b0) || (IS_WREN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_WREN_INVERTED_REG);
attr_err = 1'b1;
end
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to 8191.", MODULE_NAME, PROG_EMPTY_THRESH_REG);
attr_err = 1'b1;
end
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to 8191.", MODULE_NAME, PROG_FULL_THRESH_REG);
attr_err = 1'b1;
end
if ((RDCOUNT_TYPE_REG != "RAW_PNTR") &&
(RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SYNC_PNTR")) begin
$display("Attribute Syntax Error : The attribute RDCOUNT_TYPE on %s instance %m is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR.", MODULE_NAME, RDCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_REG != 4) &&
(READ_WIDTH_REG != 9) &&
(READ_WIDTH_REG != 18) &&
(READ_WIDTH_REG != 36) &&
(READ_WIDTH_REG != 72)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 4, 9 18, 36 or 72.", MODULE_NAME, READ_WIDTH_REG);
attr_err = 1'b1;
end
if ((REGISTER_MODE_REG != "UNREGISTERED") &&
(REGISTER_MODE_REG != "DO_PIPELINED") &&
(REGISTER_MODE_REG != "REGISTERED")) begin
$display("Attribute Syntax Error : The attribute REGISTER_MODE on %s instance %m is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED.", MODULE_NAME, REGISTER_MODE_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_REG != "RSTREG") &&
(RSTREG_PRIORITY_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_REG);
attr_err = 1'b1;
end
if ((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SLEEP_ASYNC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((WRCOUNT_TYPE_REG != "RAW_PNTR") &&
(WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SYNC_PNTR")) begin
$display("Attribute Syntax Error : The attribute WRCOUNT_TYPE on %s instance %m is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR.", MODULE_NAME, WRCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_REG != 4) &&
(WRITE_WIDTH_REG != 9) &&
(WRITE_WIDTH_REG != 18) &&
(WRITE_WIDTH_REG != 36) &&
(WRITE_WIDTH_REG != 72)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", MODULE_NAME, WRITE_WIDTH_REG);
attr_err = 1'b1;
end
case (READ_WIDTH_REG)
4 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/4)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/4);
attr_err = 1'b1;
end
end
9 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/8)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/8);
attr_err = 1'b1;
end
end
18 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/16)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/16);
attr_err = 1'b1;
end
end
36 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/32)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/32);
attr_err = 1'b1;
end
end
72 : begin
if ((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > mem_depth/64)) begin
$display("Attribute Syntax Error : The attribute PROG_EMPTY_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_EMPTY_THRESH_REG, mem_depth/64);
attr_err = 1'b1;
end
end
default : begin
$display("Attribute Syntax Error : The attribute READ_WIDTH on %s instance %m is out of range on PROG_EMPTY_THRESH check.", MODULE_NAME);
attr_err = 1'b1;
end
endcase
case (WRITE_WIDTH_REG)
4 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/4)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/4);
attr_err = 1'b1;
end
end
9 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/8)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/8);
attr_err = 1'b1;
end
end
18 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/16)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/16);
attr_err = 1'b1;
end
end
36 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/32)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/32);
attr_err = 1'b1;
end
end
72 : begin
if ((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > mem_depth/64)) begin
$display("Attribute Syntax Error : The attribute PROG_FULL_THRESH on %s instance %m is set to %d. Legal values for this attribute are 1 to %d.", MODULE_NAME, PROG_FULL_THRESH_REG, mem_depth/64);
attr_err = 1'b1;
end
end
default : begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH on %s instance %m is out of range on PROG_FULL_THRESH check.", MODULE_NAME);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) $finish;
end
assign output_stages =
((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) &&
(REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b11 :
((EN_ECC_PIPE_BIN != EN_ECC_PIPE_TRUE) &&
(REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 :
((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ^
(REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ^
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b01 : 2'b10;
assign wr_addr_b_mask =
(WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
SLEEP_reg <= 1'b0;
SLEEP_reg1 <= 1'b0;
end
else begin
SLEEP_reg <= SLEEP_in;
SLEEP_reg1 <= SLEEP_reg;
end
end
assign SLEEP_int = (SLEEP_ASYNC_BIN == SLEEP_ASYNC_FALSE) ? SLEEP_reg : SLEEP_in;
assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg :
REGCE_in;
assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int :
(RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in :
(RSTREG_in && REGCE_A_int);
assign RDEN_lat = RDEN_in || fill_reg || fill_ecc || fill_lat;
assign RDEN_ecc = (RDEN_in || fill_reg || fill_ecc) && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE);
assign RDEN_reg = RDEN_in || fill_reg ;
assign DOUT_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINA_in : mem_a_mux ^ mem_rm_douta;
assign DOUTP_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINPA_in : memp_a_mux ^ memp_rm_douta;
assign mem_a_mux = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ?
mem_a_reg : mem_a_lat;
assign memp_a_mux = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ?
memp_a_reg : memp_a_lat;
assign ECCPARITY_out = eccparity_reg;
assign mem_a_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? mem_a_pipe : mem_a_ecc_cor;
assign memp_a_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? memp_a_pipe : memp_a_ecc_cor;
assign dbit_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? dbit_pipe : dbit_int;
assign sbit_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? sbit_pipe : sbit_int;
assign DBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? dbit_reg : dbit_lat;
assign SBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? sbit_reg : sbit_lat;
assign INIT_A_int =
(READ_WIDTH_A_BIN == READ_WIDTH_A_9) ? {{8{INIT_BIN[8]}}, {8{INIT_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{INIT_BIN[17:16]}}, {4{INIT_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{INIT_BIN[35:32]}}, {2{INIT_BIN[31:0]}}} :
INIT_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN == READ_WIDTH_A_9) ? {{8{SRVAL_BIN[8]}}, {8{SRVAL_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{SRVAL_BIN[17:16]}}, {4{SRVAL_BIN[15:0]}}}:
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{SRVAL_BIN[35:32]}}, {2{SRVAL_BIN[31:0]}}}:
SRVAL_BIN;
assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr;
assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd;
assign o_stages_empty =
(output_stages==2'b00) ? ram_empty :
(output_stages==2'b01) ? o_lat_empty :
(output_stages==2'b11) ? o_reg_empty : // FWFT + ECC + REG // FWFT + REG
((output_stages==2'b10) && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) ? o_reg_empty :
o_ecc_empty; // 2 FWFT + ECC or REG + ECC
assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync;
// cascade out
assign CASDOUT_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTP_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASNXTEMPTY_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
EMPTY_out : 1'b0;
assign CASPRVRDEN_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out) : 1'b0;
// start model internals
// integers / constants
always begin
if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b;
else wr_adj = 1;
@(wr_loops_b or rd_loops_a);
end
always begin
if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) ||
((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0)))
wrcount_adj = 1;
else if ((output_stages>1) ||
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE))
wrcount_adj = output_stages*wr_adj;
else
wrcount_adj = 0;
rdcount_adj = output_stages;
@(wr_adj or output_stages or wr_loops_b or rd_loops_a);
end
// reset logic
assign RDRSTBUSY_out = RDRST_int;
assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly;
assign mem_rst_a = RDRST_int;
// RST_in sampled by WRCLK cleared by WR done
always @ (posedge mem_wr_clk_b) begin
if (RST_in && ~RST_sync) begin
RST_sync <= 1'b1;
end
else if (WRRST_done) begin
RST_sync <= 1'b0;
end
end
assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done;
always @ (posedge mem_wr_clk_b) begin
if (RST_in && ~WRRSTBUSY_out) begin
WRRST_int <= #1 1'b1;
end
else if (WRRST_done_wr) begin
WRRST_int <= #1 1'b0;
end
end
// WRRST_int sampled by RDCLK twice => RDRST_int in CDI
assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd;
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
WRRST_in_sync_rd1 <= 1'b0;
WRRST_in_sync_rd <= 1'b0;
end
else begin
WRRST_in_sync_rd1 <= #1 WRRST_int;
WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1;
end
end
// 3 rdclks to be done RD side
always @ (posedge mem_rd_clk_a) begin
if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRST_done2 <= 1'b0;
RDRST_done1 <= 1'b0;
RDRST_done <= 1'b0;
end
else begin
RDRST_done2 <= RDRST_int;
RDRST_done1 <= RDRST_done2;
RDRST_done <= RDRST_done1;
end
end
// 3 wrclks to be done WR side after RDRST_done
always @ (posedge mem_wr_clk_b) begin
if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRST_done2 <= 1'b0;
WRRST_done1 <= 1'b0;
WRRST_done <= 1'b0;
end
else if (WRRST_int) begin
WRRST_done2 <= RDRST_done;
WRRST_done1 <= WRRST_done2;
WRRST_done <= WRRST_done1;
end
end
// bug fix
always @ (posedge mem_rd_clk_a) begin
if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRSTBUSY_dly2 <= 1'b0;
RDRSTBUSY_dly1 <= 1'b0;
RDRSTBUSY_dly <= 1'b0;
end
else begin
RDRSTBUSY_dly2 <= RDRST_int;
RDRSTBUSY_dly1 <= RDRSTBUSY_dly2;
RDRSTBUSY_dly <= RDRSTBUSY_dly1;
end
end
always @ (posedge mem_wr_clk_b) begin
if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRSTBUSY_dly1 <= 1'b0;
WRRSTBUSY_dly <= 1'b0;
end
else begin
WRRSTBUSY_dly1 <= RDRSTBUSY_dly;
WRRSTBUSY_dly <= WRRSTBUSY_dly1;
end
end
// cascade control
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
// output register
assign mem_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? CASDINA_in : mem_a_lat;
assign memp_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? CASDINPA_in : memp_a_lat;
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= mem_a_reg_mux;
memp_a_reg <= memp_a_reg_mux;
end
end
// bit err reg
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RSTREG_A_int) begin
dbit_reg <= 1'b0;
sbit_reg <= 1'b0;
end
else if (REGCE_A_int) begin
dbit_reg <= dbit_lat;
sbit_reg <= sbit_lat;
end
end
// ecc pipe register
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_pipe, mem_a_pipe} <= INIT_A_int;
dbit_pipe <= 1'b0;
sbit_pipe <= 1'b0;
end
else if (RSTREG_A_int) begin
{memp_a_pipe, mem_a_pipe} <= SRVAL_A_int;
dbit_pipe <= 1'b0;
sbit_pipe <= 1'b0;
end
else if (RDEN_ecc) begin
mem_a_pipe <= mem_a_ecc_cor;
memp_a_pipe <= memp_a_ecc_cor;
dbit_pipe <= dbit_int;
sbit_pipe <= sbit_int;
end
end
// RDCOUNT sync to RDCLK
assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0];
assign RDCOUNT_out = RDRST_int ? 1'b0 :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync/(rd_loops_a) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) ? rd_simple_sync/(rd_loops_a) + rdcount_adj :
(rd_addr_a/rd_loops_a);
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_simple_sync <= 0;
end
else begin
if (rd_simple == {ADDR_WIDTH-1{1'b0}}) begin
rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]};
end
else begin
rd_simple_sync <= rd_simple;
end
end
end
// WRCOUNT sync to WRCLK
assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr};
assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0];
assign WRCOUNT_out = WRRSTBUSY_out ? 1'b0 :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? (wr_addr_b/(wr_loops_b)) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? (wr_addr_rd/(wr_loops_b)) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync/(wr_loops_b) :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync/(wr_loops_b) + wrcount_adj :
(wr_addr_b/wr_loops_b);
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_simple_sync <= 0;
end
else begin
wr_simple_sync <= wr_simple;
end
end
// with any output stage or FWFT fill the ouptut latch
// when ram not empty and o_latch empty
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_lat_empty <= 1;
end
else if (fill_lat == 1) begin
o_lat_empty <= 0;
end
else if ((ram_empty == 1) && RDEN_lat) begin
o_lat_empty <= 1;
end
end
always @ (negedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
fill_lat <= 0;
end
else if ((ram_empty == 0) && (o_lat_empty == 1) && (output_stages>0)) begin
fill_lat <= 1;
end
else begin
fill_lat <= 0;
end
end
// FWFT and
// REGISTERED not ECC_PIPE fill the ouptut register when o_latch not empty.
// REGISTERED and ECC_PIPE fill the ouptut register when o_ecc not empty.
// Empty on external read and prev stage also empty
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_reg_empty <= 1;
end
else if ((o_lat_empty == 0) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin
o_reg_empty <= 0;
end
else if ((o_ecc_empty == 0) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin
o_reg_empty <= 0;
end
else if ((o_lat_empty == 1) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin
o_reg_empty <= 1;
end
else if ((o_ecc_empty == 1) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin
o_reg_empty <= 1;
end
end
always @ (negedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
fill_reg <= 0;
end
else if ((o_lat_empty == 0) && (o_reg_empty == 1) &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE) &&
(output_stages==2)) begin
fill_reg <= 1;
end
else if ((o_ecc_empty == 0) && (o_reg_empty == 1) &&
(output_stages==3)) begin
fill_reg <= 1;
end
else begin
fill_reg <= 0;
end
end
// FWFT and
// ECC_PIPE fill the ecc register when o_latch not empty.
// Empty on external read and o_lat also empty
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_ecc_empty <= 1;
end
else if ((o_lat_empty == 0) && RDEN_ecc) begin
o_ecc_empty <= 0;
end
else if ((o_lat_empty == 1) && RDEN_ecc) begin
o_ecc_empty <= 1;
end
end
always @ (negedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
fill_ecc <= 0;
end
else if ((o_lat_empty == 0) && (o_ecc_empty == 1) &&
(output_stages>1) &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin
fill_ecc <= 1;
end
else begin
fill_ecc <= 0;
end
end
// read engine
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_a) begin
$display("DRC Error : READ on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (ra=0;ra> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if (mem_rd_en_a) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin
mem_a_lat <= mem_a_ecc;
memp_a_lat <= memp_a_ecc;
end
else begin
mem_a_lat <= mem_rd_a;
memp_a_lat <= memp_rd_a;
end
end
end
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_addr_a <= {ADDR_WIDTH-1{1'b0}};
rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_rd_en_a) begin
rd_addr_a <= rd_addr_a + rd_loops_a;
end
rd_addr_a_wr <= rd_addr_a;
wr_addr_sync_rd2 <= wr_addr_b_rd;
wr_addr_sync_rd1 <= wr_addr_sync_rd2;
wr_addr_sync_rd <= wr_addr_sync_rd1;
end
end
// write engine
always @ (posedge mem_wr_clk_b) begin
if (mem_wr_en_b) begin
if (SLEEP_in || SLEEP_int) begin
$display("DRC Error : WRITE on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
end
else begin
for (wb=0;wb WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}};
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR)
WRERR_out <= 1'b0;
else if (WREN_in && (FULL_out || WRRSTBUSY_out))
WRERR_out <= 1'b1;
else
WRERR_out <= 1'b0;
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_addr_b <= {ADDR_WIDTH-1{1'b0}};
wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}};
o_stages_full_sync2 <= 1'b0;
o_stages_full_sync1 <= 1'b0;
o_stages_full_sync <= 1'b0;
rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_wr_en_b) begin
wr_addr_b <= wr_addr_b + wr_loops_b;
end
wr_addr_b_rd <= wr_addr_b;
o_stages_full_sync2 <= ~o_stages_empty;
o_stages_full_sync1 <= o_stages_full_sync2;
o_stages_full_sync <= o_stages_full_sync1;
rd_addr_sync_wr2 <= rd_addr_a_wr;
rd_addr_sync_wr1 <= rd_addr_sync_wr2;
rd_addr_sync_wr <= rd_addr_sync_wr1;
end
end
// full flag
assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out));
assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full;
assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0;
assign m_full = ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b);
assign m_full_raw = ((output_stages>1) && o_stages_full) ? output_stages*rd_loops_a :
(output_stages==1 && o_stages_full) ? rd_loops_a : 0;
assign n_empty = output_stages;
assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a;
assign full_count_masked = full_count & wr_addr_b_mask;
assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b};
assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i;
// ram_full independent clocks is one_from_full common clocks
assign ram_one_from_full = ((full_count < 2*wr_loops_b) && (full_count > 0));
assign ram_two_from_full = ((full_count < 3*wr_loops_b) && (full_count > 0));
// when full common clocks, next read makes it not full
assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c);
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_c <= 1'b0;
end
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a < wr_loops_b)) &&
ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_rd_en_a && ram_one_read_from_not_full) begin
ram_full_c <= 1'b0;
end
else begin
ram_full_c <= ram_full_c;
end
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_i <= 1'b0;
end
else if (mem_wr_en_b && ram_two_from_full && ~ram_full_i) begin
ram_full_i <= 1'b1;
end
else if (~ram_one_from_full) begin
ram_full_i <= 1'b0;
end
else begin
ram_full_i <= ram_full_i;
end
end
always @ (posedge mem_wr_clk_b or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
PROGFULL_out <= 1'b0;
end
else begin
PROGFULL_out <= prog_full;
end
end
// empty flag
assign EMPTY_out = o_stages_empty;
assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i;
assign ram_one_read_from_empty = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty;
assign ram_one_write_from_not_empty = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a);
assign prog_empty = ((empty_count < prog_empty_val) || ram_empty) && ~FULL_out;
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_c <= 1'b1;
// RD only makes empty
else if (~mem_wr_en_b &&
mem_rd_en_a &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// RD and WR when one read from empty and RD more than WR makes empty
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a > wr_loops_b)) &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR
else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c))
ram_empty_c <= 1'b0;
else
ram_empty_c <= ram_empty_c;
end
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_i <= 1'b1;
else if (mem_rd_en_a && ram_one_read_from_empty) // RDEN_in ?
ram_empty_i <= 1'b1;
else if (empty_count < rd_loops_a)
ram_empty_i <= 1'b1;
else
ram_empty_i <= 1'b0;
end
assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a};
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RDRST_int)
PROGEMPTY_out <= 1'b1;
else
PROGEMPTY_out <= prog_empty;
end
// eccparity is flopped
assign synd_wr = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ?
fn_ecc(encode, DIN_in, DINP_in) : 8'b0;
assign synd_rd = (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) ?
fn_ecc(decode, mem_rd_a, memp_rd_a) : 8'b0;
assign synd_ecc = (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) ?
synd_rd ^ memp_rd_a : 8'b0;
assign sbit_int = (|synd_ecc && synd_ecc[7]);
assign dbit_int = (|synd_ecc && ~synd_ecc[7]);
// make sure new read has happend before checking for error.
// INIT/SRVAL values shouldn't cause error.
always @(posedge mem_rd_clk_a) begin
if (mem_rst_a) begin
sbit_lat <= 1'b0;
dbit_lat <= 1'b0;
error_bit <= 7'b0;
end
else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin
sbit_lat <= sbit_ecc;
dbit_lat <= dbit_ecc;
error_bit <= synd_ecc[6:0];
end
end
assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ?
fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) :
{memp_rd_a, mem_rd_a};
assign wrclk_ecc_out = mem_wr_clk_b && (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE);
always @ (posedge wrclk_ecc_out or glblGSR) begin
if(glblGSR)
eccparity_reg <= 8'h00;
else if (mem_wr_en_b)
eccparity_reg <= synd_wr;
end
specify
( CASDIN *> CASDOUT) = (0:0:0, 0:0:0);
( CASDIN *> DOUT) = (0:0:0, 0:0:0);
( CASDINP *> CASDOUTP) = (0:0:0, 0:0:0);
( CASDINP *> DOUTP) = (0:0:0, 0:0:0);
( CASPRVEMPTY *> CASPRVRDEN) = (0:0:0, 0:0:0);
( RDCLK *> CASDOUT) = (0:0:0, 0:0:0);
( RDCLK *> CASDOUTP) = (0:0:0, 0:0:0);
( RDCLK *> CASNXTEMPTY) = (0:0:0, 0:0:0);
( RDCLK *> DBITERR) = (0:0:0, 0:0:0);
( RDCLK *> DOUT) = (0:0:0, 0:0:0);
( RDCLK *> DOUTP) = (0:0:0, 0:0:0);
( RDCLK *> EMPTY) = (0:0:0, 0:0:0);
( RDCLK *> PROGEMPTY) = (0:0:0, 0:0:0);
( RDCLK *> RDCOUNT) = (0:0:0, 0:0:0);
( RDCLK *> RDERR) = (0:0:0, 0:0:0);
( RDCLK *> RDRSTBUSY) = (0:0:0, 0:0:0);
( RDCLK *> SBITERR) = (0:0:0, 0:0:0);
( RDCLK *> WRCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> CASDOUT) = (0:0:0, 0:0:0);
( WRCLK *> CASDOUTP) = (0:0:0, 0:0:0);
( WRCLK *> CASPRVRDEN) = (0:0:0, 0:0:0);
( WRCLK *> DOUT) = (0:0:0, 0:0:0);
( WRCLK *> DOUTP) = (0:0:0, 0:0:0);
( WRCLK *> ECCPARITY) = (0:0:0, 0:0:0);
( WRCLK *> FULL) = (0:0:0, 0:0:0);
( WRCLK *> PROGFULL) = (0:0:0, 0:0:0);
( WRCLK *> RDCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> RDRSTBUSY) = (0:0:0, 0:0:0);
( WRCLK *> WRCOUNT) = (0:0:0, 0:0:0);
( WRCLK *> WRERR) = (0:0:0, 0:0:0);
( WRCLK *> WRRSTBUSY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge RDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge RDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge RDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge RDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, RDCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, WRCLK_delay, WREN_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FRAME_ECCE2.v 0000664 0000000 0000000 00000044577 12327044266 0023136 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
/////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.71)
// \ \ Description :
// / /
// /__/ /\ Filename : FRAME_ECCE2.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 07/22/10 - Change Error to Message for input rbt file check (CR568991)
// 08/04/11 - Change FRAME_RBT_IN_FILENAME ot NONE (CR618399)
//////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE2 (
CRCERROR,
ECCERROR,
ECCERRORSINGLE,
FAR,
SYNBIT,
SYNDROME,
SYNDROMEVALID,
SYNWORD
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
parameter FARSRC = "EFAR";
parameter FRAME_RBT_IN_FILENAME = "NONE";
localparam FRAME_ECC_OUT_RBT_FILENAME = "frame_rbt_out_e2.txt";
localparam FRAME_ECC_OUT_ECC_FILENAME = "frame_ecc_out_e2.txt";
output CRCERROR;
output ECCERROR;
output ECCERRORSINGLE;
output SYNDROMEVALID;
output [12:0] SYNDROME;
output [25:0] FAR;
output [4:0] SYNBIT;
output [6:0] SYNWORD;
reg clk_osc = 0;
integer rbt_fd;
integer ecc_ecc_out_fd;
integer ecc_rbt_out_fd;
reg [31:0] rb_data = 32'b0;
reg [31:0] data_rbt;
reg [31:0] tmpwd1;
reg [31:0] tmpwd2;
reg sim_file_flag = 0;
reg [31:0] frame_data_bak[255:174];
reg [31:0] frame_data[255:174];
integer frame_addr_i;
reg [31:0] frame_addr;
reg [31:0] rb_crc_rbt;
reg [31:0] crc_curr = 32'b0;
reg [31:0] crc_new = 32'b0;
reg [36:0] crc_input = 32'b0;
reg rbcrc_err = 0;
reg rd_rbt_hold = 0;
reg rd_rbt_hold1 = 0;
reg rd_rbt_hold2 = 0;
reg [6:0] ecc_wadr;
reg [4:0] ecc_badr;
reg [31:0] corr_wd;
reg [31:0] corr_wd1;
reg rb_data_en = 0;
reg end_rbt = 0;
reg rd_rbt_en = 0;
reg hamming_rst = 0;
integer i = 0;
integer bi = 174;
integer nbi = 174;
integer n = 174;
reg ecc_run = 0;
reg calc_syndrome = 1;
wire [12:0] new_S;
wire [12:0] next_S;
reg [12:0] S = 13'd0;
reg S_valid = 0;
reg S_valid_ungated = 0;
reg [31:0] ecc_corr_mask = 32'b0;
reg ecc_error = 0;
reg ecc_error_single = 0;
reg ecc_error_ungated = 0;
reg [4:0] ecc_synbit = 5'b0;
reg [6:0] ecc_synword = 7'b0;
reg [4:0] ecc_synbit_next = 5'b0;
reg [6:0] ecc_synword_next = 7'b0;
reg efar_save = 0;
reg [11:5] hiaddr = 7'd46;
wire [11:5] hiaddrp1;
wire hiaddr63;
wire hiaddr127;
wire hclk;
wire xorall;
wire overall;
wire S_valid_next;
wire S_valid_ungated_next;
wire next_error;
wire [12:0] new_S_xor_S;
wire [6:0] ecc_synword_next_not_par;
reg [160:0] tmps1;
reg [160:0] tmps2;
reg [160:0] tmps3;
initial begin
case (FARSRC)
"EFAR" : ;
"FAR" : ;
default : begin
$display("Attribute Syntax Error : The Attribute FARSRC on FRAME_ECCE2 instance %m is set to %s. Legal values for this attribute are EFAR, or FAR.", FARSRC);
$finish;
end
endcase
sim_file_flag = 0;
if (FRAME_RBT_IN_FILENAME == "NONE")
$display(" Message: The configuration frame data file for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n");
else begin
rbt_fd = $fopen(FRAME_RBT_IN_FILENAME, "r");
ecc_ecc_out_fd = $fopen(FRAME_ECC_OUT_ECC_FILENAME, "w");
ecc_rbt_out_fd = $fopen(FRAME_ECC_OUT_RBT_FILENAME, "w");
if (rbt_fd == 0)
$display(" Message: The configuration frame data file %s for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n", FRAME_RBT_IN_FILENAME);
else
if ($fscanf(rbt_fd, "%s\t%s\t%s", tmps1, tmps2, tmps3) != -1)
rd_rbt_en <= #1 1;
if (ecc_ecc_out_fd == 0)
$display(" Error: The ecc frame data out file frame_ecc_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n");
if (ecc_rbt_out_fd == 0)
$display(" Error: The rbt frame data out file frame_rbt_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n");
if (rbt_fd !=0 && ecc_ecc_out_fd != 0 && ecc_rbt_out_fd != 0 )
sim_file_flag = 1;
end
end
assign CRCERROR = rbcrc_err;
assign ECCERROR = ecc_error;
assign ECCERRORSINGLE = ecc_error_single;
assign SYNDROMEVALID = S_valid;
assign SYNDROME = S;
assign FAR = frame_addr[25:0];
assign SYNBIT = ecc_synbit;
assign SYNWORD = ecc_synword;
always
#2000 clk_osc <= ~clk_osc;
always @(negedge clk_osc )
if (sim_file_flag == 1 && rd_rbt_en == 1 && rd_rbt_hold1 == 0 ) begin
if ( $fscanf(rbt_fd, "%d\t%b\t%b", frame_addr_i, data_rbt, rb_crc_rbt) != -1) begin
rb_data_en <= 1;
frame_addr <= frame_addr_i;
rb_data <= data_rbt;
crc_input[36:0] = {5'b00011, data_rbt};
crc_new[31:0] = bcc_next(crc_curr, crc_input);
crc_curr[31:0] <= crc_new;
if (n <= 255) begin
frame_data[n] <= data_rbt[31:0];
if (n == 255)
n <= 174;
else if (n==191)
n <= 193;
else
n <= n+ 1;
end
end
else begin
rb_data_en <= 0;
end_rbt <= 1;
n <= 173;
if ( crc_new != rb_crc_rbt)
rbcrc_err <= 1;
else
rbcrc_err <= 0;
$fclose(rbt_fd);
end
end
always @(negedge clk_osc)
if (rb_data_en == 1) begin
if ( rd_rbt_hold1 == 1 && rd_rbt_hold == 1 && rd_rbt_hold2 == 0) begin
for (bi = 174; bi<= 255; bi=bi+1)
frame_data_bak[bi] = frame_data[bi];
if (ecc_error_single == 1) begin
ecc_wadr[6:0] = SYNDROME[11:5];
ecc_badr[4:0] = SYNDROME[4:0];
corr_wd = frame_data[ecc_wadr];
corr_wd1 = frame_data[ecc_wadr];
corr_wd[ecc_badr] = ~corr_wd1[ecc_badr];
frame_data_bak[ecc_wadr] = corr_wd;
end
for (nbi = 174; nbi<= 255; nbi=nbi+1) begin
if (nbi != 192) begin
tmpwd1 = frame_data[nbi];
tmpwd2 = frame_data_bak[nbi];
$fwriteb(ecc_rbt_out_fd, tmpwd1);
$fwriteb(ecc_rbt_out_fd, "\n");
$fwriteb(ecc_ecc_out_fd, tmpwd2);
$fwriteb(ecc_ecc_out_fd, "\n");
end
end
end
end
else if (end_rbt ==1) begin
$fclose(ecc_ecc_out_fd);
$fclose(ecc_rbt_out_fd);
end
always @(posedge clk_osc)
if (rb_data_en == 1) begin
if (n == 255)
rd_rbt_hold <= 1;
rd_rbt_hold2 <= rd_rbt_hold1;
rd_rbt_hold1 <= rd_rbt_hold;
if (rd_rbt_hold2 ==1) begin
rd_rbt_hold <= 0;
rd_rbt_hold1 <= 0;
rd_rbt_hold2 <= 0;
end
end
else if ( end_rbt == 1) begin
rd_rbt_hold <= 1;
rd_rbt_hold1 <= 1;
rd_rbt_hold2 <= 1;
end
always @(negedge clk_osc)
if (rd_rbt_hold2 == 1 && hamming_rst == 0)
hamming_rst <= 1;
else
hamming_rst <= 0;
assign S_valid_next = rb_data_en & hiaddr127 & ~ecc_run;
assign S_valid_ungated_next = rb_data_en & hiaddr127;
assign next_error = (| next_S);
assign hiaddrp1 = hiaddr + 1;
assign hiaddr63 = & hiaddr[10:5];
assign hiaddr127 = & hiaddr[11:5];
assign hclk = ( hiaddr == 7'd87 ) ? 1 : 0;
always @( posedge clk_osc or posedge hamming_rst)
if (hamming_rst == 1)
hiaddr <= 7'd46;
else if ( rb_data_en == 1 ) begin
if ( hiaddr127 )
hiaddr <= 7'd46;
else
hiaddr <= { hiaddrp1[11:6], ( hiaddr63 | hiaddrp1[5] ) };
end
assign xorall = ( ^ rb_data[31:13] ) ^ ( ( ~ hclk ) & ( ^ rb_data[12:0] ) );
assign overall = ( ^ rb_data[31:13] ) ^ ( ~(hclk & calc_syndrome) & ( ^ rb_data[12:0] ) );
assign new_S[12] = overall;
assign new_S[4] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^
rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^
rb_data[19] ^ rb_data[18] ^ rb_data[17] ^ rb_data[16] ^
( hclk & ~calc_syndrome & rb_data[4] );
assign new_S[3] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^
rb_data[15] ^ rb_data[14] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[3] :
( rb_data[12] ^ rb_data[11] ^ rb_data[10] ^ rb_data[9] ^ rb_data[8]) );
assign new_S[2] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^
rb_data[15] ^ rb_data[14] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[2] :
( rb_data[12] ^ rb_data[7] ^ rb_data[6] ^ rb_data[5] ^ rb_data[4] ) );
assign new_S[1] = rb_data[31] ^ rb_data[30] ^ rb_data[27] ^ rb_data[26] ^
rb_data[23] ^ rb_data[22] ^ rb_data[19] ^ rb_data[18] ^
rb_data[15] ^ rb_data[14] ^
( hclk ? ~calc_syndrome & rb_data[1] :
( rb_data[11] ^ rb_data[10] ^ rb_data[7] ^ rb_data[6] ^ rb_data[3] ^ rb_data[2] ));
assign new_S[0] = rb_data[31] ^ rb_data[29] ^ rb_data[27] ^ rb_data[25] ^
rb_data[23] ^ rb_data[21] ^ rb_data[19] ^ rb_data[17] ^
rb_data[15] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[0] :
( rb_data[11] ^ rb_data[9] ^ rb_data[7] ^ rb_data[5] ^ rb_data[3] ^ rb_data[1] ) );
assign new_S[11:5] = ( hiaddr & { 7 { xorall } } ) ^
( { 7 { hclk & ~calc_syndrome } } &
{ rb_data[11], rb_data[10], rb_data[9], rb_data[8],
rb_data[7], rb_data[6], rb_data[5] } );
assign new_S_xor_S = S ^ new_S;
assign next_S = (hiaddr127 & calc_syndrome) ? {(^new_S_xor_S), new_S_xor_S[11:0]} :
(hiaddr == 7'd46) ? new_S : new_S_xor_S;
assign ecc_synword_next_not_par = new_S_xor_S[11:5] - 7'd46 - {6'b0, new_S_xor_S[11]};
always @(ecc_synword_next_not_par, new_S_xor_S) begin
if (!new_S_xor_S[12]) begin
ecc_synword_next = 7'd0;
ecc_synbit_next = 5'd0;
end else begin
case (new_S_xor_S[11:0])
12'h000 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd12;
end
12'h001 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd0;
end
12'h002 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd1;
end
12'h004 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd2;
end
12'h008 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd3;
end
12'h010 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd4;
end
12'h020 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd5;
end
12'h040 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd6;
end
12'h080 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd7;
end
12'h100 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd8;
end
12'h200 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd9;
end
12'h400 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd10;
end
12'h800 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd11;
end
default : begin
ecc_synword_next = ecc_synword_next_not_par;
ecc_synbit_next = new_S_xor_S[4:0];
end
endcase
end
end
always @( posedge clk_osc or posedge hamming_rst) begin
if ( hamming_rst == 1 ) begin
S_valid <= 0;
S_valid_ungated <= 0;
S <= 13'd0;
end
else if ( rb_data_en == 1 ) begin
S_valid_ungated <= S_valid_ungated_next;
S_valid <= S_valid_next;
S <= next_S;
end else begin
S_valid_ungated <= 0;
S_valid <= 0;
end
if (hamming_rst == 1 ) begin
ecc_synword <= 7'd0;
ecc_synbit <= 5'd0;
end
else if ( S_valid_next & ~efar_save ) begin
ecc_synword <= ecc_synword_next;
ecc_synbit <= ecc_synbit_next;
end
if (hamming_rst == 1) begin
ecc_error <= 0;
ecc_error_single <= 0;
end
else if (S_valid_next == 1) begin
ecc_error <= next_error;
ecc_error_single <= next_S[12];
end
if (hamming_rst == 1)
ecc_error_ungated <= 0;
else if (S_valid_ungated_next == 1)
ecc_error_ungated <= next_error;
if (hamming_rst == 1)
efar_save <= 0;
else if (ecc_error == 1 | ((S_valid_ungated_next & next_error) == 1))
efar_save <= 1;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/FRAME_ECCE3.v 0000664 0000000 0000000 00000002357 12327044266 0023125 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : FRAME_ECCE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/30/13 - Initial version.
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE3
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output CRCERROR,
output ECCERRORNOTSINGLE,
output ECCERRORSINGLE,
output ENDOFFRAME,
output ENDOFSCAN,
output [25:0] FAR,
input [1:0] FARSEL,
input ICAPBOTCLK,
input ICAPTOPCLK
);
tri0 glblGSR = glbl.GSR;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GND.v 0000664 0000000 0000000 00000001701 12327044266 0022031 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/GND.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / GND Connection
// /___/ /\ Filename : GND.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:19 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module GND(G);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output G;
assign G = 1'b0;
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTHE2_CHANNEL.v 0000664 0000000 0000000 00000556564 12327044266 0023410 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTHE2_CHANNEL.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// Initial version
// 09/22/11 - 624065 - YML update
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 11/08/12 - 686590 - YML default attribute changes
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE2_CHANNEL (
CPLLFBCLKLOST,
CPLLLOCK,
CPLLREFCLKLOST,
DMONITOROUT,
DRPDO,
DRPRDY,
EYESCANDATAERROR,
GTHTXN,
GTHTXP,
GTREFCLKMONITOR,
PCSRSVDOUT,
PHYSTATUS,
RSOSINTDONE,
RXBUFSTATUS,
RXBYTEISALIGNED,
RXBYTEREALIGN,
RXCDRLOCK,
RXCHANBONDSEQ,
RXCHANISALIGNED,
RXCHANREALIGN,
RXCHARISCOMMA,
RXCHARISK,
RXCHBONDO,
RXCLKCORCNT,
RXCOMINITDET,
RXCOMMADET,
RXCOMSASDET,
RXCOMWAKEDET,
RXDATA,
RXDATAVALID,
RXDFESLIDETAPSTARTED,
RXDFESLIDETAPSTROBEDONE,
RXDFESLIDETAPSTROBESTARTED,
RXDFESTADAPTDONE,
RXDISPERR,
RXDLYSRESETDONE,
RXELECIDLE,
RXHEADER,
RXHEADERVALID,
RXMONITOROUT,
RXNOTINTABLE,
RXOSINTSTARTED,
RXOSINTSTROBEDONE,
RXOSINTSTROBESTARTED,
RXOUTCLK,
RXOUTCLKFABRIC,
RXOUTCLKPCS,
RXPHALIGNDONE,
RXPHMONITOR,
RXPHSLIPMONITOR,
RXPMARESETDONE,
RXPRBSERR,
RXQPISENN,
RXQPISENP,
RXRATEDONE,
RXRESETDONE,
RXSTARTOFSEQ,
RXSTATUS,
RXSYNCDONE,
RXSYNCOUT,
RXVALID,
TXBUFSTATUS,
TXCOMFINISH,
TXDLYSRESETDONE,
TXGEARBOXREADY,
TXOUTCLK,
TXOUTCLKFABRIC,
TXOUTCLKPCS,
TXPHALIGNDONE,
TXPHINITDONE,
TXPMARESETDONE,
TXQPISENN,
TXQPISENP,
TXRATEDONE,
TXRESETDONE,
TXSYNCDONE,
TXSYNCOUT,
CFGRESET,
CLKRSVD0,
CLKRSVD1,
CPLLLOCKDETCLK,
CPLLLOCKEN,
CPLLPD,
CPLLREFCLKSEL,
CPLLRESET,
DMONFIFORESET,
DMONITORCLK,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
EYESCANMODE,
EYESCANRESET,
EYESCANTRIGGER,
GTGREFCLK,
GTHRXN,
GTHRXP,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTRESETSEL,
GTRSVD,
GTRXRESET,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
GTTXRESET,
LOOPBACK,
PCSRSVDIN,
PCSRSVDIN2,
PMARSVDIN,
QPLLCLK,
QPLLREFCLK,
RESETOVRD,
RX8B10BEN,
RXADAPTSELTEST,
RXBUFRESET,
RXCDRFREQRESET,
RXCDRHOLD,
RXCDROVRDEN,
RXCDRRESET,
RXCDRRESETRSV,
RXCHBONDEN,
RXCHBONDI,
RXCHBONDLEVEL,
RXCHBONDMASTER,
RXCHBONDSLAVE,
RXCOMMADETEN,
RXDDIEN,
RXDFEAGCHOLD,
RXDFEAGCOVRDEN,
RXDFEAGCTRL,
RXDFECM1EN,
RXDFELFHOLD,
RXDFELFOVRDEN,
RXDFELPMRESET,
RXDFESLIDETAP,
RXDFESLIDETAPADAPTEN,
RXDFESLIDETAPHOLD,
RXDFESLIDETAPID,
RXDFESLIDETAPINITOVRDEN,
RXDFESLIDETAPONLYADAPTEN,
RXDFESLIDETAPOVRDEN,
RXDFESLIDETAPSTROBE,
RXDFETAP2HOLD,
RXDFETAP2OVRDEN,
RXDFETAP3HOLD,
RXDFETAP3OVRDEN,
RXDFETAP4HOLD,
RXDFETAP4OVRDEN,
RXDFETAP5HOLD,
RXDFETAP5OVRDEN,
RXDFETAP6HOLD,
RXDFETAP6OVRDEN,
RXDFETAP7HOLD,
RXDFETAP7OVRDEN,
RXDFEUTHOLD,
RXDFEUTOVRDEN,
RXDFEVPHOLD,
RXDFEVPOVRDEN,
RXDFEVSEN,
RXDFEXYDEN,
RXDLYBYPASS,
RXDLYEN,
RXDLYOVRDEN,
RXDLYSRESET,
RXELECIDLEMODE,
RXGEARBOXSLIP,
RXLPMEN,
RXLPMHFHOLD,
RXLPMHFOVRDEN,
RXLPMLFHOLD,
RXLPMLFKLOVRDEN,
RXMCOMMAALIGNEN,
RXMONITORSEL,
RXOOBRESET,
RXOSCALRESET,
RXOSHOLD,
RXOSINTCFG,
RXOSINTEN,
RXOSINTHOLD,
RXOSINTID0,
RXOSINTNTRLEN,
RXOSINTOVRDEN,
RXOSINTSTROBE,
RXOSINTTESTOVRDEN,
RXOSOVRDEN,
RXOUTCLKSEL,
RXPCOMMAALIGNEN,
RXPCSRESET,
RXPD,
RXPHALIGN,
RXPHALIGNEN,
RXPHDLYPD,
RXPHDLYRESET,
RXPHOVRDEN,
RXPMARESET,
RXPOLARITY,
RXPRBSCNTRESET,
RXPRBSSEL,
RXQPIEN,
RXRATE,
RXRATEMODE,
RXSLIDE,
RXSYNCALLIN,
RXSYNCIN,
RXSYNCMODE,
RXSYSCLKSEL,
RXUSERRDY,
RXUSRCLK,
RXUSRCLK2,
SETERRSTATUS,
SIGVALIDCLK,
TSTIN,
TX8B10BBYPASS,
TX8B10BEN,
TXBUFDIFFCTRL,
TXCHARDISPMODE,
TXCHARDISPVAL,
TXCHARISK,
TXCOMINIT,
TXCOMSAS,
TXCOMWAKE,
TXDATA,
TXDEEMPH,
TXDETECTRX,
TXDIFFCTRL,
TXDIFFPD,
TXDLYBYPASS,
TXDLYEN,
TXDLYHOLD,
TXDLYOVRDEN,
TXDLYSRESET,
TXDLYUPDOWN,
TXELECIDLE,
TXHEADER,
TXINHIBIT,
TXMAINCURSOR,
TXMARGIN,
TXOUTCLKSEL,
TXPCSRESET,
TXPD,
TXPDELECIDLEMODE,
TXPHALIGN,
TXPHALIGNEN,
TXPHDLYPD,
TXPHDLYRESET,
TXPHDLYTSTCLK,
TXPHINIT,
TXPHOVRDEN,
TXPIPPMEN,
TXPIPPMOVRDEN,
TXPIPPMPD,
TXPIPPMSEL,
TXPIPPMSTEPSIZE,
TXPISOPD,
TXPMARESET,
TXPOLARITY,
TXPOSTCURSOR,
TXPOSTCURSORINV,
TXPRBSFORCEERR,
TXPRBSSEL,
TXPRECURSOR,
TXPRECURSORINV,
TXQPIBIASEN,
TXQPISTRONGPDOWN,
TXQPIWEAKPUP,
TXRATE,
TXRATEMODE,
TXSEQUENCE,
TXSTARTSEQ,
TXSWING,
TXSYNCALLIN,
TXSYNCIN,
TXSYNCMODE,
TXSYSCLKSEL,
TXUSERRDY,
TXUSRCLK,
TXUSRCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'h00C10;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter integer ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter [0:0] A_RXOSCALRESET = 1'b0;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [41:0] CFOK_CFG = 42'h24800040E80;
parameter [5:0] CFOK_CFG2 = 6'b100000;
parameter [5:0] CFOK_CFG3 = 6'b100000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter integer CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 20;
parameter integer CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter integer CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter [28:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
parameter integer CPLL_REFCLK_DIV = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "TRUE";
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000;
parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [14:0] PMA_RSV4 = 15'b000000000001000;
parameter [3:0] PMA_RSV5 = 4'b0000;
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter integer RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter integer RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
parameter [15:0] RXDLY_CFG = 16'h001F;
parameter [8:0] RXDLY_LCFG = 9'h030;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000;
parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084020;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] RXPI_CFG0 = 2'b00;
parameter [1:0] RXPI_CFG1 = 2'b00;
parameter [1:0] RXPI_CFG2 = 2'b00;
parameter [1:0] RXPI_CFG3 = 2'b00;
parameter [0:0] RXPI_CFG4 = 1'b0;
parameter [0:0] RXPI_CFG5 = 1'b0;
parameter [2:0] RXPI_CFG6 = 3'b100;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter integer RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_PD = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110;
parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010;
parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000;
parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1;
parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0;
parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000;
parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000;
parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000;
parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000;
parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000;
parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000;
parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000;
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01;
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010;
parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010;
parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1;
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10;
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010;
parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1;
parameter [15:0] RX_DFE_LPM_CFG = 16'h0080;
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F;
parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000;
parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011;
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter integer RX_INT_DATAWIDTH = 0;
parameter [12:0] RX_OS_CFG = 13'b0000010000000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter integer SAS_MAX_COM = 64;
parameter integer SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter integer SATA_MAX_BURST = 8;
parameter integer SATA_MAX_INIT = 21;
parameter integer SATA_MAX_WAKE = 7;
parameter integer SATA_MIN_BURST = 4;
parameter integer SATA_MIN_INIT = 12;
parameter integer SATA_MIN_WAKE = 4;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.1";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h001F;
parameter [8:0] TXDLY_LCFG = 9'h030;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084020;
parameter [15:0] TXPH_CFG = 16'h0780;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b100;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_PD = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter integer TX_INT_DATAWIDTH = 0;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CPLLFBCLKLOST;
output CPLLLOCK;
output CPLLREFCLKLOST;
output DRPRDY;
output EYESCANDATAERROR;
output GTHTXN;
output GTHTXP;
output GTREFCLKMONITOR;
output PHYSTATUS;
output RSOSINTDONE;
output RXBYTEISALIGNED;
output RXBYTEREALIGN;
output RXCDRLOCK;
output RXCHANBONDSEQ;
output RXCHANISALIGNED;
output RXCHANREALIGN;
output RXCOMINITDET;
output RXCOMMADET;
output RXCOMSASDET;
output RXCOMWAKEDET;
output RXDFESLIDETAPSTARTED;
output RXDFESLIDETAPSTROBEDONE;
output RXDFESLIDETAPSTROBESTARTED;
output RXDFESTADAPTDONE;
output RXDLYSRESETDONE;
output RXELECIDLE;
output RXOSINTSTARTED;
output RXOSINTSTROBEDONE;
output RXOSINTSTROBESTARTED;
output RXOUTCLK;
output RXOUTCLKFABRIC;
output RXOUTCLKPCS;
output RXPHALIGNDONE;
output RXPMARESETDONE;
output RXPRBSERR;
output RXQPISENN;
output RXQPISENP;
output RXRATEDONE;
output RXRESETDONE;
output RXSYNCDONE;
output RXSYNCOUT;
output RXVALID;
output TXCOMFINISH;
output TXDLYSRESETDONE;
output TXGEARBOXREADY;
output TXOUTCLK;
output TXOUTCLKFABRIC;
output TXOUTCLKPCS;
output TXPHALIGNDONE;
output TXPHINITDONE;
output TXPMARESETDONE;
output TXQPISENN;
output TXQPISENP;
output TXRATEDONE;
output TXRESETDONE;
output TXSYNCDONE;
output TXSYNCOUT;
output [14:0] DMONITOROUT;
output [15:0] DRPDO;
output [15:0] PCSRSVDOUT;
output [1:0] RXCLKCORCNT;
output [1:0] RXDATAVALID;
output [1:0] RXHEADERVALID;
output [1:0] RXSTARTOFSEQ;
output [1:0] TXBUFSTATUS;
output [2:0] RXBUFSTATUS;
output [2:0] RXSTATUS;
output [4:0] RXCHBONDO;
output [4:0] RXPHMONITOR;
output [4:0] RXPHSLIPMONITOR;
output [5:0] RXHEADER;
output [63:0] RXDATA;
output [6:0] RXMONITOROUT;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [7:0] RXDISPERR;
output [7:0] RXNOTINTABLE;
input CFGRESET;
input CLKRSVD0;
input CLKRSVD1;
input CPLLLOCKDETCLK;
input CPLLLOCKEN;
input CPLLPD;
input CPLLRESET;
input DMONFIFORESET;
input DMONITORCLK;
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
input GTGREFCLK;
input GTHRXN;
input GTHRXP;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTRESETSEL;
input GTRXRESET;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input GTTXRESET;
input QPLLCLK;
input QPLLREFCLK;
input RESETOVRD;
input RX8B10BEN;
input RXBUFRESET;
input RXCDRFREQRESET;
input RXCDRHOLD;
input RXCDROVRDEN;
input RXCDRRESET;
input RXCDRRESETRSV;
input RXCHBONDEN;
input RXCHBONDMASTER;
input RXCHBONDSLAVE;
input RXCOMMADETEN;
input RXDDIEN;
input RXDFEAGCHOLD;
input RXDFEAGCOVRDEN;
input RXDFECM1EN;
input RXDFELFHOLD;
input RXDFELFOVRDEN;
input RXDFELPMRESET;
input RXDFESLIDETAPADAPTEN;
input RXDFESLIDETAPHOLD;
input RXDFESLIDETAPINITOVRDEN;
input RXDFESLIDETAPONLYADAPTEN;
input RXDFESLIDETAPOVRDEN;
input RXDFESLIDETAPSTROBE;
input RXDFETAP2HOLD;
input RXDFETAP2OVRDEN;
input RXDFETAP3HOLD;
input RXDFETAP3OVRDEN;
input RXDFETAP4HOLD;
input RXDFETAP4OVRDEN;
input RXDFETAP5HOLD;
input RXDFETAP5OVRDEN;
input RXDFETAP6HOLD;
input RXDFETAP6OVRDEN;
input RXDFETAP7HOLD;
input RXDFETAP7OVRDEN;
input RXDFEUTHOLD;
input RXDFEUTOVRDEN;
input RXDFEVPHOLD;
input RXDFEVPOVRDEN;
input RXDFEVSEN;
input RXDFEXYDEN;
input RXDLYBYPASS;
input RXDLYEN;
input RXDLYOVRDEN;
input RXDLYSRESET;
input RXGEARBOXSLIP;
input RXLPMEN;
input RXLPMHFHOLD;
input RXLPMHFOVRDEN;
input RXLPMLFHOLD;
input RXLPMLFKLOVRDEN;
input RXMCOMMAALIGNEN;
input RXOOBRESET;
input RXOSCALRESET;
input RXOSHOLD;
input RXOSINTEN;
input RXOSINTHOLD;
input RXOSINTNTRLEN;
input RXOSINTOVRDEN;
input RXOSINTSTROBE;
input RXOSINTTESTOVRDEN;
input RXOSOVRDEN;
input RXPCOMMAALIGNEN;
input RXPCSRESET;
input RXPHALIGN;
input RXPHALIGNEN;
input RXPHDLYPD;
input RXPHDLYRESET;
input RXPHOVRDEN;
input RXPMARESET;
input RXPOLARITY;
input RXPRBSCNTRESET;
input RXQPIEN;
input RXRATEMODE;
input RXSLIDE;
input RXSYNCALLIN;
input RXSYNCIN;
input RXSYNCMODE;
input RXUSERRDY;
input RXUSRCLK2;
input RXUSRCLK;
input SETERRSTATUS;
input SIGVALIDCLK;
input TX8B10BEN;
input TXCOMINIT;
input TXCOMSAS;
input TXCOMWAKE;
input TXDEEMPH;
input TXDETECTRX;
input TXDIFFPD;
input TXDLYBYPASS;
input TXDLYEN;
input TXDLYHOLD;
input TXDLYOVRDEN;
input TXDLYSRESET;
input TXDLYUPDOWN;
input TXELECIDLE;
input TXINHIBIT;
input TXPCSRESET;
input TXPDELECIDLEMODE;
input TXPHALIGN;
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
input TXPIPPMEN;
input TXPIPPMOVRDEN;
input TXPIPPMPD;
input TXPIPPMSEL;
input TXPISOPD;
input TXPMARESET;
input TXPOLARITY;
input TXPOSTCURSORINV;
input TXPRBSFORCEERR;
input TXPRECURSORINV;
input TXQPIBIASEN;
input TXQPISTRONGPDOWN;
input TXQPIWEAKPUP;
input TXRATEMODE;
input TXSTARTSEQ;
input TXSWING;
input TXSYNCALLIN;
input TXSYNCIN;
input TXSYNCMODE;
input TXUSERRDY;
input TXUSRCLK2;
input TXUSRCLK;
input [13:0] RXADAPTSELTEST;
input [15:0] DRPDI;
input [15:0] GTRSVD;
input [15:0] PCSRSVDIN;
input [19:0] TSTIN;
input [1:0] RXELECIDLEMODE;
input [1:0] RXMONITORSEL;
input [1:0] RXPD;
input [1:0] RXSYSCLKSEL;
input [1:0] TXPD;
input [1:0] TXSYSCLKSEL;
input [2:0] CPLLREFCLKSEL;
input [2:0] LOOPBACK;
input [2:0] RXCHBONDLEVEL;
input [2:0] RXOUTCLKSEL;
input [2:0] RXPRBSSEL;
input [2:0] RXRATE;
input [2:0] TXBUFDIFFCTRL;
input [2:0] TXHEADER;
input [2:0] TXMARGIN;
input [2:0] TXOUTCLKSEL;
input [2:0] TXPRBSSEL;
input [2:0] TXRATE;
input [3:0] RXOSINTCFG;
input [3:0] RXOSINTID0;
input [3:0] TXDIFFCTRL;
input [4:0] PCSRSVDIN2;
input [4:0] PMARSVDIN;
input [4:0] RXCHBONDI;
input [4:0] RXDFEAGCTRL;
input [4:0] RXDFESLIDETAP;
input [4:0] TXPIPPMSTEPSIZE;
input [4:0] TXPOSTCURSOR;
input [4:0] TXPRECURSOR;
input [5:0] RXDFESLIDETAPID;
input [63:0] TXDATA;
input [6:0] TXMAINCURSOR;
input [6:0] TXSEQUENCE;
input [7:0] TX8B10BBYPASS;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [8:0] DRPADDR;
reg SIM_RECEIVER_DETECT_PASS_BINARY;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] ACJTAG_DEBUG_MODE_BINARY;
reg [0:0] ACJTAG_MODE_BINARY;
reg [0:0] ACJTAG_RESET_BINARY;
reg [0:0] ALIGN_COMMA_DOUBLE_BINARY;
reg [0:0] ALIGN_MCOMMA_DET_BINARY;
reg [0:0] ALIGN_PCOMMA_DET_BINARY;
reg [0:0] A_RXOSCALRESET_BINARY;
reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY;
reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY;
reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY;
reg [0:0] CLK_CORRECT_USE_BINARY;
reg [0:0] CLK_COR_KEEP_IDLE_BINARY;
reg [0:0] CLK_COR_PRECEDENCE_BINARY;
reg [0:0] CLK_COR_SEQ_2_USE_BINARY;
reg [0:0] CPLL_FBDIV_45_BINARY;
reg [0:0] DEC_MCOMMA_DETECT_BINARY;
reg [0:0] DEC_PCOMMA_DETECT_BINARY;
reg [0:0] DEC_VALID_COMMA_ONLY_BINARY;
reg [0:0] ES_CLK_PHASE_SEL_BINARY;
reg [0:0] ES_ERRDET_EN_BINARY;
reg [0:0] ES_EYE_SCAN_EN_BINARY;
reg [0:0] FTS_LANE_DESKEW_EN_BINARY;
reg [0:0] LOOPBACK_CFG_BINARY;
reg [0:0] PCS_PCIE_EN_BINARY;
reg [0:0] RESET_POWERSAVE_DISABLE_BINARY;
reg [0:0] RXBUF_ADDR_MODE_BINARY;
reg [0:0] RXBUF_EN_BINARY;
reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY;
reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY;
reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY;
reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] RXBUF_THRESH_OVRD_BINARY;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY;
reg [0:0] RXGEARBOX_EN_BINARY;
reg [0:0] RXOOB_CLK_CFG_BINARY;
reg [0:0] RXPI_CFG4_BINARY;
reg [0:0] RXPI_CFG5_BINARY;
reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY;
reg [0:0] RXSYNC_MULTILANE_BINARY;
reg [0:0] RXSYNC_OVRD_BINARY;
reg [0:0] RXSYNC_SKIP_DA_BINARY;
reg [0:0] RX_CLKMUX_PD_BINARY;
reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY;
reg [0:0] RX_DFELPM_CFG1_BINARY;
reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_BINARY;
reg [0:0] RX_DFE_AGC_OVRDEN_BINARY;
reg [0:0] RX_DFE_KL_LPM_KH_OVRDEN_BINARY;
reg [0:0] RX_DFE_KL_LPM_KL_OVRDEN_BINARY;
reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY;
reg [0:0] RX_INT_DATAWIDTH_BINARY;
reg [0:0] RX_XCLK_SEL_BINARY;
reg [0:0] SHOW_REALIGN_COMMA_BINARY;
reg [0:0] TXBUF_EN_BINARY;
reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] TXGEARBOX_EN_BINARY;
reg [0:0] TXOOB_CFG_BINARY;
reg [0:0] TXPI_CFG3_BINARY;
reg [0:0] TXPI_CFG4_BINARY;
reg [0:0] TXPI_GREY_SEL_BINARY;
reg [0:0] TXPI_INVSTROBE_SEL_BINARY;
reg [0:0] TXPI_PPMCLK_SEL_BINARY;
reg [0:0] TXSYNC_MULTILANE_BINARY;
reg [0:0] TXSYNC_OVRD_BINARY;
reg [0:0] TXSYNC_SKIP_DA_BINARY;
reg [0:0] TX_CLKMUX_PD_BINARY;
reg [0:0] TX_INT_DATAWIDTH_BINARY;
reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY;
reg [0:0] TX_MAINCURSOR_SEL_BINARY;
reg [0:0] TX_QPI_STATUS_EN_BINARY;
reg [0:0] TX_XCLK_SEL_BINARY;
reg [0:0] UCODEER_CLR_BINARY;
reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY;
reg [10:0] RX_DFE_H4_CFG_BINARY;
reg [10:0] RX_DFE_H5_CFG_BINARY;
reg [10:0] RX_DFE_H6_CFG_BINARY;
reg [10:0] RX_DFE_H7_CFG_BINARY;
reg [11:0] RX_DFE_H2_CFG_BINARY;
reg [11:0] RX_DFE_H3_CFG_BINARY;
reg [12:0] RX_OS_CFG_BINARY;
reg [13:0] RXLPM_HF_CFG_BINARY;
reg [13:0] RX_DEBUG_CFG_BINARY;
reg [14:0] PMA_RSV4_BINARY;
reg [14:0] TERM_RCAL_CFG_BINARY;
reg [16:0] RX_DFE_UT_CFG_BINARY;
reg [16:0] RX_DFE_VP_CFG_BINARY;
reg [17:0] RXLPM_LF_CFG_BINARY;
reg [1:0] CHAN_BOND_SEQ_LEN_BINARY;
reg [1:0] CLK_COR_SEQ_LEN_BINARY;
reg [1:0] OUTREFCLK_SEL_INV_BINARY;
reg [1:0] PMA_RSV3_BINARY;
reg [1:0] RXPI_CFG0_BINARY;
reg [1:0] RXPI_CFG1_BINARY;
reg [1:0] RXPI_CFG2_BINARY;
reg [1:0] RXPI_CFG3_BINARY;
reg [1:0] RXSLIDE_MODE_BINARY;
reg [1:0] RX_CM_SEL_BINARY;
reg [1:0] RX_DFE_AGC_CFG0_BINARY;
reg [1:0] RX_DFE_KL_LPM_KH_CFG0_BINARY;
reg [1:0] RX_DFE_KL_LPM_KL_CFG0_BINARY;
reg [1:0] SATA_CPLL_CFG_BINARY;
reg [1:0] TXPI_CFG0_BINARY;
reg [1:0] TXPI_CFG1_BINARY;
reg [1:0] TXPI_CFG2_BINARY;
reg [23:0] RX_BIAS_CFG_BINARY;
reg [2:0] ALIGN_COMMA_WORD_BINARY;
reg [2:0] GEARBOX_MODE_BINARY;
reg [2:0] RXOUT_DIV_BINARY;
reg [2:0] RXPI_CFG6_BINARY;
reg [2:0] RX_DATA_WIDTH_BINARY;
reg [2:0] RX_DFE_AGC_CFG1_BINARY;
reg [2:0] RX_DFE_KL_LPM_KH_CFG1_BINARY;
reg [2:0] RX_DFE_KL_LPM_KL_CFG1_BINARY;
reg [2:0] SATA_BURST_VAL_BINARY;
reg [2:0] SATA_EIDLE_VAL_BINARY;
reg [2:0] SIM_CPLLREFCLK_SEL_BINARY;
reg [2:0] TERM_RCAL_OVRD_BINARY;
reg [2:0] TXOUT_DIV_BINARY;
reg [2:0] TXPI_CFG5_BINARY;
reg [2:0] TXPI_SYNFREQ_PPM_BINARY;
reg [2:0] TX_DATA_WIDTH_BINARY;
reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY;
reg [2:0] TX_RXDETECT_REF_BINARY;
reg [31:0] PMA_RSV2_BINARY;
reg [31:0] PMA_RSV_BINARY;
reg [32:0] RX_DFE_KL_CFG_BINARY;
reg [3:0] CHAN_BOND_MAX_SKEW_BINARY;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY;
reg [3:0] FTS_LANE_DESKEW_CFG_BINARY;
reg [3:0] PMA_RSV5_BINARY;
reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY;
reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY;
reg [3:0] RXSLIDE_AUTO_WAIT_BINARY;
reg [3:0] RX_CM_TRIM_BINARY;
reg [3:0] RX_DFELPM_CFG0_BINARY;
reg [3:0] RX_DFE_AGC_CFG2_BINARY;
reg [3:0] RX_DFE_KL_LPM_KH_CFG2_BINARY;
reg [3:0] RX_DFE_KL_LPM_KL_CFG2_BINARY;
reg [3:0] SATA_BURST_SEQ_LEN_BINARY;
reg [4:0] CLK_COR_REPEAT_WAIT_BINARY;
reg [4:0] CPLL_REFCLK_DIV_BINARY;
reg [4:0] ES_PRESCALE_BINARY;
reg [4:0] RXBUFRESET_TIME_BINARY;
reg [4:0] RXCDRFREQRESET_TIME_BINARY;
reg [4:0] RXCDRPHRESET_TIME_BINARY;
reg [4:0] RXISCANRESET_TIME_BINARY;
reg [4:0] RXOSCALRESET_TIMEOUT_BINARY;
reg [4:0] RXOSCALRESET_TIME_BINARY;
reg [4:0] RXPCSRESET_TIME_BINARY;
reg [4:0] RXPH_MONITOR_SEL_BINARY;
reg [4:0] RXPMARESET_TIME_BINARY;
reg [4:0] RX_CLK25_DIV_BINARY;
reg [4:0] RX_SIG_VALID_DLY_BINARY;
reg [4:0] TXPCSRESET_TIME_BINARY;
reg [4:0] TXPH_MONITOR_SEL_BINARY;
reg [4:0] TXPMARESET_TIME_BINARY;
reg [4:0] TX_CLK25_DIV_BINARY;
reg [4:0] TX_DRIVE_MODE_BINARY;
reg [5:0] CFOK_CFG2_BINARY;
reg [5:0] CFOK_CFG3_BINARY;
reg [5:0] CLK_COR_MAX_LAT_BINARY;
reg [5:0] CLK_COR_MIN_LAT_BINARY;
reg [5:0] ES_CONTROL_BINARY;
reg [5:0] RXBUF_THRESH_OVFLW_BINARY;
reg [5:0] RXBUF_THRESH_UNDFLW_BINARY;
reg [5:0] RXCDR_LOCK_CFG_BINARY;
reg [5:0] RX_BUFFER_CFG_BINARY;
reg [5:0] RX_DDI_SEL_BINARY;
reg [5:0] SAS_MIN_COM_BINARY;
reg [5:0] SATA_MAX_BURST_BINARY;
reg [5:0] SATA_MAX_INIT_BINARY;
reg [5:0] SATA_MAX_WAKE_BINARY;
reg [5:0] SATA_MIN_BURST_BINARY;
reg [5:0] SATA_MIN_INIT_BINARY;
reg [5:0] SATA_MIN_WAKE_BINARY;
reg [5:0] TX_DEEMPH0_BINARY;
reg [5:0] TX_DEEMPH1_BINARY;
reg [6:0] CPLL_FBDIV_BINARY;
reg [6:0] RXDFELPMRESET_TIME_BINARY;
reg [6:0] RXOOB_CFG_BINARY;
reg [6:0] SAS_MAX_COM_BINARY;
reg [6:0] TX_MARGIN_FULL_0_BINARY;
reg [6:0] TX_MARGIN_FULL_1_BINARY;
reg [6:0] TX_MARGIN_FULL_2_BINARY;
reg [6:0] TX_MARGIN_FULL_3_BINARY;
reg [6:0] TX_MARGIN_FULL_4_BINARY;
reg [6:0] TX_MARGIN_LOW_0_BINARY;
reg [6:0] TX_MARGIN_LOW_1_BINARY;
reg [6:0] TX_MARGIN_LOW_2_BINARY;
reg [6:0] TX_MARGIN_LOW_3_BINARY;
reg [6:0] TX_MARGIN_LOW_4_BINARY;
reg [7:0] TXPI_PPM_CFG_BINARY;
reg [8:0] ES_VERT_OFFSET_BINARY;
reg [9:0] ALIGN_COMMA_ENABLE_BINARY;
reg [9:0] ALIGN_MCOMMA_VALUE_BINARY;
reg [9:0] ALIGN_PCOMMA_VALUE_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_4_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_4_BINARY;
reg [9:0] CLK_COR_SEQ_1_1_BINARY;
reg [9:0] CLK_COR_SEQ_1_2_BINARY;
reg [9:0] CLK_COR_SEQ_1_3_BINARY;
reg [9:0] CLK_COR_SEQ_1_4_BINARY;
reg [9:0] CLK_COR_SEQ_2_1_BINARY;
reg [9:0] CLK_COR_SEQ_2_2_BINARY;
reg [9:0] CLK_COR_SEQ_2_3_BINARY;
reg [9:0] CLK_COR_SEQ_2_4_BINARY;
reg [9:0] ES_PMA_CFG_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (ALIGN_COMMA_DOUBLE)
"FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0;
"TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE);
$finish;
end
endcase
case (ALIGN_COMMA_WORD)
1 : ALIGN_COMMA_WORD_BINARY = 3'b001;
2 : ALIGN_COMMA_WORD_BINARY = 3'b010;
4 : ALIGN_COMMA_WORD_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", ALIGN_COMMA_WORD, 1);
$finish;
end
endcase
case (ALIGN_MCOMMA_DET)
"TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET);
$finish;
end
endcase
case (ALIGN_PCOMMA_DET)
"TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET);
$finish;
end
endcase
case (CBCC_DATA_SOURCE_SEL)
"DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1;
"ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL);
$finish;
end
endcase
case (CHAN_BOND_KEEP_ALIGN)
"FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0;
"TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN);
$finish;
end
endcase
case (CHAN_BOND_SEQ_2_USE)
"FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE);
$finish;
end
endcase
case (CHAN_BOND_SEQ_LEN)
1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00;
2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01;
3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10;
4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1);
$finish;
end
endcase
case (CLK_CORRECT_USE)
"TRUE" : CLK_CORRECT_USE_BINARY = 1'b1;
"FALSE" : CLK_CORRECT_USE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE);
$finish;
end
endcase
case (CLK_COR_KEEP_IDLE)
"FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0;
"TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE);
$finish;
end
endcase
case (CLK_COR_PRECEDENCE)
"TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1;
"FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE);
$finish;
end
endcase
case (CLK_COR_SEQ_2_USE)
"FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE);
$finish;
end
endcase
case (CLK_COR_SEQ_LEN)
1 : CLK_COR_SEQ_LEN_BINARY = 2'b00;
2 : CLK_COR_SEQ_LEN_BINARY = 2'b01;
3 : CLK_COR_SEQ_LEN_BINARY = 2'b10;
4 : CLK_COR_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1);
$finish;
end
endcase
case (CPLL_FBDIV)
4 : CPLL_FBDIV_BINARY = 7'b0000010;
1 : CPLL_FBDIV_BINARY = 7'b0010000;
2 : CPLL_FBDIV_BINARY = 7'b0000000;
3 : CPLL_FBDIV_BINARY = 7'b0000001;
5 : CPLL_FBDIV_BINARY = 7'b0000011;
6 : CPLL_FBDIV_BINARY = 7'b0000101;
8 : CPLL_FBDIV_BINARY = 7'b0000110;
10 : CPLL_FBDIV_BINARY = 7'b0000111;
12 : CPLL_FBDIV_BINARY = 7'b0001101;
16 : CPLL_FBDIV_BINARY = 7'b0001110;
20 : CPLL_FBDIV_BINARY = 7'b0001111;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_FBDIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_FBDIV, 4);
$finish;
end
endcase
case (CPLL_FBDIV_45)
5 : CPLL_FBDIV_45_BINARY = 1'b1;
4 : CPLL_FBDIV_45_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_FBDIV_45 on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 4 to 5.", CPLL_FBDIV_45, 5);
$finish;
end
endcase
case (CPLL_REFCLK_DIV)
1 : CPLL_REFCLK_DIV_BINARY = 5'b10000;
2 : CPLL_REFCLK_DIV_BINARY = 5'b00000;
3 : CPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : CPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : CPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : CPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : CPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : CPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : CPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : CPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : CPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_REFCLK_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_REFCLK_DIV, 1);
$finish;
end
endcase
case (DEC_MCOMMA_DETECT)
"TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT);
$finish;
end
endcase
case (DEC_PCOMMA_DETECT)
"TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT);
$finish;
end
endcase
case (DEC_VALID_COMMA_ONLY)
"TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1;
"FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY);
$finish;
end
endcase
case (ES_ERRDET_EN)
"FALSE" : ES_ERRDET_EN_BINARY = 1'b0;
"TRUE" : ES_ERRDET_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN);
$finish;
end
endcase
case (ES_EYE_SCAN_EN)
"TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1;
"FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ES_EYE_SCAN_EN);
$finish;
end
endcase
case (FTS_LANE_DESKEW_EN)
"FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0;
"TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN);
$finish;
end
endcase
case (PCS_PCIE_EN)
"FALSE" : PCS_PCIE_EN_BINARY = 1'b0;
"TRUE" : PCS_PCIE_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN);
$finish;
end
endcase
case (RXBUF_ADDR_MODE)
"FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0;
"FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE);
$finish;
end
endcase
case (RXBUF_EN)
"TRUE" : RXBUF_EN_BINARY = 1'b1;
"FALSE" : RXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN);
$finish;
end
endcase
case (RXBUF_RESET_ON_CB_CHANGE)
"TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE);
$finish;
end
endcase
case (RXBUF_RESET_ON_COMMAALIGN)
"FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN);
$finish;
end
endcase
case (RXBUF_RESET_ON_EIDLE)
"FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE);
$finish;
end
endcase
case (RXBUF_RESET_ON_RATE_CHANGE)
"TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (RXBUF_THRESH_OVRD)
"FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0;
"TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD);
$finish;
end
endcase
case (RXGEARBOX_EN)
"FALSE" : RXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : RXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN);
$finish;
end
endcase
case (RXOOB_CLK_CFG)
"PMA" : RXOOB_CLK_CFG_BINARY = 1'b0;
"FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG);
$finish;
end
endcase
case (RXOUT_DIV)
2 : RXOUT_DIV_BINARY = 3'b001;
1 : RXOUT_DIV_BINARY = 3'b000;
4 : RXOUT_DIV_BINARY = 3'b010;
8 : RXOUT_DIV_BINARY = 3'b011;
16 : RXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute RXOUT_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2);
$finish;
end
endcase
case (RXSLIDE_MODE)
"OFF" : RXSLIDE_MODE_BINARY = 2'b00;
"AUTO" : RXSLIDE_MODE_BINARY = 2'b01;
"PCS" : RXSLIDE_MODE_BINARY = 2'b10;
"PMA" : RXSLIDE_MODE_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE);
$finish;
end
endcase
case (RX_CLK25_DIV)
7 : RX_CLK25_DIV_BINARY = 5'b00110;
1 : RX_CLK25_DIV_BINARY = 5'b00000;
2 : RX_CLK25_DIV_BINARY = 5'b00001;
3 : RX_CLK25_DIV_BINARY = 5'b00010;
4 : RX_CLK25_DIV_BINARY = 5'b00011;
5 : RX_CLK25_DIV_BINARY = 5'b00100;
6 : RX_CLK25_DIV_BINARY = 5'b00101;
8 : RX_CLK25_DIV_BINARY = 5'b00111;
9 : RX_CLK25_DIV_BINARY = 5'b01000;
10 : RX_CLK25_DIV_BINARY = 5'b01001;
11 : RX_CLK25_DIV_BINARY = 5'b01010;
12 : RX_CLK25_DIV_BINARY = 5'b01011;
13 : RX_CLK25_DIV_BINARY = 5'b01100;
14 : RX_CLK25_DIV_BINARY = 5'b01101;
15 : RX_CLK25_DIV_BINARY = 5'b01110;
16 : RX_CLK25_DIV_BINARY = 5'b01111;
17 : RX_CLK25_DIV_BINARY = 5'b10000;
18 : RX_CLK25_DIV_BINARY = 5'b10001;
19 : RX_CLK25_DIV_BINARY = 5'b10010;
20 : RX_CLK25_DIV_BINARY = 5'b10011;
21 : RX_CLK25_DIV_BINARY = 5'b10100;
22 : RX_CLK25_DIV_BINARY = 5'b10101;
23 : RX_CLK25_DIV_BINARY = 5'b10110;
24 : RX_CLK25_DIV_BINARY = 5'b10111;
25 : RX_CLK25_DIV_BINARY = 5'b11000;
26 : RX_CLK25_DIV_BINARY = 5'b11001;
27 : RX_CLK25_DIV_BINARY = 5'b11010;
28 : RX_CLK25_DIV_BINARY = 5'b11011;
29 : RX_CLK25_DIV_BINARY = 5'b11100;
30 : RX_CLK25_DIV_BINARY = 5'b11101;
31 : RX_CLK25_DIV_BINARY = 5'b11110;
32 : RX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7);
$finish;
end
endcase
case (RX_DATA_WIDTH)
20 : RX_DATA_WIDTH_BINARY = 3'b011;
16 : RX_DATA_WIDTH_BINARY = 3'b010;
32 : RX_DATA_WIDTH_BINARY = 3'b100;
40 : RX_DATA_WIDTH_BINARY = 3'b101;
64 : RX_DATA_WIDTH_BINARY = 3'b110;
80 : RX_DATA_WIDTH_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", RX_DATA_WIDTH, 20);
$finish;
end
endcase
case (RX_DEFER_RESET_BUF_EN)
"TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1;
"FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN);
$finish;
end
endcase
case (RX_DISPERR_SEQ_MATCH)
"TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1;
"FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH);
$finish;
end
endcase
case (RX_SIG_VALID_DLY)
10 : RX_SIG_VALID_DLY_BINARY = 5'b01001;
1 : RX_SIG_VALID_DLY_BINARY = 5'b00000;
2 : RX_SIG_VALID_DLY_BINARY = 5'b00001;
3 : RX_SIG_VALID_DLY_BINARY = 5'b00010;
4 : RX_SIG_VALID_DLY_BINARY = 5'b00011;
5 : RX_SIG_VALID_DLY_BINARY = 5'b00100;
6 : RX_SIG_VALID_DLY_BINARY = 5'b00101;
7 : RX_SIG_VALID_DLY_BINARY = 5'b00110;
8 : RX_SIG_VALID_DLY_BINARY = 5'b00111;
9 : RX_SIG_VALID_DLY_BINARY = 5'b01000;
11 : RX_SIG_VALID_DLY_BINARY = 5'b01010;
12 : RX_SIG_VALID_DLY_BINARY = 5'b01011;
13 : RX_SIG_VALID_DLY_BINARY = 5'b01100;
14 : RX_SIG_VALID_DLY_BINARY = 5'b01101;
15 : RX_SIG_VALID_DLY_BINARY = 5'b01110;
16 : RX_SIG_VALID_DLY_BINARY = 5'b01111;
17 : RX_SIG_VALID_DLY_BINARY = 5'b10000;
18 : RX_SIG_VALID_DLY_BINARY = 5'b10001;
19 : RX_SIG_VALID_DLY_BINARY = 5'b10010;
20 : RX_SIG_VALID_DLY_BINARY = 5'b10011;
21 : RX_SIG_VALID_DLY_BINARY = 5'b10100;
22 : RX_SIG_VALID_DLY_BINARY = 5'b10101;
23 : RX_SIG_VALID_DLY_BINARY = 5'b10110;
24 : RX_SIG_VALID_DLY_BINARY = 5'b10111;
25 : RX_SIG_VALID_DLY_BINARY = 5'b11000;
26 : RX_SIG_VALID_DLY_BINARY = 5'b11001;
27 : RX_SIG_VALID_DLY_BINARY = 5'b11010;
28 : RX_SIG_VALID_DLY_BINARY = 5'b11011;
29 : RX_SIG_VALID_DLY_BINARY = 5'b11100;
30 : RX_SIG_VALID_DLY_BINARY = 5'b11101;
31 : RX_SIG_VALID_DLY_BINARY = 5'b11110;
32 : RX_SIG_VALID_DLY_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10);
$finish;
end
endcase
case (RX_XCLK_SEL)
"RXREC" : RX_XCLK_SEL_BINARY = 1'b0;
"RXUSR" : RX_XCLK_SEL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL);
$finish;
end
endcase
case (SATA_CPLL_CFG)
"VCO_3000MHZ" : SATA_CPLL_CFG_BINARY = 2'b00;
"VCO_750MHZ" : SATA_CPLL_CFG_BINARY = 2'b10;
"VCO_1500MHZ" : SATA_CPLL_CFG_BINARY = 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute SATA_CPLL_CFG on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_CPLL_CFG);
$finish;
end
endcase
case (SHOW_REALIGN_COMMA)
"TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1;
"FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA);
$finish;
end
endcase
case (SIM_RECEIVER_DETECT_PASS)
"TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
"FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_TX_EIDLE_DRIVE_LEVEL)
"X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL);
$finish;
end
endcase
case (SIM_VERSION)
"1.1" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.1, 1.0, or 2.0.", SIM_VERSION);
$finish;
end
endcase
case (TXBUF_EN)
"TRUE" : TXBUF_EN_BINARY = 1'b1;
"FALSE" : TXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN);
$finish;
end
endcase
case (TXBUF_RESET_ON_RATE_CHANGE)
"FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
"TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (TXGEARBOX_EN)
"FALSE" : TXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : TXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN);
$finish;
end
endcase
case (TXOUT_DIV)
2 : TXOUT_DIV_BINARY = 3'b001;
1 : TXOUT_DIV_BINARY = 3'b000;
4 : TXOUT_DIV_BINARY = 3'b010;
8 : TXOUT_DIV_BINARY = 3'b011;
16 : TXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute TXOUT_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2);
$finish;
end
endcase
case (TXPI_PPMCLK_SEL)
"TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1;
"TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL);
$finish;
end
endcase
case (TX_CLK25_DIV)
7 : TX_CLK25_DIV_BINARY = 5'b00110;
1 : TX_CLK25_DIV_BINARY = 5'b00000;
2 : TX_CLK25_DIV_BINARY = 5'b00001;
3 : TX_CLK25_DIV_BINARY = 5'b00010;
4 : TX_CLK25_DIV_BINARY = 5'b00011;
5 : TX_CLK25_DIV_BINARY = 5'b00100;
6 : TX_CLK25_DIV_BINARY = 5'b00101;
8 : TX_CLK25_DIV_BINARY = 5'b00111;
9 : TX_CLK25_DIV_BINARY = 5'b01000;
10 : TX_CLK25_DIV_BINARY = 5'b01001;
11 : TX_CLK25_DIV_BINARY = 5'b01010;
12 : TX_CLK25_DIV_BINARY = 5'b01011;
13 : TX_CLK25_DIV_BINARY = 5'b01100;
14 : TX_CLK25_DIV_BINARY = 5'b01101;
15 : TX_CLK25_DIV_BINARY = 5'b01110;
16 : TX_CLK25_DIV_BINARY = 5'b01111;
17 : TX_CLK25_DIV_BINARY = 5'b10000;
18 : TX_CLK25_DIV_BINARY = 5'b10001;
19 : TX_CLK25_DIV_BINARY = 5'b10010;
20 : TX_CLK25_DIV_BINARY = 5'b10011;
21 : TX_CLK25_DIV_BINARY = 5'b10100;
22 : TX_CLK25_DIV_BINARY = 5'b10101;
23 : TX_CLK25_DIV_BINARY = 5'b10110;
24 : TX_CLK25_DIV_BINARY = 5'b10111;
25 : TX_CLK25_DIV_BINARY = 5'b11000;
26 : TX_CLK25_DIV_BINARY = 5'b11001;
27 : TX_CLK25_DIV_BINARY = 5'b11010;
28 : TX_CLK25_DIV_BINARY = 5'b11011;
29 : TX_CLK25_DIV_BINARY = 5'b11100;
30 : TX_CLK25_DIV_BINARY = 5'b11101;
31 : TX_CLK25_DIV_BINARY = 5'b11110;
32 : TX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7);
$finish;
end
endcase
case (TX_DATA_WIDTH)
20 : TX_DATA_WIDTH_BINARY = 3'b011;
16 : TX_DATA_WIDTH_BINARY = 3'b010;
32 : TX_DATA_WIDTH_BINARY = 3'b100;
40 : TX_DATA_WIDTH_BINARY = 3'b101;
64 : TX_DATA_WIDTH_BINARY = 3'b110;
80 : TX_DATA_WIDTH_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", TX_DATA_WIDTH, 20);
$finish;
end
endcase
case (TX_DRIVE_MODE)
"DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000;
"PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001;
"PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE);
$finish;
end
endcase
case (TX_LOOPBACK_DRIVE_HIZ)
"FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0;
"TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ);
$finish;
end
endcase
case (TX_XCLK_SEL)
"TXUSR" : TX_XCLK_SEL_BINARY = 1'b1;
"TXOUT" : TX_XCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL);
$finish;
end
endcase
if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1))
ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE);
$finish;
end
if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1))
ACJTAG_MODE_BINARY = ACJTAG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE);
$finish;
end
if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1))
ACJTAG_RESET_BINARY = ACJTAG_RESET;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_RESET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET);
$finish;
end
if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111))
ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE);
$finish;
end
if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111))
ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE);
$finish;
end
if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111))
ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE);
$finish;
end
if ((A_RXOSCALRESET >= 1'b0) && (A_RXOSCALRESET <= 1'b1))
A_RXOSCALRESET_BINARY = A_RXOSCALRESET;
else begin
$display("Attribute Syntax Error : The Attribute A_RXOSCALRESET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", A_RXOSCALRESET);
$finish;
end
if ((CFOK_CFG2 >= 6'b000000) && (CFOK_CFG2 <= 6'b111111))
CFOK_CFG2_BINARY = CFOK_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", CFOK_CFG2);
$finish;
end
if ((CFOK_CFG3 >= 6'b000000) && (CFOK_CFG3 <= 6'b111111))
CFOK_CFG3_BINARY = CFOK_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", CFOK_CFG3);
$finish;
end
if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14))
CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW);
$finish;
end
if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111))
CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1);
$finish;
end
if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111))
CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2);
$finish;
end
if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111))
CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3);
$finish;
end
if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111))
CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4);
$finish;
end
if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE);
$finish;
end
if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111))
CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1);
$finish;
end
if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111))
CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2);
$finish;
end
if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111))
CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3);
$finish;
end
if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111))
CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4);
$finish;
end
if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE);
$finish;
end
if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60))
CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT);
$finish;
end
if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60))
CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT);
$finish;
end
if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31))
CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT);
$finish;
end
if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111))
CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1);
$finish;
end
if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111))
CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2);
$finish;
end
if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111))
CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3);
$finish;
end
if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111))
CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4);
$finish;
end
if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111))
CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE);
$finish;
end
if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111))
CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1);
$finish;
end
if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111))
CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2);
$finish;
end
if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111))
CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3);
$finish;
end
if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111))
CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4);
$finish;
end
if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111))
CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE);
$finish;
end
if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1))
ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL);
$finish;
end
if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111))
ES_CONTROL_BINARY = ES_CONTROL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CONTROL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL);
$finish;
end
if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111))
ES_PMA_CFG_BINARY = ES_PMA_CFG;
else begin
$display("Attribute Syntax Error : The Attribute ES_PMA_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG);
$finish;
end
if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111))
ES_PRESCALE_BINARY = ES_PRESCALE;
else begin
$display("Attribute Syntax Error : The Attribute ES_PRESCALE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE);
$finish;
end
if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111))
ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET;
else begin
$display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET);
$finish;
end
if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111))
FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE);
$finish;
end
if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111))
FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG;
else begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG);
$finish;
end
if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111))
GEARBOX_MODE_BINARY = GEARBOX_MODE;
else begin
$display("Attribute Syntax Error : The Attribute GEARBOX_MODE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE);
$finish;
end
if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1))
LOOPBACK_CFG_BINARY = LOOPBACK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG);
$finish;
end
if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11))
OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV;
else begin
$display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV);
$finish;
end
if ((PMA_RSV >= 32'b00000000000000000000000000000000) && (PMA_RSV <= 32'b11111111111111111111111111111111))
PMA_RSV_BINARY = PMA_RSV;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 32'b00000000000000000000000000000000 to 32'b11111111111111111111111111111111.", PMA_RSV);
$finish;
end
if ((PMA_RSV2 >= 32'b00000000000000000000000000000000) && (PMA_RSV2 <= 32'b11111111111111111111111111111111))
PMA_RSV2_BINARY = PMA_RSV2;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 32'b00000000000000000000000000000000 to 32'b11111111111111111111111111111111.", PMA_RSV2);
$finish;
end
if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11))
PMA_RSV3_BINARY = PMA_RSV3;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3);
$finish;
end
if ((PMA_RSV4 >= 15'b000000000000000) && (PMA_RSV4 <= 15'b111111111111111))
PMA_RSV4_BINARY = PMA_RSV4;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", PMA_RSV4);
$finish;
end
if ((PMA_RSV5 >= 4'b0000) && (PMA_RSV5 <= 4'b1111))
PMA_RSV5_BINARY = PMA_RSV5;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV5);
$finish;
end
if ((RESET_POWERSAVE_DISABLE >= 1'b0) && (RESET_POWERSAVE_DISABLE <= 1'b1))
RESET_POWERSAVE_DISABLE_BINARY = RESET_POWERSAVE_DISABLE;
else begin
$display("Attribute Syntax Error : The Attribute RESET_POWERSAVE_DISABLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RESET_POWERSAVE_DISABLE);
$finish;
end
if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111))
RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME);
$finish;
end
if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111))
RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT);
$finish;
end
if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111))
RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT);
$finish;
end
if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63))
RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW);
$finish;
end
if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63))
RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW);
$finish;
end
if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111))
RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME);
$finish;
end
if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111))
RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME);
$finish;
end
if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1))
RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE);
$finish;
end
if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1))
RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE);
$finish;
end
if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111))
RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG);
$finish;
end
if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1))
RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE);
$finish;
end
if ((RXDFELPMRESET_TIME >= 7'b0000000) && (RXDFELPMRESET_TIME <= 7'b1111111))
RXDFELPMRESET_TIME_BINARY = RXDFELPMRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXDFELPMRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXDFELPMRESET_TIME);
$finish;
end
if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111))
RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME);
$finish;
end
if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111))
RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG);
$finish;
end
if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111))
RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG);
$finish;
end
if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111))
RXOOB_CFG_BINARY = RXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXOOB_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG);
$finish;
end
if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111))
RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME);
$finish;
end
if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111))
RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT);
$finish;
end
if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111))
RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME);
$finish;
end
if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111))
RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL);
$finish;
end
if ((RXPI_CFG0 >= 2'b00) && (RXPI_CFG0 <= 2'b11))
RXPI_CFG0_BINARY = RXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG0);
$finish;
end
if ((RXPI_CFG1 >= 2'b00) && (RXPI_CFG1 <= 2'b11))
RXPI_CFG1_BINARY = RXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG1);
$finish;
end
if ((RXPI_CFG2 >= 2'b00) && (RXPI_CFG2 <= 2'b11))
RXPI_CFG2_BINARY = RXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG2);
$finish;
end
if ((RXPI_CFG3 >= 2'b00) && (RXPI_CFG3 <= 2'b11))
RXPI_CFG3_BINARY = RXPI_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RXPI_CFG3);
$finish;
end
if ((RXPI_CFG4 >= 1'b0) && (RXPI_CFG4 <= 1'b1))
RXPI_CFG4_BINARY = RXPI_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG4);
$finish;
end
if ((RXPI_CFG5 >= 1'b0) && (RXPI_CFG5 <= 1'b1))
RXPI_CFG5_BINARY = RXPI_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG5);
$finish;
end
if ((RXPI_CFG6 >= 3'b000) && (RXPI_CFG6 <= 3'b111))
RXPI_CFG6_BINARY = RXPI_CFG6;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG6 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG6);
$finish;
end
if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111))
RXPMARESET_TIME_BINARY = RXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME);
$finish;
end
if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1))
RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK;
else begin
$display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK);
$finish;
end
if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15))
RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT);
$finish;
end
if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1))
RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE);
$finish;
end
if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1))
RXSYNC_OVRD_BINARY = RXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD);
$finish;
end
if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1))
RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA);
$finish;
end
if ((RX_BIAS_CFG >= 24'b000000000000000000000000) && (RX_BIAS_CFG <= 24'b111111111111111111111111))
RX_BIAS_CFG_BINARY = RX_BIAS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 24'b000000000000000000000000 to 24'b111111111111111111111111.", RX_BIAS_CFG);
$finish;
end
if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111))
RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG);
$finish;
end
if ((RX_CLKMUX_PD >= 1'b0) && (RX_CLKMUX_PD <= 1'b1))
RX_CLKMUX_PD_BINARY = RX_CLKMUX_PD;
else begin
$display("Attribute Syntax Error : The Attribute RX_CLKMUX_PD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_PD);
$finish;
end
if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11))
RX_CM_SEL_BINARY = RX_CM_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL);
$finish;
end
if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111))
RX_CM_TRIM_BINARY = RX_CM_TRIM;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_TRIM on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM);
$finish;
end
if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111))
RX_DDI_SEL_BINARY = RX_DDI_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_DDI_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL);
$finish;
end
if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111))
RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG);
$finish;
end
if ((RX_DFELPM_CFG0 >= 4'b0000) && (RX_DFELPM_CFG0 <= 4'b1111))
RX_DFELPM_CFG0_BINARY = RX_DFELPM_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFELPM_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFELPM_CFG0);
$finish;
end
if ((RX_DFELPM_CFG1 >= 1'b0) && (RX_DFELPM_CFG1 <= 1'b1))
RX_DFELPM_CFG1_BINARY = RX_DFELPM_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFELPM_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFELPM_CFG1);
$finish;
end
if ((RX_DFELPM_KLKH_AGC_STUP_EN >= 1'b0) && (RX_DFELPM_KLKH_AGC_STUP_EN <= 1'b1))
RX_DFELPM_KLKH_AGC_STUP_EN_BINARY = RX_DFELPM_KLKH_AGC_STUP_EN;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFELPM_KLKH_AGC_STUP_EN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFELPM_KLKH_AGC_STUP_EN);
$finish;
end
if ((RX_DFE_AGC_CFG0 >= 2'b00) && (RX_DFE_AGC_CFG0 <= 2'b11))
RX_DFE_AGC_CFG0_BINARY = RX_DFE_AGC_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_AGC_CFG0);
$finish;
end
if ((RX_DFE_AGC_CFG1 >= 3'b000) && (RX_DFE_AGC_CFG1 <= 3'b111))
RX_DFE_AGC_CFG1_BINARY = RX_DFE_AGC_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_AGC_CFG1);
$finish;
end
if ((RX_DFE_AGC_CFG2 >= 4'b0000) && (RX_DFE_AGC_CFG2 <= 4'b1111))
RX_DFE_AGC_CFG2_BINARY = RX_DFE_AGC_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_AGC_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_AGC_CFG2);
$finish;
end
if ((RX_DFE_AGC_OVRDEN >= 1'b0) && (RX_DFE_AGC_OVRDEN <= 1'b1))
RX_DFE_AGC_OVRDEN_BINARY = RX_DFE_AGC_OVRDEN;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_AGC_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_AGC_OVRDEN);
$finish;
end
if ((RX_DFE_H2_CFG >= 12'b000000000000) && (RX_DFE_H2_CFG <= 12'b111111111111))
RX_DFE_H2_CFG_BINARY = RX_DFE_H2_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H2_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H2_CFG);
$finish;
end
if ((RX_DFE_H3_CFG >= 12'b000000000000) && (RX_DFE_H3_CFG <= 12'b111111111111))
RX_DFE_H3_CFG_BINARY = RX_DFE_H3_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H3_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H3_CFG);
$finish;
end
if ((RX_DFE_H4_CFG >= 11'b00000000000) && (RX_DFE_H4_CFG <= 11'b11111111111))
RX_DFE_H4_CFG_BINARY = RX_DFE_H4_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H4_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H4_CFG);
$finish;
end
if ((RX_DFE_H5_CFG >= 11'b00000000000) && (RX_DFE_H5_CFG <= 11'b11111111111))
RX_DFE_H5_CFG_BINARY = RX_DFE_H5_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H5_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H5_CFG);
$finish;
end
if ((RX_DFE_H6_CFG >= 11'b00000000000) && (RX_DFE_H6_CFG <= 11'b11111111111))
RX_DFE_H6_CFG_BINARY = RX_DFE_H6_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H6_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H6_CFG);
$finish;
end
if ((RX_DFE_H7_CFG >= 11'b00000000000) && (RX_DFE_H7_CFG <= 11'b11111111111))
RX_DFE_H7_CFG_BINARY = RX_DFE_H7_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H7_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H7_CFG);
$finish;
end
if ((RX_DFE_KL_CFG >= 33'b000000000000000000000000000000000) && (RX_DFE_KL_CFG <= 33'b111111111111111111111111111111111))
RX_DFE_KL_CFG_BINARY = RX_DFE_KL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 33'b000000000000000000000000000000000 to 33'b111111111111111111111111111111111.", RX_DFE_KL_CFG);
$finish;
end
if ((RX_DFE_KL_LPM_KH_CFG0 >= 2'b00) && (RX_DFE_KL_LPM_KH_CFG0 <= 2'b11))
RX_DFE_KL_LPM_KH_CFG0_BINARY = RX_DFE_KL_LPM_KH_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_KL_LPM_KH_CFG0);
$finish;
end
if ((RX_DFE_KL_LPM_KH_CFG1 >= 3'b000) && (RX_DFE_KL_LPM_KH_CFG1 <= 3'b111))
RX_DFE_KL_LPM_KH_CFG1_BINARY = RX_DFE_KL_LPM_KH_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_KL_LPM_KH_CFG1);
$finish;
end
if ((RX_DFE_KL_LPM_KH_CFG2 >= 4'b0000) && (RX_DFE_KL_LPM_KH_CFG2 <= 4'b1111))
RX_DFE_KL_LPM_KH_CFG2_BINARY = RX_DFE_KL_LPM_KH_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_KL_LPM_KH_CFG2);
$finish;
end
if ((RX_DFE_KL_LPM_KH_OVRDEN >= 1'b0) && (RX_DFE_KL_LPM_KH_OVRDEN <= 1'b1))
RX_DFE_KL_LPM_KH_OVRDEN_BINARY = RX_DFE_KL_LPM_KH_OVRDEN;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KH_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_KL_LPM_KH_OVRDEN);
$finish;
end
if ((RX_DFE_KL_LPM_KL_CFG0 >= 2'b00) && (RX_DFE_KL_LPM_KL_CFG0 <= 2'b11))
RX_DFE_KL_LPM_KL_CFG0_BINARY = RX_DFE_KL_LPM_KL_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_DFE_KL_LPM_KL_CFG0);
$finish;
end
if ((RX_DFE_KL_LPM_KL_CFG1 >= 3'b000) && (RX_DFE_KL_LPM_KL_CFG1 <= 3'b111))
RX_DFE_KL_LPM_KL_CFG1_BINARY = RX_DFE_KL_LPM_KL_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_DFE_KL_LPM_KL_CFG1);
$finish;
end
if ((RX_DFE_KL_LPM_KL_CFG2 >= 4'b0000) && (RX_DFE_KL_LPM_KL_CFG2 <= 4'b1111))
RX_DFE_KL_LPM_KL_CFG2_BINARY = RX_DFE_KL_LPM_KL_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_DFE_KL_LPM_KL_CFG2);
$finish;
end
if ((RX_DFE_KL_LPM_KL_OVRDEN >= 1'b0) && (RX_DFE_KL_LPM_KL_OVRDEN <= 1'b1))
RX_DFE_KL_LPM_KL_OVRDEN_BINARY = RX_DFE_KL_LPM_KL_OVRDEN;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_LPM_KL_OVRDEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_KL_LPM_KL_OVRDEN);
$finish;
end
if ((RX_DFE_LPM_HOLD_DURING_EIDLE >= 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE <= 1'b1))
RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY = RX_DFE_LPM_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_LPM_HOLD_DURING_EIDLE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_LPM_HOLD_DURING_EIDLE);
$finish;
end
if ((RX_DFE_UT_CFG >= 17'b00000000000000000) && (RX_DFE_UT_CFG <= 17'b11111111111111111))
RX_DFE_UT_CFG_BINARY = RX_DFE_UT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_UT_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_UT_CFG);
$finish;
end
if ((RX_DFE_VP_CFG >= 17'b00000000000000000) && (RX_DFE_VP_CFG <= 17'b11111111111111111))
RX_DFE_VP_CFG_BINARY = RX_DFE_VP_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_VP_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_VP_CFG);
$finish;
end
if ((RX_INT_DATAWIDTH >= 0) && (RX_INT_DATAWIDTH <= 1))
RX_INT_DATAWIDTH_BINARY = RX_INT_DATAWIDTH;
else begin
$display("Attribute Syntax Error : The Attribute RX_INT_DATAWIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", RX_INT_DATAWIDTH);
$finish;
end
if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111))
RX_OS_CFG_BINARY = RX_OS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_OS_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG);
$finish;
end
if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127))
SAS_MAX_COM_BINARY = SAS_MAX_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MAX_COM on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM);
$finish;
end
if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63))
SAS_MIN_COM_BINARY = SAS_MIN_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MIN_COM on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM);
$finish;
end
if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111))
SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN);
$finish;
end
if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111))
SATA_BURST_VAL_BINARY = SATA_BURST_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL);
$finish;
end
if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111))
SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL);
$finish;
end
if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63))
SATA_MAX_BURST_BINARY = SATA_MAX_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST);
$finish;
end
if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63))
SATA_MAX_INIT_BINARY = SATA_MAX_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT);
$finish;
end
if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63))
SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE);
$finish;
end
if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61))
SATA_MIN_BURST_BINARY = SATA_MIN_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST);
$finish;
end
if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63))
SATA_MIN_INIT_BINARY = SATA_MIN_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT);
$finish;
end
if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63))
SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE);
$finish;
end
if ((SIM_CPLLREFCLK_SEL >= 3'b0) && (SIM_CPLLREFCLK_SEL <= 3'b111))
SIM_CPLLREFCLK_SEL_BINARY = SIM_CPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_CPLLREFCLK_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_CPLLREFCLK_SEL);
$finish;
end
if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111))
TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG);
$finish;
end
if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111))
TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD);
$finish;
end
if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1))
TXOOB_CFG_BINARY = TXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXOOB_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG);
$finish;
end
if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111))
TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME);
$finish;
end
if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111))
TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL);
$finish;
end
if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11))
TXPI_CFG0_BINARY = TXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0);
$finish;
end
if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11))
TXPI_CFG1_BINARY = TXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1);
$finish;
end
if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11))
TXPI_CFG2_BINARY = TXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2);
$finish;
end
if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1))
TXPI_CFG3_BINARY = TXPI_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3);
$finish;
end
if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1))
TXPI_CFG4_BINARY = TXPI_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4);
$finish;
end
if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111))
TXPI_CFG5_BINARY = TXPI_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG5 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5);
$finish;
end
if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1))
TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL);
$finish;
end
if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1))
TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL);
$finish;
end
if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111))
TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG);
$finish;
end
if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111))
TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM);
$finish;
end
if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111))
TXPMARESET_TIME_BINARY = TXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME);
$finish;
end
if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1))
TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE);
$finish;
end
if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1))
TXSYNC_OVRD_BINARY = TXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD);
$finish;
end
if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1))
TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA);
$finish;
end
if ((TX_CLKMUX_PD >= 1'b0) && (TX_CLKMUX_PD <= 1'b1))
TX_CLKMUX_PD_BINARY = TX_CLKMUX_PD;
else begin
$display("Attribute Syntax Error : The Attribute TX_CLKMUX_PD on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_PD);
$finish;
end
if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111))
TX_DEEMPH0_BINARY = TX_DEEMPH0;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0);
$finish;
end
if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111))
TX_DEEMPH1_BINARY = TX_DEEMPH1;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1);
$finish;
end
if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111))
TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY);
$finish;
end
if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111))
TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY);
$finish;
end
if ((TX_INT_DATAWIDTH >= 0) && (TX_INT_DATAWIDTH <= 1))
TX_INT_DATAWIDTH_BINARY = TX_INT_DATAWIDTH;
else begin
$display("Attribute Syntax Error : The Attribute TX_INT_DATAWIDTH on GTHE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", TX_INT_DATAWIDTH);
$finish;
end
if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1))
TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL);
$finish;
end
if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111))
TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0);
$finish;
end
if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111))
TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1);
$finish;
end
if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111))
TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2);
$finish;
end
if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111))
TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3);
$finish;
end
if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111))
TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4);
$finish;
end
if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111))
TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0);
$finish;
end
if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111))
TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1);
$finish;
end
if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111))
TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2);
$finish;
end
if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111))
TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3);
$finish;
end
if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111))
TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4);
$finish;
end
if ((TX_QPI_STATUS_EN >= 1'b0) && (TX_QPI_STATUS_EN <= 1'b1))
TX_QPI_STATUS_EN_BINARY = TX_QPI_STATUS_EN;
else begin
$display("Attribute Syntax Error : The Attribute TX_QPI_STATUS_EN on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_QPI_STATUS_EN);
$finish;
end
if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111))
TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF;
else begin
$display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF);
$finish;
end
if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1))
UCODEER_CLR_BINARY = UCODEER_CLR;
else begin
$display("Attribute Syntax Error : The Attribute UCODEER_CLR on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR);
$finish;
end
if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1))
USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on GTHE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL);
$finish;
end
end
wire [14:0] delay_DMONITOROUT;
wire [15:0] delay_DRPDO;
wire [15:0] delay_PCSRSVDOUT;
wire [1:0] delay_RXCLKCORCNT;
wire [1:0] delay_RXDATAVALID;
wire [1:0] delay_RXHEADERVALID;
wire [1:0] delay_RXSTARTOFSEQ;
wire [1:0] delay_TXBUFSTATUS;
wire [2:0] delay_RXBUFSTATUS;
wire [2:0] delay_RXSTATUS;
wire [4:0] delay_RXCHBONDO;
wire [4:0] delay_RXPHMONITOR;
wire [4:0] delay_RXPHSLIPMONITOR;
wire [5:0] delay_RXHEADER;
wire [63:0] delay_RXDATA;
wire [6:0] delay_RXMONITOROUT;
wire [7:0] delay_RXCHARISCOMMA;
wire [7:0] delay_RXCHARISK;
wire [7:0] delay_RXDISPERR;
wire [7:0] delay_RXNOTINTABLE;
wire delay_CPLLFBCLKLOST;
wire delay_CPLLLOCK;
wire delay_CPLLREFCLKLOST;
wire delay_DRPRDY;
wire delay_EYESCANDATAERROR;
wire delay_GTHTXN;
wire delay_GTHTXP;
wire delay_GTREFCLKMONITOR;
wire delay_PHYSTATUS;
wire delay_RSOSINTDONE;
wire delay_RXBYTEISALIGNED;
wire delay_RXBYTEREALIGN;
wire delay_RXCDRLOCK;
wire delay_RXCHANBONDSEQ;
wire delay_RXCHANISALIGNED;
wire delay_RXCHANREALIGN;
wire delay_RXCOMINITDET;
wire delay_RXCOMMADET;
wire delay_RXCOMSASDET;
wire delay_RXCOMWAKEDET;
wire delay_RXDFESLIDETAPSTARTED;
wire delay_RXDFESLIDETAPSTROBEDONE;
wire delay_RXDFESLIDETAPSTROBESTARTED;
wire delay_RXDFESTADAPTDONE;
wire delay_RXDLYSRESETDONE;
wire delay_RXELECIDLE;
wire delay_RXOSINTSTARTED;
wire delay_RXOSINTSTROBEDONE;
wire delay_RXOSINTSTROBESTARTED;
wire delay_RXOUTCLK;
wire delay_RXOUTCLKFABRIC;
wire delay_RXOUTCLKPCS;
wire delay_RXPHALIGNDONE;
wire delay_RXPMARESETDONE;
wire delay_RXPRBSERR;
wire delay_RXQPISENN;
wire delay_RXQPISENP;
wire delay_RXRATEDONE;
wire delay_RXRESETDONE;
wire delay_RXSYNCDONE;
wire delay_RXSYNCOUT;
wire delay_RXVALID;
wire delay_TXCOMFINISH;
wire delay_TXDLYSRESETDONE;
wire delay_TXGEARBOXREADY;
wire delay_TXOUTCLK;
wire delay_TXOUTCLKFABRIC;
wire delay_TXOUTCLKPCS;
wire delay_TXPHALIGNDONE;
wire delay_TXPHINITDONE;
wire delay_TXPMARESETDONE;
wire delay_TXQPISENN;
wire delay_TXQPISENP;
wire delay_TXRATEDONE;
wire delay_TXRESETDONE;
wire delay_TXSYNCDONE;
wire delay_TXSYNCOUT;
wire [13:0] delay_RXADAPTSELTEST;
wire [15:0] delay_DRPDI;
wire [15:0] delay_GTRSVD;
wire [15:0] delay_PCSRSVDIN;
wire [19:0] delay_TSTIN;
wire [1:0] delay_RXELECIDLEMODE;
wire [1:0] delay_RXMONITORSEL;
wire [1:0] delay_RXPD;
wire [1:0] delay_RXSYSCLKSEL;
wire [1:0] delay_TXPD;
wire [1:0] delay_TXSYSCLKSEL;
wire [2:0] delay_CPLLREFCLKSEL;
wire [2:0] delay_LOOPBACK;
wire [2:0] delay_RXCHBONDLEVEL;
wire [2:0] delay_RXOUTCLKSEL;
wire [2:0] delay_RXPRBSSEL;
wire [2:0] delay_RXRATE;
wire [2:0] delay_TXBUFDIFFCTRL;
wire [2:0] delay_TXHEADER;
wire [2:0] delay_TXMARGIN;
wire [2:0] delay_TXOUTCLKSEL;
wire [2:0] delay_TXPRBSSEL;
wire [2:0] delay_TXRATE;
wire [3:0] delay_RXOSINTCFG;
wire [3:0] delay_RXOSINTID0;
wire [3:0] delay_TXDIFFCTRL;
wire [4:0] delay_PCSRSVDIN2;
wire [4:0] delay_PMARSVDIN;
wire [4:0] delay_RXCHBONDI;
wire [4:0] delay_RXDFEAGCTRL;
wire [4:0] delay_RXDFESLIDETAP;
wire [4:0] delay_TXPIPPMSTEPSIZE;
wire [4:0] delay_TXPOSTCURSOR;
wire [4:0] delay_TXPRECURSOR;
wire [5:0] delay_RXDFESLIDETAPID;
wire [63:0] delay_TXDATA;
wire [6:0] delay_TXMAINCURSOR;
wire [6:0] delay_TXSEQUENCE;
wire [7:0] delay_TX8B10BBYPASS;
wire [7:0] delay_TXCHARDISPMODE;
wire [7:0] delay_TXCHARDISPVAL;
wire [7:0] delay_TXCHARISK;
wire [8:0] delay_DRPADDR;
wire delay_CFGRESET;
wire delay_CLKRSVD0;
wire delay_CLKRSVD1;
wire delay_CPLLLOCKDETCLK;
wire delay_CPLLLOCKEN;
wire delay_CPLLPD;
wire delay_CPLLRESET;
wire delay_DMONFIFORESET;
wire delay_DMONITORCLK;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_EYESCANMODE;
wire delay_EYESCANRESET;
wire delay_EYESCANTRIGGER;
wire delay_GTGREFCLK;
wire delay_GTHRXN;
wire delay_GTHRXP;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTRESETSEL;
wire delay_GTRXRESET;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_GTTXRESET;
wire delay_QPLLCLK;
wire delay_QPLLREFCLK;
wire delay_RESETOVRD;
wire delay_RX8B10BEN;
wire delay_RXBUFRESET;
wire delay_RXCDRFREQRESET;
wire delay_RXCDRHOLD;
wire delay_RXCDROVRDEN;
wire delay_RXCDRRESET;
wire delay_RXCDRRESETRSV;
wire delay_RXCHBONDEN;
wire delay_RXCHBONDMASTER;
wire delay_RXCHBONDSLAVE;
wire delay_RXCOMMADETEN;
wire delay_RXDDIEN;
wire delay_RXDFEAGCHOLD;
wire delay_RXDFEAGCOVRDEN;
wire delay_RXDFECM1EN;
wire delay_RXDFELFHOLD;
wire delay_RXDFELFOVRDEN;
wire delay_RXDFELPMRESET;
wire delay_RXDFESLIDETAPADAPTEN;
wire delay_RXDFESLIDETAPHOLD;
wire delay_RXDFESLIDETAPINITOVRDEN;
wire delay_RXDFESLIDETAPONLYADAPTEN;
wire delay_RXDFESLIDETAPOVRDEN;
wire delay_RXDFESLIDETAPSTROBE;
wire delay_RXDFETAP2HOLD;
wire delay_RXDFETAP2OVRDEN;
wire delay_RXDFETAP3HOLD;
wire delay_RXDFETAP3OVRDEN;
wire delay_RXDFETAP4HOLD;
wire delay_RXDFETAP4OVRDEN;
wire delay_RXDFETAP5HOLD;
wire delay_RXDFETAP5OVRDEN;
wire delay_RXDFETAP6HOLD;
wire delay_RXDFETAP6OVRDEN;
wire delay_RXDFETAP7HOLD;
wire delay_RXDFETAP7OVRDEN;
wire delay_RXDFEUTHOLD;
wire delay_RXDFEUTOVRDEN;
wire delay_RXDFEVPHOLD;
wire delay_RXDFEVPOVRDEN;
wire delay_RXDFEVSEN;
wire delay_RXDFEXYDEN;
wire delay_RXDLYBYPASS;
wire delay_RXDLYEN;
wire delay_RXDLYOVRDEN;
wire delay_RXDLYSRESET;
wire delay_RXGEARBOXSLIP;
wire delay_RXLPMEN;
wire delay_RXLPMHFHOLD;
wire delay_RXLPMHFOVRDEN;
wire delay_RXLPMLFHOLD;
wire delay_RXLPMLFKLOVRDEN;
wire delay_RXMCOMMAALIGNEN;
wire delay_RXOOBRESET;
wire delay_RXOSCALRESET;
wire delay_RXOSHOLD;
wire delay_RXOSINTEN;
wire delay_RXOSINTHOLD;
wire delay_RXOSINTNTRLEN;
wire delay_RXOSINTOVRDEN;
wire delay_RXOSINTSTROBE;
wire delay_RXOSINTTESTOVRDEN;
wire delay_RXOSOVRDEN;
wire delay_RXPCOMMAALIGNEN;
wire delay_RXPCSRESET;
wire delay_RXPHALIGN;
wire delay_RXPHALIGNEN;
wire delay_RXPHDLYPD;
wire delay_RXPHDLYRESET;
wire delay_RXPHOVRDEN;
wire delay_RXPMARESET;
wire delay_RXPOLARITY;
wire delay_RXPRBSCNTRESET;
wire delay_RXQPIEN;
wire delay_RXRATEMODE;
wire delay_RXSLIDE;
wire delay_RXSYNCALLIN;
wire delay_RXSYNCIN;
wire delay_RXSYNCMODE;
wire delay_RXUSERRDY;
wire delay_RXUSRCLK2;
wire delay_RXUSRCLK;
wire delay_SETERRSTATUS;
wire delay_SIGVALIDCLK;
wire delay_TX8B10BEN;
wire delay_TXCOMINIT;
wire delay_TXCOMSAS;
wire delay_TXCOMWAKE;
wire delay_TXDEEMPH;
wire delay_TXDETECTRX;
wire delay_TXDIFFPD;
wire delay_TXDLYBYPASS;
wire delay_TXDLYEN;
wire delay_TXDLYHOLD;
wire delay_TXDLYOVRDEN;
wire delay_TXDLYSRESET;
wire delay_TXDLYUPDOWN;
wire delay_TXELECIDLE;
wire delay_TXINHIBIT;
wire delay_TXPCSRESET;
wire delay_TXPDELECIDLEMODE;
wire delay_TXPHALIGN;
wire delay_TXPHALIGNEN;
wire delay_TXPHDLYPD;
wire delay_TXPHDLYRESET;
wire delay_TXPHDLYTSTCLK;
wire delay_TXPHINIT;
wire delay_TXPHOVRDEN;
wire delay_TXPIPPMEN;
wire delay_TXPIPPMOVRDEN;
wire delay_TXPIPPMPD;
wire delay_TXPIPPMSEL;
wire delay_TXPISOPD;
wire delay_TXPMARESET;
wire delay_TXPOLARITY;
wire delay_TXPOSTCURSORINV;
wire delay_TXPRBSFORCEERR;
wire delay_TXPRECURSORINV;
wire delay_TXQPIBIASEN;
wire delay_TXQPISTRONGPDOWN;
wire delay_TXQPIWEAKPUP;
wire delay_TXRATEMODE;
wire delay_TXSTARTSEQ;
wire delay_TXSWING;
wire delay_TXSYNCALLIN;
wire delay_TXSYNCIN;
wire delay_TXSYNCMODE;
wire delay_TXUSERRDY;
wire delay_TXUSRCLK2;
wire delay_TXUSRCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED;
reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED;
reg [0:0] IS_CPLLLOCKDETCLK_INVERTED_REG = IS_CPLLLOCKDETCLK_INVERTED;
reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED;
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED;
reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED;
reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED;
reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED;
reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED;
reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED;
assign #(OUTCLK_DELAY) GTREFCLKMONITOR = delay_GTREFCLKMONITOR;
assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK;
assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK;
assign #(out_delay) CPLLFBCLKLOST = delay_CPLLFBCLKLOST;
assign #(out_delay) CPLLLOCK = delay_CPLLLOCK;
assign #(out_delay) CPLLREFCLKLOST = delay_CPLLREFCLKLOST;
assign #(out_delay) DMONITOROUT = delay_DMONITOROUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR;
assign #(out_delay) GTHTXN = delay_GTHTXN;
assign #(out_delay) GTHTXP = delay_GTHTXP;
assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT;
assign #(out_delay) PHYSTATUS = delay_PHYSTATUS;
assign #(out_delay) RSOSINTDONE = delay_RSOSINTDONE;
assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS;
assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED;
assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN;
assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK;
assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ;
assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED;
assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN;
assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA;
assign #(out_delay) RXCHARISK = delay_RXCHARISK;
assign #(out_delay) RXCHBONDO = delay_RXCHBONDO;
assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT;
assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET;
assign #(out_delay) RXCOMMADET = delay_RXCOMMADET;
assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET;
assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET;
assign #(out_delay) RXDATA = delay_RXDATA;
assign #(out_delay) RXDATAVALID = delay_RXDATAVALID;
assign #(out_delay) RXDFESLIDETAPSTARTED = delay_RXDFESLIDETAPSTARTED;
assign #(out_delay) RXDFESLIDETAPSTROBEDONE = delay_RXDFESLIDETAPSTROBEDONE;
assign #(out_delay) RXDFESLIDETAPSTROBESTARTED = delay_RXDFESLIDETAPSTROBESTARTED;
assign #(out_delay) RXDFESTADAPTDONE = delay_RXDFESTADAPTDONE;
assign #(out_delay) RXDISPERR = delay_RXDISPERR;
assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE;
assign #(out_delay) RXELECIDLE = delay_RXELECIDLE;
assign #(out_delay) RXHEADER = delay_RXHEADER;
assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID;
assign #(out_delay) RXMONITOROUT = delay_RXMONITOROUT;
assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE;
assign #(out_delay) RXOSINTSTARTED = delay_RXOSINTSTARTED;
assign #(out_delay) RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE;
assign #(out_delay) RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED;
assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC;
assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS;
assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE;
assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR;
assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR;
assign #(out_delay) RXPMARESETDONE = delay_RXPMARESETDONE;
assign #(out_delay) RXPRBSERR = delay_RXPRBSERR;
assign #(out_delay) RXQPISENN = delay_RXQPISENN;
assign #(out_delay) RXQPISENP = delay_RXQPISENP;
assign #(out_delay) RXRATEDONE = delay_RXRATEDONE;
assign #(out_delay) RXRESETDONE = delay_RXRESETDONE;
assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ;
assign #(out_delay) RXSTATUS = delay_RXSTATUS;
assign #(out_delay) RXSYNCDONE = delay_RXSYNCDONE;
assign #(out_delay) RXSYNCOUT = delay_RXSYNCOUT;
assign #(out_delay) RXVALID = delay_RXVALID;
assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS;
assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH;
assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE;
assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY;
assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC;
assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS;
assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE;
assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE;
assign #(out_delay) TXPMARESETDONE = delay_TXPMARESETDONE;
assign #(out_delay) TXQPISENN = delay_TXQPISENN;
assign #(out_delay) TXQPISENP = delay_TXQPISENP;
assign #(out_delay) TXRATEDONE = delay_TXRATEDONE;
assign #(out_delay) TXRESETDONE = delay_TXRESETDONE;
assign #(out_delay) TXSYNCDONE = delay_TXSYNCDONE;
assign #(out_delay) TXSYNCOUT = delay_TXSYNCOUT;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG;
assign #(INCLK_DELAY) delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG;
assign #(INCLK_DELAY) delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK;
assign #(INCLK_DELAY) delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign #(INCLK_DELAY) delay_QPLLCLK = QPLLCLK;
assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_SIGVALIDCLK = SIGVALIDCLK ^ IS_SIGVALIDCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK ^ IS_TXUSRCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2 ^ IS_TXUSRCLK2_INVERTED_REG;
assign #(in_delay) delay_CFGRESET = CFGRESET;
assign #(in_delay) delay_CPLLLOCKEN = CPLLLOCKEN;
assign #(in_delay) delay_CPLLPD = CPLLPD;
assign #(in_delay) delay_CPLLREFCLKSEL = CPLLREFCLKSEL;
assign #(in_delay) delay_CPLLRESET = CPLLRESET;
assign #(in_delay) delay_DMONFIFORESET = DMONFIFORESET;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_EYESCANMODE = EYESCANMODE;
assign #(in_delay) delay_EYESCANRESET = EYESCANRESET;
assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign #(in_delay) delay_GTHRXN = GTHRXN;
assign #(in_delay) delay_GTHRXP = GTHRXP;
assign #(in_delay) delay_GTRESETSEL = GTRESETSEL;
assign #(in_delay) delay_GTRSVD = GTRSVD;
assign #(in_delay) delay_GTRXRESET = GTRXRESET;
assign #(in_delay) delay_GTTXRESET = GTTXRESET;
assign #(in_delay) delay_LOOPBACK = LOOPBACK;
assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN;
assign #(in_delay) delay_PCSRSVDIN2 = PCSRSVDIN2;
assign #(in_delay) delay_PMARSVDIN = PMARSVDIN;
assign #(in_delay) delay_QPLLREFCLK = QPLLREFCLK;
assign #(in_delay) delay_RESETOVRD = RESETOVRD;
assign #(in_delay) delay_RX8B10BEN = RX8B10BEN;
assign #(in_delay) delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign #(in_delay) delay_RXBUFRESET = RXBUFRESET;
assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD;
assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN;
assign #(in_delay) delay_RXCDRRESET = RXCDRRESET;
assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN;
assign #(in_delay) delay_RXCHBONDI = RXCHBONDI;
assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL;
assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER;
assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE;
assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN;
assign #(in_delay) delay_RXDDIEN = RXDDIEN;
assign #(in_delay) delay_RXDFEAGCHOLD = RXDFEAGCHOLD;
assign #(in_delay) delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN;
assign #(in_delay) delay_RXDFEAGCTRL = RXDFEAGCTRL;
assign #(in_delay) delay_RXDFECM1EN = RXDFECM1EN;
assign #(in_delay) delay_RXDFELFHOLD = RXDFELFHOLD;
assign #(in_delay) delay_RXDFELFOVRDEN = RXDFELFOVRDEN;
assign #(in_delay) delay_RXDFELPMRESET = RXDFELPMRESET;
assign #(in_delay) delay_RXDFESLIDETAP = RXDFESLIDETAP;
assign #(in_delay) delay_RXDFESLIDETAPADAPTEN = RXDFESLIDETAPADAPTEN;
assign #(in_delay) delay_RXDFESLIDETAPHOLD = RXDFESLIDETAPHOLD;
assign #(in_delay) delay_RXDFESLIDETAPID = RXDFESLIDETAPID;
assign #(in_delay) delay_RXDFESLIDETAPINITOVRDEN = RXDFESLIDETAPINITOVRDEN;
assign #(in_delay) delay_RXDFESLIDETAPONLYADAPTEN = RXDFESLIDETAPONLYADAPTEN;
assign #(in_delay) delay_RXDFESLIDETAPOVRDEN = RXDFESLIDETAPOVRDEN;
assign #(in_delay) delay_RXDFESLIDETAPSTROBE = RXDFESLIDETAPSTROBE;
assign #(in_delay) delay_RXDFETAP2HOLD = RXDFETAP2HOLD;
assign #(in_delay) delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN;
assign #(in_delay) delay_RXDFETAP3HOLD = RXDFETAP3HOLD;
assign #(in_delay) delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN;
assign #(in_delay) delay_RXDFETAP4HOLD = RXDFETAP4HOLD;
assign #(in_delay) delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN;
assign #(in_delay) delay_RXDFETAP5HOLD = RXDFETAP5HOLD;
assign #(in_delay) delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN;
assign #(in_delay) delay_RXDFETAP6HOLD = RXDFETAP6HOLD;
assign #(in_delay) delay_RXDFETAP6OVRDEN = RXDFETAP6OVRDEN;
assign #(in_delay) delay_RXDFETAP7HOLD = RXDFETAP7HOLD;
assign #(in_delay) delay_RXDFETAP7OVRDEN = RXDFETAP7OVRDEN;
assign #(in_delay) delay_RXDFEUTHOLD = RXDFEUTHOLD;
assign #(in_delay) delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN;
assign #(in_delay) delay_RXDFEVPHOLD = RXDFEVPHOLD;
assign #(in_delay) delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN;
assign #(in_delay) delay_RXDFEVSEN = RXDFEVSEN;
assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN;
assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS;
assign #(in_delay) delay_RXDLYEN = RXDLYEN;
assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET;
assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP;
assign #(in_delay) delay_RXLPMEN = RXLPMEN;
assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign #(in_delay) delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN;
assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN;
assign #(in_delay) delay_RXMONITORSEL = RXMONITORSEL;
assign #(in_delay) delay_RXOOBRESET = RXOOBRESET;
assign #(in_delay) delay_RXOSCALRESET = RXOSCALRESET;
assign #(in_delay) delay_RXOSHOLD = RXOSHOLD;
assign #(in_delay) delay_RXOSINTCFG = RXOSINTCFG;
assign #(in_delay) delay_RXOSINTEN = RXOSINTEN;
assign #(in_delay) delay_RXOSINTHOLD = RXOSINTHOLD;
assign #(in_delay) delay_RXOSINTID0 = RXOSINTID0;
assign #(in_delay) delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign #(in_delay) delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign #(in_delay) delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign #(in_delay) delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN;
assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN;
assign #(in_delay) delay_RXPCSRESET = RXPCSRESET;
assign #(in_delay) delay_RXPD = RXPD;
assign #(in_delay) delay_RXPHALIGN = RXPHALIGN;
assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN;
assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD;
assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET;
assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN;
assign #(in_delay) delay_RXPMARESET = RXPMARESET;
assign #(in_delay) delay_RXPOLARITY = RXPOLARITY;
assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET;
assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL;
assign #(in_delay) delay_RXQPIEN = RXQPIEN;
assign #(in_delay) delay_RXRATE = RXRATE;
assign #(in_delay) delay_RXRATEMODE = RXRATEMODE;
assign #(in_delay) delay_RXSLIDE = RXSLIDE;
assign #(in_delay) delay_RXSYNCALLIN = RXSYNCALLIN;
assign #(in_delay) delay_RXSYNCIN = RXSYNCIN;
assign #(in_delay) delay_RXSYNCMODE = RXSYNCMODE;
assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign #(in_delay) delay_RXUSERRDY = RXUSERRDY;
assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS;
assign #(in_delay) delay_TSTIN = TSTIN;
assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS;
assign #(in_delay) delay_TX8B10BEN = TX8B10BEN;
assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE;
assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL;
assign #(in_delay) delay_TXCHARISK = TXCHARISK;
assign #(in_delay) delay_TXCOMINIT = TXCOMINIT;
assign #(in_delay) delay_TXCOMSAS = TXCOMSAS;
assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE;
assign #(in_delay) delay_TXDATA = TXDATA;
assign #(in_delay) delay_TXDEEMPH = TXDEEMPH;
assign #(in_delay) delay_TXDETECTRX = TXDETECTRX;
assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL;
assign #(in_delay) delay_TXDIFFPD = TXDIFFPD;
assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS;
assign #(in_delay) delay_TXDLYEN = TXDLYEN;
assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD;
assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET;
assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN;
assign #(in_delay) delay_TXELECIDLE = TXELECIDLE;
assign #(in_delay) delay_TXHEADER = TXHEADER;
assign #(in_delay) delay_TXINHIBIT = TXINHIBIT;
assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR;
assign #(in_delay) delay_TXMARGIN = TXMARGIN;
assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign #(in_delay) delay_TXPCSRESET = TXPCSRESET;
assign #(in_delay) delay_TXPD = TXPD;
assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign #(in_delay) delay_TXPHALIGN = TXPHALIGN;
assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN;
assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD;
assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET;
assign #(in_delay) delay_TXPHINIT = TXPHINIT;
assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN;
assign #(in_delay) delay_TXPIPPMEN = TXPIPPMEN;
assign #(in_delay) delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN;
assign #(in_delay) delay_TXPIPPMPD = TXPIPPMPD;
assign #(in_delay) delay_TXPIPPMSEL = TXPIPPMSEL;
assign #(in_delay) delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE;
assign #(in_delay) delay_TXPISOPD = TXPISOPD;
assign #(in_delay) delay_TXPMARESET = TXPMARESET;
assign #(in_delay) delay_TXPOLARITY = TXPOLARITY;
assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR;
assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL;
assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR;
assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV;
assign #(in_delay) delay_TXQPIBIASEN = TXQPIBIASEN;
assign #(in_delay) delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN;
assign #(in_delay) delay_TXQPIWEAKPUP = TXQPIWEAKPUP;
assign #(in_delay) delay_TXRATE = TXRATE;
assign #(in_delay) delay_TXRATEMODE = TXRATEMODE;
assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE;
assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ;
assign #(in_delay) delay_TXSWING = TXSWING;
assign #(in_delay) delay_TXSYNCALLIN = TXSYNCALLIN;
assign #(in_delay) delay_TXSYNCIN = TXSYNCIN;
assign #(in_delay) delay_TXSYNCMODE = TXSYNCMODE;
assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign #(in_delay) delay_TXUSERRDY = TXUSERRDY;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CFGRESET = CFGRESET;
assign delay_CLKRSVD0 = CLKRSVD0;
assign delay_CLKRSVD1 = CLKRSVD1;
assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK;
assign delay_CPLLLOCKEN = CPLLLOCKEN;
assign delay_CPLLPD = CPLLPD;
assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL;
assign delay_CPLLRESET = CPLLRESET;
assign delay_DMONFIFORESET = DMONFIFORESET;
assign delay_DMONITORCLK = DMONITORCLK;
assign delay_EYESCANMODE = EYESCANMODE;
assign delay_EYESCANRESET = EYESCANRESET;
assign delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTHRXN = GTHRXN;
assign delay_GTHRXP = GTHRXP;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTRESETSEL = GTRESETSEL;
assign delay_GTRSVD = GTRSVD;
assign delay_GTRXRESET = GTRXRESET;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_GTTXRESET = GTTXRESET;
assign delay_LOOPBACK = LOOPBACK;
assign delay_PCSRSVDIN = PCSRSVDIN;
assign delay_PCSRSVDIN2 = PCSRSVDIN2;
assign delay_PMARSVDIN = PMARSVDIN;
assign delay_QPLLCLK = QPLLCLK;
assign delay_QPLLREFCLK = QPLLREFCLK;
assign delay_RESETOVRD = RESETOVRD;
assign delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign delay_RXBUFRESET = RXBUFRESET;
assign delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign delay_RXCDRHOLD = RXCDRHOLD;
assign delay_RXCDROVRDEN = RXCDROVRDEN;
assign delay_RXCDRRESET = RXCDRRESET;
assign delay_RXCDRRESETRSV = RXCDRRESETRSV;
// assign delay_RXCHBONDI = RXCHBONDI;
assign delay_RXDDIEN = RXDDIEN;
assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD;
assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN;
assign delay_RXDFEAGCTRL = RXDFEAGCTRL;
assign delay_RXDFECM1EN = RXDFECM1EN;
assign delay_RXDFELFHOLD = RXDFELFHOLD;
assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN;
assign delay_RXDFELPMRESET = RXDFELPMRESET;
assign delay_RXDFESLIDETAP = RXDFESLIDETAP;
assign delay_RXDFESLIDETAPADAPTEN = RXDFESLIDETAPADAPTEN;
assign delay_RXDFESLIDETAPHOLD = RXDFESLIDETAPHOLD;
assign delay_RXDFESLIDETAPID = RXDFESLIDETAPID;
assign delay_RXDFESLIDETAPINITOVRDEN = RXDFESLIDETAPINITOVRDEN;
assign delay_RXDFESLIDETAPONLYADAPTEN = RXDFESLIDETAPONLYADAPTEN;
assign delay_RXDFESLIDETAPOVRDEN = RXDFESLIDETAPOVRDEN;
assign delay_RXDFESLIDETAPSTROBE = RXDFESLIDETAPSTROBE;
assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD;
assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN;
assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD;
assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN;
assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD;
assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN;
assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD;
assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN;
assign delay_RXDFETAP6HOLD = RXDFETAP6HOLD;
assign delay_RXDFETAP6OVRDEN = RXDFETAP6OVRDEN;
assign delay_RXDFETAP7HOLD = RXDFETAP7HOLD;
assign delay_RXDFETAP7OVRDEN = RXDFETAP7OVRDEN;
assign delay_RXDFEUTHOLD = RXDFEUTHOLD;
assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN;
assign delay_RXDFEVPHOLD = RXDFEVPHOLD;
assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN;
assign delay_RXDFEVSEN = RXDFEVSEN;
assign delay_RXDFEXYDEN = RXDFEXYDEN;
assign delay_RXDLYBYPASS = RXDLYBYPASS;
assign delay_RXDLYEN = RXDLYEN;
assign delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign delay_RXDLYSRESET = RXDLYSRESET;
assign delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign delay_RXLPMEN = RXLPMEN;
assign delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN;
assign delay_RXMONITORSEL = RXMONITORSEL;
assign delay_RXOOBRESET = RXOOBRESET;
assign delay_RXOSCALRESET = RXOSCALRESET;
assign delay_RXOSHOLD = RXOSHOLD;
assign delay_RXOSINTCFG = RXOSINTCFG;
assign delay_RXOSINTEN = RXOSINTEN;
assign delay_RXOSINTHOLD = RXOSINTHOLD;
assign delay_RXOSINTID0 = RXOSINTID0;
assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign delay_RXOSOVRDEN = RXOSOVRDEN;
assign delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign delay_RXPCSRESET = RXPCSRESET;
assign delay_RXPD = RXPD;
assign delay_RXPHALIGN = RXPHALIGN;
assign delay_RXPHALIGNEN = RXPHALIGNEN;
assign delay_RXPHDLYPD = RXPHDLYPD;
assign delay_RXPHDLYRESET = RXPHDLYRESET;
assign delay_RXPHOVRDEN = RXPHOVRDEN;
assign delay_RXPMARESET = RXPMARESET;
assign delay_RXQPIEN = RXQPIEN;
assign delay_RXRATEMODE = RXRATEMODE;
assign delay_RXSYNCALLIN = RXSYNCALLIN;
assign delay_RXSYNCIN = RXSYNCIN;
assign delay_RXSYNCMODE = RXSYNCMODE;
assign delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign delay_RXUSERRDY = RXUSERRDY;
// assign delay_RXUSRCLK = RXUSRCLK;
assign delay_SIGVALIDCLK = SIGVALIDCLK;
assign delay_TSTIN = TSTIN;
assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign delay_TXDEEMPH = TXDEEMPH;
assign delay_TXDIFFCTRL = TXDIFFCTRL;
assign delay_TXDIFFPD = TXDIFFPD;
assign delay_TXDLYBYPASS = TXDLYBYPASS;
assign delay_TXDLYEN = TXDLYEN;
assign delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign delay_TXDLYSRESET = TXDLYSRESET;
assign delay_TXMAINCURSOR = TXMAINCURSOR;
assign delay_TXMARGIN = TXMARGIN;
assign delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign delay_TXPCSRESET = TXPCSRESET;
assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign delay_TXPHALIGN = TXPHALIGN;
assign delay_TXPHALIGNEN = TXPHALIGNEN;
assign delay_TXPHDLYPD = TXPHDLYPD;
assign delay_TXPHDLYRESET = TXPHDLYRESET;
assign delay_TXPHINIT = TXPHINIT;
assign delay_TXPHOVRDEN = TXPHOVRDEN;
assign delay_TXPISOPD = TXPISOPD;
assign delay_TXPMARESET = TXPMARESET;
assign delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign delay_TXPRECURSOR = TXPRECURSOR;
assign delay_TXPRECURSORINV = TXPRECURSORINV;
assign delay_TXQPIBIASEN = TXQPIBIASEN;
assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN;
assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP;
assign delay_TXRATEMODE = TXRATEMODE;
assign delay_TXSWING = TXSWING;
assign delay_TXSYNCALLIN = TXSYNCALLIN;
assign delay_TXSYNCIN = TXSYNCIN;
assign delay_TXSYNCMODE = TXSYNCMODE;
assign delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign delay_TXUSERRDY = TXUSERRDY;
`endif
B_GTHE2_CHANNEL #(
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE),
.ACJTAG_MODE (ACJTAG_MODE),
.ACJTAG_RESET (ACJTAG_RESET),
.ADAPT_CFG0 (ADAPT_CFG0),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.A_RXOSCALRESET (A_RXOSCALRESET),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CFOK_CFG (CFOK_CFG),
.CFOK_CFG2 (CFOK_CFG2),
.CFOK_CFG3 (CFOK_CFG3),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.GEARBOX_MODE (GEARBOX_MODE),
.LOOPBACK_CFG (LOOPBACK_CFG),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV5 (PMA_RSV5),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME),
.RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT),
.RXOUT_DIV (RXOUT_DIV),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_CFG2 (RXPI_CFG2),
.RXPI_CFG3 (RXPI_CFG3),
.RXPI_CFG4 (RXPI_CFG4),
.RXPI_CFG5 (RXPI_CFG5),
.RXPI_CFG6 (RXPI_CFG6),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE),
.RXSYNC_OVRD (RXSYNC_OVRD),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_PD (RX_CLKMUX_PD),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1),
.RX_DFE_AGC_CFG2 (RX_DFE_AGC_CFG2),
.RX_DFE_AGC_OVRDEN (RX_DFE_AGC_OVRDEN),
.RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG),
.RX_DFE_H2_CFG (RX_DFE_H2_CFG),
.RX_DFE_H3_CFG (RX_DFE_H3_CFG),
.RX_DFE_H4_CFG (RX_DFE_H4_CFG),
.RX_DFE_H5_CFG (RX_DFE_H5_CFG),
.RX_DFE_H6_CFG (RX_DFE_H6_CFG),
.RX_DFE_H7_CFG (RX_DFE_H7_CFG),
.RX_DFE_KL_CFG (RX_DFE_KL_CFG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1),
.RX_DFE_KL_LPM_KH_CFG2 (RX_DFE_KL_LPM_KH_CFG2),
.RX_DFE_KL_LPM_KH_OVRDEN (RX_DFE_KL_LPM_KH_OVRDEN),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1),
.RX_DFE_KL_LPM_KL_CFG2 (RX_DFE_KL_LPM_KL_CFG2),
.RX_DFE_KL_LPM_KL_OVRDEN (RX_DFE_KL_LPM_KL_OVRDEN),
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE),
.RX_DFE_ST_CFG (RX_DFE_ST_CFG),
.RX_DFE_UT_CFG (RX_DFE_UT_CFG),
.RX_DFE_VP_CFG (RX_DFE_VP_CFG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.RX_XCLK_SEL (RX_XCLK_SEL),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOOB_CFG (TXOOB_CFG),
.TXOUT_DIV (TXOUT_DIV),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_CFG2 (TXPI_CFG2),
.TXPI_CFG3 (TXPI_CFG3),
.TXPI_CFG4 (TXPI_CFG4),
.TXPI_CFG5 (TXPI_CFG5),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_OVRD (TXSYNC_OVRD),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_PD (TX_CLKMUX_PD),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_PRECHARGE_TIME (TX_RXDETECT_PRECHARGE_TIME),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL (TX_XCLK_SEL),
.UCODEER_CLR (UCODEER_CLR),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL))
B_GTHE2_CHANNEL_INST (
.CPLLFBCLKLOST (delay_CPLLFBCLKLOST),
.CPLLLOCK (delay_CPLLLOCK),
.CPLLREFCLKLOST (delay_CPLLREFCLKLOST),
.DMONITOROUT (delay_DMONITOROUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.EYESCANDATAERROR (delay_EYESCANDATAERROR),
.GTHTXN (delay_GTHTXN),
.GTHTXP (delay_GTHTXP),
.GTREFCLKMONITOR (delay_GTREFCLKMONITOR),
.PCSRSVDOUT (delay_PCSRSVDOUT),
.PHYSTATUS (delay_PHYSTATUS),
.RSOSINTDONE (delay_RSOSINTDONE),
.RXBUFSTATUS (delay_RXBUFSTATUS),
.RXBYTEISALIGNED (delay_RXBYTEISALIGNED),
.RXBYTEREALIGN (delay_RXBYTEREALIGN),
.RXCDRLOCK (delay_RXCDRLOCK),
.RXCHANBONDSEQ (delay_RXCHANBONDSEQ),
.RXCHANISALIGNED (delay_RXCHANISALIGNED),
.RXCHANREALIGN (delay_RXCHANREALIGN),
.RXCHARISCOMMA (delay_RXCHARISCOMMA),
.RXCHARISK (delay_RXCHARISK),
.RXCHBONDO (delay_RXCHBONDO),
.RXCLKCORCNT (delay_RXCLKCORCNT),
.RXCOMINITDET (delay_RXCOMINITDET),
.RXCOMMADET (delay_RXCOMMADET),
.RXCOMSASDET (delay_RXCOMSASDET),
.RXCOMWAKEDET (delay_RXCOMWAKEDET),
.RXDATA (delay_RXDATA),
.RXDATAVALID (delay_RXDATAVALID),
.RXDFESLIDETAPSTARTED (delay_RXDFESLIDETAPSTARTED),
.RXDFESLIDETAPSTROBEDONE (delay_RXDFESLIDETAPSTROBEDONE),
.RXDFESLIDETAPSTROBESTARTED (delay_RXDFESLIDETAPSTROBESTARTED),
.RXDFESTADAPTDONE (delay_RXDFESTADAPTDONE),
.RXDISPERR (delay_RXDISPERR),
.RXDLYSRESETDONE (delay_RXDLYSRESETDONE),
.RXELECIDLE (delay_RXELECIDLE),
.RXHEADER (delay_RXHEADER),
.RXHEADERVALID (delay_RXHEADERVALID),
.RXMONITOROUT (delay_RXMONITOROUT),
.RXNOTINTABLE (delay_RXNOTINTABLE),
.RXOSINTSTARTED (delay_RXOSINTSTARTED),
.RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE),
.RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED),
.RXOUTCLK (delay_RXOUTCLK),
.RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC),
.RXOUTCLKPCS (delay_RXOUTCLKPCS),
.RXPHALIGNDONE (delay_RXPHALIGNDONE),
.RXPHMONITOR (delay_RXPHMONITOR),
.RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR),
.RXPMARESETDONE (delay_RXPMARESETDONE),
.RXPRBSERR (delay_RXPRBSERR),
.RXQPISENN (delay_RXQPISENN),
.RXQPISENP (delay_RXQPISENP),
.RXRATEDONE (delay_RXRATEDONE),
.RXRESETDONE (delay_RXRESETDONE),
.RXSTARTOFSEQ (delay_RXSTARTOFSEQ),
.RXSTATUS (delay_RXSTATUS),
.RXSYNCDONE (delay_RXSYNCDONE),
.RXSYNCOUT (delay_RXSYNCOUT),
.RXVALID (delay_RXVALID),
.TXBUFSTATUS (delay_TXBUFSTATUS),
.TXCOMFINISH (delay_TXCOMFINISH),
.TXDLYSRESETDONE (delay_TXDLYSRESETDONE),
.TXGEARBOXREADY (delay_TXGEARBOXREADY),
.TXOUTCLK (delay_TXOUTCLK),
.TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC),
.TXOUTCLKPCS (delay_TXOUTCLKPCS),
.TXPHALIGNDONE (delay_TXPHALIGNDONE),
.TXPHINITDONE (delay_TXPHINITDONE),
.TXPMARESETDONE (delay_TXPMARESETDONE),
.TXQPISENN (delay_TXQPISENN),
.TXQPISENP (delay_TXQPISENP),
.TXRATEDONE (delay_TXRATEDONE),
.TXRESETDONE (delay_TXRESETDONE),
.TXSYNCDONE (delay_TXSYNCDONE),
.TXSYNCOUT (delay_TXSYNCOUT),
.CFGRESET (delay_CFGRESET),
.CLKRSVD0 (delay_CLKRSVD0),
.CLKRSVD1 (delay_CLKRSVD1),
.CPLLLOCKDETCLK (delay_CPLLLOCKDETCLK),
.CPLLLOCKEN (delay_CPLLLOCKEN),
.CPLLPD (delay_CPLLPD),
.CPLLREFCLKSEL (delay_CPLLREFCLKSEL),
.CPLLRESET (delay_CPLLRESET),
.DMONFIFORESET (delay_DMONFIFORESET),
.DMONITORCLK (delay_DMONITORCLK),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.EYESCANMODE (delay_EYESCANMODE),
.EYESCANRESET (delay_EYESCANRESET),
.EYESCANTRIGGER (delay_EYESCANTRIGGER),
.GTGREFCLK (delay_GTGREFCLK),
.GTHRXN (delay_GTHRXN),
.GTHRXP (delay_GTHRXP),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTRESETSEL (delay_GTRESETSEL),
.GTRSVD (delay_GTRSVD),
.GTRXRESET (delay_GTRXRESET),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.GTTXRESET (delay_GTTXRESET),
.LOOPBACK (delay_LOOPBACK),
.PCSRSVDIN (delay_PCSRSVDIN),
.PCSRSVDIN2 (delay_PCSRSVDIN2),
.PMARSVDIN (delay_PMARSVDIN),
.QPLLCLK (delay_QPLLCLK),
.QPLLREFCLK (delay_QPLLREFCLK),
.RESETOVRD (delay_RESETOVRD),
.RX8B10BEN (delay_RX8B10BEN),
.RXADAPTSELTEST (delay_RXADAPTSELTEST),
.RXBUFRESET (delay_RXBUFRESET),
.RXCDRFREQRESET (delay_RXCDRFREQRESET),
.RXCDRHOLD (delay_RXCDRHOLD),
.RXCDROVRDEN (delay_RXCDROVRDEN),
.RXCDRRESET (delay_RXCDRRESET),
.RXCDRRESETRSV (delay_RXCDRRESETRSV),
.RXCHBONDEN (delay_RXCHBONDEN),
.RXCHBONDI (delay_RXCHBONDI),
.RXCHBONDLEVEL (delay_RXCHBONDLEVEL),
.RXCHBONDMASTER (delay_RXCHBONDMASTER),
.RXCHBONDSLAVE (delay_RXCHBONDSLAVE),
.RXCOMMADETEN (delay_RXCOMMADETEN),
.RXDDIEN (delay_RXDDIEN),
.RXDFEAGCHOLD (delay_RXDFEAGCHOLD),
.RXDFEAGCOVRDEN (delay_RXDFEAGCOVRDEN),
.RXDFEAGCTRL (delay_RXDFEAGCTRL),
.RXDFECM1EN (delay_RXDFECM1EN),
.RXDFELFHOLD (delay_RXDFELFHOLD),
.RXDFELFOVRDEN (delay_RXDFELFOVRDEN),
.RXDFELPMRESET (delay_RXDFELPMRESET),
.RXDFESLIDETAP (delay_RXDFESLIDETAP),
.RXDFESLIDETAPADAPTEN (delay_RXDFESLIDETAPADAPTEN),
.RXDFESLIDETAPHOLD (delay_RXDFESLIDETAPHOLD),
.RXDFESLIDETAPID (delay_RXDFESLIDETAPID),
.RXDFESLIDETAPINITOVRDEN (delay_RXDFESLIDETAPINITOVRDEN),
.RXDFESLIDETAPONLYADAPTEN (delay_RXDFESLIDETAPONLYADAPTEN),
.RXDFESLIDETAPOVRDEN (delay_RXDFESLIDETAPOVRDEN),
.RXDFESLIDETAPSTROBE (delay_RXDFESLIDETAPSTROBE),
.RXDFETAP2HOLD (delay_RXDFETAP2HOLD),
.RXDFETAP2OVRDEN (delay_RXDFETAP2OVRDEN),
.RXDFETAP3HOLD (delay_RXDFETAP3HOLD),
.RXDFETAP3OVRDEN (delay_RXDFETAP3OVRDEN),
.RXDFETAP4HOLD (delay_RXDFETAP4HOLD),
.RXDFETAP4OVRDEN (delay_RXDFETAP4OVRDEN),
.RXDFETAP5HOLD (delay_RXDFETAP5HOLD),
.RXDFETAP5OVRDEN (delay_RXDFETAP5OVRDEN),
.RXDFETAP6HOLD (delay_RXDFETAP6HOLD),
.RXDFETAP6OVRDEN (delay_RXDFETAP6OVRDEN),
.RXDFETAP7HOLD (delay_RXDFETAP7HOLD),
.RXDFETAP7OVRDEN (delay_RXDFETAP7OVRDEN),
.RXDFEUTHOLD (delay_RXDFEUTHOLD),
.RXDFEUTOVRDEN (delay_RXDFEUTOVRDEN),
.RXDFEVPHOLD (delay_RXDFEVPHOLD),
.RXDFEVPOVRDEN (delay_RXDFEVPOVRDEN),
.RXDFEVSEN (delay_RXDFEVSEN),
.RXDFEXYDEN (delay_RXDFEXYDEN),
.RXDLYBYPASS (delay_RXDLYBYPASS),
.RXDLYEN (delay_RXDLYEN),
.RXDLYOVRDEN (delay_RXDLYOVRDEN),
.RXDLYSRESET (delay_RXDLYSRESET),
.RXELECIDLEMODE (delay_RXELECIDLEMODE),
.RXGEARBOXSLIP (delay_RXGEARBOXSLIP),
.RXLPMEN (delay_RXLPMEN),
.RXLPMHFHOLD (delay_RXLPMHFHOLD),
.RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN),
.RXLPMLFHOLD (delay_RXLPMLFHOLD),
.RXLPMLFKLOVRDEN (delay_RXLPMLFKLOVRDEN),
.RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN),
.RXMONITORSEL (delay_RXMONITORSEL),
.RXOOBRESET (delay_RXOOBRESET),
.RXOSCALRESET (delay_RXOSCALRESET),
.RXOSHOLD (delay_RXOSHOLD),
.RXOSINTCFG (delay_RXOSINTCFG),
.RXOSINTEN (delay_RXOSINTEN),
.RXOSINTHOLD (delay_RXOSINTHOLD),
.RXOSINTID0 (delay_RXOSINTID0),
.RXOSINTNTRLEN (delay_RXOSINTNTRLEN),
.RXOSINTOVRDEN (delay_RXOSINTOVRDEN),
.RXOSINTSTROBE (delay_RXOSINTSTROBE),
.RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN),
.RXOSOVRDEN (delay_RXOSOVRDEN),
.RXOUTCLKSEL (delay_RXOUTCLKSEL),
.RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN),
.RXPCSRESET (delay_RXPCSRESET),
.RXPD (delay_RXPD),
.RXPHALIGN (delay_RXPHALIGN),
.RXPHALIGNEN (delay_RXPHALIGNEN),
.RXPHDLYPD (delay_RXPHDLYPD),
.RXPHDLYRESET (delay_RXPHDLYRESET),
.RXPHOVRDEN (delay_RXPHOVRDEN),
.RXPMARESET (delay_RXPMARESET),
.RXPOLARITY (delay_RXPOLARITY),
.RXPRBSCNTRESET (delay_RXPRBSCNTRESET),
.RXPRBSSEL (delay_RXPRBSSEL),
.RXQPIEN (delay_RXQPIEN),
.RXRATE (delay_RXRATE),
.RXRATEMODE (delay_RXRATEMODE),
.RXSLIDE (delay_RXSLIDE),
.RXSYNCALLIN (delay_RXSYNCALLIN),
.RXSYNCIN (delay_RXSYNCIN),
.RXSYNCMODE (delay_RXSYNCMODE),
.RXSYSCLKSEL (delay_RXSYSCLKSEL),
.RXUSERRDY (delay_RXUSERRDY),
.RXUSRCLK (delay_RXUSRCLK),
.RXUSRCLK2 (delay_RXUSRCLK2),
.SETERRSTATUS (delay_SETERRSTATUS),
.SIGVALIDCLK (delay_SIGVALIDCLK),
.TSTIN (delay_TSTIN),
.TX8B10BBYPASS (delay_TX8B10BBYPASS),
.TX8B10BEN (delay_TX8B10BEN),
.TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL),
.TXCHARDISPMODE (delay_TXCHARDISPMODE),
.TXCHARDISPVAL (delay_TXCHARDISPVAL),
.TXCHARISK (delay_TXCHARISK),
.TXCOMINIT (delay_TXCOMINIT),
.TXCOMSAS (delay_TXCOMSAS),
.TXCOMWAKE (delay_TXCOMWAKE),
.TXDATA (delay_TXDATA),
.TXDEEMPH (delay_TXDEEMPH),
.TXDETECTRX (delay_TXDETECTRX),
.TXDIFFCTRL (delay_TXDIFFCTRL),
.TXDIFFPD (delay_TXDIFFPD),
.TXDLYBYPASS (delay_TXDLYBYPASS),
.TXDLYEN (delay_TXDLYEN),
.TXDLYHOLD (delay_TXDLYHOLD),
.TXDLYOVRDEN (delay_TXDLYOVRDEN),
.TXDLYSRESET (delay_TXDLYSRESET),
.TXDLYUPDOWN (delay_TXDLYUPDOWN),
.TXELECIDLE (delay_TXELECIDLE),
.TXHEADER (delay_TXHEADER),
.TXINHIBIT (delay_TXINHIBIT),
.TXMAINCURSOR (delay_TXMAINCURSOR),
.TXMARGIN (delay_TXMARGIN),
.TXOUTCLKSEL (delay_TXOUTCLKSEL),
.TXPCSRESET (delay_TXPCSRESET),
.TXPD (delay_TXPD),
.TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE),
.TXPHALIGN (delay_TXPHALIGN),
.TXPHALIGNEN (delay_TXPHALIGNEN),
.TXPHDLYPD (delay_TXPHDLYPD),
.TXPHDLYRESET (delay_TXPHDLYRESET),
.TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK),
.TXPHINIT (delay_TXPHINIT),
.TXPHOVRDEN (delay_TXPHOVRDEN),
.TXPIPPMEN (delay_TXPIPPMEN),
.TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN),
.TXPIPPMPD (delay_TXPIPPMPD),
.TXPIPPMSEL (delay_TXPIPPMSEL),
.TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE),
.TXPISOPD (delay_TXPISOPD),
.TXPMARESET (delay_TXPMARESET),
.TXPOLARITY (delay_TXPOLARITY),
.TXPOSTCURSOR (delay_TXPOSTCURSOR),
.TXPOSTCURSORINV (delay_TXPOSTCURSORINV),
.TXPRBSFORCEERR (delay_TXPRBSFORCEERR),
.TXPRBSSEL (delay_TXPRBSSEL),
.TXPRECURSOR (delay_TXPRECURSOR),
.TXPRECURSORINV (delay_TXPRECURSORINV),
.TXQPIBIASEN (delay_TXQPIBIASEN),
.TXQPISTRONGPDOWN (delay_TXQPISTRONGPDOWN),
.TXQPIWEAKPUP (delay_TXQPIWEAKPUP),
.TXRATE (delay_TXRATE),
.TXRATEMODE (delay_TXRATEMODE),
.TXSEQUENCE (delay_TXSEQUENCE),
.TXSTARTSEQ (delay_TXSTARTSEQ),
.TXSWING (delay_TXSWING),
.TXSYNCALLIN (delay_TXSYNCALLIN),
.TXSYNCIN (delay_TXSYNCIN),
.TXSYNCMODE (delay_TXSYNCMODE),
.TXSYSCLKSEL (delay_TXSYSCLKSEL),
.TXUSERRDY (delay_TXUSERRDY),
.TXUSRCLK (delay_TXUSRCLK),
.TXUSRCLK2 (delay_TXUSRCLK2),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CLKRSVD0, 0:0:0, notifier);
$period (posedge CLKRSVD1, 0:0:0, notifier);
$period (posedge CPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge DMONITORCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLKMONITOR, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLCLK, 0:0:0, notifier);
$period (posedge RXOUTCLK, 0:0:0, notifier);
$period (posedge RXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge RXOUTCLKPCS, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge SIGVALIDCLK, 0:0:0, notifier);
$period (posedge TXOUTCLK, 0:0:0, notifier);
$period (posedge TXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge TXOUTCLKPCS, 0:0:0, notifier);
$period (posedge TXPHDLYTSTCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMOVRDEN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMPD);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSEL);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMOVRDEN);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMPD);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSEL);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMPD);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSEL);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMOVRDEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMOVRDEN);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMPD);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSEL);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
`endif
( DMONITORCLK *> DMONITOROUT) = (0, 0);
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTNORTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( GTREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( QPLLCLK *> GTREFCLKMONITOR) = (0, 0);
( RXUSRCLK *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> PHYSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0);
( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0);
( RXUSRCLK2 *> RXCHARISK) = (0, 0);
( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0);
( RXUSRCLK2 *> RXCOMINITDET) = (0, 0);
( RXUSRCLK2 *> RXCOMMADET) = (0, 0);
( RXUSRCLK2 *> RXCOMSASDET) = (0, 0);
( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0);
( RXUSRCLK2 *> RXDATA) = (0, 0);
( RXUSRCLK2 *> RXDATAVALID) = (0, 0);
( RXUSRCLK2 *> RXDISPERR) = (0, 0);
( RXUSRCLK2 *> RXHEADER) = (0, 0);
( RXUSRCLK2 *> RXHEADERVALID) = (0, 0);
( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0);
( RXUSRCLK2 *> RXPRBSERR) = (0, 0);
( RXUSRCLK2 *> RXRATEDONE) = (0, 0);
( RXUSRCLK2 *> RXRESETDONE) = (0, 0);
( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0);
( RXUSRCLK2 *> RXSTATUS) = (0, 0);
( RXUSRCLK2 *> RXVALID) = (0, 0);
( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0);
( TXUSRCLK2 *> TXCOMFINISH) = (0, 0);
( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0);
( TXUSRCLK2 *> TXRATEDONE) = (0, 0);
( TXUSRCLK2 *> TXRESETDONE) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTHE2_COMMON.v 0000664 0000000 0000000 00000051743 12327044266 0023315 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTHE2_COMMON.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// Initial version
// 09/22/11 - 624065 - YML update
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 06/12/12 - 664920 - YML update
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE2_COMMON (
DRPDO,
DRPRDY,
PMARSVDOUT,
QPLLDMONITOR,
QPLLFBCLKLOST,
QPLLLOCK,
QPLLOUTCLK,
QPLLOUTREFCLK,
QPLLREFCLKLOST,
REFCLKOUTMONITOR,
BGBYPASSB,
BGMONITORENB,
BGPDB,
BGRCALOVRD,
BGRCALOVRDENB,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
GTGREFCLK,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
PMARSVD,
QPLLLOCKDETCLK,
QPLLLOCKEN,
QPLLOUTRESET,
QPLLPD,
QPLLREFCLKSEL,
QPLLRESET,
QPLLRSVD1,
QPLLRSVD2,
RCALENB
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
parameter [31:0] COMMON_CFG = 32'h0000001C;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [26:0] QPLL_CFG = 27'h0480181;
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
parameter [9:0] QPLL_CP = 10'b0000011111;
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
parameter [15:0] QPLL_LOCK_CFG = 16'h01E8;
parameter [3:0] QPLL_LPF = 4'b1111;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [0:0] QPLL_RP_COMP = 1'b0;
parameter [1:0] QPLL_VTRL_RESET = 2'b00;
parameter [1:0] RCAL_CFG = 2'b00;
parameter [15:0] RSVD_ATTR0 = 16'h0000;
parameter [15:0] RSVD_ATTR1 = 16'h0000;
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_VERSION = "1.1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output QPLLFBCLKLOST;
output QPLLLOCK;
output QPLLOUTCLK;
output QPLLOUTREFCLK;
output QPLLREFCLKLOST;
output REFCLKOUTMONITOR;
output [15:0] DRPDO;
output [15:0] PMARSVDOUT;
output [7:0] QPLLDMONITOR;
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
input BGRCALOVRDENB;
input DRPCLK;
input DRPEN;
input DRPWE;
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
input QPLLPD;
input QPLLRESET;
input RCALENB;
input [15:0] DRPDI;
input [15:0] QPLLRSVD1;
input [2:0] QPLLREFCLKSEL;
input [4:0] BGRCALOVRD;
input [4:0] QPLLRSVD2;
input [7:0] DRPADDR;
input [7:0] PMARSVD;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY;
reg [0:0] QPLL_CP_MONITOR_EN_BINARY;
reg [0:0] QPLL_DMONITOR_SEL_BINARY;
reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY;
reg [0:0] QPLL_FBDIV_RATIO_BINARY;
reg [0:0] QPLL_RP_COMP_BINARY;
reg [1:0] QPLL_VTRL_RESET_BINARY;
reg [1:0] RCAL_CFG_BINARY;
reg [2:0] SIM_QPLLREFCLK_SEL_BINARY;
reg [3:0] QPLL_CLKOUT_CFG_BINARY;
reg [3:0] QPLL_LPF_BINARY;
reg [4:0] QPLL_REFCLK_DIV_BINARY;
reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY;
reg [9:0] QPLL_CP_BINARY;
reg [9:0] QPLL_FBDIV_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (QPLL_REFCLK_DIV)
2 : QPLL_REFCLK_DIV_BINARY = 5'b00000;
1 : QPLL_REFCLK_DIV_BINARY = 5'b10000;
3 : QPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : QPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : QPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : QPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : QPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : QPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : QPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : QPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : QPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on GTHE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTHE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_VERSION)
"1.1" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.1, 1.0, or 2.0.", SIM_VERSION);
$finish;
end
endcase
if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111))
QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG);
$finish;
end
if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111))
QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD);
$finish;
end
if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1))
QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN);
$finish;
end
if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111))
QPLL_CP_BINARY = QPLL_CP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP);
$finish;
end
if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1))
QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN);
$finish;
end
if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1))
QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL);
$finish;
end
if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111))
QPLL_FBDIV_BINARY = QPLL_FBDIV;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV);
$finish;
end
if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1))
QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN);
$finish;
end
if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1))
QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO);
$finish;
end
if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111))
QPLL_LPF_BINARY = QPLL_LPF;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_LPF on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF);
$finish;
end
if ((QPLL_RP_COMP >= 1'b0) && (QPLL_RP_COMP <= 1'b1))
QPLL_RP_COMP_BINARY = QPLL_RP_COMP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_RP_COMP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_RP_COMP);
$finish;
end
if ((QPLL_VTRL_RESET >= 2'b00) && (QPLL_VTRL_RESET <= 2'b11))
QPLL_VTRL_RESET_BINARY = QPLL_VTRL_RESET;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_VTRL_RESET on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", QPLL_VTRL_RESET);
$finish;
end
if ((RCAL_CFG >= 2'b00) && (RCAL_CFG <= 2'b11))
RCAL_CFG_BINARY = RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RCAL_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RCAL_CFG);
$finish;
end
if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111))
SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL);
$finish;
end
end
wire [15:0] delay_DRPDO;
wire [15:0] delay_PMARSVDOUT;
wire [7:0] delay_QPLLDMONITOR;
wire delay_DRPRDY;
wire delay_QPLLFBCLKLOST;
wire delay_QPLLLOCK;
wire delay_QPLLOUTCLK;
wire delay_QPLLOUTREFCLK;
wire delay_QPLLREFCLKLOST;
wire delay_REFCLKOUTMONITOR;
wire [15:0] delay_DRPDI;
wire [15:0] delay_QPLLRSVD1;
wire [2:0] delay_QPLLREFCLKSEL;
wire [4:0] delay_BGRCALOVRD;
wire [4:0] delay_QPLLRSVD2;
wire [7:0] delay_DRPADDR;
wire [7:0] delay_PMARSVD;
wire delay_BGBYPASSB;
wire delay_BGMONITORENB;
wire delay_BGPDB;
wire delay_BGRCALOVRDENB;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_GTGREFCLK;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_QPLLLOCKDETCLK;
wire delay_QPLLLOCKEN;
wire delay_QPLLOUTRESET;
wire delay_QPLLPD;
wire delay_QPLLRESET;
wire delay_RCALENB;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED;
assign #(OUTCLK_DELAY) QPLLOUTCLK = delay_QPLLOUTCLK;
assign #(OUTCLK_DELAY) REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) PMARSVDOUT = delay_PMARSVDOUT;
assign #(out_delay) QPLLDMONITOR = delay_QPLLDMONITOR;
assign #(out_delay) QPLLFBCLKLOST = delay_QPLLFBCLKLOST;
assign #(out_delay) QPLLLOCK = delay_QPLLLOCK;
assign #(out_delay) QPLLOUTREFCLK = delay_QPLLOUTREFCLK;
assign #(out_delay) QPLLREFCLKLOST = delay_QPLLREFCLKLOST;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign #(INCLK_DELAY) delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG;
assign #(in_delay) delay_BGBYPASSB = BGBYPASSB;
assign #(in_delay) delay_BGMONITORENB = BGMONITORENB;
assign #(in_delay) delay_BGPDB = BGPDB;
assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD;
assign #(in_delay) delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_PMARSVD = PMARSVD;
assign #(in_delay) delay_QPLLLOCKEN = QPLLLOCKEN;
assign #(in_delay) delay_QPLLOUTRESET = QPLLOUTRESET;
assign #(in_delay) delay_QPLLPD = QPLLPD;
assign #(in_delay) delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign #(in_delay) delay_QPLLRESET = QPLLRESET;
assign #(in_delay) delay_QPLLRSVD1 = QPLLRSVD1;
assign #(in_delay) delay_QPLLRSVD2 = QPLLRSVD2;
assign #(in_delay) delay_RCALENB = RCALENB;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_PMARSVD = PMARSVD;
assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK;
assign delay_QPLLLOCKEN = QPLLLOCKEN;
assign delay_QPLLOUTRESET = QPLLOUTRESET;
assign delay_QPLLPD = QPLLPD;
assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign delay_QPLLRESET = QPLLRESET;
assign delay_QPLLRSVD1 = QPLLRSVD1;
assign delay_QPLLRSVD2 = QPLLRSVD2;
assign delay_RCALENB = RCALENB;
`endif
B_GTHE2_COMMON #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG),
.QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD),
.QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN),
.QPLL_CP (QPLL_CP),
.QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN),
.QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (QPLL_INIT_CFG),
.QPLL_LOCK_CFG (QPLL_LOCK_CFG),
.QPLL_LPF (QPLL_LPF),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_RP_COMP (QPLL_RP_COMP),
.QPLL_VTRL_RESET (QPLL_VTRL_RESET),
.RCAL_CFG (RCAL_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION))
B_GTHE2_COMMON_INST (
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.PMARSVDOUT (delay_PMARSVDOUT),
.QPLLDMONITOR (delay_QPLLDMONITOR),
.QPLLFBCLKLOST (delay_QPLLFBCLKLOST),
.QPLLLOCK (delay_QPLLLOCK),
.QPLLOUTCLK (delay_QPLLOUTCLK),
.QPLLOUTREFCLK (delay_QPLLOUTREFCLK),
.QPLLREFCLKLOST (delay_QPLLREFCLKLOST),
.REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR),
.BGBYPASSB (delay_BGBYPASSB),
.BGMONITORENB (delay_BGMONITORENB),
.BGPDB (delay_BGPDB),
.BGRCALOVRD (delay_BGRCALOVRD),
.BGRCALOVRDENB (delay_BGRCALOVRDENB),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.GTGREFCLK (delay_GTGREFCLK),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.PMARSVD (delay_PMARSVD),
.QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK),
.QPLLLOCKEN (delay_QPLLLOCKEN),
.QPLLOUTRESET (delay_QPLLOUTRESET),
.QPLLPD (delay_QPLLPD),
.QPLLREFCLKSEL (delay_QPLLREFCLKSEL),
.QPLLRESET (delay_QPLLRESET),
.QPLLRSVD1 (delay_QPLLRSVD1),
.QPLLRSVD2 (delay_QPLLRSVD2),
.RCALENB (delay_RCALENB),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge QPLLOUTCLK, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
`endif
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTHE3_CHANNEL.v 0000664 0000000 0000000 00000726473 12327044266 0023407 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTHE3_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE3_CHANNEL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'h0000,
parameter [15:0] ADAPT_CFG1 = 16'h0000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h20F8,
parameter [15:0] CPLL_CFG1 = 16'hA494,
parameter [15:0] CPLL_CFG2 = 16'hF001,
parameter [5:0] CPLL_CFG3 = 6'h00,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [7:0] CPLL_INIT_CFG1 = 8'h00,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DFE_D_X_REL_POS = 1'b0,
parameter [0:0] DFE_VCM_COMP_EN = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h000,
parameter [9:0] ES_PMA_CFG = 10'b0000000000,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] GM_BIAS_SELECT = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [2:0] PCS_RSVD1 = 3'b000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0,
parameter [15:0] PMA_RSV1 = 16'h0000,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0000,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG1 = 16'h0000,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h0000,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG3 = 16'h0000,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG4 = 16'h0000,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG5 = 16'h0000,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [15:0] RXCFOK_CFG0 = 16'h0000,
parameter [15:0] RXCFOK_CFG1 = 16'h0000,
parameter [15:0] RXCFOK_CFG2 = 16'h0000,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000,
parameter [15:0] RXDFE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0000,
parameter [15:0] RXDLY_CFG = 16'h001F,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "Sigcfg_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h0000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0000,
parameter [15:0] RXLPM_OS_CFG0 = 16'h0000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000,
parameter [8:0] RXOOB_CFG = 9'b000000110,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h6622,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] RXPI_CFG0 = 2'b00,
parameter [1:0] RXPI_CFG1 = 2'b00,
parameter [1:0] RXPI_CFG2 = 2'b00,
parameter [1:0] RXPI_CFG3 = 2'b00,
parameter [0:0] RXPI_CFG4 = 1'b0,
parameter [0:0] RXPI_CFG5 = 1'b1,
parameter [2:0] RXPI_CFG6 = 3'b000,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h0000,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b0000,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter [1:0] RX_CM_SEL = 2'b11,
parameter [3:0] RX_CM_TRIM = 4'b0100,
parameter [7:0] RX_CTLE3_LPF = 8'b00000000,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110,
parameter [0:0] RX_DFELPM_CFG1 = 1'b0,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010,
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_HI_LR = 1'b0,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter real RX_PROGDIV_CFG = 4.0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter [1:0] RX_SUM_RES_CTRL = 2'b00,
parameter [3:0] RX_SUM_VCMTUNE = 4'b0000,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b000,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [0:0] RX_WIDEMODE_CDR = 1'b0,
parameter RX_XCLK_SEL = "RXDES",
parameter integer SAS_MAX_COM = 64,
parameter integer SAS_MIN_COM = 36,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter integer SATA_MAX_BURST = 8,
parameter integer SATA_MAX_INIT = 21,
parameter integer SATA_MAX_WAKE = 7,
parameter integer SATA_MIN_BURST = 4,
parameter integer SATA_MIN_INIT = 12,
parameter integer SATA_MIN_WAKE = 4,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001,
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0,
parameter SIM_VERSION = "Ver_1",
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATUR_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h001F,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter [3:0] TXDRVBIAS_N = 4'b1010,
parameter [3:0] TXDRVBIAS_P = 4'b1100,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h2020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0001,
parameter [15:0] TXPH_CFG = 16'h0980,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter integer TX_DATA_WIDTH = 20,
parameter [5:0] TX_DCD_CFG = 6'b000010,
parameter [0:0] TX_DCD_EN = 1'b0,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_EML_PHI_TUNE = 1'b0,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [2:0] TX_MODE_SEL = 3'b000,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 4.0,
parameter [0:0] TX_QPI_STATUS_EN = 1'b0,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter [2:0] TX_RXDETECT_REF = 3'b100,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0,
parameter [1:0] WB_MODE = 2'b00
)(
output [2:0] BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output [2:0] BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [16:0] DMONITOROUT,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTHTXN,
output GTHTXP,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [11:0] PCSRSVDOUT,
output PHYSTATUS,
output [7:0] PINRSRVDAS,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output [6:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXQPISENN,
output RXQPISENP,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXQPISENN,
output TXQPISENP,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input EVODDPHICALDONE,
input EVODDPHICALSTART,
input EVODDPHIDRDEN,
input EVODDPHIDWREN,
input EVODDPHIXRDEN,
input EVODDPHIXWREN,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTGREFCLK,
input GTHRXN,
input GTHRXP,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTRESETSEL,
input [15:0] GTRSVD,
input GTRXRESET,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input [2:0] LOOPBACK,
input LPBKRXTXSEREN,
input LPBKTXRXSEREN,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input QPLL0CLK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1REFCLK,
input RESETOVRD,
input RSTCLKENTX,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input [1:0] RXDFEAGCCTRL,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEVSEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input [3:0] RXOSINTCFG,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTOVRDEN,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input RXQPIEN,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [2:0] TXBUFDIFFCTRL,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDEEMPH,
input TXDETECTRX,
input [3:0] TXDIFFCTRL,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXPROGDIVRESET,
input TXQPIBIASEN,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTHE3_CHANNEL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0;
localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1;
localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2;
localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3;
localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1;
localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
localparam [1:0] DDI_CTRL_REG = DDI_CTRL;
localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS;
localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN;
localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
localparam [5:0] ES_CONTROL_REG = ES_CONTROL;
localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG;
localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE;
localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG;
localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT;
localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL;
localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP;
localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0;
localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1;
localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12;
localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3;
localparam [15:0] PMA_RSV1_REG = PMA_RSV1;
localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR;
localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
localparam [40:1] RXBUF_EN_REG = RXBUF_EN;
localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG;
localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG;
localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG;
localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
localparam [4:0] RXOUT_DIV_REG = RXOUT_DIV;
localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
localparam [1:0] RXPI_CFG0_REG = RXPI_CFG0;
localparam [1:0] RXPI_CFG1_REG = RXPI_CFG1;
localparam [1:0] RXPI_CFG2_REG = RXPI_CFG2;
localparam [1:0] RXPI_CFG3_REG = RXPI_CFG3;
localparam [0:0] RXPI_CFG4_REG = RXPI_CFG4;
localparam [0:0] RXPI_CFG5_REG = RXPI_CFG5;
localparam [2:0] RXPI_CFG6_REG = RXPI_CFG6;
localparam [0:0] RXPI_LPM_REG = RXPI_LPM;
localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL;
localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
localparam [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF;
localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
localparam [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
localparam [1:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL;
localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
localparam [0:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM;
localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM;
localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST;
localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT;
localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE;
localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST;
localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT;
localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE;
localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
localparam [2:0] SIM_CPLLREFCLK_SEL_REG = SIM_CPLLREFCLK_SEL;
localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
localparam [3:0] TEMPERATUR_PAR_REG = TEMPERATUR_PAR;
localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
localparam [7:0] TST_RSV0_REG = TST_RSV0;
localparam [7:0] TST_RSV1_REG = TST_RSV1;
localparam [40:1] TXBUF_EN_REG = TXBUF_EN;
localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG;
localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
localparam [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N;
localparam [3:0] TXDRVBIAS_P_REG = TXDRVBIAS_P;
localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
localparam [4:0] TXOUT_DIV_REG = TXOUT_DIV;
localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
localparam [15:0] TXPH_CFG_REG = TXPH_CFG;
localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0;
localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1;
localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2;
localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3;
localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4;
localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5;
localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
localparam [0:0] TXPI_LPM_REG = TXPI_LPM;
localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG;
localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN;
localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE;
localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL;
localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
localparam [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN;
localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
localparam [1:0] WB_MODE_REG = WB_MODE;
`endif
localparam [0:0] AEN_CPLL_REG = 1'b0;
localparam [0:0] AEN_EYESCAN_REG = 1'b1;
localparam [0:0] AEN_LOOPBACK_REG = 1'b0;
localparam [0:0] AEN_MASTER_REG = 1'b0;
localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
localparam [0:0] AEN_POLARITY_REG = 1'b0;
localparam [0:0] AEN_PRBS_REG = 1'b0;
localparam [0:0] AEN_QPI_REG = 1'b0;
localparam [0:0] AEN_RESET_REG = 1'b0;
localparam [0:0] AEN_RXCDR_REG = 1'b0;
localparam [0:0] AEN_RXDFE_REG = 1'b0;
localparam [0:0] AEN_RXDFELPM_REG = 1'b0;
localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXPHDLY_REG = 1'b0;
localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXPHDLY_REG = 1'b0;
localparam [0:0] AEN_TXPI_PPM_REG = 1'b0;
localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
localparam [15:0] AMONITOR_CFG_REG = 16'h0000;
localparam [0:0] A_AFECFOKEN_REG = 1'b0;
localparam [0:0] A_CPLLLOCKEN_REG = 1'b0;
localparam [0:0] A_CPLLPD_REG = 1'b0;
localparam [0:0] A_CPLLRESET_REG = 1'b0;
localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000;
localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000;
localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0;
localparam [0:0] A_DFECFOKHOLD_REG = 1'b0;
localparam [0:0] A_DFECFOKOVREN_REG = 1'b0;
localparam [0:0] A_EYESCANMODE_REG = 1'b0;
localparam [0:0] A_EYESCANRESET_REG = 1'b0;
localparam [0:0] A_GTRESETSEL_REG = 1'b0;
localparam [0:0] A_GTRXRESET_REG = 1'b0;
localparam [0:0] A_GTTXRESET_REG = 1'b0;
localparam [80:1] A_LOOPBACK_REG = "NoLoopBack";
localparam [0:0] A_LPMGCHOLD_REG = 1'b0;
localparam [0:0] A_LPMGCOVREN_REG = 1'b0;
localparam [0:0] A_LPMOSHOLD_REG = 1'b0;
localparam [0:0] A_LPMOSOVREN_REG = 1'b0;
localparam [0:0] A_RXBUFRESET_REG = 1'b0;
localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0;
localparam [0:0] A_RXCDRHOLD_REG = 1'b0;
localparam [0:0] A_RXCDROVRDEN_REG = 1'b0;
localparam [0:0] A_RXCDRRESET_REG = 1'b0;
localparam [1:0] A_RXDFEAGCCTRL_REG = 2'b00;
localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0;
localparam [0:0] A_RXDFELFHOLD_REG = 1'b0;
localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFELPMRESET_REG = 1'b0;
localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVSEN_REG = 1'b0;
localparam [0:0] A_RXDFEXYDEN_REG = 1'b0;
localparam [0:0] A_RXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_RXDLYEN_REG = 1'b0;
localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDLYSRESET_REG = 1'b0;
localparam [0:0] A_RXLPMEN_REG = 1'b0;
localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
localparam [1:0] A_RXMONITORSEL_REG = 2'b00;
localparam [0:0] A_RXOOBRESET_REG = 1'b0;
localparam [0:0] A_RXOSHOLD_REG = 1'b0;
localparam [0:0] A_RXOSOVRDEN_REG = 1'b0;
localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_RXPCSRESET_REG = 1'b0;
localparam [24:1] A_RXPD_REG = "P0";
localparam [0:0] A_RXPHALIGN_REG = 1'b0;
localparam [0:0] A_RXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_RXPHDLYPD_REG = 1'b0;
localparam [0:0] A_RXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_RXPHOVRDEN_REG = 1'b0;
localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_RXPMARESET_REG = 1'b0;
localparam [0:0] A_RXPOLARITY_REG = 1'b0;
localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
localparam [48:1] A_RXPRBSSEL_REG = "PRBS7";
localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
localparam [0:0] A_TXDEEMPH_REG = 1'b0;
localparam [3:0] A_TXDIFFCTRL_REG = 4'b1100;
localparam [0:0] A_TXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_TXDLYEN_REG = 1'b0;
localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_TXDLYSRESET_REG = 1'b0;
localparam [0:0] A_TXELECIDLE_REG = 1'b0;
localparam [0:0] A_TXINHIBIT_REG = 1'b0;
localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
localparam [2:0] A_TXMARGIN_REG = 3'b000;
localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_TXPCSRESET_REG = 1'b0;
localparam [24:1] A_TXPD_REG = "P0";
localparam [0:0] A_TXPHALIGN_REG = 1'b0;
localparam [0:0] A_TXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_TXPHDLYPD_REG = 1'b0;
localparam [0:0] A_TXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_TXPHINIT_REG = 1'b0;
localparam [0:0] A_TXPHOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMPD_REG = 1'b0;
localparam [0:0] A_TXPIPPMSEL_REG = 1'b0;
localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_TXPMARESET_REG = 1'b0;
localparam [0:0] A_TXPOLARITY_REG = 1'b0;
localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
localparam [0:0] A_TXPOSTCURSORINV_REG = 1'b0;
localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
localparam [96:1] A_TXPRBSSEL_REG = "PRBS7";
localparam [4:0] A_TXPRECURSOR_REG = 5'b00000;
localparam [0:0] A_TXPRECURSORINV_REG = 1'b0;
localparam [0:0] A_TXQPIBIASEN_REG = 1'b0;
localparam [0:0] A_TXSWING_REG = 1'b0;
localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [0:0] CPLL_IPS_EN_REG = 1'b1;
localparam [2:0] CPLL_IPS_REFCLK_SEL_REG = 3'b000;
localparam [40:1] GEN_RXUSRCLK_REG = "TRUE";
localparam [40:1] GEN_TXUSRCLK_REG = "TRUE";
localparam [0:0] GT_INSTANTIATED_REG = 1'b1;
localparam [40:1] RXPLL_SEL_REG = "CPLL";
reg [63:0] RX_PROGDIV_CFG_INT = RX_PROGDIV_CFG * 1000;
localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
reg [63:0] TX_PROGDIV_CFG_INT = TX_PROGDIV_CFG * 1000;
localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTHE3_CHANNEL_dr.v"
`endif
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTHTXN_out;
wire GTHTXP_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXQPISENN_out;
wire RXQPISENP_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXQPISENN_out;
wire TXQPISENP_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [11:0] PCSRSVDOUT_out;
wire [11:0] PMASCANOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DRPDO_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [16:0] DMONITOROUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTCE_out;
wire [2:0] BUFGTRESET_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [6:0] RXMONITOROUT_out;
wire [7:0] PINRSRVDAS_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [8:0] BUFGTDIV_out;
wire CPLLFBCLKLOST_delay;
wire CPLLLOCK_delay;
wire CPLLREFCLKLOST_delay;
wire DRPRDY_delay;
wire EYESCANDATAERROR_delay;
wire GTHTXN_delay;
wire GTHTXP_delay;
wire GTPOWERGOOD_delay;
wire GTREFCLKMONITOR_delay;
wire PCIERATEGEN3_delay;
wire PCIERATEIDLE_delay;
wire PCIESYNCTXSYNCDONE_delay;
wire PCIEUSERGEN3RDY_delay;
wire PCIEUSERPHYSTATUSRST_delay;
wire PCIEUSERRATESTART_delay;
wire PHYSTATUS_delay;
wire RESETEXCEPTION_delay;
wire RXBYTEISALIGNED_delay;
wire RXBYTEREALIGN_delay;
wire RXCDRLOCK_delay;
wire RXCDRPHDONE_delay;
wire RXCHANBONDSEQ_delay;
wire RXCHANISALIGNED_delay;
wire RXCHANREALIGN_delay;
wire RXCOMINITDET_delay;
wire RXCOMMADET_delay;
wire RXCOMSASDET_delay;
wire RXCOMWAKEDET_delay;
wire RXDLYSRESETDONE_delay;
wire RXELECIDLE_delay;
wire RXOSINTDONE_delay;
wire RXOSINTSTARTED_delay;
wire RXOSINTSTROBEDONE_delay;
wire RXOSINTSTROBESTARTED_delay;
wire RXOUTCLKFABRIC_delay;
wire RXOUTCLKPCS_delay;
wire RXOUTCLK_delay;
wire RXPHALIGNDONE_delay;
wire RXPHALIGNERR_delay;
wire RXPMARESETDONE_delay;
wire RXPRBSERR_delay;
wire RXPRBSLOCKED_delay;
wire RXPRGDIVRESETDONE_delay;
wire RXQPISENN_delay;
wire RXQPISENP_delay;
wire RXRATEDONE_delay;
wire RXRECCLKOUT_delay;
wire RXRESETDONE_delay;
wire RXSLIDERDY_delay;
wire RXSLIPDONE_delay;
wire RXSLIPOUTCLKRDY_delay;
wire RXSLIPPMARDY_delay;
wire RXSYNCDONE_delay;
wire RXSYNCOUT_delay;
wire RXVALID_delay;
wire TXCOMFINISH_delay;
wire TXDLYSRESETDONE_delay;
wire TXOUTCLKFABRIC_delay;
wire TXOUTCLKPCS_delay;
wire TXOUTCLK_delay;
wire TXPHALIGNDONE_delay;
wire TXPHINITDONE_delay;
wire TXPMARESETDONE_delay;
wire TXPRGDIVRESETDONE_delay;
wire TXQPISENN_delay;
wire TXQPISENP_delay;
wire TXRATEDONE_delay;
wire TXRESETDONE_delay;
wire TXSYNCDONE_delay;
wire TXSYNCOUT_delay;
wire [11:0] PCSRSVDOUT_delay;
wire [127:0] RXDATA_delay;
wire [15:0] DRPDO_delay;
wire [15:0] RXCTRL0_delay;
wire [15:0] RXCTRL1_delay;
wire [16:0] DMONITOROUT_delay;
wire [1:0] PCIERATEQPLLPD_delay;
wire [1:0] PCIERATEQPLLRESET_delay;
wire [1:0] RXCLKCORCNT_delay;
wire [1:0] RXDATAVALID_delay;
wire [1:0] RXHEADERVALID_delay;
wire [1:0] RXSTARTOFSEQ_delay;
wire [1:0] TXBUFSTATUS_delay;
wire [2:0] BUFGTCEMASK_delay;
wire [2:0] BUFGTCE_delay;
wire [2:0] BUFGTRESET_delay;
wire [2:0] BUFGTRSTMASK_delay;
wire [2:0] RXBUFSTATUS_delay;
wire [2:0] RXSTATUS_delay;
wire [4:0] RXCHBONDO_delay;
wire [5:0] RXHEADER_delay;
wire [6:0] RXMONITOROUT_delay;
wire [7:0] PINRSRVDAS_delay;
wire [7:0] RXCTRL2_delay;
wire [7:0] RXCTRL3_delay;
wire [7:0] RXDATAEXTENDRSVD_delay;
wire [8:0] BUFGTDIV_delay;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire EVODDPHICALDONE_in;
wire EVODDPHICALSTART_in;
wire EVODDPHIDRDEN_in;
wire EVODDPHIDWREN_in;
wire EVODDPHIXRDEN_in;
wire EVODDPHIXWREN_in;
wire EYESCANMODE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire GTGREFCLK_in;
wire GTHRXN_in;
wire GTHRXP_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESET_in;
wire LPBKRXTXSEREN_in;
wire LPBKTXRXSEREN_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RSTCLKENTX_in;
wire RX8B10BEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESETRSV_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCOMMADETEN_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEVSEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSINTEN_in;
wire RXOSINTHOLD_in;
wire RXOSINTOVRDEN_in;
wire RXOSINTSTROBE_in;
wire RXOSINTTESTOVRDEN_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXQPIEN_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDEEMPH_in;
wire TXDETECTRX_in;
wire TXDIFFPD_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPOSTCURSORINV_in;
wire TXPRBSFORCEERR_in;
wire TXPRECURSORINV_in;
wire TXPROGDIVRESET_in;
wire TXQPIBIASEN_in;
wire TXQPISTRONGPDOWN_in;
wire TXQPIWEAKPUP_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [11:0] PMASCANIN_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXDFEAGCCTRL_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXBUFDIFFCTRL_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXOSINTCFG_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXDIFFCTRL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] PCSRSVDIN2_in;
wire [4:0] PMARSVDIN_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [8:0] DRPADDR_in;
wire CFGRESET_delay;
wire CLKRSVD0_delay;
wire CLKRSVD1_delay;
wire CPLLLOCKDETCLK_delay;
wire CPLLLOCKEN_delay;
wire CPLLPD_delay;
wire CPLLRESET_delay;
wire DMONFIFORESET_delay;
wire DMONITORCLK_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire EVODDPHICALDONE_delay;
wire EVODDPHICALSTART_delay;
wire EVODDPHIDRDEN_delay;
wire EVODDPHIDWREN_delay;
wire EVODDPHIXRDEN_delay;
wire EVODDPHIXWREN_delay;
wire EYESCANMODE_delay;
wire EYESCANRESET_delay;
wire EYESCANTRIGGER_delay;
wire GTGREFCLK_delay;
wire GTHRXN_delay;
wire GTHRXP_delay;
wire GTNORTHREFCLK0_delay;
wire GTNORTHREFCLK1_delay;
wire GTREFCLK0_delay;
wire GTREFCLK1_delay;
wire GTRESETSEL_delay;
wire GTRXRESET_delay;
wire GTSOUTHREFCLK0_delay;
wire GTSOUTHREFCLK1_delay;
wire GTTXRESET_delay;
wire LPBKRXTXSEREN_delay;
wire LPBKTXRXSEREN_delay;
wire PCIEEQRXEQADAPTDONE_delay;
wire PCIERSTIDLE_delay;
wire PCIERSTTXSYNCSTART_delay;
wire PCIEUSERRATEDONE_delay;
wire QPLL0CLK_delay;
wire QPLL0REFCLK_delay;
wire QPLL1CLK_delay;
wire QPLL1REFCLK_delay;
wire RESETOVRD_delay;
wire RSTCLKENTX_delay;
wire RX8B10BEN_delay;
wire RXBUFRESET_delay;
wire RXCDRFREQRESET_delay;
wire RXCDRHOLD_delay;
wire RXCDROVRDEN_delay;
wire RXCDRRESETRSV_delay;
wire RXCDRRESET_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCOMMADETEN_delay;
wire RXDFEAGCHOLD_delay;
wire RXDFEAGCOVRDEN_delay;
wire RXDFELFHOLD_delay;
wire RXDFELFOVRDEN_delay;
wire RXDFELPMRESET_delay;
wire RXDFETAP10HOLD_delay;
wire RXDFETAP10OVRDEN_delay;
wire RXDFETAP11HOLD_delay;
wire RXDFETAP11OVRDEN_delay;
wire RXDFETAP12HOLD_delay;
wire RXDFETAP12OVRDEN_delay;
wire RXDFETAP13HOLD_delay;
wire RXDFETAP13OVRDEN_delay;
wire RXDFETAP14HOLD_delay;
wire RXDFETAP14OVRDEN_delay;
wire RXDFETAP15HOLD_delay;
wire RXDFETAP15OVRDEN_delay;
wire RXDFETAP2HOLD_delay;
wire RXDFETAP2OVRDEN_delay;
wire RXDFETAP3HOLD_delay;
wire RXDFETAP3OVRDEN_delay;
wire RXDFETAP4HOLD_delay;
wire RXDFETAP4OVRDEN_delay;
wire RXDFETAP5HOLD_delay;
wire RXDFETAP5OVRDEN_delay;
wire RXDFETAP6HOLD_delay;
wire RXDFETAP6OVRDEN_delay;
wire RXDFETAP7HOLD_delay;
wire RXDFETAP7OVRDEN_delay;
wire RXDFETAP8HOLD_delay;
wire RXDFETAP8OVRDEN_delay;
wire RXDFETAP9HOLD_delay;
wire RXDFETAP9OVRDEN_delay;
wire RXDFEUTHOLD_delay;
wire RXDFEUTOVRDEN_delay;
wire RXDFEVPHOLD_delay;
wire RXDFEVPOVRDEN_delay;
wire RXDFEVSEN_delay;
wire RXDFEXYDEN_delay;
wire RXDLYBYPASS_delay;
wire RXDLYEN_delay;
wire RXDLYOVRDEN_delay;
wire RXDLYSRESET_delay;
wire RXGEARBOXSLIP_delay;
wire RXLATCLK_delay;
wire RXLPMEN_delay;
wire RXLPMGCHOLD_delay;
wire RXLPMGCOVRDEN_delay;
wire RXLPMHFHOLD_delay;
wire RXLPMHFOVRDEN_delay;
wire RXLPMLFHOLD_delay;
wire RXLPMLFKLOVRDEN_delay;
wire RXLPMOSHOLD_delay;
wire RXLPMOSOVRDEN_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXOOBRESET_delay;
wire RXOSCALRESET_delay;
wire RXOSHOLD_delay;
wire RXOSINTEN_delay;
wire RXOSINTHOLD_delay;
wire RXOSINTOVRDEN_delay;
wire RXOSINTSTROBE_delay;
wire RXOSINTTESTOVRDEN_delay;
wire RXOSOVRDEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPCSRESET_delay;
wire RXPHALIGNEN_delay;
wire RXPHALIGN_delay;
wire RXPHDLYPD_delay;
wire RXPHDLYRESET_delay;
wire RXPHOVRDEN_delay;
wire RXPMARESET_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXPROGDIVRESET_delay;
wire RXQPIEN_delay;
wire RXRATEMODE_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXSYNCALLIN_delay;
wire RXSYNCIN_delay;
wire RXSYNCMODE_delay;
wire RXUSERRDY_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire SIGVALIDCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDEEMPH_delay;
wire TXDETECTRX_delay;
wire TXDIFFPD_delay;
wire TXDLYBYPASS_delay;
wire TXDLYEN_delay;
wire TXDLYHOLD_delay;
wire TXDLYOVRDEN_delay;
wire TXDLYSRESET_delay;
wire TXDLYUPDOWN_delay;
wire TXELECIDLE_delay;
wire TXINHIBIT_delay;
wire TXLATCLK_delay;
wire TXPCSRESET_delay;
wire TXPDELECIDLEMODE_delay;
wire TXPHALIGNEN_delay;
wire TXPHALIGN_delay;
wire TXPHDLYPD_delay;
wire TXPHDLYRESET_delay;
wire TXPHDLYTSTCLK_delay;
wire TXPHINIT_delay;
wire TXPHOVRDEN_delay;
wire TXPIPPMEN_delay;
wire TXPIPPMOVRDEN_delay;
wire TXPIPPMPD_delay;
wire TXPIPPMSEL_delay;
wire TXPISOPD_delay;
wire TXPMARESET_delay;
wire TXPOLARITY_delay;
wire TXPOSTCURSORINV_delay;
wire TXPRBSFORCEERR_delay;
wire TXPRECURSORINV_delay;
wire TXPROGDIVRESET_delay;
wire TXQPIBIASEN_delay;
wire TXQPISTRONGPDOWN_delay;
wire TXQPIWEAKPUP_delay;
wire TXRATEMODE_delay;
wire TXSWING_delay;
wire TXSYNCALLIN_delay;
wire TXSYNCIN_delay;
wire TXSYNCMODE_delay;
wire TXUSERRDY_delay;
wire TXUSRCLK2_delay;
wire TXUSRCLK_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] GTRSVD_delay;
wire [15:0] PCSRSVDIN_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [19:0] TSTIN_delay;
wire [1:0] RXDFEAGCCTRL_delay;
wire [1:0] RXELECIDLEMODE_delay;
wire [1:0] RXMONITORSEL_delay;
wire [1:0] RXPD_delay;
wire [1:0] RXPLLCLKSEL_delay;
wire [1:0] RXSYSCLKSEL_delay;
wire [1:0] TXPD_delay;
wire [1:0] TXPLLCLKSEL_delay;
wire [1:0] TXSYSCLKSEL_delay;
wire [2:0] CPLLREFCLKSEL_delay;
wire [2:0] LOOPBACK_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXOUTCLKSEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXBUFDIFFCTRL_delay;
wire [2:0] TXMARGIN_delay;
wire [2:0] TXOUTCLKSEL_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXOSINTCFG_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXDIFFCTRL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] PCSRSVDIN2_delay;
wire [4:0] PMARSVDIN_delay;
wire [4:0] RXCHBONDI_delay;
wire [4:0] TXPIPPMSTEPSIZE_delay;
wire [4:0] TXPOSTCURSOR_delay;
wire [4:0] TXPRECURSOR_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXMAINCURSOR_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [7:0] TXDATAEXTENDRSVD_delay;
wire [8:0] DRPADDR_delay;
assign #(out_delay) BUFGTCE = BUFGTCE_delay;
assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay;
assign #(out_delay) BUFGTDIV = BUFGTDIV_delay;
assign #(out_delay) BUFGTRESET = BUFGTRESET_delay;
assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay;
assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay;
assign #(out_delay) CPLLLOCK = CPLLLOCK_delay;
assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay;
assign #(out_delay) DMONITOROUT = DMONITOROUT_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay;
assign #(out_delay) GTHTXN = GTHTXN_delay;
assign #(out_delay) GTHTXP = GTHTXP_delay;
assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay;
assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay;
assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay;
assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay;
assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay;
assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay;
assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay;
assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay;
assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay;
assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay;
assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay;
assign #(out_delay) PHYSTATUS = PHYSTATUS_delay;
assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay;
assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay;
assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay;
assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay;
assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay;
assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay;
assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay;
assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay;
assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay;
assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay;
assign #(out_delay) RXCHBONDO = RXCHBONDO_delay;
assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay;
assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay;
assign #(out_delay) RXCOMMADET = RXCOMMADET_delay;
assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay;
assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay;
assign #(out_delay) RXCTRL0 = RXCTRL0_delay;
assign #(out_delay) RXCTRL1 = RXCTRL1_delay;
assign #(out_delay) RXCTRL2 = RXCTRL2_delay;
assign #(out_delay) RXCTRL3 = RXCTRL3_delay;
assign #(out_delay) RXDATA = RXDATA_delay;
assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay;
assign #(out_delay) RXDATAVALID = RXDATAVALID_delay;
assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay;
assign #(out_delay) RXELECIDLE = RXELECIDLE_delay;
assign #(out_delay) RXHEADER = RXHEADER_delay;
assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay;
assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay;
assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay;
assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay;
assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay;
assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay;
assign #(out_delay) RXOUTCLK = RXOUTCLK_delay;
assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay;
assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay;
assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay;
assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay;
assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay;
assign #(out_delay) RXPRBSERR = RXPRBSERR_delay;
assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay;
assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay;
assign #(out_delay) RXQPISENN = RXQPISENN_delay;
assign #(out_delay) RXQPISENP = RXQPISENP_delay;
assign #(out_delay) RXRATEDONE = RXRATEDONE_delay;
assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay;
assign #(out_delay) RXRESETDONE = RXRESETDONE_delay;
assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay;
assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay;
assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay;
assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay;
assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay;
assign #(out_delay) RXSTATUS = RXSTATUS_delay;
assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay;
assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay;
assign #(out_delay) RXVALID = RXVALID_delay;
assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay;
assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay;
assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay;
assign #(out_delay) TXOUTCLK = TXOUTCLK_delay;
assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay;
assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay;
assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay;
assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay;
assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay;
assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay;
assign #(out_delay) TXQPISENN = TXQPISENN_delay;
assign #(out_delay) TXQPISENP = TXQPISENP_delay;
assign #(out_delay) TXRATEDONE = TXRATEDONE_delay;
assign #(out_delay) TXRESETDONE = TXRESETDONE_delay;
assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay;
assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2;
assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) RX8B10BEN_delay = RX8B10BEN;
assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN;
assign #(in_delay) RXCHBONDI_delay = RXCHBONDI;
assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL;
assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER;
assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE;
assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN;
assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP;
assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN;
assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN;
assign #(in_delay) RXPOLARITY_delay = RXPOLARITY;
assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET;
assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL;
assign #(in_delay) RXRATE_delay = RXRATE;
assign #(in_delay) RXSLIDE_delay = RXSLIDE;
assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK;
assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA;
assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS;
assign #(in_delay) TX8B10BEN_delay = TX8B10BEN;
assign #(in_delay) TXCOMINIT_delay = TXCOMINIT;
assign #(in_delay) TXCOMSAS_delay = TXCOMSAS;
assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE;
assign #(in_delay) TXCTRL0_delay = TXCTRL0;
assign #(in_delay) TXCTRL1_delay = TXCTRL1;
assign #(in_delay) TXCTRL2_delay = TXCTRL2;
assign #(in_delay) TXDATA_delay = TXDATA;
assign #(in_delay) TXDETECTRX_delay = TXDETECTRX;
assign #(in_delay) TXELECIDLE_delay = TXELECIDLE;
assign #(in_delay) TXHEADER_delay = TXHEADER;
assign #(in_delay) TXINHIBIT_delay = TXINHIBIT;
assign #(in_delay) TXPD_delay = TXPD;
assign #(in_delay) TXPOLARITY_delay = TXPOLARITY;
assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR;
assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL;
assign #(in_delay) TXRATE_delay = TXRATE;
assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0;
assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1;
assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK;
assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK;
assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK;
assign #(inclk_delay) RXLATCLK_delay = RXLATCLK;
assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK;
assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK;
assign #(inclk_delay) TXLATCLK_delay = TXLATCLK;
assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK;
assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK;
assign #(in_delay) CFGRESET_delay = CFGRESET;
assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN;
assign #(in_delay) CPLLPD_delay = CPLLPD;
assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL;
assign #(in_delay) CPLLRESET_delay = CPLLRESET;
assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET;
assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE;
assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART;
assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN;
assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN;
assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN;
assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN;
assign #(in_delay) EYESCANMODE_delay = EYESCANMODE;
assign #(in_delay) EYESCANRESET_delay = EYESCANRESET;
assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER;
assign #(in_delay) GTHRXN_delay = GTHRXN;
assign #(in_delay) GTHRXP_delay = GTHRXP;
assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0;
assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1;
assign #(in_delay) GTREFCLK0_delay = GTREFCLK0;
assign #(in_delay) GTREFCLK1_delay = GTREFCLK1;
assign #(in_delay) GTRESETSEL_delay = GTRESETSEL;
assign #(in_delay) GTRSVD_delay = GTRSVD;
assign #(in_delay) GTRXRESET_delay = GTRXRESET;
assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0;
assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1;
assign #(in_delay) GTTXRESET_delay = GTTXRESET;
assign #(in_delay) LOOPBACK_delay = LOOPBACK;
assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN;
assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN;
assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE;
assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE;
assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART;
assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE;
assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2;
assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN;
assign #(in_delay) PMARSVDIN_delay = PMARSVDIN;
assign #(in_delay) QPLL0CLK_delay = QPLL0CLK;
assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK;
assign #(in_delay) QPLL1CLK_delay = QPLL1CLK;
assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK;
assign #(in_delay) RESETOVRD_delay = RESETOVRD;
assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX;
assign #(in_delay) RXBUFRESET_delay = RXBUFRESET;
assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET;
assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD;
assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN;
assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV;
assign #(in_delay) RXCDRRESET_delay = RXCDRRESET;
assign #(in_delay) RXDFEAGCCTRL_delay = RXDFEAGCCTRL;
assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD;
assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN;
assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD;
assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN;
assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET;
assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD;
assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN;
assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD;
assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN;
assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD;
assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN;
assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD;
assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN;
assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD;
assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN;
assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD;
assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN;
assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD;
assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN;
assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD;
assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN;
assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD;
assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN;
assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD;
assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN;
assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD;
assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN;
assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD;
assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN;
assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD;
assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN;
assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD;
assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN;
assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD;
assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN;
assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD;
assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN;
assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN;
assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN;
assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS;
assign #(in_delay) RXDLYEN_delay = RXDLYEN;
assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN;
assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET;
assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE;
assign #(in_delay) RXLPMEN_delay = RXLPMEN;
assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD;
assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN;
assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD;
assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN;
assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD;
assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN;
assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD;
assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN;
assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL;
assign #(in_delay) RXOOBRESET_delay = RXOOBRESET;
assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET;
assign #(in_delay) RXOSHOLD_delay = RXOSHOLD;
assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG;
assign #(in_delay) RXOSINTEN_delay = RXOSINTEN;
assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD;
assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN;
assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE;
assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN;
assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN;
assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL;
assign #(in_delay) RXPCSRESET_delay = RXPCSRESET;
assign #(in_delay) RXPD_delay = RXPD;
assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN;
assign #(in_delay) RXPHALIGN_delay = RXPHALIGN;
assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD;
assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET;
assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN;
assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL;
assign #(in_delay) RXPMARESET_delay = RXPMARESET;
assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET;
assign #(in_delay) RXQPIEN_delay = RXQPIEN;
assign #(in_delay) RXRATEMODE_delay = RXRATEMODE;
assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN;
assign #(in_delay) RXSYNCIN_delay = RXSYNCIN;
assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE;
assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL;
assign #(in_delay) RXUSERRDY_delay = RXUSERRDY;
assign #(in_delay) TSTIN_delay = TSTIN;
assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL;
assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD;
assign #(in_delay) TXDEEMPH_delay = TXDEEMPH;
assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL;
assign #(in_delay) TXDIFFPD_delay = TXDIFFPD;
assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS;
assign #(in_delay) TXDLYEN_delay = TXDLYEN;
assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD;
assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN;
assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET;
assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN;
assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR;
assign #(in_delay) TXMARGIN_delay = TXMARGIN;
assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL;
assign #(in_delay) TXPCSRESET_delay = TXPCSRESET;
assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE;
assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN;
assign #(in_delay) TXPHALIGN_delay = TXPHALIGN;
assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD;
assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET;
assign #(in_delay) TXPHINIT_delay = TXPHINIT;
assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN;
assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN;
assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN;
assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD;
assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL;
assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE;
assign #(in_delay) TXPISOPD_delay = TXPISOPD;
assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL;
assign #(in_delay) TXPMARESET_delay = TXPMARESET;
assign #(in_delay) TXPOSTCURSORINV_delay = TXPOSTCURSORINV;
assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR;
assign #(in_delay) TXPRECURSORINV_delay = TXPRECURSORINV;
assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR;
assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET;
assign #(in_delay) TXQPIBIASEN_delay = TXQPIBIASEN;
assign #(in_delay) TXQPISTRONGPDOWN_delay = TXQPISTRONGPDOWN;
assign #(in_delay) TXQPIWEAKPUP_delay = TXQPIWEAKPUP;
assign #(in_delay) TXRATEMODE_delay = TXRATEMODE;
assign #(in_delay) TXSWING_delay = TXSWING;
assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN;
assign #(in_delay) TXSYNCIN_delay = TXSYNCIN;
assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE;
assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL;
assign #(in_delay) TXUSERRDY_delay = TXUSERRDY;
assign BUFGTCEMASK_delay = BUFGTCEMASK_out;
assign BUFGTCE_delay = BUFGTCE_out;
assign BUFGTDIV_delay = BUFGTDIV_out;
assign BUFGTRESET_delay = BUFGTRESET_out;
assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out;
assign CPLLLOCK_delay = CPLLLOCK_out;
assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out;
assign DMONITOROUT_delay = DMONITOROUT_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out;
assign GTHTXN_delay = GTHTXN_out;
assign GTHTXP_delay = GTHTXP_out;
assign GTPOWERGOOD_delay = GTPOWERGOOD_out;
assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out;
assign PCIERATEGEN3_delay = PCIERATEGEN3_out;
assign PCIERATEIDLE_delay = PCIERATEIDLE_out;
assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out;
assign PCSRSVDOUT_delay = PCSRSVDOUT_out;
assign PHYSTATUS_delay = PHYSTATUS_out;
assign PINRSRVDAS_delay = PINRSRVDAS_out;
assign RESETEXCEPTION_delay = RESETEXCEPTION_out;
assign RXBUFSTATUS_delay = RXBUFSTATUS_out;
assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out;
assign RXCDRLOCK_delay = RXCDRLOCK_out;
assign RXCDRPHDONE_delay = RXCDRPHDONE_out;
assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out;
assign RXCHANREALIGN_delay = RXCHANREALIGN_out;
assign RXCHBONDO_delay = RXCHBONDO_out;
assign RXCLKCORCNT_delay = RXCLKCORCNT_out;
assign RXCOMINITDET_delay = RXCOMINITDET_out;
assign RXCOMMADET_delay = RXCOMMADET_out;
assign RXCOMSASDET_delay = RXCOMSASDET_out;
assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out;
assign RXCTRL0_delay = RXCTRL0_out;
assign RXCTRL1_delay = RXCTRL1_out;
assign RXCTRL2_delay = RXCTRL2_out;
assign RXCTRL3_delay = RXCTRL3_out;
assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out;
assign RXDATAVALID_delay = RXDATAVALID_out;
assign RXDATA_delay = RXDATA_out;
assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out;
assign RXELECIDLE_delay = RXELECIDLE_out;
assign RXHEADERVALID_delay = RXHEADERVALID_out;
assign RXHEADER_delay = RXHEADER_out;
assign RXMONITOROUT_delay = RXMONITOROUT_out;
assign RXOSINTDONE_delay = RXOSINTDONE_out;
assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out;
assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out;
assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out;
assign RXOUTCLK_delay = RXOUTCLK_out;
assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out;
assign RXPHALIGNERR_delay = RXPHALIGNERR_out;
assign RXPMARESETDONE_delay = RXPMARESETDONE_out;
assign RXPRBSERR_delay = RXPRBSERR_out;
assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out;
assign RXQPISENN_delay = RXQPISENN_out;
assign RXQPISENP_delay = RXQPISENP_out;
assign RXRATEDONE_delay = RXRATEDONE_out;
assign RXRECCLKOUT_delay = RXRECCLKOUT_out;
assign RXRESETDONE_delay = RXRESETDONE_out;
assign RXSLIDERDY_delay = RXSLIDERDY_out;
assign RXSLIPDONE_delay = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out;
assign RXSTATUS_delay = RXSTATUS_out;
assign RXSYNCDONE_delay = RXSYNCDONE_out;
assign RXSYNCOUT_delay = RXSYNCOUT_out;
assign RXVALID_delay = RXVALID_out;
assign TXBUFSTATUS_delay = TXBUFSTATUS_out;
assign TXCOMFINISH_delay = TXCOMFINISH_out;
assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out;
assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out;
assign TXOUTCLK_delay = TXOUTCLK_out;
assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out;
assign TXPHINITDONE_delay = TXPHINITDONE_out;
assign TXPMARESETDONE_delay = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out;
assign TXQPISENN_delay = TXQPISENN_out;
assign TXQPISENP_delay = TXQPISENP_out;
assign TXRATEDONE_delay = TXRATEDONE_out;
assign TXRESETDONE_delay = TXRESETDONE_out;
assign TXSYNCDONE_delay = TXSYNCDONE_out;
assign TXSYNCOUT_delay = TXSYNCOUT_out;
assign CFGRESET_in = CFGRESET_delay;
assign CLKRSVD0_in = CLKRSVD0_delay;
assign CLKRSVD1_in = CLKRSVD1_delay;
assign CPLLLOCKDETCLK_in = CPLLLOCKDETCLK_delay;
assign CPLLLOCKEN_in = CPLLLOCKEN_delay;
assign CPLLPD_in = CPLLPD_delay;
assign CPLLREFCLKSEL_in = CPLLREFCLKSEL_delay;
assign CPLLRESET_in = CPLLRESET_delay;
assign DMONFIFORESET_in = DMONFIFORESET_delay;
assign DMONITORCLK_in = DMONITORCLK_delay;
assign DRPADDR_in = DRPADDR_delay;
assign DRPCLK_in = DRPCLK_delay;
assign DRPDI_in = DRPDI_delay;
assign DRPEN_in = DRPEN_delay;
assign DRPWE_in = DRPWE_delay;
assign EVODDPHICALDONE_in = EVODDPHICALDONE_delay;
assign EVODDPHICALSTART_in = EVODDPHICALSTART_delay;
assign EVODDPHIDRDEN_in = EVODDPHIDRDEN_delay;
assign EVODDPHIDWREN_in = EVODDPHIDWREN_delay;
assign EVODDPHIXRDEN_in = EVODDPHIXRDEN_delay;
assign EVODDPHIXWREN_in = EVODDPHIXWREN_delay;
assign EYESCANMODE_in = EYESCANMODE_delay;
assign EYESCANRESET_in = EYESCANRESET_delay;
assign EYESCANTRIGGER_in = EYESCANTRIGGER_delay;
assign GTGREFCLK_in = GTGREFCLK_delay;
assign GTHRXN_in = GTHRXN_delay;
assign GTHRXP_in = GTHRXP_delay;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay;
assign GTREFCLK0_in = GTREFCLK0_delay;
assign GTREFCLK1_in = GTREFCLK1_delay;
assign GTRESETSEL_in = GTRESETSEL_delay;
assign GTRSVD_in = GTRSVD_delay;
assign GTRXRESET_in = GTRXRESET_delay;
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay;
assign GTTXRESET_in = GTTXRESET_delay;
assign LOOPBACK_in = LOOPBACK_delay;
assign LPBKRXTXSEREN_in = LPBKRXTXSEREN_delay;
assign LPBKTXRXSEREN_in = LPBKTXRXSEREN_delay;
assign PCIEEQRXEQADAPTDONE_in = PCIEEQRXEQADAPTDONE_delay;
assign PCIERSTIDLE_in = PCIERSTIDLE_delay;
assign PCIERSTTXSYNCSTART_in = PCIERSTTXSYNCSTART_delay;
assign PCIEUSERRATEDONE_in = PCIEUSERRATEDONE_delay;
assign PCSRSVDIN2_in = PCSRSVDIN2_delay;
assign PCSRSVDIN_in = PCSRSVDIN_delay;
assign PMARSVDIN_in = PMARSVDIN_delay;
assign QPLL0CLK_in = QPLL0CLK_delay;
assign QPLL0REFCLK_in = QPLL0REFCLK_delay;
assign QPLL1CLK_in = QPLL1CLK_delay;
assign QPLL1REFCLK_in = QPLL1REFCLK_delay;
assign RESETOVRD_in = RESETOVRD_delay;
assign RSTCLKENTX_in = RSTCLKENTX_delay;
assign RX8B10BEN_in = RX8B10BEN_delay;
assign RXBUFRESET_in = RXBUFRESET_delay;
assign RXCDRFREQRESET_in = RXCDRFREQRESET_delay;
assign RXCDRHOLD_in = RXCDRHOLD_delay;
assign RXCDROVRDEN_in = RXCDROVRDEN_delay;
assign RXCDRRESETRSV_in = RXCDRRESETRSV_delay;
assign RXCDRRESET_in = RXCDRRESET_delay;
assign RXCHBONDEN_in = RXCHBONDEN_delay;
assign RXCHBONDI_in = RXCHBONDI_delay;
assign RXCHBONDLEVEL_in = RXCHBONDLEVEL_delay;
assign RXCHBONDMASTER_in = RXCHBONDMASTER_delay;
assign RXCHBONDSLAVE_in = RXCHBONDSLAVE_delay;
assign RXCOMMADETEN_in = RXCOMMADETEN_delay;
assign RXDFEAGCCTRL_in = RXDFEAGCCTRL_delay;
assign RXDFEAGCHOLD_in = RXDFEAGCHOLD_delay;
assign RXDFEAGCOVRDEN_in = RXDFEAGCOVRDEN_delay;
assign RXDFELFHOLD_in = RXDFELFHOLD_delay;
assign RXDFELFOVRDEN_in = RXDFELFOVRDEN_delay;
assign RXDFELPMRESET_in = RXDFELPMRESET_delay;
assign RXDFETAP10HOLD_in = RXDFETAP10HOLD_delay;
assign RXDFETAP10OVRDEN_in = RXDFETAP10OVRDEN_delay;
assign RXDFETAP11HOLD_in = RXDFETAP11HOLD_delay;
assign RXDFETAP11OVRDEN_in = RXDFETAP11OVRDEN_delay;
assign RXDFETAP12HOLD_in = RXDFETAP12HOLD_delay;
assign RXDFETAP12OVRDEN_in = RXDFETAP12OVRDEN_delay;
assign RXDFETAP13HOLD_in = RXDFETAP13HOLD_delay;
assign RXDFETAP13OVRDEN_in = RXDFETAP13OVRDEN_delay;
assign RXDFETAP14HOLD_in = RXDFETAP14HOLD_delay;
assign RXDFETAP14OVRDEN_in = RXDFETAP14OVRDEN_delay;
assign RXDFETAP15HOLD_in = RXDFETAP15HOLD_delay;
assign RXDFETAP15OVRDEN_in = RXDFETAP15OVRDEN_delay;
assign RXDFETAP2HOLD_in = RXDFETAP2HOLD_delay;
assign RXDFETAP2OVRDEN_in = RXDFETAP2OVRDEN_delay;
assign RXDFETAP3HOLD_in = RXDFETAP3HOLD_delay;
assign RXDFETAP3OVRDEN_in = RXDFETAP3OVRDEN_delay;
assign RXDFETAP4HOLD_in = RXDFETAP4HOLD_delay;
assign RXDFETAP4OVRDEN_in = RXDFETAP4OVRDEN_delay;
assign RXDFETAP5HOLD_in = RXDFETAP5HOLD_delay;
assign RXDFETAP5OVRDEN_in = RXDFETAP5OVRDEN_delay;
assign RXDFETAP6HOLD_in = RXDFETAP6HOLD_delay;
assign RXDFETAP6OVRDEN_in = RXDFETAP6OVRDEN_delay;
assign RXDFETAP7HOLD_in = RXDFETAP7HOLD_delay;
assign RXDFETAP7OVRDEN_in = RXDFETAP7OVRDEN_delay;
assign RXDFETAP8HOLD_in = RXDFETAP8HOLD_delay;
assign RXDFETAP8OVRDEN_in = RXDFETAP8OVRDEN_delay;
assign RXDFETAP9HOLD_in = RXDFETAP9HOLD_delay;
assign RXDFETAP9OVRDEN_in = RXDFETAP9OVRDEN_delay;
assign RXDFEUTHOLD_in = RXDFEUTHOLD_delay;
assign RXDFEUTOVRDEN_in = RXDFEUTOVRDEN_delay;
assign RXDFEVPHOLD_in = RXDFEVPHOLD_delay;
assign RXDFEVPOVRDEN_in = RXDFEVPOVRDEN_delay;
assign RXDFEVSEN_in = RXDFEVSEN_delay;
assign RXDFEXYDEN_in = RXDFEXYDEN_delay;
assign RXDLYBYPASS_in = RXDLYBYPASS_delay;
assign RXDLYEN_in = RXDLYEN_delay;
assign RXDLYOVRDEN_in = RXDLYOVRDEN_delay;
assign RXDLYSRESET_in = RXDLYSRESET_delay;
assign RXELECIDLEMODE_in = RXELECIDLEMODE_delay;
assign RXGEARBOXSLIP_in = RXGEARBOXSLIP_delay;
assign RXLATCLK_in = RXLATCLK_delay;
assign RXLPMEN_in = RXLPMEN_delay;
assign RXLPMGCHOLD_in = RXLPMGCHOLD_delay;
assign RXLPMGCOVRDEN_in = RXLPMGCOVRDEN_delay;
assign RXLPMHFHOLD_in = RXLPMHFHOLD_delay;
assign RXLPMHFOVRDEN_in = RXLPMHFOVRDEN_delay;
assign RXLPMLFHOLD_in = RXLPMLFHOLD_delay;
assign RXLPMLFKLOVRDEN_in = RXLPMLFKLOVRDEN_delay;
assign RXLPMOSHOLD_in = RXLPMOSHOLD_delay;
assign RXLPMOSOVRDEN_in = RXLPMOSOVRDEN_delay;
assign RXMCOMMAALIGNEN_in = RXMCOMMAALIGNEN_delay;
assign RXMONITORSEL_in = RXMONITORSEL_delay;
assign RXOOBRESET_in = RXOOBRESET_delay;
assign RXOSCALRESET_in = RXOSCALRESET_delay;
assign RXOSHOLD_in = RXOSHOLD_delay;
assign RXOSINTCFG_in = RXOSINTCFG_delay;
assign RXOSINTEN_in = RXOSINTEN_delay;
assign RXOSINTHOLD_in = RXOSINTHOLD_delay;
assign RXOSINTOVRDEN_in = RXOSINTOVRDEN_delay;
assign RXOSINTSTROBE_in = RXOSINTSTROBE_delay;
assign RXOSINTTESTOVRDEN_in = RXOSINTTESTOVRDEN_delay;
assign RXOSOVRDEN_in = RXOSOVRDEN_delay;
assign RXOUTCLKSEL_in = RXOUTCLKSEL_delay;
assign RXPCOMMAALIGNEN_in = RXPCOMMAALIGNEN_delay;
assign RXPCSRESET_in = RXPCSRESET_delay;
assign RXPD_in = RXPD_delay;
assign RXPHALIGNEN_in = RXPHALIGNEN_delay;
assign RXPHALIGN_in = RXPHALIGN_delay;
assign RXPHDLYPD_in = RXPHDLYPD_delay;
assign RXPHDLYRESET_in = RXPHDLYRESET_delay;
assign RXPHOVRDEN_in = RXPHOVRDEN_delay;
assign RXPLLCLKSEL_in = RXPLLCLKSEL_delay;
assign RXPMARESET_in = RXPMARESET_delay;
assign RXPOLARITY_in = RXPOLARITY_delay;
assign RXPRBSCNTRESET_in = RXPRBSCNTRESET_delay;
assign RXPRBSSEL_in = RXPRBSSEL_delay;
assign RXPROGDIVRESET_in = RXPROGDIVRESET_delay;
assign RXQPIEN_in = RXQPIEN_delay;
assign RXRATEMODE_in = RXRATEMODE_delay;
assign RXRATE_in = RXRATE_delay;
assign RXSLIDE_in = RXSLIDE_delay;
assign RXSLIPOUTCLK_in = RXSLIPOUTCLK_delay;
assign RXSLIPPMA_in = RXSLIPPMA_delay;
assign RXSYNCALLIN_in = RXSYNCALLIN_delay;
assign RXSYNCIN_in = RXSYNCIN_delay;
assign RXSYNCMODE_in = RXSYNCMODE_delay;
assign RXSYSCLKSEL_in = RXSYSCLKSEL_delay;
assign RXUSERRDY_in = RXUSERRDY_delay;
assign RXUSRCLK2_in = RXUSRCLK2_delay;
assign RXUSRCLK_in = RXUSRCLK_delay;
assign SIGVALIDCLK_in = SIGVALIDCLK_delay;
assign TSTIN_in = TSTIN_delay;
assign TX8B10BBYPASS_in = TX8B10BBYPASS_delay;
assign TX8B10BEN_in = TX8B10BEN_delay;
assign TXBUFDIFFCTRL_in = TXBUFDIFFCTRL_delay;
assign TXCOMINIT_in = TXCOMINIT_delay;
assign TXCOMSAS_in = TXCOMSAS_delay;
assign TXCOMWAKE_in = TXCOMWAKE_delay;
assign TXCTRL0_in = TXCTRL0_delay;
assign TXCTRL1_in = TXCTRL1_delay;
assign TXCTRL2_in = TXCTRL2_delay;
assign TXDATAEXTENDRSVD_in = TXDATAEXTENDRSVD_delay;
assign TXDATA_in = TXDATA_delay;
assign TXDEEMPH_in = TXDEEMPH_delay;
assign TXDETECTRX_in = TXDETECTRX_delay;
assign TXDIFFCTRL_in = TXDIFFCTRL_delay;
assign TXDIFFPD_in = TXDIFFPD_delay;
assign TXDLYBYPASS_in = TXDLYBYPASS_delay;
assign TXDLYEN_in = TXDLYEN_delay;
assign TXDLYHOLD_in = TXDLYHOLD_delay;
assign TXDLYOVRDEN_in = TXDLYOVRDEN_delay;
assign TXDLYSRESET_in = TXDLYSRESET_delay;
assign TXDLYUPDOWN_in = TXDLYUPDOWN_delay;
assign TXELECIDLE_in = TXELECIDLE_delay;
assign TXHEADER_in = TXHEADER_delay;
assign TXINHIBIT_in = TXINHIBIT_delay;
assign TXLATCLK_in = TXLATCLK_delay;
assign TXMAINCURSOR_in = TXMAINCURSOR_delay;
assign TXMARGIN_in = TXMARGIN_delay;
assign TXOUTCLKSEL_in = TXOUTCLKSEL_delay;
assign TXPCSRESET_in = TXPCSRESET_delay;
assign TXPDELECIDLEMODE_in = TXPDELECIDLEMODE_delay;
assign TXPD_in = TXPD_delay;
assign TXPHALIGNEN_in = TXPHALIGNEN_delay;
assign TXPHALIGN_in = TXPHALIGN_delay;
assign TXPHDLYPD_in = TXPHDLYPD_delay;
assign TXPHDLYRESET_in = TXPHDLYRESET_delay;
assign TXPHDLYTSTCLK_in = TXPHDLYTSTCLK_delay;
assign TXPHINIT_in = TXPHINIT_delay;
assign TXPHOVRDEN_in = TXPHOVRDEN_delay;
assign TXPIPPMEN_in = TXPIPPMEN_delay;
assign TXPIPPMOVRDEN_in = TXPIPPMOVRDEN_delay;
assign TXPIPPMPD_in = TXPIPPMPD_delay;
assign TXPIPPMSEL_in = TXPIPPMSEL_delay;
assign TXPIPPMSTEPSIZE_in = TXPIPPMSTEPSIZE_delay;
assign TXPISOPD_in = TXPISOPD_delay;
assign TXPLLCLKSEL_in = TXPLLCLKSEL_delay;
assign TXPMARESET_in = TXPMARESET_delay;
assign TXPOLARITY_in = TXPOLARITY_delay;
assign TXPOSTCURSORINV_in = TXPOSTCURSORINV_delay;
assign TXPOSTCURSOR_in = TXPOSTCURSOR_delay;
assign TXPRBSFORCEERR_in = TXPRBSFORCEERR_delay;
assign TXPRBSSEL_in = TXPRBSSEL_delay;
assign TXPRECURSORINV_in = TXPRECURSORINV_delay;
assign TXPRECURSOR_in = TXPRECURSOR_delay;
assign TXPROGDIVRESET_in = TXPROGDIVRESET_delay;
assign TXQPIBIASEN_in = TXQPIBIASEN_delay;
assign TXQPISTRONGPDOWN_in = TXQPISTRONGPDOWN_delay;
assign TXQPIWEAKPUP_in = TXQPIWEAKPUP_delay;
assign TXRATEMODE_in = TXRATEMODE_delay;
assign TXRATE_in = TXRATE_delay;
assign TXSEQUENCE_in = TXSEQUENCE_delay;
assign TXSWING_in = TXSWING_delay;
assign TXSYNCALLIN_in = TXSYNCALLIN_delay;
assign TXSYNCIN_in = TXSYNCIN_delay;
assign TXSYNCMODE_in = TXSYNCMODE_delay;
assign TXSYSCLKSEL_in = TXSYSCLKSEL_delay;
assign TXUSERRDY_in = TXUSERRDY_delay;
assign TXUSRCLK2_in = TXUSRCLK2_delay;
assign TXUSRCLK_in = TXUSRCLK_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((ACJTAG_DEBUG_MODE_REG < 1'b0) || (ACJTAG_DEBUG_MODE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_DEBUG_MODE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_DEBUG_MODE_REG);
attr_err = 1'b1;
end
if ((ACJTAG_MODE_REG < 1'b0) || (ACJTAG_MODE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_MODE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_MODE_REG);
attr_err = 1'b1;
end
if ((ACJTAG_RESET_REG < 1'b0) || (ACJTAG_RESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_RESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_RESET_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_DOUBLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_ENABLE_REG < 10'b0000000000) || (ALIGN_COMMA_ENABLE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_COMMA_ENABLE_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4)) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_WORD on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, ALIGN_COMMA_WORD_REG, 1);
attr_err = 1'b1;
end
if ((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_MCOMMA_DET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((ALIGN_MCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_MCOMMA_VALUE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_MCOMMA_VALUE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_MCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_PCOMMA_DET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((ALIGN_PCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_PCOMMA_VALUE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_PCOMMA_VALUE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_PCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((A_RXOSCALRESET_REG < 1'b0) || (A_RXOSCALRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_RXOSCALRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_RXOSCALRESET_REG);
attr_err = 1'b1;
end
if ((A_RXPROGDIVRESET_REG < 1'b0) || (A_RXPROGDIVRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_RXPROGDIVRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_RXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((A_TXPROGDIVRESET_REG < 1'b0) || (A_TXPROGDIVRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_TXPROGDIVRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_TXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED")) begin
$display("Attribute Syntax Error : The attribute CBCC_DATA_SOURCE_SEL on %s instance %m is set to %s. Legal values for this attribute are DECODED or ENCODED.", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((CDR_SWAP_MODE_EN_REG < 1'b0) || (CDR_SWAP_MODE_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute CDR_SWAP_MODE_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, CDR_SWAP_MODE_EN_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_KEEP_ALIGN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_MAX_SKEW on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG, 7);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_1_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_2_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_USE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_LEN on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG, 2);
attr_err = 1'b1;
end
if ((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CLK_CORRECT_USE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_KEEP_IDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_MAX_LAT on %s instance %m is set to %d. Legal values for this attribute are 3 to 60.", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_MIN_LAT on %s instance %m is set to %d. Legal values for this attribute are 3 to 63.", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_PRECEDENCE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_REPEAT_WAIT on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_1_REG < 10'b0000000000) || (CLK_COR_SEQ_1_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_2_REG < 10'b0000000000) || (CLK_COR_SEQ_1_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_3_REG < 10'b0000000000) || (CLK_COR_SEQ_1_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_4_REG < 10'b0000000000) || (CLK_COR_SEQ_1_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_1_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_1_REG < 10'b0000000000) || (CLK_COR_SEQ_2_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_2_REG < 10'b0000000000) || (CLK_COR_SEQ_2_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_3_REG < 10'b0000000000) || (CLK_COR_SEQ_2_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_4_REG < 10'b0000000000) || (CLK_COR_SEQ_2_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_2_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_USE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_LEN on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, CLK_COR_SEQ_LEN_REG, 2);
attr_err = 1'b1;
end
if ((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5)) begin
$display("Attribute Syntax Error : The attribute CPLL_FBDIV_45 on %s instance %m is set to %d. Legal values for this attribute are 4 to 5.", MODULE_NAME, CPLL_FBDIV_45_REG, 4);
attr_err = 1'b1;
end
if ((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute CPLL_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, CPLL_FBDIV_REG, 4);
attr_err = 1'b1;
end
if ((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute CPLL_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, CPLL_REFCLK_DIV_REG, 1);
attr_err = 1'b1;
end
if ((DDI_CTRL_REG < 2'b00) || (DDI_CTRL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute DDI_CTRL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, DDI_CTRL_REG);
attr_err = 1'b1;
end
if ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31)) begin
$display("Attribute Syntax Error : The attribute DDI_REALIGN_WAIT on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_MCOMMA_DETECT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_PCOMMA_DETECT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_VALID_COMMA_ONLY on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((DFE_D_X_REL_POS_REG < 1'b0) || (DFE_D_X_REL_POS_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute DFE_D_X_REL_POS on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DFE_D_X_REL_POS_REG);
attr_err = 1'b1;
end
if ((DFE_VCM_COMP_EN_REG < 1'b0) || (DFE_VCM_COMP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute DFE_VCM_COMP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DFE_VCM_COMP_EN_REG);
attr_err = 1'b1;
end
if ((ES_CLK_PHASE_SEL_REG < 1'b0) || (ES_CLK_PHASE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ES_CLK_PHASE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ES_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((ES_CONTROL_REG < 6'b000000) || (ES_CONTROL_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute ES_CONTROL on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, ES_CONTROL_REG);
attr_err = 1'b1;
end
if ((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ES_ERRDET_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ES_EYE_SCAN_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((ES_PMA_CFG_REG < 10'b0000000000) || (ES_PMA_CFG_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ES_PMA_CFG on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ES_PMA_CFG_REG);
attr_err = 1'b1;
end
if ((ES_PRESCALE_REG < 5'b00000) || (ES_PRESCALE_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute ES_PRESCALE on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, ES_PRESCALE_REG);
attr_err = 1'b1;
end
if ((EVODD_PHI_CFG_REG < 11'b00000000000) || (EVODD_PHI_CFG_REG > 11'b11111111111)) begin
$display("Attribute Syntax Error : The attribute EVODD_PHI_CFG on %s instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", MODULE_NAME, EVODD_PHI_CFG_REG);
attr_err = 1'b1;
end
if ((EYE_SCAN_SWAP_EN_REG < 1'b0) || (EYE_SCAN_SWAP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute EYE_SCAN_SWAP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, EYE_SCAN_SWAP_EN_REG);
attr_err = 1'b1;
end
if ((FTS_DESKEW_SEQ_ENABLE_REG < 4'b0000) || (FTS_DESKEW_SEQ_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute FTS_DESKEW_SEQ_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, FTS_DESKEW_SEQ_ENABLE_REG);
attr_err = 1'b1;
end
if ((FTS_LANE_DESKEW_CFG_REG < 4'b0000) || (FTS_LANE_DESKEW_CFG_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute FTS_LANE_DESKEW_CFG on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, FTS_LANE_DESKEW_CFG_REG);
attr_err = 1'b1;
end
if ((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FTS_LANE_DESKEW_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((GEARBOX_MODE_REG < 5'b00000) || (GEARBOX_MODE_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute GEARBOX_MODE on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, GEARBOX_MODE_REG);
attr_err = 1'b1;
end
if ((GM_BIAS_SELECT_REG < 1'b0) || (GM_BIAS_SELECT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute GM_BIAS_SELECT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, GM_BIAS_SELECT_REG);
attr_err = 1'b1;
end
if ((LOCAL_MASTER_REG < 1'b0) || (LOCAL_MASTER_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute LOCAL_MASTER on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, LOCAL_MASTER_REG);
attr_err = 1'b1;
end
if ((OOBDIVCTL_REG < 2'b00) || (OOBDIVCTL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute OOBDIVCTL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, OOBDIVCTL_REG);
attr_err = 1'b1;
end
if ((OOB_PWRUP_REG < 1'b0) || (OOB_PWRUP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute OOB_PWRUP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, OOB_PWRUP_REG);
attr_err = 1'b1;
end
if ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK")) begin
$display("Attribute Syntax Error : The attribute PCI3_AUTO_REALIGN on %s instance %m is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK.", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((PCI3_PIPE_RX_ELECIDLE_REG < 1'b0) || (PCI3_PIPE_RX_ELECIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_PIPE_RX_ELECIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_PIPE_RX_ELECIDLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ASYNC_EBUF_BYPASS_REG < 2'b00) || (PCI3_RX_ASYNC_EBUF_BYPASS_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ASYNC_EBUF_BYPASS on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, PCI3_RX_ASYNC_EBUF_BYPASS_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_EI2_ENABLE_REG < 1'b0) || (PCI3_RX_ELECIDLE_EI2_ENABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_EI2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_ELECIDLE_EI2_ENABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_H2L_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_H2L_COUNT_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_H2L_COUNT on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_COUNT_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_H2L_DISABLE_REG < 3'b000) || (PCI3_RX_ELECIDLE_H2L_DISABLE_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_H2L_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_HI_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_HI_COUNT_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_HI_COUNT on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, PCI3_RX_ELECIDLE_HI_COUNT_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_LP4_DISABLE_REG < 1'b0) || (PCI3_RX_ELECIDLE_LP4_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_LP4_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_ELECIDLE_LP4_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_FIFO_DISABLE_REG < 1'b0) || (PCI3_RX_FIFO_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_FIFO_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_FIFO_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PCS_PCIE_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((PCS_RSVD0_REG < 16'b0000000000000000) || (PCS_RSVD0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute PCS_RSVD0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, PCS_RSVD0_REG);
attr_err = 1'b1;
end
if ((PCS_RSVD1_REG < 3'b000) || (PCS_RSVD1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PCS_RSVD1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PCS_RSVD1_REG);
attr_err = 1'b1;
end
if ((PROCESS_PAR_REG < 3'b000) || (PROCESS_PAR_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PROCESS_PAR on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PROCESS_PAR_REG);
attr_err = 1'b1;
end
if ((RATE_SW_USE_DRP_REG < 1'b0) || (RATE_SW_USE_DRP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RATE_SW_USE_DRP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RATE_SW_USE_DRP_REG);
attr_err = 1'b1;
end
if ((RESET_POWERSAVE_DISABLE_REG < 1'b0) || (RESET_POWERSAVE_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RESET_POWERSAVE_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RESET_POWERSAVE_DISABLE_REG);
attr_err = 1'b1;
end
if ((RXBUFRESET_TIME_REG < 5'b00000) || (RXBUFRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXBUFRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXBUFRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST")) begin
$display("Attribute Syntax Error : The attribute RXBUF_ADDR_MODE on %s instance %m is set to %s. Legal values for this attribute are FULL or FAST.", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((RXBUF_EIDLE_HI_CNT_REG < 4'b0000) || (RXBUF_EIDLE_HI_CNT_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RXBUF_EIDLE_HI_CNT on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RXBUF_EIDLE_HI_CNT_REG);
attr_err = 1'b1;
end
if ((RXBUF_EIDLE_LO_CNT_REG < 4'b0000) || (RXBUF_EIDLE_LO_CNT_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RXBUF_EIDLE_LO_CNT on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RXBUF_EIDLE_LO_CNT_REG);
attr_err = 1'b1;
end
if ((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_CB_CHANGE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_COMMAALIGN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_EIDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_RATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63)) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_OVFLW on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_OVRD on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63)) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_UNDFLW on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((RXCDRFREQRESET_TIME_REG < 5'b00000) || (RXCDRFREQRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXCDRFREQRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXCDRFREQRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXCDRPHRESET_TIME_REG < 5'b00000) || (RXCDRPHRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXCDRPHRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXCDRPHRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXCDR_FR_RESET_ON_EIDLE_REG < 1'b0) || (RXCDR_FR_RESET_ON_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_FR_RESET_ON_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_FR_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXCDR_HOLD_DURING_EIDLE_REG < 1'b0) || (RXCDR_HOLD_DURING_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_HOLD_DURING_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXCDR_PH_RESET_ON_EIDLE_REG < 1'b0) || (RXCDR_PH_RESET_ON_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_PH_RESET_ON_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_PH_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXDFELPMRESET_TIME_REG < 7'b0000000) || (RXDFELPMRESET_TIME_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute RXDFELPMRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, RXDFELPMRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXELECIDLE_CFG_REG != "Sigcfg_4") &&
(RXELECIDLE_CFG_REG != "Sigcfg_1") &&
(RXELECIDLE_CFG_REG != "Sigcfg_2") &&
(RXELECIDLE_CFG_REG != "Sigcfg_3") &&
(RXELECIDLE_CFG_REG != "Sigcfg_6") &&
(RXELECIDLE_CFG_REG != "Sigcfg_8") &&
(RXELECIDLE_CFG_REG != "Sigcfg_12") &&
(RXELECIDLE_CFG_REG != "Sigcfg_16")) begin
$display("Attribute Syntax Error : The attribute RXELECIDLE_CFG on %s instance %m is set to %s. Legal values for this attribute are Sigcfg_4, Sigcfg_1, Sigcfg_2, Sigcfg_3, Sigcfg_6, Sigcfg_8, Sigcfg_12 or Sigcfg_16.", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5)) begin
$display("Attribute Syntax Error : The attribute RXGBOX_FIFO_INIT_RD_ADDR on %s instance %m is set to %d. Legal values for this attribute are 2 to 5.", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG, 4);
attr_err = 1'b1;
end
if ((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXGEARBOX_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((RXISCANRESET_TIME_REG < 5'b00000) || (RXISCANRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXISCANRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXISCANRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXOOB_CFG_REG < 9'b000000000) || (RXOOB_CFG_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute RXOOB_CFG on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, RXOOB_CFG_REG);
attr_err = 1'b1;
end
if ((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC")) begin
$display("Attribute Syntax Error : The attribute RXOOB_CLK_CFG on %s instance %m is set to %s. Legal values for this attribute are PMA or FABRIC.", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((RXOSCALRESET_TIME_REG < 5'b00000) || (RXOSCALRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXOSCALRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXOSCALRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16)) begin
$display("Attribute Syntax Error : The attribute RXOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 16.", MODULE_NAME, RXOUT_DIV_REG, 4);
attr_err = 1'b1;
end
if ((RXPCSRESET_TIME_REG < 5'b00000) || (RXPCSRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPCSRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXPH_MONITOR_SEL_REG < 5'b00000) || (RXPH_MONITOR_SEL_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPH_MONITOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG0_REG < 2'b00) || (RXPI_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG1_REG < 2'b00) || (RXPI_CFG1_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG2_REG < 2'b00) || (RXPI_CFG2_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG3_REG < 2'b00) || (RXPI_CFG3_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG3 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG4_REG < 1'b0) || (RXPI_CFG4_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG4 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG5_REG < 1'b0) || (RXPI_CFG5_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG5 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((RXPI_CFG6_REG < 3'b000) || (RXPI_CFG6_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RXPI_CFG6 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RXPI_CFG6_REG);
attr_err = 1'b1;
end
if ((RXPI_LPM_REG < 1'b0) || (RXPI_LPM_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_LPM on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_LPM_REG);
attr_err = 1'b1;
end
if ((RXPI_VREFSEL_REG < 1'b0) || (RXPI_VREFSEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_VREFSEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN")) begin
$display("Attribute Syntax Error : The attribute RXPMACLK_SEL on %s instance %m is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN.", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((RXPMARESET_TIME_REG < 5'b00000) || (RXPMARESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPMARESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXPRBS_ERR_LOOPBACK_REG < 1'b0) || (RXPRBS_ERR_LOOPBACK_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPRBS_ERR_LOOPBACK on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPRBS_ERR_LOOPBACK_REG);
attr_err = 1'b1;
end
if ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255)) begin
$display("Attribute Syntax Error : The attribute RXPRBS_LINKACQ_CNT on %s instance %m is set to %d. Legal values for this attribute are 15 to 255.", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15)) begin
$display("Attribute Syntax Error : The attribute RXSLIDE_AUTO_WAIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 15.", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG, 7);
attr_err = 1'b1;
end
if ((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA")) begin
$display("Attribute Syntax Error : The attribute RXSLIDE_MODE on %s instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA.", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((RXSYNC_MULTILANE_REG < 1'b0) || (RXSYNC_MULTILANE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_MULTILANE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((RXSYNC_OVRD_REG < 1'b0) || (RXSYNC_OVRD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_OVRD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((RXSYNC_SKIP_DA_REG < 1'b0) || (RXSYNC_SKIP_DA_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_SKIP_DA on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((RX_AFE_CM_EN_REG < 1'b0) || (RX_AFE_CM_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_AFE_CM_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_AFE_CM_EN_REG);
attr_err = 1'b1;
end
if ((RX_BUFFER_CFG_REG < 6'b000000) || (RX_BUFFER_CFG_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute RX_BUFFER_CFG on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, RX_BUFFER_CFG_REG);
attr_err = 1'b1;
end
if ((RX_CAPFF_SARC_ENB_REG < 1'b0) || (RX_CAPFF_SARC_ENB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CAPFF_SARC_ENB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CAPFF_SARC_ENB_REG);
attr_err = 1'b1;
end
if ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32)) begin
$display("Attribute Syntax Error : The attribute RX_CLK25_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((RX_CLKMUX_EN_REG < 1'b0) || (RX_CLKMUX_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CLKMUX_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((RX_CLK_SLIP_OVRD_REG < 5'b00000) || (RX_CLK_SLIP_OVRD_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RX_CLK_SLIP_OVRD on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RX_CLK_SLIP_OVRD_REG);
attr_err = 1'b1;
end
if ((RX_CM_BUF_CFG_REG < 4'b0000) || (RX_CM_BUF_CFG_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_CM_BUF_CFG on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_CM_BUF_CFG_REG);
attr_err = 1'b1;
end
if ((RX_CM_BUF_PD_REG < 1'b0) || (RX_CM_BUF_PD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CM_BUF_PD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CM_BUF_PD_REG);
attr_err = 1'b1;
end
if ((RX_CM_SEL_REG < 2'b00) || (RX_CM_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_CM_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((RX_CM_TRIM_REG < 4'b0000) || (RX_CM_TRIM_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_CM_TRIM on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((RX_CTLE3_LPF_REG < 8'b00000000) || (RX_CTLE3_LPF_REG > 8'b11111111)) begin
$display("Attribute Syntax Error : The attribute RX_CTLE3_LPF on %s instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", MODULE_NAME, RX_CTLE3_LPF_REG);
attr_err = 1'b1;
end
if ((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160)) begin
$display("Attribute Syntax Error : The attribute RX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, RX_DATA_WIDTH_REG, 20);
attr_err = 1'b1;
end
if ((RX_DDI_SEL_REG < 6'b000000) || (RX_DDI_SEL_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute RX_DDI_SEL on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, RX_DDI_SEL_REG);
attr_err = 1'b1;
end
if ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RX_DEFER_RESET_BUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_CFG0_REG < 4'b0000) || (RX_DFELPM_CFG0_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_CFG1_REG < 1'b0) || (RX_DFELPM_CFG1_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFELPM_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_KLKH_AGC_STUP_EN_REG < 1'b0) || (RX_DFELPM_KLKH_AGC_STUP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_KLKH_AGC_STUP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFELPM_KLKH_AGC_STUP_EN_REG);
attr_err = 1'b1;
end
if ((RX_DFE_AGC_CFG0_REG < 2'b00) || (RX_DFE_AGC_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_AGC_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_AGC_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_AGC_CFG1_REG < 3'b000) || (RX_DFE_AGC_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_AGC_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KH_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KH_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KH_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KH_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KH_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KH_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KL_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KL_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KL_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KL_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KL_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KL_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_LPM_HOLD_DURING_EIDLE_REG < 1'b0) || (RX_DFE_LPM_HOLD_DURING_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_LPM_HOLD_DURING_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFE_LPM_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RX_DISPERR_SEQ_MATCH on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((RX_DIVRESET_TIME_REG < 5'b00000) || (RX_DIVRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RX_DIVRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RX_EN_HI_LR_REG < 1'b0) || (RX_EN_HI_LR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EN_HI_LR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EN_HI_LR_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_CODE_REG < 7'b0000000) || (RX_EYESCAN_VS_CODE_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_CODE on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, RX_EYESCAN_VS_CODE_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_NEG_DIR_REG < 1'b0) || (RX_EYESCAN_VS_NEG_DIR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_NEG_DIR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EYESCAN_VS_NEG_DIR_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_RANGE_REG < 2'b00) || (RX_EYESCAN_VS_RANGE_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_RANGE on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_EYESCAN_VS_RANGE_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_UT_SIGN_REG < 1'b0) || (RX_EYESCAN_VS_UT_SIGN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_UT_SIGN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EYESCAN_VS_UT_SIGN_REG);
attr_err = 1'b1;
end
if ((RX_FABINT_USRCLK_FLOP_REG < 1'b0) || (RX_FABINT_USRCLK_FLOP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_FABINT_USRCLK_FLOP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2)) begin
$display("Attribute Syntax Error : The attribute RX_INT_DATAWIDTH on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, RX_INT_DATAWIDTH_REG, 1);
attr_err = 1'b1;
end
if ((RX_PMA_POWER_SAVE_REG < 1'b0) || (RX_PMA_POWER_SAVE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_PMA_POWER_SAVE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((RX_SAMPLE_PERIOD_REG < 3'b000) || (RX_SAMPLE_PERIOD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_SAMPLE_PERIOD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32)) begin
$display("Attribute Syntax Error : The attribute RX_SIG_VALID_DLY on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((RX_SUM_DFETAPREP_EN_REG < 1'b0) || (RX_SUM_DFETAPREP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_DFETAPREP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_SUM_DFETAPREP_EN_REG);
attr_err = 1'b1;
end
if ((RX_SUM_IREF_TUNE_REG < 4'b0000) || (RX_SUM_IREF_TUNE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_IREF_TUNE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_SUM_IREF_TUNE_REG);
attr_err = 1'b1;
end
if ((RX_SUM_RES_CTRL_REG < 2'b00) || (RX_SUM_RES_CTRL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_RES_CTRL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_SUM_RES_CTRL_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VCMTUNE_REG < 4'b0000) || (RX_SUM_VCMTUNE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VCMTUNE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_SUM_VCMTUNE_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VCM_OVWR_REG < 1'b0) || (RX_SUM_VCM_OVWR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VCM_OVWR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_SUM_VCM_OVWR_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VREF_TUNE_REG < 3'b000) || (RX_SUM_VREF_TUNE_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VREF_TUNE on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_SUM_VREF_TUNE_REG);
attr_err = 1'b1;
end
if ((RX_TUNE_AFE_OS_REG < 2'b00) || (RX_TUNE_AFE_OS_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_TUNE_AFE_OS on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_TUNE_AFE_OS_REG);
attr_err = 1'b1;
end
if ((RX_WIDEMODE_CDR_REG < 1'b0) || (RX_WIDEMODE_CDR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_WIDEMODE_CDR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_WIDEMODE_CDR_REG);
attr_err = 1'b1;
end
if ((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR")) begin
$display("Attribute Syntax Error : The attribute RX_XCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR.", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127)) begin
$display("Attribute Syntax Error : The attribute SAS_MAX_COM on %s instance %m is set to %d. Legal values for this attribute are 1 to 127.", MODULE_NAME, SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SAS_MIN_COM on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if ((SATA_BURST_SEQ_LEN_REG < 4'b0000) || (SATA_BURST_SEQ_LEN_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute SATA_BURST_SEQ_LEN on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, SATA_BURST_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((SATA_BURST_VAL_REG < 3'b000) || (SATA_BURST_VAL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SATA_BURST_VAL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SATA_BURST_VAL_REG);
attr_err = 1'b1;
end
if ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ")) begin
$display("Attribute Syntax Error : The attribute SATA_CPLL_CFG on %s instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ.", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((SATA_EIDLE_VAL_REG < 3'b000) || (SATA_EIDLE_VAL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SATA_EIDLE_VAL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SATA_EIDLE_VAL_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_BURST on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_INIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_WAKE on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_BURST on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_INIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_WAKE on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SHOW_REALIGN_COMMA on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((SIM_CPLLREFCLK_SEL_REG < 3'b000) || (SIM_CPLLREFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_CPLLREFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_CPLLREFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RECEIVER_DETECT_PASS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RESET_SPEEDUP on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((SIM_TX_EIDLE_DRIVE_LEVEL_REG < 1'b0) || (SIM_TX_EIDLE_DRIVE_LEVEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SIM_TX_EIDLE_DRIVE_LEVEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2")) begin
$display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2.", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((TEMPERATUR_PAR_REG < 4'b0000) || (TEMPERATUR_PAR_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute TEMPERATUR_PAR on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, TEMPERATUR_PAR_REG);
attr_err = 1'b1;
end
if ((TERM_RCAL_CFG_REG < 15'b000000000000000) || (TERM_RCAL_CFG_REG > 15'b111111111111111)) begin
$display("Attribute Syntax Error : The attribute TERM_RCAL_CFG on %s instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", MODULE_NAME, TERM_RCAL_CFG_REG);
attr_err = 1'b1;
end
if ((TERM_RCAL_OVRD_REG < 3'b000) || (TERM_RCAL_OVRD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TERM_RCAL_OVRD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TERM_RCAL_OVRD_REG);
attr_err = 1'b1;
end
if ((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TXBUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TXBUF_RESET_ON_RATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((TXDRVBIAS_N_REG < 4'b0000) || (TXDRVBIAS_N_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute TXDRVBIAS_N on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, TXDRVBIAS_N_REG);
attr_err = 1'b1;
end
if ((TXDRVBIAS_P_REG < 4'b0000) || (TXDRVBIAS_P_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute TXDRVBIAS_P on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, TXDRVBIAS_P_REG);
attr_err = 1'b1;
end
if ((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH")) begin
$display("Attribute Syntax Error : The attribute TXFIFO_ADDR_CFG on %s instance %m is set to %s. Legal values for this attribute are LOW or HIGH.", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6)) begin
$display("Attribute Syntax Error : The attribute TXGBOX_FIFO_INIT_RD_ADDR on %s instance %m is set to %d. Legal values for this attribute are 2 to 6.", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG, 4);
attr_err = 1'b1;
end
if ((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TXGEARBOX_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16)) begin
$display("Attribute Syntax Error : The attribute TXOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 16.", MODULE_NAME, TXOUT_DIV_REG, 4);
attr_err = 1'b1;
end
if ((TXPCSRESET_TIME_REG < 5'b00000) || (TXPCSRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPCSRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((TXPH_MONITOR_SEL_REG < 5'b00000) || (TXPH_MONITOR_SEL_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPH_MONITOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG0_REG < 2'b00) || (TXPI_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG1_REG < 2'b00) || (TXPI_CFG1_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG2_REG < 2'b00) || (TXPI_CFG2_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG3_REG < 1'b0) || (TXPI_CFG3_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG3 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG4_REG < 1'b0) || (TXPI_CFG4_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG4 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG5_REG < 3'b000) || (TXPI_CFG5_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG5 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((TXPI_GRAY_SEL_REG < 1'b0) || (TXPI_GRAY_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_GRAY_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_GRAY_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_INVSTROBE_SEL_REG < 1'b0) || (TXPI_INVSTROBE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_INVSTROBE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_INVSTROBE_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_LPM_REG < 1'b0) || (TXPI_LPM_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_LPM on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_LPM_REG);
attr_err = 1'b1;
end
if ((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK")) begin
$display("Attribute Syntax Error : The attribute TXPI_PPMCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK.", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_PPM_CFG_REG < 8'b00000000) || (TXPI_PPM_CFG_REG > 8'b11111111)) begin
$display("Attribute Syntax Error : The attribute TXPI_PPM_CFG on %s instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", MODULE_NAME, TXPI_PPM_CFG_REG);
attr_err = 1'b1;
end
if ((TXPI_SYNFREQ_PPM_REG < 3'b000) || (TXPI_SYNFREQ_PPM_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TXPI_SYNFREQ_PPM on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TXPI_SYNFREQ_PPM_REG);
attr_err = 1'b1;
end
if ((TXPI_VREFSEL_REG < 1'b0) || (TXPI_VREFSEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_VREFSEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((TXPMARESET_TIME_REG < 5'b00000) || (TXPMARESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPMARESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((TXSYNC_MULTILANE_REG < 1'b0) || (TXSYNC_MULTILANE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_MULTILANE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((TXSYNC_OVRD_REG < 1'b0) || (TXSYNC_OVRD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_OVRD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((TXSYNC_SKIP_DA_REG < 1'b0) || (TXSYNC_SKIP_DA_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_SKIP_DA on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32)) begin
$display("Attribute Syntax Error : The attribute TX_CLK25_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((TX_CLKMUX_EN_REG < 1'b0) || (TX_CLKMUX_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_CLKMUX_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160)) begin
$display("Attribute Syntax Error : The attribute TX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, TX_DATA_WIDTH_REG, 20);
attr_err = 1'b1;
end
if ((TX_DCD_CFG_REG < 6'b000000) || (TX_DCD_CFG_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DCD_CFG on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DCD_CFG_REG);
attr_err = 1'b1;
end
if ((TX_DCD_EN_REG < 1'b0) || (TX_DCD_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_DCD_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_DCD_EN_REG);
attr_err = 1'b1;
end
if ((TX_DEEMPH0_REG < 6'b000000) || (TX_DEEMPH0_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DEEMPH0 on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DEEMPH0_REG);
attr_err = 1'b1;
end
if ((TX_DEEMPH1_REG < 6'b000000) || (TX_DEEMPH1_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DEEMPH1 on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DEEMPH1_REG);
attr_err = 1'b1;
end
if ((TX_DIVRESET_TIME_REG < 5'b00000) || (TX_DIVRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TX_DIVRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3")) begin
$display("Attribute Syntax Error : The attribute TX_DRIVE_MODE on %s instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3.", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((TX_EIDLE_ASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_ASSERT_DELAY_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_EIDLE_ASSERT_DELAY on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_EIDLE_ASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((TX_EIDLE_DEASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_DEASSERT_DELAY_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_EIDLE_DEASSERT_DELAY on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_EIDLE_DEASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((TX_EML_PHI_TUNE_REG < 1'b0) || (TX_EML_PHI_TUNE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_EML_PHI_TUNE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_EML_PHI_TUNE_REG);
attr_err = 1'b1;
end
if ((TX_FABINT_USRCLK_FLOP_REG < 1'b0) || (TX_FABINT_USRCLK_FLOP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_FABINT_USRCLK_FLOP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((TX_IDLE_DATA_ZERO_REG < 1'b0) || (TX_IDLE_DATA_ZERO_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_IDLE_DATA_ZERO on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_IDLE_DATA_ZERO_REG);
attr_err = 1'b1;
end
if ((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2)) begin
$display("Attribute Syntax Error : The attribute TX_INT_DATAWIDTH on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, TX_INT_DATAWIDTH_REG, 1);
attr_err = 1'b1;
end
if ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TX_LOOPBACK_DRIVE_HIZ on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((TX_MAINCURSOR_SEL_REG < 1'b0) || (TX_MAINCURSOR_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_MAINCURSOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_MAINCURSOR_SEL_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_0_REG < 7'b0000000) || (TX_MARGIN_FULL_0_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_0 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_0_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_1_REG < 7'b0000000) || (TX_MARGIN_FULL_1_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_1 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_1_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_2_REG < 7'b0000000) || (TX_MARGIN_FULL_2_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_2 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_2_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_3_REG < 7'b0000000) || (TX_MARGIN_FULL_3_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_3 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_3_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_4_REG < 7'b0000000) || (TX_MARGIN_FULL_4_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_4 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_4_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_0_REG < 7'b0000000) || (TX_MARGIN_LOW_0_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_0 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_0_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_1_REG < 7'b0000000) || (TX_MARGIN_LOW_1_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_1 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_1_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_2_REG < 7'b0000000) || (TX_MARGIN_LOW_2_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_2 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_2_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_3_REG < 7'b0000000) || (TX_MARGIN_LOW_3_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_3 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_3_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_4_REG < 7'b0000000) || (TX_MARGIN_LOW_4_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_4 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_4_REG);
attr_err = 1'b1;
end
if ((TX_MODE_SEL_REG < 3'b000) || (TX_MODE_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_MODE_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_MODE_SEL_REG);
attr_err = 1'b1;
end
if ((TX_PMADATA_OPT_REG < 1'b0) || (TX_PMADATA_OPT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PMADATA_OPT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PMADATA_OPT_REG);
attr_err = 1'b1;
end
if ((TX_PMA_POWER_SAVE_REG < 1'b0) || (TX_PMA_POWER_SAVE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PMA_POWER_SAVE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI")) begin
$display("Attribute Syntax Error : The attribute TX_PROGCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI.", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((TX_QPI_STATUS_EN_REG < 1'b0) || (TX_QPI_STATUS_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_QPI_STATUS_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_QPI_STATUS_EN_REG);
attr_err = 1'b1;
end
if ((TX_RXDETECT_REF_REG < 3'b000) || (TX_RXDETECT_REF_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_RXDETECT_REF on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((TX_SAMPLE_PERIOD_REG < 3'b000) || (TX_SAMPLE_PERIOD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_SAMPLE_PERIOD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((TX_SARC_LPBK_ENB_REG < 1'b0) || (TX_SARC_LPBK_ENB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_SARC_LPBK_ENB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_SARC_LPBK_ENB_REG);
attr_err = 1'b1;
end
if ((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR")) begin
$display("Attribute Syntax Error : The attribute TX_XCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are TXOUT or TXUSR.", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((USE_PCS_CLK_PHASE_SEL_REG < 1'b0) || (USE_PCS_CLK_PHASE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute USE_PCS_CLK_PHASE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, USE_PCS_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((WB_MODE_REG < 2'b00) || (WB_MODE_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute WB_MODE on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, WB_MODE_REG);
attr_err = 1'b1;
end
if (RX_PROGDIV_CFG_REG >= 4.0 && RX_PROGDIV_CFG_REG <= 66.0) begin // float
RX_PROGDIV_CFG_INT <= RX_PROGDIV_CFG_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute RX_PROGDIV_CFG on %s instance %m is set to %f. Legal values for this attribute are 4.0 to 66.0.", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if (TX_PROGDIV_CFG_REG >= 4.0 && TX_PROGDIV_CFG_REG <= 66.0) begin // float
TX_PROGDIV_CFG_INT <= TX_PROGDIV_CFG_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute TX_PROGDIV_CFG on %s instance %m is set to %f. Legal values for this attribute are 4.0 to 66.0.", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 12'b111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTHE3_CHANNEL SIP_GTHE3_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_EYESCAN (AEN_EYESCAN_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_QPI (AEN_QPI_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.A_AFECFOKEN (A_AFECFOKEN_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG),
.A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG),
.A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG),
.A_DFECFOKHOLD (A_DFECFOKHOLD_REG),
.A_DFECFOKOVREN (A_DFECFOKOVREN_REG),
.A_EYESCANMODE (A_EYESCANMODE_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_LPMGCHOLD (A_LPMGCHOLD_REG),
.A_LPMGCOVREN (A_LPMGCOVREN_REG),
.A_LPMOSHOLD (A_LPMOSHOLD_REG),
.A_LPMOSOVREN (A_LPMOSOVREN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEVSEN (A_RXDFEVSEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPOSTCURSORINV (A_TXPOSTCURSORINV_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPRECURSORINV (A_TXPRECURSORINV_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXQPIBIASEN (A_TXQPIBIASEN_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG),
.CPLL_IPS_EN (CPLL_IPS_EN_REG),
.CPLL_IPS_REFCLK_SEL (CPLL_IPS_REFCLK_SEL_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG),
.DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PMA_CFG (ES_PMA_CFG_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.EVODD_PHI_CFG (EVODD_PHI_CFG_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GM_BIAS_SELECT (GM_BIAS_SELECT_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PCS_RSVD1 (PCS_RSVD1_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG),
.PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG),
.PMA_RSV1 (PMA_RSV1_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_CFG0 (RXPI_CFG0_REG),
.RXPI_CFG1 (RXPI_CFG1_REG),
.RXPI_CFG2 (RXPI_CFG2_REG),
.RXPI_CFG3 (RXPI_CFG3_REG),
.RXPI_CFG4 (RXPI_CFG4_REG),
.RXPI_CFG5 (RXPI_CFG5_REG),
.RXPI_CFG6 (RXPI_CFG6_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPLL_SEL (RXPLL_SEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE3_LPF (RX_CTLE3_LPF_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_INT),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.SAS_MAX_COM (SAS_MAX_COM_REG),
.SAS_MIN_COM (SAS_MIN_COM_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SATA_MAX_BURST (SATA_MAX_BURST_REG),
.SATA_MAX_INIT (SATA_MAX_INIT_REG),
.SATA_MAX_WAKE (SATA_MAX_WAKE_REG),
.SATA_MIN_BURST (SATA_MIN_BURST_REG),
.SATA_MIN_INIT (SATA_MIN_INIT_REG),
.SATA_MIN_WAKE (SATA_MIN_WAKE_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATUR_PAR (TEMPERATUR_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXDRVBIAS_N (TXDRVBIAS_N_REG),
.TXDRVBIAS_P (TXDRVBIAS_P_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCD_CFG (TX_DCD_CFG_REG),
.TX_DCD_EN (TX_DCD_EN_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_MODE_SEL (TX_MODE_SEL_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_INT),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.WB_MODE (WB_MODE_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.DMONITOROUT (DMONITOROUT_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTHTXN (GTHTXN_out),
.GTHTXP (GTHTXP_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXQPISENN (RXQPISENN_out),
.RXQPISENP (RXQPISENP_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXQPISENN (TXQPISENN_out),
.TXQPISENP (TXQPISENP_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.EVODDPHICALDONE (EVODDPHICALDONE_in),
.EVODDPHICALSTART (EVODDPHICALSTART_in),
.EVODDPHIDRDEN (EVODDPHIDRDEN_in),
.EVODDPHIDWREN (EVODDPHIDWREN_in),
.EVODDPHIXRDEN (EVODDPHIXRDEN_in),
.EVODDPHIXWREN (EVODDPHIXWREN_in),
.EYESCANMODE (EYESCANMODE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.GTGREFCLK (GTGREFCLK_in),
.GTHRXN (GTHRXN_in),
.GTHRXP (GTHRXP_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRESETSEL (GTRESETSEL_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.LOOPBACK (LOOPBACK_in),
.LPBKRXTXSEREN (LPBKRXTXSEREN_in),
.LPBKTXRXSEREN (LPBKTXRXSEREN_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PCSRSVDIN2 (PCSRSVDIN2_in),
.PMARSVDIN (PMARSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RSTCLKENTX (RSTCLKENTX_in),
.RX8B10BEN (RX8B10BEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCDRRESETRSV (RXCDRRESETRSV_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDFEAGCCTRL (RXDFEAGCCTRL_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEVSEN (RXDFEVSEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSINTCFG (RXOSINTCFG_in),
.RXOSINTEN (RXOSINTEN_in),
.RXOSINTHOLD (RXOSINTHOLD_in),
.RXOSINTOVRDEN (RXOSINTOVRDEN_in),
.RXOSINTSTROBE (RXOSINTSTROBE_in),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXQPIEN (RXQPIEN_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDIFFPD (TXDIFFPD_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPOSTCURSORINV (TXPOSTCURSORINV_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPRECURSORINV (TXPRECURSORINV_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXQPIBIASEN (TXQPIBIASEN_in),
.TXQPISTRONGPDOWN (TXQPISTRONGPDOWN_in),
.TXQPIWEAKPUP (TXQPIWEAKPUP_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
specify
(DMONITORCLK *> DMONITOROUT) = (0:0:0, 0:0:0);
(DRPCLK *> DRPDO) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
(RXUSRCLK *> RXCHBONDO) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXBUFSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCHBONDO) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCLKCORCNT) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCTRL0) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCTRL1) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCTRL2) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXCTRL3) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXDATA) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXDATAVALID) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXHEADER) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXHEADERVALID) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXSTARTOFSEQ) = (0:0:0, 0:0:0);
(RXUSRCLK2 *> RXSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => PHYSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANBONDSEQ) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMINITDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMMADET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMSASDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMWAKEDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSERR) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSLOCKED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRATEDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIDERDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPPMARDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXVALID) = (0:0:0, 0:0:0);
(TXUSRCLK2 *> TXBUFSTATUS) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXCOMFINISH) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRATEDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRESETDONE) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDI_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay);
$setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDI_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay);
$setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay);
$setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay);
$setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay);
$setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay);
$setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTHE3_COMMON.v 0000664 0000000 0000000 00000130302 12327044266 0023303 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTHE3_COMMON.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE3_COMMON #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [15:0] BIAS_CFG0 = 16'h0000,
parameter [15:0] BIAS_CFG1 = 16'h0000,
parameter [15:0] BIAS_CFG2 = 16'h0000,
parameter [15:0] BIAS_CFG3 = 16'h0000,
parameter [15:0] BIAS_CFG4 = 16'h0000,
parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000,
parameter [15:0] COMMON_CFG0 = 16'h0000,
parameter [15:0] COMMON_CFG1 = 16'h0000,
parameter [15:0] POR_CFG = 16'h0004,
parameter [15:0] QPLL0_CFG0 = 16'h301C,
parameter [15:0] QPLL0_CFG1 = 16'h0000,
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL0_CFG2 = 16'h0000,
parameter [15:0] QPLL0_CFG2_G3 = 16'h0000,
parameter [15:0] QPLL0_CFG3 = 16'h0120,
parameter [15:0] QPLL0_CFG4 = 16'h0009,
parameter [9:0] QPLL0_CP = 10'b0000011111,
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111,
parameter integer QPLL0_FBDIV = 66,
parameter integer QPLL0_FBDIV_G3 = 80,
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL0_LOCK_CFG = 16'h21E8,
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL0_LPF = 10'b1111111111,
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111,
parameter integer QPLL0_REFCLK_DIV = 2,
parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000,
parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000,
parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000,
parameter [15:0] QPLL1_CFG0 = 16'h301C,
parameter [15:0] QPLL1_CFG1 = 16'h0000,
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL1_CFG2 = 16'h0000,
parameter [15:0] QPLL1_CFG2_G3 = 16'h0000,
parameter [15:0] QPLL1_CFG3 = 16'h0120,
parameter [15:0] QPLL1_CFG4 = 16'h0009,
parameter [9:0] QPLL1_CP = 10'b0000011111,
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111,
parameter integer QPLL1_FBDIV = 66,
parameter integer QPLL1_FBDIV_G3 = 80,
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL1_LOCK_CFG = 16'h21E8,
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL1_LPF = 10'b1111111111,
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111,
parameter integer QPLL1_REFCLK_DIV = 2,
parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000,
parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000,
parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000,
parameter [15:0] RSVD_ATTR0 = 16'h0000,
parameter [15:0] RSVD_ATTR1 = 16'h0000,
parameter [15:0] RSVD_ATTR2 = 16'h0000,
parameter [15:0] RSVD_ATTR3 = 16'h0000,
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00,
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00,
parameter [0:0] SARC_EN = 1'b1,
parameter [0:0] SARC_SEL = 1'b0,
parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000,
parameter [8:0] SDM0DATA1_1 = 9'b000000000,
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000,
parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0,
parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0,
parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000,
parameter [8:0] SDM1DATA1_1 = 9'b000000000,
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000,
parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0,
parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0,
parameter [2:0] SIM_QPLL0REFCLK_SEL = 3'b001,
parameter [2:0] SIM_QPLL1REFCLK_SEL = 3'b001,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter SIM_VERSION = "Ver_1"
)(
output [15:0] DRPDO,
output DRPRDY,
output [7:0] PMARSVDOUT0,
output [7:0] PMARSVDOUT1,
output QPLL0FBCLKLOST,
output QPLL0LOCK,
output QPLL0OUTCLK,
output QPLL0OUTREFCLK,
output QPLL0REFCLKLOST,
output QPLL1FBCLKLOST,
output QPLL1LOCK,
output QPLL1OUTCLK,
output QPLL1OUTREFCLK,
output QPLL1REFCLKLOST,
output [7:0] QPLLDMONITOR0,
output [7:0] QPLLDMONITOR1,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [1:0] RXRECCLK0_SEL,
output [1:0] RXRECCLK1_SEL,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input [4:0] BGRCALOVRD,
input BGRCALOVRDENB,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input GTGREFCLK0,
input GTGREFCLK1,
input GTNORTHREFCLK00,
input GTNORTHREFCLK01,
input GTNORTHREFCLK10,
input GTNORTHREFCLK11,
input GTREFCLK00,
input GTREFCLK01,
input GTREFCLK10,
input GTREFCLK11,
input GTSOUTHREFCLK00,
input GTSOUTHREFCLK01,
input GTSOUTHREFCLK10,
input GTSOUTHREFCLK11,
input [7:0] PMARSVD0,
input [7:0] PMARSVD1,
input QPLL0CLKRSVD0,
input QPLL0CLKRSVD1,
input QPLL0LOCKDETCLK,
input QPLL0LOCKEN,
input QPLL0PD,
input [2:0] QPLL0REFCLKSEL,
input QPLL0RESET,
input QPLL1CLKRSVD0,
input QPLL1CLKRSVD1,
input QPLL1LOCKDETCLK,
input QPLL1LOCKEN,
input QPLL1PD,
input [2:0] QPLL1REFCLKSEL,
input QPLL1RESET,
input [7:0] QPLLRSVD1,
input [4:0] QPLLRSVD2,
input [4:0] QPLLRSVD3,
input [7:0] QPLLRSVD4,
input RCALENB
);
// define constants
localparam MODULE_NAME = "GTHE3_COMMON";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0;
localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1;
localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2;
localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3;
localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4;
localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD;
localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0;
localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1;
localparam [15:0] POR_CFG_REG = POR_CFG;
localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0;
localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1;
localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3;
localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2;
localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3;
localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3;
localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4;
localparam [9:0] QPLL0_CP_REG = QPLL0_CP;
localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3;
localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV;
localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3;
localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0;
localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1;
localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG;
localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3;
localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF;
localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3;
localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV;
localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0;
localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1;
localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2;
localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0;
localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1;
localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3;
localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2;
localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3;
localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3;
localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4;
localparam [9:0] QPLL1_CP_REG = QPLL1_CP;
localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3;
localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV;
localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3;
localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0;
localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1;
localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG;
localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3;
localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF;
localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3;
localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV;
localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0;
localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1;
localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2;
localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0;
localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1;
localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2;
localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3;
localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL;
localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL;
localparam [0:0] SARC_EN_REG = SARC_EN;
localparam [0:0] SARC_SEL_REG = SARC_SEL;
localparam [15:0] SDM0DATA1_0_REG = SDM0DATA1_0;
localparam [8:0] SDM0DATA1_1_REG = SDM0DATA1_1;
localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0;
localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1;
localparam [0:0] SDM0_DATA_PIN_SEL_REG = SDM0_DATA_PIN_SEL;
localparam [0:0] SDM0_WIDTH_PIN_SEL_REG = SDM0_WIDTH_PIN_SEL;
localparam [15:0] SDM1DATA1_0_REG = SDM1DATA1_0;
localparam [8:0] SDM1DATA1_1_REG = SDM1DATA1_1;
localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0;
localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1;
localparam [0:0] SDM1_DATA_PIN_SEL_REG = SDM1_DATA_PIN_SEL;
localparam [0:0] SDM1_WIDTH_PIN_SEL_REG = SDM1_WIDTH_PIN_SEL;
localparam [2:0] SIM_QPLL0REFCLK_SEL_REG = SIM_QPLL0REFCLK_SEL;
localparam [2:0] SIM_QPLL1REFCLK_SEL_REG = SIM_QPLL1REFCLK_SEL;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
`endif
localparam [0:0] AEN_BGBS0_REG = 1'b0;
localparam [0:0] AEN_BGBS1_REG = 1'b0;
localparam [0:0] AEN_MASTER0_REG = 1'b0;
localparam [0:0] AEN_MASTER1_REG = 1'b0;
localparam [0:0] AEN_PD0_REG = 1'b0;
localparam [0:0] AEN_PD1_REG = 1'b0;
localparam [0:0] AEN_QPLL0_REG = 1'b0;
localparam [0:0] AEN_QPLL1_REG = 1'b0;
localparam [0:0] AEN_REFCLK0_REG = 1'b0;
localparam [0:0] AEN_REFCLK1_REG = 1'b0;
localparam [0:0] AEN_RESET0_REG = 1'b0;
localparam [0:0] AEN_RESET1_REG = 1'b0;
localparam [3:0] AQDMUXSEL1_REG = 4'b0000;
localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000;
localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000;
localparam [0:0] A_BGMONITOREN_REG = 1'b0;
localparam [0:0] A_BGPD_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD0_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD1_REG = 1'b0;
localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL0PD_REG = 1'b0;
localparam [0:0] A_QPLL0RESET_REG = 1'b0;
localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL1PD_REG = 1'b0;
localparam [0:0] A_QPLL1RESET_REG = 1'b0;
localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00;
localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00;
localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1;
localparam [15:0] PPF0_CFG_REG = 16'h0000;
localparam [15:0] PPF1_CFG_REG = 16'h0000;
localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] QPLL0_IPS_EN_REG = 1'b1;
localparam [2:0] QPLL0_IPS_REFCLK_SEL_REG = 3'b000;
localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] QPLL1_IPS_EN_REG = 1'b1;
localparam [2:0] QPLL1_IPS_REFCLK_SEL_REG = 3'b000;
localparam [0:0] RCALSAP_TESTEN_REG = 1'b0;
localparam [0:0] RCAL_APROBE_REG = 1'b0;
localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0;
localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0;
localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTHE3_COMMON_dr.v"
`endif
wire DRPRDY_out;
wire QPLL0FBCLKLOST_out;
wire QPLL0LOCK_out;
wire QPLL0OUTCLK_out;
wire QPLL0OUTREFCLK_out;
wire QPLL0REFCLKLOST_out;
wire QPLL1FBCLKLOST_out;
wire QPLL1LOCK_out;
wire QPLL1OUTCLK_out;
wire QPLL1OUTREFCLK_out;
wire QPLL1REFCLKLOST_out;
wire REFCLKOUTMONITOR0_out;
wire REFCLKOUTMONITOR1_out;
wire [15:0] DRPDO_out;
wire [1:0] RXRECCLK0_SEL_out;
wire [1:0] RXRECCLK1_SEL_out;
wire [3:0] SARCCLK_out;
wire [7:0] PMARSVDOUT0_out;
wire [7:0] PMARSVDOUT1_out;
wire [7:0] PMASCANOUT_out;
wire [7:0] QPLLDMONITOR0_out;
wire [7:0] QPLLDMONITOR1_out;
wire DRPRDY_delay;
wire QPLL0FBCLKLOST_delay;
wire QPLL0LOCK_delay;
wire QPLL0OUTCLK_delay;
wire QPLL0OUTREFCLK_delay;
wire QPLL0REFCLKLOST_delay;
wire QPLL1FBCLKLOST_delay;
wire QPLL1LOCK_delay;
wire QPLL1OUTCLK_delay;
wire QPLL1OUTREFCLK_delay;
wire QPLL1REFCLKLOST_delay;
wire REFCLKOUTMONITOR0_delay;
wire REFCLKOUTMONITOR1_delay;
wire [15:0] DRPDO_delay;
wire [1:0] RXRECCLK0_SEL_delay;
wire [1:0] RXRECCLK1_SEL_delay;
wire [7:0] PMARSVDOUT0_delay;
wire [7:0] PMARSVDOUT1_delay;
wire [7:0] QPLLDMONITOR0_delay;
wire [7:0] QPLLDMONITOR1_delay;
wire BGBYPASSB_in;
wire BGMONITORENB_in;
wire BGPDB_in;
wire BGRCALOVRDENB_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire GTGREFCLK0_in;
wire GTGREFCLK1_in;
wire GTNORTHREFCLK00_in;
wire GTNORTHREFCLK01_in;
wire GTNORTHREFCLK10_in;
wire GTNORTHREFCLK11_in;
wire GTREFCLK00_in;
wire GTREFCLK01_in;
wire GTREFCLK10_in;
wire GTREFCLK11_in;
wire GTSOUTHREFCLK00_in;
wire GTSOUTHREFCLK01_in;
wire GTSOUTHREFCLK10_in;
wire GTSOUTHREFCLK11_in;
wire PMASCANENB_in;
wire QDPMASCANMODEB_in;
wire QDPMASCANRSTEN_in;
wire QPLL0CLKRSVD0_in;
wire QPLL0CLKRSVD1_in;
wire QPLL0LOCKDETCLK_in;
wire QPLL0LOCKEN_in;
wire QPLL0PD_in;
wire QPLL0RESET_in;
wire QPLL1CLKRSVD0_in;
wire QPLL1CLKRSVD1_in;
wire QPLL1LOCKDETCLK_in;
wire QPLL1LOCKEN_in;
wire QPLL1PD_in;
wire QPLL1RESET_in;
wire RCALENB_in;
wire [15:0] DRPDI_in;
wire [2:0] QPLL0REFCLKSEL_in;
wire [2:0] QPLL1REFCLKSEL_in;
wire [3:0] RXRECCLK_in;
wire [4:0] BGRCALOVRD_in;
wire [4:0] QPLLRSVD2_in;
wire [4:0] QPLLRSVD3_in;
wire [7:0] PMARSVD0_in;
wire [7:0] PMARSVD1_in;
wire [7:0] PMASCANCLK_in;
wire [7:0] PMASCANIN_in;
wire [7:0] QPLLRSVD1_in;
wire [7:0] QPLLRSVD4_in;
wire [8:0] DRPADDR_in;
wire BGBYPASSB_delay;
wire BGMONITORENB_delay;
wire BGPDB_delay;
wire BGRCALOVRDENB_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire GTGREFCLK0_delay;
wire GTGREFCLK1_delay;
wire GTNORTHREFCLK00_delay;
wire GTNORTHREFCLK01_delay;
wire GTNORTHREFCLK10_delay;
wire GTNORTHREFCLK11_delay;
wire GTREFCLK00_delay;
wire GTREFCLK01_delay;
wire GTREFCLK10_delay;
wire GTREFCLK11_delay;
wire GTSOUTHREFCLK00_delay;
wire GTSOUTHREFCLK01_delay;
wire GTSOUTHREFCLK10_delay;
wire GTSOUTHREFCLK11_delay;
wire QPLL0CLKRSVD0_delay;
wire QPLL0CLKRSVD1_delay;
wire QPLL0LOCKDETCLK_delay;
wire QPLL0LOCKEN_delay;
wire QPLL0PD_delay;
wire QPLL0RESET_delay;
wire QPLL1CLKRSVD0_delay;
wire QPLL1CLKRSVD1_delay;
wire QPLL1LOCKDETCLK_delay;
wire QPLL1LOCKEN_delay;
wire QPLL1PD_delay;
wire QPLL1RESET_delay;
wire RCALENB_delay;
wire [15:0] DRPDI_delay;
wire [2:0] QPLL0REFCLKSEL_delay;
wire [2:0] QPLL1REFCLKSEL_delay;
wire [4:0] BGRCALOVRD_delay;
wire [4:0] QPLLRSVD2_delay;
wire [4:0] QPLLRSVD3_delay;
wire [7:0] PMARSVD0_delay;
wire [7:0] PMARSVD1_delay;
wire [7:0] QPLLRSVD1_delay;
wire [7:0] QPLLRSVD4_delay;
wire [8:0] DRPADDR_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay;
assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay;
assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay;
assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay;
assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay;
assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay;
assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay;
assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay;
assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay;
assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay;
assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay;
assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay;
assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay;
assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay;
assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay;
assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay;
assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay;
assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0;
assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1;
assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00;
assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01;
assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10;
assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11;
assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00;
assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01;
assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10;
assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11;
assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00;
assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01;
assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10;
assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11;
assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0;
assign #(inclk_delay) QPLL0CLKRSVD1_delay = QPLL0CLKRSVD1;
assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK;
assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0;
assign #(inclk_delay) QPLL1CLKRSVD1_delay = QPLL1CLKRSVD1;
assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK;
assign #(in_delay) BGBYPASSB_delay = BGBYPASSB;
assign #(in_delay) BGMONITORENB_delay = BGMONITORENB;
assign #(in_delay) BGPDB_delay = BGPDB;
assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB;
assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD;
assign #(in_delay) PMARSVD0_delay = PMARSVD0;
assign #(in_delay) PMARSVD1_delay = PMARSVD1;
assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN;
assign #(in_delay) QPLL0PD_delay = QPLL0PD;
assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL;
assign #(in_delay) QPLL0RESET_delay = QPLL0RESET;
assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN;
assign #(in_delay) QPLL1PD_delay = QPLL1PD;
assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL;
assign #(in_delay) QPLL1RESET_delay = QPLL1RESET;
assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1;
assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2;
assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3;
assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4;
assign #(in_delay) RCALENB_delay = RCALENB;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign PMARSVDOUT0_delay = PMARSVDOUT0_out;
assign PMARSVDOUT1_delay = PMARSVDOUT1_out;
assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out;
assign QPLL0LOCK_delay = QPLL0LOCK_out;
assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out;
assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out;
assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out;
assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out;
assign QPLL1LOCK_delay = QPLL1LOCK_out;
assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out;
assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out;
assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out;
assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out;
assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out;
assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out;
assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out;
assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out;
assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out;
assign BGBYPASSB_in = BGBYPASSB_delay;
assign BGMONITORENB_in = BGMONITORENB_delay;
assign BGPDB_in = BGPDB_delay;
assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay;
assign BGRCALOVRD_in = BGRCALOVRD_delay;
assign DRPADDR_in = DRPADDR_delay;
assign DRPCLK_in = DRPCLK_delay;
assign DRPDI_in = DRPDI_delay;
assign DRPEN_in = DRPEN_delay;
assign DRPWE_in = DRPWE_delay;
assign GTGREFCLK0_in = GTGREFCLK0_delay;
assign GTGREFCLK1_in = GTGREFCLK1_delay;
assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay;
assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay;
assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay;
assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay;
assign GTREFCLK00_in = GTREFCLK00_delay;
assign GTREFCLK01_in = GTREFCLK01_delay;
assign GTREFCLK10_in = GTREFCLK10_delay;
assign GTREFCLK11_in = GTREFCLK11_delay;
assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay;
assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay;
assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay;
assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay;
assign PMARSVD0_in = PMARSVD0_delay;
assign PMARSVD1_in = PMARSVD1_delay;
assign QPLL0CLKRSVD0_in = QPLL0CLKRSVD0_delay;
assign QPLL0CLKRSVD1_in = QPLL0CLKRSVD1_delay;
assign QPLL0LOCKDETCLK_in = QPLL0LOCKDETCLK_delay;
assign QPLL0LOCKEN_in = QPLL0LOCKEN_delay;
assign QPLL0PD_in = QPLL0PD_delay;
assign QPLL0REFCLKSEL_in = QPLL0REFCLKSEL_delay;
assign QPLL0RESET_in = QPLL0RESET_delay;
assign QPLL1CLKRSVD0_in = QPLL1CLKRSVD0_delay;
assign QPLL1CLKRSVD1_in = QPLL1CLKRSVD1_delay;
assign QPLL1LOCKDETCLK_in = QPLL1LOCKDETCLK_delay;
assign QPLL1LOCKEN_in = QPLL1LOCKEN_delay;
assign QPLL1PD_in = QPLL1PD_delay;
assign QPLL1REFCLKSEL_in = QPLL1REFCLKSEL_delay;
assign QPLL1RESET_in = QPLL1RESET_delay;
assign QPLLRSVD1_in = QPLLRSVD1_delay;
assign QPLLRSVD2_in = QPLLRSVD2_delay;
assign QPLLRSVD3_in = QPLLRSVD3_delay;
assign QPLLRSVD4_in = QPLLRSVD4_delay;
assign RCALENB_in = RCALENB_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((BIAS_CFG_RSVD_REG < 10'b0000000000) || (BIAS_CFG_RSVD_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute BIAS_CFG_RSVD on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, BIAS_CFG_RSVD_REG);
attr_err = 1'b1;
end
if ((QPLL0_CP_G3_REG < 10'b0000000000) || (QPLL0_CP_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_CP_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_CP_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_CP_REG < 10'b0000000000) || (QPLL0_CP_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_CP on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_CP_REG);
attr_err = 1'b1;
end
if ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL0_FBDIV_G3 on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL0_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL0_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL0_FBDIV_REG);
attr_err = 1'b1;
end
if ((QPLL0_LPF_G3_REG < 10'b0000000000) || (QPLL0_LPF_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_LPF_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_LPF_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_LPF_REG < 10'b0000000000) || (QPLL0_LPF_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_LPF on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_LPF_REG);
attr_err = 1'b1;
end
if ((QPLL0_REFCLK_DIV_REG != 2) &&
(QPLL0_REFCLK_DIV_REG != 1) &&
(QPLL0_REFCLK_DIV_REG != 3) &&
(QPLL0_REFCLK_DIV_REG != 4) &&
(QPLL0_REFCLK_DIV_REG != 5) &&
(QPLL0_REFCLK_DIV_REG != 6) &&
(QPLL0_REFCLK_DIV_REG != 8) &&
(QPLL0_REFCLK_DIV_REG != 10) &&
(QPLL0_REFCLK_DIV_REG != 12) &&
(QPLL0_REFCLK_DIV_REG != 16) &&
(QPLL0_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute QPLL0_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, QPLL0_REFCLK_DIV_REG, 2);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG0_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG0_REG);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG1_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG1_REG);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG2_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG2_REG);
attr_err = 1'b1;
end
if ((QPLL1_CP_G3_REG < 10'b0000000000) || (QPLL1_CP_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_CP_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_CP_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_CP_REG < 10'b0000000000) || (QPLL1_CP_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_CP on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_CP_REG);
attr_err = 1'b1;
end
if ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL1_FBDIV_G3 on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL1_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL1_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL1_FBDIV_REG);
attr_err = 1'b1;
end
if ((QPLL1_LPF_G3_REG < 10'b0000000000) || (QPLL1_LPF_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_LPF_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_LPF_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_LPF_REG < 10'b0000000000) || (QPLL1_LPF_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_LPF on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_LPF_REG);
attr_err = 1'b1;
end
if ((QPLL1_REFCLK_DIV_REG != 2) &&
(QPLL1_REFCLK_DIV_REG != 1) &&
(QPLL1_REFCLK_DIV_REG != 3) &&
(QPLL1_REFCLK_DIV_REG != 4) &&
(QPLL1_REFCLK_DIV_REG != 5) &&
(QPLL1_REFCLK_DIV_REG != 6) &&
(QPLL1_REFCLK_DIV_REG != 8) &&
(QPLL1_REFCLK_DIV_REG != 10) &&
(QPLL1_REFCLK_DIV_REG != 12) &&
(QPLL1_REFCLK_DIV_REG != 16) &&
(QPLL1_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute QPLL1_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, QPLL1_REFCLK_DIV_REG, 2);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG0_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG0_REG);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG1_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG1_REG);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG2_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG2_REG);
attr_err = 1'b1;
end
if ((RXRECCLKOUT0_SEL_REG < 2'b00) || (RXRECCLKOUT0_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXRECCLKOUT0_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXRECCLKOUT0_SEL_REG);
attr_err = 1'b1;
end
if ((RXRECCLKOUT1_SEL_REG < 2'b00) || (RXRECCLKOUT1_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXRECCLKOUT1_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXRECCLKOUT1_SEL_REG);
attr_err = 1'b1;
end
if ((SARC_EN_REG < 1'b0) || (SARC_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SARC_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SARC_EN_REG);
attr_err = 1'b1;
end
if ((SARC_SEL_REG < 1'b0) || (SARC_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SARC_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SARC_SEL_REG);
attr_err = 1'b1;
end
if ((SDM0DATA1_0_REG < 16'b0000000000000000) || (SDM0DATA1_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0DATA1_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM0DATA1_0_REG);
attr_err = 1'b1;
end
if ((SDM0DATA1_1_REG < 9'b000000000) || (SDM0DATA1_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0DATA1_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM0DATA1_1_REG);
attr_err = 1'b1;
end
if ((SDM0INITSEED0_0_REG < 16'b0000000000000000) || (SDM0INITSEED0_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0INITSEED0_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM0INITSEED0_0_REG);
attr_err = 1'b1;
end
if ((SDM0INITSEED0_1_REG < 9'b000000000) || (SDM0INITSEED0_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0INITSEED0_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM0INITSEED0_1_REG);
attr_err = 1'b1;
end
if ((SDM0_DATA_PIN_SEL_REG < 1'b0) || (SDM0_DATA_PIN_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SDM0_DATA_PIN_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SDM0_DATA_PIN_SEL_REG);
attr_err = 1'b1;
end
if ((SDM0_WIDTH_PIN_SEL_REG < 1'b0) || (SDM0_WIDTH_PIN_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SDM0_WIDTH_PIN_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SDM0_WIDTH_PIN_SEL_REG);
attr_err = 1'b1;
end
if ((SDM1DATA1_0_REG < 16'b0000000000000000) || (SDM1DATA1_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1DATA1_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM1DATA1_0_REG);
attr_err = 1'b1;
end
if ((SDM1DATA1_1_REG < 9'b000000000) || (SDM1DATA1_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1DATA1_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM1DATA1_1_REG);
attr_err = 1'b1;
end
if ((SDM1INITSEED0_0_REG < 16'b0000000000000000) || (SDM1INITSEED0_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1INITSEED0_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM1INITSEED0_0_REG);
attr_err = 1'b1;
end
if ((SDM1INITSEED0_1_REG < 9'b000000000) || (SDM1INITSEED0_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1INITSEED0_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM1INITSEED0_1_REG);
attr_err = 1'b1;
end
if ((SDM1_DATA_PIN_SEL_REG < 1'b0) || (SDM1_DATA_PIN_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SDM1_DATA_PIN_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SDM1_DATA_PIN_SEL_REG);
attr_err = 1'b1;
end
if ((SDM1_WIDTH_PIN_SEL_REG < 1'b0) || (SDM1_WIDTH_PIN_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SDM1_WIDTH_PIN_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SDM1_WIDTH_PIN_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_QPLL0REFCLK_SEL_REG < 3'b000) || (SIM_QPLL0REFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_QPLL0REFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_QPLL0REFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_QPLL1REFCLK_SEL_REG < 3'b000) || (SIM_QPLL1REFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_QPLL1REFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_QPLL1REFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RESET_SPEEDUP on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2")) begin
$display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2.", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK_in = 8'b11111111; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 8'b11111111; // tie off
assign QDPMASCANMODEB_in = 1'b1; // tie off
assign QDPMASCANRSTEN_in = 1'b1; // tie off
assign RXRECCLK_in = 4'b1111; // tie off
SIP_GTHE3_COMMON SIP_GTHE3_COMMON_INST (
.AEN_BGBS0 (AEN_BGBS0_REG),
.AEN_BGBS1 (AEN_BGBS1_REG),
.AEN_MASTER0 (AEN_MASTER0_REG),
.AEN_MASTER1 (AEN_MASTER1_REG),
.AEN_PD0 (AEN_PD0_REG),
.AEN_PD1 (AEN_PD1_REG),
.AEN_QPLL0 (AEN_QPLL0_REG),
.AEN_QPLL1 (AEN_QPLL1_REG),
.AEN_REFCLK0 (AEN_REFCLK0_REG),
.AEN_REFCLK1 (AEN_REFCLK1_REG),
.AEN_RESET0 (AEN_RESET0_REG),
.AEN_RESET1 (AEN_RESET1_REG),
.AQDMUXSEL1 (AQDMUXSEL1_REG),
.AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG),
.AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG),
.A_BGMONITOREN (A_BGMONITOREN_REG),
.A_BGPD (A_BGPD_REG),
.A_GTREFCLKPD0 (A_GTREFCLKPD0_REG),
.A_GTREFCLKPD1 (A_GTREFCLKPD1_REG),
.A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG),
.A_QPLL0PD (A_QPLL0PD_REG),
.A_QPLL0RESET (A_QPLL0RESET_REG),
.A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG),
.A_QPLL1PD (A_QPLL1PD_REG),
.A_QPLL1RESET (A_QPLL1RESET_REG),
.BIAS_CFG0 (BIAS_CFG0_REG),
.BIAS_CFG1 (BIAS_CFG1_REG),
.BIAS_CFG2 (BIAS_CFG2_REG),
.BIAS_CFG3 (BIAS_CFG3_REG),
.BIAS_CFG4 (BIAS_CFG4_REG),
.BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG),
.COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG),
.COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG),
.COMMON_CFG0 (COMMON_CFG0_REG),
.COMMON_CFG1 (COMMON_CFG1_REG),
.COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG),
.POR_CFG (POR_CFG_REG),
.PPF0_CFG (PPF0_CFG_REG),
.PPF1_CFG (PPF1_CFG_REG),
.QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG),
.QPLL0_CFG0 (QPLL0_CFG0_REG),
.QPLL0_CFG1 (QPLL0_CFG1_REG),
.QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG),
.QPLL0_CFG2 (QPLL0_CFG2_REG),
.QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG),
.QPLL0_CFG3 (QPLL0_CFG3_REG),
.QPLL0_CFG4 (QPLL0_CFG4_REG),
.QPLL0_CP (QPLL0_CP_REG),
.QPLL0_CP_G3 (QPLL0_CP_G3_REG),
.QPLL0_FBDIV (QPLL0_FBDIV_REG),
.QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG),
.QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG),
.QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG),
.QPLL0_IPS_EN (QPLL0_IPS_EN_REG),
.QPLL0_IPS_REFCLK_SEL (QPLL0_IPS_REFCLK_SEL_REG),
.QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG),
.QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG),
.QPLL0_LPF (QPLL0_LPF_REG),
.QPLL0_LPF_G3 (QPLL0_LPF_G3_REG),
.QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG),
.QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG),
.QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG),
.QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG),
.QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG),
.QPLL1_CFG0 (QPLL1_CFG0_REG),
.QPLL1_CFG1 (QPLL1_CFG1_REG),
.QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG),
.QPLL1_CFG2 (QPLL1_CFG2_REG),
.QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG),
.QPLL1_CFG3 (QPLL1_CFG3_REG),
.QPLL1_CFG4 (QPLL1_CFG4_REG),
.QPLL1_CP (QPLL1_CP_REG),
.QPLL1_CP_G3 (QPLL1_CP_G3_REG),
.QPLL1_FBDIV (QPLL1_FBDIV_REG),
.QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG),
.QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG),
.QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG),
.QPLL1_IPS_EN (QPLL1_IPS_EN_REG),
.QPLL1_IPS_REFCLK_SEL (QPLL1_IPS_REFCLK_SEL_REG),
.QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG),
.QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG),
.QPLL1_LPF (QPLL1_LPF_REG),
.QPLL1_LPF_G3 (QPLL1_LPF_G3_REG),
.QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG),
.QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG),
.QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG),
.QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG),
.RCALSAP_TESTEN (RCALSAP_TESTEN_REG),
.RCAL_APROBE (RCAL_APROBE_REG),
.REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG),
.REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG),
.REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG),
.REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG),
.REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG),
.REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG),
.RSVD_ATTR0 (RSVD_ATTR0_REG),
.RSVD_ATTR1 (RSVD_ATTR1_REG),
.RSVD_ATTR2 (RSVD_ATTR2_REG),
.RSVD_ATTR3 (RSVD_ATTR3_REG),
.RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG),
.RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG),
.SARC_EN (SARC_EN_REG),
.SARC_SEL (SARC_SEL_REG),
.SDM0DATA1_0 (SDM0DATA1_0_REG),
.SDM0DATA1_1 (SDM0DATA1_1_REG),
.SDM0INITSEED0_0 (SDM0INITSEED0_0_REG),
.SDM0INITSEED0_1 (SDM0INITSEED0_1_REG),
.SDM0_DATA_PIN_SEL (SDM0_DATA_PIN_SEL_REG),
.SDM0_WIDTH_PIN_SEL (SDM0_WIDTH_PIN_SEL_REG),
.SDM1DATA1_0 (SDM1DATA1_0_REG),
.SDM1DATA1_1 (SDM1DATA1_1_REG),
.SDM1INITSEED0_0 (SDM1INITSEED0_0_REG),
.SDM1INITSEED0_1 (SDM1INITSEED0_1_REG),
.SDM1_DATA_PIN_SEL (SDM1_DATA_PIN_SEL_REG),
.SDM1_WIDTH_PIN_SEL (SDM1_WIDTH_PIN_SEL_REG),
.VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.PMARSVDOUT0 (PMARSVDOUT0_out),
.PMARSVDOUT1 (PMARSVDOUT1_out),
.PMASCANOUT (PMASCANOUT_out),
.QPLL0FBCLKLOST (QPLL0FBCLKLOST_out),
.QPLL0LOCK (QPLL0LOCK_out),
.QPLL0OUTCLK (QPLL0OUTCLK_out),
.QPLL0OUTREFCLK (QPLL0OUTREFCLK_out),
.QPLL0REFCLKLOST (QPLL0REFCLKLOST_out),
.QPLL1FBCLKLOST (QPLL1FBCLKLOST_out),
.QPLL1LOCK (QPLL1LOCK_out),
.QPLL1OUTCLK (QPLL1OUTCLK_out),
.QPLL1OUTREFCLK (QPLL1OUTREFCLK_out),
.QPLL1REFCLKLOST (QPLL1REFCLKLOST_out),
.QPLLDMONITOR0 (QPLLDMONITOR0_out),
.QPLLDMONITOR1 (QPLLDMONITOR1_out),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out),
.RXRECCLK0_SEL (RXRECCLK0_SEL_out),
.RXRECCLK1_SEL (RXRECCLK1_SEL_out),
.SARCCLK (SARCCLK_out),
.BGBYPASSB (BGBYPASSB_in),
.BGMONITORENB (BGMONITORENB_in),
.BGPDB (BGPDB_in),
.BGRCALOVRD (BGRCALOVRD_in),
.BGRCALOVRDENB (BGRCALOVRDENB_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.GTGREFCLK0 (GTGREFCLK0_in),
.GTGREFCLK1 (GTGREFCLK1_in),
.GTNORTHREFCLK00 (GTNORTHREFCLK00_in),
.GTNORTHREFCLK01 (GTNORTHREFCLK01_in),
.GTNORTHREFCLK10 (GTNORTHREFCLK10_in),
.GTNORTHREFCLK11 (GTNORTHREFCLK11_in),
.GTREFCLK00 (GTREFCLK00_in),
.GTREFCLK01 (GTREFCLK01_in),
.GTREFCLK10 (GTREFCLK10_in),
.GTREFCLK11 (GTREFCLK11_in),
.GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in),
.GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in),
.GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in),
.GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in),
.PMARSVD0 (PMARSVD0_in),
.PMARSVD1 (PMARSVD1_in),
.PMASCANCLK (PMASCANCLK_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.QDPMASCANMODEB (QDPMASCANMODEB_in),
.QDPMASCANRSTEN (QDPMASCANRSTEN_in),
.QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in),
.QPLL0CLKRSVD1 (QPLL0CLKRSVD1_in),
.QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in),
.QPLL0LOCKEN (QPLL0LOCKEN_in),
.QPLL0PD (QPLL0PD_in),
.QPLL0REFCLKSEL (QPLL0REFCLKSEL_in),
.QPLL0RESET (QPLL0RESET_in),
.QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in),
.QPLL1CLKRSVD1 (QPLL1CLKRSVD1_in),
.QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in),
.QPLL1LOCKEN (QPLL1LOCKEN_in),
.QPLL1PD (QPLL1PD_in),
.QPLL1REFCLKSEL (QPLL1REFCLKSEL_in),
.QPLL1RESET (QPLL1RESET_in),
.QPLLRSVD1 (QPLLRSVD1_in),
.QPLLRSVD2 (QPLLRSVD2_in),
.QPLLRSVD3 (QPLLRSVD3_in),
.QPLLRSVD4 (QPLLRSVD4_in),
.RCALENB (RCALENB_in),
.RXRECCLK (RXRECCLK_in),
.GSR (glblGSR)
);
specify
(DRPCLK *> DRPDO) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTPE2_CHANNEL.v 0000664 0000000 0000000 00000476540 12327044266 0023413 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTPE2_CHANNEL.uniprim.v
// \ \ / \
// \__\/\__ \
//
// 11/8/12 - 686589 - YML default changes
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTPE2_CHANNEL (
DMONITOROUT,
DRPDO,
DRPRDY,
EYESCANDATAERROR,
GTPTXN,
GTPTXP,
PCSRSVDOUT,
PHYSTATUS,
PMARSVDOUT0,
PMARSVDOUT1,
RXBUFSTATUS,
RXBYTEISALIGNED,
RXBYTEREALIGN,
RXCDRLOCK,
RXCHANBONDSEQ,
RXCHANISALIGNED,
RXCHANREALIGN,
RXCHARISCOMMA,
RXCHARISK,
RXCHBONDO,
RXCLKCORCNT,
RXCOMINITDET,
RXCOMMADET,
RXCOMSASDET,
RXCOMWAKEDET,
RXDATA,
RXDATAVALID,
RXDISPERR,
RXDLYSRESETDONE,
RXELECIDLE,
RXHEADER,
RXHEADERVALID,
RXNOTINTABLE,
RXOSINTDONE,
RXOSINTSTARTED,
RXOSINTSTROBEDONE,
RXOSINTSTROBESTARTED,
RXOUTCLK,
RXOUTCLKFABRIC,
RXOUTCLKPCS,
RXPHALIGNDONE,
RXPHMONITOR,
RXPHSLIPMONITOR,
RXPMARESETDONE,
RXPRBSERR,
RXRATEDONE,
RXRESETDONE,
RXSTARTOFSEQ,
RXSTATUS,
RXSYNCDONE,
RXSYNCOUT,
RXVALID,
TXBUFSTATUS,
TXCOMFINISH,
TXDLYSRESETDONE,
TXGEARBOXREADY,
TXOUTCLK,
TXOUTCLKFABRIC,
TXOUTCLKPCS,
TXPHALIGNDONE,
TXPHINITDONE,
TXPMARESETDONE,
TXRATEDONE,
TXRESETDONE,
TXSYNCDONE,
TXSYNCOUT,
CFGRESET,
CLKRSVD0,
CLKRSVD1,
DMONFIFORESET,
DMONITORCLK,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
EYESCANMODE,
EYESCANRESET,
EYESCANTRIGGER,
GTPRXN,
GTPRXP,
GTRESETSEL,
GTRSVD,
GTRXRESET,
GTTXRESET,
LOOPBACK,
PCSRSVDIN,
PLL0CLK,
PLL0REFCLK,
PLL1CLK,
PLL1REFCLK,
PMARSVDIN0,
PMARSVDIN1,
PMARSVDIN2,
PMARSVDIN3,
PMARSVDIN4,
RESETOVRD,
RX8B10BEN,
RXADAPTSELTEST,
RXBUFRESET,
RXCDRFREQRESET,
RXCDRHOLD,
RXCDROVRDEN,
RXCDRRESET,
RXCDRRESETRSV,
RXCHBONDEN,
RXCHBONDI,
RXCHBONDLEVEL,
RXCHBONDMASTER,
RXCHBONDSLAVE,
RXCOMMADETEN,
RXDDIEN,
RXDFEXYDEN,
RXDLYBYPASS,
RXDLYEN,
RXDLYOVRDEN,
RXDLYSRESET,
RXELECIDLEMODE,
RXGEARBOXSLIP,
RXLPMHFHOLD,
RXLPMHFOVRDEN,
RXLPMLFHOLD,
RXLPMLFOVRDEN,
RXLPMOSINTNTRLEN,
RXLPMRESET,
RXMCOMMAALIGNEN,
RXOOBRESET,
RXOSCALRESET,
RXOSHOLD,
RXOSINTCFG,
RXOSINTEN,
RXOSINTHOLD,
RXOSINTID0,
RXOSINTNTRLEN,
RXOSINTOVRDEN,
RXOSINTPD,
RXOSINTSTROBE,
RXOSINTTESTOVRDEN,
RXOSOVRDEN,
RXOUTCLKSEL,
RXPCOMMAALIGNEN,
RXPCSRESET,
RXPD,
RXPHALIGN,
RXPHALIGNEN,
RXPHDLYPD,
RXPHDLYRESET,
RXPHOVRDEN,
RXPMARESET,
RXPOLARITY,
RXPRBSCNTRESET,
RXPRBSSEL,
RXRATE,
RXRATEMODE,
RXSLIDE,
RXSYNCALLIN,
RXSYNCIN,
RXSYNCMODE,
RXSYSCLKSEL,
RXUSERRDY,
RXUSRCLK,
RXUSRCLK2,
SETERRSTATUS,
SIGVALIDCLK,
TSTIN,
TX8B10BBYPASS,
TX8B10BEN,
TXBUFDIFFCTRL,
TXCHARDISPMODE,
TXCHARDISPVAL,
TXCHARISK,
TXCOMINIT,
TXCOMSAS,
TXCOMWAKE,
TXDATA,
TXDEEMPH,
TXDETECTRX,
TXDIFFCTRL,
TXDIFFPD,
TXDLYBYPASS,
TXDLYEN,
TXDLYHOLD,
TXDLYOVRDEN,
TXDLYSRESET,
TXDLYUPDOWN,
TXELECIDLE,
TXHEADER,
TXINHIBIT,
TXMAINCURSOR,
TXMARGIN,
TXOUTCLKSEL,
TXPCSRESET,
TXPD,
TXPDELECIDLEMODE,
TXPHALIGN,
TXPHALIGNEN,
TXPHDLYPD,
TXPHDLYRESET,
TXPHDLYTSTCLK,
TXPHINIT,
TXPHOVRDEN,
TXPIPPMEN,
TXPIPPMOVRDEN,
TXPIPPMPD,
TXPIPPMSEL,
TXPIPPMSTEPSIZE,
TXPISOPD,
TXPMARESET,
TXPOLARITY,
TXPOSTCURSOR,
TXPOSTCURSORINV,
TXPRBSFORCEERR,
TXPRBSSEL,
TXPRECURSOR,
TXPRECURSORINV,
TXRATE,
TXRATEMODE,
TXSEQUENCE,
TXSTARTSEQ,
TXSWING,
TXSYNCALLIN,
TXSYNCIN,
TXSYNCMODE,
TXSYSCLKSEL,
TXUSERRDY,
TXUSRCLK,
TXUSRCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter integer ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
parameter [6:0] CFOK_CFG2 = 7'b0100000;
parameter [6:0] CFOK_CFG3 = 7'b0100000;
parameter [0:0] CFOK_CFG4 = 1'b0;
parameter [1:0] CFOK_CFG5 = 2'b00;
parameter [3:0] CFOK_CFG6 = 4'b0000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter integer CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter [0:0] CLK_COMMON_SWING = 1'b0;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 20;
parameter integer CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter integer CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
parameter [31:0] PMA_RSV = 32'h00000333;
parameter [31:0] PMA_RSV2 = 32'h00002050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [3:0] PMA_RSV4 = 4'b0000;
parameter [0:0] PMA_RSV5 = 1'b0;
parameter [0:0] PMA_RSV6 = 1'b0;
parameter [0:0] PMA_RSV7 = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter integer RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter integer RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [15:0] RXDLY_CFG = 16'h0010;
parameter [8:0] RXDLY_LCFG = 9'h020;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
parameter [3:0] RXLPM_CFG = 4'b0110;
parameter [0:0] RXLPM_CFG1 = 1'b0;
parameter [0:0] RXLPM_CM_CFG = 1'b0;
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084000;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [2:0] RXPI_CFG0 = 3'b000;
parameter [0:0] RXPI_CFG1 = 1'b0;
parameter [0:0] RXPI_CFG2 = 1'b0;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter integer RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_EN = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter integer SAS_MAX_COM = 64;
parameter integer SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter integer SATA_MAX_BURST = 8;
parameter integer SATA_MAX_INIT = 21;
parameter integer SATA_MAX_WAKE = 7;
parameter integer SATA_MIN_BURST = 4;
parameter integer SATA_MIN_INIT = 12;
parameter integer SATA_MIN_WAKE = 4;
parameter SATA_PLL_CFG = "VCO_3000MHZ";
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h0010;
parameter [8:0] TXDLY_LCFG = 9'h020;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084000;
parameter [15:0] TXPH_CFG = 16'h0400;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b000;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_EN = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output EYESCANDATAERROR;
output GTPTXN;
output GTPTXP;
output PHYSTATUS;
output PMARSVDOUT0;
output PMARSVDOUT1;
output RXBYTEISALIGNED;
output RXBYTEREALIGN;
output RXCDRLOCK;
output RXCHANBONDSEQ;
output RXCHANISALIGNED;
output RXCHANREALIGN;
output RXCOMINITDET;
output RXCOMMADET;
output RXCOMSASDET;
output RXCOMWAKEDET;
output RXDLYSRESETDONE;
output RXELECIDLE;
output RXHEADERVALID;
output RXOSINTDONE;
output RXOSINTSTARTED;
output RXOSINTSTROBEDONE;
output RXOSINTSTROBESTARTED;
output RXOUTCLK;
output RXOUTCLKFABRIC;
output RXOUTCLKPCS;
output RXPHALIGNDONE;
output RXPMARESETDONE;
output RXPRBSERR;
output RXRATEDONE;
output RXRESETDONE;
output RXSYNCDONE;
output RXSYNCOUT;
output RXVALID;
output TXCOMFINISH;
output TXDLYSRESETDONE;
output TXGEARBOXREADY;
output TXOUTCLK;
output TXOUTCLKFABRIC;
output TXOUTCLKPCS;
output TXPHALIGNDONE;
output TXPHINITDONE;
output TXPMARESETDONE;
output TXRATEDONE;
output TXRESETDONE;
output TXSYNCDONE;
output TXSYNCOUT;
output [14:0] DMONITOROUT;
output [15:0] DRPDO;
output [15:0] PCSRSVDOUT;
output [1:0] RXCLKCORCNT;
output [1:0] RXDATAVALID;
output [1:0] RXSTARTOFSEQ;
output [1:0] TXBUFSTATUS;
output [2:0] RXBUFSTATUS;
output [2:0] RXHEADER;
output [2:0] RXSTATUS;
output [31:0] RXDATA;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [3:0] RXCHBONDO;
output [3:0] RXDISPERR;
output [3:0] RXNOTINTABLE;
output [4:0] RXPHMONITOR;
output [4:0] RXPHSLIPMONITOR;
input CFGRESET;
input CLKRSVD0;
input CLKRSVD1;
input DMONFIFORESET;
input DMONITORCLK;
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
input GTPRXN;
input GTPRXP;
input GTRESETSEL;
input GTRXRESET;
input GTTXRESET;
input PLL0CLK;
input PLL0REFCLK;
input PLL1CLK;
input PLL1REFCLK;
input PMARSVDIN0;
input PMARSVDIN1;
input PMARSVDIN2;
input PMARSVDIN3;
input PMARSVDIN4;
input RESETOVRD;
input RX8B10BEN;
input RXBUFRESET;
input RXCDRFREQRESET;
input RXCDRHOLD;
input RXCDROVRDEN;
input RXCDRRESET;
input RXCDRRESETRSV;
input RXCHBONDEN;
input RXCHBONDMASTER;
input RXCHBONDSLAVE;
input RXCOMMADETEN;
input RXDDIEN;
input RXDFEXYDEN;
input RXDLYBYPASS;
input RXDLYEN;
input RXDLYOVRDEN;
input RXDLYSRESET;
input RXGEARBOXSLIP;
input RXLPMHFHOLD;
input RXLPMHFOVRDEN;
input RXLPMLFHOLD;
input RXLPMLFOVRDEN;
input RXLPMOSINTNTRLEN;
input RXLPMRESET;
input RXMCOMMAALIGNEN;
input RXOOBRESET;
input RXOSCALRESET;
input RXOSHOLD;
input RXOSINTEN;
input RXOSINTHOLD;
input RXOSINTNTRLEN;
input RXOSINTOVRDEN;
input RXOSINTPD;
input RXOSINTSTROBE;
input RXOSINTTESTOVRDEN;
input RXOSOVRDEN;
input RXPCOMMAALIGNEN;
input RXPCSRESET;
input RXPHALIGN;
input RXPHALIGNEN;
input RXPHDLYPD;
input RXPHDLYRESET;
input RXPHOVRDEN;
input RXPMARESET;
input RXPOLARITY;
input RXPRBSCNTRESET;
input RXRATEMODE;
input RXSLIDE;
input RXSYNCALLIN;
input RXSYNCIN;
input RXSYNCMODE;
input RXUSERRDY;
input RXUSRCLK2;
input RXUSRCLK;
input SETERRSTATUS;
input SIGVALIDCLK;
input TX8B10BEN;
input TXCOMINIT;
input TXCOMSAS;
input TXCOMWAKE;
input TXDEEMPH;
input TXDETECTRX;
input TXDIFFPD;
input TXDLYBYPASS;
input TXDLYEN;
input TXDLYHOLD;
input TXDLYOVRDEN;
input TXDLYSRESET;
input TXDLYUPDOWN;
input TXELECIDLE;
input TXINHIBIT;
input TXPCSRESET;
input TXPDELECIDLEMODE;
input TXPHALIGN;
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
input TXPIPPMEN;
input TXPIPPMOVRDEN;
input TXPIPPMPD;
input TXPIPPMSEL;
input TXPISOPD;
input TXPMARESET;
input TXPOLARITY;
input TXPOSTCURSORINV;
input TXPRBSFORCEERR;
input TXPRECURSORINV;
input TXRATEMODE;
input TXSTARTSEQ;
input TXSWING;
input TXSYNCALLIN;
input TXSYNCIN;
input TXSYNCMODE;
input TXUSERRDY;
input TXUSRCLK2;
input TXUSRCLK;
input [13:0] RXADAPTSELTEST;
input [15:0] DRPDI;
input [15:0] GTRSVD;
input [15:0] PCSRSVDIN;
input [19:0] TSTIN;
input [1:0] RXELECIDLEMODE;
input [1:0] RXPD;
input [1:0] RXSYSCLKSEL;
input [1:0] TXPD;
input [1:0] TXSYSCLKSEL;
input [2:0] LOOPBACK;
input [2:0] RXCHBONDLEVEL;
input [2:0] RXOUTCLKSEL;
input [2:0] RXPRBSSEL;
input [2:0] RXRATE;
input [2:0] TXBUFDIFFCTRL;
input [2:0] TXHEADER;
input [2:0] TXMARGIN;
input [2:0] TXOUTCLKSEL;
input [2:0] TXPRBSSEL;
input [2:0] TXRATE;
input [31:0] TXDATA;
input [3:0] RXCHBONDI;
input [3:0] RXOSINTCFG;
input [3:0] RXOSINTID0;
input [3:0] TX8B10BBYPASS;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [3:0] TXDIFFCTRL;
input [4:0] TXPIPPMSTEPSIZE;
input [4:0] TXPOSTCURSOR;
input [4:0] TXPRECURSOR;
input [6:0] TXMAINCURSOR;
input [6:0] TXSEQUENCE;
input [8:0] DRPADDR;
reg SIM_RECEIVER_DETECT_PASS_BINARY;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] ACJTAG_DEBUG_MODE_BINARY;
reg [0:0] ACJTAG_MODE_BINARY;
reg [0:0] ACJTAG_RESET_BINARY;
reg [0:0] ALIGN_COMMA_DOUBLE_BINARY;
reg [0:0] ALIGN_MCOMMA_DET_BINARY;
reg [0:0] ALIGN_PCOMMA_DET_BINARY;
reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY;
reg [0:0] CFOK_CFG4_BINARY;
reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY;
reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY;
reg [0:0] CLK_COMMON_SWING_BINARY;
reg [0:0] CLK_CORRECT_USE_BINARY;
reg [0:0] CLK_COR_KEEP_IDLE_BINARY;
reg [0:0] CLK_COR_PRECEDENCE_BINARY;
reg [0:0] CLK_COR_SEQ_2_USE_BINARY;
reg [0:0] DEC_MCOMMA_DETECT_BINARY;
reg [0:0] DEC_PCOMMA_DETECT_BINARY;
reg [0:0] DEC_VALID_COMMA_ONLY_BINARY;
reg [0:0] ES_CLK_PHASE_SEL_BINARY;
reg [0:0] ES_ERRDET_EN_BINARY;
reg [0:0] ES_EYE_SCAN_EN_BINARY;
reg [0:0] FTS_LANE_DESKEW_EN_BINARY;
reg [0:0] LOOPBACK_CFG_BINARY;
reg [0:0] PCS_PCIE_EN_BINARY;
reg [0:0] PMA_LOOPBACK_CFG_BINARY;
reg [0:0] PMA_RSV5_BINARY;
reg [0:0] PMA_RSV6_BINARY;
reg [0:0] PMA_RSV7_BINARY;
reg [0:0] RXBUF_ADDR_MODE_BINARY;
reg [0:0] RXBUF_EN_BINARY;
reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY;
reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY;
reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY;
reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] RXBUF_THRESH_OVRD_BINARY;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY;
reg [0:0] RXGEARBOX_EN_BINARY;
reg [0:0] RXLPM_BIAS_STARTUP_DISABLE_BINARY;
reg [0:0] RXLPM_CFG1_BINARY;
reg [0:0] RXLPM_CM_CFG_BINARY;
reg [0:0] RXLPM_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXLPM_INCM_CFG_BINARY;
reg [0:0] RXLPM_IPCM_CFG_BINARY;
reg [0:0] RXOOB_CLK_CFG_BINARY;
reg [0:0] RXPI_CFG1_BINARY;
reg [0:0] RXPI_CFG2_BINARY;
reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY;
reg [0:0] RXSYNC_MULTILANE_BINARY;
reg [0:0] RXSYNC_OVRD_BINARY;
reg [0:0] RXSYNC_SKIP_DA_BINARY;
reg [0:0] RX_CLKMUX_EN_BINARY;
reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY;
reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY;
reg [0:0] RX_XCLK_SEL_BINARY;
reg [0:0] SHOW_REALIGN_COMMA_BINARY;
reg [0:0] TXBUF_EN_BINARY;
reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] TXGEARBOX_EN_BINARY;
reg [0:0] TXOOB_CFG_BINARY;
reg [0:0] TXPI_CFG3_BINARY;
reg [0:0] TXPI_CFG4_BINARY;
reg [0:0] TXPI_GREY_SEL_BINARY;
reg [0:0] TXPI_INVSTROBE_SEL_BINARY;
reg [0:0] TXPI_PPMCLK_SEL_BINARY;
reg [0:0] TXSYNC_MULTILANE_BINARY;
reg [0:0] TXSYNC_OVRD_BINARY;
reg [0:0] TXSYNC_SKIP_DA_BINARY;
reg [0:0] TX_CLKMUX_EN_BINARY;
reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY;
reg [0:0] TX_MAINCURSOR_SEL_BINARY;
reg [0:0] TX_PREDRIVER_MODE_BINARY;
reg [0:0] TX_XCLK_SEL_BINARY;
reg [0:0] UCODEER_CLR_BINARY;
reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY;
reg [12:0] RX_OS_CFG_BINARY;
reg [13:0] RXLPM_HF_CFG_BINARY;
reg [13:0] RX_DEBUG_CFG_BINARY;
reg [14:0] TERM_RCAL_CFG_BINARY;
reg [15:0] RX_BIAS_CFG_BINARY;
reg [17:0] RXLPM_LF_CFG_BINARY;
reg [19:0] ADAPT_CFG0_BINARY;
reg [1:0] ALIGN_COMMA_WORD_BINARY;
reg [1:0] CFOK_CFG5_BINARY;
reg [1:0] CHAN_BOND_SEQ_LEN_BINARY;
reg [1:0] CLK_COR_SEQ_LEN_BINARY;
reg [1:0] OUTREFCLK_SEL_INV_BINARY;
reg [1:0] PMA_RSV3_BINARY;
reg [1:0] RXSLIDE_MODE_BINARY;
reg [1:0] RX_CM_SEL_BINARY;
reg [1:0] SATA_PLL_CFG_BINARY;
reg [1:0] TXPI_CFG0_BINARY;
reg [1:0] TXPI_CFG1_BINARY;
reg [1:0] TXPI_CFG2_BINARY;
reg [2:0] GEARBOX_MODE_BINARY;
reg [2:0] RXLPM_GC_CFG2_BINARY;
reg [2:0] RXLPM_OSINT_CFG_BINARY;
reg [2:0] RXOUT_DIV_BINARY;
reg [2:0] RXPI_CFG0_BINARY;
reg [2:0] RX_DATA_WIDTH_BINARY;
reg [2:0] SATA_BURST_VAL_BINARY;
reg [2:0] SATA_EIDLE_VAL_BINARY;
reg [2:0] TERM_RCAL_OVRD_BINARY;
reg [2:0] TXOUT_DIV_BINARY;
reg [2:0] TXPI_CFG5_BINARY;
reg [2:0] TXPI_SYNFREQ_PPM_BINARY;
reg [2:0] TX_DATA_WIDTH_BINARY;
reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY;
reg [2:0] TX_RXDETECT_REF_BINARY;
reg [3:0] CFOK_CFG6_BINARY;
reg [3:0] CHAN_BOND_MAX_SKEW_BINARY;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY;
reg [3:0] FTS_LANE_DESKEW_CFG_BINARY;
reg [3:0] PMA_RSV4_BINARY;
reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY;
reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY;
reg [3:0] RXLPM_CFG_BINARY;
reg [3:0] RXLPM_HF_CFG3_BINARY;
reg [3:0] RXSLIDE_AUTO_WAIT_BINARY;
reg [3:0] RX_CM_TRIM_BINARY;
reg [3:0] SATA_BURST_SEQ_LEN_BINARY;
reg [42:0] CFOK_CFG_BINARY;
reg [4:0] CLK_COR_REPEAT_WAIT_BINARY;
reg [4:0] ES_PRESCALE_BINARY;
reg [4:0] RXBUFRESET_TIME_BINARY;
reg [4:0] RXCDRFREQRESET_TIME_BINARY;
reg [4:0] RXCDRPHRESET_TIME_BINARY;
reg [4:0] RXISCANRESET_TIME_BINARY;
reg [4:0] RXLPM_HF_CFG2_BINARY;
reg [4:0] RXLPM_LF_CFG2_BINARY;
reg [4:0] RXOSCALRESET_TIMEOUT_BINARY;
reg [4:0] RXOSCALRESET_TIME_BINARY;
reg [4:0] RXPCSRESET_TIME_BINARY;
reg [4:0] RXPH_MONITOR_SEL_BINARY;
reg [4:0] RXPMARESET_TIME_BINARY;
reg [4:0] RX_CLK25_DIV_BINARY;
reg [4:0] RX_SIG_VALID_DLY_BINARY;
reg [4:0] TXPCSRESET_TIME_BINARY;
reg [4:0] TXPH_MONITOR_SEL_BINARY;
reg [4:0] TXPMARESET_TIME_BINARY;
reg [4:0] TX_CLK25_DIV_BINARY;
reg [4:0] TX_DRIVE_MODE_BINARY;
reg [5:0] CLK_COR_MAX_LAT_BINARY;
reg [5:0] CLK_COR_MIN_LAT_BINARY;
reg [5:0] ES_CONTROL_BINARY;
reg [5:0] RXBUF_THRESH_OVFLW_BINARY;
reg [5:0] RXBUF_THRESH_UNDFLW_BINARY;
reg [5:0] RXCDR_LOCK_CFG_BINARY;
reg [5:0] RX_BUFFER_CFG_BINARY;
reg [5:0] RX_DDI_SEL_BINARY;
reg [5:0] SAS_MIN_COM_BINARY;
reg [5:0] SATA_MAX_BURST_BINARY;
reg [5:0] SATA_MAX_INIT_BINARY;
reg [5:0] SATA_MAX_WAKE_BINARY;
reg [5:0] SATA_MIN_BURST_BINARY;
reg [5:0] SATA_MIN_INIT_BINARY;
reg [5:0] SATA_MIN_WAKE_BINARY;
reg [5:0] TX_DEEMPH0_BINARY;
reg [5:0] TX_DEEMPH1_BINARY;
reg [6:0] CFOK_CFG2_BINARY;
reg [6:0] CFOK_CFG3_BINARY;
reg [6:0] RXLPMRESET_TIME_BINARY;
reg [6:0] RXOOB_CFG_BINARY;
reg [6:0] SAS_MAX_COM_BINARY;
reg [6:0] TX_MARGIN_FULL_0_BINARY;
reg [6:0] TX_MARGIN_FULL_1_BINARY;
reg [6:0] TX_MARGIN_FULL_2_BINARY;
reg [6:0] TX_MARGIN_FULL_3_BINARY;
reg [6:0] TX_MARGIN_FULL_4_BINARY;
reg [6:0] TX_MARGIN_LOW_0_BINARY;
reg [6:0] TX_MARGIN_LOW_1_BINARY;
reg [6:0] TX_MARGIN_LOW_2_BINARY;
reg [6:0] TX_MARGIN_LOW_3_BINARY;
reg [6:0] TX_MARGIN_LOW_4_BINARY;
reg [7:0] TXPI_PPM_CFG_BINARY;
reg [8:0] ES_VERT_OFFSET_BINARY;
reg [8:0] RXLPM_GC_CFG_BINARY;
reg [9:0] ALIGN_COMMA_ENABLE_BINARY;
reg [9:0] ALIGN_MCOMMA_VALUE_BINARY;
reg [9:0] ALIGN_PCOMMA_VALUE_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_4_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_4_BINARY;
reg [9:0] CLK_COR_SEQ_1_1_BINARY;
reg [9:0] CLK_COR_SEQ_1_2_BINARY;
reg [9:0] CLK_COR_SEQ_1_3_BINARY;
reg [9:0] CLK_COR_SEQ_1_4_BINARY;
reg [9:0] CLK_COR_SEQ_2_1_BINARY;
reg [9:0] CLK_COR_SEQ_2_2_BINARY;
reg [9:0] CLK_COR_SEQ_2_3_BINARY;
reg [9:0] CLK_COR_SEQ_2_4_BINARY;
reg [9:0] ES_PMA_CFG_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (ALIGN_COMMA_DOUBLE)
"FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0;
"TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE);
$finish;
end
endcase
case (ALIGN_MCOMMA_DET)
"TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET);
$finish;
end
endcase
case (ALIGN_PCOMMA_DET)
"TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET);
$finish;
end
endcase
case (CBCC_DATA_SOURCE_SEL)
"DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1;
"ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL);
$finish;
end
endcase
case (CHAN_BOND_KEEP_ALIGN)
"FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0;
"TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN);
$finish;
end
endcase
case (CHAN_BOND_SEQ_2_USE)
"FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE);
$finish;
end
endcase
case (CHAN_BOND_SEQ_LEN)
1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00;
2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01;
3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10;
4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1);
$finish;
end
endcase
case (CLK_CORRECT_USE)
"TRUE" : CLK_CORRECT_USE_BINARY = 1'b1;
"FALSE" : CLK_CORRECT_USE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE);
$finish;
end
endcase
case (CLK_COR_KEEP_IDLE)
"FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0;
"TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE);
$finish;
end
endcase
case (CLK_COR_PRECEDENCE)
"TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1;
"FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE);
$finish;
end
endcase
case (CLK_COR_SEQ_2_USE)
"FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE);
$finish;
end
endcase
case (CLK_COR_SEQ_LEN)
1 : CLK_COR_SEQ_LEN_BINARY = 2'b00;
2 : CLK_COR_SEQ_LEN_BINARY = 2'b01;
3 : CLK_COR_SEQ_LEN_BINARY = 2'b10;
4 : CLK_COR_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1);
$finish;
end
endcase
case (DEC_MCOMMA_DETECT)
"TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT);
$finish;
end
endcase
case (DEC_PCOMMA_DETECT)
"TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT);
$finish;
end
endcase
case (DEC_VALID_COMMA_ONLY)
"TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1;
"FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY);
$finish;
end
endcase
case (ES_ERRDET_EN)
"FALSE" : ES_ERRDET_EN_BINARY = 1'b0;
"TRUE" : ES_ERRDET_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN);
$finish;
end
endcase
case (ES_EYE_SCAN_EN)
"FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0;
"TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN);
$finish;
end
endcase
case (FTS_LANE_DESKEW_EN)
"FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0;
"TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN);
$finish;
end
endcase
case (PCS_PCIE_EN)
"FALSE" : PCS_PCIE_EN_BINARY = 1'b0;
"TRUE" : PCS_PCIE_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN);
$finish;
end
endcase
case (RXBUF_ADDR_MODE)
"FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0;
"FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE);
$finish;
end
endcase
case (RXBUF_EN)
"TRUE" : RXBUF_EN_BINARY = 1'b1;
"FALSE" : RXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN);
$finish;
end
endcase
case (RXBUF_RESET_ON_CB_CHANGE)
"TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE);
$finish;
end
endcase
case (RXBUF_RESET_ON_COMMAALIGN)
"FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN);
$finish;
end
endcase
case (RXBUF_RESET_ON_EIDLE)
"FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE);
$finish;
end
endcase
case (RXBUF_RESET_ON_RATE_CHANGE)
"TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (RXBUF_THRESH_OVRD)
"FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0;
"TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD);
$finish;
end
endcase
case (RXGEARBOX_EN)
"FALSE" : RXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : RXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN);
$finish;
end
endcase
case (RXOOB_CLK_CFG)
"PMA" : RXOOB_CLK_CFG_BINARY = 1'b0;
"FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG);
$finish;
end
endcase
case (RXOUT_DIV)
2 : RXOUT_DIV_BINARY = 3'b001;
1 : RXOUT_DIV_BINARY = 3'b000;
4 : RXOUT_DIV_BINARY = 3'b010;
8 : RXOUT_DIV_BINARY = 3'b011;
16 : RXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute RXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2);
$finish;
end
endcase
case (RXSLIDE_MODE)
"OFF" : RXSLIDE_MODE_BINARY = 2'b00;
"AUTO" : RXSLIDE_MODE_BINARY = 2'b01;
"PCS" : RXSLIDE_MODE_BINARY = 2'b10;
"PMA" : RXSLIDE_MODE_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE);
$finish;
end
endcase
case (RX_CLK25_DIV)
7 : RX_CLK25_DIV_BINARY = 5'b00110;
1 : RX_CLK25_DIV_BINARY = 5'b00000;
2 : RX_CLK25_DIV_BINARY = 5'b00001;
3 : RX_CLK25_DIV_BINARY = 5'b00010;
4 : RX_CLK25_DIV_BINARY = 5'b00011;
5 : RX_CLK25_DIV_BINARY = 5'b00100;
6 : RX_CLK25_DIV_BINARY = 5'b00101;
8 : RX_CLK25_DIV_BINARY = 5'b00111;
9 : RX_CLK25_DIV_BINARY = 5'b01000;
10 : RX_CLK25_DIV_BINARY = 5'b01001;
11 : RX_CLK25_DIV_BINARY = 5'b01010;
12 : RX_CLK25_DIV_BINARY = 5'b01011;
13 : RX_CLK25_DIV_BINARY = 5'b01100;
14 : RX_CLK25_DIV_BINARY = 5'b01101;
15 : RX_CLK25_DIV_BINARY = 5'b01110;
16 : RX_CLK25_DIV_BINARY = 5'b01111;
17 : RX_CLK25_DIV_BINARY = 5'b10000;
18 : RX_CLK25_DIV_BINARY = 5'b10001;
19 : RX_CLK25_DIV_BINARY = 5'b10010;
20 : RX_CLK25_DIV_BINARY = 5'b10011;
21 : RX_CLK25_DIV_BINARY = 5'b10100;
22 : RX_CLK25_DIV_BINARY = 5'b10101;
23 : RX_CLK25_DIV_BINARY = 5'b10110;
24 : RX_CLK25_DIV_BINARY = 5'b10111;
25 : RX_CLK25_DIV_BINARY = 5'b11000;
26 : RX_CLK25_DIV_BINARY = 5'b11001;
27 : RX_CLK25_DIV_BINARY = 5'b11010;
28 : RX_CLK25_DIV_BINARY = 5'b11011;
29 : RX_CLK25_DIV_BINARY = 5'b11100;
30 : RX_CLK25_DIV_BINARY = 5'b11101;
31 : RX_CLK25_DIV_BINARY = 5'b11110;
32 : RX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7);
$finish;
end
endcase
case (RX_DATA_WIDTH)
20 : RX_DATA_WIDTH_BINARY = 3'b011;
16 : RX_DATA_WIDTH_BINARY = 3'b010;
32 : RX_DATA_WIDTH_BINARY = 3'b100;
40 : RX_DATA_WIDTH_BINARY = 3'b101;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", RX_DATA_WIDTH, 20);
$finish;
end
endcase
case (RX_DEFER_RESET_BUF_EN)
"TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1;
"FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN);
$finish;
end
endcase
case (RX_DISPERR_SEQ_MATCH)
"TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1;
"FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH);
$finish;
end
endcase
case (RX_SIG_VALID_DLY)
10 : RX_SIG_VALID_DLY_BINARY = 5'b01001;
1 : RX_SIG_VALID_DLY_BINARY = 5'b00000;
2 : RX_SIG_VALID_DLY_BINARY = 5'b00001;
3 : RX_SIG_VALID_DLY_BINARY = 5'b00010;
4 : RX_SIG_VALID_DLY_BINARY = 5'b00011;
5 : RX_SIG_VALID_DLY_BINARY = 5'b00100;
6 : RX_SIG_VALID_DLY_BINARY = 5'b00101;
7 : RX_SIG_VALID_DLY_BINARY = 5'b00110;
8 : RX_SIG_VALID_DLY_BINARY = 5'b00111;
9 : RX_SIG_VALID_DLY_BINARY = 5'b01000;
11 : RX_SIG_VALID_DLY_BINARY = 5'b01010;
12 : RX_SIG_VALID_DLY_BINARY = 5'b01011;
13 : RX_SIG_VALID_DLY_BINARY = 5'b01100;
14 : RX_SIG_VALID_DLY_BINARY = 5'b01101;
15 : RX_SIG_VALID_DLY_BINARY = 5'b01110;
16 : RX_SIG_VALID_DLY_BINARY = 5'b01111;
17 : RX_SIG_VALID_DLY_BINARY = 5'b10000;
18 : RX_SIG_VALID_DLY_BINARY = 5'b10001;
19 : RX_SIG_VALID_DLY_BINARY = 5'b10010;
20 : RX_SIG_VALID_DLY_BINARY = 5'b10011;
21 : RX_SIG_VALID_DLY_BINARY = 5'b10100;
22 : RX_SIG_VALID_DLY_BINARY = 5'b10101;
23 : RX_SIG_VALID_DLY_BINARY = 5'b10110;
24 : RX_SIG_VALID_DLY_BINARY = 5'b10111;
25 : RX_SIG_VALID_DLY_BINARY = 5'b11000;
26 : RX_SIG_VALID_DLY_BINARY = 5'b11001;
27 : RX_SIG_VALID_DLY_BINARY = 5'b11010;
28 : RX_SIG_VALID_DLY_BINARY = 5'b11011;
29 : RX_SIG_VALID_DLY_BINARY = 5'b11100;
30 : RX_SIG_VALID_DLY_BINARY = 5'b11101;
31 : RX_SIG_VALID_DLY_BINARY = 5'b11110;
32 : RX_SIG_VALID_DLY_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10);
$finish;
end
endcase
case (RX_XCLK_SEL)
"RXREC" : RX_XCLK_SEL_BINARY = 1'b0;
"RXUSR" : RX_XCLK_SEL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL);
$finish;
end
endcase
case (SATA_PLL_CFG)
"VCO_3000MHZ" : SATA_PLL_CFG_BINARY = 2'b00;
"VCO_750MHZ" : SATA_PLL_CFG_BINARY = 2'b10;
"VCO_1500MHZ" : SATA_PLL_CFG_BINARY = 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute SATA_PLL_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_PLL_CFG);
$finish;
end
endcase
case (SHOW_REALIGN_COMMA)
"TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1;
"FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA);
$finish;
end
endcase
case (SIM_RECEIVER_DETECT_PASS)
"TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
"FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_TX_EIDLE_DRIVE_LEVEL)
"X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL);
$finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION);
$finish;
end
endcase
case (TXBUF_EN)
"TRUE" : TXBUF_EN_BINARY = 1'b1;
"FALSE" : TXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN);
$finish;
end
endcase
case (TXBUF_RESET_ON_RATE_CHANGE)
"FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
"TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (TXGEARBOX_EN)
"FALSE" : TXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : TXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN);
$finish;
end
endcase
case (TXOUT_DIV)
2 : TXOUT_DIV_BINARY = 3'b001;
1 : TXOUT_DIV_BINARY = 3'b000;
4 : TXOUT_DIV_BINARY = 3'b010;
8 : TXOUT_DIV_BINARY = 3'b011;
16 : TXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute TXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2);
$finish;
end
endcase
case (TXPI_PPMCLK_SEL)
"TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1;
"TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL);
$finish;
end
endcase
case (TX_CLK25_DIV)
7 : TX_CLK25_DIV_BINARY = 5'b00110;
1 : TX_CLK25_DIV_BINARY = 5'b00000;
2 : TX_CLK25_DIV_BINARY = 5'b00001;
3 : TX_CLK25_DIV_BINARY = 5'b00010;
4 : TX_CLK25_DIV_BINARY = 5'b00011;
5 : TX_CLK25_DIV_BINARY = 5'b00100;
6 : TX_CLK25_DIV_BINARY = 5'b00101;
8 : TX_CLK25_DIV_BINARY = 5'b00111;
9 : TX_CLK25_DIV_BINARY = 5'b01000;
10 : TX_CLK25_DIV_BINARY = 5'b01001;
11 : TX_CLK25_DIV_BINARY = 5'b01010;
12 : TX_CLK25_DIV_BINARY = 5'b01011;
13 : TX_CLK25_DIV_BINARY = 5'b01100;
14 : TX_CLK25_DIV_BINARY = 5'b01101;
15 : TX_CLK25_DIV_BINARY = 5'b01110;
16 : TX_CLK25_DIV_BINARY = 5'b01111;
17 : TX_CLK25_DIV_BINARY = 5'b10000;
18 : TX_CLK25_DIV_BINARY = 5'b10001;
19 : TX_CLK25_DIV_BINARY = 5'b10010;
20 : TX_CLK25_DIV_BINARY = 5'b10011;
21 : TX_CLK25_DIV_BINARY = 5'b10100;
22 : TX_CLK25_DIV_BINARY = 5'b10101;
23 : TX_CLK25_DIV_BINARY = 5'b10110;
24 : TX_CLK25_DIV_BINARY = 5'b10111;
25 : TX_CLK25_DIV_BINARY = 5'b11000;
26 : TX_CLK25_DIV_BINARY = 5'b11001;
27 : TX_CLK25_DIV_BINARY = 5'b11010;
28 : TX_CLK25_DIV_BINARY = 5'b11011;
29 : TX_CLK25_DIV_BINARY = 5'b11100;
30 : TX_CLK25_DIV_BINARY = 5'b11101;
31 : TX_CLK25_DIV_BINARY = 5'b11110;
32 : TX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7);
$finish;
end
endcase
case (TX_DATA_WIDTH)
20 : TX_DATA_WIDTH_BINARY = 3'b011;
16 : TX_DATA_WIDTH_BINARY = 3'b010;
32 : TX_DATA_WIDTH_BINARY = 3'b100;
40 : TX_DATA_WIDTH_BINARY = 3'b101;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", TX_DATA_WIDTH, 20);
$finish;
end
endcase
case (TX_DRIVE_MODE)
"DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000;
"PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001;
"PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE);
$finish;
end
endcase
case (TX_LOOPBACK_DRIVE_HIZ)
"FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0;
"TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ);
$finish;
end
endcase
case (TX_XCLK_SEL)
"TXUSR" : TX_XCLK_SEL_BINARY = 1'b1;
"TXOUT" : TX_XCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL);
$finish;
end
endcase
if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1))
ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE);
$finish;
end
if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1))
ACJTAG_MODE_BINARY = ACJTAG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE);
$finish;
end
if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1))
ACJTAG_RESET_BINARY = ACJTAG_RESET;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_RESET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET);
$finish;
end
if ((ADAPT_CFG0 >= 20'b00000000000000000000) && (ADAPT_CFG0 <= 20'b11111111111111111111))
ADAPT_CFG0_BINARY = ADAPT_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute ADAPT_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 20'b00000000000000000000 to 20'b11111111111111111111.", ADAPT_CFG0);
$finish;
end
if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111))
ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE);
$finish;
end
if ((ALIGN_COMMA_WORD >= 1) && (ALIGN_COMMA_WORD <= 2))
ALIGN_COMMA_WORD_BINARY = ALIGN_COMMA_WORD;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 2.", ALIGN_COMMA_WORD);
$finish;
end
if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111))
ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE);
$finish;
end
if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111))
ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE);
$finish;
end
if ((CFOK_CFG >= 43'b0000000000000000000000000000000000000000000) && (CFOK_CFG <= 43'b1111111111111111111111111111111111111111111))
CFOK_CFG_BINARY = CFOK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 43'b0000000000000000000000000000000000000000000 to 43'b1111111111111111111111111111111111111111111.", CFOK_CFG);
$finish;
end
if ((CFOK_CFG2 >= 7'b0000000) && (CFOK_CFG2 <= 7'b1111111))
CFOK_CFG2_BINARY = CFOK_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG2);
$finish;
end
if ((CFOK_CFG3 >= 7'b0000000) && (CFOK_CFG3 <= 7'b1111111))
CFOK_CFG3_BINARY = CFOK_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG3);
$finish;
end
if ((CFOK_CFG4 >= 1'b0) && (CFOK_CFG4 <= 1'b1))
CFOK_CFG4_BINARY = CFOK_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CFOK_CFG4);
$finish;
end
if ((CFOK_CFG5 >= 2'b00) && (CFOK_CFG5 <= 2'b11))
CFOK_CFG5_BINARY = CFOK_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CFOK_CFG5);
$finish;
end
if ((CFOK_CFG6 >= 4'b0000) && (CFOK_CFG6 <= 4'b1111))
CFOK_CFG6_BINARY = CFOK_CFG6;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CFOK_CFG6);
$finish;
end
if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14))
CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW);
$finish;
end
if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111))
CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1);
$finish;
end
if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111))
CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2);
$finish;
end
if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111))
CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3);
$finish;
end
if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111))
CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4);
$finish;
end
if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE);
$finish;
end
if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111))
CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1);
$finish;
end
if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111))
CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2);
$finish;
end
if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111))
CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3);
$finish;
end
if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111))
CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4);
$finish;
end
if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE);
$finish;
end
if ((CLK_COMMON_SWING >= 1'b0) && (CLK_COMMON_SWING <= 1'b1))
CLK_COMMON_SWING_BINARY = CLK_COMMON_SWING;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COMMON_SWING on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CLK_COMMON_SWING);
$finish;
end
if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60))
CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT);
$finish;
end
if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60))
CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT);
$finish;
end
if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31))
CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT);
$finish;
end
if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111))
CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1);
$finish;
end
if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111))
CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2);
$finish;
end
if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111))
CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3);
$finish;
end
if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111))
CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4);
$finish;
end
if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111))
CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE);
$finish;
end
if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111))
CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1);
$finish;
end
if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111))
CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2);
$finish;
end
if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111))
CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3);
$finish;
end
if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111))
CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4);
$finish;
end
if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111))
CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE);
$finish;
end
if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1))
ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL);
$finish;
end
if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111))
ES_CONTROL_BINARY = ES_CONTROL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CONTROL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL);
$finish;
end
if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111))
ES_PMA_CFG_BINARY = ES_PMA_CFG;
else begin
$display("Attribute Syntax Error : The Attribute ES_PMA_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG);
$finish;
end
if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111))
ES_PRESCALE_BINARY = ES_PRESCALE;
else begin
$display("Attribute Syntax Error : The Attribute ES_PRESCALE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE);
$finish;
end
if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111))
ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET;
else begin
$display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET);
$finish;
end
if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111))
FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE);
$finish;
end
if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111))
FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG;
else begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG);
$finish;
end
if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111))
GEARBOX_MODE_BINARY = GEARBOX_MODE;
else begin
$display("Attribute Syntax Error : The Attribute GEARBOX_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE);
$finish;
end
if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1))
LOOPBACK_CFG_BINARY = LOOPBACK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG);
$finish;
end
if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11))
OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV;
else begin
$display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV);
$finish;
end
if ((PMA_LOOPBACK_CFG >= 1'b0) && (PMA_LOOPBACK_CFG <= 1'b1))
PMA_LOOPBACK_CFG_BINARY = PMA_LOOPBACK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute PMA_LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_LOOPBACK_CFG);
$finish;
end
if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11))
PMA_RSV3_BINARY = PMA_RSV3;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3);
$finish;
end
if ((PMA_RSV4 >= 4'b0000) && (PMA_RSV4 <= 4'b1111))
PMA_RSV4_BINARY = PMA_RSV4;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV4);
$finish;
end
if ((PMA_RSV5 >= 1'b0) && (PMA_RSV5 <= 1'b1))
PMA_RSV5_BINARY = PMA_RSV5;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV5);
$finish;
end
if ((PMA_RSV6 >= 1'b0) && (PMA_RSV6 <= 1'b1))
PMA_RSV6_BINARY = PMA_RSV6;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV6);
$finish;
end
if ((PMA_RSV7 >= 1'b0) && (PMA_RSV7 <= 1'b1))
PMA_RSV7_BINARY = PMA_RSV7;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV7 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV7);
$finish;
end
if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111))
RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME);
$finish;
end
if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111))
RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT);
$finish;
end
if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111))
RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT);
$finish;
end
if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63))
RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW);
$finish;
end
if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63))
RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW);
$finish;
end
if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111))
RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME);
$finish;
end
if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111))
RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME);
$finish;
end
if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1))
RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE);
$finish;
end
if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1))
RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE);
$finish;
end
if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111))
RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG);
$finish;
end
if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1))
RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE);
$finish;
end
if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111))
RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME);
$finish;
end
if ((RXLPMRESET_TIME >= 7'b0000000) && (RXLPMRESET_TIME <= 7'b1111111))
RXLPMRESET_TIME_BINARY = RXLPMRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXLPMRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXLPMRESET_TIME);
$finish;
end
if ((RXLPM_BIAS_STARTUP_DISABLE >= 1'b0) && (RXLPM_BIAS_STARTUP_DISABLE <= 1'b1))
RXLPM_BIAS_STARTUP_DISABLE_BINARY = RXLPM_BIAS_STARTUP_DISABLE;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_BIAS_STARTUP_DISABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_BIAS_STARTUP_DISABLE);
$finish;
end
if ((RXLPM_CFG >= 4'b0000) && (RXLPM_CFG <= 4'b1111))
RXLPM_CFG_BINARY = RXLPM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_CFG);
$finish;
end
if ((RXLPM_CFG1 >= 1'b0) && (RXLPM_CFG1 <= 1'b1))
RXLPM_CFG1_BINARY = RXLPM_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CFG1);
$finish;
end
if ((RXLPM_CM_CFG >= 1'b0) && (RXLPM_CM_CFG <= 1'b1))
RXLPM_CM_CFG_BINARY = RXLPM_CM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CM_CFG);
$finish;
end
if ((RXLPM_GC_CFG >= 9'b000000000) && (RXLPM_GC_CFG <= 9'b111111111))
RXLPM_GC_CFG_BINARY = RXLPM_GC_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", RXLPM_GC_CFG);
$finish;
end
if ((RXLPM_GC_CFG2 >= 3'b000) && (RXLPM_GC_CFG2 <= 3'b111))
RXLPM_GC_CFG2_BINARY = RXLPM_GC_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_GC_CFG2);
$finish;
end
if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111))
RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG);
$finish;
end
if ((RXLPM_HF_CFG2 >= 5'b00000) && (RXLPM_HF_CFG2 <= 5'b11111))
RXLPM_HF_CFG2_BINARY = RXLPM_HF_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_HF_CFG2);
$finish;
end
if ((RXLPM_HF_CFG3 >= 4'b0000) && (RXLPM_HF_CFG3 <= 4'b1111))
RXLPM_HF_CFG3_BINARY = RXLPM_HF_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_HF_CFG3);
$finish;
end
if ((RXLPM_HOLD_DURING_EIDLE >= 1'b0) && (RXLPM_HOLD_DURING_EIDLE <= 1'b1))
RXLPM_HOLD_DURING_EIDLE_BINARY = RXLPM_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_HOLD_DURING_EIDLE);
$finish;
end
if ((RXLPM_INCM_CFG >= 1'b0) && (RXLPM_INCM_CFG <= 1'b1))
RXLPM_INCM_CFG_BINARY = RXLPM_INCM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_INCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_INCM_CFG);
$finish;
end
if ((RXLPM_IPCM_CFG >= 1'b0) && (RXLPM_IPCM_CFG <= 1'b1))
RXLPM_IPCM_CFG_BINARY = RXLPM_IPCM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_IPCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_IPCM_CFG);
$finish;
end
if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111))
RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG);
$finish;
end
if ((RXLPM_LF_CFG2 >= 5'b00000) && (RXLPM_LF_CFG2 <= 5'b11111))
RXLPM_LF_CFG2_BINARY = RXLPM_LF_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_LF_CFG2);
$finish;
end
if ((RXLPM_OSINT_CFG >= 3'b000) && (RXLPM_OSINT_CFG <= 3'b111))
RXLPM_OSINT_CFG_BINARY = RXLPM_OSINT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_OSINT_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_OSINT_CFG);
$finish;
end
if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111))
RXOOB_CFG_BINARY = RXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG);
$finish;
end
if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111))
RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME);
$finish;
end
if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111))
RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT);
$finish;
end
if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111))
RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME);
$finish;
end
if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111))
RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL);
$finish;
end
if ((RXPI_CFG0 >= 3'b000) && (RXPI_CFG0 <= 3'b111))
RXPI_CFG0_BINARY = RXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG0);
$finish;
end
if ((RXPI_CFG1 >= 1'b0) && (RXPI_CFG1 <= 1'b1))
RXPI_CFG1_BINARY = RXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG1);
$finish;
end
if ((RXPI_CFG2 >= 1'b0) && (RXPI_CFG2 <= 1'b1))
RXPI_CFG2_BINARY = RXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG2);
$finish;
end
if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111))
RXPMARESET_TIME_BINARY = RXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME);
$finish;
end
if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1))
RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK;
else begin
$display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK);
$finish;
end
if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15))
RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT);
$finish;
end
if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1))
RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE);
$finish;
end
if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1))
RXSYNC_OVRD_BINARY = RXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD);
$finish;
end
if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1))
RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA);
$finish;
end
if ((RX_BIAS_CFG >= 16'b0000000000000000) && (RX_BIAS_CFG <= 16'b1111111111111111))
RX_BIAS_CFG_BINARY = RX_BIAS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", RX_BIAS_CFG);
$finish;
end
if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111))
RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG);
$finish;
end
if ((RX_CLKMUX_EN >= 1'b0) && (RX_CLKMUX_EN <= 1'b1))
RX_CLKMUX_EN_BINARY = RX_CLKMUX_EN;
else begin
$display("Attribute Syntax Error : The Attribute RX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_EN);
$finish;
end
if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11))
RX_CM_SEL_BINARY = RX_CM_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL);
$finish;
end
if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111))
RX_CM_TRIM_BINARY = RX_CM_TRIM;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_TRIM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM);
$finish;
end
if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111))
RX_DDI_SEL_BINARY = RX_DDI_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_DDI_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL);
$finish;
end
if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111))
RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG);
$finish;
end
if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111))
RX_OS_CFG_BINARY = RX_OS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_OS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG);
$finish;
end
if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127))
SAS_MAX_COM_BINARY = SAS_MAX_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MAX_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM);
$finish;
end
if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63))
SAS_MIN_COM_BINARY = SAS_MIN_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MIN_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM);
$finish;
end
if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111))
SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN);
$finish;
end
if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111))
SATA_BURST_VAL_BINARY = SATA_BURST_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL);
$finish;
end
if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111))
SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL);
$finish;
end
if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63))
SATA_MAX_BURST_BINARY = SATA_MAX_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST);
$finish;
end
if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63))
SATA_MAX_INIT_BINARY = SATA_MAX_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT);
$finish;
end
if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63))
SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE);
$finish;
end
if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61))
SATA_MIN_BURST_BINARY = SATA_MIN_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST);
$finish;
end
if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63))
SATA_MIN_INIT_BINARY = SATA_MIN_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT);
$finish;
end
if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63))
SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE);
$finish;
end
if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111))
TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG);
$finish;
end
if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111))
TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD);
$finish;
end
if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1))
TXOOB_CFG_BINARY = TXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG);
$finish;
end
if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111))
TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME);
$finish;
end
if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111))
TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL);
$finish;
end
if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11))
TXPI_CFG0_BINARY = TXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0);
$finish;
end
if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11))
TXPI_CFG1_BINARY = TXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1);
$finish;
end
if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11))
TXPI_CFG2_BINARY = TXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2);
$finish;
end
if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1))
TXPI_CFG3_BINARY = TXPI_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3);
$finish;
end
if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1))
TXPI_CFG4_BINARY = TXPI_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4);
$finish;
end
if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111))
TXPI_CFG5_BINARY = TXPI_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5);
$finish;
end
if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1))
TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL);
$finish;
end
if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1))
TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL);
$finish;
end
if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111))
TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG);
$finish;
end
if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111))
TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM);
$finish;
end
if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111))
TXPMARESET_TIME_BINARY = TXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME);
$finish;
end
if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1))
TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE);
$finish;
end
if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1))
TXSYNC_OVRD_BINARY = TXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD);
$finish;
end
if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1))
TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA);
$finish;
end
if ((TX_CLKMUX_EN >= 1'b0) && (TX_CLKMUX_EN <= 1'b1))
TX_CLKMUX_EN_BINARY = TX_CLKMUX_EN;
else begin
$display("Attribute Syntax Error : The Attribute TX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_EN);
$finish;
end
if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111))
TX_DEEMPH0_BINARY = TX_DEEMPH0;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0);
$finish;
end
if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111))
TX_DEEMPH1_BINARY = TX_DEEMPH1;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1);
$finish;
end
if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111))
TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY);
$finish;
end
if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111))
TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY);
$finish;
end
if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1))
TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL);
$finish;
end
if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111))
TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0);
$finish;
end
if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111))
TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1);
$finish;
end
if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111))
TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2);
$finish;
end
if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111))
TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3);
$finish;
end
if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111))
TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4);
$finish;
end
if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111))
TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0);
$finish;
end
if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111))
TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1);
$finish;
end
if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111))
TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2);
$finish;
end
if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111))
TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3);
$finish;
end
if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111))
TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4);
$finish;
end
if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1))
TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE;
else begin
$display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE);
$finish;
end
if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111))
TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF;
else begin
$display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF);
$finish;
end
if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1))
UCODEER_CLR_BINARY = UCODEER_CLR;
else begin
$display("Attribute Syntax Error : The Attribute UCODEER_CLR on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR);
$finish;
end
if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1))
USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL);
$finish;
end
end
wire [14:0] delay_DMONITOROUT;
wire [15:0] delay_DRPDO;
wire [15:0] delay_PCSRSVDOUT;
wire [1:0] delay_RXCLKCORCNT;
wire [1:0] delay_RXDATAVALID;
wire [1:0] delay_RXSTARTOFSEQ;
wire [1:0] delay_TXBUFSTATUS;
wire [2:0] delay_RXBUFSTATUS;
wire [2:0] delay_RXHEADER;
wire [2:0] delay_RXSTATUS;
wire [31:0] delay_RXDATA;
wire [3:0] delay_RXCHARISCOMMA;
wire [3:0] delay_RXCHARISK;
wire [3:0] delay_RXCHBONDO;
wire [3:0] delay_RXDISPERR;
wire [3:0] delay_RXNOTINTABLE;
wire [4:0] delay_RXPHMONITOR;
wire [4:0] delay_RXPHSLIPMONITOR;
wire delay_DRPRDY;
wire delay_EYESCANDATAERROR;
wire delay_GTPTXN;
wire delay_GTPTXP;
wire delay_PHYSTATUS;
wire delay_PMARSVDOUT0;
wire delay_PMARSVDOUT1;
wire delay_RXBYTEISALIGNED;
wire delay_RXBYTEREALIGN;
wire delay_RXCDRLOCK;
wire delay_RXCHANBONDSEQ;
wire delay_RXCHANISALIGNED;
wire delay_RXCHANREALIGN;
wire delay_RXCOMINITDET;
wire delay_RXCOMMADET;
wire delay_RXCOMSASDET;
wire delay_RXCOMWAKEDET;
wire delay_RXDLYSRESETDONE;
wire delay_RXELECIDLE;
wire delay_RXHEADERVALID;
wire delay_RXOSINTDONE;
wire delay_RXOSINTSTARTED;
wire delay_RXOSINTSTROBEDONE;
wire delay_RXOSINTSTROBESTARTED;
wire delay_RXOUTCLK;
wire delay_RXOUTCLKFABRIC;
wire delay_RXOUTCLKPCS;
wire delay_RXPHALIGNDONE;
wire delay_RXPMARESETDONE;
wire delay_RXPRBSERR;
wire delay_RXRATEDONE;
wire delay_RXRESETDONE;
wire delay_RXSYNCDONE;
wire delay_RXSYNCOUT;
wire delay_RXVALID;
wire delay_TXCOMFINISH;
wire delay_TXDLYSRESETDONE;
wire delay_TXGEARBOXREADY;
wire delay_TXOUTCLK;
wire delay_TXOUTCLKFABRIC;
wire delay_TXOUTCLKPCS;
wire delay_TXPHALIGNDONE;
wire delay_TXPHINITDONE;
wire delay_TXPMARESETDONE;
wire delay_TXRATEDONE;
wire delay_TXRESETDONE;
wire delay_TXSYNCDONE;
wire delay_TXSYNCOUT;
wire [13:0] delay_RXADAPTSELTEST;
wire [15:0] delay_DRPDI;
wire [15:0] delay_GTRSVD;
wire [15:0] delay_PCSRSVDIN;
wire [19:0] delay_TSTIN;
wire [1:0] delay_RXELECIDLEMODE;
wire [1:0] delay_RXPD;
wire [1:0] delay_RXSYSCLKSEL;
wire [1:0] delay_TXPD;
wire [1:0] delay_TXSYSCLKSEL;
wire [2:0] delay_LOOPBACK;
wire [2:0] delay_RXCHBONDLEVEL;
wire [2:0] delay_RXOUTCLKSEL;
wire [2:0] delay_RXPRBSSEL;
wire [2:0] delay_RXRATE;
wire [2:0] delay_TXBUFDIFFCTRL;
wire [2:0] delay_TXHEADER;
wire [2:0] delay_TXMARGIN;
wire [2:0] delay_TXOUTCLKSEL;
wire [2:0] delay_TXPRBSSEL;
wire [2:0] delay_TXRATE;
wire [31:0] delay_TXDATA;
wire [3:0] delay_RXCHBONDI;
wire [3:0] delay_RXOSINTCFG;
wire [3:0] delay_RXOSINTID0;
wire [3:0] delay_TX8B10BBYPASS;
wire [3:0] delay_TXCHARDISPMODE;
wire [3:0] delay_TXCHARDISPVAL;
wire [3:0] delay_TXCHARISK;
wire [3:0] delay_TXDIFFCTRL;
wire [4:0] delay_TXPIPPMSTEPSIZE;
wire [4:0] delay_TXPOSTCURSOR;
wire [4:0] delay_TXPRECURSOR;
wire [6:0] delay_TXMAINCURSOR;
wire [6:0] delay_TXSEQUENCE;
wire [8:0] delay_DRPADDR;
wire delay_CFGRESET;
wire delay_CLKRSVD0;
wire delay_CLKRSVD1;
wire delay_DMONFIFORESET;
wire delay_DMONITORCLK;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_EYESCANMODE;
wire delay_EYESCANRESET;
wire delay_EYESCANTRIGGER;
wire delay_GTPRXN;
wire delay_GTPRXP;
wire delay_GTRESETSEL;
wire delay_GTRXRESET;
wire delay_GTTXRESET;
wire delay_PLL0CLK;
wire delay_PLL0REFCLK;
wire delay_PLL1CLK;
wire delay_PLL1REFCLK;
wire delay_PMARSVDIN0;
wire delay_PMARSVDIN1;
wire delay_PMARSVDIN2;
wire delay_PMARSVDIN3;
wire delay_PMARSVDIN4;
wire delay_RESETOVRD;
wire delay_RX8B10BEN;
wire delay_RXBUFRESET;
wire delay_RXCDRFREQRESET;
wire delay_RXCDRHOLD;
wire delay_RXCDROVRDEN;
wire delay_RXCDRRESET;
wire delay_RXCDRRESETRSV;
wire delay_RXCHBONDEN;
wire delay_RXCHBONDMASTER;
wire delay_RXCHBONDSLAVE;
wire delay_RXCOMMADETEN;
wire delay_RXDDIEN;
wire delay_RXDFEXYDEN;
wire delay_RXDLYBYPASS;
wire delay_RXDLYEN;
wire delay_RXDLYOVRDEN;
wire delay_RXDLYSRESET;
wire delay_RXGEARBOXSLIP;
wire delay_RXLPMHFHOLD;
wire delay_RXLPMHFOVRDEN;
wire delay_RXLPMLFHOLD;
wire delay_RXLPMLFOVRDEN;
wire delay_RXLPMOSINTNTRLEN;
wire delay_RXLPMRESET;
wire delay_RXMCOMMAALIGNEN;
wire delay_RXOOBRESET;
wire delay_RXOSCALRESET;
wire delay_RXOSHOLD;
wire delay_RXOSINTEN;
wire delay_RXOSINTHOLD;
wire delay_RXOSINTNTRLEN;
wire delay_RXOSINTOVRDEN;
wire delay_RXOSINTPD;
wire delay_RXOSINTSTROBE;
wire delay_RXOSINTTESTOVRDEN;
wire delay_RXOSOVRDEN;
wire delay_RXPCOMMAALIGNEN;
wire delay_RXPCSRESET;
wire delay_RXPHALIGN;
wire delay_RXPHALIGNEN;
wire delay_RXPHDLYPD;
wire delay_RXPHDLYRESET;
wire delay_RXPHOVRDEN;
wire delay_RXPMARESET;
wire delay_RXPOLARITY;
wire delay_RXPRBSCNTRESET;
wire delay_RXRATEMODE;
wire delay_RXSLIDE;
wire delay_RXSYNCALLIN;
wire delay_RXSYNCIN;
wire delay_RXSYNCMODE;
wire delay_RXUSERRDY;
wire delay_RXUSRCLK2;
wire delay_RXUSRCLK;
wire delay_SETERRSTATUS;
wire delay_SIGVALIDCLK;
wire delay_TX8B10BEN;
wire delay_TXCOMINIT;
wire delay_TXCOMSAS;
wire delay_TXCOMWAKE;
wire delay_TXDEEMPH;
wire delay_TXDETECTRX;
wire delay_TXDIFFPD;
wire delay_TXDLYBYPASS;
wire delay_TXDLYEN;
wire delay_TXDLYHOLD;
wire delay_TXDLYOVRDEN;
wire delay_TXDLYSRESET;
wire delay_TXDLYUPDOWN;
wire delay_TXELECIDLE;
wire delay_TXINHIBIT;
wire delay_TXPCSRESET;
wire delay_TXPDELECIDLEMODE;
wire delay_TXPHALIGN;
wire delay_TXPHALIGNEN;
wire delay_TXPHDLYPD;
wire delay_TXPHDLYRESET;
wire delay_TXPHDLYTSTCLK;
wire delay_TXPHINIT;
wire delay_TXPHOVRDEN;
wire delay_TXPIPPMEN;
wire delay_TXPIPPMOVRDEN;
wire delay_TXPIPPMPD;
wire delay_TXPIPPMSEL;
wire delay_TXPISOPD;
wire delay_TXPMARESET;
wire delay_TXPOLARITY;
wire delay_TXPOSTCURSORINV;
wire delay_TXPRBSFORCEERR;
wire delay_TXPRECURSORINV;
wire delay_TXRATEMODE;
wire delay_TXSTARTSEQ;
wire delay_TXSWING;
wire delay_TXSYNCALLIN;
wire delay_TXSYNCIN;
wire delay_TXSYNCMODE;
wire delay_TXUSERRDY;
wire delay_TXUSRCLK2;
wire delay_TXUSRCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= DRPEN;
drpwe_r1 <= DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((DRPWE === 1'b1) && (DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge DRPCLK)
//end drp monitor
reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED;
reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED;
reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED;
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED;
reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED;
reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED;
reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED;
reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED;
reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED;
assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK;
assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK;
assign #(out_delay) DMONITOROUT = delay_DMONITOROUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR;
assign #(out_delay) GTPTXN = delay_GTPTXN;
assign #(out_delay) GTPTXP = delay_GTPTXP;
assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT;
assign #(out_delay) PHYSTATUS = delay_PHYSTATUS;
assign #(out_delay) PMARSVDOUT0 = delay_PMARSVDOUT0;
assign #(out_delay) PMARSVDOUT1 = delay_PMARSVDOUT1;
assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS;
assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED;
assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN;
assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK;
assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ;
assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED;
assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN;
assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA;
assign #(out_delay) RXCHARISK = delay_RXCHARISK;
assign #(out_delay) RXCHBONDO = delay_RXCHBONDO;
assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT;
assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET;
assign #(out_delay) RXCOMMADET = delay_RXCOMMADET;
assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET;
assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET;
assign #(out_delay) RXDATA = delay_RXDATA;
assign #(out_delay) RXDATAVALID = delay_RXDATAVALID;
assign #(out_delay) RXDISPERR = delay_RXDISPERR;
assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE;
assign #(out_delay) RXELECIDLE = delay_RXELECIDLE;
assign #(out_delay) RXHEADER = delay_RXHEADER;
assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID;
assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE;
assign #(out_delay) RXOSINTDONE = delay_RXOSINTDONE;
assign #(out_delay) RXOSINTSTARTED = delay_RXOSINTSTARTED;
assign #(out_delay) RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE;
assign #(out_delay) RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED;
assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC;
assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS;
assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE;
assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR;
assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR;
assign #(out_delay) RXPMARESETDONE = delay_RXPMARESETDONE;
assign #(out_delay) RXPRBSERR = delay_RXPRBSERR;
assign #(out_delay) RXRATEDONE = delay_RXRATEDONE;
assign #(out_delay) RXRESETDONE = delay_RXRESETDONE;
assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ;
assign #(out_delay) RXSTATUS = delay_RXSTATUS;
assign #(out_delay) RXSYNCDONE = delay_RXSYNCDONE;
assign #(out_delay) RXSYNCOUT = delay_RXSYNCOUT;
assign #(out_delay) RXVALID = delay_RXVALID;
assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS;
assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH;
assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE;
assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY;
assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC;
assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS;
assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE;
assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE;
assign #(out_delay) TXPMARESETDONE = delay_TXPMARESETDONE;
assign #(out_delay) TXRATEDONE = delay_TXRATEDONE;
assign #(out_delay) TXRESETDONE = delay_TXRESETDONE;
assign #(out_delay) TXSYNCDONE = delay_TXSYNCDONE;
assign #(out_delay) TXSYNCOUT = delay_TXSYNCOUT;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG;
assign #(INCLK_DELAY) delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG;
assign #(INCLK_DELAY) delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_PLL0CLK = PLL0CLK;
assign #(INCLK_DELAY) delay_PLL1CLK = PLL1CLK;
assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_SIGVALIDCLK = SIGVALIDCLK^ IS_SIGVALIDCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK;
assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2;
assign #(in_delay) delay_CFGRESET = CFGRESET;
assign #(in_delay) delay_DMONFIFORESET = DMONFIFORESET;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_EYESCANMODE = EYESCANMODE;
assign #(in_delay) delay_EYESCANRESET = EYESCANRESET;
assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign #(in_delay) delay_GTPRXN = GTPRXN;
assign #(in_delay) delay_GTPRXP = GTPRXP;
assign #(in_delay) delay_GTRESETSEL = GTRESETSEL;
assign #(in_delay) delay_GTRSVD = GTRSVD;
assign #(in_delay) delay_GTRXRESET = GTRXRESET;
assign #(in_delay) delay_GTTXRESET = GTTXRESET;
assign #(in_delay) delay_LOOPBACK = LOOPBACK;
assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN;
assign #(in_delay) delay_PLL0REFCLK = PLL0REFCLK;
assign #(in_delay) delay_PLL1REFCLK = PLL1REFCLK;
assign #(in_delay) delay_PMARSVDIN0 = PMARSVDIN0;
assign #(in_delay) delay_PMARSVDIN1 = PMARSVDIN1;
assign #(in_delay) delay_PMARSVDIN2 = PMARSVDIN2;
assign #(in_delay) delay_PMARSVDIN3 = PMARSVDIN3;
assign #(in_delay) delay_PMARSVDIN4 = PMARSVDIN4;
assign #(in_delay) delay_RESETOVRD = RESETOVRD;
assign #(in_delay) delay_RX8B10BEN = RX8B10BEN;
assign #(in_delay) delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign #(in_delay) delay_RXBUFRESET = RXBUFRESET;
assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD;
assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN;
assign #(in_delay) delay_RXCDRRESET = RXCDRRESET;
assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN;
assign #(in_delay) delay_RXCHBONDI = RXCHBONDI;
assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL;
assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER;
assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE;
assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN;
assign #(in_delay) delay_RXDDIEN = RXDDIEN;
assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN;
assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS;
assign #(in_delay) delay_RXDLYEN = RXDLYEN;
assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET;
assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP;
assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign #(in_delay) delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN;
assign #(in_delay) delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN;
assign #(in_delay) delay_RXLPMRESET = RXLPMRESET;
assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN;
assign #(in_delay) delay_RXOOBRESET = RXOOBRESET;
assign #(in_delay) delay_RXOSCALRESET = RXOSCALRESET;
assign #(in_delay) delay_RXOSHOLD = RXOSHOLD;
assign #(in_delay) delay_RXOSINTCFG = RXOSINTCFG;
assign #(in_delay) delay_RXOSINTEN = RXOSINTEN;
assign #(in_delay) delay_RXOSINTHOLD = RXOSINTHOLD;
assign #(in_delay) delay_RXOSINTID0 = RXOSINTID0;
assign #(in_delay) delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign #(in_delay) delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign #(in_delay) delay_RXOSINTPD = RXOSINTPD;
assign #(in_delay) delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign #(in_delay) delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN;
assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN;
assign #(in_delay) delay_RXPCSRESET = RXPCSRESET;
assign #(in_delay) delay_RXPD = RXPD;
assign #(in_delay) delay_RXPHALIGN = RXPHALIGN;
assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN;
assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD;
assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET;
assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN;
assign #(in_delay) delay_RXPMARESET = RXPMARESET;
assign #(in_delay) delay_RXPOLARITY = RXPOLARITY;
assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET;
assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL;
assign #(in_delay) delay_RXRATE = RXRATE;
assign #(in_delay) delay_RXRATEMODE = RXRATEMODE;
assign #(in_delay) delay_RXSLIDE = RXSLIDE;
assign #(in_delay) delay_RXSYNCALLIN = RXSYNCALLIN;
assign #(in_delay) delay_RXSYNCIN = RXSYNCIN;
assign #(in_delay) delay_RXSYNCMODE = RXSYNCMODE;
assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign #(in_delay) delay_RXUSERRDY = RXUSERRDY;
assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS;
assign #(in_delay) delay_TSTIN = TSTIN;
assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS;
assign #(in_delay) delay_TX8B10BEN = TX8B10BEN;
assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE;
assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL;
assign #(in_delay) delay_TXCHARISK = TXCHARISK;
assign #(in_delay) delay_TXCOMINIT = TXCOMINIT;
assign #(in_delay) delay_TXCOMSAS = TXCOMSAS;
assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE;
assign #(in_delay) delay_TXDATA = TXDATA;
assign #(in_delay) delay_TXDEEMPH = TXDEEMPH;
assign #(in_delay) delay_TXDETECTRX = TXDETECTRX;
assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL;
assign #(in_delay) delay_TXDIFFPD = TXDIFFPD;
assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS;
assign #(in_delay) delay_TXDLYEN = TXDLYEN;
assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD;
assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET;
assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN;
assign #(in_delay) delay_TXELECIDLE = TXELECIDLE;
assign #(in_delay) delay_TXHEADER = TXHEADER;
assign #(in_delay) delay_TXINHIBIT = TXINHIBIT;
assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR;
assign #(in_delay) delay_TXMARGIN = TXMARGIN;
assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign #(in_delay) delay_TXPCSRESET = TXPCSRESET;
assign #(in_delay) delay_TXPD = TXPD;
assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign #(in_delay) delay_TXPHALIGN = TXPHALIGN;
assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN;
assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD;
assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET;
assign #(in_delay) delay_TXPHINIT = TXPHINIT;
assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN;
assign #(in_delay) delay_TXPIPPMEN = TXPIPPMEN;
assign #(in_delay) delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN;
assign #(in_delay) delay_TXPIPPMPD = TXPIPPMPD;
assign #(in_delay) delay_TXPIPPMSEL = TXPIPPMSEL;
assign #(in_delay) delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE;
assign #(in_delay) delay_TXPISOPD = TXPISOPD;
assign #(in_delay) delay_TXPMARESET = TXPMARESET;
assign #(in_delay) delay_TXPOLARITY = TXPOLARITY;
assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR;
assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL;
assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR;
assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV;
assign #(in_delay) delay_TXRATE = TXRATE;
assign #(in_delay) delay_TXRATEMODE = TXRATEMODE;
assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE;
assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ;
assign #(in_delay) delay_TXSWING = TXSWING;
assign #(in_delay) delay_TXSYNCALLIN = TXSYNCALLIN;
assign #(in_delay) delay_TXSYNCIN = TXSYNCIN;
assign #(in_delay) delay_TXSYNCMODE = TXSYNCMODE;
assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign #(in_delay) delay_TXUSERRDY = TXUSERRDY;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CFGRESET = CFGRESET;
assign delay_CLKRSVD0 = CLKRSVD0;
assign delay_CLKRSVD1 = CLKRSVD1;
assign delay_DMONFIFORESET = DMONFIFORESET;
assign delay_DMONITORCLK = DMONITORCLK;
assign delay_EYESCANMODE = EYESCANMODE;
assign delay_EYESCANRESET = EYESCANRESET;
assign delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign delay_GTPRXN = GTPRXN;
assign delay_GTPRXP = GTPRXP;
assign delay_GTRESETSEL = GTRESETSEL;
assign delay_GTRSVD = GTRSVD;
assign delay_GTRXRESET = GTRXRESET;
assign delay_GTTXRESET = GTTXRESET;
assign delay_LOOPBACK = LOOPBACK;
assign delay_PCSRSVDIN = PCSRSVDIN;
assign delay_PLL0CLK = PLL0CLK;
assign delay_PLL0REFCLK = PLL0REFCLK;
assign delay_PLL1CLK = PLL1CLK;
assign delay_PLL1REFCLK = PLL1REFCLK;
assign delay_PMARSVDIN0 = PMARSVDIN0;
assign delay_PMARSVDIN1 = PMARSVDIN1;
assign delay_PMARSVDIN2 = PMARSVDIN2;
assign delay_PMARSVDIN3 = PMARSVDIN3;
assign delay_PMARSVDIN4 = PMARSVDIN4;
assign delay_RESETOVRD = RESETOVRD;
assign delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign delay_RXBUFRESET = RXBUFRESET;
assign delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign delay_RXCDRHOLD = RXCDRHOLD;
assign delay_RXCDROVRDEN = RXCDROVRDEN;
assign delay_RXCDRRESET = RXCDRRESET;
assign delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign delay_RXCHBONDI = RXCHBONDI;
assign delay_RXDDIEN = RXDDIEN;
assign delay_RXDFEXYDEN = RXDFEXYDEN;
assign delay_RXDLYBYPASS = RXDLYBYPASS;
assign delay_RXDLYEN = RXDLYEN;
assign delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign delay_RXDLYSRESET = RXDLYSRESET;
assign delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN;
assign delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN;
assign delay_RXLPMRESET = RXLPMRESET;
assign delay_RXOOBRESET = RXOOBRESET;
assign delay_RXOSCALRESET = RXOSCALRESET;
assign delay_RXOSHOLD = RXOSHOLD;
assign delay_RXOSINTCFG = RXOSINTCFG;
assign delay_RXOSINTEN = RXOSINTEN;
assign delay_RXOSINTHOLD = RXOSINTHOLD;
assign delay_RXOSINTID0 = RXOSINTID0;
assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign delay_RXOSINTPD = RXOSINTPD;
assign delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign delay_RXOSOVRDEN = RXOSOVRDEN;
assign delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign delay_RXPCSRESET = RXPCSRESET;
assign delay_RXPD = RXPD;
assign delay_RXPHALIGN = RXPHALIGN;
assign delay_RXPHALIGNEN = RXPHALIGNEN;
assign delay_RXPHDLYPD = RXPHDLYPD;
assign delay_RXPHDLYRESET = RXPHDLYRESET;
assign delay_RXPHOVRDEN = RXPHOVRDEN;
assign delay_RXPMARESET = RXPMARESET;
assign delay_RXRATEMODE = RXRATEMODE;
assign delay_RXSYNCALLIN = RXSYNCALLIN;
assign delay_RXSYNCIN = RXSYNCIN;
assign delay_RXSYNCMODE = RXSYNCMODE;
assign delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign delay_RXUSERRDY = RXUSERRDY;
assign delay_SIGVALIDCLK = SIGVALIDCLK;
assign delay_TSTIN = TSTIN;
assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign delay_TXDEEMPH = TXDEEMPH;
assign delay_TXDIFFCTRL = TXDIFFCTRL;
assign delay_TXDIFFPD = TXDIFFPD;
assign delay_TXDLYBYPASS = TXDLYBYPASS;
assign delay_TXDLYEN = TXDLYEN;
assign delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign delay_TXDLYSRESET = TXDLYSRESET;
assign delay_TXMAINCURSOR = TXMAINCURSOR;
assign delay_TXMARGIN = TXMARGIN;
assign delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign delay_TXPCSRESET = TXPCSRESET;
assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign delay_TXPHALIGN = TXPHALIGN;
assign delay_TXPHALIGNEN = TXPHALIGNEN;
assign delay_TXPHDLYPD = TXPHDLYPD;
assign delay_TXPHDLYRESET = TXPHDLYRESET;
assign delay_TXPHINIT = TXPHINIT;
assign delay_TXPHOVRDEN = TXPHOVRDEN;
assign delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN;
assign delay_TXPIPPMPD = TXPIPPMPD;
assign delay_TXPIPPMSEL = TXPIPPMSEL;
assign delay_TXPISOPD = TXPISOPD;
assign delay_TXPMARESET = TXPMARESET;
assign delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign delay_TXPRECURSOR = TXPRECURSOR;
assign delay_TXPRECURSORINV = TXPRECURSORINV;
assign delay_TXRATEMODE = TXRATEMODE;
assign delay_TXSWING = TXSWING;
assign delay_TXSYNCALLIN = TXSYNCALLIN;
assign delay_TXSYNCIN = TXSYNCIN;
assign delay_TXSYNCMODE = TXSYNCMODE;
assign delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign delay_TXUSERRDY = TXUSERRDY;
`endif
B_GTPE2_CHANNEL #(
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE),
.ACJTAG_MODE (ACJTAG_MODE),
.ACJTAG_RESET (ACJTAG_RESET),
.ADAPT_CFG0 (ADAPT_CFG0),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CFOK_CFG (CFOK_CFG),
.CFOK_CFG2 (CFOK_CFG2),
.CFOK_CFG3 (CFOK_CFG3),
.CFOK_CFG4 (CFOK_CFG4),
.CFOK_CFG5 (CFOK_CFG5),
.CFOK_CFG6 (CFOK_CFG6),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CLK_COMMON_SWING (CLK_COMMON_SWING),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.GEARBOX_MODE (GEARBOX_MODE),
.LOOPBACK_CFG (LOOPBACK_CFG),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV5 (PMA_RSV5),
.PMA_RSV6 (PMA_RSV6),
.PMA_RSV7 (PMA_RSV7),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPMRESET_TIME (RXLPMRESET_TIME),
.RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE),
.RXLPM_CFG (RXLPM_CFG),
.RXLPM_CFG1 (RXLPM_CFG1),
.RXLPM_CM_CFG (RXLPM_CM_CFG),
.RXLPM_GC_CFG (RXLPM_GC_CFG),
.RXLPM_GC_CFG2 (RXLPM_GC_CFG2),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_HF_CFG2 (RXLPM_HF_CFG2),
.RXLPM_HF_CFG3 (RXLPM_HF_CFG3),
.RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE),
.RXLPM_INCM_CFG (RXLPM_INCM_CFG),
.RXLPM_IPCM_CFG (RXLPM_IPCM_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_LF_CFG2 (RXLPM_LF_CFG2),
.RXLPM_OSINT_CFG (RXLPM_OSINT_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME),
.RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT),
.RXOUT_DIV (RXOUT_DIV),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_CFG2 (RXPI_CFG2),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE),
.RXSYNC_OVRD (RXSYNC_OVRD),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (RX_CLKMUX_EN),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.RX_XCLK_SEL (RX_XCLK_SEL),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_PLL_CFG (SATA_PLL_CFG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOOB_CFG (TXOOB_CFG),
.TXOUT_DIV (TXOUT_DIV),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_CFG2 (TXPI_CFG2),
.TXPI_CFG3 (TXPI_CFG3),
.TXPI_CFG4 (TXPI_CFG4),
.TXPI_CFG5 (TXPI_CFG5),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_OVRD (TXSYNC_OVRD),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (TX_CLKMUX_EN),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL (TX_XCLK_SEL),
.UCODEER_CLR (UCODEER_CLR),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL))
B_GTPE2_CHANNEL_INST (
.DMONITOROUT (delay_DMONITOROUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.EYESCANDATAERROR (delay_EYESCANDATAERROR),
.GTPTXN (delay_GTPTXN),
.GTPTXP (delay_GTPTXP),
.PCSRSVDOUT (delay_PCSRSVDOUT),
.PHYSTATUS (delay_PHYSTATUS),
.PMARSVDOUT0 (delay_PMARSVDOUT0),
.PMARSVDOUT1 (delay_PMARSVDOUT1),
.RXBUFSTATUS (delay_RXBUFSTATUS),
.RXBYTEISALIGNED (delay_RXBYTEISALIGNED),
.RXBYTEREALIGN (delay_RXBYTEREALIGN),
.RXCDRLOCK (delay_RXCDRLOCK),
.RXCHANBONDSEQ (delay_RXCHANBONDSEQ),
.RXCHANISALIGNED (delay_RXCHANISALIGNED),
.RXCHANREALIGN (delay_RXCHANREALIGN),
.RXCHARISCOMMA (delay_RXCHARISCOMMA),
.RXCHARISK (delay_RXCHARISK),
.RXCHBONDO (delay_RXCHBONDO),
.RXCLKCORCNT (delay_RXCLKCORCNT),
.RXCOMINITDET (delay_RXCOMINITDET),
.RXCOMMADET (delay_RXCOMMADET),
.RXCOMSASDET (delay_RXCOMSASDET),
.RXCOMWAKEDET (delay_RXCOMWAKEDET),
.RXDATA (delay_RXDATA),
.RXDATAVALID (delay_RXDATAVALID),
.RXDISPERR (delay_RXDISPERR),
.RXDLYSRESETDONE (delay_RXDLYSRESETDONE),
.RXELECIDLE (delay_RXELECIDLE),
.RXHEADER (delay_RXHEADER),
.RXHEADERVALID (delay_RXHEADERVALID),
.RXNOTINTABLE (delay_RXNOTINTABLE),
.RXOSINTDONE (delay_RXOSINTDONE),
.RXOSINTSTARTED (delay_RXOSINTSTARTED),
.RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE),
.RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED),
.RXOUTCLK (delay_RXOUTCLK),
.RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC),
.RXOUTCLKPCS (delay_RXOUTCLKPCS),
.RXPHALIGNDONE (delay_RXPHALIGNDONE),
.RXPHMONITOR (delay_RXPHMONITOR),
.RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR),
.RXPMARESETDONE (delay_RXPMARESETDONE),
.RXPRBSERR (delay_RXPRBSERR),
.RXRATEDONE (delay_RXRATEDONE),
.RXRESETDONE (delay_RXRESETDONE),
.RXSTARTOFSEQ (delay_RXSTARTOFSEQ),
.RXSTATUS (delay_RXSTATUS),
.RXSYNCDONE (delay_RXSYNCDONE),
.RXSYNCOUT (delay_RXSYNCOUT),
.RXVALID (delay_RXVALID),
.TXBUFSTATUS (delay_TXBUFSTATUS),
.TXCOMFINISH (delay_TXCOMFINISH),
.TXDLYSRESETDONE (delay_TXDLYSRESETDONE),
.TXGEARBOXREADY (delay_TXGEARBOXREADY),
.TXOUTCLK (delay_TXOUTCLK),
.TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC),
.TXOUTCLKPCS (delay_TXOUTCLKPCS),
.TXPHALIGNDONE (delay_TXPHALIGNDONE),
.TXPHINITDONE (delay_TXPHINITDONE),
.TXPMARESETDONE (delay_TXPMARESETDONE),
.TXRATEDONE (delay_TXRATEDONE),
.TXRESETDONE (delay_TXRESETDONE),
.TXSYNCDONE (delay_TXSYNCDONE),
.TXSYNCOUT (delay_TXSYNCOUT),
.CFGRESET (delay_CFGRESET),
.CLKRSVD0 (delay_CLKRSVD0),
.CLKRSVD1 (delay_CLKRSVD1),
.DMONFIFORESET (delay_DMONFIFORESET),
.DMONITORCLK (delay_DMONITORCLK),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.EYESCANMODE (delay_EYESCANMODE),
.EYESCANRESET (delay_EYESCANRESET),
.EYESCANTRIGGER (delay_EYESCANTRIGGER),
.GTPRXN (delay_GTPRXN),
.GTPRXP (delay_GTPRXP),
.GTRESETSEL (delay_GTRESETSEL),
.GTRSVD (delay_GTRSVD),
.GTRXRESET (delay_GTRXRESET),
.GTTXRESET (delay_GTTXRESET),
.LOOPBACK (delay_LOOPBACK),
.PCSRSVDIN (delay_PCSRSVDIN),
.PLL0CLK (delay_PLL0CLK),
.PLL0REFCLK (delay_PLL0REFCLK),
.PLL1CLK (delay_PLL1CLK),
.PLL1REFCLK (delay_PLL1REFCLK),
.PMARSVDIN0 (delay_PMARSVDIN0),
.PMARSVDIN1 (delay_PMARSVDIN1),
.PMARSVDIN2 (delay_PMARSVDIN2),
.PMARSVDIN3 (delay_PMARSVDIN3),
.PMARSVDIN4 (delay_PMARSVDIN4),
.RESETOVRD (delay_RESETOVRD),
.RX8B10BEN (delay_RX8B10BEN),
.RXADAPTSELTEST (delay_RXADAPTSELTEST),
.RXBUFRESET (delay_RXBUFRESET),
.RXCDRFREQRESET (delay_RXCDRFREQRESET),
.RXCDRHOLD (delay_RXCDRHOLD),
.RXCDROVRDEN (delay_RXCDROVRDEN),
.RXCDRRESET (delay_RXCDRRESET),
.RXCDRRESETRSV (delay_RXCDRRESETRSV),
.RXCHBONDEN (delay_RXCHBONDEN),
.RXCHBONDI (delay_RXCHBONDI),
.RXCHBONDLEVEL (delay_RXCHBONDLEVEL),
.RXCHBONDMASTER (delay_RXCHBONDMASTER),
.RXCHBONDSLAVE (delay_RXCHBONDSLAVE),
.RXCOMMADETEN (delay_RXCOMMADETEN),
.RXDDIEN (delay_RXDDIEN),
.RXDFEXYDEN (delay_RXDFEXYDEN),
.RXDLYBYPASS (delay_RXDLYBYPASS),
.RXDLYEN (delay_RXDLYEN),
.RXDLYOVRDEN (delay_RXDLYOVRDEN),
.RXDLYSRESET (delay_RXDLYSRESET),
.RXELECIDLEMODE (delay_RXELECIDLEMODE),
.RXGEARBOXSLIP (delay_RXGEARBOXSLIP),
.RXLPMHFHOLD (delay_RXLPMHFHOLD),
.RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN),
.RXLPMLFHOLD (delay_RXLPMLFHOLD),
.RXLPMLFOVRDEN (delay_RXLPMLFOVRDEN),
.RXLPMOSINTNTRLEN (delay_RXLPMOSINTNTRLEN),
.RXLPMRESET (delay_RXLPMRESET),
.RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN),
.RXOOBRESET (delay_RXOOBRESET),
.RXOSCALRESET (delay_RXOSCALRESET),
.RXOSHOLD (delay_RXOSHOLD),
.RXOSINTCFG (delay_RXOSINTCFG),
.RXOSINTEN (delay_RXOSINTEN),
.RXOSINTHOLD (delay_RXOSINTHOLD),
.RXOSINTID0 (delay_RXOSINTID0),
.RXOSINTNTRLEN (delay_RXOSINTNTRLEN),
.RXOSINTOVRDEN (delay_RXOSINTOVRDEN),
.RXOSINTPD (delay_RXOSINTPD),
.RXOSINTSTROBE (delay_RXOSINTSTROBE),
.RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN),
.RXOSOVRDEN (delay_RXOSOVRDEN),
.RXOUTCLKSEL (delay_RXOUTCLKSEL),
.RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN),
.RXPCSRESET (delay_RXPCSRESET),
.RXPD (delay_RXPD),
.RXPHALIGN (delay_RXPHALIGN),
.RXPHALIGNEN (delay_RXPHALIGNEN),
.RXPHDLYPD (delay_RXPHDLYPD),
.RXPHDLYRESET (delay_RXPHDLYRESET),
.RXPHOVRDEN (delay_RXPHOVRDEN),
.RXPMARESET (delay_RXPMARESET),
.RXPOLARITY (delay_RXPOLARITY),
.RXPRBSCNTRESET (delay_RXPRBSCNTRESET),
.RXPRBSSEL (delay_RXPRBSSEL),
.RXRATE (delay_RXRATE),
.RXRATEMODE (delay_RXRATEMODE),
.RXSLIDE (delay_RXSLIDE),
.RXSYNCALLIN (delay_RXSYNCALLIN),
.RXSYNCIN (delay_RXSYNCIN),
.RXSYNCMODE (delay_RXSYNCMODE),
.RXSYSCLKSEL (delay_RXSYSCLKSEL),
.RXUSERRDY (delay_RXUSERRDY),
.RXUSRCLK (delay_RXUSRCLK),
.RXUSRCLK2 (delay_RXUSRCLK2),
.SETERRSTATUS (delay_SETERRSTATUS),
.SIGVALIDCLK (delay_SIGVALIDCLK),
.TSTIN (delay_TSTIN),
.TX8B10BBYPASS (delay_TX8B10BBYPASS),
.TX8B10BEN (delay_TX8B10BEN),
.TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL),
.TXCHARDISPMODE (delay_TXCHARDISPMODE),
.TXCHARDISPVAL (delay_TXCHARDISPVAL),
.TXCHARISK (delay_TXCHARISK),
.TXCOMINIT (delay_TXCOMINIT),
.TXCOMSAS (delay_TXCOMSAS),
.TXCOMWAKE (delay_TXCOMWAKE),
.TXDATA (delay_TXDATA),
.TXDEEMPH (delay_TXDEEMPH),
.TXDETECTRX (delay_TXDETECTRX),
.TXDIFFCTRL (delay_TXDIFFCTRL),
.TXDIFFPD (delay_TXDIFFPD),
.TXDLYBYPASS (delay_TXDLYBYPASS),
.TXDLYEN (delay_TXDLYEN),
.TXDLYHOLD (delay_TXDLYHOLD),
.TXDLYOVRDEN (delay_TXDLYOVRDEN),
.TXDLYSRESET (delay_TXDLYSRESET),
.TXDLYUPDOWN (delay_TXDLYUPDOWN),
.TXELECIDLE (delay_TXELECIDLE),
.TXHEADER (delay_TXHEADER),
.TXINHIBIT (delay_TXINHIBIT),
.TXMAINCURSOR (delay_TXMAINCURSOR),
.TXMARGIN (delay_TXMARGIN),
.TXOUTCLKSEL (delay_TXOUTCLKSEL),
.TXPCSRESET (delay_TXPCSRESET),
.TXPD (delay_TXPD),
.TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE),
.TXPHALIGN (delay_TXPHALIGN),
.TXPHALIGNEN (delay_TXPHALIGNEN),
.TXPHDLYPD (delay_TXPHDLYPD),
.TXPHDLYRESET (delay_TXPHDLYRESET),
.TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK),
.TXPHINIT (delay_TXPHINIT),
.TXPHOVRDEN (delay_TXPHOVRDEN),
.TXPIPPMEN (delay_TXPIPPMEN),
.TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN),
.TXPIPPMPD (delay_TXPIPPMPD),
.TXPIPPMSEL (delay_TXPIPPMSEL),
.TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE),
.TXPISOPD (delay_TXPISOPD),
.TXPMARESET (delay_TXPMARESET),
.TXPOLARITY (delay_TXPOLARITY),
.TXPOSTCURSOR (delay_TXPOSTCURSOR),
.TXPOSTCURSORINV (delay_TXPOSTCURSORINV),
.TXPRBSFORCEERR (delay_TXPRBSFORCEERR),
.TXPRBSSEL (delay_TXPRBSSEL),
.TXPRECURSOR (delay_TXPRECURSOR),
.TXPRECURSORINV (delay_TXPRECURSORINV),
.TXRATE (delay_TXRATE),
.TXRATEMODE (delay_TXRATEMODE),
.TXSEQUENCE (delay_TXSEQUENCE),
.TXSTARTSEQ (delay_TXSTARTSEQ),
.TXSWING (delay_TXSWING),
.TXSYNCALLIN (delay_TXSYNCALLIN),
.TXSYNCIN (delay_TXSYNCIN),
.TXSYNCMODE (delay_TXSYNCMODE),
.TXSYSCLKSEL (delay_TXSYSCLKSEL),
.TXUSERRDY (delay_TXUSERRDY),
.TXUSRCLK (delay_TXUSRCLK),
.TXUSRCLK2 (delay_TXUSRCLK2),
.GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CLKRSVD0, 0:0:0, notifier);
$period (posedge CLKRSVD1, 0:0:0, notifier);
$period (posedge DMONITORCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge PLL0CLK, 0:0:0, notifier);
$period (posedge PLL1CLK, 0:0:0, notifier);
$period (posedge RXOUTCLK, 0:0:0, notifier);
$period (posedge RXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge RXOUTCLKPCS, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge SIGVALIDCLK, 0:0:0, notifier);
$period (posedge TXOUTCLK, 0:0:0, notifier);
$period (posedge TXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge TXOUTCLKPCS, 0:0:0, notifier);
$period (posedge TXPHDLYTSTCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
`endif
( DMONITORCLK *> DMONITOROUT) = (0, 0);
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( RXUSRCLK2 *> PHYSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0);
( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0);
( RXUSRCLK2 *> RXCHARISK) = (0, 0);
( RXUSRCLK2 *> RXCHBONDO) = (0, 0);
( RXUSRCLK *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0);
( RXUSRCLK2 *> RXCOMINITDET) = (0, 0);
( RXUSRCLK2 *> RXCOMMADET) = (0, 0);
( RXUSRCLK2 *> RXCOMSASDET) = (0, 0);
( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0);
( RXUSRCLK2 *> RXDATA) = (0, 0);
( RXUSRCLK2 *> RXDATAVALID) = (0, 0);
( RXUSRCLK2 *> RXDISPERR) = (0, 0);
( RXUSRCLK2 *> RXHEADER) = (0, 0);
( RXUSRCLK2 *> RXHEADERVALID) = (0, 0);
( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0);
( RXUSRCLK2 *> RXPRBSERR) = (0, 0);
( RXUSRCLK2 *> RXRATEDONE) = (0, 0);
( RXUSRCLK2 *> RXRESETDONE) = (0, 0);
( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0);
( RXUSRCLK2 *> RXSTATUS) = (0, 0);
( RXUSRCLK2 *> RXVALID) = (0, 0);
( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0);
( TXUSRCLK2 *> TXCOMFINISH) = (0, 0);
( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0);
( TXUSRCLK2 *> TXRATEDONE) = (0, 0);
( TXUSRCLK2 *> TXRESETDONE) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTPE2_COMMON.v 0000664 0000000 0000000 00000055426 12327044266 0023327 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTPE2_COMMON.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 11/8/12 - 686589 - YML default changes
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTPE2_COMMON (
DMONITOROUT,
DRPDO,
DRPRDY,
PLL0FBCLKLOST,
PLL0LOCK,
PLL0OUTCLK,
PLL0OUTREFCLK,
PLL0REFCLKLOST,
PLL1FBCLKLOST,
PLL1LOCK,
PLL1OUTCLK,
PLL1OUTREFCLK,
PLL1REFCLKLOST,
PMARSVDOUT,
REFCLKOUTMONITOR0,
REFCLKOUTMONITOR1,
BGBYPASSB,
BGMONITORENB,
BGPDB,
BGRCALOVRD,
BGRCALOVRDENB,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
GTEASTREFCLK0,
GTEASTREFCLK1,
GTGREFCLK0,
GTGREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTWESTREFCLK0,
GTWESTREFCLK1,
PLL0LOCKDETCLK,
PLL0LOCKEN,
PLL0PD,
PLL0REFCLKSEL,
PLL0RESET,
PLL1LOCKDETCLK,
PLL1LOCKEN,
PLL1PD,
PLL1REFCLKSEL,
PLL1RESET,
PLLRSVD1,
PLLRSVD2,
PMARSVD,
RCALENB
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [63:0] BIAS_CFG = 64'h0000000000000000;
parameter [31:0] COMMON_CFG = 32'h00000000;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
parameter [26:0] PLL0_CFG = 27'h01F03DC;
parameter [0:0] PLL0_DMON_CFG = 1'b0;
parameter integer PLL0_FBDIV = 4;
parameter integer PLL0_FBDIV_45 = 5;
parameter [23:0] PLL0_INIT_CFG = 24'h00001E;
parameter [8:0] PLL0_LOCK_CFG = 9'h1E8;
parameter integer PLL0_REFCLK_DIV = 1;
parameter [26:0] PLL1_CFG = 27'h01F03DC;
parameter [0:0] PLL1_DMON_CFG = 1'b0;
parameter integer PLL1_FBDIV = 4;
parameter integer PLL1_FBDIV_45 = 5;
parameter [23:0] PLL1_INIT_CFG = 24'h00001E;
parameter [8:0] PLL1_LOCK_CFG = 9'h1E8;
parameter integer PLL1_REFCLK_DIV = 1;
parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000;
parameter [15:0] RSVD_ATTR0 = 16'h0000;
parameter [15:0] RSVD_ATTR1 = 16'h0000;
parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001;
parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001;
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_VERSION = "1.0";
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output PLL0FBCLKLOST;
output PLL0LOCK;
output PLL0OUTCLK;
output PLL0OUTREFCLK;
output PLL0REFCLKLOST;
output PLL1FBCLKLOST;
output PLL1LOCK;
output PLL1OUTCLK;
output PLL1OUTREFCLK;
output PLL1REFCLKLOST;
output REFCLKOUTMONITOR0;
output REFCLKOUTMONITOR1;
output [15:0] DRPDO;
output [15:0] PMARSVDOUT;
output [7:0] DMONITOROUT;
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
input BGRCALOVRDENB;
input DRPCLK;
input DRPEN;
input DRPWE;
input GTEASTREFCLK0;
input GTEASTREFCLK1;
input GTGREFCLK0;
input GTGREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTWESTREFCLK0;
input GTWESTREFCLK1;
input PLL0LOCKDETCLK;
input PLL0LOCKEN;
input PLL0PD;
input PLL0RESET;
input PLL1LOCKDETCLK;
input PLL1LOCKEN;
input PLL1PD;
input PLL1RESET;
input RCALENB;
input [15:0] DRPDI;
input [15:0] PLLRSVD1;
input [2:0] PLL0REFCLKSEL;
input [2:0] PLL1REFCLKSEL;
input [4:0] BGRCALOVRD;
input [4:0] PLLRSVD2;
input [7:0] DRPADDR;
input [7:0] PMARSVD;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] PLL0_DMON_CFG_BINARY;
reg [0:0] PLL0_FBDIV_45_BINARY;
reg [0:0] PLL1_DMON_CFG_BINARY;
reg [0:0] PLL1_FBDIV_45_BINARY;
reg [2:0] SIM_PLL0REFCLK_SEL_BINARY;
reg [2:0] SIM_PLL1REFCLK_SEL_BINARY;
reg [4:0] PLL0_REFCLK_DIV_BINARY;
reg [4:0] PLL1_REFCLK_DIV_BINARY;
reg [5:0] PLL0_FBDIV_BINARY;
reg [5:0] PLL1_FBDIV_BINARY;
reg [7:0] PLL_CLKOUT_CFG_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (PLL0_FBDIV)
4 : PLL0_FBDIV_BINARY = 6'b000010;
1 : PLL0_FBDIV_BINARY = 6'b010000;
2 : PLL0_FBDIV_BINARY = 6'b000000;
3 : PLL0_FBDIV_BINARY = 6'b000001;
5 : PLL0_FBDIV_BINARY = 6'b000011;
6 : PLL0_FBDIV_BINARY = 6'b000101;
8 : PLL0_FBDIV_BINARY = 6'b000110;
10 : PLL0_FBDIV_BINARY = 6'b000111;
12 : PLL0_FBDIV_BINARY = 6'b001101;
16 : PLL0_FBDIV_BINARY = 6'b001110;
20 : PLL0_FBDIV_BINARY = 6'b001111;
default : begin
$display("Attribute Syntax Error : The Attribute PLL0_FBDIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL0_FBDIV, 4);
$finish;
end
endcase
case (PLL0_FBDIV_45)
5 : PLL0_FBDIV_45_BINARY = 1'b1;
4 : PLL0_FBDIV_45_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PLL0_FBDIV_45 on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 4 to 5.", PLL0_FBDIV_45, 5);
$finish;
end
endcase
case (PLL0_REFCLK_DIV)
1 : PLL0_REFCLK_DIV_BINARY = 5'b10000;
2 : PLL0_REFCLK_DIV_BINARY = 5'b00000;
3 : PLL0_REFCLK_DIV_BINARY = 5'b00001;
4 : PLL0_REFCLK_DIV_BINARY = 5'b00010;
5 : PLL0_REFCLK_DIV_BINARY = 5'b00011;
6 : PLL0_REFCLK_DIV_BINARY = 5'b00101;
8 : PLL0_REFCLK_DIV_BINARY = 5'b00110;
10 : PLL0_REFCLK_DIV_BINARY = 5'b00111;
12 : PLL0_REFCLK_DIV_BINARY = 5'b01101;
16 : PLL0_REFCLK_DIV_BINARY = 5'b01110;
20 : PLL0_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute PLL0_REFCLK_DIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL0_REFCLK_DIV, 1);
$finish;
end
endcase
case (PLL1_FBDIV)
4 : PLL1_FBDIV_BINARY = 6'b000010;
1 : PLL1_FBDIV_BINARY = 6'b010000;
2 : PLL1_FBDIV_BINARY = 6'b000000;
3 : PLL1_FBDIV_BINARY = 6'b000001;
5 : PLL1_FBDIV_BINARY = 6'b000011;
6 : PLL1_FBDIV_BINARY = 6'b000101;
8 : PLL1_FBDIV_BINARY = 6'b000110;
10 : PLL1_FBDIV_BINARY = 6'b000111;
12 : PLL1_FBDIV_BINARY = 6'b001101;
16 : PLL1_FBDIV_BINARY = 6'b001110;
20 : PLL1_FBDIV_BINARY = 6'b001111;
default : begin
$display("Attribute Syntax Error : The Attribute PLL1_FBDIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL1_FBDIV, 4);
$finish;
end
endcase
case (PLL1_FBDIV_45)
5 : PLL1_FBDIV_45_BINARY = 1'b1;
4 : PLL1_FBDIV_45_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PLL1_FBDIV_45 on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 4 to 5.", PLL1_FBDIV_45, 5);
$finish;
end
endcase
case (PLL1_REFCLK_DIV)
1 : PLL1_REFCLK_DIV_BINARY = 5'b10000;
2 : PLL1_REFCLK_DIV_BINARY = 5'b00000;
3 : PLL1_REFCLK_DIV_BINARY = 5'b00001;
4 : PLL1_REFCLK_DIV_BINARY = 5'b00010;
5 : PLL1_REFCLK_DIV_BINARY = 5'b00011;
6 : PLL1_REFCLK_DIV_BINARY = 5'b00101;
8 : PLL1_REFCLK_DIV_BINARY = 5'b00110;
10 : PLL1_REFCLK_DIV_BINARY = 5'b00111;
12 : PLL1_REFCLK_DIV_BINARY = 5'b01101;
16 : PLL1_REFCLK_DIV_BINARY = 5'b01110;
20 : PLL1_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute PLL1_REFCLK_DIV on X_GTPE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", PLL1_REFCLK_DIV, 1);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_COMMON instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION);
$finish;
end
endcase
if ((PLL0_DMON_CFG >= 1'b0) && (PLL0_DMON_CFG <= 1'b1))
PLL0_DMON_CFG_BINARY = PLL0_DMON_CFG;
else begin
$display("Attribute Syntax Error : The Attribute PLL0_DMON_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PLL0_DMON_CFG);
$finish;
end
if ((PLL1_DMON_CFG >= 1'b0) && (PLL1_DMON_CFG <= 1'b1))
PLL1_DMON_CFG_BINARY = PLL1_DMON_CFG;
else begin
$display("Attribute Syntax Error : The Attribute PLL1_DMON_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PLL1_DMON_CFG);
$finish;
end
if ((PLL_CLKOUT_CFG >= 8'b00000000) && (PLL_CLKOUT_CFG <= 8'b11111111))
PLL_CLKOUT_CFG_BINARY = PLL_CLKOUT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute PLL_CLKOUT_CFG on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", PLL_CLKOUT_CFG);
$finish;
end
if ((SIM_PLL0REFCLK_SEL >= 3'b0) && (SIM_PLL0REFCLK_SEL <= 3'b111))
SIM_PLL0REFCLK_SEL_BINARY = SIM_PLL0REFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_PLL0REFCLK_SEL on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_PLL0REFCLK_SEL);
$finish;
end
if ((SIM_PLL1REFCLK_SEL >= 3'b0) && (SIM_PLL1REFCLK_SEL <= 3'b111))
SIM_PLL1REFCLK_SEL_BINARY = SIM_PLL1REFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_PLL1REFCLK_SEL on X_GTPE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_PLL1REFCLK_SEL);
$finish;
end
end
wire [15:0] delay_DRPDO;
wire [15:0] delay_PMARSVDOUT;
wire [7:0] delay_DMONITOROUT;
wire delay_DRPRDY;
wire delay_PLL0FBCLKLOST;
wire delay_PLL0LOCK;
wire delay_PLL0OUTCLK;
wire delay_PLL0OUTREFCLK;
wire delay_PLL0REFCLKLOST;
wire delay_PLL1FBCLKLOST;
wire delay_PLL1LOCK;
wire delay_PLL1OUTCLK;
wire delay_PLL1OUTREFCLK;
wire delay_PLL1REFCLKLOST;
wire delay_REFCLKOUTMONITOR0;
wire delay_REFCLKOUTMONITOR1;
wire [15:0] delay_DRPDI;
wire [15:0] delay_PLLRSVD1;
wire [2:0] delay_PLL0REFCLKSEL;
wire [2:0] delay_PLL1REFCLKSEL;
wire [4:0] delay_BGRCALOVRD;
wire [4:0] delay_PLLRSVD2;
wire [7:0] delay_DRPADDR;
wire [7:0] delay_PMARSVD;
wire delay_BGBYPASSB;
wire delay_BGMONITORENB;
wire delay_BGPDB;
wire delay_BGRCALOVRDENB;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_GTEASTREFCLK0;
wire delay_GTEASTREFCLK1;
wire delay_GTGREFCLK0;
wire delay_GTGREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTWESTREFCLK0;
wire delay_GTWESTREFCLK1;
wire delay_PLL0LOCKDETCLK;
wire delay_PLL0LOCKEN;
wire delay_PLL0PD;
wire delay_PLL0RESET;
wire delay_PLL1LOCKDETCLK;
wire delay_PLL1LOCKEN;
wire delay_PLL1PD;
wire delay_PLL1RESET;
wire delay_RCALENB;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK0_INVERTED_REG = IS_GTGREFCLK0_INVERTED;
reg [0:0] IS_GTGREFCLK1_INVERTED_REG = IS_GTGREFCLK1_INVERTED;
reg [0:0] IS_PLL0LOCKDETCLK_INVERTED_REG = IS_PLL0LOCKDETCLK_INVERTED;
reg [0:0] IS_PLL1LOCKDETCLK_INVERTED_REG = IS_PLL1LOCKDETCLK_INVERTED;
assign #(OUTCLK_DELAY) PLL0OUTCLK = delay_PLL0OUTCLK;
assign #(OUTCLK_DELAY) PLL1OUTCLK = delay_PLL1OUTCLK;
assign #(OUTCLK_DELAY) REFCLKOUTMONITOR0 = delay_REFCLKOUTMONITOR0;
assign #(OUTCLK_DELAY) REFCLKOUTMONITOR1 = delay_REFCLKOUTMONITOR1;
assign #(out_delay) DMONITOROUT = delay_DMONITOROUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) PLL0FBCLKLOST = delay_PLL0FBCLKLOST;
assign #(out_delay) PLL0LOCK = delay_PLL0LOCK;
assign #(out_delay) PLL0OUTREFCLK = delay_PLL0OUTREFCLK;
assign #(out_delay) PLL0REFCLKLOST = delay_PLL0REFCLKLOST;
assign #(out_delay) PLL1FBCLKLOST = delay_PLL1FBCLKLOST;
assign #(out_delay) PLL1LOCK = delay_PLL1LOCK;
assign #(out_delay) PLL1OUTREFCLK = delay_PLL1OUTREFCLK;
assign #(out_delay) PLL1REFCLKLOST = delay_PLL1REFCLKLOST;
assign #(out_delay) PMARSVDOUT = delay_PMARSVDOUT;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTEASTREFCLK0 = GTEASTREFCLK0 ^ IS_GTGREFCLK0_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTEASTREFCLK1 = GTEASTREFCLK1 ^ IS_GTGREFCLK1_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK0 = GTGREFCLK0;
assign #(INCLK_DELAY) delay_GTGREFCLK1 = GTGREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTWESTREFCLK0 = GTWESTREFCLK0;
assign #(INCLK_DELAY) delay_GTWESTREFCLK1 = GTWESTREFCLK1;
assign #(INCLK_DELAY) delay_PLL0LOCKDETCLK = PLL0LOCKDETCLK ^ IS_PLL0LOCKDETCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_PLL1LOCKDETCLK = PLL1LOCKDETCLK^ IS_PLL1LOCKDETCLK_INVERTED_REG;
assign #(in_delay) delay_BGBYPASSB = BGBYPASSB;
assign #(in_delay) delay_BGMONITORENB = BGMONITORENB;
assign #(in_delay) delay_BGPDB = BGPDB;
assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD;
assign #(in_delay) delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_PLL0LOCKEN = PLL0LOCKEN;
assign #(in_delay) delay_PLL0PD = PLL0PD;
assign #(in_delay) delay_PLL0REFCLKSEL = PLL0REFCLKSEL;
assign #(in_delay) delay_PLL0RESET = PLL0RESET;
assign #(in_delay) delay_PLL1LOCKEN = PLL1LOCKEN;
assign #(in_delay) delay_PLL1PD = PLL1PD;
assign #(in_delay) delay_PLL1REFCLKSEL = PLL1REFCLKSEL;
assign #(in_delay) delay_PLL1RESET = PLL1RESET;
assign #(in_delay) delay_PLLRSVD1 = PLLRSVD1;
assign #(in_delay) delay_PLLRSVD2 = PLLRSVD2;
assign #(in_delay) delay_PMARSVD = PMARSVD;
assign #(in_delay) delay_RCALENB = RCALENB;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign delay_GTEASTREFCLK0 = GTEASTREFCLK0;
assign delay_GTEASTREFCLK1 = GTEASTREFCLK1;
assign delay_GTGREFCLK0 = GTGREFCLK0;
assign delay_GTGREFCLK1 = GTGREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTWESTREFCLK0 = GTWESTREFCLK0;
assign delay_GTWESTREFCLK1 = GTWESTREFCLK1;
assign delay_PLL0LOCKDETCLK = PLL0LOCKDETCLK;
assign delay_PLL0LOCKEN = PLL0LOCKEN;
assign delay_PLL0PD = PLL0PD;
assign delay_PLL0REFCLKSEL = PLL0REFCLKSEL;
assign delay_PLL0RESET = PLL0RESET;
assign delay_PLL1LOCKDETCLK = PLL1LOCKDETCLK;
assign delay_PLL1LOCKEN = PLL1LOCKEN;
assign delay_PLL1PD = PLL1PD;
assign delay_PLL1REFCLKSEL = PLL1REFCLKSEL;
assign delay_PLL1RESET = PLL1RESET;
assign delay_PLLRSVD1 = PLLRSVD1;
assign delay_PLLRSVD2 = PLLRSVD2;
assign delay_PMARSVD = PMARSVD;
assign delay_RCALENB = RCALENB;
`endif
B_GTPE2_COMMON #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV),
.PLL0_FBDIV_45 (PLL0_FBDIV_45),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV),
.PLL1_FBDIV_45 (PLL1_FBDIV_45),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.SIM_PLL0REFCLK_SEL (SIM_PLL0REFCLK_SEL),
.SIM_PLL1REFCLK_SEL (SIM_PLL1REFCLK_SEL),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION))
B_GTPE2_COMMON_INST (
.DMONITOROUT (delay_DMONITOROUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.PLL0FBCLKLOST (delay_PLL0FBCLKLOST),
.PLL0LOCK (delay_PLL0LOCK),
.PLL0OUTCLK (delay_PLL0OUTCLK),
.PLL0OUTREFCLK (delay_PLL0OUTREFCLK),
.PLL0REFCLKLOST (delay_PLL0REFCLKLOST),
.PLL1FBCLKLOST (delay_PLL1FBCLKLOST),
.PLL1LOCK (delay_PLL1LOCK),
.PLL1OUTCLK (delay_PLL1OUTCLK),
.PLL1OUTREFCLK (delay_PLL1OUTREFCLK),
.PLL1REFCLKLOST (delay_PLL1REFCLKLOST),
.PMARSVDOUT (delay_PMARSVDOUT),
.REFCLKOUTMONITOR0 (delay_REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (delay_REFCLKOUTMONITOR1),
.BGBYPASSB (delay_BGBYPASSB),
.BGMONITORENB (delay_BGMONITORENB),
.BGPDB (delay_BGPDB),
.BGRCALOVRD (delay_BGRCALOVRD),
.BGRCALOVRDENB (delay_BGRCALOVRDENB),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.GTEASTREFCLK0 (delay_GTEASTREFCLK0),
.GTEASTREFCLK1 (delay_GTEASTREFCLK1),
.GTGREFCLK0 (delay_GTGREFCLK0),
.GTGREFCLK1 (delay_GTGREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTWESTREFCLK0 (delay_GTWESTREFCLK0),
.GTWESTREFCLK1 (delay_GTWESTREFCLK1),
.PLL0LOCKDETCLK (delay_PLL0LOCKDETCLK),
.PLL0LOCKEN (delay_PLL0LOCKEN),
.PLL0PD (delay_PLL0PD),
.PLL0REFCLKSEL (delay_PLL0REFCLKSEL),
.PLL0RESET (delay_PLL0RESET),
.PLL1LOCKDETCLK (delay_PLL1LOCKDETCLK),
.PLL1LOCKEN (delay_PLL1LOCKEN),
.PLL1PD (delay_PLL1PD),
.PLL1REFCLKSEL (delay_PLL1REFCLKSEL),
.PLL1RESET (delay_PLL1RESET),
.PLLRSVD1 (delay_PLLRSVD1),
.PLLRSVD2 (delay_PLLRSVD2),
.PMARSVD (delay_PMARSVD),
.RCALENB (delay_RCALENB),
.GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge GTEASTREFCLK0, 0:0:0, notifier);
$period (posedge GTEASTREFCLK1, 0:0:0, notifier);
$period (posedge GTGREFCLK0, 0:0:0, notifier);
$period (posedge GTGREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTWESTREFCLK0, 0:0:0, notifier);
$period (posedge GTWESTREFCLK1, 0:0:0, notifier);
$period (posedge PLL0LOCKDETCLK, 0:0:0, notifier);
$period (posedge PLL0OUTCLK, 0:0:0, notifier);
$period (posedge PLL1LOCKDETCLK, 0:0:0, notifier);
$period (posedge PLL1OUTCLK, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR0, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR1, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
`endif
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTGREFCLK0 *> REFCLKOUTMONITOR0) = (0, 0);
( GTGREFCLK0 *> REFCLKOUTMONITOR1) = (0, 0);
( GTGREFCLK1 *> REFCLKOUTMONITOR0) = (0, 0);
( GTGREFCLK1 *> REFCLKOUTMONITOR1) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR0) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR1) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR0) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR1) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTXE2_CHANNEL.v 0000664 0000000 0000000 00000442637 12327044266 0023423 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / /
// /__/ /\ Filename : GTXE2_CHANNEL.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 11/10/09 - CR - Initial version
// 02/28/11 - CR595054 - Add missing setuphold check - RXCHBONDI-RXUSRCLK2
// 03/24/11 - CR596791 - CLKRSVD<1> minperiod & pathdelay added
// 04/01/11 - CR596791 - update CLKRSVD[1] bit to bus timing
// 05/12/11 - CR608414 - Attribute name YML update
// 05/19/11 - CR611019 - Added missing IOPATH RXUSRCLK_RXCHBONDO
// 06/02/11 - CR612815 - Add missing setuphold RXUSRCLK_RXCHBONDI
// 07/08/11 - CR616301 - Remove assign on RXUSRCLK for simprim
// 09/16/11 - CR624064 - YML update
// 01/18/13 - 695630 - added drp monitor
/////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTXE2_CHANNEL (
CPLLFBCLKLOST,
CPLLLOCK,
CPLLREFCLKLOST,
DMONITOROUT,
DRPDO,
DRPRDY,
EYESCANDATAERROR,
GTREFCLKMONITOR,
GTXTXN,
GTXTXP,
PCSRSVDOUT,
PHYSTATUS,
RXBUFSTATUS,
RXBYTEISALIGNED,
RXBYTEREALIGN,
RXCDRLOCK,
RXCHANBONDSEQ,
RXCHANISALIGNED,
RXCHANREALIGN,
RXCHARISCOMMA,
RXCHARISK,
RXCHBONDO,
RXCLKCORCNT,
RXCOMINITDET,
RXCOMMADET,
RXCOMSASDET,
RXCOMWAKEDET,
RXDATA,
RXDATAVALID,
RXDISPERR,
RXDLYSRESETDONE,
RXELECIDLE,
RXHEADER,
RXHEADERVALID,
RXMONITOROUT,
RXNOTINTABLE,
RXOUTCLK,
RXOUTCLKFABRIC,
RXOUTCLKPCS,
RXPHALIGNDONE,
RXPHMONITOR,
RXPHSLIPMONITOR,
RXPRBSERR,
RXQPISENN,
RXQPISENP,
RXRATEDONE,
RXRESETDONE,
RXSTARTOFSEQ,
RXSTATUS,
RXVALID,
TSTOUT,
TXBUFSTATUS,
TXCOMFINISH,
TXDLYSRESETDONE,
TXGEARBOXREADY,
TXOUTCLK,
TXOUTCLKFABRIC,
TXOUTCLKPCS,
TXPHALIGNDONE,
TXPHINITDONE,
TXQPISENN,
TXQPISENP,
TXRATEDONE,
TXRESETDONE,
CFGRESET,
CLKRSVD,
CPLLLOCKDETCLK,
CPLLLOCKEN,
CPLLPD,
CPLLREFCLKSEL,
CPLLRESET,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
EYESCANMODE,
EYESCANRESET,
EYESCANTRIGGER,
GTGREFCLK,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTRESETSEL,
GTRSVD,
GTRXRESET,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
GTTXRESET,
GTXRXN,
GTXRXP,
LOOPBACK,
PCSRSVDIN,
PCSRSVDIN2,
PMARSVDIN,
PMARSVDIN2,
QPLLCLK,
QPLLREFCLK,
RESETOVRD,
RX8B10BEN,
RXBUFRESET,
RXCDRFREQRESET,
RXCDRHOLD,
RXCDROVRDEN,
RXCDRRESET,
RXCDRRESETRSV,
RXCHBONDEN,
RXCHBONDI,
RXCHBONDLEVEL,
RXCHBONDMASTER,
RXCHBONDSLAVE,
RXCOMMADETEN,
RXDDIEN,
RXDFEAGCHOLD,
RXDFEAGCOVRDEN,
RXDFECM1EN,
RXDFELFHOLD,
RXDFELFOVRDEN,
RXDFELPMRESET,
RXDFETAP2HOLD,
RXDFETAP2OVRDEN,
RXDFETAP3HOLD,
RXDFETAP3OVRDEN,
RXDFETAP4HOLD,
RXDFETAP4OVRDEN,
RXDFETAP5HOLD,
RXDFETAP5OVRDEN,
RXDFEUTHOLD,
RXDFEUTOVRDEN,
RXDFEVPHOLD,
RXDFEVPOVRDEN,
RXDFEVSEN,
RXDFEXYDEN,
RXDFEXYDHOLD,
RXDFEXYDOVRDEN,
RXDLYBYPASS,
RXDLYEN,
RXDLYOVRDEN,
RXDLYSRESET,
RXELECIDLEMODE,
RXGEARBOXSLIP,
RXLPMEN,
RXLPMHFHOLD,
RXLPMHFOVRDEN,
RXLPMLFHOLD,
RXLPMLFKLOVRDEN,
RXMCOMMAALIGNEN,
RXMONITORSEL,
RXOOBRESET,
RXOSHOLD,
RXOSOVRDEN,
RXOUTCLKSEL,
RXPCOMMAALIGNEN,
RXPCSRESET,
RXPD,
RXPHALIGN,
RXPHALIGNEN,
RXPHDLYPD,
RXPHDLYRESET,
RXPHOVRDEN,
RXPMARESET,
RXPOLARITY,
RXPRBSCNTRESET,
RXPRBSSEL,
RXQPIEN,
RXRATE,
RXSLIDE,
RXSYSCLKSEL,
RXUSERRDY,
RXUSRCLK,
RXUSRCLK2,
SETERRSTATUS,
TSTIN,
TX8B10BBYPASS,
TX8B10BEN,
TXBUFDIFFCTRL,
TXCHARDISPMODE,
TXCHARDISPVAL,
TXCHARISK,
TXCOMINIT,
TXCOMSAS,
TXCOMWAKE,
TXDATA,
TXDEEMPH,
TXDETECTRX,
TXDIFFCTRL,
TXDIFFPD,
TXDLYBYPASS,
TXDLYEN,
TXDLYHOLD,
TXDLYOVRDEN,
TXDLYSRESET,
TXDLYUPDOWN,
TXELECIDLE,
TXHEADER,
TXINHIBIT,
TXMAINCURSOR,
TXMARGIN,
TXOUTCLKSEL,
TXPCSRESET,
TXPD,
TXPDELECIDLEMODE,
TXPHALIGN,
TXPHALIGNEN,
TXPHDLYPD,
TXPHDLYRESET,
TXPHDLYTSTCLK,
TXPHINIT,
TXPHOVRDEN,
TXPISOPD,
TXPMARESET,
TXPOLARITY,
TXPOSTCURSOR,
TXPOSTCURSORINV,
TXPRBSFORCEERR,
TXPRBSSEL,
TXPRECURSOR,
TXPRECURSORINV,
TXQPIBIASEN,
TXQPISTRONGPDOWN,
TXQPIWEAKPUP,
TXRATE,
TXSEQUENCE,
TXSTARTSEQ,
TXSWING,
TXSYSCLKSEL,
TXUSERRDY,
TXUSRCLK,
TXUSRCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter integer ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter integer CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 20;
parameter integer CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter integer CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter [23:0] CPLL_CFG = 24'hB007D8;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
parameter integer CPLL_REFCLK_DIV = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [31:0] PMA_RSV = 32'h00000000;
parameter [15:0] PMA_RSV2 = 16'h2050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [31:0] PMA_RSV4 = 32'h00000000;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter integer RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter integer RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b010101;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
parameter [15:0] RXDLY_CFG = 16'h001F;
parameter [8:0] RXDLY_LCFG = 9'h030;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000;
parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084020;
parameter [23:0] RXPH_CFG = 24'h000000;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter integer RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [11:0] RX_BIAS_CFG = 12'b000000000000;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_PD = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [2:0] RX_CM_TRIM = 3'b100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [11:0] RX_DEBUG_CFG = 12'b000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F;
parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000;
parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000;
parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000;
parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000;
parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000;
parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A;
parameter [15:0] RX_DFE_LPM_CFG = 16'h0904;
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000;
parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000;
parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000;
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter integer RX_INT_DATAWIDTH = 0;
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter integer SAS_MAX_COM = 64;
parameter integer SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter integer SATA_MAX_BURST = 8;
parameter integer SATA_MAX_INIT = 21;
parameter integer SATA_MAX_WAKE = 7;
parameter integer SATA_MIN_BURST = 4;
parameter integer SATA_MIN_INIT = 12;
parameter integer SATA_MIN_WAKE = 4;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "4.0";
parameter [4:0] TERM_RCAL_CFG = 5'b10000;
parameter [0:0] TERM_RCAL_OVRD = 1'b0;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h001F;
parameter [8:0] TXDLY_LCFG = 9'h030;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084020;
parameter [15:0] TXPH_CFG = 16'h0780;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_PD = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [4:0] TX_DEEMPH0 = 5'b00000;
parameter [4:0] TX_DEEMPH1 = 5'b00000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter integer TX_INT_DATAWIDTH = 0;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CPLLFBCLKLOST;
output CPLLLOCK;
output CPLLREFCLKLOST;
output DRPRDY;
output EYESCANDATAERROR;
output GTREFCLKMONITOR;
output GTXTXN;
output GTXTXP;
output PHYSTATUS;
output RXBYTEISALIGNED;
output RXBYTEREALIGN;
output RXCDRLOCK;
output RXCHANBONDSEQ;
output RXCHANISALIGNED;
output RXCHANREALIGN;
output RXCOMINITDET;
output RXCOMMADET;
output RXCOMSASDET;
output RXCOMWAKEDET;
output RXDATAVALID;
output RXDLYSRESETDONE;
output RXELECIDLE;
output RXHEADERVALID;
output RXOUTCLK;
output RXOUTCLKFABRIC;
output RXOUTCLKPCS;
output RXPHALIGNDONE;
output RXPRBSERR;
output RXQPISENN;
output RXQPISENP;
output RXRATEDONE;
output RXRESETDONE;
output RXSTARTOFSEQ;
output RXVALID;
output TXCOMFINISH;
output TXDLYSRESETDONE;
output TXGEARBOXREADY;
output TXOUTCLK;
output TXOUTCLKFABRIC;
output TXOUTCLKPCS;
output TXPHALIGNDONE;
output TXPHINITDONE;
output TXQPISENN;
output TXQPISENP;
output TXRATEDONE;
output TXRESETDONE;
output [15:0] DRPDO;
output [15:0] PCSRSVDOUT;
output [1:0] RXCLKCORCNT;
output [1:0] TXBUFSTATUS;
output [2:0] RXBUFSTATUS;
output [2:0] RXHEADER;
output [2:0] RXSTATUS;
output [4:0] RXCHBONDO;
output [4:0] RXPHMONITOR;
output [4:0] RXPHSLIPMONITOR;
output [63:0] RXDATA;
output [6:0] RXMONITOROUT;
output [7:0] DMONITOROUT;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [7:0] RXDISPERR;
output [7:0] RXNOTINTABLE;
output [9:0] TSTOUT;
input CFGRESET;
input CPLLLOCKDETCLK;
input CPLLLOCKEN;
input CPLLPD;
input CPLLRESET;
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTRESETSEL;
input GTRXRESET;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input GTTXRESET;
input GTXRXN;
input GTXRXP;
input QPLLCLK;
input QPLLREFCLK;
input RESETOVRD;
input RX8B10BEN;
input RXBUFRESET;
input RXCDRFREQRESET;
input RXCDRHOLD;
input RXCDROVRDEN;
input RXCDRRESET;
input RXCDRRESETRSV;
input RXCHBONDEN;
input RXCHBONDMASTER;
input RXCHBONDSLAVE;
input RXCOMMADETEN;
input RXDDIEN;
input RXDFEAGCHOLD;
input RXDFEAGCOVRDEN;
input RXDFECM1EN;
input RXDFELFHOLD;
input RXDFELFOVRDEN;
input RXDFELPMRESET;
input RXDFETAP2HOLD;
input RXDFETAP2OVRDEN;
input RXDFETAP3HOLD;
input RXDFETAP3OVRDEN;
input RXDFETAP4HOLD;
input RXDFETAP4OVRDEN;
input RXDFETAP5HOLD;
input RXDFETAP5OVRDEN;
input RXDFEUTHOLD;
input RXDFEUTOVRDEN;
input RXDFEVPHOLD;
input RXDFEVPOVRDEN;
input RXDFEVSEN;
input RXDFEXYDEN;
input RXDFEXYDHOLD;
input RXDFEXYDOVRDEN;
input RXDLYBYPASS;
input RXDLYEN;
input RXDLYOVRDEN;
input RXDLYSRESET;
input RXGEARBOXSLIP;
input RXLPMEN;
input RXLPMHFHOLD;
input RXLPMHFOVRDEN;
input RXLPMLFHOLD;
input RXLPMLFKLOVRDEN;
input RXMCOMMAALIGNEN;
input RXOOBRESET;
input RXOSHOLD;
input RXOSOVRDEN;
input RXPCOMMAALIGNEN;
input RXPCSRESET;
input RXPHALIGN;
input RXPHALIGNEN;
input RXPHDLYPD;
input RXPHDLYRESET;
input RXPHOVRDEN;
input RXPMARESET;
input RXPOLARITY;
input RXPRBSCNTRESET;
input RXQPIEN;
input RXSLIDE;
input RXUSERRDY;
input RXUSRCLK2;
input RXUSRCLK;
input SETERRSTATUS;
input TX8B10BEN;
input TXCOMINIT;
input TXCOMSAS;
input TXCOMWAKE;
input TXDEEMPH;
input TXDETECTRX;
input TXDIFFPD;
input TXDLYBYPASS;
input TXDLYEN;
input TXDLYHOLD;
input TXDLYOVRDEN;
input TXDLYSRESET;
input TXDLYUPDOWN;
input TXELECIDLE;
input TXINHIBIT;
input TXPCSRESET;
input TXPDELECIDLEMODE;
input TXPHALIGN;
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
input TXPISOPD;
input TXPMARESET;
input TXPOLARITY;
input TXPOSTCURSORINV;
input TXPRBSFORCEERR;
input TXPRECURSORINV;
input TXQPIBIASEN;
input TXQPISTRONGPDOWN;
input TXQPIWEAKPUP;
input TXSTARTSEQ;
input TXSWING;
input TXUSERRDY;
input TXUSRCLK2;
input TXUSRCLK;
input [15:0] DRPDI;
input [15:0] GTRSVD;
input [15:0] PCSRSVDIN;
input [19:0] TSTIN;
input [1:0] RXELECIDLEMODE;
input [1:0] RXMONITORSEL;
input [1:0] RXPD;
input [1:0] RXSYSCLKSEL;
input [1:0] TXPD;
input [1:0] TXSYSCLKSEL;
input [2:0] CPLLREFCLKSEL;
input [2:0] LOOPBACK;
input [2:0] RXCHBONDLEVEL;
input [2:0] RXOUTCLKSEL;
input [2:0] RXPRBSSEL;
input [2:0] RXRATE;
input [2:0] TXBUFDIFFCTRL;
input [2:0] TXHEADER;
input [2:0] TXMARGIN;
input [2:0] TXOUTCLKSEL;
input [2:0] TXPRBSSEL;
input [2:0] TXRATE;
input [3:0] CLKRSVD;
input [3:0] TXDIFFCTRL;
input [4:0] PCSRSVDIN2;
input [4:0] PMARSVDIN2;
input [4:0] PMARSVDIN;
input [4:0] RXCHBONDI;
input [4:0] TXPOSTCURSOR;
input [4:0] TXPRECURSOR;
input [63:0] TXDATA;
input [6:0] TXMAINCURSOR;
input [6:0] TXSEQUENCE;
input [7:0] TX8B10BBYPASS;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [8:0] DRPADDR;
reg SIM_RECEIVER_DETECT_PASS_BINARY;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] ALIGN_COMMA_DOUBLE_BINARY;
reg [0:0] ALIGN_MCOMMA_DET_BINARY;
reg [0:0] ALIGN_PCOMMA_DET_BINARY;
reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY;
reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY;
reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY;
reg [0:0] CLK_CORRECT_USE_BINARY;
reg [0:0] CLK_COR_KEEP_IDLE_BINARY;
reg [0:0] CLK_COR_PRECEDENCE_BINARY;
reg [0:0] CLK_COR_SEQ_2_USE_BINARY;
reg [0:0] CPLL_FBDIV_45_BINARY;
reg [0:0] DEC_MCOMMA_DETECT_BINARY;
reg [0:0] DEC_PCOMMA_DETECT_BINARY;
reg [0:0] DEC_VALID_COMMA_ONLY_BINARY;
reg [0:0] ES_ERRDET_EN_BINARY;
reg [0:0] ES_EYE_SCAN_EN_BINARY;
reg [0:0] FTS_LANE_DESKEW_EN_BINARY;
reg [0:0] PCS_PCIE_EN_BINARY;
reg [0:0] RXBUF_ADDR_MODE_BINARY;
reg [0:0] RXBUF_EN_BINARY;
reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY;
reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY;
reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY;
reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] RXBUF_THRESH_OVRD_BINARY;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY;
reg [0:0] RXGEARBOX_EN_BINARY;
reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY;
reg [0:0] RX_CLKMUX_PD_BINARY;
reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY;
reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY;
reg [0:0] RX_INT_DATAWIDTH_BINARY;
reg [0:0] RX_XCLK_SEL_BINARY;
reg [0:0] SHOW_REALIGN_COMMA_BINARY;
reg [0:0] TERM_RCAL_OVRD_BINARY;
reg [0:0] TXBUF_EN_BINARY;
reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] TXGEARBOX_EN_BINARY;
reg [0:0] TX_CLKMUX_PD_BINARY;
reg [0:0] TX_INT_DATAWIDTH_BINARY;
reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY;
reg [0:0] TX_MAINCURSOR_SEL_BINARY;
reg [0:0] TX_PREDRIVER_MODE_BINARY;
reg [0:0] TX_QPI_STATUS_EN_BINARY;
reg [0:0] TX_XCLK_SEL_BINARY;
reg [0:0] UCODEER_CLR_BINARY;
reg [10:0] RX_DFE_H4_CFG_BINARY;
reg [10:0] RX_DFE_H5_CFG_BINARY;
reg [11:0] RX_BIAS_CFG_BINARY;
reg [11:0] RX_DEBUG_CFG_BINARY;
reg [11:0] RX_DFE_H2_CFG_BINARY;
reg [11:0] RX_DFE_H3_CFG_BINARY;
reg [12:0] RX_DFE_KL_CFG_BINARY;
reg [12:0] RX_DFE_XYD_CFG_BINARY;
reg [12:0] RX_OS_CFG_BINARY;
reg [13:0] RXLPM_HF_CFG_BINARY;
reg [13:0] RXLPM_LF_CFG_BINARY;
reg [16:0] RX_DFE_UT_CFG_BINARY;
reg [16:0] RX_DFE_VP_CFG_BINARY;
reg [1:0] CHAN_BOND_SEQ_LEN_BINARY;
reg [1:0] CLK_COR_SEQ_LEN_BINARY;
reg [1:0] OUTREFCLK_SEL_INV_BINARY;
reg [1:0] PMA_RSV3_BINARY;
reg [1:0] RXSLIDE_MODE_BINARY;
reg [1:0] RX_CM_SEL_BINARY;
reg [1:0] SATA_CPLL_CFG_BINARY;
reg [2:0] ALIGN_COMMA_WORD_BINARY;
reg [2:0] GEARBOX_MODE_BINARY;
reg [2:0] RXOUT_DIV_BINARY;
reg [2:0] RX_CM_TRIM_BINARY;
reg [2:0] RX_DATA_WIDTH_BINARY;
reg [2:0] SATA_BURST_VAL_BINARY;
reg [2:0] SATA_EIDLE_VAL_BINARY;
reg [2:0] SIM_CPLLREFCLK_SEL_BINARY;
reg [2:0] TXOUT_DIV_BINARY;
reg [2:0] TX_DATA_WIDTH_BINARY;
reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY;
reg [2:0] TX_RXDETECT_REF_BINARY;
reg [3:0] CHAN_BOND_MAX_SKEW_BINARY;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY;
reg [3:0] FTS_LANE_DESKEW_CFG_BINARY;
reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY;
reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY;
reg [3:0] RXSLIDE_AUTO_WAIT_BINARY;
reg [3:0] SATA_BURST_SEQ_LEN_BINARY;
reg [4:0] CLK_COR_REPEAT_WAIT_BINARY;
reg [4:0] CPLL_REFCLK_DIV_BINARY;
reg [4:0] ES_PRESCALE_BINARY;
reg [4:0] RXBUFRESET_TIME_BINARY;
reg [4:0] RXCDRFREQRESET_TIME_BINARY;
reg [4:0] RXCDRPHRESET_TIME_BINARY;
reg [4:0] RXISCANRESET_TIME_BINARY;
reg [4:0] RXPCSRESET_TIME_BINARY;
reg [4:0] RXPH_MONITOR_SEL_BINARY;
reg [4:0] RXPMARESET_TIME_BINARY;
reg [4:0] RX_CLK25_DIV_BINARY;
reg [4:0] RX_SIG_VALID_DLY_BINARY;
reg [4:0] TERM_RCAL_CFG_BINARY;
reg [4:0] TXPCSRESET_TIME_BINARY;
reg [4:0] TXPH_MONITOR_SEL_BINARY;
reg [4:0] TXPMARESET_TIME_BINARY;
reg [4:0] TX_CLK25_DIV_BINARY;
reg [4:0] TX_DEEMPH0_BINARY;
reg [4:0] TX_DEEMPH1_BINARY;
reg [4:0] TX_DRIVE_MODE_BINARY;
reg [5:0] CLK_COR_MAX_LAT_BINARY;
reg [5:0] CLK_COR_MIN_LAT_BINARY;
reg [5:0] ES_CONTROL_BINARY;
reg [5:0] RXBUF_THRESH_OVFLW_BINARY;
reg [5:0] RXBUF_THRESH_UNDFLW_BINARY;
reg [5:0] RXCDR_LOCK_CFG_BINARY;
reg [5:0] RX_BUFFER_CFG_BINARY;
reg [5:0] RX_DDI_SEL_BINARY;
reg [5:0] SAS_MIN_COM_BINARY;
reg [5:0] SATA_MAX_BURST_BINARY;
reg [5:0] SATA_MAX_INIT_BINARY;
reg [5:0] SATA_MAX_WAKE_BINARY;
reg [5:0] SATA_MIN_BURST_BINARY;
reg [5:0] SATA_MIN_INIT_BINARY;
reg [5:0] SATA_MIN_WAKE_BINARY;
reg [6:0] CPLL_FBDIV_BINARY;
reg [6:0] RXDFELPMRESET_TIME_BINARY;
reg [6:0] RXOOB_CFG_BINARY;
reg [6:0] SAS_MAX_COM_BINARY;
reg [6:0] TX_MARGIN_FULL_0_BINARY;
reg [6:0] TX_MARGIN_FULL_1_BINARY;
reg [6:0] TX_MARGIN_FULL_2_BINARY;
reg [6:0] TX_MARGIN_FULL_3_BINARY;
reg [6:0] TX_MARGIN_FULL_4_BINARY;
reg [6:0] TX_MARGIN_LOW_0_BINARY;
reg [6:0] TX_MARGIN_LOW_1_BINARY;
reg [6:0] TX_MARGIN_LOW_2_BINARY;
reg [6:0] TX_MARGIN_LOW_3_BINARY;
reg [6:0] TX_MARGIN_LOW_4_BINARY;
reg [8:0] ES_VERT_OFFSET_BINARY;
reg [9:0] ALIGN_COMMA_ENABLE_BINARY;
reg [9:0] ALIGN_MCOMMA_VALUE_BINARY;
reg [9:0] ALIGN_PCOMMA_VALUE_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_4_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_4_BINARY;
reg [9:0] CLK_COR_SEQ_1_1_BINARY;
reg [9:0] CLK_COR_SEQ_1_2_BINARY;
reg [9:0] CLK_COR_SEQ_1_3_BINARY;
reg [9:0] CLK_COR_SEQ_1_4_BINARY;
reg [9:0] CLK_COR_SEQ_2_1_BINARY;
reg [9:0] CLK_COR_SEQ_2_2_BINARY;
reg [9:0] CLK_COR_SEQ_2_3_BINARY;
reg [9:0] CLK_COR_SEQ_2_4_BINARY;
reg [9:0] ES_PMA_CFG_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (ALIGN_COMMA_DOUBLE)
"FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0;
"TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE);
$finish;
end
endcase
case (ALIGN_COMMA_WORD)
1 : ALIGN_COMMA_WORD_BINARY = 3'b001;
2 : ALIGN_COMMA_WORD_BINARY = 3'b010;
4 : ALIGN_COMMA_WORD_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", ALIGN_COMMA_WORD, 1);
$finish;
end
endcase
case (ALIGN_MCOMMA_DET)
"TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET);
$finish;
end
endcase
case (ALIGN_PCOMMA_DET)
"TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET);
$finish;
end
endcase
case (CBCC_DATA_SOURCE_SEL)
"DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1;
"ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL);
$finish;
end
endcase
case (CHAN_BOND_KEEP_ALIGN)
"FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0;
"TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN);
$finish;
end
endcase
case (CHAN_BOND_SEQ_2_USE)
"FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE);
$finish;
end
endcase
case (CHAN_BOND_SEQ_LEN)
1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00;
2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01;
3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10;
4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1);
$finish;
end
endcase
case (CLK_CORRECT_USE)
"TRUE" : CLK_CORRECT_USE_BINARY = 1'b1;
"FALSE" : CLK_CORRECT_USE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE);
$finish;
end
endcase
case (CLK_COR_KEEP_IDLE)
"FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0;
"TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE);
$finish;
end
endcase
case (CLK_COR_PRECEDENCE)
"TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1;
"FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE);
$finish;
end
endcase
case (CLK_COR_SEQ_2_USE)
"FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE);
$finish;
end
endcase
case (CLK_COR_SEQ_LEN)
1 : CLK_COR_SEQ_LEN_BINARY = 2'b00;
2 : CLK_COR_SEQ_LEN_BINARY = 2'b01;
3 : CLK_COR_SEQ_LEN_BINARY = 2'b10;
4 : CLK_COR_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1);
$finish;
end
endcase
case (CPLL_FBDIV)
4 : CPLL_FBDIV_BINARY = 7'b0000010;
1 : CPLL_FBDIV_BINARY = 7'b0010000;
2 : CPLL_FBDIV_BINARY = 7'b0000000;
3 : CPLL_FBDIV_BINARY = 7'b0000001;
5 : CPLL_FBDIV_BINARY = 7'b0000011;
6 : CPLL_FBDIV_BINARY = 7'b0000101;
8 : CPLL_FBDIV_BINARY = 7'b0000110;
10 : CPLL_FBDIV_BINARY = 7'b0000111;
12 : CPLL_FBDIV_BINARY = 7'b0001101;
16 : CPLL_FBDIV_BINARY = 7'b0001110;
20 : CPLL_FBDIV_BINARY = 7'b0001111;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_FBDIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_FBDIV, 4);
$finish;
end
endcase
case (CPLL_FBDIV_45)
5 : CPLL_FBDIV_45_BINARY = 1'b1;
4 : CPLL_FBDIV_45_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_FBDIV_45 on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 4 to 5.", CPLL_FBDIV_45, 5);
$finish;
end
endcase
case (CPLL_REFCLK_DIV)
1 : CPLL_REFCLK_DIV_BINARY = 5'b10000;
2 : CPLL_REFCLK_DIV_BINARY = 5'b00000;
3 : CPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : CPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : CPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : CPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : CPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : CPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : CPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : CPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : CPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute CPLL_REFCLK_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 20.", CPLL_REFCLK_DIV, 1);
$finish;
end
endcase
case (DEC_MCOMMA_DETECT)
"TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT);
$finish;
end
endcase
case (DEC_PCOMMA_DETECT)
"TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT);
$finish;
end
endcase
case (DEC_VALID_COMMA_ONLY)
"TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1;
"FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY);
$finish;
end
endcase
case (ES_ERRDET_EN)
"FALSE" : ES_ERRDET_EN_BINARY = 1'b0;
"TRUE" : ES_ERRDET_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN);
$finish;
end
endcase
case (ES_EYE_SCAN_EN)
"FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0;
"TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN);
$finish;
end
endcase
case (FTS_LANE_DESKEW_EN)
"FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0;
"TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN);
$finish;
end
endcase
case (PCS_PCIE_EN)
"FALSE" : PCS_PCIE_EN_BINARY = 1'b0;
"TRUE" : PCS_PCIE_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN);
$finish;
end
endcase
case (RXBUF_ADDR_MODE)
"FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0;
"FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE);
$finish;
end
endcase
case (RXBUF_EN)
"TRUE" : RXBUF_EN_BINARY = 1'b1;
"FALSE" : RXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN);
$finish;
end
endcase
case (RXBUF_RESET_ON_CB_CHANGE)
"TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE);
$finish;
end
endcase
case (RXBUF_RESET_ON_COMMAALIGN)
"FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN);
$finish;
end
endcase
case (RXBUF_RESET_ON_EIDLE)
"FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE);
$finish;
end
endcase
case (RXBUF_RESET_ON_RATE_CHANGE)
"TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (RXBUF_THRESH_OVRD)
"FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0;
"TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD);
$finish;
end
endcase
case (RXGEARBOX_EN)
"FALSE" : RXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : RXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN);
$finish;
end
endcase
case (RXOUT_DIV)
2 : RXOUT_DIV_BINARY = 3'b001;
1 : RXOUT_DIV_BINARY = 3'b000;
4 : RXOUT_DIV_BINARY = 3'b010;
8 : RXOUT_DIV_BINARY = 3'b011;
16 : RXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute RXOUT_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2);
$finish;
end
endcase
case (RXSLIDE_MODE)
"OFF" : RXSLIDE_MODE_BINARY = 2'b00;
"AUTO" : RXSLIDE_MODE_BINARY = 2'b01;
"PCS" : RXSLIDE_MODE_BINARY = 2'b10;
"PMA" : RXSLIDE_MODE_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE);
$finish;
end
endcase
case (RX_CLK25_DIV)
7 : RX_CLK25_DIV_BINARY = 5'b00110;
1 : RX_CLK25_DIV_BINARY = 5'b00000;
2 : RX_CLK25_DIV_BINARY = 5'b00001;
3 : RX_CLK25_DIV_BINARY = 5'b00010;
4 : RX_CLK25_DIV_BINARY = 5'b00011;
5 : RX_CLK25_DIV_BINARY = 5'b00100;
6 : RX_CLK25_DIV_BINARY = 5'b00101;
8 : RX_CLK25_DIV_BINARY = 5'b00111;
9 : RX_CLK25_DIV_BINARY = 5'b01000;
10 : RX_CLK25_DIV_BINARY = 5'b01001;
11 : RX_CLK25_DIV_BINARY = 5'b01010;
12 : RX_CLK25_DIV_BINARY = 5'b01011;
13 : RX_CLK25_DIV_BINARY = 5'b01100;
14 : RX_CLK25_DIV_BINARY = 5'b01101;
15 : RX_CLK25_DIV_BINARY = 5'b01110;
16 : RX_CLK25_DIV_BINARY = 5'b01111;
17 : RX_CLK25_DIV_BINARY = 5'b10000;
18 : RX_CLK25_DIV_BINARY = 5'b10001;
19 : RX_CLK25_DIV_BINARY = 5'b10010;
20 : RX_CLK25_DIV_BINARY = 5'b10011;
21 : RX_CLK25_DIV_BINARY = 5'b10100;
22 : RX_CLK25_DIV_BINARY = 5'b10101;
23 : RX_CLK25_DIV_BINARY = 5'b10110;
24 : RX_CLK25_DIV_BINARY = 5'b10111;
25 : RX_CLK25_DIV_BINARY = 5'b11000;
26 : RX_CLK25_DIV_BINARY = 5'b11001;
27 : RX_CLK25_DIV_BINARY = 5'b11010;
28 : RX_CLK25_DIV_BINARY = 5'b11011;
29 : RX_CLK25_DIV_BINARY = 5'b11100;
30 : RX_CLK25_DIV_BINARY = 5'b11101;
31 : RX_CLK25_DIV_BINARY = 5'b11110;
32 : RX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7);
$finish;
end
endcase
case (RX_DATA_WIDTH)
20 : RX_DATA_WIDTH_BINARY = 3'b011;
16 : RX_DATA_WIDTH_BINARY = 3'b010;
32 : RX_DATA_WIDTH_BINARY = 3'b100;
40 : RX_DATA_WIDTH_BINARY = 3'b101;
64 : RX_DATA_WIDTH_BINARY = 3'b110;
80 : RX_DATA_WIDTH_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", RX_DATA_WIDTH, 20);
$finish;
end
endcase
case (RX_DEFER_RESET_BUF_EN)
"TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1;
"FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN);
$finish;
end
endcase
case (RX_DISPERR_SEQ_MATCH)
"TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1;
"FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH);
$finish;
end
endcase
case (RX_SIG_VALID_DLY)
10 : RX_SIG_VALID_DLY_BINARY = 5'b01001;
1 : RX_SIG_VALID_DLY_BINARY = 5'b00000;
2 : RX_SIG_VALID_DLY_BINARY = 5'b00001;
3 : RX_SIG_VALID_DLY_BINARY = 5'b00010;
4 : RX_SIG_VALID_DLY_BINARY = 5'b00011;
5 : RX_SIG_VALID_DLY_BINARY = 5'b00100;
6 : RX_SIG_VALID_DLY_BINARY = 5'b00101;
7 : RX_SIG_VALID_DLY_BINARY = 5'b00110;
8 : RX_SIG_VALID_DLY_BINARY = 5'b00111;
9 : RX_SIG_VALID_DLY_BINARY = 5'b01000;
11 : RX_SIG_VALID_DLY_BINARY = 5'b01010;
12 : RX_SIG_VALID_DLY_BINARY = 5'b01011;
13 : RX_SIG_VALID_DLY_BINARY = 5'b01100;
14 : RX_SIG_VALID_DLY_BINARY = 5'b01101;
15 : RX_SIG_VALID_DLY_BINARY = 5'b01110;
16 : RX_SIG_VALID_DLY_BINARY = 5'b01111;
17 : RX_SIG_VALID_DLY_BINARY = 5'b10000;
18 : RX_SIG_VALID_DLY_BINARY = 5'b10001;
19 : RX_SIG_VALID_DLY_BINARY = 5'b10010;
20 : RX_SIG_VALID_DLY_BINARY = 5'b10011;
21 : RX_SIG_VALID_DLY_BINARY = 5'b10100;
22 : RX_SIG_VALID_DLY_BINARY = 5'b10101;
23 : RX_SIG_VALID_DLY_BINARY = 5'b10110;
24 : RX_SIG_VALID_DLY_BINARY = 5'b10111;
25 : RX_SIG_VALID_DLY_BINARY = 5'b11000;
26 : RX_SIG_VALID_DLY_BINARY = 5'b11001;
27 : RX_SIG_VALID_DLY_BINARY = 5'b11010;
28 : RX_SIG_VALID_DLY_BINARY = 5'b11011;
29 : RX_SIG_VALID_DLY_BINARY = 5'b11100;
30 : RX_SIG_VALID_DLY_BINARY = 5'b11101;
31 : RX_SIG_VALID_DLY_BINARY = 5'b11110;
32 : RX_SIG_VALID_DLY_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10);
$finish;
end
endcase
case (RX_XCLK_SEL)
"RXREC" : RX_XCLK_SEL_BINARY = 1'b0;
"RXUSR" : RX_XCLK_SEL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL);
$finish;
end
endcase
case (SATA_CPLL_CFG)
"VCO_3000MHZ" : SATA_CPLL_CFG_BINARY = 2'b00;
"VCO_750MHZ" : SATA_CPLL_CFG_BINARY = 2'b10;
"VCO_1500MHZ" : SATA_CPLL_CFG_BINARY = 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute SATA_CPLL_CFG on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_CPLL_CFG);
$finish;
end
endcase
case (SHOW_REALIGN_COMMA)
"TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1;
"FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA);
$finish;
end
endcase
case (SIM_RECEIVER_DETECT_PASS)
"TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
"FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_TX_EIDLE_DRIVE_LEVEL)
"X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL);
$finish;
end
endcase
case (SIM_VERSION)
"4.0" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.1" : SIM_VERSION_BINARY = 0;
"5.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 4.0, 1.0, 1.1, 2.0, 3.0, 4.1, or 5.0.", SIM_VERSION);
$finish;
end
endcase
case (TXBUF_EN)
"TRUE" : TXBUF_EN_BINARY = 1'b1;
"FALSE" : TXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN);
$finish;
end
endcase
case (TXBUF_RESET_ON_RATE_CHANGE)
"FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
"TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE);
$finish;
end
endcase
case (TXGEARBOX_EN)
"FALSE" : TXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : TXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN);
$finish;
end
endcase
case (TXOUT_DIV)
2 : TXOUT_DIV_BINARY = 3'b001;
1 : TXOUT_DIV_BINARY = 3'b000;
4 : TXOUT_DIV_BINARY = 3'b010;
8 : TXOUT_DIV_BINARY = 3'b011;
16 : TXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute TXOUT_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2);
$finish;
end
endcase
case (TX_CLK25_DIV)
7 : TX_CLK25_DIV_BINARY = 5'b00110;
1 : TX_CLK25_DIV_BINARY = 5'b00000;
2 : TX_CLK25_DIV_BINARY = 5'b00001;
3 : TX_CLK25_DIV_BINARY = 5'b00010;
4 : TX_CLK25_DIV_BINARY = 5'b00011;
5 : TX_CLK25_DIV_BINARY = 5'b00100;
6 : TX_CLK25_DIV_BINARY = 5'b00101;
8 : TX_CLK25_DIV_BINARY = 5'b00111;
9 : TX_CLK25_DIV_BINARY = 5'b01000;
10 : TX_CLK25_DIV_BINARY = 5'b01001;
11 : TX_CLK25_DIV_BINARY = 5'b01010;
12 : TX_CLK25_DIV_BINARY = 5'b01011;
13 : TX_CLK25_DIV_BINARY = 5'b01100;
14 : TX_CLK25_DIV_BINARY = 5'b01101;
15 : TX_CLK25_DIV_BINARY = 5'b01110;
16 : TX_CLK25_DIV_BINARY = 5'b01111;
17 : TX_CLK25_DIV_BINARY = 5'b10000;
18 : TX_CLK25_DIV_BINARY = 5'b10001;
19 : TX_CLK25_DIV_BINARY = 5'b10010;
20 : TX_CLK25_DIV_BINARY = 5'b10011;
21 : TX_CLK25_DIV_BINARY = 5'b10100;
22 : TX_CLK25_DIV_BINARY = 5'b10101;
23 : TX_CLK25_DIV_BINARY = 5'b10110;
24 : TX_CLK25_DIV_BINARY = 5'b10111;
25 : TX_CLK25_DIV_BINARY = 5'b11000;
26 : TX_CLK25_DIV_BINARY = 5'b11001;
27 : TX_CLK25_DIV_BINARY = 5'b11010;
28 : TX_CLK25_DIV_BINARY = 5'b11011;
29 : TX_CLK25_DIV_BINARY = 5'b11100;
30 : TX_CLK25_DIV_BINARY = 5'b11101;
31 : TX_CLK25_DIV_BINARY = 5'b11110;
32 : TX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7);
$finish;
end
endcase
case (TX_DATA_WIDTH)
20 : TX_DATA_WIDTH_BINARY = 3'b011;
16 : TX_DATA_WIDTH_BINARY = 3'b010;
32 : TX_DATA_WIDTH_BINARY = 3'b100;
40 : TX_DATA_WIDTH_BINARY = 3'b101;
64 : TX_DATA_WIDTH_BINARY = 3'b110;
80 : TX_DATA_WIDTH_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 80.", TX_DATA_WIDTH, 20);
$finish;
end
endcase
case (TX_DRIVE_MODE)
"DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000;
"PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001;
"PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE);
$finish;
end
endcase
case (TX_LOOPBACK_DRIVE_HIZ)
"FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0;
"TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ);
$finish;
end
endcase
case (TX_XCLK_SEL)
"TXUSR" : TX_XCLK_SEL_BINARY = 1'b1;
"TXOUT" : TX_XCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on GTXE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL);
$finish;
end
endcase
if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111))
ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE);
$finish;
end
if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111))
ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE);
$finish;
end
if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111))
ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE);
$finish;
end
if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14))
CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW);
$finish;
end
if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111))
CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1);
$finish;
end
if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111))
CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2);
$finish;
end
if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111))
CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3);
$finish;
end
if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111))
CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4);
$finish;
end
if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE);
$finish;
end
if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111))
CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1);
$finish;
end
if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111))
CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2);
$finish;
end
if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111))
CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3);
$finish;
end
if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111))
CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4);
$finish;
end
if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE);
$finish;
end
if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60))
CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT);
$finish;
end
if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60))
CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT);
$finish;
end
if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31))
CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT);
$finish;
end
if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111))
CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1);
$finish;
end
if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111))
CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2);
$finish;
end
if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111))
CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3);
$finish;
end
if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111))
CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4);
$finish;
end
if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111))
CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE);
$finish;
end
if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111))
CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1);
$finish;
end
if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111))
CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2);
$finish;
end
if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111))
CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3);
$finish;
end
if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111))
CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4);
$finish;
end
if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111))
CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE);
$finish;
end
if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111))
ES_CONTROL_BINARY = ES_CONTROL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CONTROL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL);
$finish;
end
if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111))
ES_PMA_CFG_BINARY = ES_PMA_CFG;
else begin
$display("Attribute Syntax Error : The Attribute ES_PMA_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG);
$finish;
end
if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111))
ES_PRESCALE_BINARY = ES_PRESCALE;
else begin
$display("Attribute Syntax Error : The Attribute ES_PRESCALE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE);
$finish;
end
if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111))
ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET;
else begin
$display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET);
$finish;
end
if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111))
FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE);
$finish;
end
if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111))
FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG;
else begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG);
$finish;
end
if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111))
GEARBOX_MODE_BINARY = GEARBOX_MODE;
else begin
$display("Attribute Syntax Error : The Attribute GEARBOX_MODE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE);
$finish;
end
if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11))
OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV;
else begin
$display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV);
$finish;
end
if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11))
PMA_RSV3_BINARY = PMA_RSV3;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3);
$finish;
end
if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111))
RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME);
$finish;
end
if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111))
RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT);
$finish;
end
if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111))
RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT);
$finish;
end
if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63))
RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW);
$finish;
end
if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63))
RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW);
$finish;
end
if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111))
RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME);
$finish;
end
if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111))
RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME);
$finish;
end
if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1))
RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE);
$finish;
end
if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1))
RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE);
$finish;
end
if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111))
RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG);
$finish;
end
if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1))
RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE);
$finish;
end
if ((RXDFELPMRESET_TIME >= 7'b0000000) && (RXDFELPMRESET_TIME <= 7'b1111111))
RXDFELPMRESET_TIME_BINARY = RXDFELPMRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXDFELPMRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXDFELPMRESET_TIME);
$finish;
end
if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111))
RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME);
$finish;
end
if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111))
RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG);
$finish;
end
if ((RXLPM_LF_CFG >= 14'b00000000000000) && (RXLPM_LF_CFG <= 14'b11111111111111))
RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_LF_CFG);
$finish;
end
if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111))
RXOOB_CFG_BINARY = RXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXOOB_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG);
$finish;
end
if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111))
RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME);
$finish;
end
if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111))
RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL);
$finish;
end
if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111))
RXPMARESET_TIME_BINARY = RXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME);
$finish;
end
if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1))
RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK;
else begin
$display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK);
$finish;
end
if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15))
RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT);
$finish;
end
if ((RX_BIAS_CFG >= 12'b000000000000) && (RX_BIAS_CFG <= 12'b111111111111))
RX_BIAS_CFG_BINARY = RX_BIAS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_BIAS_CFG);
$finish;
end
if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111))
RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG);
$finish;
end
if ((RX_CLKMUX_PD >= 1'b0) && (RX_CLKMUX_PD <= 1'b1))
RX_CLKMUX_PD_BINARY = RX_CLKMUX_PD;
else begin
$display("Attribute Syntax Error : The Attribute RX_CLKMUX_PD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_PD);
$finish;
end
if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11))
RX_CM_SEL_BINARY = RX_CM_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL);
$finish;
end
if ((RX_CM_TRIM >= 3'b000) && (RX_CM_TRIM <= 3'b111))
RX_CM_TRIM_BINARY = RX_CM_TRIM;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_TRIM on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RX_CM_TRIM);
$finish;
end
if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111))
RX_DDI_SEL_BINARY = RX_DDI_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_DDI_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL);
$finish;
end
if ((RX_DEBUG_CFG >= 12'b000000000000) && (RX_DEBUG_CFG <= 12'b111111111111))
RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DEBUG_CFG);
$finish;
end
if ((RX_DFE_H2_CFG >= 12'b000000000000) && (RX_DFE_H2_CFG <= 12'b111111111111))
RX_DFE_H2_CFG_BINARY = RX_DFE_H2_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H2_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H2_CFG);
$finish;
end
if ((RX_DFE_H3_CFG >= 12'b000000000000) && (RX_DFE_H3_CFG <= 12'b111111111111))
RX_DFE_H3_CFG_BINARY = RX_DFE_H3_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H3_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 12'b000000000000 to 12'b111111111111.", RX_DFE_H3_CFG);
$finish;
end
if ((RX_DFE_H4_CFG >= 11'b00000000000) && (RX_DFE_H4_CFG <= 11'b11111111111))
RX_DFE_H4_CFG_BINARY = RX_DFE_H4_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H4_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H4_CFG);
$finish;
end
if ((RX_DFE_H5_CFG >= 11'b00000000000) && (RX_DFE_H5_CFG <= 11'b11111111111))
RX_DFE_H5_CFG_BINARY = RX_DFE_H5_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_H5_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", RX_DFE_H5_CFG);
$finish;
end
if ((RX_DFE_KL_CFG >= 13'b0000000000000) && (RX_DFE_KL_CFG <= 13'b1111111111111))
RX_DFE_KL_CFG_BINARY = RX_DFE_KL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_KL_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_DFE_KL_CFG);
$finish;
end
if ((RX_DFE_LPM_HOLD_DURING_EIDLE >= 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE <= 1'b1))
RX_DFE_LPM_HOLD_DURING_EIDLE_BINARY = RX_DFE_LPM_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_LPM_HOLD_DURING_EIDLE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_DFE_LPM_HOLD_DURING_EIDLE);
$finish;
end
if ((RX_DFE_UT_CFG >= 17'b00000000000000000) && (RX_DFE_UT_CFG <= 17'b11111111111111111))
RX_DFE_UT_CFG_BINARY = RX_DFE_UT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_UT_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_UT_CFG);
$finish;
end
if ((RX_DFE_VP_CFG >= 17'b00000000000000000) && (RX_DFE_VP_CFG <= 17'b11111111111111111))
RX_DFE_VP_CFG_BINARY = RX_DFE_VP_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_VP_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 17'b00000000000000000 to 17'b11111111111111111.", RX_DFE_VP_CFG);
$finish;
end
if ((RX_DFE_XYD_CFG >= 13'b0000000000000) && (RX_DFE_XYD_CFG <= 13'b1111111111111))
RX_DFE_XYD_CFG_BINARY = RX_DFE_XYD_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DFE_XYD_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_DFE_XYD_CFG);
$finish;
end
if ((RX_INT_DATAWIDTH >= 0) && (RX_INT_DATAWIDTH <= 1))
RX_INT_DATAWIDTH_BINARY = RX_INT_DATAWIDTH;
else begin
$display("Attribute Syntax Error : The Attribute RX_INT_DATAWIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", RX_INT_DATAWIDTH);
$finish;
end
if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111))
RX_OS_CFG_BINARY = RX_OS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_OS_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG);
$finish;
end
if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127))
SAS_MAX_COM_BINARY = SAS_MAX_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MAX_COM on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM);
$finish;
end
if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63))
SAS_MIN_COM_BINARY = SAS_MIN_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MIN_COM on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM);
$finish;
end
if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111))
SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN);
$finish;
end
if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111))
SATA_BURST_VAL_BINARY = SATA_BURST_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL);
$finish;
end
if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111))
SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL);
$finish;
end
if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63))
SATA_MAX_BURST_BINARY = SATA_MAX_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST);
$finish;
end
if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63))
SATA_MAX_INIT_BINARY = SATA_MAX_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT);
$finish;
end
if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63))
SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE);
$finish;
end
if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61))
SATA_MIN_BURST_BINARY = SATA_MIN_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST);
$finish;
end
if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63))
SATA_MIN_INIT_BINARY = SATA_MIN_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT);
$finish;
end
if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63))
SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE);
$finish;
end
if ((SIM_CPLLREFCLK_SEL >= 3'b0) && (SIM_CPLLREFCLK_SEL <= 3'b111))
SIM_CPLLREFCLK_SEL_BINARY = SIM_CPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_CPLLREFCLK_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_CPLLREFCLK_SEL);
$finish;
end
if ((TERM_RCAL_CFG >= 5'b00000) && (TERM_RCAL_CFG <= 5'b11111))
TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TERM_RCAL_CFG);
$finish;
end
if ((TERM_RCAL_OVRD >= 1'b0) && (TERM_RCAL_OVRD <= 1'b1))
TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TERM_RCAL_OVRD);
$finish;
end
if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111))
TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME);
$finish;
end
if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111))
TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL);
$finish;
end
if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111))
TXPMARESET_TIME_BINARY = TXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME);
$finish;
end
if ((TX_CLKMUX_PD >= 1'b0) && (TX_CLKMUX_PD <= 1'b1))
TX_CLKMUX_PD_BINARY = TX_CLKMUX_PD;
else begin
$display("Attribute Syntax Error : The Attribute TX_CLKMUX_PD on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_PD);
$finish;
end
if ((TX_DEEMPH0 >= 5'b00000) && (TX_DEEMPH0 <= 5'b11111))
TX_DEEMPH0_BINARY = TX_DEEMPH0;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TX_DEEMPH0);
$finish;
end
if ((TX_DEEMPH1 >= 5'b00000) && (TX_DEEMPH1 <= 5'b11111))
TX_DEEMPH1_BINARY = TX_DEEMPH1;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TX_DEEMPH1);
$finish;
end
if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111))
TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY);
$finish;
end
if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111))
TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY);
$finish;
end
if ((TX_INT_DATAWIDTH >= 0) && (TX_INT_DATAWIDTH <= 1))
TX_INT_DATAWIDTH_BINARY = TX_INT_DATAWIDTH;
else begin
$display("Attribute Syntax Error : The Attribute TX_INT_DATAWIDTH on GTXE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 1.", TX_INT_DATAWIDTH);
$finish;
end
if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1))
TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL);
$finish;
end
if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111))
TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0);
$finish;
end
if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111))
TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1);
$finish;
end
if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111))
TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2);
$finish;
end
if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111))
TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3);
$finish;
end
if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111))
TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4);
$finish;
end
if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111))
TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0);
$finish;
end
if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111))
TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1);
$finish;
end
if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111))
TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2);
$finish;
end
if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111))
TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3);
$finish;
end
if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111))
TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4);
$finish;
end
if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1))
TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE;
else begin
$display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE);
$finish;
end
if ((TX_QPI_STATUS_EN >= 1'b0) && (TX_QPI_STATUS_EN <= 1'b1))
TX_QPI_STATUS_EN_BINARY = TX_QPI_STATUS_EN;
else begin
$display("Attribute Syntax Error : The Attribute TX_QPI_STATUS_EN on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_QPI_STATUS_EN);
$finish;
end
if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111))
TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF;
else begin
$display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF);
$finish;
end
if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1))
UCODEER_CLR_BINARY = UCODEER_CLR;
else begin
$display("Attribute Syntax Error : The Attribute UCODEER_CLR on GTXE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR);
$finish;
end
end
wire [15:0] delay_DRPDO;
wire [15:0] delay_PCSRSVDOUT;
wire [1:0] delay_RXCLKCORCNT;
wire [1:0] delay_TXBUFSTATUS;
wire [2:0] delay_RXBUFSTATUS;
wire [2:0] delay_RXHEADER;
wire [2:0] delay_RXSTATUS;
wire [4:0] delay_RXCHBONDO;
wire [4:0] delay_RXPHMONITOR;
wire [4:0] delay_RXPHSLIPMONITOR;
wire [63:0] delay_RXDATA;
wire [6:0] delay_RXMONITOROUT;
wire [7:0] delay_DMONITOROUT;
wire [7:0] delay_RXCHARISCOMMA;
wire [7:0] delay_RXCHARISK;
wire [7:0] delay_RXDISPERR;
wire [7:0] delay_RXNOTINTABLE;
wire [9:0] delay_TSTOUT;
wire delay_CPLLFBCLKLOST;
wire delay_CPLLLOCK;
wire delay_CPLLREFCLKLOST;
wire delay_DRPRDY;
wire delay_EYESCANDATAERROR;
wire delay_GTREFCLKMONITOR;
wire delay_GTXTXN;
wire delay_GTXTXP;
wire delay_PHYSTATUS;
wire delay_RXBYTEISALIGNED;
wire delay_RXBYTEREALIGN;
wire delay_RXCDRLOCK;
wire delay_RXCHANBONDSEQ;
wire delay_RXCHANISALIGNED;
wire delay_RXCHANREALIGN;
wire delay_RXCOMINITDET;
wire delay_RXCOMMADET;
wire delay_RXCOMSASDET;
wire delay_RXCOMWAKEDET;
wire delay_RXDATAVALID;
wire delay_RXDLYSRESETDONE;
wire delay_RXELECIDLE;
wire delay_RXHEADERVALID;
wire delay_RXOUTCLK;
wire delay_RXOUTCLKFABRIC;
wire delay_RXOUTCLKPCS;
wire delay_RXPHALIGNDONE;
wire delay_RXPRBSERR;
wire delay_RXQPISENN;
wire delay_RXQPISENP;
wire delay_RXRATEDONE;
wire delay_RXRESETDONE;
wire delay_RXSTARTOFSEQ;
wire delay_RXVALID;
wire delay_TXCOMFINISH;
wire delay_TXDLYSRESETDONE;
wire delay_TXGEARBOXREADY;
wire delay_TXOUTCLK;
wire delay_TXOUTCLKFABRIC;
wire delay_TXOUTCLKPCS;
wire delay_TXPHALIGNDONE;
wire delay_TXPHINITDONE;
wire delay_TXQPISENN;
wire delay_TXQPISENP;
wire delay_TXRATEDONE;
wire delay_TXRESETDONE;
wire [15:0] delay_DRPDI;
wire [15:0] delay_GTRSVD;
wire [15:0] delay_PCSRSVDIN;
wire [19:0] delay_TSTIN;
wire [1:0] delay_RXELECIDLEMODE;
wire [1:0] delay_RXMONITORSEL;
wire [1:0] delay_RXPD;
wire [1:0] delay_RXSYSCLKSEL;
wire [1:0] delay_TXPD;
wire [1:0] delay_TXSYSCLKSEL;
wire [2:0] delay_CPLLREFCLKSEL;
wire [2:0] delay_LOOPBACK;
wire [2:0] delay_RXCHBONDLEVEL;
wire [2:0] delay_RXOUTCLKSEL;
wire [2:0] delay_RXPRBSSEL;
wire [2:0] delay_RXRATE;
wire [2:0] delay_TXBUFDIFFCTRL;
wire [2:0] delay_TXHEADER;
wire [2:0] delay_TXMARGIN;
wire [2:0] delay_TXOUTCLKSEL;
wire [2:0] delay_TXPRBSSEL;
wire [2:0] delay_TXRATE;
wire [3:0] delay_CLKRSVD;
wire [3:0] delay_TXDIFFCTRL;
wire [4:0] delay_PCSRSVDIN2;
wire [4:0] delay_PMARSVDIN2;
wire [4:0] delay_PMARSVDIN;
wire [4:0] delay_RXCHBONDI;
wire [4:0] delay_TXPOSTCURSOR;
wire [4:0] delay_TXPRECURSOR;
wire [63:0] delay_TXDATA;
wire [6:0] delay_TXMAINCURSOR;
wire [6:0] delay_TXSEQUENCE;
wire [7:0] delay_TX8B10BBYPASS;
wire [7:0] delay_TXCHARDISPMODE;
wire [7:0] delay_TXCHARDISPVAL;
wire [7:0] delay_TXCHARISK;
wire [8:0] delay_DRPADDR;
wire delay_CFGRESET;
wire delay_CPLLLOCKDETCLK;
wire delay_CPLLLOCKEN;
wire delay_CPLLPD;
wire delay_CPLLRESET;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_EYESCANMODE;
wire delay_EYESCANRESET;
wire delay_EYESCANTRIGGER;
wire delay_GTGREFCLK;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTRESETSEL;
wire delay_GTRXRESET;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_GTTXRESET;
wire delay_GTXRXN;
wire delay_GTXRXP;
wire delay_QPLLCLK;
wire delay_QPLLREFCLK;
wire delay_RESETOVRD;
wire delay_RX8B10BEN;
wire delay_RXBUFRESET;
wire delay_RXCDRFREQRESET;
wire delay_RXCDRHOLD;
wire delay_RXCDROVRDEN;
wire delay_RXCDRRESET;
wire delay_RXCDRRESETRSV;
wire delay_RXCHBONDEN;
wire delay_RXCHBONDMASTER;
wire delay_RXCHBONDSLAVE;
wire delay_RXCOMMADETEN;
wire delay_RXDDIEN;
wire delay_RXDFEAGCHOLD;
wire delay_RXDFEAGCOVRDEN;
wire delay_RXDFECM1EN;
wire delay_RXDFELFHOLD;
wire delay_RXDFELFOVRDEN;
wire delay_RXDFELPMRESET;
wire delay_RXDFETAP2HOLD;
wire delay_RXDFETAP2OVRDEN;
wire delay_RXDFETAP3HOLD;
wire delay_RXDFETAP3OVRDEN;
wire delay_RXDFETAP4HOLD;
wire delay_RXDFETAP4OVRDEN;
wire delay_RXDFETAP5HOLD;
wire delay_RXDFETAP5OVRDEN;
wire delay_RXDFEUTHOLD;
wire delay_RXDFEUTOVRDEN;
wire delay_RXDFEVPHOLD;
wire delay_RXDFEVPOVRDEN;
wire delay_RXDFEVSEN;
wire delay_RXDFEXYDEN;
wire delay_RXDFEXYDHOLD;
wire delay_RXDFEXYDOVRDEN;
wire delay_RXDLYBYPASS;
wire delay_RXDLYEN;
wire delay_RXDLYOVRDEN;
wire delay_RXDLYSRESET;
wire delay_RXGEARBOXSLIP;
wire delay_RXLPMEN;
wire delay_RXLPMHFHOLD;
wire delay_RXLPMHFOVRDEN;
wire delay_RXLPMLFHOLD;
wire delay_RXLPMLFKLOVRDEN;
wire delay_RXMCOMMAALIGNEN;
wire delay_RXOOBRESET;
wire delay_RXOSHOLD;
wire delay_RXOSOVRDEN;
wire delay_RXPCOMMAALIGNEN;
wire delay_RXPCSRESET;
wire delay_RXPHALIGN;
wire delay_RXPHALIGNEN;
wire delay_RXPHDLYPD;
wire delay_RXPHDLYRESET;
wire delay_RXPHOVRDEN;
wire delay_RXPMARESET;
wire delay_RXPOLARITY;
wire delay_RXPRBSCNTRESET;
wire delay_RXQPIEN;
wire delay_RXSLIDE;
wire delay_RXUSERRDY;
wire delay_RXUSRCLK2;
wire delay_RXUSRCLK;
wire delay_SETERRSTATUS;
wire delay_TX8B10BEN;
wire delay_TXCOMINIT;
wire delay_TXCOMSAS;
wire delay_TXCOMWAKE;
wire delay_TXDEEMPH;
wire delay_TXDETECTRX;
wire delay_TXDIFFPD;
wire delay_TXDLYBYPASS;
wire delay_TXDLYEN;
wire delay_TXDLYHOLD;
wire delay_TXDLYOVRDEN;
wire delay_TXDLYSRESET;
wire delay_TXDLYUPDOWN;
wire delay_TXELECIDLE;
wire delay_TXINHIBIT;
wire delay_TXPCSRESET;
wire delay_TXPDELECIDLEMODE;
wire delay_TXPHALIGN;
wire delay_TXPHALIGNEN;
wire delay_TXPHDLYPD;
wire delay_TXPHDLYRESET;
wire delay_TXPHDLYTSTCLK;
wire delay_TXPHINIT;
wire delay_TXPHOVRDEN;
wire delay_TXPISOPD;
wire delay_TXPMARESET;
wire delay_TXPOLARITY;
wire delay_TXPOSTCURSORINV;
wire delay_TXPRBSFORCEERR;
wire delay_TXPRECURSORINV;
wire delay_TXQPIBIASEN;
wire delay_TXQPISTRONGPDOWN;
wire delay_TXQPIWEAKPUP;
wire delay_TXSTARTSEQ;
wire delay_TXSWING;
wire delay_TXUSERRDY;
wire delay_TXUSRCLK2;
wire delay_TXUSRCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_CPLLLOCKDETCLK_INVERTED_REG = IS_CPLLLOCKDETCLK_INVERTED;
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED;
reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED;
reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED;
reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED;
reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED;
assign #(OUTCLK_DELAY) GTREFCLKMONITOR = delay_GTREFCLKMONITOR;
assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK;
assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK;
assign #(out_delay) CPLLFBCLKLOST = delay_CPLLFBCLKLOST;
assign #(out_delay) CPLLLOCK = delay_CPLLLOCK;
assign #(out_delay) CPLLREFCLKLOST = delay_CPLLREFCLKLOST;
assign #(out_delay) DMONITOROUT = delay_DMONITOROUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR;
assign #(out_delay) GTXTXN = delay_GTXTXN;
assign #(out_delay) GTXTXP = delay_GTXTXP;
assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT;
assign #(out_delay) PHYSTATUS = delay_PHYSTATUS;
assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS;
assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED;
assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN;
assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK;
assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ;
assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED;
assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN;
assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA;
assign #(out_delay) RXCHARISK = delay_RXCHARISK;
assign #(out_delay) RXCHBONDO = delay_RXCHBONDO;
assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT;
assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET;
assign #(out_delay) RXCOMMADET = delay_RXCOMMADET;
assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET;
assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET;
assign #(out_delay) RXDATAVALID = delay_RXDATAVALID;
assign #(out_delay) RXDATA = delay_RXDATA;
assign #(out_delay) RXDISPERR = delay_RXDISPERR;
assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE;
assign #(out_delay) RXELECIDLE = delay_RXELECIDLE;
assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID;
assign #(out_delay) RXHEADER = delay_RXHEADER;
assign #(out_delay) RXMONITOROUT = delay_RXMONITOROUT;
assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE;
assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC;
assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS;
assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE;
assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR;
assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR;
assign #(out_delay) RXPRBSERR = delay_RXPRBSERR;
assign #(out_delay) RXQPISENN = delay_RXQPISENN;
assign #(out_delay) RXQPISENP = delay_RXQPISENP;
assign #(out_delay) RXRATEDONE = delay_RXRATEDONE;
assign #(out_delay) RXRESETDONE = delay_RXRESETDONE;
assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ;
assign #(out_delay) RXSTATUS = delay_RXSTATUS;
assign #(out_delay) RXVALID = delay_RXVALID;
assign #(out_delay) TSTOUT = delay_TSTOUT;
assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS;
assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH;
assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE;
assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY;
assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC;
assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS;
assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE;
assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE;
assign #(out_delay) TXQPISENN = delay_TXQPISENN;
assign #(out_delay) TXQPISENP = delay_TXQPISENP;
assign #(out_delay) TXRATEDONE = delay_TXRATEDONE;
assign #(out_delay) TXRESETDONE = delay_TXRESETDONE;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK ^ IS_CPLLLOCKDETCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign #(INCLK_DELAY) delay_QPLLCLK = QPLLCLK;
assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK ^ IS_TXUSRCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2 ^ IS_TXUSRCLK2_INVERTED_REG;
assign #(in_delay) delay_CFGRESET = CFGRESET;
assign #(in_delay) delay_CLKRSVD = CLKRSVD;
assign #(in_delay) delay_CPLLLOCKEN = CPLLLOCKEN;
assign #(in_delay) delay_CPLLPD = CPLLPD;
assign #(in_delay) delay_CPLLREFCLKSEL = CPLLREFCLKSEL;
assign #(in_delay) delay_CPLLRESET = CPLLRESET;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_EYESCANMODE = EYESCANMODE;
assign #(in_delay) delay_EYESCANRESET = EYESCANRESET;
assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign #(in_delay) delay_GTRESETSEL = GTRESETSEL;
assign #(in_delay) delay_GTRSVD = GTRSVD;
assign #(in_delay) delay_GTRXRESET = GTRXRESET;
assign #(in_delay) delay_GTTXRESET = GTTXRESET;
assign #(in_delay) delay_GTXRXN = GTXRXN;
assign #(in_delay) delay_GTXRXP = GTXRXP;
assign #(in_delay) delay_LOOPBACK = LOOPBACK;
assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN;
assign #(in_delay) delay_PCSRSVDIN2 = PCSRSVDIN2;
assign #(in_delay) delay_PMARSVDIN = PMARSVDIN;
assign #(in_delay) delay_PMARSVDIN2 = PMARSVDIN2;
assign #(in_delay) delay_QPLLREFCLK = QPLLREFCLK;
assign #(in_delay) delay_RESETOVRD = RESETOVRD;
assign #(in_delay) delay_RX8B10BEN = RX8B10BEN;
assign #(in_delay) delay_RXBUFRESET = RXBUFRESET;
assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD;
assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN;
assign #(in_delay) delay_RXCDRRESET = RXCDRRESET;
assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN;
assign #(in_delay) delay_RXCHBONDI = RXCHBONDI;
assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL;
assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER;
assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE;
assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN;
assign #(in_delay) delay_RXDDIEN = RXDDIEN;
assign #(in_delay) delay_RXDFEAGCHOLD = RXDFEAGCHOLD;
assign #(in_delay) delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN;
assign #(in_delay) delay_RXDFECM1EN = RXDFECM1EN;
assign #(in_delay) delay_RXDFELFHOLD = RXDFELFHOLD;
assign #(in_delay) delay_RXDFELFOVRDEN = RXDFELFOVRDEN;
assign #(in_delay) delay_RXDFELPMRESET = RXDFELPMRESET;
assign #(in_delay) delay_RXDFETAP2HOLD = RXDFETAP2HOLD;
assign #(in_delay) delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN;
assign #(in_delay) delay_RXDFETAP3HOLD = RXDFETAP3HOLD;
assign #(in_delay) delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN;
assign #(in_delay) delay_RXDFETAP4HOLD = RXDFETAP4HOLD;
assign #(in_delay) delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN;
assign #(in_delay) delay_RXDFETAP5HOLD = RXDFETAP5HOLD;
assign #(in_delay) delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN;
assign #(in_delay) delay_RXDFEUTHOLD = RXDFEUTHOLD;
assign #(in_delay) delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN;
assign #(in_delay) delay_RXDFEVPHOLD = RXDFEVPHOLD;
assign #(in_delay) delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN;
assign #(in_delay) delay_RXDFEVSEN = RXDFEVSEN;
assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN;
assign #(in_delay) delay_RXDFEXYDHOLD = RXDFEXYDHOLD;
assign #(in_delay) delay_RXDFEXYDOVRDEN = RXDFEXYDOVRDEN;
assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS;
assign #(in_delay) delay_RXDLYEN = RXDLYEN;
assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET;
assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP;
assign #(in_delay) delay_RXLPMEN = RXLPMEN;
assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign #(in_delay) delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN;
assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN;
assign #(in_delay) delay_RXMONITORSEL = RXMONITORSEL;
assign #(in_delay) delay_RXOOBRESET = RXOOBRESET;
assign #(in_delay) delay_RXOSHOLD = RXOSHOLD;
assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN;
assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN;
assign #(in_delay) delay_RXPCSRESET = RXPCSRESET;
assign #(in_delay) delay_RXPD = RXPD;
assign #(in_delay) delay_RXPHALIGN = RXPHALIGN;
assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN;
assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD;
assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET;
assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN;
assign #(in_delay) delay_RXPMARESET = RXPMARESET;
assign #(in_delay) delay_RXPOLARITY = RXPOLARITY;
assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET;
assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL;
assign #(in_delay) delay_RXQPIEN = RXQPIEN;
assign #(in_delay) delay_RXRATE = RXRATE;
assign #(in_delay) delay_RXSLIDE = RXSLIDE;
assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign #(in_delay) delay_RXUSERRDY = RXUSERRDY;
assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS;
assign #(in_delay) delay_TSTIN = TSTIN;
assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS;
assign #(in_delay) delay_TX8B10BEN = TX8B10BEN;
assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE;
assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL;
assign #(in_delay) delay_TXCHARISK = TXCHARISK;
assign #(in_delay) delay_TXCOMINIT = TXCOMINIT;
assign #(in_delay) delay_TXCOMSAS = TXCOMSAS;
assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE;
assign #(in_delay) delay_TXDATA = TXDATA;
assign #(in_delay) delay_TXDEEMPH = TXDEEMPH;
assign #(in_delay) delay_TXDETECTRX = TXDETECTRX;
assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL;
assign #(in_delay) delay_TXDIFFPD = TXDIFFPD;
assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS;
assign #(in_delay) delay_TXDLYEN = TXDLYEN;
assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD;
assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET;
assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN;
assign #(in_delay) delay_TXELECIDLE = TXELECIDLE;
assign #(in_delay) delay_TXHEADER = TXHEADER;
assign #(in_delay) delay_TXINHIBIT = TXINHIBIT;
assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR;
assign #(in_delay) delay_TXMARGIN = TXMARGIN;
assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign #(in_delay) delay_TXPCSRESET = TXPCSRESET;
assign #(in_delay) delay_TXPD = TXPD;
assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign #(in_delay) delay_TXPHALIGN = TXPHALIGN;
assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN;
assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD;
assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET;
assign #(in_delay) delay_TXPHINIT = TXPHINIT;
assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN;
assign #(in_delay) delay_TXPISOPD = TXPISOPD;
assign #(in_delay) delay_TXPMARESET = TXPMARESET;
assign #(in_delay) delay_TXPOLARITY = TXPOLARITY;
assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR;
assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL;
assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR;
assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV;
assign #(in_delay) delay_TXQPIBIASEN = TXQPIBIASEN;
assign #(in_delay) delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN;
assign #(in_delay) delay_TXQPIWEAKPUP = TXQPIWEAKPUP;
assign #(in_delay) delay_TXRATE = TXRATE;
assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE;
assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ;
assign #(in_delay) delay_TXSWING = TXSWING;
assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign #(in_delay) delay_TXUSERRDY = TXUSERRDY;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CFGRESET = CFGRESET;
assign delay_CLKRSVD = CLKRSVD;
assign delay_CPLLLOCKDETCLK = CPLLLOCKDETCLK;
assign delay_CPLLLOCKEN = CPLLLOCKEN;
assign delay_CPLLPD = CPLLPD;
assign delay_CPLLREFCLKSEL = CPLLREFCLKSEL;
assign delay_CPLLRESET = CPLLRESET;
assign delay_EYESCANMODE = EYESCANMODE;
assign delay_EYESCANRESET = EYESCANRESET;
assign delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTRESETSEL = GTRESETSEL;
assign delay_GTRSVD = GTRSVD;
assign delay_GTRXRESET = GTRXRESET;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_GTTXRESET = GTTXRESET;
assign delay_GTXRXN = GTXRXN;
assign delay_GTXRXP = GTXRXP;
assign delay_LOOPBACK = LOOPBACK;
assign delay_PCSRSVDIN = PCSRSVDIN;
assign delay_PCSRSVDIN2 = PCSRSVDIN2;
assign delay_PMARSVDIN = PMARSVDIN;
assign delay_PMARSVDIN2 = PMARSVDIN2;
assign delay_QPLLCLK = QPLLCLK;
assign delay_QPLLREFCLK = QPLLREFCLK;
assign delay_RESETOVRD = RESETOVRD;
assign delay_RXBUFRESET = RXBUFRESET;
assign delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign delay_RXCDRHOLD = RXCDRHOLD;
assign delay_RXCDROVRDEN = RXCDROVRDEN;
assign delay_RXCDRRESET = RXCDRRESET;
assign delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign delay_RXDDIEN = RXDDIEN;
assign delay_RXDFEAGCHOLD = RXDFEAGCHOLD;
assign delay_RXDFEAGCOVRDEN = RXDFEAGCOVRDEN;
assign delay_RXDFECM1EN = RXDFECM1EN;
assign delay_RXDFELFHOLD = RXDFELFHOLD;
assign delay_RXDFELFOVRDEN = RXDFELFOVRDEN;
assign delay_RXDFELPMRESET = RXDFELPMRESET;
assign delay_RXDFETAP2HOLD = RXDFETAP2HOLD;
assign delay_RXDFETAP2OVRDEN = RXDFETAP2OVRDEN;
assign delay_RXDFETAP3HOLD = RXDFETAP3HOLD;
assign delay_RXDFETAP3OVRDEN = RXDFETAP3OVRDEN;
assign delay_RXDFETAP4HOLD = RXDFETAP4HOLD;
assign delay_RXDFETAP4OVRDEN = RXDFETAP4OVRDEN;
assign delay_RXDFETAP5HOLD = RXDFETAP5HOLD;
assign delay_RXDFETAP5OVRDEN = RXDFETAP5OVRDEN;
assign delay_RXDFEUTHOLD = RXDFEUTHOLD;
assign delay_RXDFEUTOVRDEN = RXDFEUTOVRDEN;
assign delay_RXDFEVPHOLD = RXDFEVPHOLD;
assign delay_RXDFEVPOVRDEN = RXDFEVPOVRDEN;
assign delay_RXDFEVSEN = RXDFEVSEN;
assign delay_RXDFEXYDEN = RXDFEXYDEN;
assign delay_RXDFEXYDHOLD = RXDFEXYDHOLD;
assign delay_RXDFEXYDOVRDEN = RXDFEXYDOVRDEN;
assign delay_RXDLYBYPASS = RXDLYBYPASS;
assign delay_RXDLYEN = RXDLYEN;
assign delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign delay_RXDLYSRESET = RXDLYSRESET;
assign delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign delay_RXLPMEN = RXLPMEN;
assign delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign delay_RXLPMLFKLOVRDEN = RXLPMLFKLOVRDEN;
assign delay_RXMONITORSEL = RXMONITORSEL;
assign delay_RXOOBRESET = RXOOBRESET;
assign delay_RXOSHOLD = RXOSHOLD;
assign delay_RXOSOVRDEN = RXOSOVRDEN;
assign delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign delay_RXPCSRESET = RXPCSRESET;
assign delay_RXPHALIGN = RXPHALIGN;
assign delay_RXPHALIGNEN = RXPHALIGNEN;
assign delay_RXPHDLYPD = RXPHDLYPD;
assign delay_RXPHDLYRESET = RXPHDLYRESET;
assign delay_RXPHOVRDEN = RXPHOVRDEN;
assign delay_RXPMARESET = RXPMARESET;
assign delay_RXQPIEN = RXQPIEN;
assign delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign delay_RXUSERRDY = RXUSERRDY;
//assign delay_RXUSRCLK = RXUSRCLK;
assign delay_TSTIN = TSTIN;
assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign delay_TXDEEMPH = TXDEEMPH;
assign delay_TXDIFFCTRL = TXDIFFCTRL;
assign delay_TXDIFFPD = TXDIFFPD;
assign delay_TXDLYBYPASS = TXDLYBYPASS;
assign delay_TXDLYEN = TXDLYEN;
assign delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign delay_TXDLYSRESET = TXDLYSRESET;
assign delay_TXMAINCURSOR = TXMAINCURSOR;
assign delay_TXMARGIN = TXMARGIN;
assign delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign delay_TXPCSRESET = TXPCSRESET;
assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign delay_TXPHALIGN = TXPHALIGN;
assign delay_TXPHALIGNEN = TXPHALIGNEN;
assign delay_TXPHDLYPD = TXPHDLYPD;
assign delay_TXPHDLYRESET = TXPHDLYRESET;
assign delay_TXPHINIT = TXPHINIT;
assign delay_TXPHOVRDEN = TXPHOVRDEN;
assign delay_TXPISOPD = TXPISOPD;
assign delay_TXPMARESET = TXPMARESET;
assign delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign delay_TXPRECURSOR = TXPRECURSOR;
assign delay_TXPRECURSORINV = TXPRECURSORINV;
assign delay_TXQPIBIASEN = TXQPIBIASEN;
assign delay_TXQPISTRONGPDOWN = TXQPISTRONGPDOWN;
assign delay_TXQPIWEAKPUP = TXQPIWEAKPUP;
assign delay_TXSWING = TXSWING;
assign delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign delay_TXUSERRDY = TXUSERRDY;
assign delay_TXUSRCLK = TXUSRCLK;
`endif
B_GTXE2_CHANNEL #(
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.GEARBOX_MODE (GEARBOX_MODE),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOUT_DIV (RXOUT_DIV),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_PD (RX_CLKMUX_PD),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG),
.RX_DFE_H2_CFG (RX_DFE_H2_CFG),
.RX_DFE_H3_CFG (RX_DFE_H3_CFG),
.RX_DFE_H4_CFG (RX_DFE_H4_CFG),
.RX_DFE_H5_CFG (RX_DFE_H5_CFG),
.RX_DFE_KL_CFG (RX_DFE_KL_CFG),
.RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2),
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE),
.RX_DFE_UT_CFG (RX_DFE_UT_CFG),
.RX_DFE_VP_CFG (RX_DFE_VP_CFG),
.RX_DFE_XYD_CFG (RX_DFE_XYD_CFG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.RX_XCLK_SEL (RX_XCLK_SEL),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOUT_DIV (TXOUT_DIV),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_PD (TX_CLKMUX_PD),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL (TX_XCLK_SEL),
.UCODEER_CLR (UCODEER_CLR))
B_GTXE2_CHANNEL_INST (
.CPLLFBCLKLOST (delay_CPLLFBCLKLOST),
.CPLLLOCK (delay_CPLLLOCK),
.CPLLREFCLKLOST (delay_CPLLREFCLKLOST),
.DMONITOROUT (delay_DMONITOROUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.EYESCANDATAERROR (delay_EYESCANDATAERROR),
.GTREFCLKMONITOR (delay_GTREFCLKMONITOR),
.GTXTXN (delay_GTXTXN),
.GTXTXP (delay_GTXTXP),
.PCSRSVDOUT (delay_PCSRSVDOUT),
.PHYSTATUS (delay_PHYSTATUS),
.RXBUFSTATUS (delay_RXBUFSTATUS),
.RXBYTEISALIGNED (delay_RXBYTEISALIGNED),
.RXBYTEREALIGN (delay_RXBYTEREALIGN),
.RXCDRLOCK (delay_RXCDRLOCK),
.RXCHANBONDSEQ (delay_RXCHANBONDSEQ),
.RXCHANISALIGNED (delay_RXCHANISALIGNED),
.RXCHANREALIGN (delay_RXCHANREALIGN),
.RXCHARISCOMMA (delay_RXCHARISCOMMA),
.RXCHARISK (delay_RXCHARISK),
.RXCHBONDO (delay_RXCHBONDO),
.RXCLKCORCNT (delay_RXCLKCORCNT),
.RXCOMINITDET (delay_RXCOMINITDET),
.RXCOMMADET (delay_RXCOMMADET),
.RXCOMSASDET (delay_RXCOMSASDET),
.RXCOMWAKEDET (delay_RXCOMWAKEDET),
.RXDATA (delay_RXDATA),
.RXDATAVALID (delay_RXDATAVALID),
.RXDISPERR (delay_RXDISPERR),
.RXDLYSRESETDONE (delay_RXDLYSRESETDONE),
.RXELECIDLE (delay_RXELECIDLE),
.RXHEADER (delay_RXHEADER),
.RXHEADERVALID (delay_RXHEADERVALID),
.RXMONITOROUT (delay_RXMONITOROUT),
.RXNOTINTABLE (delay_RXNOTINTABLE),
.RXOUTCLK (delay_RXOUTCLK),
.RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC),
.RXOUTCLKPCS (delay_RXOUTCLKPCS),
.RXPHALIGNDONE (delay_RXPHALIGNDONE),
.RXPHMONITOR (delay_RXPHMONITOR),
.RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR),
.RXPRBSERR (delay_RXPRBSERR),
.RXQPISENN (delay_RXQPISENN),
.RXQPISENP (delay_RXQPISENP),
.RXRATEDONE (delay_RXRATEDONE),
.RXRESETDONE (delay_RXRESETDONE),
.RXSTARTOFSEQ (delay_RXSTARTOFSEQ),
.RXSTATUS (delay_RXSTATUS),
.RXVALID (delay_RXVALID),
.TSTOUT (delay_TSTOUT),
.TXBUFSTATUS (delay_TXBUFSTATUS),
.TXCOMFINISH (delay_TXCOMFINISH),
.TXDLYSRESETDONE (delay_TXDLYSRESETDONE),
.TXGEARBOXREADY (delay_TXGEARBOXREADY),
.TXOUTCLK (delay_TXOUTCLK),
.TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC),
.TXOUTCLKPCS (delay_TXOUTCLKPCS),
.TXPHALIGNDONE (delay_TXPHALIGNDONE),
.TXPHINITDONE (delay_TXPHINITDONE),
.TXQPISENN (delay_TXQPISENN),
.TXQPISENP (delay_TXQPISENP),
.TXRATEDONE (delay_TXRATEDONE),
.TXRESETDONE (delay_TXRESETDONE),
.CFGRESET (delay_CFGRESET),
.CLKRSVD (delay_CLKRSVD),
.CPLLLOCKDETCLK (delay_CPLLLOCKDETCLK),
.CPLLLOCKEN (delay_CPLLLOCKEN),
.CPLLPD (delay_CPLLPD),
.CPLLREFCLKSEL (delay_CPLLREFCLKSEL),
.CPLLRESET (delay_CPLLRESET),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.EYESCANMODE (delay_EYESCANMODE),
.EYESCANRESET (delay_EYESCANRESET),
.EYESCANTRIGGER (delay_EYESCANTRIGGER),
.GTGREFCLK (delay_GTGREFCLK),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTRESETSEL (delay_GTRESETSEL),
.GTRSVD (delay_GTRSVD),
.GTRXRESET (delay_GTRXRESET),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.GTTXRESET (delay_GTTXRESET),
.GTXRXN (delay_GTXRXN),
.GTXRXP (delay_GTXRXP),
.LOOPBACK (delay_LOOPBACK),
.PCSRSVDIN (delay_PCSRSVDIN),
.PCSRSVDIN2 (delay_PCSRSVDIN2),
.PMARSVDIN (delay_PMARSVDIN),
.PMARSVDIN2 (delay_PMARSVDIN2),
.QPLLCLK (delay_QPLLCLK),
.QPLLREFCLK (delay_QPLLREFCLK),
.RESETOVRD (delay_RESETOVRD),
.RX8B10BEN (delay_RX8B10BEN),
.RXBUFRESET (delay_RXBUFRESET),
.RXCDRFREQRESET (delay_RXCDRFREQRESET),
.RXCDRHOLD (delay_RXCDRHOLD),
.RXCDROVRDEN (delay_RXCDROVRDEN),
.RXCDRRESET (delay_RXCDRRESET),
.RXCDRRESETRSV (delay_RXCDRRESETRSV),
.RXCHBONDEN (delay_RXCHBONDEN),
.RXCHBONDI (delay_RXCHBONDI),
.RXCHBONDLEVEL (delay_RXCHBONDLEVEL),
.RXCHBONDMASTER (delay_RXCHBONDMASTER),
.RXCHBONDSLAVE (delay_RXCHBONDSLAVE),
.RXCOMMADETEN (delay_RXCOMMADETEN),
.RXDDIEN (delay_RXDDIEN),
.RXDFEAGCHOLD (delay_RXDFEAGCHOLD),
.RXDFEAGCOVRDEN (delay_RXDFEAGCOVRDEN),
.RXDFECM1EN (delay_RXDFECM1EN),
.RXDFELFHOLD (delay_RXDFELFHOLD),
.RXDFELFOVRDEN (delay_RXDFELFOVRDEN),
.RXDFELPMRESET (delay_RXDFELPMRESET),
.RXDFETAP2HOLD (delay_RXDFETAP2HOLD),
.RXDFETAP2OVRDEN (delay_RXDFETAP2OVRDEN),
.RXDFETAP3HOLD (delay_RXDFETAP3HOLD),
.RXDFETAP3OVRDEN (delay_RXDFETAP3OVRDEN),
.RXDFETAP4HOLD (delay_RXDFETAP4HOLD),
.RXDFETAP4OVRDEN (delay_RXDFETAP4OVRDEN),
.RXDFETAP5HOLD (delay_RXDFETAP5HOLD),
.RXDFETAP5OVRDEN (delay_RXDFETAP5OVRDEN),
.RXDFEUTHOLD (delay_RXDFEUTHOLD),
.RXDFEUTOVRDEN (delay_RXDFEUTOVRDEN),
.RXDFEVPHOLD (delay_RXDFEVPHOLD),
.RXDFEVPOVRDEN (delay_RXDFEVPOVRDEN),
.RXDFEVSEN (delay_RXDFEVSEN),
.RXDFEXYDEN (delay_RXDFEXYDEN),
.RXDFEXYDHOLD (delay_RXDFEXYDHOLD),
.RXDFEXYDOVRDEN (delay_RXDFEXYDOVRDEN),
.RXDLYBYPASS (delay_RXDLYBYPASS),
.RXDLYEN (delay_RXDLYEN),
.RXDLYOVRDEN (delay_RXDLYOVRDEN),
.RXDLYSRESET (delay_RXDLYSRESET),
.RXELECIDLEMODE (delay_RXELECIDLEMODE),
.RXGEARBOXSLIP (delay_RXGEARBOXSLIP),
.RXLPMEN (delay_RXLPMEN),
.RXLPMHFHOLD (delay_RXLPMHFHOLD),
.RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN),
.RXLPMLFHOLD (delay_RXLPMLFHOLD),
.RXLPMLFKLOVRDEN (delay_RXLPMLFKLOVRDEN),
.RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN),
.RXMONITORSEL (delay_RXMONITORSEL),
.RXOOBRESET (delay_RXOOBRESET),
.RXOSHOLD (delay_RXOSHOLD),
.RXOSOVRDEN (delay_RXOSOVRDEN),
.RXOUTCLKSEL (delay_RXOUTCLKSEL),
.RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN),
.RXPCSRESET (delay_RXPCSRESET),
.RXPD (delay_RXPD),
.RXPHALIGN (delay_RXPHALIGN),
.RXPHALIGNEN (delay_RXPHALIGNEN),
.RXPHDLYPD (delay_RXPHDLYPD),
.RXPHDLYRESET (delay_RXPHDLYRESET),
.RXPHOVRDEN (delay_RXPHOVRDEN),
.RXPMARESET (delay_RXPMARESET),
.RXPOLARITY (delay_RXPOLARITY),
.RXPRBSCNTRESET (delay_RXPRBSCNTRESET),
.RXPRBSSEL (delay_RXPRBSSEL),
.RXQPIEN (delay_RXQPIEN),
.RXRATE (delay_RXRATE),
.RXSLIDE (delay_RXSLIDE),
.RXSYSCLKSEL (delay_RXSYSCLKSEL),
.RXUSERRDY (delay_RXUSERRDY),
.RXUSRCLK (delay_RXUSRCLK),
.RXUSRCLK2 (delay_RXUSRCLK2),
.SETERRSTATUS (delay_SETERRSTATUS),
.TSTIN (delay_TSTIN),
.TX8B10BBYPASS (delay_TX8B10BBYPASS),
.TX8B10BEN (delay_TX8B10BEN),
.TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL),
.TXCHARDISPMODE (delay_TXCHARDISPMODE),
.TXCHARDISPVAL (delay_TXCHARDISPVAL),
.TXCHARISK (delay_TXCHARISK),
.TXCOMINIT (delay_TXCOMINIT),
.TXCOMSAS (delay_TXCOMSAS),
.TXCOMWAKE (delay_TXCOMWAKE),
.TXDATA (delay_TXDATA),
.TXDEEMPH (delay_TXDEEMPH),
.TXDETECTRX (delay_TXDETECTRX),
.TXDIFFCTRL (delay_TXDIFFCTRL),
.TXDIFFPD (delay_TXDIFFPD),
.TXDLYBYPASS (delay_TXDLYBYPASS),
.TXDLYEN (delay_TXDLYEN),
.TXDLYHOLD (delay_TXDLYHOLD),
.TXDLYOVRDEN (delay_TXDLYOVRDEN),
.TXDLYSRESET (delay_TXDLYSRESET),
.TXDLYUPDOWN (delay_TXDLYUPDOWN),
.TXELECIDLE (delay_TXELECIDLE),
.TXHEADER (delay_TXHEADER),
.TXINHIBIT (delay_TXINHIBIT),
.TXMAINCURSOR (delay_TXMAINCURSOR),
.TXMARGIN (delay_TXMARGIN),
.TXOUTCLKSEL (delay_TXOUTCLKSEL),
.TXPCSRESET (delay_TXPCSRESET),
.TXPD (delay_TXPD),
.TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE),
.TXPHALIGN (delay_TXPHALIGN),
.TXPHALIGNEN (delay_TXPHALIGNEN),
.TXPHDLYPD (delay_TXPHDLYPD),
.TXPHDLYRESET (delay_TXPHDLYRESET),
.TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK),
.TXPHINIT (delay_TXPHINIT),
.TXPHOVRDEN (delay_TXPHOVRDEN),
.TXPISOPD (delay_TXPISOPD),
.TXPMARESET (delay_TXPMARESET),
.TXPOLARITY (delay_TXPOLARITY),
.TXPOSTCURSOR (delay_TXPOSTCURSOR),
.TXPOSTCURSORINV (delay_TXPOSTCURSORINV),
.TXPRBSFORCEERR (delay_TXPRBSFORCEERR),
.TXPRBSSEL (delay_TXPRBSSEL),
.TXPRECURSOR (delay_TXPRECURSOR),
.TXPRECURSORINV (delay_TXPRECURSORINV),
.TXQPIBIASEN (delay_TXQPIBIASEN),
.TXQPISTRONGPDOWN (delay_TXQPISTRONGPDOWN),
.TXQPIWEAKPUP (delay_TXQPIWEAKPUP),
.TXRATE (delay_TXRATE),
.TXSEQUENCE (delay_TXSEQUENCE),
.TXSTARTSEQ (delay_TXSTARTSEQ),
.TXSWING (delay_TXSWING),
.TXSYSCLKSEL (delay_TXSYSCLKSEL),
.TXUSERRDY (delay_TXUSERRDY),
.TXUSRCLK (delay_TXUSRCLK),
.TXUSRCLK2 (delay_TXUSRCLK2),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CLKRSVD[0], 0:0:0, notifier);
$period (posedge CLKRSVD[1], 0:0:0, notifier);
$period (posedge CPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLKMONITOR, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLCLK, 0:0:0, notifier);
$period (posedge RXOUTCLK, 0:0:0, notifier);
$period (posedge RXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge RXOUTCLKPCS, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge TXOUTCLK, 0:0:0, notifier);
$period (posedge TXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge TXOUTCLKPCS, 0:0:0, notifier);
$period (posedge TXPHDLYTSTCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPD, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPD);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPD, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPD);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ);
`endif
( CLKRSVD[1:1] *> DMONITOROUT[7:0]) = (0, 0);
( CLKRSVD[1:1] *> PCSRSVDOUT[8:2]) = (0, 0);
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTNORTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( GTREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> GTREFCLKMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> GTREFCLKMONITOR) = (0, 0);
( QPLLCLK *> GTREFCLKMONITOR) = (0, 0);
( RXUSRCLK *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> PHYSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0);
( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0);
( RXUSRCLK2 *> RXCHARISK) = (0, 0);
( RXUSRCLK2 *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0);
( RXUSRCLK2 *> RXCOMINITDET) = (0, 0);
( RXUSRCLK2 *> RXCOMMADET) = (0, 0);
( RXUSRCLK2 *> RXCOMSASDET) = (0, 0);
( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0);
( RXUSRCLK2 *> RXDATA) = (0, 0);
( RXUSRCLK2 *> RXDATAVALID) = (0, 0);
( RXUSRCLK2 *> RXDISPERR) = (0, 0);
( RXUSRCLK2 *> RXHEADER) = (0, 0);
( RXUSRCLK2 *> RXHEADERVALID) = (0, 0);
( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0);
( RXUSRCLK2 *> RXPRBSERR) = (0, 0);
( RXUSRCLK2 *> RXRATEDONE) = (0, 0);
( RXUSRCLK2 *> RXRESETDONE) = (0, 0);
( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0);
( RXUSRCLK2 *> RXSTATUS) = (0, 0);
( RXUSRCLK2 *> RXVALID) = (0, 0);
( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0);
( TXUSRCLK2 *> TXCOMFINISH) = (0, 0);
( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0);
( TXUSRCLK2 *> TXRATEDONE) = (0, 0);
( TXUSRCLK2 *> TXRESETDONE) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTXE2_COMMON.v 0000664 0000000 0000000 00000046614 12327044266 0023336 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTXE2_COMMON.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTXE2_COMMON (
DRPDO,
DRPRDY,
QPLLDMONITOR,
QPLLFBCLKLOST,
QPLLLOCK,
QPLLOUTCLK,
QPLLOUTREFCLK,
QPLLREFCLKLOST,
REFCLKOUTMONITOR,
BGBYPASSB,
BGMONITORENB,
BGPDB,
BGRCALOVRD,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
GTGREFCLK,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
PMARSVD,
QPLLLOCKDETCLK,
QPLLLOCKEN,
QPLLOUTRESET,
QPLLPD,
QPLLREFCLKSEL,
QPLLRESET,
QPLLRSVD1,
QPLLRSVD2,
RCALENB
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
parameter [31:0] COMMON_CFG = 32'h00000000;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [26:0] QPLL_CFG = 27'h0680181;
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
parameter [9:0] QPLL_CP = 10'b0000011111;
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
parameter [15:0] QPLL_LOCK_CFG = 16'h21E8;
parameter [3:0] QPLL_LPF = 4'b1111;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_VERSION = "4.0";
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output QPLLFBCLKLOST;
output QPLLLOCK;
output QPLLOUTCLK;
output QPLLOUTREFCLK;
output QPLLREFCLKLOST;
output REFCLKOUTMONITOR;
output [15:0] DRPDO;
output [7:0] QPLLDMONITOR;
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
input DRPCLK;
input DRPEN;
input DRPWE;
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
input QPLLPD;
input QPLLRESET;
input RCALENB;
input [15:0] DRPDI;
input [15:0] QPLLRSVD1;
input [2:0] QPLLREFCLKSEL;
input [4:0] BGRCALOVRD;
input [4:0] QPLLRSVD2;
input [7:0] DRPADDR;
input [7:0] PMARSVD;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY;
reg [0:0] QPLL_CP_MONITOR_EN_BINARY;
reg [0:0] QPLL_DMONITOR_SEL_BINARY;
reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY;
reg [0:0] QPLL_FBDIV_RATIO_BINARY;
reg [2:0] SIM_QPLLREFCLK_SEL_BINARY;
reg [3:0] QPLL_CLKOUT_CFG_BINARY;
reg [3:0] QPLL_LPF_BINARY;
reg [4:0] QPLL_REFCLK_DIV_BINARY;
reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY;
reg [9:0] QPLL_CP_BINARY;
reg [9:0] QPLL_FBDIV_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (QPLL_REFCLK_DIV)
2 : QPLL_REFCLK_DIV_BINARY = 5'b00000;
1 : QPLL_REFCLK_DIV_BINARY = 5'b10000;
3 : QPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : QPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : QPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : QPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : QPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : QPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : QPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : QPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : QPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on X_GTXE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2);
$finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
$finish;
end
endcase
case (SIM_VERSION)
"4.0" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.1" : SIM_VERSION_BINARY = 0;
"5.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are 4.0, 1.0, 1.1, 2.0, 3.0, 4.1, or 5.0.", SIM_VERSION);
$finish;
end
endcase
if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111))
QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG);
$finish;
end
if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111))
QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD);
$finish;
end
if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1))
QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN);
$finish;
end
if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111))
QPLL_CP_BINARY = QPLL_CP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP);
$finish;
end
if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1))
QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN);
$finish;
end
if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1))
QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL);
$finish;
end
if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111))
QPLL_FBDIV_BINARY = QPLL_FBDIV;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV);
$finish;
end
if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1))
QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN);
$finish;
end
if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1))
QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO);
$finish;
end
if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111))
QPLL_LPF_BINARY = QPLL_LPF;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_LPF on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF);
$finish;
end
if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111))
SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL);
$finish;
end
end
wire [15:0] delay_DRPDO;
wire [7:0] delay_QPLLDMONITOR;
wire delay_DRPRDY;
wire delay_QPLLFBCLKLOST;
wire delay_QPLLLOCK;
wire delay_QPLLOUTCLK;
wire delay_QPLLOUTREFCLK;
wire delay_QPLLREFCLKLOST;
wire delay_REFCLKOUTMONITOR;
wire [15:0] delay_DRPDI;
wire [15:0] delay_QPLLRSVD1;
wire [2:0] delay_QPLLREFCLKSEL;
wire [4:0] delay_BGRCALOVRD;
wire [4:0] delay_QPLLRSVD2;
wire [7:0] delay_DRPADDR;
wire [7:0] delay_PMARSVD;
wire delay_BGBYPASSB;
wire delay_BGMONITORENB;
wire delay_BGPDB;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_GTGREFCLK;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_QPLLLOCKDETCLK;
wire delay_QPLLLOCKEN;
wire delay_QPLLOUTRESET;
wire delay_QPLLPD;
wire delay_QPLLRESET;
wire delay_RCALENB;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED;
assign #(OUTCLK_DELAY) QPLLOUTCLK = delay_QPLLOUTCLK;
assign #(OUTCLK_DELAY) REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) QPLLDMONITOR = delay_QPLLDMONITOR;
assign #(out_delay) QPLLFBCLKLOST = delay_QPLLFBCLKLOST;
assign #(out_delay) QPLLLOCK = delay_QPLLLOCK;
assign #(out_delay) QPLLOUTREFCLK = delay_QPLLOUTREFCLK;
assign #(out_delay) QPLLREFCLKLOST = delay_QPLLREFCLKLOST;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign #(INCLK_DELAY) delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG;
assign #(in_delay) delay_BGBYPASSB = BGBYPASSB;
assign #(in_delay) delay_BGMONITORENB = BGMONITORENB;
assign #(in_delay) delay_BGPDB = BGPDB;
assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_PMARSVD = PMARSVD;
assign #(in_delay) delay_QPLLLOCKEN = QPLLLOCKEN;
assign #(in_delay) delay_QPLLOUTRESET = QPLLOUTRESET;
assign #(in_delay) delay_QPLLPD = QPLLPD;
assign #(in_delay) delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign #(in_delay) delay_QPLLRESET = QPLLRESET;
assign #(in_delay) delay_QPLLRSVD1 = QPLLRSVD1;
assign #(in_delay) delay_QPLLRSVD2 = QPLLRSVD2;
assign #(in_delay) delay_RCALENB = RCALENB;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_PMARSVD = PMARSVD;
assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK;
assign delay_QPLLLOCKEN = QPLLLOCKEN;
assign delay_QPLLOUTRESET = QPLLOUTRESET;
assign delay_QPLLPD = QPLLPD;
assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign delay_QPLLRESET = QPLLRESET;
assign delay_QPLLRSVD1 = QPLLRSVD1;
assign delay_QPLLRSVD2 = QPLLRSVD2;
assign delay_RCALENB = RCALENB;
`endif
B_GTXE2_COMMON #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG),
.QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD),
.QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN),
.QPLL_CP (QPLL_CP),
.QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN),
.QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (QPLL_INIT_CFG),
.QPLL_LOCK_CFG (QPLL_LOCK_CFG),
.QPLL_LPF (QPLL_LPF),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION))
B_GTXE2_COMMON_INST (
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.QPLLDMONITOR (delay_QPLLDMONITOR),
.QPLLFBCLKLOST (delay_QPLLFBCLKLOST),
.QPLLLOCK (delay_QPLLLOCK),
.QPLLOUTCLK (delay_QPLLOUTCLK),
.QPLLOUTREFCLK (delay_QPLLOUTREFCLK),
.QPLLREFCLKLOST (delay_QPLLREFCLKLOST),
.REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR),
.BGBYPASSB (delay_BGBYPASSB),
.BGMONITORENB (delay_BGMONITORENB),
.BGPDB (delay_BGPDB),
.BGRCALOVRD (delay_BGRCALOVRD),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.GTGREFCLK (delay_GTGREFCLK),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.PMARSVD (delay_PMARSVD),
.QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK),
.QPLLLOCKEN (delay_QPLLLOCKEN),
.QPLLOUTRESET (delay_QPLLOUTRESET),
.QPLLPD (delay_QPLLPD),
.QPLLREFCLKSEL (delay_QPLLREFCLKSEL),
.QPLLRESET (delay_QPLLRESET),
.QPLLRSVD1 (delay_QPLLRSVD1),
.QPLLRSVD2 (delay_QPLLRSVD2),
.RCALENB (delay_RCALENB),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge QPLLOUTCLK, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
`endif
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTYE3_CHANNEL.v 0000664 0000000 0000000 00000755340 12327044266 0023423 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTYE3_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTYE3_CHANNEL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'hF800,
parameter [15:0] ADAPT_CFG1 = 16'h0000,
parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [4:0] A_TXDIFFCTRL = 5'b01100,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter [0:0] CAPBYPASS_FORCE = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter [15:0] CH_HSPMUX = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000,
parameter [15:0] CKCAL_RSVD0 = 16'b0000000000000000,
parameter [15:0] CKCAL_RSVD1 = 16'b0000000000000000,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h20F8,
parameter [15:0] CPLL_CFG1 = 16'hA494,
parameter [15:0] CPLL_CFG2 = 16'hF001,
parameter [5:0] CPLL_CFG3 = 6'h00,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [7:0] CPLL_INIT_CFG1 = 8'h00,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000,
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DFE_D_X_REL_POS = 1'b0,
parameter [0:0] DFE_VCM_COMP_EN = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h000,
parameter [9:0] ES_PMA_CFG = 10'b0000000000,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUALIFIER5 = 16'h0000,
parameter [15:0] ES_QUALIFIER6 = 16'h0000,
parameter [15:0] ES_QUALIFIER7 = 16'h0000,
parameter [15:0] ES_QUALIFIER8 = 16'h0000,
parameter [15:0] ES_QUALIFIER9 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK5 = 16'h0000,
parameter [15:0] ES_QUAL_MASK6 = 16'h0000,
parameter [15:0] ES_QUAL_MASK7 = 16'h0000,
parameter [15:0] ES_QUAL_MASK8 = 16'h0000,
parameter [15:0] ES_QUAL_MASK9 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK5 = 16'h0000,
parameter [15:0] ES_SDATA_MASK6 = 16'h0000,
parameter [15:0] ES_SDATA_MASK7 = 16'h0000,
parameter [15:0] ES_SDATA_MASK8 = 16'h0000,
parameter [15:0] ES_SDATA_MASK9 = 16'h0000,
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] GM_BIAS_SELECT = 1'b0,
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [15:0] LOOP0_CFG = 16'h0000,
parameter [15:0] LOOP10_CFG = 16'h0000,
parameter [15:0] LOOP11_CFG = 16'h0000,
parameter [15:0] LOOP12_CFG = 16'h0000,
parameter [15:0] LOOP13_CFG = 16'h0000,
parameter [15:0] LOOP1_CFG = 16'h0000,
parameter [15:0] LOOP2_CFG = 16'h0000,
parameter [15:0] LOOP3_CFG = 16'h0000,
parameter [15:0] LOOP4_CFG = 16'h0000,
parameter [15:0] LOOP5_CFG = 16'h0000,
parameter [15:0] LOOP6_CFG = 16'h0000,
parameter [15:0] LOOP7_CFG = 16'h0000,
parameter [15:0] LOOP8_CFG = 16'h0000,
parameter [15:0] LOOP9_CFG = 16'h0000,
parameter [2:0] LPBK_BIAS_CTRL = 3'b000,
parameter [0:0] LPBK_EN_RCAL_B = 1'b0,
parameter [3:0] LPBK_EXT_RCAL = 4'b0000,
parameter [3:0] LPBK_RG_CTRL = 4'b0000,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [2:0] PCS_RSVD1 = 3'b000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0,
parameter [15:0] PMA_RSV0 = 16'h0000,
parameter [15:0] PMA_RSV1 = 16'h0000,
parameter [1:0] PREIQ_FREQ_BST = 2'b00,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0000,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG1 = 16'h0080,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h07E6,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG3 = 16'h0000,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG4 = 16'h0000,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG5 = 16'h0000,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42,
parameter [15:0] RXCDR_LOCK_CFG3 = 16'b0000000000000000,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [1:0] RXCFOKDONE_SRC = 2'b00,
parameter [15:0] RXCFOK_CFG0 = 16'h4000,
parameter [15:0] RXCFOK_CFG1 = 16'h0060,
parameter [15:0] RXCFOK_CFG2 = 16'h000E,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000,
parameter [15:0] RXDFE_CFG0 = 16'h0A00,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h7840,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG0 = 16'h4000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H6_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h8000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000,
parameter [0:0] RXDFE_PWR_SAVING = 1'b0,
parameter [15:0] RXDFE_UT_CFG0 = 16'h8000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0003,
parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0033,
parameter [15:0] RXDLY_CFG = 16'h001F,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "Sigcfg_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h0000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h8000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0002,
parameter [8:0] RXOOB_CFG = 9'b000000110,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h9933,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0,
parameter [15:0] RXPI_CFG = 16'h0100,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [15:0] RXPI_RSV0 = 16'h0000,
parameter [1:0] RXPI_SEL_LC = 2'b00,
parameter [1:0] RXPI_STARTCODE = 2'b00,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b0000,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter [1:0] RX_CM_SEL = 2'b11,
parameter [3:0] RX_CM_TRIM = 4'b0100,
parameter [0:0] RX_CTLE1_KHKL = 1'b0,
parameter [0:0] RX_CTLE2_KHKL = 1'b0,
parameter [0:0] RX_CTLE3_AGC = 1'b0,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [2:0] RX_DEGEN_CTRL = 3'b000,
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110,
parameter [0:0] RX_DFELPM_CFG1 = 1'b0,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100,
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [0:0] RX_DIV2_MODE_B = 1'b0,
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0,
parameter [0:0] RX_EN_HI_LR = 1'b0,
parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter real RX_PROGDIV_CFG = 0.0,
parameter [15:0] RX_PROGDIV_RATE = 16'h0001,
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000,
parameter [0:0] RX_RESLOAD_OVRD = 1'b0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter [3:0] RX_SUM_VCMTUNE = 4'b0000,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b000,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [2:0] RX_VREG_CTRL = 3'b000,
parameter [0:0] RX_VREG_PDB = 1'b0,
parameter [1:0] RX_WIDEMODE_CDR = 2'b00,
parameter RX_XCLK_SEL = "RXDES",
parameter [0:0] RX_XMODE_SEL = 1'b0,
parameter integer SAS_MAX_COM = 64,
parameter integer SAS_MIN_COM = 36,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter integer SATA_MAX_BURST = 8,
parameter integer SATA_MAX_INIT = 21,
parameter integer SATA_MAX_WAKE = 7,
parameter integer SATA_MIN_BURST = 4,
parameter integer SATA_MIN_INIT = 12,
parameter integer SATA_MIN_WAKE = 4,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001,
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0,
parameter SIM_VERSION = "Ver_1",
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATURE_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h001F,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h2020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0001,
parameter [15:0] TXPH_CFG = 16'h0123,
parameter [15:0] TXPH_CFG2 = 16'h0000,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [15:0] TXPI_RSV0 = 16'h0000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter [0:0] TX_CLKREG_PDB = 1'b0,
parameter [2:0] TX_CLKREG_SET = 3'b000,
parameter integer TX_DATA_WIDTH = 20,
parameter [5:0] TX_DCD_CFG = 6'b000010,
parameter [0:0] TX_DCD_EN = 1'b0,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter [1:0] TX_DRVMUX_CTRL = 2'b00,
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_EML_PHI_TUNE = 1'b0,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_FIFO_BYP_EN = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [2:0] TX_MODE_SEL = 3'b000,
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000,
parameter [15:0] TX_PHICAL_CFG1 = 16'h0000,
parameter [15:0] TX_PHICAL_CFG2 = 16'h0000,
parameter [1:0] TX_PI_BIASSET = 2'b00,
parameter [15:0] TX_PI_CFG0 = 16'h0000,
parameter [15:0] TX_PI_CFG1 = 16'h0000,
parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0,
parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0,
parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter [1:0] TX_PREDRV_CTRL = 2'b00,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 0.0,
parameter [15:0] TX_PROGDIV_RATE = 16'h0001,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter [2:0] TX_RXDETECT_REF = 3'b100,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0
)(
output [2:0] BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output [2:0] BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [16:0] DMONITOROUT,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output GTYTXN,
output GTYTXP,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [15:0] PCSRSVDOUT,
output PHYSTATUS,
output [7:0] PINRSRVDAS,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output RXCKOKDONE,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output [6:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDCCDONE,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CDRSTEPDIR,
input CDRSTEPSQ,
input CDRSTEPSX,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input ELPCALDVORWREN,
input ELPCALPAORWREN,
input EVODDPHICALDONE,
input EVODDPHICALSTART,
input EVODDPHIDRDEN,
input EVODDPHIDWREN,
input EVODDPHIXRDEN,
input EVODDPHIXWREN,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTRESETSEL,
input [15:0] GTRSVD,
input GTRXRESET,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input GTYRXN,
input GTYRXP,
input [2:0] LOOPBACK,
input [15:0] LOOPRSVD,
input LPBKRXTXSEREN,
input LPBKTXRXSEREN,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input QPLL0CLK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1REFCLK,
input RESETOVRD,
input RSTCLKENTX,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCKOKRESET,
input RXCOMMADETEN,
input RXDCCFORCESTART,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEVSEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input [3:0] RXOSINTCFG,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTOVRDEN,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [2:0] TXBUFDIFFCTRL,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDCCFORCESTART,
input TXDCCRESET,
input TXDEEMPH,
input TXDETECTRX,
input [4:0] TXDIFFCTRL,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input TXELFORCESTART,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPROGDIVRESET,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTYE3_CHANNEL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
localparam [15:0] ADAPT_CFG2_REG = ADAPT_CFG2;
localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
localparam [0:0] AUTO_BW_SEL_BYPASS_REG = AUTO_BW_SEL_BYPASS;
localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
localparam [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL;
localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
localparam [0:0] CAPBYPASS_FORCE_REG = CAPBYPASS_FORCE;
localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
localparam [15:0] CH_HSPMUX_REG = CH_HSPMUX;
localparam [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0;
localparam [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1;
localparam [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2;
localparam [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3;
localparam [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0;
localparam [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1;
localparam [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2;
localparam [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3;
localparam [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4;
localparam [15:0] CKCAL_RSVD0_REG = CKCAL_RSVD0;
localparam [15:0] CKCAL_RSVD1_REG = CKCAL_RSVD1;
localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0;
localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1;
localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2;
localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3;
localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1;
localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
localparam [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL;
localparam [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN;
localparam [1:0] DDI_CTRL_REG = DDI_CTRL;
localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS;
localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN;
localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
localparam [5:0] ES_CONTROL_REG = ES_CONTROL;
localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG;
localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE;
localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
localparam [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5;
localparam [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6;
localparam [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7;
localparam [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8;
localparam [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9;
localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
localparam [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5;
localparam [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6;
localparam [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7;
localparam [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8;
localparam [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9;
localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
localparam [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5;
localparam [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6;
localparam [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7;
localparam [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8;
localparam [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9;
localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG;
localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT;
localparam [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2;
localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
localparam [15:0] LOOP0_CFG_REG = LOOP0_CFG;
localparam [15:0] LOOP10_CFG_REG = LOOP10_CFG;
localparam [15:0] LOOP11_CFG_REG = LOOP11_CFG;
localparam [15:0] LOOP12_CFG_REG = LOOP12_CFG;
localparam [15:0] LOOP13_CFG_REG = LOOP13_CFG;
localparam [15:0] LOOP1_CFG_REG = LOOP1_CFG;
localparam [15:0] LOOP2_CFG_REG = LOOP2_CFG;
localparam [15:0] LOOP3_CFG_REG = LOOP3_CFG;
localparam [15:0] LOOP4_CFG_REG = LOOP4_CFG;
localparam [15:0] LOOP5_CFG_REG = LOOP5_CFG;
localparam [15:0] LOOP6_CFG_REG = LOOP6_CFG;
localparam [15:0] LOOP7_CFG_REG = LOOP7_CFG;
localparam [15:0] LOOP8_CFG_REG = LOOP8_CFG;
localparam [15:0] LOOP9_CFG_REG = LOOP9_CFG;
localparam [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL;
localparam [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B;
localparam [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL;
localparam [3:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL;
localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL;
localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP;
localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0;
localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1;
localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12;
localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3;
localparam [15:0] PMA_RSV0_REG = PMA_RSV0;
localparam [15:0] PMA_RSV1_REG = PMA_RSV1;
localparam [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST;
localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR;
localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
localparam [40:1] RXBUF_EN_REG = RXBUF_EN;
localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
localparam [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3;
localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
localparam [1:0] RXCFOKDONE_SRC_REG = RXCFOKDONE_SRC;
localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
localparam [0:0] RXDFE_PWR_SAVING_REG = RXDFE_PWR_SAVING;
localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG;
localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG;
localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG;
localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
localparam [5:0] RXOUT_DIV_REG = RXOUT_DIV;
localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
localparam [0:0] RXPI_AUTO_BW_SEL_BYPASS_REG = RXPI_AUTO_BW_SEL_BYPASS;
localparam [15:0] RXPI_CFG_REG = RXPI_CFG;
localparam [0:0] RXPI_LPM_REG = RXPI_LPM;
localparam [15:0] RXPI_RSV0_REG = RXPI_RSV0;
localparam [1:0] RXPI_SEL_LC_REG = RXPI_SEL_LC;
localparam [1:0] RXPI_STARTCODE_REG = RXPI_STARTCODE;
localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL;
localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
localparam [0:0] RX_CTLE1_KHKL_REG = RX_CTLE1_KHKL;
localparam [0:0] RX_CTLE2_KHKL_REG = RX_CTLE2_KHKL;
localparam [0:0] RX_CTLE3_AGC_REG = RX_CTLE3_AGC;
localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
localparam [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL;
localparam [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
localparam [0:0] RX_DIV2_MODE_B_REG = RX_DIV2_MODE_B;
localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
localparam [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B;
localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
localparam [8:0] RX_EXT_RL_CTRL_REG = RX_EXT_RL_CTRL;
localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
localparam [63:0] RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG * 1000;
localparam [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE;
localparam [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL;
localparam [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD;
localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
localparam [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL;
localparam [0:0] RX_VREG_PDB_REG = RX_VREG_PDB;
localparam [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
localparam [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL;
localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM;
localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM;
localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST;
localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT;
localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE;
localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST;
localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT;
localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE;
localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
localparam [2:0] SIM_CPLLREFCLK_SEL_REG = SIM_CPLLREFCLK_SEL;
localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
localparam [3:0] TEMPERATURE_PAR_REG = TEMPERATURE_PAR;
localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
localparam [7:0] TST_RSV0_REG = TST_RSV0;
localparam [7:0] TST_RSV1_REG = TST_RSV1;
localparam [40:1] TXBUF_EN_REG = TXBUF_EN;
localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG;
localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
localparam [4:0] TXOUT_DIV_REG = TXOUT_DIV;
localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
localparam [15:0] TXPH_CFG_REG = TXPH_CFG;
localparam [15:0] TXPH_CFG2_REG = TXPH_CFG2;
localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0;
localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1;
localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2;
localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3;
localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4;
localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5;
localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
localparam [0:0] TXPI_LPM_REG = TXPI_LPM;
localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
localparam [15:0] TXPI_RSV0_REG = TXPI_RSV0;
localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
localparam [0:0] TX_CLKREG_PDB_REG = TX_CLKREG_PDB;
localparam [2:0] TX_CLKREG_SET_REG = TX_CLKREG_SET;
localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG;
localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN;
localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
localparam [1:0] TX_DRVMUX_CTRL_REG = TX_DRVMUX_CTRL;
localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE;
localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
localparam [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN;
localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL;
localparam [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0;
localparam [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1;
localparam [15:0] TX_PHICAL_CFG2_REG = TX_PHICAL_CFG2;
localparam [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET;
localparam [15:0] TX_PI_CFG0_REG = TX_PI_CFG0;
localparam [15:0] TX_PI_CFG1_REG = TX_PI_CFG1;
localparam [0:0] TX_PI_DIV2_MODE_B_REG = TX_PI_DIV2_MODE_B;
localparam [0:0] TX_PI_SEL_QPLL0_REG = TX_PI_SEL_QPLL0;
localparam [0:0] TX_PI_SEL_QPLL1_REG = TX_PI_SEL_QPLL1;
localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
localparam [1:0] TX_PREDRV_CTRL_REG = TX_PREDRV_CTRL;
localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
localparam [63:0] TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG * 1000;
localparam [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE;
localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
`endif
localparam [0:0] AEN_CDRSTEPSEL_REG = 1'b0;
localparam [0:0] AEN_CPLL_REG = 1'b0;
localparam [0:0] AEN_ELPCAL_REG = 1'b0;
localparam [0:0] AEN_EYESCAN_REG = 1'b1;
localparam [0:0] AEN_LOOPBACK_REG = 1'b0;
localparam [0:0] AEN_MASTER_REG = 1'b0;
localparam [0:0] AEN_MUXDCD_REG = 1'b0;
localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
localparam [0:0] AEN_POLARITY_REG = 1'b0;
localparam [0:0] AEN_PRBS_REG = 1'b0;
localparam [0:0] AEN_RESET_REG = 1'b0;
localparam [0:0] AEN_RXCDR_REG = 1'b0;
localparam [0:0] AEN_RXDFE_REG = 1'b0;
localparam [0:0] AEN_RXDFELPM_REG = 1'b0;
localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXPHDLY_REG = 1'b0;
localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXPHDLY_REG = 1'b0;
localparam [0:0] AEN_TXPI_PPM_REG = 1'b0;
localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
localparam [15:0] AMONITOR_CFG_REG = 16'h0000;
localparam [0:0] A_AFECFOKEN_REG = 1'b0;
localparam [0:0] A_CPLLLOCKEN_REG = 1'b0;
localparam [0:0] A_CPLLPD_REG = 1'b0;
localparam [0:0] A_CPLLRESET_REG = 1'b0;
localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000;
localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000;
localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0;
localparam [0:0] A_DFECFOKHOLD_REG = 1'b0;
localparam [0:0] A_DFECFOKOVREN_REG = 1'b0;
localparam [0:0] A_ELPCALDVORWREN_REG = 1'b0;
localparam [0:0] A_ELPCALPAORWREN_REG = 1'b0;
localparam [0:0] A_EYESCANMODE_REG = 1'b0;
localparam [0:0] A_EYESCANRESET_REG = 1'b0;
localparam [0:0] A_GTRESETSEL_REG = 1'b0;
localparam [0:0] A_GTRXRESET_REG = 1'b0;
localparam [0:0] A_GTTXRESET_REG = 1'b0;
localparam [80:1] A_LOOPBACK_REG = "NoLoopBack";
localparam [0:0] A_LPMGCHOLD_REG = 1'b0;
localparam [0:0] A_LPMGCOVREN_REG = 1'b0;
localparam [0:0] A_LPMOSHOLD_REG = 1'b0;
localparam [0:0] A_LPMOSOVREN_REG = 1'b0;
localparam [0:0] A_MUXDCDEXHOLD_REG = 1'b0;
localparam [0:0] A_MUXDCDORWREN_REG = 1'b0;
localparam [0:0] A_RXBUFRESET_REG = 1'b0;
localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0;
localparam [0:0] A_RXCDRHOLD_REG = 1'b0;
localparam [0:0] A_RXCDROVRDEN_REG = 1'b0;
localparam [0:0] A_RXCDRRESET_REG = 1'b0;
localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0;
localparam [0:0] A_RXDFELFHOLD_REG = 1'b0;
localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFELPMRESET_REG = 1'b0;
localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP12HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP13HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP14HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP15HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVSEN_REG = 1'b0;
localparam [0:0] A_RXDFEXYDEN_REG = 1'b0;
localparam [0:0] A_RXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_RXDLYEN_REG = 1'b0;
localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDLYSRESET_REG = 1'b0;
localparam [0:0] A_RXLPMEN_REG = 1'b0;
localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
localparam [1:0] A_RXMONITORSEL_REG = 2'b00;
localparam [0:0] A_RXOOBRESET_REG = 1'b0;
localparam [0:0] A_RXOSHOLD_REG = 1'b0;
localparam [0:0] A_RXOSOVRDEN_REG = 1'b0;
localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_RXPCSRESET_REG = 1'b0;
localparam [24:1] A_RXPD_REG = "P0";
localparam [0:0] A_RXPHALIGN_REG = 1'b0;
localparam [0:0] A_RXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_RXPHDLYPD_REG = 1'b0;
localparam [0:0] A_RXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_RXPHOVRDEN_REG = 1'b0;
localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_RXPMARESET_REG = 1'b0;
localparam [0:0] A_RXPOLARITY_REG = 1'b0;
localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
localparam [48:1] A_RXPRBSSEL_REG = "PRBS7";
localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
localparam [0:0] A_TXDEEMPH_REG = 1'b0;
localparam [0:0] A_TXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_TXDLYEN_REG = 1'b0;
localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_TXDLYSRESET_REG = 1'b0;
localparam [0:0] A_TXELECIDLE_REG = 1'b0;
localparam [0:0] A_TXINHIBIT_REG = 1'b0;
localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
localparam [2:0] A_TXMARGIN_REG = 3'b000;
localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_TXPCSRESET_REG = 1'b0;
localparam [24:1] A_TXPD_REG = "P0";
localparam [0:0] A_TXPHALIGN_REG = 1'b0;
localparam [0:0] A_TXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_TXPHDLYPD_REG = 1'b0;
localparam [0:0] A_TXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_TXPHINIT_REG = 1'b0;
localparam [0:0] A_TXPHOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMPD_REG = 1'b0;
localparam [0:0] A_TXPIPPMSEL_REG = 1'b0;
localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_TXPMARESET_REG = 1'b0;
localparam [0:0] A_TXPOLARITY_REG = 1'b0;
localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
localparam [96:1] A_TXPRBSSEL_REG = "PRBS7";
localparam [4:0] A_TXPRECURSOR_REG = 5'b00000;
localparam [0:0] A_TXSWING_REG = 1'b0;
localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [0:0] CPLL_IPS_EN_REG = 1'b1;
localparam [2:0] CPLL_IPS_REFCLK_SEL_REG = 3'b000;
localparam [40:1] GEN_RXUSRCLK_REG = "TRUE";
localparam [40:1] GEN_TXUSRCLK_REG = "TRUE";
localparam [0:0] GT_INSTANTIATED_REG = 1'b1;
localparam [40:1] RXPLL_SEL_REG = "CPLL";
localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
localparam [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTYE3_CHANNEL_dr.v"
`endif
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire GTYTXN_out;
wire GTYTXP_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCKOKDONE_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDCCDONE_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [11:0] PMASCANOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DRPDO_out;
wire [15:0] PCSRSVDOUT_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [16:0] DMONITOROUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTCE_out;
wire [2:0] BUFGTRESET_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [6:0] RXMONITOROUT_out;
wire [7:0] PINRSRVDAS_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [8:0] BUFGTDIV_out;
wire CPLLFBCLKLOST_delay;
wire CPLLLOCK_delay;
wire CPLLREFCLKLOST_delay;
wire DRPRDY_delay;
wire EYESCANDATAERROR_delay;
wire GTPOWERGOOD_delay;
wire GTREFCLKMONITOR_delay;
wire GTYTXN_delay;
wire GTYTXP_delay;
wire PCIERATEGEN3_delay;
wire PCIERATEIDLE_delay;
wire PCIESYNCTXSYNCDONE_delay;
wire PCIEUSERGEN3RDY_delay;
wire PCIEUSERPHYSTATUSRST_delay;
wire PCIEUSERRATESTART_delay;
wire PHYSTATUS_delay;
wire RESETEXCEPTION_delay;
wire RXBYTEISALIGNED_delay;
wire RXBYTEREALIGN_delay;
wire RXCDRLOCK_delay;
wire RXCDRPHDONE_delay;
wire RXCHANBONDSEQ_delay;
wire RXCHANISALIGNED_delay;
wire RXCHANREALIGN_delay;
wire RXCKOKDONE_delay;
wire RXCOMINITDET_delay;
wire RXCOMMADET_delay;
wire RXCOMSASDET_delay;
wire RXCOMWAKEDET_delay;
wire RXDLYSRESETDONE_delay;
wire RXELECIDLE_delay;
wire RXOSINTDONE_delay;
wire RXOSINTSTARTED_delay;
wire RXOSINTSTROBEDONE_delay;
wire RXOSINTSTROBESTARTED_delay;
wire RXOUTCLKFABRIC_delay;
wire RXOUTCLKPCS_delay;
wire RXOUTCLK_delay;
wire RXPHALIGNDONE_delay;
wire RXPHALIGNERR_delay;
wire RXPMARESETDONE_delay;
wire RXPRBSERR_delay;
wire RXPRBSLOCKED_delay;
wire RXPRGDIVRESETDONE_delay;
wire RXRATEDONE_delay;
wire RXRECCLKOUT_delay;
wire RXRESETDONE_delay;
wire RXSLIDERDY_delay;
wire RXSLIPDONE_delay;
wire RXSLIPOUTCLKRDY_delay;
wire RXSLIPPMARDY_delay;
wire RXSYNCDONE_delay;
wire RXSYNCOUT_delay;
wire RXVALID_delay;
wire TXCOMFINISH_delay;
wire TXDCCDONE_delay;
wire TXDLYSRESETDONE_delay;
wire TXOUTCLKFABRIC_delay;
wire TXOUTCLKPCS_delay;
wire TXOUTCLK_delay;
wire TXPHALIGNDONE_delay;
wire TXPHINITDONE_delay;
wire TXPMARESETDONE_delay;
wire TXPRGDIVRESETDONE_delay;
wire TXRATEDONE_delay;
wire TXRESETDONE_delay;
wire TXSYNCDONE_delay;
wire TXSYNCOUT_delay;
wire [127:0] RXDATA_delay;
wire [15:0] DRPDO_delay;
wire [15:0] PCSRSVDOUT_delay;
wire [15:0] RXCTRL0_delay;
wire [15:0] RXCTRL1_delay;
wire [16:0] DMONITOROUT_delay;
wire [1:0] PCIERATEQPLLPD_delay;
wire [1:0] PCIERATEQPLLRESET_delay;
wire [1:0] RXCLKCORCNT_delay;
wire [1:0] RXDATAVALID_delay;
wire [1:0] RXHEADERVALID_delay;
wire [1:0] RXSTARTOFSEQ_delay;
wire [1:0] TXBUFSTATUS_delay;
wire [2:0] BUFGTCEMASK_delay;
wire [2:0] BUFGTCE_delay;
wire [2:0] BUFGTRESET_delay;
wire [2:0] BUFGTRSTMASK_delay;
wire [2:0] RXBUFSTATUS_delay;
wire [2:0] RXSTATUS_delay;
wire [4:0] RXCHBONDO_delay;
wire [5:0] RXHEADER_delay;
wire [6:0] RXMONITOROUT_delay;
wire [7:0] PINRSRVDAS_delay;
wire [7:0] RXCTRL2_delay;
wire [7:0] RXCTRL3_delay;
wire [7:0] RXDATAEXTENDRSVD_delay;
wire [8:0] BUFGTDIV_delay;
wire CDRSTEPDIR_in;
wire CDRSTEPSQ_in;
wire CDRSTEPSX_in;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire ELPCALDVORWREN_in;
wire ELPCALPAORWREN_in;
wire EVODDPHICALDONE_in;
wire EVODDPHICALSTART_in;
wire EVODDPHIDRDEN_in;
wire EVODDPHIDWREN_in;
wire EVODDPHIXRDEN_in;
wire EVODDPHIXWREN_in;
wire EYESCANMODE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire GTGREFCLK_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESET_in;
wire GTYRXN_in;
wire GTYRXP_in;
wire LPBKRXTXSEREN_in;
wire LPBKTXRXSEREN_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RSTCLKENTX_in;
wire RX8B10BEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESETRSV_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCKOKRESET_in;
wire RXCOMMADETEN_in;
wire RXDCCFORCESTART_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEVSEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSINTEN_in;
wire RXOSINTHOLD_in;
wire RXOSINTOVRDEN_in;
wire RXOSINTSTROBE_in;
wire RXOSINTTESTOVRDEN_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDCCFORCESTART_in;
wire TXDCCRESET_in;
wire TXDEEMPH_in;
wire TXDETECTRX_in;
wire TXDIFFPD_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXELFORCESTART_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPRBSFORCEERR_in;
wire TXPROGDIVRESET_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [11:0] PMASCANIN_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] LOOPRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXBUFDIFFCTRL_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXOSINTCFG_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] PCSRSVDIN2_in;
wire [4:0] PMARSVDIN_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXDIFFCTRL_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [9:0] DRPADDR_in;
wire CDRSTEPDIR_delay;
wire CDRSTEPSQ_delay;
wire CDRSTEPSX_delay;
wire CFGRESET_delay;
wire CLKRSVD0_delay;
wire CLKRSVD1_delay;
wire CPLLLOCKDETCLK_delay;
wire CPLLLOCKEN_delay;
wire CPLLPD_delay;
wire CPLLRESET_delay;
wire DMONFIFORESET_delay;
wire DMONITORCLK_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire ELPCALDVORWREN_delay;
wire ELPCALPAORWREN_delay;
wire EVODDPHICALDONE_delay;
wire EVODDPHICALSTART_delay;
wire EVODDPHIDRDEN_delay;
wire EVODDPHIDWREN_delay;
wire EVODDPHIXRDEN_delay;
wire EVODDPHIXWREN_delay;
wire EYESCANMODE_delay;
wire EYESCANRESET_delay;
wire EYESCANTRIGGER_delay;
wire GTGREFCLK_delay;
wire GTNORTHREFCLK0_delay;
wire GTNORTHREFCLK1_delay;
wire GTREFCLK0_delay;
wire GTREFCLK1_delay;
wire GTRESETSEL_delay;
wire GTRXRESET_delay;
wire GTSOUTHREFCLK0_delay;
wire GTSOUTHREFCLK1_delay;
wire GTTXRESET_delay;
wire GTYRXN_delay;
wire GTYRXP_delay;
wire LPBKRXTXSEREN_delay;
wire LPBKTXRXSEREN_delay;
wire PCIEEQRXEQADAPTDONE_delay;
wire PCIERSTIDLE_delay;
wire PCIERSTTXSYNCSTART_delay;
wire PCIEUSERRATEDONE_delay;
wire QPLL0CLK_delay;
wire QPLL0REFCLK_delay;
wire QPLL1CLK_delay;
wire QPLL1REFCLK_delay;
wire RESETOVRD_delay;
wire RSTCLKENTX_delay;
wire RX8B10BEN_delay;
wire RXBUFRESET_delay;
wire RXCDRFREQRESET_delay;
wire RXCDRHOLD_delay;
wire RXCDROVRDEN_delay;
wire RXCDRRESETRSV_delay;
wire RXCDRRESET_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCKOKRESET_delay;
wire RXCOMMADETEN_delay;
wire RXDCCFORCESTART_delay;
wire RXDFEAGCHOLD_delay;
wire RXDFEAGCOVRDEN_delay;
wire RXDFELFHOLD_delay;
wire RXDFELFOVRDEN_delay;
wire RXDFELPMRESET_delay;
wire RXDFETAP10HOLD_delay;
wire RXDFETAP10OVRDEN_delay;
wire RXDFETAP11HOLD_delay;
wire RXDFETAP11OVRDEN_delay;
wire RXDFETAP12HOLD_delay;
wire RXDFETAP12OVRDEN_delay;
wire RXDFETAP13HOLD_delay;
wire RXDFETAP13OVRDEN_delay;
wire RXDFETAP14HOLD_delay;
wire RXDFETAP14OVRDEN_delay;
wire RXDFETAP15HOLD_delay;
wire RXDFETAP15OVRDEN_delay;
wire RXDFETAP2HOLD_delay;
wire RXDFETAP2OVRDEN_delay;
wire RXDFETAP3HOLD_delay;
wire RXDFETAP3OVRDEN_delay;
wire RXDFETAP4HOLD_delay;
wire RXDFETAP4OVRDEN_delay;
wire RXDFETAP5HOLD_delay;
wire RXDFETAP5OVRDEN_delay;
wire RXDFETAP6HOLD_delay;
wire RXDFETAP6OVRDEN_delay;
wire RXDFETAP7HOLD_delay;
wire RXDFETAP7OVRDEN_delay;
wire RXDFETAP8HOLD_delay;
wire RXDFETAP8OVRDEN_delay;
wire RXDFETAP9HOLD_delay;
wire RXDFETAP9OVRDEN_delay;
wire RXDFEUTHOLD_delay;
wire RXDFEUTOVRDEN_delay;
wire RXDFEVPHOLD_delay;
wire RXDFEVPOVRDEN_delay;
wire RXDFEVSEN_delay;
wire RXDFEXYDEN_delay;
wire RXDLYBYPASS_delay;
wire RXDLYEN_delay;
wire RXDLYOVRDEN_delay;
wire RXDLYSRESET_delay;
wire RXGEARBOXSLIP_delay;
wire RXLATCLK_delay;
wire RXLPMEN_delay;
wire RXLPMGCHOLD_delay;
wire RXLPMGCOVRDEN_delay;
wire RXLPMHFHOLD_delay;
wire RXLPMHFOVRDEN_delay;
wire RXLPMLFHOLD_delay;
wire RXLPMLFKLOVRDEN_delay;
wire RXLPMOSHOLD_delay;
wire RXLPMOSOVRDEN_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXOOBRESET_delay;
wire RXOSCALRESET_delay;
wire RXOSHOLD_delay;
wire RXOSINTEN_delay;
wire RXOSINTHOLD_delay;
wire RXOSINTOVRDEN_delay;
wire RXOSINTSTROBE_delay;
wire RXOSINTTESTOVRDEN_delay;
wire RXOSOVRDEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPCSRESET_delay;
wire RXPHALIGNEN_delay;
wire RXPHALIGN_delay;
wire RXPHDLYPD_delay;
wire RXPHDLYRESET_delay;
wire RXPHOVRDEN_delay;
wire RXPMARESET_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXPROGDIVRESET_delay;
wire RXRATEMODE_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXSYNCALLIN_delay;
wire RXSYNCIN_delay;
wire RXSYNCMODE_delay;
wire RXUSERRDY_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire SIGVALIDCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDCCFORCESTART_delay;
wire TXDCCRESET_delay;
wire TXDEEMPH_delay;
wire TXDETECTRX_delay;
wire TXDIFFPD_delay;
wire TXDLYBYPASS_delay;
wire TXDLYEN_delay;
wire TXDLYHOLD_delay;
wire TXDLYOVRDEN_delay;
wire TXDLYSRESET_delay;
wire TXDLYUPDOWN_delay;
wire TXELECIDLE_delay;
wire TXELFORCESTART_delay;
wire TXINHIBIT_delay;
wire TXLATCLK_delay;
wire TXPCSRESET_delay;
wire TXPDELECIDLEMODE_delay;
wire TXPHALIGNEN_delay;
wire TXPHALIGN_delay;
wire TXPHDLYPD_delay;
wire TXPHDLYRESET_delay;
wire TXPHDLYTSTCLK_delay;
wire TXPHINIT_delay;
wire TXPHOVRDEN_delay;
wire TXPIPPMEN_delay;
wire TXPIPPMOVRDEN_delay;
wire TXPIPPMPD_delay;
wire TXPIPPMSEL_delay;
wire TXPISOPD_delay;
wire TXPMARESET_delay;
wire TXPOLARITY_delay;
wire TXPRBSFORCEERR_delay;
wire TXPROGDIVRESET_delay;
wire TXRATEMODE_delay;
wire TXSWING_delay;
wire TXSYNCALLIN_delay;
wire TXSYNCIN_delay;
wire TXSYNCMODE_delay;
wire TXUSERRDY_delay;
wire TXUSRCLK2_delay;
wire TXUSRCLK_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] GTRSVD_delay;
wire [15:0] LOOPRSVD_delay;
wire [15:0] PCSRSVDIN_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [19:0] TSTIN_delay;
wire [1:0] RXELECIDLEMODE_delay;
wire [1:0] RXMONITORSEL_delay;
wire [1:0] RXPD_delay;
wire [1:0] RXPLLCLKSEL_delay;
wire [1:0] RXSYSCLKSEL_delay;
wire [1:0] TXPD_delay;
wire [1:0] TXPLLCLKSEL_delay;
wire [1:0] TXSYSCLKSEL_delay;
wire [2:0] CPLLREFCLKSEL_delay;
wire [2:0] LOOPBACK_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXOUTCLKSEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXBUFDIFFCTRL_delay;
wire [2:0] TXMARGIN_delay;
wire [2:0] TXOUTCLKSEL_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXOSINTCFG_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] PCSRSVDIN2_delay;
wire [4:0] PMARSVDIN_delay;
wire [4:0] RXCHBONDI_delay;
wire [4:0] TXDIFFCTRL_delay;
wire [4:0] TXPIPPMSTEPSIZE_delay;
wire [4:0] TXPOSTCURSOR_delay;
wire [4:0] TXPRECURSOR_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXMAINCURSOR_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [7:0] TXDATAEXTENDRSVD_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) BUFGTCE = BUFGTCE_delay;
assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay;
assign #(out_delay) BUFGTDIV = BUFGTDIV_delay;
assign #(out_delay) BUFGTRESET = BUFGTRESET_delay;
assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay;
assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay;
assign #(out_delay) CPLLLOCK = CPLLLOCK_delay;
assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay;
assign #(out_delay) DMONITOROUT = DMONITOROUT_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay;
assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay;
assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay;
assign #(out_delay) GTYTXN = GTYTXN_delay;
assign #(out_delay) GTYTXP = GTYTXP_delay;
assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay;
assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay;
assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay;
assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay;
assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay;
assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay;
assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay;
assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay;
assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay;
assign #(out_delay) PHYSTATUS = PHYSTATUS_delay;
assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay;
assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay;
assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay;
assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay;
assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay;
assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay;
assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay;
assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay;
assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay;
assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay;
assign #(out_delay) RXCHBONDO = RXCHBONDO_delay;
assign #(out_delay) RXCKOKDONE = RXCKOKDONE_delay;
assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay;
assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay;
assign #(out_delay) RXCOMMADET = RXCOMMADET_delay;
assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay;
assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay;
assign #(out_delay) RXCTRL0 = RXCTRL0_delay;
assign #(out_delay) RXCTRL1 = RXCTRL1_delay;
assign #(out_delay) RXCTRL2 = RXCTRL2_delay;
assign #(out_delay) RXCTRL3 = RXCTRL3_delay;
assign #(out_delay) RXDATA = RXDATA_delay;
assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay;
assign #(out_delay) RXDATAVALID = RXDATAVALID_delay;
assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay;
assign #(out_delay) RXELECIDLE = RXELECIDLE_delay;
assign #(out_delay) RXHEADER = RXHEADER_delay;
assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay;
assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay;
assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay;
assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay;
assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay;
assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay;
assign #(out_delay) RXOUTCLK = RXOUTCLK_delay;
assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay;
assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay;
assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay;
assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay;
assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay;
assign #(out_delay) RXPRBSERR = RXPRBSERR_delay;
assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay;
assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay;
assign #(out_delay) RXRATEDONE = RXRATEDONE_delay;
assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay;
assign #(out_delay) RXRESETDONE = RXRESETDONE_delay;
assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay;
assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay;
assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay;
assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay;
assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay;
assign #(out_delay) RXSTATUS = RXSTATUS_delay;
assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay;
assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay;
assign #(out_delay) RXVALID = RXVALID_delay;
assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay;
assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay;
assign #(out_delay) TXDCCDONE = TXDCCDONE_delay;
assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay;
assign #(out_delay) TXOUTCLK = TXOUTCLK_delay;
assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay;
assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay;
assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay;
assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay;
assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay;
assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay;
assign #(out_delay) TXRATEDONE = TXRATEDONE_delay;
assign #(out_delay) TXRESETDONE = TXRESETDONE_delay;
assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay;
assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay;
// inputs with no timing checks
assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0;
assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1;
assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK;
assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK;
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK;
assign #(inclk_delay) RXLATCLK_delay = RXLATCLK;
assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2;
assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK;
assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK;
assign #(inclk_delay) TXLATCLK_delay = TXLATCLK;
assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK;
assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2;
assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK;
assign #(in_delay) CDRSTEPDIR_delay = CDRSTEPDIR;
assign #(in_delay) CDRSTEPSQ_delay = CDRSTEPSQ;
assign #(in_delay) CDRSTEPSX_delay = CDRSTEPSX;
assign #(in_delay) CFGRESET_delay = CFGRESET;
assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN;
assign #(in_delay) CPLLPD_delay = CPLLPD;
assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL;
assign #(in_delay) CPLLRESET_delay = CPLLRESET;
assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) ELPCALDVORWREN_delay = ELPCALDVORWREN;
assign #(in_delay) ELPCALPAORWREN_delay = ELPCALPAORWREN;
assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE;
assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART;
assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN;
assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN;
assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN;
assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN;
assign #(in_delay) EYESCANMODE_delay = EYESCANMODE;
assign #(in_delay) EYESCANRESET_delay = EYESCANRESET;
assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER;
assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0;
assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1;
assign #(in_delay) GTREFCLK0_delay = GTREFCLK0;
assign #(in_delay) GTREFCLK1_delay = GTREFCLK1;
assign #(in_delay) GTRESETSEL_delay = GTRESETSEL;
assign #(in_delay) GTRSVD_delay = GTRSVD;
assign #(in_delay) GTRXRESET_delay = GTRXRESET;
assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0;
assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1;
assign #(in_delay) GTTXRESET_delay = GTTXRESET;
assign #(in_delay) GTYRXN_delay = GTYRXN;
assign #(in_delay) GTYRXP_delay = GTYRXP;
assign #(in_delay) LOOPBACK_delay = LOOPBACK;
assign #(in_delay) LOOPRSVD_delay = LOOPRSVD;
assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN;
assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN;
assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE;
assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE;
assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART;
assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE;
assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2;
assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN;
assign #(in_delay) PMARSVDIN_delay = PMARSVDIN;
assign #(in_delay) QPLL0CLK_delay = QPLL0CLK;
assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK;
assign #(in_delay) QPLL1CLK_delay = QPLL1CLK;
assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK;
assign #(in_delay) RESETOVRD_delay = RESETOVRD;
assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX;
assign #(in_delay) RX8B10BEN_delay = RX8B10BEN;
assign #(in_delay) RXBUFRESET_delay = RXBUFRESET;
assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET;
assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD;
assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN;
assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV;
assign #(in_delay) RXCDRRESET_delay = RXCDRRESET;
assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN;
assign #(in_delay) RXCHBONDI_delay = RXCHBONDI;
assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL;
assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER;
assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE;
assign #(in_delay) RXCKOKRESET_delay = RXCKOKRESET;
assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN;
assign #(in_delay) RXDCCFORCESTART_delay = RXDCCFORCESTART;
assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD;
assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN;
assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD;
assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN;
assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET;
assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD;
assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN;
assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD;
assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN;
assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD;
assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN;
assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD;
assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN;
assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD;
assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN;
assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD;
assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN;
assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD;
assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN;
assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD;
assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN;
assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD;
assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN;
assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD;
assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN;
assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD;
assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN;
assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD;
assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN;
assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD;
assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN;
assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD;
assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN;
assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD;
assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN;
assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD;
assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN;
assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN;
assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN;
assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS;
assign #(in_delay) RXDLYEN_delay = RXDLYEN;
assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN;
assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET;
assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE;
assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP;
assign #(in_delay) RXLPMEN_delay = RXLPMEN;
assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD;
assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN;
assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD;
assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN;
assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD;
assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN;
assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD;
assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN;
assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN;
assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL;
assign #(in_delay) RXOOBRESET_delay = RXOOBRESET;
assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET;
assign #(in_delay) RXOSHOLD_delay = RXOSHOLD;
assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG;
assign #(in_delay) RXOSINTEN_delay = RXOSINTEN;
assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD;
assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN;
assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE;
assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN;
assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN;
assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL;
assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN;
assign #(in_delay) RXPCSRESET_delay = RXPCSRESET;
assign #(in_delay) RXPD_delay = RXPD;
assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN;
assign #(in_delay) RXPHALIGN_delay = RXPHALIGN;
assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD;
assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET;
assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN;
assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL;
assign #(in_delay) RXPMARESET_delay = RXPMARESET;
assign #(in_delay) RXPOLARITY_delay = RXPOLARITY;
assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET;
assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL;
assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET;
assign #(in_delay) RXRATEMODE_delay = RXRATEMODE;
assign #(in_delay) RXRATE_delay = RXRATE;
assign #(in_delay) RXSLIDE_delay = RXSLIDE;
assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK;
assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA;
assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN;
assign #(in_delay) RXSYNCIN_delay = RXSYNCIN;
assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE;
assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL;
assign #(in_delay) RXUSERRDY_delay = RXUSERRDY;
assign #(in_delay) TSTIN_delay = TSTIN;
assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS;
assign #(in_delay) TX8B10BEN_delay = TX8B10BEN;
assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL;
assign #(in_delay) TXCOMINIT_delay = TXCOMINIT;
assign #(in_delay) TXCOMSAS_delay = TXCOMSAS;
assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE;
assign #(in_delay) TXCTRL0_delay = TXCTRL0;
assign #(in_delay) TXCTRL1_delay = TXCTRL1;
assign #(in_delay) TXCTRL2_delay = TXCTRL2;
assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD;
assign #(in_delay) TXDATA_delay = TXDATA;
assign #(in_delay) TXDCCFORCESTART_delay = TXDCCFORCESTART;
assign #(in_delay) TXDCCRESET_delay = TXDCCRESET;
assign #(in_delay) TXDEEMPH_delay = TXDEEMPH;
assign #(in_delay) TXDETECTRX_delay = TXDETECTRX;
assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL;
assign #(in_delay) TXDIFFPD_delay = TXDIFFPD;
assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS;
assign #(in_delay) TXDLYEN_delay = TXDLYEN;
assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD;
assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN;
assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET;
assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN;
assign #(in_delay) TXELECIDLE_delay = TXELECIDLE;
assign #(in_delay) TXELFORCESTART_delay = TXELFORCESTART;
assign #(in_delay) TXHEADER_delay = TXHEADER;
assign #(in_delay) TXINHIBIT_delay = TXINHIBIT;
assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR;
assign #(in_delay) TXMARGIN_delay = TXMARGIN;
assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL;
assign #(in_delay) TXPCSRESET_delay = TXPCSRESET;
assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE;
assign #(in_delay) TXPD_delay = TXPD;
assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN;
assign #(in_delay) TXPHALIGN_delay = TXPHALIGN;
assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD;
assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET;
assign #(in_delay) TXPHINIT_delay = TXPHINIT;
assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN;
assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN;
assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN;
assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD;
assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL;
assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE;
assign #(in_delay) TXPISOPD_delay = TXPISOPD;
assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL;
assign #(in_delay) TXPMARESET_delay = TXPMARESET;
assign #(in_delay) TXPOLARITY_delay = TXPOLARITY;
assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR;
assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR;
assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL;
assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR;
assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET;
assign #(in_delay) TXRATEMODE_delay = TXRATEMODE;
assign #(in_delay) TXRATE_delay = TXRATE;
assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE;
assign #(in_delay) TXSWING_delay = TXSWING;
assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN;
assign #(in_delay) TXSYNCIN_delay = TXSYNCIN;
assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE;
assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL;
assign #(in_delay) TXUSERRDY_delay = TXUSERRDY;
assign BUFGTCEMASK_delay = BUFGTCEMASK_out;
assign BUFGTCE_delay = BUFGTCE_out;
assign BUFGTDIV_delay = BUFGTDIV_out;
assign BUFGTRESET_delay = BUFGTRESET_out;
assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out;
assign CPLLLOCK_delay = CPLLLOCK_out;
assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out;
assign DMONITOROUT_delay = DMONITOROUT_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out;
assign GTPOWERGOOD_delay = GTPOWERGOOD_out;
assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out;
assign GTYTXN_delay = GTYTXN_out;
assign GTYTXP_delay = GTYTXP_out;
assign PCIERATEGEN3_delay = PCIERATEGEN3_out;
assign PCIERATEIDLE_delay = PCIERATEIDLE_out;
assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out;
assign PCSRSVDOUT_delay = PCSRSVDOUT_out;
assign PHYSTATUS_delay = PHYSTATUS_out;
assign PINRSRVDAS_delay = PINRSRVDAS_out;
assign RESETEXCEPTION_delay = RESETEXCEPTION_out;
assign RXBUFSTATUS_delay = RXBUFSTATUS_out;
assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out;
assign RXCDRLOCK_delay = RXCDRLOCK_out;
assign RXCDRPHDONE_delay = RXCDRPHDONE_out;
assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out;
assign RXCHANREALIGN_delay = RXCHANREALIGN_out;
assign RXCHBONDO_delay = RXCHBONDO_out;
assign RXCKOKDONE_delay = RXCKOKDONE_out;
assign RXCLKCORCNT_delay = RXCLKCORCNT_out;
assign RXCOMINITDET_delay = RXCOMINITDET_out;
assign RXCOMMADET_delay = RXCOMMADET_out;
assign RXCOMSASDET_delay = RXCOMSASDET_out;
assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out;
assign RXCTRL0_delay = RXCTRL0_out;
assign RXCTRL1_delay = RXCTRL1_out;
assign RXCTRL2_delay = RXCTRL2_out;
assign RXCTRL3_delay = RXCTRL3_out;
assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out;
assign RXDATAVALID_delay = RXDATAVALID_out;
assign RXDATA_delay = RXDATA_out;
assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out;
assign RXELECIDLE_delay = RXELECIDLE_out;
assign RXHEADERVALID_delay = RXHEADERVALID_out;
assign RXHEADER_delay = RXHEADER_out;
assign RXMONITOROUT_delay = RXMONITOROUT_out;
assign RXOSINTDONE_delay = RXOSINTDONE_out;
assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out;
assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out;
assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out;
assign RXOUTCLK_delay = RXOUTCLK_out;
assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out;
assign RXPHALIGNERR_delay = RXPHALIGNERR_out;
assign RXPMARESETDONE_delay = RXPMARESETDONE_out;
assign RXPRBSERR_delay = RXPRBSERR_out;
assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out;
assign RXRATEDONE_delay = RXRATEDONE_out;
assign RXRECCLKOUT_delay = RXRECCLKOUT_out;
assign RXRESETDONE_delay = RXRESETDONE_out;
assign RXSLIDERDY_delay = RXSLIDERDY_out;
assign RXSLIPDONE_delay = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out;
assign RXSTATUS_delay = RXSTATUS_out;
assign RXSYNCDONE_delay = RXSYNCDONE_out;
assign RXSYNCOUT_delay = RXSYNCOUT_out;
assign RXVALID_delay = RXVALID_out;
assign TXBUFSTATUS_delay = TXBUFSTATUS_out;
assign TXCOMFINISH_delay = TXCOMFINISH_out;
assign TXDCCDONE_delay = TXDCCDONE_out;
assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out;
assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out;
assign TXOUTCLK_delay = TXOUTCLK_out;
assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out;
assign TXPHINITDONE_delay = TXPHINITDONE_out;
assign TXPMARESETDONE_delay = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out;
assign TXRATEDONE_delay = TXRATEDONE_out;
assign TXRESETDONE_delay = TXRESETDONE_out;
assign TXSYNCDONE_delay = TXSYNCDONE_out;
assign TXSYNCOUT_delay = TXSYNCOUT_out;
assign CDRSTEPDIR_in = CDRSTEPDIR_delay;
assign CDRSTEPSQ_in = CDRSTEPSQ_delay;
assign CDRSTEPSX_in = CDRSTEPSX_delay;
assign CFGRESET_in = CFGRESET_delay;
assign CLKRSVD0_in = CLKRSVD0_delay;
assign CLKRSVD1_in = CLKRSVD1_delay;
assign CPLLLOCKDETCLK_in = CPLLLOCKDETCLK_delay;
assign CPLLLOCKEN_in = CPLLLOCKEN_delay;
assign CPLLPD_in = CPLLPD_delay;
assign CPLLREFCLKSEL_in = CPLLREFCLKSEL_delay;
assign CPLLRESET_in = CPLLRESET_delay;
assign DMONFIFORESET_in = DMONFIFORESET_delay;
assign DMONITORCLK_in = DMONITORCLK_delay;
assign DRPADDR_in = DRPADDR_delay;
assign DRPCLK_in = DRPCLK_delay;
assign DRPDI_in = DRPDI_delay;
assign DRPEN_in = DRPEN_delay;
assign DRPWE_in = DRPWE_delay;
assign ELPCALDVORWREN_in = ELPCALDVORWREN_delay;
assign ELPCALPAORWREN_in = ELPCALPAORWREN_delay;
assign EVODDPHICALDONE_in = EVODDPHICALDONE_delay;
assign EVODDPHICALSTART_in = EVODDPHICALSTART_delay;
assign EVODDPHIDRDEN_in = EVODDPHIDRDEN_delay;
assign EVODDPHIDWREN_in = EVODDPHIDWREN_delay;
assign EVODDPHIXRDEN_in = EVODDPHIXRDEN_delay;
assign EVODDPHIXWREN_in = EVODDPHIXWREN_delay;
assign EYESCANMODE_in = EYESCANMODE_delay;
assign EYESCANRESET_in = EYESCANRESET_delay;
assign EYESCANTRIGGER_in = EYESCANTRIGGER_delay;
assign GTGREFCLK_in = GTGREFCLK_delay;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay;
assign GTREFCLK0_in = GTREFCLK0_delay;
assign GTREFCLK1_in = GTREFCLK1_delay;
assign GTRESETSEL_in = GTRESETSEL_delay;
assign GTRSVD_in = GTRSVD_delay;
assign GTRXRESET_in = GTRXRESET_delay;
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay;
assign GTTXRESET_in = GTTXRESET_delay;
assign GTYRXN_in = GTYRXN_delay;
assign GTYRXP_in = GTYRXP_delay;
assign LOOPBACK_in = LOOPBACK_delay;
assign LOOPRSVD_in = LOOPRSVD_delay;
assign LPBKRXTXSEREN_in = LPBKRXTXSEREN_delay;
assign LPBKTXRXSEREN_in = LPBKTXRXSEREN_delay;
assign PCIEEQRXEQADAPTDONE_in = PCIEEQRXEQADAPTDONE_delay;
assign PCIERSTIDLE_in = PCIERSTIDLE_delay;
assign PCIERSTTXSYNCSTART_in = PCIERSTTXSYNCSTART_delay;
assign PCIEUSERRATEDONE_in = PCIEUSERRATEDONE_delay;
assign PCSRSVDIN2_in = PCSRSVDIN2_delay;
assign PCSRSVDIN_in = PCSRSVDIN_delay;
assign PMARSVDIN_in = PMARSVDIN_delay;
assign QPLL0CLK_in = QPLL0CLK_delay;
assign QPLL0REFCLK_in = QPLL0REFCLK_delay;
assign QPLL1CLK_in = QPLL1CLK_delay;
assign QPLL1REFCLK_in = QPLL1REFCLK_delay;
assign RESETOVRD_in = RESETOVRD_delay;
assign RSTCLKENTX_in = RSTCLKENTX_delay;
assign RX8B10BEN_in = RX8B10BEN_delay;
assign RXBUFRESET_in = RXBUFRESET_delay;
assign RXCDRFREQRESET_in = RXCDRFREQRESET_delay;
assign RXCDRHOLD_in = RXCDRHOLD_delay;
assign RXCDROVRDEN_in = RXCDROVRDEN_delay;
assign RXCDRRESETRSV_in = RXCDRRESETRSV_delay;
assign RXCDRRESET_in = RXCDRRESET_delay;
assign RXCHBONDEN_in = RXCHBONDEN_delay;
assign RXCHBONDI_in = RXCHBONDI_delay;
assign RXCHBONDLEVEL_in = RXCHBONDLEVEL_delay;
assign RXCHBONDMASTER_in = RXCHBONDMASTER_delay;
assign RXCHBONDSLAVE_in = RXCHBONDSLAVE_delay;
assign RXCKOKRESET_in = RXCKOKRESET_delay;
assign RXCOMMADETEN_in = RXCOMMADETEN_delay;
assign RXDCCFORCESTART_in = RXDCCFORCESTART_delay;
assign RXDFEAGCHOLD_in = RXDFEAGCHOLD_delay;
assign RXDFEAGCOVRDEN_in = RXDFEAGCOVRDEN_delay;
assign RXDFELFHOLD_in = RXDFELFHOLD_delay;
assign RXDFELFOVRDEN_in = RXDFELFOVRDEN_delay;
assign RXDFELPMRESET_in = RXDFELPMRESET_delay;
assign RXDFETAP10HOLD_in = RXDFETAP10HOLD_delay;
assign RXDFETAP10OVRDEN_in = RXDFETAP10OVRDEN_delay;
assign RXDFETAP11HOLD_in = RXDFETAP11HOLD_delay;
assign RXDFETAP11OVRDEN_in = RXDFETAP11OVRDEN_delay;
assign RXDFETAP12HOLD_in = RXDFETAP12HOLD_delay;
assign RXDFETAP12OVRDEN_in = RXDFETAP12OVRDEN_delay;
assign RXDFETAP13HOLD_in = RXDFETAP13HOLD_delay;
assign RXDFETAP13OVRDEN_in = RXDFETAP13OVRDEN_delay;
assign RXDFETAP14HOLD_in = RXDFETAP14HOLD_delay;
assign RXDFETAP14OVRDEN_in = RXDFETAP14OVRDEN_delay;
assign RXDFETAP15HOLD_in = RXDFETAP15HOLD_delay;
assign RXDFETAP15OVRDEN_in = RXDFETAP15OVRDEN_delay;
assign RXDFETAP2HOLD_in = RXDFETAP2HOLD_delay;
assign RXDFETAP2OVRDEN_in = RXDFETAP2OVRDEN_delay;
assign RXDFETAP3HOLD_in = RXDFETAP3HOLD_delay;
assign RXDFETAP3OVRDEN_in = RXDFETAP3OVRDEN_delay;
assign RXDFETAP4HOLD_in = RXDFETAP4HOLD_delay;
assign RXDFETAP4OVRDEN_in = RXDFETAP4OVRDEN_delay;
assign RXDFETAP5HOLD_in = RXDFETAP5HOLD_delay;
assign RXDFETAP5OVRDEN_in = RXDFETAP5OVRDEN_delay;
assign RXDFETAP6HOLD_in = RXDFETAP6HOLD_delay;
assign RXDFETAP6OVRDEN_in = RXDFETAP6OVRDEN_delay;
assign RXDFETAP7HOLD_in = RXDFETAP7HOLD_delay;
assign RXDFETAP7OVRDEN_in = RXDFETAP7OVRDEN_delay;
assign RXDFETAP8HOLD_in = RXDFETAP8HOLD_delay;
assign RXDFETAP8OVRDEN_in = RXDFETAP8OVRDEN_delay;
assign RXDFETAP9HOLD_in = RXDFETAP9HOLD_delay;
assign RXDFETAP9OVRDEN_in = RXDFETAP9OVRDEN_delay;
assign RXDFEUTHOLD_in = RXDFEUTHOLD_delay;
assign RXDFEUTOVRDEN_in = RXDFEUTOVRDEN_delay;
assign RXDFEVPHOLD_in = RXDFEVPHOLD_delay;
assign RXDFEVPOVRDEN_in = RXDFEVPOVRDEN_delay;
assign RXDFEVSEN_in = RXDFEVSEN_delay;
assign RXDFEXYDEN_in = RXDFEXYDEN_delay;
assign RXDLYBYPASS_in = RXDLYBYPASS_delay;
assign RXDLYEN_in = RXDLYEN_delay;
assign RXDLYOVRDEN_in = RXDLYOVRDEN_delay;
assign RXDLYSRESET_in = RXDLYSRESET_delay;
assign RXELECIDLEMODE_in = RXELECIDLEMODE_delay;
assign RXGEARBOXSLIP_in = RXGEARBOXSLIP_delay;
assign RXLATCLK_in = RXLATCLK_delay;
assign RXLPMEN_in = RXLPMEN_delay;
assign RXLPMGCHOLD_in = RXLPMGCHOLD_delay;
assign RXLPMGCOVRDEN_in = RXLPMGCOVRDEN_delay;
assign RXLPMHFHOLD_in = RXLPMHFHOLD_delay;
assign RXLPMHFOVRDEN_in = RXLPMHFOVRDEN_delay;
assign RXLPMLFHOLD_in = RXLPMLFHOLD_delay;
assign RXLPMLFKLOVRDEN_in = RXLPMLFKLOVRDEN_delay;
assign RXLPMOSHOLD_in = RXLPMOSHOLD_delay;
assign RXLPMOSOVRDEN_in = RXLPMOSOVRDEN_delay;
assign RXMCOMMAALIGNEN_in = RXMCOMMAALIGNEN_delay;
assign RXMONITORSEL_in = RXMONITORSEL_delay;
assign RXOOBRESET_in = RXOOBRESET_delay;
assign RXOSCALRESET_in = RXOSCALRESET_delay;
assign RXOSHOLD_in = RXOSHOLD_delay;
assign RXOSINTCFG_in = RXOSINTCFG_delay;
assign RXOSINTEN_in = RXOSINTEN_delay;
assign RXOSINTHOLD_in = RXOSINTHOLD_delay;
assign RXOSINTOVRDEN_in = RXOSINTOVRDEN_delay;
assign RXOSINTSTROBE_in = RXOSINTSTROBE_delay;
assign RXOSINTTESTOVRDEN_in = RXOSINTTESTOVRDEN_delay;
assign RXOSOVRDEN_in = RXOSOVRDEN_delay;
assign RXOUTCLKSEL_in = RXOUTCLKSEL_delay;
assign RXPCOMMAALIGNEN_in = RXPCOMMAALIGNEN_delay;
assign RXPCSRESET_in = RXPCSRESET_delay;
assign RXPD_in = RXPD_delay;
assign RXPHALIGNEN_in = RXPHALIGNEN_delay;
assign RXPHALIGN_in = RXPHALIGN_delay;
assign RXPHDLYPD_in = RXPHDLYPD_delay;
assign RXPHDLYRESET_in = RXPHDLYRESET_delay;
assign RXPHOVRDEN_in = RXPHOVRDEN_delay;
assign RXPLLCLKSEL_in = RXPLLCLKSEL_delay;
assign RXPMARESET_in = RXPMARESET_delay;
assign RXPOLARITY_in = RXPOLARITY_delay;
assign RXPRBSCNTRESET_in = RXPRBSCNTRESET_delay;
assign RXPRBSSEL_in = RXPRBSSEL_delay;
assign RXPROGDIVRESET_in = RXPROGDIVRESET_delay;
assign RXRATEMODE_in = RXRATEMODE_delay;
assign RXRATE_in = RXRATE_delay;
assign RXSLIDE_in = RXSLIDE_delay;
assign RXSLIPOUTCLK_in = RXSLIPOUTCLK_delay;
assign RXSLIPPMA_in = RXSLIPPMA_delay;
assign RXSYNCALLIN_in = RXSYNCALLIN_delay;
assign RXSYNCIN_in = RXSYNCIN_delay;
assign RXSYNCMODE_in = RXSYNCMODE_delay;
assign RXSYSCLKSEL_in = RXSYSCLKSEL_delay;
assign RXUSERRDY_in = RXUSERRDY_delay;
assign RXUSRCLK2_in = RXUSRCLK2_delay;
assign RXUSRCLK_in = RXUSRCLK_delay;
assign SIGVALIDCLK_in = SIGVALIDCLK_delay;
assign TSTIN_in = TSTIN_delay;
assign TX8B10BBYPASS_in = TX8B10BBYPASS_delay;
assign TX8B10BEN_in = TX8B10BEN_delay;
assign TXBUFDIFFCTRL_in = TXBUFDIFFCTRL_delay;
assign TXCOMINIT_in = TXCOMINIT_delay;
assign TXCOMSAS_in = TXCOMSAS_delay;
assign TXCOMWAKE_in = TXCOMWAKE_delay;
assign TXCTRL0_in = TXCTRL0_delay;
assign TXCTRL1_in = TXCTRL1_delay;
assign TXCTRL2_in = TXCTRL2_delay;
assign TXDATAEXTENDRSVD_in = TXDATAEXTENDRSVD_delay;
assign TXDATA_in = TXDATA_delay;
assign TXDCCFORCESTART_in = TXDCCFORCESTART_delay;
assign TXDCCRESET_in = TXDCCRESET_delay;
assign TXDEEMPH_in = TXDEEMPH_delay;
assign TXDETECTRX_in = TXDETECTRX_delay;
assign TXDIFFCTRL_in = TXDIFFCTRL_delay;
assign TXDIFFPD_in = TXDIFFPD_delay;
assign TXDLYBYPASS_in = TXDLYBYPASS_delay;
assign TXDLYEN_in = TXDLYEN_delay;
assign TXDLYHOLD_in = TXDLYHOLD_delay;
assign TXDLYOVRDEN_in = TXDLYOVRDEN_delay;
assign TXDLYSRESET_in = TXDLYSRESET_delay;
assign TXDLYUPDOWN_in = TXDLYUPDOWN_delay;
assign TXELECIDLE_in = TXELECIDLE_delay;
assign TXELFORCESTART_in = TXELFORCESTART_delay;
assign TXHEADER_in = TXHEADER_delay;
assign TXINHIBIT_in = TXINHIBIT_delay;
assign TXLATCLK_in = TXLATCLK_delay;
assign TXMAINCURSOR_in = TXMAINCURSOR_delay;
assign TXMARGIN_in = TXMARGIN_delay;
assign TXOUTCLKSEL_in = TXOUTCLKSEL_delay;
assign TXPCSRESET_in = TXPCSRESET_delay;
assign TXPDELECIDLEMODE_in = TXPDELECIDLEMODE_delay;
assign TXPD_in = TXPD_delay;
assign TXPHALIGNEN_in = TXPHALIGNEN_delay;
assign TXPHALIGN_in = TXPHALIGN_delay;
assign TXPHDLYPD_in = TXPHDLYPD_delay;
assign TXPHDLYRESET_in = TXPHDLYRESET_delay;
assign TXPHDLYTSTCLK_in = TXPHDLYTSTCLK_delay;
assign TXPHINIT_in = TXPHINIT_delay;
assign TXPHOVRDEN_in = TXPHOVRDEN_delay;
assign TXPIPPMEN_in = TXPIPPMEN_delay;
assign TXPIPPMOVRDEN_in = TXPIPPMOVRDEN_delay;
assign TXPIPPMPD_in = TXPIPPMPD_delay;
assign TXPIPPMSEL_in = TXPIPPMSEL_delay;
assign TXPIPPMSTEPSIZE_in = TXPIPPMSTEPSIZE_delay;
assign TXPISOPD_in = TXPISOPD_delay;
assign TXPLLCLKSEL_in = TXPLLCLKSEL_delay;
assign TXPMARESET_in = TXPMARESET_delay;
assign TXPOLARITY_in = TXPOLARITY_delay;
assign TXPOSTCURSOR_in = TXPOSTCURSOR_delay;
assign TXPRBSFORCEERR_in = TXPRBSFORCEERR_delay;
assign TXPRBSSEL_in = TXPRBSSEL_delay;
assign TXPRECURSOR_in = TXPRECURSOR_delay;
assign TXPROGDIVRESET_in = TXPROGDIVRESET_delay;
assign TXRATEMODE_in = TXRATEMODE_delay;
assign TXRATE_in = TXRATE_delay;
assign TXSEQUENCE_in = TXSEQUENCE_delay;
assign TXSWING_in = TXSWING_delay;
assign TXSYNCALLIN_in = TXSYNCALLIN_delay;
assign TXSYNCIN_in = TXSYNCIN_delay;
assign TXSYNCMODE_in = TXSYNCMODE_delay;
assign TXSYSCLKSEL_in = TXSYSCLKSEL_delay;
assign TXUSERRDY_in = TXUSERRDY_delay;
assign TXUSRCLK2_in = TXUSRCLK2_delay;
assign TXUSRCLK_in = TXUSRCLK_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((ACJTAG_DEBUG_MODE_REG < 1'b0) || (ACJTAG_DEBUG_MODE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_DEBUG_MODE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_DEBUG_MODE_REG);
attr_err = 1'b1;
end
if ((ACJTAG_MODE_REG < 1'b0) || (ACJTAG_MODE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_MODE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_MODE_REG);
attr_err = 1'b1;
end
if ((ACJTAG_RESET_REG < 1'b0) || (ACJTAG_RESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ACJTAG_RESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ACJTAG_RESET_REG);
attr_err = 1'b1;
end
if ((ADAPT_CFG2_REG < 16'b0000000000000000) || (ADAPT_CFG2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute ADAPT_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, ADAPT_CFG2_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_DOUBLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_ENABLE_REG < 10'b0000000000) || (ALIGN_COMMA_ENABLE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_COMMA_ENABLE_REG);
attr_err = 1'b1;
end
if ((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4)) begin
$display("Attribute Syntax Error : The attribute ALIGN_COMMA_WORD on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, ALIGN_COMMA_WORD_REG, 1);
attr_err = 1'b1;
end
if ((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_MCOMMA_DET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((ALIGN_MCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_MCOMMA_VALUE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_MCOMMA_VALUE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_MCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute ALIGN_PCOMMA_DET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((ALIGN_PCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_PCOMMA_VALUE_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ALIGN_PCOMMA_VALUE on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ALIGN_PCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((AUTO_BW_SEL_BYPASS_REG < 1'b0) || (AUTO_BW_SEL_BYPASS_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute AUTO_BW_SEL_BYPASS on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, AUTO_BW_SEL_BYPASS_REG);
attr_err = 1'b1;
end
if ((A_RXOSCALRESET_REG < 1'b0) || (A_RXOSCALRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_RXOSCALRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_RXOSCALRESET_REG);
attr_err = 1'b1;
end
if ((A_RXPROGDIVRESET_REG < 1'b0) || (A_RXPROGDIVRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_RXPROGDIVRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_RXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((A_TXDIFFCTRL_REG < 5'b00000) || (A_TXDIFFCTRL_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute A_TXDIFFCTRL on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, A_TXDIFFCTRL_REG);
attr_err = 1'b1;
end
if ((A_TXPROGDIVRESET_REG < 1'b0) || (A_TXPROGDIVRESET_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute A_TXPROGDIVRESET on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, A_TXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((CAPBYPASS_FORCE_REG < 1'b0) || (CAPBYPASS_FORCE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute CAPBYPASS_FORCE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, CAPBYPASS_FORCE_REG);
attr_err = 1'b1;
end
if ((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED")) begin
$display("Attribute Syntax Error : The attribute CBCC_DATA_SOURCE_SEL on %s instance %m is set to %s. Legal values for this attribute are DECODED or ENCODED.", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((CDR_SWAP_MODE_EN_REG < 1'b0) || (CDR_SWAP_MODE_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute CDR_SWAP_MODE_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, CDR_SWAP_MODE_EN_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_KEEP_ALIGN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_MAX_SKEW on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG, 7);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_1_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_1_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_1_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CHAN_BOND_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_2_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_2_USE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4)) begin
$display("Attribute Syntax Error : The attribute CHAN_BOND_SEQ_LEN on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG, 2);
attr_err = 1'b1;
end
if ((CH_HSPMUX_REG < 16'b0000000000000000) || (CH_HSPMUX_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CH_HSPMUX on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CH_HSPMUX_REG);
attr_err = 1'b1;
end
if ((CKCAL1_CFG_0_REG < 16'b0000000000000000) || (CKCAL1_CFG_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL1_CFG_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL1_CFG_0_REG);
attr_err = 1'b1;
end
if ((CKCAL1_CFG_1_REG < 16'b0000000000000000) || (CKCAL1_CFG_1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL1_CFG_1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL1_CFG_1_REG);
attr_err = 1'b1;
end
if ((CKCAL1_CFG_2_REG < 16'b0000000000000000) || (CKCAL1_CFG_2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL1_CFG_2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL1_CFG_2_REG);
attr_err = 1'b1;
end
if ((CKCAL1_CFG_3_REG < 16'b0000000000000000) || (CKCAL1_CFG_3_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL1_CFG_3 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL1_CFG_3_REG);
attr_err = 1'b1;
end
if ((CKCAL2_CFG_0_REG < 16'b0000000000000000) || (CKCAL2_CFG_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL2_CFG_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL2_CFG_0_REG);
attr_err = 1'b1;
end
if ((CKCAL2_CFG_1_REG < 16'b0000000000000000) || (CKCAL2_CFG_1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL2_CFG_1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL2_CFG_1_REG);
attr_err = 1'b1;
end
if ((CKCAL2_CFG_2_REG < 16'b0000000000000000) || (CKCAL2_CFG_2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL2_CFG_2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL2_CFG_2_REG);
attr_err = 1'b1;
end
if ((CKCAL2_CFG_3_REG < 16'b0000000000000000) || (CKCAL2_CFG_3_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL2_CFG_3 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL2_CFG_3_REG);
attr_err = 1'b1;
end
if ((CKCAL2_CFG_4_REG < 16'b0000000000000000) || (CKCAL2_CFG_4_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL2_CFG_4 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL2_CFG_4_REG);
attr_err = 1'b1;
end
if ((CKCAL_RSVD0_REG < 16'b0000000000000000) || (CKCAL_RSVD0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL_RSVD0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL_RSVD0_REG);
attr_err = 1'b1;
end
if ((CKCAL_RSVD1_REG < 16'b0000000000000000) || (CKCAL_RSVD1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute CKCAL_RSVD1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, CKCAL_RSVD1_REG);
attr_err = 1'b1;
end
if ((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CLK_CORRECT_USE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_KEEP_IDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_MAX_LAT on %s instance %m is set to %d. Legal values for this attribute are 3 to 60.", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_MIN_LAT on %s instance %m is set to %d. Legal values for this attribute are 3 to 63.", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_PRECEDENCE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_REPEAT_WAIT on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_1_REG < 10'b0000000000) || (CLK_COR_SEQ_1_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_2_REG < 10'b0000000000) || (CLK_COR_SEQ_1_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_3_REG < 10'b0000000000) || (CLK_COR_SEQ_1_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_4_REG < 10'b0000000000) || (CLK_COR_SEQ_1_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_1_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_1_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_1_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_1_REG < 10'b0000000000) || (CLK_COR_SEQ_2_1_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_1 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_2_REG < 10'b0000000000) || (CLK_COR_SEQ_2_2_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_2 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_3_REG < 10'b0000000000) || (CLK_COR_SEQ_2_3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_4_REG < 10'b0000000000) || (CLK_COR_SEQ_2_4_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_4 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, CLK_COR_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_2_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_2_USE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4)) begin
$display("Attribute Syntax Error : The attribute CLK_COR_SEQ_LEN on %s instance %m is set to %d. Legal values for this attribute are 1 to 4.", MODULE_NAME, CLK_COR_SEQ_LEN_REG, 2);
attr_err = 1'b1;
end
if ((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5)) begin
$display("Attribute Syntax Error : The attribute CPLL_FBDIV_45 on %s instance %m is set to %d. Legal values for this attribute are 4 to 5.", MODULE_NAME, CPLL_FBDIV_45_REG, 4);
attr_err = 1'b1;
end
if ((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute CPLL_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, CPLL_FBDIV_REG, 4);
attr_err = 1'b1;
end
if ((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute CPLL_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, CPLL_REFCLK_DIV_REG, 1);
attr_err = 1'b1;
end
if ((CTLE3_OCAP_EXT_CTRL_REG < 3'b000) || (CTLE3_OCAP_EXT_CTRL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute CTLE3_OCAP_EXT_CTRL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, CTLE3_OCAP_EXT_CTRL_REG);
attr_err = 1'b1;
end
if ((CTLE3_OCAP_EXT_EN_REG < 1'b0) || (CTLE3_OCAP_EXT_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute CTLE3_OCAP_EXT_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, CTLE3_OCAP_EXT_EN_REG);
attr_err = 1'b1;
end
if ((DDI_CTRL_REG < 2'b00) || (DDI_CTRL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute DDI_CTRL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, DDI_CTRL_REG);
attr_err = 1'b1;
end
if ((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31)) begin
$display("Attribute Syntax Error : The attribute DDI_REALIGN_WAIT on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_MCOMMA_DETECT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_PCOMMA_DETECT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute DEC_VALID_COMMA_ONLY on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((DFE_D_X_REL_POS_REG < 1'b0) || (DFE_D_X_REL_POS_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute DFE_D_X_REL_POS on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DFE_D_X_REL_POS_REG);
attr_err = 1'b1;
end
if ((DFE_VCM_COMP_EN_REG < 1'b0) || (DFE_VCM_COMP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute DFE_VCM_COMP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DFE_VCM_COMP_EN_REG);
attr_err = 1'b1;
end
if ((ES_CLK_PHASE_SEL_REG < 1'b0) || (ES_CLK_PHASE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ES_CLK_PHASE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ES_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((ES_CONTROL_REG < 6'b000000) || (ES_CONTROL_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute ES_CONTROL on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, ES_CONTROL_REG);
attr_err = 1'b1;
end
if ((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ES_ERRDET_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ES_EYE_SCAN_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((ES_PMA_CFG_REG < 10'b0000000000) || (ES_PMA_CFG_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute ES_PMA_CFG on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, ES_PMA_CFG_REG);
attr_err = 1'b1;
end
if ((ES_PRESCALE_REG < 5'b00000) || (ES_PRESCALE_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute ES_PRESCALE on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, ES_PRESCALE_REG);
attr_err = 1'b1;
end
if ((EVODD_PHI_CFG_REG < 11'b00000000000) || (EVODD_PHI_CFG_REG > 11'b11111111111)) begin
$display("Attribute Syntax Error : The attribute EVODD_PHI_CFG on %s instance %m is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111.", MODULE_NAME, EVODD_PHI_CFG_REG);
attr_err = 1'b1;
end
if ((EYE_SCAN_SWAP_EN_REG < 1'b0) || (EYE_SCAN_SWAP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute EYE_SCAN_SWAP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, EYE_SCAN_SWAP_EN_REG);
attr_err = 1'b1;
end
if ((FTS_DESKEW_SEQ_ENABLE_REG < 4'b0000) || (FTS_DESKEW_SEQ_ENABLE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute FTS_DESKEW_SEQ_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, FTS_DESKEW_SEQ_ENABLE_REG);
attr_err = 1'b1;
end
if ((FTS_LANE_DESKEW_CFG_REG < 4'b0000) || (FTS_LANE_DESKEW_CFG_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute FTS_LANE_DESKEW_CFG on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, FTS_LANE_DESKEW_CFG_REG);
attr_err = 1'b1;
end
if ((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FTS_LANE_DESKEW_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((GEARBOX_MODE_REG < 5'b00000) || (GEARBOX_MODE_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute GEARBOX_MODE on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, GEARBOX_MODE_REG);
attr_err = 1'b1;
end
if ((GM_BIAS_SELECT_REG < 1'b0) || (GM_BIAS_SELECT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute GM_BIAS_SELECT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, GM_BIAS_SELECT_REG);
attr_err = 1'b1;
end
if ((ISCAN_CK_PH_SEL2_REG < 1'b0) || (ISCAN_CK_PH_SEL2_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute ISCAN_CK_PH_SEL2 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, ISCAN_CK_PH_SEL2_REG);
attr_err = 1'b1;
end
if ((LOCAL_MASTER_REG < 1'b0) || (LOCAL_MASTER_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute LOCAL_MASTER on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, LOCAL_MASTER_REG);
attr_err = 1'b1;
end
if ((LPBK_BIAS_CTRL_REG < 3'b000) || (LPBK_BIAS_CTRL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute LPBK_BIAS_CTRL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, LPBK_BIAS_CTRL_REG);
attr_err = 1'b1;
end
if ((LPBK_EN_RCAL_B_REG < 1'b0) || (LPBK_EN_RCAL_B_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute LPBK_EN_RCAL_B on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, LPBK_EN_RCAL_B_REG);
attr_err = 1'b1;
end
if ((LPBK_EXT_RCAL_REG < 4'b0000) || (LPBK_EXT_RCAL_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute LPBK_EXT_RCAL on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, LPBK_EXT_RCAL_REG);
attr_err = 1'b1;
end
if ((LPBK_RG_CTRL_REG < 4'b0000) || (LPBK_RG_CTRL_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute LPBK_RG_CTRL on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, LPBK_RG_CTRL_REG);
attr_err = 1'b1;
end
if ((OOBDIVCTL_REG < 2'b00) || (OOBDIVCTL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute OOBDIVCTL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, OOBDIVCTL_REG);
attr_err = 1'b1;
end
if ((OOB_PWRUP_REG < 1'b0) || (OOB_PWRUP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute OOB_PWRUP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, OOB_PWRUP_REG);
attr_err = 1'b1;
end
if ((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK")) begin
$display("Attribute Syntax Error : The attribute PCI3_AUTO_REALIGN on %s instance %m is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK.", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((PCI3_PIPE_RX_ELECIDLE_REG < 1'b0) || (PCI3_PIPE_RX_ELECIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_PIPE_RX_ELECIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_PIPE_RX_ELECIDLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ASYNC_EBUF_BYPASS_REG < 2'b00) || (PCI3_RX_ASYNC_EBUF_BYPASS_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ASYNC_EBUF_BYPASS on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, PCI3_RX_ASYNC_EBUF_BYPASS_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_EI2_ENABLE_REG < 1'b0) || (PCI3_RX_ELECIDLE_EI2_ENABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_EI2_ENABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_ELECIDLE_EI2_ENABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_H2L_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_H2L_COUNT_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_H2L_COUNT on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_COUNT_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_H2L_DISABLE_REG < 3'b000) || (PCI3_RX_ELECIDLE_H2L_DISABLE_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_H2L_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_HI_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_HI_COUNT_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_HI_COUNT on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, PCI3_RX_ELECIDLE_HI_COUNT_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_ELECIDLE_LP4_DISABLE_REG < 1'b0) || (PCI3_RX_ELECIDLE_LP4_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_ELECIDLE_LP4_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_ELECIDLE_LP4_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCI3_RX_FIFO_DISABLE_REG < 1'b0) || (PCI3_RX_FIFO_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute PCI3_RX_FIFO_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, PCI3_RX_FIFO_DISABLE_REG);
attr_err = 1'b1;
end
if ((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PCS_PCIE_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((PCS_RSVD0_REG < 16'b0000000000000000) || (PCS_RSVD0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute PCS_RSVD0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, PCS_RSVD0_REG);
attr_err = 1'b1;
end
if ((PCS_RSVD1_REG < 3'b000) || (PCS_RSVD1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PCS_RSVD1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PCS_RSVD1_REG);
attr_err = 1'b1;
end
if ((PREIQ_FREQ_BST_REG < 2'b00) || (PREIQ_FREQ_BST_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute PREIQ_FREQ_BST on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, PREIQ_FREQ_BST_REG);
attr_err = 1'b1;
end
if ((PROCESS_PAR_REG < 3'b000) || (PROCESS_PAR_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute PROCESS_PAR on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PROCESS_PAR_REG);
attr_err = 1'b1;
end
if ((RATE_SW_USE_DRP_REG < 1'b0) || (RATE_SW_USE_DRP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RATE_SW_USE_DRP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RATE_SW_USE_DRP_REG);
attr_err = 1'b1;
end
if ((RESET_POWERSAVE_DISABLE_REG < 1'b0) || (RESET_POWERSAVE_DISABLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RESET_POWERSAVE_DISABLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RESET_POWERSAVE_DISABLE_REG);
attr_err = 1'b1;
end
if ((RXBUFRESET_TIME_REG < 5'b00000) || (RXBUFRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXBUFRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXBUFRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST")) begin
$display("Attribute Syntax Error : The attribute RXBUF_ADDR_MODE on %s instance %m is set to %s. Legal values for this attribute are FULL or FAST.", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((RXBUF_EIDLE_HI_CNT_REG < 4'b0000) || (RXBUF_EIDLE_HI_CNT_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RXBUF_EIDLE_HI_CNT on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RXBUF_EIDLE_HI_CNT_REG);
attr_err = 1'b1;
end
if ((RXBUF_EIDLE_LO_CNT_REG < 4'b0000) || (RXBUF_EIDLE_LO_CNT_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RXBUF_EIDLE_LO_CNT on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RXBUF_EIDLE_LO_CNT_REG);
attr_err = 1'b1;
end
if ((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_CB_CHANGE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_COMMAALIGN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_EIDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_RESET_ON_RATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63)) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_OVFLW on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_OVRD on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63)) begin
$display("Attribute Syntax Error : The attribute RXBUF_THRESH_UNDFLW on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((RXCDRFREQRESET_TIME_REG < 5'b00000) || (RXCDRFREQRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXCDRFREQRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXCDRFREQRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXCDRPHRESET_TIME_REG < 5'b00000) || (RXCDRPHRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXCDRPHRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXCDRPHRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXCDR_FR_RESET_ON_EIDLE_REG < 1'b0) || (RXCDR_FR_RESET_ON_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_FR_RESET_ON_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_FR_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXCDR_HOLD_DURING_EIDLE_REG < 1'b0) || (RXCDR_HOLD_DURING_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_HOLD_DURING_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXCDR_LOCK_CFG3_REG < 16'b0000000000000000) || (RXCDR_LOCK_CFG3_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute RXCDR_LOCK_CFG3 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, RXCDR_LOCK_CFG3_REG);
attr_err = 1'b1;
end
if ((RXCDR_PH_RESET_ON_EIDLE_REG < 1'b0) || (RXCDR_PH_RESET_ON_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXCDR_PH_RESET_ON_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXCDR_PH_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((RXCFOKDONE_SRC_REG < 2'b00) || (RXCFOKDONE_SRC_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXCFOKDONE_SRC on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXCFOKDONE_SRC_REG);
attr_err = 1'b1;
end
if ((RXDFELPMRESET_TIME_REG < 7'b0000000) || (RXDFELPMRESET_TIME_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute RXDFELPMRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, RXDFELPMRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXDFE_PWR_SAVING_REG < 1'b0) || (RXDFE_PWR_SAVING_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXDFE_PWR_SAVING on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXDFE_PWR_SAVING_REG);
attr_err = 1'b1;
end
if ((RXELECIDLE_CFG_REG != "Sigcfg_4") &&
(RXELECIDLE_CFG_REG != "Sigcfg_1") &&
(RXELECIDLE_CFG_REG != "Sigcfg_2") &&
(RXELECIDLE_CFG_REG != "Sigcfg_3") &&
(RXELECIDLE_CFG_REG != "Sigcfg_6") &&
(RXELECIDLE_CFG_REG != "Sigcfg_8") &&
(RXELECIDLE_CFG_REG != "Sigcfg_12") &&
(RXELECIDLE_CFG_REG != "Sigcfg_16")) begin
$display("Attribute Syntax Error : The attribute RXELECIDLE_CFG on %s instance %m is set to %s. Legal values for this attribute are Sigcfg_4, Sigcfg_1, Sigcfg_2, Sigcfg_3, Sigcfg_6, Sigcfg_8, Sigcfg_12 or Sigcfg_16.", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5)) begin
$display("Attribute Syntax Error : The attribute RXGBOX_FIFO_INIT_RD_ADDR on %s instance %m is set to %d. Legal values for this attribute are 2 to 5.", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG, 4);
attr_err = 1'b1;
end
if ((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RXGEARBOX_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((RXISCANRESET_TIME_REG < 5'b00000) || (RXISCANRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXISCANRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXISCANRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXOOB_CFG_REG < 9'b000000000) || (RXOOB_CFG_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute RXOOB_CFG on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, RXOOB_CFG_REG);
attr_err = 1'b1;
end
if ((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC")) begin
$display("Attribute Syntax Error : The attribute RXOOB_CLK_CFG on %s instance %m is set to %s. Legal values for this attribute are PMA or FABRIC.", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((RXOSCALRESET_TIME_REG < 5'b00000) || (RXOSCALRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXOSCALRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXOSCALRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16) &&
(RXOUT_DIV_REG != 32)) begin
$display("Attribute Syntax Error : The attribute RXOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, RXOUT_DIV_REG, 4);
attr_err = 1'b1;
end
if ((RXPCSRESET_TIME_REG < 5'b00000) || (RXPCSRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPCSRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXPH_MONITOR_SEL_REG < 5'b00000) || (RXPH_MONITOR_SEL_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPH_MONITOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((RXPI_AUTO_BW_SEL_BYPASS_REG < 1'b0) || (RXPI_AUTO_BW_SEL_BYPASS_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_AUTO_BW_SEL_BYPASS on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_AUTO_BW_SEL_BYPASS_REG);
attr_err = 1'b1;
end
if ((RXPI_LPM_REG < 1'b0) || (RXPI_LPM_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_LPM on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_LPM_REG);
attr_err = 1'b1;
end
if ((RXPI_SEL_LC_REG < 2'b00) || (RXPI_SEL_LC_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_SEL_LC on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_SEL_LC_REG);
attr_err = 1'b1;
end
if ((RXPI_STARTCODE_REG < 2'b00) || (RXPI_STARTCODE_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXPI_STARTCODE on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXPI_STARTCODE_REG);
attr_err = 1'b1;
end
if ((RXPI_VREFSEL_REG < 1'b0) || (RXPI_VREFSEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPI_VREFSEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN")) begin
$display("Attribute Syntax Error : The attribute RXPMACLK_SEL on %s instance %m is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN.", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((RXPMARESET_TIME_REG < 5'b00000) || (RXPMARESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RXPMARESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((RXPRBS_ERR_LOOPBACK_REG < 1'b0) || (RXPRBS_ERR_LOOPBACK_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXPRBS_ERR_LOOPBACK on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXPRBS_ERR_LOOPBACK_REG);
attr_err = 1'b1;
end
if ((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255)) begin
$display("Attribute Syntax Error : The attribute RXPRBS_LINKACQ_CNT on %s instance %m is set to %d. Legal values for this attribute are 15 to 255.", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15)) begin
$display("Attribute Syntax Error : The attribute RXSLIDE_AUTO_WAIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 15.", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG, 7);
attr_err = 1'b1;
end
if ((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA")) begin
$display("Attribute Syntax Error : The attribute RXSLIDE_MODE on %s instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA.", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((RXSYNC_MULTILANE_REG < 1'b0) || (RXSYNC_MULTILANE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_MULTILANE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((RXSYNC_OVRD_REG < 1'b0) || (RXSYNC_OVRD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_OVRD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((RXSYNC_SKIP_DA_REG < 1'b0) || (RXSYNC_SKIP_DA_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RXSYNC_SKIP_DA on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((RX_AFE_CM_EN_REG < 1'b0) || (RX_AFE_CM_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_AFE_CM_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_AFE_CM_EN_REG);
attr_err = 1'b1;
end
if ((RX_BUFFER_CFG_REG < 6'b000000) || (RX_BUFFER_CFG_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute RX_BUFFER_CFG on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, RX_BUFFER_CFG_REG);
attr_err = 1'b1;
end
if ((RX_CAPFF_SARC_ENB_REG < 1'b0) || (RX_CAPFF_SARC_ENB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CAPFF_SARC_ENB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CAPFF_SARC_ENB_REG);
attr_err = 1'b1;
end
if ((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32)) begin
$display("Attribute Syntax Error : The attribute RX_CLK25_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((RX_CLKMUX_EN_REG < 1'b0) || (RX_CLKMUX_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CLKMUX_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((RX_CLK_SLIP_OVRD_REG < 5'b00000) || (RX_CLK_SLIP_OVRD_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RX_CLK_SLIP_OVRD on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RX_CLK_SLIP_OVRD_REG);
attr_err = 1'b1;
end
if ((RX_CM_BUF_CFG_REG < 4'b0000) || (RX_CM_BUF_CFG_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_CM_BUF_CFG on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_CM_BUF_CFG_REG);
attr_err = 1'b1;
end
if ((RX_CM_BUF_PD_REG < 1'b0) || (RX_CM_BUF_PD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CM_BUF_PD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CM_BUF_PD_REG);
attr_err = 1'b1;
end
if ((RX_CM_SEL_REG < 2'b00) || (RX_CM_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_CM_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((RX_CM_TRIM_REG < 4'b0000) || (RX_CM_TRIM_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_CM_TRIM on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((RX_CTLE1_KHKL_REG < 1'b0) || (RX_CTLE1_KHKL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CTLE1_KHKL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CTLE1_KHKL_REG);
attr_err = 1'b1;
end
if ((RX_CTLE2_KHKL_REG < 1'b0) || (RX_CTLE2_KHKL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CTLE2_KHKL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CTLE2_KHKL_REG);
attr_err = 1'b1;
end
if ((RX_CTLE3_AGC_REG < 1'b0) || (RX_CTLE3_AGC_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_CTLE3_AGC on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_CTLE3_AGC_REG);
attr_err = 1'b1;
end
if ((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160)) begin
$display("Attribute Syntax Error : The attribute RX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, RX_DATA_WIDTH_REG, 20);
attr_err = 1'b1;
end
if ((RX_DDI_SEL_REG < 6'b000000) || (RX_DDI_SEL_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute RX_DDI_SEL on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, RX_DDI_SEL_REG);
attr_err = 1'b1;
end
if ((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RX_DEFER_RESET_BUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((RX_DEGEN_CTRL_REG < 3'b000) || (RX_DEGEN_CTRL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DEGEN_CTRL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DEGEN_CTRL_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_CFG0_REG < 4'b0000) || (RX_DFELPM_CFG0_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_CFG1_REG < 1'b0) || (RX_DFELPM_CFG1_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFELPM_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFELPM_KLKH_AGC_STUP_EN_REG < 1'b0) || (RX_DFELPM_KLKH_AGC_STUP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFELPM_KLKH_AGC_STUP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFELPM_KLKH_AGC_STUP_EN_REG);
attr_err = 1'b1;
end
if ((RX_DFE_AGC_CFG0_REG < 2'b00) || (RX_DFE_AGC_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_AGC_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_AGC_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_AGC_CFG1_REG < 3'b000) || (RX_DFE_AGC_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_AGC_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KH_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KH_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KH_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KH_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KH_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KH_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KL_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KL_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KL_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((RX_DFE_KL_LPM_KL_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KL_CFG1_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_KL_LPM_KL_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((RX_DFE_LPM_HOLD_DURING_EIDLE_REG < 1'b0) || (RX_DFE_LPM_HOLD_DURING_EIDLE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DFE_LPM_HOLD_DURING_EIDLE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DFE_LPM_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute RX_DISPERR_SEQ_MATCH on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((RX_DIV2_MODE_B_REG < 1'b0) || (RX_DIV2_MODE_B_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_DIV2_MODE_B on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_DIV2_MODE_B_REG);
attr_err = 1'b1;
end
if ((RX_DIVRESET_TIME_REG < 5'b00000) || (RX_DIVRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute RX_DIVRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, RX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((RX_EN_CTLE_RCAL_B_REG < 1'b0) || (RX_EN_CTLE_RCAL_B_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EN_CTLE_RCAL_B on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EN_CTLE_RCAL_B_REG);
attr_err = 1'b1;
end
if ((RX_EN_HI_LR_REG < 1'b0) || (RX_EN_HI_LR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EN_HI_LR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EN_HI_LR_REG);
attr_err = 1'b1;
end
if ((RX_EXT_RL_CTRL_REG < 9'b000000000) || (RX_EXT_RL_CTRL_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute RX_EXT_RL_CTRL on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, RX_EXT_RL_CTRL_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_CODE_REG < 7'b0000000) || (RX_EYESCAN_VS_CODE_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_CODE on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, RX_EYESCAN_VS_CODE_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_NEG_DIR_REG < 1'b0) || (RX_EYESCAN_VS_NEG_DIR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_NEG_DIR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EYESCAN_VS_NEG_DIR_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_RANGE_REG < 2'b00) || (RX_EYESCAN_VS_RANGE_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_RANGE on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_EYESCAN_VS_RANGE_REG);
attr_err = 1'b1;
end
if ((RX_EYESCAN_VS_UT_SIGN_REG < 1'b0) || (RX_EYESCAN_VS_UT_SIGN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_EYESCAN_VS_UT_SIGN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_EYESCAN_VS_UT_SIGN_REG);
attr_err = 1'b1;
end
if ((RX_FABINT_USRCLK_FLOP_REG < 1'b0) || (RX_FABINT_USRCLK_FLOP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_FABINT_USRCLK_FLOP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2)) begin
$display("Attribute Syntax Error : The attribute RX_INT_DATAWIDTH on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, RX_INT_DATAWIDTH_REG, 1);
attr_err = 1'b1;
end
if ((RX_PMA_POWER_SAVE_REG < 1'b0) || (RX_PMA_POWER_SAVE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_PMA_POWER_SAVE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((RX_PROGDIV_CFG_REG/1000.0 != 0.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 4.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 5.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 8.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 10.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 16.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 16.5) &&
(RX_PROGDIV_CFG_REG/1000.0 != 20.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 32.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 33.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 40.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 64.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 66.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 80.0) &&
(RX_PROGDIV_CFG_REG/1000.0 != 100.0)) begin
$display("Attribute Syntax Error : The attribute RX_PROGDIV_CFG on %s instance %m is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0.", MODULE_NAME, RX_PROGDIV_CFG_REG/1000.0);
attr_err = 1'b1;
end
if ((RX_RESLOAD_CTRL_REG < 4'b0000) || (RX_RESLOAD_CTRL_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_RESLOAD_CTRL on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_RESLOAD_CTRL_REG);
attr_err = 1'b1;
end
if ((RX_RESLOAD_OVRD_REG < 1'b0) || (RX_RESLOAD_OVRD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_RESLOAD_OVRD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_RESLOAD_OVRD_REG);
attr_err = 1'b1;
end
if ((RX_SAMPLE_PERIOD_REG < 3'b000) || (RX_SAMPLE_PERIOD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_SAMPLE_PERIOD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32)) begin
$display("Attribute Syntax Error : The attribute RX_SIG_VALID_DLY on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((RX_SUM_DFETAPREP_EN_REG < 1'b0) || (RX_SUM_DFETAPREP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_DFETAPREP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_SUM_DFETAPREP_EN_REG);
attr_err = 1'b1;
end
if ((RX_SUM_IREF_TUNE_REG < 4'b0000) || (RX_SUM_IREF_TUNE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_IREF_TUNE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_SUM_IREF_TUNE_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VCMTUNE_REG < 4'b0000) || (RX_SUM_VCMTUNE_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VCMTUNE on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, RX_SUM_VCMTUNE_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VCM_OVWR_REG < 1'b0) || (RX_SUM_VCM_OVWR_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VCM_OVWR on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_SUM_VCM_OVWR_REG);
attr_err = 1'b1;
end
if ((RX_SUM_VREF_TUNE_REG < 3'b000) || (RX_SUM_VREF_TUNE_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_SUM_VREF_TUNE on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_SUM_VREF_TUNE_REG);
attr_err = 1'b1;
end
if ((RX_TUNE_AFE_OS_REG < 2'b00) || (RX_TUNE_AFE_OS_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_TUNE_AFE_OS on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_TUNE_AFE_OS_REG);
attr_err = 1'b1;
end
if ((RX_VREG_CTRL_REG < 3'b000) || (RX_VREG_CTRL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute RX_VREG_CTRL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, RX_VREG_CTRL_REG);
attr_err = 1'b1;
end
if ((RX_VREG_PDB_REG < 1'b0) || (RX_VREG_PDB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_VREG_PDB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_VREG_PDB_REG);
attr_err = 1'b1;
end
if ((RX_WIDEMODE_CDR_REG < 2'b00) || (RX_WIDEMODE_CDR_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RX_WIDEMODE_CDR on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RX_WIDEMODE_CDR_REG);
attr_err = 1'b1;
end
if ((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR")) begin
$display("Attribute Syntax Error : The attribute RX_XCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR.", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((RX_XMODE_SEL_REG < 1'b0) || (RX_XMODE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute RX_XMODE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, RX_XMODE_SEL_REG);
attr_err = 1'b1;
end
if ((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127)) begin
$display("Attribute Syntax Error : The attribute SAS_MAX_COM on %s instance %m is set to %d. Legal values for this attribute are 1 to 127.", MODULE_NAME, SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SAS_MIN_COM on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if ((SATA_BURST_SEQ_LEN_REG < 4'b0000) || (SATA_BURST_SEQ_LEN_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute SATA_BURST_SEQ_LEN on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, SATA_BURST_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((SATA_BURST_VAL_REG < 3'b000) || (SATA_BURST_VAL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SATA_BURST_VAL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SATA_BURST_VAL_REG);
attr_err = 1'b1;
end
if ((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ")) begin
$display("Attribute Syntax Error : The attribute SATA_CPLL_CFG on %s instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ.", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((SATA_EIDLE_VAL_REG < 3'b000) || (SATA_EIDLE_VAL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SATA_EIDLE_VAL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SATA_EIDLE_VAL_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_BURST on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_INIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MAX_WAKE on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_BURST on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_INIT on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63)) begin
$display("Attribute Syntax Error : The attribute SATA_MIN_WAKE on %s instance %m is set to %d. Legal values for this attribute are 1 to 63.", MODULE_NAME, SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SHOW_REALIGN_COMMA on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((SIM_CPLLREFCLK_SEL_REG < 3'b000) || (SIM_CPLLREFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_CPLLREFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_CPLLREFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RECEIVER_DETECT_PASS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RESET_SPEEDUP on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((SIM_TX_EIDLE_DRIVE_LEVEL_REG < 1'b0) || (SIM_TX_EIDLE_DRIVE_LEVEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SIM_TX_EIDLE_DRIVE_LEVEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2")) begin
$display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2.", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((TEMPERATURE_PAR_REG < 4'b0000) || (TEMPERATURE_PAR_REG > 4'b1111)) begin
$display("Attribute Syntax Error : The attribute TEMPERATURE_PAR on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, TEMPERATURE_PAR_REG);
attr_err = 1'b1;
end
if ((TERM_RCAL_CFG_REG < 15'b000000000000000) || (TERM_RCAL_CFG_REG > 15'b111111111111111)) begin
$display("Attribute Syntax Error : The attribute TERM_RCAL_CFG on %s instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", MODULE_NAME, TERM_RCAL_CFG_REG);
attr_err = 1'b1;
end
if ((TERM_RCAL_OVRD_REG < 3'b000) || (TERM_RCAL_OVRD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TERM_RCAL_OVRD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TERM_RCAL_OVRD_REG);
attr_err = 1'b1;
end
if ((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TXBUF_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TXBUF_RESET_ON_RATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH")) begin
$display("Attribute Syntax Error : The attribute TXFIFO_ADDR_CFG on %s instance %m is set to %s. Legal values for this attribute are LOW or HIGH.", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6)) begin
$display("Attribute Syntax Error : The attribute TXGBOX_FIFO_INIT_RD_ADDR on %s instance %m is set to %d. Legal values for this attribute are 2 to 6.", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG, 4);
attr_err = 1'b1;
end
if ((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TXGEARBOX_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16)) begin
$display("Attribute Syntax Error : The attribute TXOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 16.", MODULE_NAME, TXOUT_DIV_REG, 4);
attr_err = 1'b1;
end
if ((TXPCSRESET_TIME_REG < 5'b00000) || (TXPCSRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPCSRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((TXPH_MONITOR_SEL_REG < 5'b00000) || (TXPH_MONITOR_SEL_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPH_MONITOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG0_REG < 2'b00) || (TXPI_CFG0_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG1_REG < 2'b00) || (TXPI_CFG1_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG2_REG < 2'b00) || (TXPI_CFG2_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG3_REG < 1'b0) || (TXPI_CFG3_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG3 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG4_REG < 1'b0) || (TXPI_CFG4_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG4 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((TXPI_CFG5_REG < 3'b000) || (TXPI_CFG5_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TXPI_CFG5 on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((TXPI_GRAY_SEL_REG < 1'b0) || (TXPI_GRAY_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_GRAY_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_GRAY_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_INVSTROBE_SEL_REG < 1'b0) || (TXPI_INVSTROBE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_INVSTROBE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_INVSTROBE_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_LPM_REG < 1'b0) || (TXPI_LPM_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_LPM on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_LPM_REG);
attr_err = 1'b1;
end
if ((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK")) begin
$display("Attribute Syntax Error : The attribute TXPI_PPMCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK.", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((TXPI_PPM_CFG_REG < 8'b00000000) || (TXPI_PPM_CFG_REG > 8'b11111111)) begin
$display("Attribute Syntax Error : The attribute TXPI_PPM_CFG on %s instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", MODULE_NAME, TXPI_PPM_CFG_REG);
attr_err = 1'b1;
end
if ((TXPI_SYNFREQ_PPM_REG < 3'b000) || (TXPI_SYNFREQ_PPM_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TXPI_SYNFREQ_PPM on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TXPI_SYNFREQ_PPM_REG);
attr_err = 1'b1;
end
if ((TXPI_VREFSEL_REG < 1'b0) || (TXPI_VREFSEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXPI_VREFSEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((TXPMARESET_TIME_REG < 5'b00000) || (TXPMARESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TXPMARESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((TXSYNC_MULTILANE_REG < 1'b0) || (TXSYNC_MULTILANE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_MULTILANE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((TXSYNC_OVRD_REG < 1'b0) || (TXSYNC_OVRD_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_OVRD on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((TXSYNC_SKIP_DA_REG < 1'b0) || (TXSYNC_SKIP_DA_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TXSYNC_SKIP_DA on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32)) begin
$display("Attribute Syntax Error : The attribute TX_CLK25_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 32.", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((TX_CLKMUX_EN_REG < 1'b0) || (TX_CLKMUX_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_CLKMUX_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((TX_CLKREG_PDB_REG < 1'b0) || (TX_CLKREG_PDB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_CLKREG_PDB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_CLKREG_PDB_REG);
attr_err = 1'b1;
end
if ((TX_CLKREG_SET_REG < 3'b000) || (TX_CLKREG_SET_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_CLKREG_SET on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_CLKREG_SET_REG);
attr_err = 1'b1;
end
if ((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160)) begin
$display("Attribute Syntax Error : The attribute TX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, TX_DATA_WIDTH_REG, 20);
attr_err = 1'b1;
end
if ((TX_DCD_CFG_REG < 6'b000000) || (TX_DCD_CFG_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DCD_CFG on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DCD_CFG_REG);
attr_err = 1'b1;
end
if ((TX_DCD_EN_REG < 1'b0) || (TX_DCD_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_DCD_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_DCD_EN_REG);
attr_err = 1'b1;
end
if ((TX_DEEMPH0_REG < 6'b000000) || (TX_DEEMPH0_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DEEMPH0 on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DEEMPH0_REG);
attr_err = 1'b1;
end
if ((TX_DEEMPH1_REG < 6'b000000) || (TX_DEEMPH1_REG > 6'b111111)) begin
$display("Attribute Syntax Error : The attribute TX_DEEMPH1 on %s instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", MODULE_NAME, TX_DEEMPH1_REG);
attr_err = 1'b1;
end
if ((TX_DIVRESET_TIME_REG < 5'b00000) || (TX_DIVRESET_TIME_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute TX_DIVRESET_TIME on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, TX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3")) begin
$display("Attribute Syntax Error : The attribute TX_DRIVE_MODE on %s instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3.", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((TX_DRVMUX_CTRL_REG < 2'b00) || (TX_DRVMUX_CTRL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TX_DRVMUX_CTRL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TX_DRVMUX_CTRL_REG);
attr_err = 1'b1;
end
if ((TX_EIDLE_ASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_ASSERT_DELAY_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_EIDLE_ASSERT_DELAY on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_EIDLE_ASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((TX_EIDLE_DEASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_DEASSERT_DELAY_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_EIDLE_DEASSERT_DELAY on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_EIDLE_DEASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((TX_EML_PHI_TUNE_REG < 1'b0) || (TX_EML_PHI_TUNE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_EML_PHI_TUNE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_EML_PHI_TUNE_REG);
attr_err = 1'b1;
end
if ((TX_FABINT_USRCLK_FLOP_REG < 1'b0) || (TX_FABINT_USRCLK_FLOP_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_FABINT_USRCLK_FLOP on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((TX_FIFO_BYP_EN_REG < 1'b0) || (TX_FIFO_BYP_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_FIFO_BYP_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_FIFO_BYP_EN_REG);
attr_err = 1'b1;
end
if ((TX_IDLE_DATA_ZERO_REG < 1'b0) || (TX_IDLE_DATA_ZERO_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_IDLE_DATA_ZERO on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_IDLE_DATA_ZERO_REG);
attr_err = 1'b1;
end
if ((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2)) begin
$display("Attribute Syntax Error : The attribute TX_INT_DATAWIDTH on %s instance %m is set to %d. Legal values for this attribute are 0 to 2.", MODULE_NAME, TX_INT_DATAWIDTH_REG, 1);
attr_err = 1'b1;
end
if ((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TX_LOOPBACK_DRIVE_HIZ on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((TX_MAINCURSOR_SEL_REG < 1'b0) || (TX_MAINCURSOR_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_MAINCURSOR_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_MAINCURSOR_SEL_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_0_REG < 7'b0000000) || (TX_MARGIN_FULL_0_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_0 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_0_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_1_REG < 7'b0000000) || (TX_MARGIN_FULL_1_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_1 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_1_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_2_REG < 7'b0000000) || (TX_MARGIN_FULL_2_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_2 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_2_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_3_REG < 7'b0000000) || (TX_MARGIN_FULL_3_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_3 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_3_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_FULL_4_REG < 7'b0000000) || (TX_MARGIN_FULL_4_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_FULL_4 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_FULL_4_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_0_REG < 7'b0000000) || (TX_MARGIN_LOW_0_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_0 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_0_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_1_REG < 7'b0000000) || (TX_MARGIN_LOW_1_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_1 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_1_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_2_REG < 7'b0000000) || (TX_MARGIN_LOW_2_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_2 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_2_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_3_REG < 7'b0000000) || (TX_MARGIN_LOW_3_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_3 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_3_REG);
attr_err = 1'b1;
end
if ((TX_MARGIN_LOW_4_REG < 7'b0000000) || (TX_MARGIN_LOW_4_REG > 7'b1111111)) begin
$display("Attribute Syntax Error : The attribute TX_MARGIN_LOW_4 on %s instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", MODULE_NAME, TX_MARGIN_LOW_4_REG);
attr_err = 1'b1;
end
if ((TX_MODE_SEL_REG < 3'b000) || (TX_MODE_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_MODE_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_MODE_SEL_REG);
attr_err = 1'b1;
end
if ((TX_PI_BIASSET_REG < 2'b00) || (TX_PI_BIASSET_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TX_PI_BIASSET on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TX_PI_BIASSET_REG);
attr_err = 1'b1;
end
if ((TX_PI_DIV2_MODE_B_REG < 1'b0) || (TX_PI_DIV2_MODE_B_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PI_DIV2_MODE_B on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PI_DIV2_MODE_B_REG);
attr_err = 1'b1;
end
if ((TX_PI_SEL_QPLL0_REG < 1'b0) || (TX_PI_SEL_QPLL0_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PI_SEL_QPLL0 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PI_SEL_QPLL0_REG);
attr_err = 1'b1;
end
if ((TX_PI_SEL_QPLL1_REG < 1'b0) || (TX_PI_SEL_QPLL1_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PI_SEL_QPLL1 on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PI_SEL_QPLL1_REG);
attr_err = 1'b1;
end
if ((TX_PMADATA_OPT_REG < 1'b0) || (TX_PMADATA_OPT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PMADATA_OPT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PMADATA_OPT_REG);
attr_err = 1'b1;
end
if ((TX_PMA_POWER_SAVE_REG < 1'b0) || (TX_PMA_POWER_SAVE_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_PMA_POWER_SAVE on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((TX_PREDRV_CTRL_REG < 2'b00) || (TX_PREDRV_CTRL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute TX_PREDRV_CTRL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, TX_PREDRV_CTRL_REG);
attr_err = 1'b1;
end
if ((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI")) begin
$display("Attribute Syntax Error : The attribute TX_PROGCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI.", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((TX_PROGDIV_CFG_REG/1000.0 != 0.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 4.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 5.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 8.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 10.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 16.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 16.5) &&
(TX_PROGDIV_CFG_REG/1000.0 != 20.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 32.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 33.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 40.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 64.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 66.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 80.0) &&
(TX_PROGDIV_CFG_REG/1000.0 != 100.0)) begin
$display("Attribute Syntax Error : The attribute TX_PROGDIV_CFG on %s instance %m is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0.", MODULE_NAME, TX_PROGDIV_CFG_REG/1000.0);
attr_err = 1'b1;
end
if ((TX_RXDETECT_REF_REG < 3'b000) || (TX_RXDETECT_REF_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_RXDETECT_REF on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((TX_SAMPLE_PERIOD_REG < 3'b000) || (TX_SAMPLE_PERIOD_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute TX_SAMPLE_PERIOD on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, TX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((TX_SARC_LPBK_ENB_REG < 1'b0) || (TX_SARC_LPBK_ENB_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute TX_SARC_LPBK_ENB on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, TX_SARC_LPBK_ENB_REG);
attr_err = 1'b1;
end
if ((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR")) begin
$display("Attribute Syntax Error : The attribute TX_XCLK_SEL on %s instance %m is set to %s. Legal values for this attribute are TXOUT or TXUSR.", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((USE_PCS_CLK_PHASE_SEL_REG < 1'b0) || (USE_PCS_CLK_PHASE_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute USE_PCS_CLK_PHASE_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, USE_PCS_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 12'b111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTYE3_CHANNEL SIP_GTYE3_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.ADAPT_CFG2 (ADAPT_CFG2_REG),
.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_ELPCAL (AEN_ELPCAL_REG),
.AEN_EYESCAN (AEN_EYESCAN_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_MUXDCD (AEN_MUXDCD_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.AUTO_BW_SEL_BYPASS (AUTO_BW_SEL_BYPASS_REG),
.A_AFECFOKEN (A_AFECFOKEN_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG),
.A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG),
.A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG),
.A_DFECFOKHOLD (A_DFECFOKHOLD_REG),
.A_DFECFOKOVREN (A_DFECFOKOVREN_REG),
.A_ELPCALDVORWREN (A_ELPCALDVORWREN_REG),
.A_ELPCALPAORWREN (A_ELPCALPAORWREN_REG),
.A_EYESCANMODE (A_EYESCANMODE_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_LPMGCHOLD (A_LPMGCHOLD_REG),
.A_LPMGCOVREN (A_LPMGCOVREN_REG),
.A_LPMOSHOLD (A_LPMOSHOLD_REG),
.A_LPMOSOVREN (A_LPMOSOVREN_REG),
.A_MUXDCDEXHOLD (A_MUXDCDEXHOLD_REG),
.A_MUXDCDORWREN (A_MUXDCDORWREN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG),
.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG),
.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG),
.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG),
.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG),
.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG),
.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG),
.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEVSEN (A_RXDFEVSEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.CAPBYPASS_FORCE (CAPBYPASS_FORCE_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CH_HSPMUX (CH_HSPMUX_REG),
.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG),
.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG),
.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG),
.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG),
.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG),
.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG),
.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG),
.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG),
.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG),
.CKCAL_RSVD0 (CKCAL_RSVD0_REG),
.CKCAL_RSVD1 (CKCAL_RSVD1_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG),
.CPLL_IPS_EN (CPLL_IPS_EN_REG),
.CPLL_IPS_REFCLK_SEL (CPLL_IPS_REFCLK_SEL_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG),
.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG),
.DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PMA_CFG (ES_PMA_CFG_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUALIFIER5 (ES_QUALIFIER5_REG),
.ES_QUALIFIER6 (ES_QUALIFIER6_REG),
.ES_QUALIFIER7 (ES_QUALIFIER7_REG),
.ES_QUALIFIER8 (ES_QUALIFIER8_REG),
.ES_QUALIFIER9 (ES_QUALIFIER9_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG),
.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG),
.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG),
.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG),
.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG),
.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG),
.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG),
.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG),
.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG),
.EVODD_PHI_CFG (EVODD_PHI_CFG_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GM_BIAS_SELECT (GM_BIAS_SELECT_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.LOOP0_CFG (LOOP0_CFG_REG),
.LOOP10_CFG (LOOP10_CFG_REG),
.LOOP11_CFG (LOOP11_CFG_REG),
.LOOP12_CFG (LOOP12_CFG_REG),
.LOOP13_CFG (LOOP13_CFG_REG),
.LOOP1_CFG (LOOP1_CFG_REG),
.LOOP2_CFG (LOOP2_CFG_REG),
.LOOP3_CFG (LOOP3_CFG_REG),
.LOOP4_CFG (LOOP4_CFG_REG),
.LOOP5_CFG (LOOP5_CFG_REG),
.LOOP6_CFG (LOOP6_CFG_REG),
.LOOP7_CFG (LOOP7_CFG_REG),
.LOOP8_CFG (LOOP8_CFG_REG),
.LOOP9_CFG (LOOP9_CFG_REG),
.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG),
.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG),
.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG),
.LPBK_RG_CTRL (LPBK_RG_CTRL_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PCS_RSVD1 (PCS_RSVD1_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG),
.PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG),
.PMA_RSV0 (PMA_RSV0_REG),
.PMA_RSV1 (PMA_RSV1_REG),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOKDONE_SRC (RXCFOKDONE_SRC_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_PWR_SAVING (RXDFE_PWR_SAVING_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_AUTO_BW_SEL_BYPASS (RXPI_AUTO_BW_SEL_BYPASS_REG),
.RXPI_CFG (RXPI_CFG_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_RSV0 (RXPI_RSV0_REG),
.RXPI_SEL_LC (RXPI_SEL_LC_REG),
.RXPI_STARTCODE (RXPI_STARTCODE_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPLL_SEL (RXPLL_SEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE1_KHKL (RX_CTLE1_KHKL_REG),
.RX_CTLE2_KHKL (RX_CTLE2_KHKL_REG),
.RX_CTLE3_AGC (RX_CTLE3_AGC_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIV2_MODE_B (RX_DIV2_MODE_B_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EXT_RL_CTRL (RX_EXT_RL_CTRL_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_REG),
.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG),
.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG),
.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_VREG_CTRL (RX_VREG_CTRL_REG),
.RX_VREG_PDB (RX_VREG_PDB_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.RX_XMODE_SEL (RX_XMODE_SEL_REG),
.SAS_MAX_COM (SAS_MAX_COM_REG),
.SAS_MIN_COM (SAS_MIN_COM_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SATA_MAX_BURST (SATA_MAX_BURST_REG),
.SATA_MAX_INIT (SATA_MAX_INIT_REG),
.SATA_MAX_WAKE (SATA_MAX_WAKE_REG),
.SATA_MIN_BURST (SATA_MIN_BURST_REG),
.SATA_MIN_INIT (SATA_MIN_INIT_REG),
.SATA_MIN_WAKE (SATA_MIN_WAKE_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATURE_PAR (TEMPERATURE_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_CFG2 (TXPH_CFG2_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_RSV0 (TXPI_RSV0_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_CLKREG_PDB (TX_CLKREG_PDB_REG),
.TX_CLKREG_SET (TX_CLKREG_SET_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCD_CFG (TX_DCD_CFG_REG),
.TX_DCD_EN (TX_DCD_EN_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_DRVMUX_CTRL (TX_DRVMUX_CTRL_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_MODE_SEL (TX_MODE_SEL_REG),
.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG),
.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG),
.TX_PHICAL_CFG2 (TX_PHICAL_CFG2_REG),
.TX_PI_BIASSET (TX_PI_BIASSET_REG),
.TX_PI_CFG0 (TX_PI_CFG0_REG),
.TX_PI_CFG1 (TX_PI_CFG1_REG),
.TX_PI_DIV2_MODE_B (TX_PI_DIV2_MODE_B_REG),
.TX_PI_SEL_QPLL0 (TX_PI_SEL_QPLL0_REG),
.TX_PI_SEL_QPLL1 (TX_PI_SEL_QPLL1_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PREDRV_CTRL (TX_PREDRV_CTRL_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_REG),
.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG),
.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG),
.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG),
.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.DMONITOROUT (DMONITOROUT_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.GTYTXN (GTYTXN_out),
.GTYTXP (GTYTXP_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCKOKDONE (RXCKOKDONE_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDCCDONE (TXDCCDONE_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.CDRSTEPDIR (CDRSTEPDIR_in),
.CDRSTEPSQ (CDRSTEPSQ_in),
.CDRSTEPSX (CDRSTEPSX_in),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.ELPCALDVORWREN (ELPCALDVORWREN_in),
.ELPCALPAORWREN (ELPCALPAORWREN_in),
.EVODDPHICALDONE (EVODDPHICALDONE_in),
.EVODDPHICALSTART (EVODDPHICALSTART_in),
.EVODDPHIDRDEN (EVODDPHIDRDEN_in),
.EVODDPHIDWREN (EVODDPHIDWREN_in),
.EVODDPHIXRDEN (EVODDPHIXRDEN_in),
.EVODDPHIXWREN (EVODDPHIXWREN_in),
.EYESCANMODE (EYESCANMODE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.GTGREFCLK (GTGREFCLK_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRESETSEL (GTRESETSEL_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.GTYRXN (GTYRXN_in),
.GTYRXP (GTYRXP_in),
.LOOPBACK (LOOPBACK_in),
.LOOPRSVD (LOOPRSVD_in),
.LPBKRXTXSEREN (LPBKRXTXSEREN_in),
.LPBKTXRXSEREN (LPBKTXRXSEREN_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PCSRSVDIN2 (PCSRSVDIN2_in),
.PMARSVDIN (PMARSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RSTCLKENTX (RSTCLKENTX_in),
.RX8B10BEN (RX8B10BEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCDRRESETRSV (RXCDRRESETRSV_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCKOKRESET (RXCKOKRESET_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDCCFORCESTART (RXDCCFORCESTART_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEVSEN (RXDFEVSEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSINTCFG (RXOSINTCFG_in),
.RXOSINTEN (RXOSINTEN_in),
.RXOSINTHOLD (RXOSINTHOLD_in),
.RXOSINTOVRDEN (RXOSINTOVRDEN_in),
.RXOSINTSTROBE (RXOSINTSTROBE_in),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDCCFORCESTART (TXDCCFORCESTART_in),
.TXDCCRESET (TXDCCRESET_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDIFFPD (TXDIFFPD_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXELFORCESTART (TXELFORCESTART_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/GTYE3_COMMON.v 0000664 0000000 0000000 00000127650 12327044266 0023340 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTYE3_COMMON.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTYE3_COMMON #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000,
parameter [8:0] A_SDM1DATA1_1 = 9'b000000000,
parameter [15:0] BIAS_CFG0 = 16'h0000,
parameter [15:0] BIAS_CFG1 = 16'h0000,
parameter [15:0] BIAS_CFG2 = 16'h0000,
parameter [15:0] BIAS_CFG3 = 16'h0000,
parameter [15:0] BIAS_CFG4 = 16'h0000,
parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000,
parameter [15:0] COMMON_CFG0 = 16'h0000,
parameter [15:0] COMMON_CFG1 = 16'h0000,
parameter [15:0] POR_CFG = 16'h0004,
parameter [15:0] PPF0_CFG = 16'h0FFF,
parameter [15:0] PPF1_CFG = 16'h0FFF,
parameter QPLL0CLKOUT_RATE = "FULL",
parameter [15:0] QPLL0_CFG0 = 16'h301C,
parameter [15:0] QPLL0_CFG1 = 16'h0000,
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL0_CFG2 = 16'h0780,
parameter [15:0] QPLL0_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL0_CFG3 = 16'h0120,
parameter [15:0] QPLL0_CFG4 = 16'h0021,
parameter [9:0] QPLL0_CP = 10'b0000011111,
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111,
parameter integer QPLL0_FBDIV = 66,
parameter integer QPLL0_FBDIV_G3 = 80,
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL0_LOCK_CFG = 16'h21E8,
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL0_LPF = 10'b1111111111,
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111,
parameter integer QPLL0_REFCLK_DIV = 2,
parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000001000000,
parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000,
parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000,
parameter QPLL1CLKOUT_RATE = "FULL",
parameter [15:0] QPLL1_CFG0 = 16'h301C,
parameter [15:0] QPLL1_CFG1 = 16'h0000,
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL1_CFG2 = 16'h0780,
parameter [15:0] QPLL1_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL1_CFG3 = 16'h0120,
parameter [15:0] QPLL1_CFG4 = 16'h0021,
parameter [9:0] QPLL1_CP = 10'b0000011111,
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111,
parameter integer QPLL1_FBDIV = 66,
parameter integer QPLL1_FBDIV_G3 = 80,
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL1_LOCK_CFG = 16'h21E8,
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL1_LPF = 10'b1111111111,
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111,
parameter integer QPLL1_REFCLK_DIV = 2,
parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000001000000,
parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000,
parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000,
parameter [15:0] RSVD_ATTR0 = 16'h0000,
parameter [15:0] RSVD_ATTR1 = 16'h0000,
parameter [15:0] RSVD_ATTR2 = 16'h0000,
parameter [15:0] RSVD_ATTR3 = 16'h0000,
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00,
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00,
parameter [0:0] SARC_EN = 1'b1,
parameter [0:0] SARC_SEL = 1'b0,
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000,
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000,
parameter [2:0] SIM_QPLL0REFCLK_SEL = 3'b001,
parameter [2:0] SIM_QPLL1REFCLK_SEL = 3'b001,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter SIM_VERSION = "Ver_1"
)(
output [15:0] DRPDO,
output DRPRDY,
output [7:0] PMARSVDOUT0,
output [7:0] PMARSVDOUT1,
output QPLL0FBCLKLOST,
output QPLL0LOCK,
output QPLL0OUTCLK,
output QPLL0OUTREFCLK,
output QPLL0REFCLKLOST,
output QPLL1FBCLKLOST,
output QPLL1LOCK,
output QPLL1OUTCLK,
output QPLL1OUTREFCLK,
output QPLL1REFCLKLOST,
output [7:0] QPLLDMONITOR0,
output [7:0] QPLLDMONITOR1,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [1:0] RXRECCLK0_SEL,
output [1:0] RXRECCLK1_SEL,
output [3:0] SDM0FINALOUT,
output [14:0] SDM0TESTDATA,
output [3:0] SDM1FINALOUT,
output [14:0] SDM1TESTDATA,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input [4:0] BGRCALOVRD,
input BGRCALOVRDENB,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input GTGREFCLK0,
input GTGREFCLK1,
input GTNORTHREFCLK00,
input GTNORTHREFCLK01,
input GTNORTHREFCLK10,
input GTNORTHREFCLK11,
input GTREFCLK00,
input GTREFCLK01,
input GTREFCLK10,
input GTREFCLK11,
input GTSOUTHREFCLK00,
input GTSOUTHREFCLK01,
input GTSOUTHREFCLK10,
input GTSOUTHREFCLK11,
input [7:0] PMARSVD0,
input [7:0] PMARSVD1,
input QPLL0CLKRSVD0,
input QPLL0LOCKDETCLK,
input QPLL0LOCKEN,
input QPLL0PD,
input [2:0] QPLL0REFCLKSEL,
input QPLL0RESET,
input QPLL1CLKRSVD0,
input QPLL1LOCKDETCLK,
input QPLL1LOCKEN,
input QPLL1PD,
input [2:0] QPLL1REFCLKSEL,
input QPLL1RESET,
input [7:0] QPLLRSVD1,
input [4:0] QPLLRSVD2,
input [4:0] QPLLRSVD3,
input [7:0] QPLLRSVD4,
input RCALENB,
input [24:0] SDM0DATA,
input SDM0RESET,
input [1:0] SDM0WIDTH,
input [24:0] SDM1DATA,
input SDM1RESET,
input [1:0] SDM1WIDTH
);
// define constants
localparam MODULE_NAME = "GTYE3_COMMON";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [15:0] A_SDM1DATA1_0_REG = A_SDM1DATA1_0;
localparam [8:0] A_SDM1DATA1_1_REG = A_SDM1DATA1_1;
localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0;
localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1;
localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2;
localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3;
localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4;
localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD;
localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0;
localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1;
localparam [15:0] POR_CFG_REG = POR_CFG;
localparam [15:0] PPF0_CFG_REG = PPF0_CFG;
localparam [15:0] PPF1_CFG_REG = PPF1_CFG;
localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE;
localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0;
localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1;
localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3;
localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2;
localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3;
localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3;
localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4;
localparam [9:0] QPLL0_CP_REG = QPLL0_CP;
localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3;
localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV;
localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3;
localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0;
localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1;
localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG;
localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3;
localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF;
localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3;
localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV;
localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0;
localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1;
localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2;
localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE;
localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0;
localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1;
localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3;
localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2;
localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3;
localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3;
localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4;
localparam [9:0] QPLL1_CP_REG = QPLL1_CP;
localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3;
localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV;
localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3;
localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0;
localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1;
localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG;
localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3;
localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF;
localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3;
localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV;
localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0;
localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1;
localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2;
localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0;
localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1;
localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2;
localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3;
localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL;
localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL;
localparam [0:0] SARC_EN_REG = SARC_EN;
localparam [0:0] SARC_SEL_REG = SARC_SEL;
localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0;
localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1;
localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0;
localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1;
localparam [2:0] SIM_QPLL0REFCLK_SEL_REG = SIM_QPLL0REFCLK_SEL;
localparam [2:0] SIM_QPLL1REFCLK_SEL_REG = SIM_QPLL1REFCLK_SEL;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
`endif
localparam [0:0] AEN_BGBS0_REG = 1'b0;
localparam [0:0] AEN_BGBS1_REG = 1'b0;
localparam [0:0] AEN_MASTER0_REG = 1'b0;
localparam [0:0] AEN_MASTER1_REG = 1'b0;
localparam [0:0] AEN_PD0_REG = 1'b0;
localparam [0:0] AEN_PD1_REG = 1'b0;
localparam [0:0] AEN_QPLL0_REG = 1'b0;
localparam [0:0] AEN_QPLL1_REG = 1'b0;
localparam [0:0] AEN_REFCLK0_REG = 1'b0;
localparam [0:0] AEN_REFCLK1_REG = 1'b0;
localparam [0:0] AEN_RESET0_REG = 1'b0;
localparam [0:0] AEN_RESET1_REG = 1'b0;
localparam [0:0] AEN_SDMDATA0_REG = 1'b0;
localparam [0:0] AEN_SDMDATA1_REG = 1'b0;
localparam [0:0] AEN_SDMRESET0_REG = 1'b0;
localparam [0:0] AEN_SDMRESET1_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH0_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH1_REG = 1'b0;
localparam [3:0] AQDMUXSEL1_REG = 4'b0000;
localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000;
localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000;
localparam [0:0] A_BGMONITOREN_REG = 1'b0;
localparam [0:0] A_BGPD_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD0_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD1_REG = 1'b0;
localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL0PD_REG = 1'b0;
localparam [0:0] A_QPLL0RESET_REG = 1'b0;
localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL1PD_REG = 1'b0;
localparam [0:0] A_QPLL1RESET_REG = 1'b0;
localparam [15:0] A_SDM0DATA1_0_REG = 16'b0000000000000000;
localparam [8:0] A_SDM0DATA1_1_REG = 9'b000000000;
localparam [0:0] A_SDMRESET0_REG = 1'b0;
localparam [0:0] A_SDMRESET1_REG = 1'b0;
localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00;
localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00;
localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1;
localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] QPLL0_IPS_EN_REG = 1'b1;
localparam [2:0] QPLL0_IPS_REFCLK_SEL_REG = 3'b000;
localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] QPLL1_IPS_EN_REG = 1'b1;
localparam [2:0] QPLL1_IPS_REFCLK_SEL_REG = 3'b000;
localparam [0:0] RCALSAP_TESTEN_REG = 1'b0;
localparam [0:0] RCAL_APROBE_REG = 1'b0;
localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0;
localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0;
localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTYE3_COMMON_dr.v"
`endif
wire DRPRDY_out;
wire QPLL0FBCLKLOST_out;
wire QPLL0LOCK_out;
wire QPLL0OUTCLK_out;
wire QPLL0OUTREFCLK_out;
wire QPLL0REFCLKLOST_out;
wire QPLL1FBCLKLOST_out;
wire QPLL1LOCK_out;
wire QPLL1OUTCLK_out;
wire QPLL1OUTREFCLK_out;
wire QPLL1REFCLKLOST_out;
wire REFCLKOUTMONITOR0_out;
wire REFCLKOUTMONITOR1_out;
wire [14:0] SDM0TESTDATA_out;
wire [14:0] SDM1TESTDATA_out;
wire [15:0] DRPDO_out;
wire [1:0] RXRECCLK0_SEL_out;
wire [1:0] RXRECCLK1_SEL_out;
wire [3:0] SARCCLK_out;
wire [3:0] SDM0FINALOUT_out;
wire [3:0] SDM1FINALOUT_out;
wire [7:0] PMARSVDOUT0_out;
wire [7:0] PMARSVDOUT1_out;
wire [7:0] PMASCANOUT_out;
wire [7:0] QPLLDMONITOR0_out;
wire [7:0] QPLLDMONITOR1_out;
wire DRPRDY_delay;
wire QPLL0FBCLKLOST_delay;
wire QPLL0LOCK_delay;
wire QPLL0OUTCLK_delay;
wire QPLL0OUTREFCLK_delay;
wire QPLL0REFCLKLOST_delay;
wire QPLL1FBCLKLOST_delay;
wire QPLL1LOCK_delay;
wire QPLL1OUTCLK_delay;
wire QPLL1OUTREFCLK_delay;
wire QPLL1REFCLKLOST_delay;
wire REFCLKOUTMONITOR0_delay;
wire REFCLKOUTMONITOR1_delay;
wire [14:0] SDM0TESTDATA_delay;
wire [14:0] SDM1TESTDATA_delay;
wire [15:0] DRPDO_delay;
wire [1:0] RXRECCLK0_SEL_delay;
wire [1:0] RXRECCLK1_SEL_delay;
wire [3:0] SDM0FINALOUT_delay;
wire [3:0] SDM1FINALOUT_delay;
wire [7:0] PMARSVDOUT0_delay;
wire [7:0] PMARSVDOUT1_delay;
wire [7:0] QPLLDMONITOR0_delay;
wire [7:0] QPLLDMONITOR1_delay;
wire BGBYPASSB_in;
wire BGMONITORENB_in;
wire BGPDB_in;
wire BGRCALOVRDENB_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire GTGREFCLK0_in;
wire GTGREFCLK1_in;
wire GTNORTHREFCLK00_in;
wire GTNORTHREFCLK01_in;
wire GTNORTHREFCLK10_in;
wire GTNORTHREFCLK11_in;
wire GTREFCLK00_in;
wire GTREFCLK01_in;
wire GTREFCLK10_in;
wire GTREFCLK11_in;
wire GTSOUTHREFCLK00_in;
wire GTSOUTHREFCLK01_in;
wire GTSOUTHREFCLK10_in;
wire GTSOUTHREFCLK11_in;
wire PMASCANENB_in;
wire QDPMASCANMODEB_in;
wire QDPMASCANRSTEN_in;
wire QPLL0CLKRSVD0_in;
wire QPLL0LOCKDETCLK_in;
wire QPLL0LOCKEN_in;
wire QPLL0PD_in;
wire QPLL0RESET_in;
wire QPLL1CLKRSVD0_in;
wire QPLL1LOCKDETCLK_in;
wire QPLL1LOCKEN_in;
wire QPLL1PD_in;
wire QPLL1RESET_in;
wire RCALENB_in;
wire SDM0RESET_in;
wire SDM1RESET_in;
wire [15:0] DRPDI_in;
wire [1:0] SDM0WIDTH_in;
wire [1:0] SDM1WIDTH_in;
wire [24:0] SDM0DATA_in;
wire [24:0] SDM1DATA_in;
wire [2:0] QPLL0REFCLKSEL_in;
wire [2:0] QPLL1REFCLKSEL_in;
wire [3:0] RXRECCLK_in;
wire [4:0] BGRCALOVRD_in;
wire [4:0] QPLLRSVD2_in;
wire [4:0] QPLLRSVD3_in;
wire [7:0] PMARSVD0_in;
wire [7:0] PMARSVD1_in;
wire [7:0] PMASCANCLK_in;
wire [7:0] PMASCANIN_in;
wire [7:0] QPLLRSVD1_in;
wire [7:0] QPLLRSVD4_in;
wire [9:0] DRPADDR_in;
wire BGBYPASSB_delay;
wire BGMONITORENB_delay;
wire BGPDB_delay;
wire BGRCALOVRDENB_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire GTGREFCLK0_delay;
wire GTGREFCLK1_delay;
wire GTNORTHREFCLK00_delay;
wire GTNORTHREFCLK01_delay;
wire GTNORTHREFCLK10_delay;
wire GTNORTHREFCLK11_delay;
wire GTREFCLK00_delay;
wire GTREFCLK01_delay;
wire GTREFCLK10_delay;
wire GTREFCLK11_delay;
wire GTSOUTHREFCLK00_delay;
wire GTSOUTHREFCLK01_delay;
wire GTSOUTHREFCLK10_delay;
wire GTSOUTHREFCLK11_delay;
wire QPLL0CLKRSVD0_delay;
wire QPLL0LOCKDETCLK_delay;
wire QPLL0LOCKEN_delay;
wire QPLL0PD_delay;
wire QPLL0RESET_delay;
wire QPLL1CLKRSVD0_delay;
wire QPLL1LOCKDETCLK_delay;
wire QPLL1LOCKEN_delay;
wire QPLL1PD_delay;
wire QPLL1RESET_delay;
wire RCALENB_delay;
wire SDM0RESET_delay;
wire SDM1RESET_delay;
wire [15:0] DRPDI_delay;
wire [1:0] SDM0WIDTH_delay;
wire [1:0] SDM1WIDTH_delay;
wire [24:0] SDM0DATA_delay;
wire [24:0] SDM1DATA_delay;
wire [2:0] QPLL0REFCLKSEL_delay;
wire [2:0] QPLL1REFCLKSEL_delay;
wire [4:0] BGRCALOVRD_delay;
wire [4:0] QPLLRSVD2_delay;
wire [4:0] QPLLRSVD3_delay;
wire [7:0] PMARSVD0_delay;
wire [7:0] PMARSVD1_delay;
wire [7:0] QPLLRSVD1_delay;
wire [7:0] QPLLRSVD4_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay;
assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay;
assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay;
assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay;
assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay;
assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay;
assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay;
assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay;
assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay;
assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay;
assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay;
assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay;
assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay;
assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay;
assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay;
assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay;
assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay;
assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay;
assign #(out_delay) SDM0FINALOUT = SDM0FINALOUT_delay;
assign #(out_delay) SDM0TESTDATA = SDM0TESTDATA_delay;
assign #(out_delay) SDM1FINALOUT = SDM1FINALOUT_delay;
assign #(out_delay) SDM1TESTDATA = SDM1TESTDATA_delay;
// inputs with no timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0;
assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1;
assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00;
assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01;
assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10;
assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11;
assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00;
assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01;
assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10;
assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11;
assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00;
assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01;
assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10;
assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11;
assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0;
assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK;
assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0;
assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK;
assign #(in_delay) BGBYPASSB_delay = BGBYPASSB;
assign #(in_delay) BGMONITORENB_delay = BGMONITORENB;
assign #(in_delay) BGPDB_delay = BGPDB;
assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB;
assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) PMARSVD0_delay = PMARSVD0;
assign #(in_delay) PMARSVD1_delay = PMARSVD1;
assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN;
assign #(in_delay) QPLL0PD_delay = QPLL0PD;
assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL;
assign #(in_delay) QPLL0RESET_delay = QPLL0RESET;
assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN;
assign #(in_delay) QPLL1PD_delay = QPLL1PD;
assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL;
assign #(in_delay) QPLL1RESET_delay = QPLL1RESET;
assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1;
assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2;
assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3;
assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4;
assign #(in_delay) RCALENB_delay = RCALENB;
assign #(in_delay) SDM0DATA_delay = SDM0DATA;
assign #(in_delay) SDM0RESET_delay = SDM0RESET;
assign #(in_delay) SDM0WIDTH_delay = SDM0WIDTH;
assign #(in_delay) SDM1DATA_delay = SDM1DATA;
assign #(in_delay) SDM1RESET_delay = SDM1RESET;
assign #(in_delay) SDM1WIDTH_delay = SDM1WIDTH;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign PMARSVDOUT0_delay = PMARSVDOUT0_out;
assign PMARSVDOUT1_delay = PMARSVDOUT1_out;
assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out;
assign QPLL0LOCK_delay = QPLL0LOCK_out;
assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out;
assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out;
assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out;
assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out;
assign QPLL1LOCK_delay = QPLL1LOCK_out;
assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out;
assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out;
assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out;
assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out;
assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out;
assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out;
assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out;
assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out;
assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out;
assign SDM0FINALOUT_delay = SDM0FINALOUT_out;
assign SDM0TESTDATA_delay = SDM0TESTDATA_out;
assign SDM1FINALOUT_delay = SDM1FINALOUT_out;
assign SDM1TESTDATA_delay = SDM1TESTDATA_out;
assign BGBYPASSB_in = BGBYPASSB_delay;
assign BGMONITORENB_in = BGMONITORENB_delay;
assign BGPDB_in = BGPDB_delay;
assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay;
assign BGRCALOVRD_in = BGRCALOVRD_delay;
assign DRPADDR_in = DRPADDR_delay;
assign DRPCLK_in = DRPCLK_delay;
assign DRPDI_in = DRPDI_delay;
assign DRPEN_in = DRPEN_delay;
assign DRPWE_in = DRPWE_delay;
assign GTGREFCLK0_in = GTGREFCLK0_delay;
assign GTGREFCLK1_in = GTGREFCLK1_delay;
assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay;
assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay;
assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay;
assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay;
assign GTREFCLK00_in = GTREFCLK00_delay;
assign GTREFCLK01_in = GTREFCLK01_delay;
assign GTREFCLK10_in = GTREFCLK10_delay;
assign GTREFCLK11_in = GTREFCLK11_delay;
assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay;
assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay;
assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay;
assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay;
assign PMARSVD0_in = PMARSVD0_delay;
assign PMARSVD1_in = PMARSVD1_delay;
assign QPLL0CLKRSVD0_in = QPLL0CLKRSVD0_delay;
assign QPLL0LOCKDETCLK_in = QPLL0LOCKDETCLK_delay;
assign QPLL0LOCKEN_in = QPLL0LOCKEN_delay;
assign QPLL0PD_in = QPLL0PD_delay;
assign QPLL0REFCLKSEL_in = QPLL0REFCLKSEL_delay;
assign QPLL0RESET_in = QPLL0RESET_delay;
assign QPLL1CLKRSVD0_in = QPLL1CLKRSVD0_delay;
assign QPLL1LOCKDETCLK_in = QPLL1LOCKDETCLK_delay;
assign QPLL1LOCKEN_in = QPLL1LOCKEN_delay;
assign QPLL1PD_in = QPLL1PD_delay;
assign QPLL1REFCLKSEL_in = QPLL1REFCLKSEL_delay;
assign QPLL1RESET_in = QPLL1RESET_delay;
assign QPLLRSVD1_in = QPLLRSVD1_delay;
assign QPLLRSVD2_in = QPLLRSVD2_delay;
assign QPLLRSVD3_in = QPLLRSVD3_delay;
assign QPLLRSVD4_in = QPLLRSVD4_delay;
assign RCALENB_in = RCALENB_delay;
assign SDM0DATA_in = SDM0DATA_delay;
assign SDM0RESET_in = SDM0RESET_delay;
assign SDM0WIDTH_in = SDM0WIDTH_delay;
assign SDM1DATA_in = SDM1DATA_delay;
assign SDM1RESET_in = SDM1RESET_delay;
assign SDM1WIDTH_in = SDM1WIDTH_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((A_SDM1DATA1_0_REG < 16'b0000000000000000) || (A_SDM1DATA1_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute A_SDM1DATA1_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, A_SDM1DATA1_0_REG);
attr_err = 1'b1;
end
if ((A_SDM1DATA1_1_REG < 9'b000000000) || (A_SDM1DATA1_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute A_SDM1DATA1_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, A_SDM1DATA1_1_REG);
attr_err = 1'b1;
end
if ((BIAS_CFG_RSVD_REG < 10'b0000000000) || (BIAS_CFG_RSVD_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute BIAS_CFG_RSVD on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, BIAS_CFG_RSVD_REG);
attr_err = 1'b1;
end
if ((QPLL0CLKOUT_RATE_REG != "FULL") &&
(QPLL0CLKOUT_RATE_REG != "HALF")) begin
$display("Attribute Syntax Error : The attribute QPLL0CLKOUT_RATE on %s instance %m is set to %s. Legal values for this attribute are FULL or HALF.", MODULE_NAME, QPLL0CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((QPLL0_CP_G3_REG < 10'b0000000000) || (QPLL0_CP_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_CP_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_CP_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_CP_REG < 10'b0000000000) || (QPLL0_CP_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_CP on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_CP_REG);
attr_err = 1'b1;
end
if ((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL0_FBDIV_G3 on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL0_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL0_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL0_FBDIV_REG);
attr_err = 1'b1;
end
if ((QPLL0_LPF_G3_REG < 10'b0000000000) || (QPLL0_LPF_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_LPF_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_LPF_G3_REG);
attr_err = 1'b1;
end
if ((QPLL0_LPF_REG < 10'b0000000000) || (QPLL0_LPF_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_LPF on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL0_LPF_REG);
attr_err = 1'b1;
end
if ((QPLL0_REFCLK_DIV_REG != 2) &&
(QPLL0_REFCLK_DIV_REG != 1) &&
(QPLL0_REFCLK_DIV_REG != 3) &&
(QPLL0_REFCLK_DIV_REG != 4) &&
(QPLL0_REFCLK_DIV_REG != 5) &&
(QPLL0_REFCLK_DIV_REG != 6) &&
(QPLL0_REFCLK_DIV_REG != 8) &&
(QPLL0_REFCLK_DIV_REG != 10) &&
(QPLL0_REFCLK_DIV_REG != 12) &&
(QPLL0_REFCLK_DIV_REG != 16) &&
(QPLL0_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute QPLL0_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, QPLL0_REFCLK_DIV_REG, 2);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG0_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG0_REG);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG1_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG1_REG);
attr_err = 1'b1;
end
if ((QPLL0_SDM_CFG2_REG < 16'b0000000000000000) || (QPLL0_SDM_CFG2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL0_SDM_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL0_SDM_CFG2_REG);
attr_err = 1'b1;
end
if ((QPLL1CLKOUT_RATE_REG != "FULL") &&
(QPLL1CLKOUT_RATE_REG != "HALF")) begin
$display("Attribute Syntax Error : The attribute QPLL1CLKOUT_RATE on %s instance %m is set to %s. Legal values for this attribute are FULL or HALF.", MODULE_NAME, QPLL1CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((QPLL1_CP_G3_REG < 10'b0000000000) || (QPLL1_CP_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_CP_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_CP_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_CP_REG < 10'b0000000000) || (QPLL1_CP_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_CP on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_CP_REG);
attr_err = 1'b1;
end
if ((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL1_FBDIV_G3 on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL1_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160)) begin
$display("Attribute Syntax Error : The attribute QPLL1_FBDIV on %s instance %m is set to %d. Legal values for this attribute are 16 to 160.", MODULE_NAME, QPLL1_FBDIV_REG);
attr_err = 1'b1;
end
if ((QPLL1_LPF_G3_REG < 10'b0000000000) || (QPLL1_LPF_G3_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_LPF_G3 on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_LPF_G3_REG);
attr_err = 1'b1;
end
if ((QPLL1_LPF_REG < 10'b0000000000) || (QPLL1_LPF_REG > 10'b1111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_LPF on %s instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", MODULE_NAME, QPLL1_LPF_REG);
attr_err = 1'b1;
end
if ((QPLL1_REFCLK_DIV_REG != 2) &&
(QPLL1_REFCLK_DIV_REG != 1) &&
(QPLL1_REFCLK_DIV_REG != 3) &&
(QPLL1_REFCLK_DIV_REG != 4) &&
(QPLL1_REFCLK_DIV_REG != 5) &&
(QPLL1_REFCLK_DIV_REG != 6) &&
(QPLL1_REFCLK_DIV_REG != 8) &&
(QPLL1_REFCLK_DIV_REG != 10) &&
(QPLL1_REFCLK_DIV_REG != 12) &&
(QPLL1_REFCLK_DIV_REG != 16) &&
(QPLL1_REFCLK_DIV_REG != 20)) begin
$display("Attribute Syntax Error : The attribute QPLL1_REFCLK_DIV on %s instance %m is set to %d. Legal values for this attribute are 1 to 20.", MODULE_NAME, QPLL1_REFCLK_DIV_REG, 2);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG0_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG0_REG);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG1_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG1_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG1 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG1_REG);
attr_err = 1'b1;
end
if ((QPLL1_SDM_CFG2_REG < 16'b0000000000000000) || (QPLL1_SDM_CFG2_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute QPLL1_SDM_CFG2 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, QPLL1_SDM_CFG2_REG);
attr_err = 1'b1;
end
if ((RXRECCLKOUT0_SEL_REG < 2'b00) || (RXRECCLKOUT0_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXRECCLKOUT0_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXRECCLKOUT0_SEL_REG);
attr_err = 1'b1;
end
if ((RXRECCLKOUT1_SEL_REG < 2'b00) || (RXRECCLKOUT1_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute RXRECCLKOUT1_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, RXRECCLKOUT1_SEL_REG);
attr_err = 1'b1;
end
if ((SARC_EN_REG < 1'b0) || (SARC_EN_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SARC_EN on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SARC_EN_REG);
attr_err = 1'b1;
end
if ((SARC_SEL_REG < 1'b0) || (SARC_SEL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SARC_SEL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SARC_SEL_REG);
attr_err = 1'b1;
end
if ((SDM0INITSEED0_0_REG < 16'b0000000000000000) || (SDM0INITSEED0_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0INITSEED0_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM0INITSEED0_0_REG);
attr_err = 1'b1;
end
if ((SDM0INITSEED0_1_REG < 9'b000000000) || (SDM0INITSEED0_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM0INITSEED0_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM0INITSEED0_1_REG);
attr_err = 1'b1;
end
if ((SDM1INITSEED0_0_REG < 16'b0000000000000000) || (SDM1INITSEED0_0_REG > 16'b1111111111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1INITSEED0_0 on %s instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", MODULE_NAME, SDM1INITSEED0_0_REG);
attr_err = 1'b1;
end
if ((SDM1INITSEED0_1_REG < 9'b000000000) || (SDM1INITSEED0_1_REG > 9'b111111111)) begin
$display("Attribute Syntax Error : The attribute SDM1INITSEED0_1 on %s instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", MODULE_NAME, SDM1INITSEED0_1_REG);
attr_err = 1'b1;
end
if ((SIM_QPLL0REFCLK_SEL_REG < 3'b000) || (SIM_QPLL0REFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_QPLL0REFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_QPLL0REFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_QPLL1REFCLK_SEL_REG < 3'b000) || (SIM_QPLL1REFCLK_SEL_REG > 3'b111)) begin
$display("Attribute Syntax Error : The attribute SIM_QPLL1REFCLK_SEL on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, SIM_QPLL1REFCLK_SEL_REG);
attr_err = 1'b1;
end
if ((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute SIM_RESET_SPEEDUP on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2")) begin
$display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2.", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK_in = 8'b11111111; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 8'b11111111; // tie off
assign QDPMASCANMODEB_in = 1'b1; // tie off
assign QDPMASCANRSTEN_in = 1'b1; // tie off
assign RXRECCLK_in = 4'b1111; // tie off
SIP_GTYE3_COMMON SIP_GTYE3_COMMON_INST (
.AEN_BGBS0 (AEN_BGBS0_REG),
.AEN_BGBS1 (AEN_BGBS1_REG),
.AEN_MASTER0 (AEN_MASTER0_REG),
.AEN_MASTER1 (AEN_MASTER1_REG),
.AEN_PD0 (AEN_PD0_REG),
.AEN_PD1 (AEN_PD1_REG),
.AEN_QPLL0 (AEN_QPLL0_REG),
.AEN_QPLL1 (AEN_QPLL1_REG),
.AEN_REFCLK0 (AEN_REFCLK0_REG),
.AEN_REFCLK1 (AEN_REFCLK1_REG),
.AEN_RESET0 (AEN_RESET0_REG),
.AEN_RESET1 (AEN_RESET1_REG),
.AEN_SDMDATA0 (AEN_SDMDATA0_REG),
.AEN_SDMDATA1 (AEN_SDMDATA1_REG),
.AEN_SDMRESET0 (AEN_SDMRESET0_REG),
.AEN_SDMRESET1 (AEN_SDMRESET1_REG),
.AEN_SDMWIDTH0 (AEN_SDMWIDTH0_REG),
.AEN_SDMWIDTH1 (AEN_SDMWIDTH1_REG),
.AQDMUXSEL1 (AQDMUXSEL1_REG),
.AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG),
.AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG),
.A_BGMONITOREN (A_BGMONITOREN_REG),
.A_BGPD (A_BGPD_REG),
.A_GTREFCLKPD0 (A_GTREFCLKPD0_REG),
.A_GTREFCLKPD1 (A_GTREFCLKPD1_REG),
.A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG),
.A_QPLL0PD (A_QPLL0PD_REG),
.A_QPLL0RESET (A_QPLL0RESET_REG),
.A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG),
.A_QPLL1PD (A_QPLL1PD_REG),
.A_QPLL1RESET (A_QPLL1RESET_REG),
.A_SDM0DATA1_0 (A_SDM0DATA1_0_REG),
.A_SDM0DATA1_1 (A_SDM0DATA1_1_REG),
.A_SDM1DATA1_0 (A_SDM1DATA1_0_REG),
.A_SDM1DATA1_1 (A_SDM1DATA1_1_REG),
.A_SDMRESET0 (A_SDMRESET0_REG),
.A_SDMRESET1 (A_SDMRESET1_REG),
.BIAS_CFG0 (BIAS_CFG0_REG),
.BIAS_CFG1 (BIAS_CFG1_REG),
.BIAS_CFG2 (BIAS_CFG2_REG),
.BIAS_CFG3 (BIAS_CFG3_REG),
.BIAS_CFG4 (BIAS_CFG4_REG),
.BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG),
.COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG),
.COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG),
.COMMON_CFG0 (COMMON_CFG0_REG),
.COMMON_CFG1 (COMMON_CFG1_REG),
.COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG),
.POR_CFG (POR_CFG_REG),
.PPF0_CFG (PPF0_CFG_REG),
.PPF1_CFG (PPF1_CFG_REG),
.QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG),
.QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG),
.QPLL0_CFG0 (QPLL0_CFG0_REG),
.QPLL0_CFG1 (QPLL0_CFG1_REG),
.QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG),
.QPLL0_CFG2 (QPLL0_CFG2_REG),
.QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG),
.QPLL0_CFG3 (QPLL0_CFG3_REG),
.QPLL0_CFG4 (QPLL0_CFG4_REG),
.QPLL0_CP (QPLL0_CP_REG),
.QPLL0_CP_G3 (QPLL0_CP_G3_REG),
.QPLL0_FBDIV (QPLL0_FBDIV_REG),
.QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG),
.QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG),
.QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG),
.QPLL0_IPS_EN (QPLL0_IPS_EN_REG),
.QPLL0_IPS_REFCLK_SEL (QPLL0_IPS_REFCLK_SEL_REG),
.QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG),
.QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG),
.QPLL0_LPF (QPLL0_LPF_REG),
.QPLL0_LPF_G3 (QPLL0_LPF_G3_REG),
.QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG),
.QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG),
.QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG),
.QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG),
.QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG),
.QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG),
.QPLL1_CFG0 (QPLL1_CFG0_REG),
.QPLL1_CFG1 (QPLL1_CFG1_REG),
.QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG),
.QPLL1_CFG2 (QPLL1_CFG2_REG),
.QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG),
.QPLL1_CFG3 (QPLL1_CFG3_REG),
.QPLL1_CFG4 (QPLL1_CFG4_REG),
.QPLL1_CP (QPLL1_CP_REG),
.QPLL1_CP_G3 (QPLL1_CP_G3_REG),
.QPLL1_FBDIV (QPLL1_FBDIV_REG),
.QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG),
.QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG),
.QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG),
.QPLL1_IPS_EN (QPLL1_IPS_EN_REG),
.QPLL1_IPS_REFCLK_SEL (QPLL1_IPS_REFCLK_SEL_REG),
.QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG),
.QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG),
.QPLL1_LPF (QPLL1_LPF_REG),
.QPLL1_LPF_G3 (QPLL1_LPF_G3_REG),
.QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG),
.QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG),
.QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG),
.QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG),
.RCALSAP_TESTEN (RCALSAP_TESTEN_REG),
.RCAL_APROBE (RCAL_APROBE_REG),
.REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG),
.REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG),
.REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG),
.REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG),
.REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG),
.REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG),
.RSVD_ATTR0 (RSVD_ATTR0_REG),
.RSVD_ATTR1 (RSVD_ATTR1_REG),
.RSVD_ATTR2 (RSVD_ATTR2_REG),
.RSVD_ATTR3 (RSVD_ATTR3_REG),
.RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG),
.RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG),
.SARC_EN (SARC_EN_REG),
.SARC_SEL (SARC_SEL_REG),
.SDM0INITSEED0_0 (SDM0INITSEED0_0_REG),
.SDM0INITSEED0_1 (SDM0INITSEED0_1_REG),
.SDM1INITSEED0_0 (SDM1INITSEED0_0_REG),
.SDM1INITSEED0_1 (SDM1INITSEED0_1_REG),
.VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.PMARSVDOUT0 (PMARSVDOUT0_out),
.PMARSVDOUT1 (PMARSVDOUT1_out),
.PMASCANOUT (PMASCANOUT_out),
.QPLL0FBCLKLOST (QPLL0FBCLKLOST_out),
.QPLL0LOCK (QPLL0LOCK_out),
.QPLL0OUTCLK (QPLL0OUTCLK_out),
.QPLL0OUTREFCLK (QPLL0OUTREFCLK_out),
.QPLL0REFCLKLOST (QPLL0REFCLKLOST_out),
.QPLL1FBCLKLOST (QPLL1FBCLKLOST_out),
.QPLL1LOCK (QPLL1LOCK_out),
.QPLL1OUTCLK (QPLL1OUTCLK_out),
.QPLL1OUTREFCLK (QPLL1OUTREFCLK_out),
.QPLL1REFCLKLOST (QPLL1REFCLKLOST_out),
.QPLLDMONITOR0 (QPLLDMONITOR0_out),
.QPLLDMONITOR1 (QPLLDMONITOR1_out),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out),
.RXRECCLK0_SEL (RXRECCLK0_SEL_out),
.RXRECCLK1_SEL (RXRECCLK1_SEL_out),
.SARCCLK (SARCCLK_out),
.SDM0FINALOUT (SDM0FINALOUT_out),
.SDM0TESTDATA (SDM0TESTDATA_out),
.SDM1FINALOUT (SDM1FINALOUT_out),
.SDM1TESTDATA (SDM1TESTDATA_out),
.BGBYPASSB (BGBYPASSB_in),
.BGMONITORENB (BGMONITORENB_in),
.BGPDB (BGPDB_in),
.BGRCALOVRD (BGRCALOVRD_in),
.BGRCALOVRDENB (BGRCALOVRDENB_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.GTGREFCLK0 (GTGREFCLK0_in),
.GTGREFCLK1 (GTGREFCLK1_in),
.GTNORTHREFCLK00 (GTNORTHREFCLK00_in),
.GTNORTHREFCLK01 (GTNORTHREFCLK01_in),
.GTNORTHREFCLK10 (GTNORTHREFCLK10_in),
.GTNORTHREFCLK11 (GTNORTHREFCLK11_in),
.GTREFCLK00 (GTREFCLK00_in),
.GTREFCLK01 (GTREFCLK01_in),
.GTREFCLK10 (GTREFCLK10_in),
.GTREFCLK11 (GTREFCLK11_in),
.GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in),
.GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in),
.GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in),
.GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in),
.PMARSVD0 (PMARSVD0_in),
.PMARSVD1 (PMARSVD1_in),
.PMASCANCLK (PMASCANCLK_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.QDPMASCANMODEB (QDPMASCANMODEB_in),
.QDPMASCANRSTEN (QDPMASCANRSTEN_in),
.QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in),
.QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in),
.QPLL0LOCKEN (QPLL0LOCKEN_in),
.QPLL0PD (QPLL0PD_in),
.QPLL0REFCLKSEL (QPLL0REFCLKSEL_in),
.QPLL0RESET (QPLL0RESET_in),
.QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in),
.QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in),
.QPLL1LOCKEN (QPLL1LOCKEN_in),
.QPLL1PD (QPLL1PD_in),
.QPLL1REFCLKSEL (QPLL1REFCLKSEL_in),
.QPLL1RESET (QPLL1RESET_in),
.QPLLRSVD1 (QPLLRSVD1_in),
.QPLLRSVD2 (QPLLRSVD2_in),
.QPLLRSVD3 (QPLLRSVD3_in),
.QPLLRSVD4 (QPLLRSVD4_in),
.RCALENB (RCALENB_in),
.RXRECCLK (RXRECCLK_in),
.SDM0DATA (SDM0DATA_in),
.SDM0RESET (SDM0RESET_in),
.SDM0WIDTH (SDM0WIDTH_in),
.SDM1DATA (SDM1DATA_in),
.SDM1RESET (SDM1RESET_in),
.SDM1WIDTH (SDM1WIDTH_in),
.GSR (glblGSR)
);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/HARD_SYNC.v 0000664 0000000 0000000 00000010443 12327044266 0022776 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : HARD_SYNC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 01/30/13 Initial version
// 05/08/13 712367 - fix blocking assignments
// 05/17/13 718960 - fix BIN encoding
// 05/17/13 719092 - remove SR, add IS_CLK_INVERTED
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HARD_SYNC #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter integer LATENCY = 2
)(
output DOUT,
input CLK,
input DIN
);
// define constants
localparam MODULE_NAME = "HARD_SYNC";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam [0:0] LATENCY_2 = 1'b0;
localparam [0:0] LATENCY_3 = 1'b1;
`ifndef XIL_DR
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [1:0] LATENCY_REG = LATENCY;
`endif
wire INIT_BIN;
wire IS_CLK_INVERTED_BIN;
wire LATENCY_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "HARD_SYNC_dr.v"
`endif
wire DOUT_out;
wire DOUT_delay;
wire CLK_in;
wire DIN_in;
wire CLK_delay;
wire DIN_delay;
// input output assignments
assign #(out_delay) DOUT = DOUT_delay;
assign #(in_delay) CLK_delay = CLK;
assign #(in_delay) DIN_delay = DIN;
assign DOUT_delay = DOUT_out;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign DIN_in = DIN_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign INIT_BIN = INIT_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign LATENCY_BIN =
(LATENCY_REG == 2) ? LATENCY_2 :
(LATENCY_REG == 3) ? LATENCY_3 :
LATENCY_2;
always @ (trig_attr) begin
#1;
if ((LATENCY_REG != 2) && (LATENCY_REG != 3)) begin
$display("Attribute Syntax Error : The attribute LATENCY on %s instance %m is set to %d. Legal values for this attribute are 2 to 3.", MODULE_NAME, LATENCY_REG);
attr_err = 1'b1;
end
if ((INIT_REG != 1'b0) && (INIT_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG != 1'b0) && (IS_CLK_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
reg D1_reg, D2_reg, D3_reg;
assign DOUT_out = (LATENCY_BIN == LATENCY_2) ? D2_reg : D3_reg;
always @ (posedge CLK_in or posedge glblGSR) begin
if (glblGSR == 1'b1) begin
D3_reg <= INIT_BIN;
D2_reg <= INIT_BIN;
D1_reg <= INIT_BIN;
end
else begin
D3_reg <= D2_reg;
D2_reg <= D1_reg;
D1_reg <= DIN_in;
end
end
specify
(CLK *> DOUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, DIN_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/HPIO_VREF.v 0000664 0000000 0000000 00000005323 12327044266 0023006 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : HPIO_VREF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HPIO_VREF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter VREF_CNTR = "OFF"
)(
output VREF,
input [6:0] FABRIC_VREF_TUNE
);
// define constants
localparam MODULE_NAME = "HPIO_VREF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam VREF_CNTR_FABRIC_RANGE1 = 1;
localparam VREF_CNTR_FABRIC_RANGE2 = 2;
localparam VREF_CNTR_OFF = 0;
localparam [104:1] VREF_CNTR_REG = VREF_CNTR;
wire [1:0] VREF_CNTR_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
wire VREF_out = 1'b1;
wire VREF_delay;
wire [6:0] FABRIC_VREF_TUNE_in;
wire [6:0] FABRIC_VREF_TUNE_delay;
assign #(out_delay) VREF = VREF_delay;
// inputs with no timing checks
assign #(in_delay) FABRIC_VREF_TUNE_delay = FABRIC_VREF_TUNE;
assign VREF_delay = VREF_out;
assign FABRIC_VREF_TUNE_in = FABRIC_VREF_TUNE_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign VREF_CNTR_BIN =
(VREF_CNTR_REG == "OFF") ? VREF_CNTR_OFF :
(VREF_CNTR_REG == "FABRIC_RANGE1") ? VREF_CNTR_FABRIC_RANGE1 :
(VREF_CNTR_REG == "FABRIC_RANGE2") ? VREF_CNTR_FABRIC_RANGE2 :
VREF_CNTR_OFF;
always @ (trig_attr) begin
#1;
if ((VREF_CNTR_REG != "OFF") &&
(VREF_CNTR_REG != "FABRIC_RANGE1") &&
(VREF_CNTR_REG != "FABRIC_RANGE2")) begin
$display("Attribute Syntax Error : The attribute VREF_CNTR on %s instance %m is set to %s. Legal values for this attribute are OFF, FABRIC_RANGE1 or FABRIC_RANGE2.", MODULE_NAME, VREF_CNTR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @ (FABRIC_VREF_TUNE_in) begin
$display("Fabric Tune Value changed to %b",FABRIC_VREF_TUNE_in);
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUF.v 0000664 0000000 0000000 00000005720 12327044266 0022153 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFCTRL.v 0000664 0000000 0000000 00000010215 12327044266 0022633 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFCTRL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFCTRL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter ISTANDARD = "UNUSED",
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
input I,
input IBUFDISABLE,
input INTERMDISABLE,
input T
);
// define constants
localparam MODULE_NAME = "IBUFCTRL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam ISTANDARD_UNUSED = 0;
localparam USE_IBUFDISABLE_FALSE = 1;
localparam USE_IBUFDISABLE_TRUE = 0;
integer USE_IBUFDISABLE_BIN;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
localparam [56:1] ISTANDARD_REG = ISTANDARD;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
wire O_out;
wire O_delay;
wire ISTANDARD_BIN;
wire IBUFDISABLE_in;
wire INTERMDISABLE_in;
wire I_in;
wire T_in;
wire IBUFDISABLE_delay;
wire INTERMDISABLE_delay;
wire I_delay;
wire T_delay;
wire NOT_T_OR_IBUFDISABLE;
// input output assignments
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) INTERMDISABLE_delay = INTERMDISABLE;
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign O_delay = O_out;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign INTERMDISABLE_in = INTERMDISABLE_delay;
assign I_in = I_delay;
assign T_in = T_delay;
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign ISTANDARD_BIN =
(ISTANDARD_REG == "UNUSED") ? ISTANDARD_UNUSED :
ISTANDARD_UNUSED;
always @ (trig_attr) begin
#1;
if ((ISTANDARD_REG != "UNUSED") && (ISTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute ISTANDARD on %s instance %m is set to %s. Legal values for this attribute are UNUSED.", MODULE_NAME, ISTANDARD_REG);
attr_err = 1'b1;
end
case (USE_IBUFDISABLE_REG)
"TRUE" : USE_IBUFDISABLE_BIN = USE_IBUFDISABLE_TRUE;
"FALSE" : USE_IBUFDISABLE_BIN = USE_IBUFDISABLE_FALSE;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) $finish;
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign NOT_T_OR_IBUFDISABLE = ~T_in || IBUFDISABLE_in;
assign O_out = (NOT_T_OR_IBUFDISABLE == 0)? I_in : (NOT_T_OR_IBUFDISABLE == 1)? 1'b0 : 1'bx;
end
"FALSE" : begin
assign O_out = I_in;
end
endcase
endgenerate
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS.v 0000664 0000000 0000000 00000011143 12327044266 0022376 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 07/19/06 - Add else to handle x case for o_out (CR 234718).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS (O, I, IB);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
localparam MODULE_NAME = "IBUFDS";
output O;
input I, IB;
wire i_in, ib_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
assign O = o_out;
assign i_in = I;
assign ib_in = IB;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDSE3.v 0000664 0000000 0000000 00000013305 12327044266 0022570 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDSE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
input I,
input IB,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "IBUFDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire IOSTANDARD_BIN;
wire [5:0] SIM_INPUT_BUFFER_OFFSET_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
reg O_out;
reg O_OSC_in;
wire O_delay;
wire IB_in;
wire I_in;
wire VREF_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire IB_delay;
wire I_delay;
wire VREF_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IB_delay = IB;
assign #(in_delay) I_delay = I;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
//assign O_delay = O_out;
assign IB_in = IB_delay;
assign I_in = I_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
assign O_delay = (OSC_EN_in == 2'b11) ? O_OSC_in : (OSC_EN_in == 2'b10 || OSC_EN_in == 2'b01) ? 1'bx : O_out;
integer OSC_int = 0;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= 1'bx;
end
initial begin
#1;
trig_attr = ~trig_attr;
end
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
IBUF_LOW_PWR_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
always @ (trig_attr) begin
#1;
if ((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(I_in or IB_in or DQS_BIAS_BIN) begin
if (I_in == 1'b1 && IB_in == 1'b0)
O_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
O_out <= 1'b0;
else if ((I_in === 1'bz || I_in == 1'b0) && (IB_in === 1'bz || IB_in == 1'b1))
if (DQS_BIAS_BIN == 1'b1)
O_out <= 1'b0;
else
O_out <= 1'bx;
else if ((I_in === 1'bx) || (IB_in === 1'bx))
O_out <= 1'bx;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_DIFF_OUT.v 0000664 0000000 0000000 00000005507 12327044266 0023724 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_DIFF_OUT.v,v 1.10 2010/11/03 22:31:02 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/13/08 - CR 458290 -- Added else condition to handle x case.
// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM.
// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR.
// 11/03/10 - CR 576577 -- changed default value of IOSTANDARD from LVDS_25 to DEFAULT.
// 09/30/11 - CR 626400 -- Added PATHPULSE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT (O, OB, I, IB);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O, OB;
input I, IB;
reg o_out;
buf B0 (O, o_out);
not B1 (OB, o_out);
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_DIFF_OUT_IBUFDISABLE.v 0000664 0000000 0000000 00000006276 12327044266 0025521 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_IBUFDISABLE.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_IBUFDISABLE (O, OB, I, IB, IBUFDISABLE);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
reg o_out;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_DIFF_OUT_INTERMDISABLE.v 0000664 0000000 0000000 00000006471 12327044266 0025767 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, I, IB, IBUFDISABLE, INTERMDISABLE);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
reg o_out;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_GTE2.v 0000664 0000000 0000000 00000010406 12327044266 0023160 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_GTE2.v
// \ \ / \ Timestamp : Tue Jun 1 14:31:01 PDT 2010
// \___\/\___\
//
// Revision:
// 06/01/10 - Initial version.
// 09/29/11 - 627247 -- Changed CLKSWING_CFG from blooean to bits
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module IBUFDS_GTE2 (
O,
ODIV2,
CEB,
I,
IB
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
output O;
output ODIV2;
input CEB;
input I;
input IB;
// Output signals
reg O_out=0, ODIV2_out=0;
// Counters and Flags
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
// Attribute settings
// Other signals
reg clkcm_cfg_int = 0;
reg clkrcv_trst_int = 0;
reg clkswing_cfg_int = 0;
reg [1:0] CLKSWING_CFG_BINARY;
reg notifier;
initial begin
allEqual = 0;
//-------------------------------------------------
//----- CLKCM_CFG check
//-------------------------------------------------
case (CLKCM_CFG)
"FALSE" : clkcm_cfg_int <= 1'b0;
"TRUE" : clkcm_cfg_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG);
$finish;
end
endcase // case(CLKCM_CFG)
//-------------------------------------------------
//----- CLKRCV_TRST check
//-------------------------------------------------
case (CLKRCV_TRST)
"FALSE" : clkrcv_trst_int <= 1'b0;
"TRUE" : clkrcv_trst_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST);
$finish;
end
endcase // case(CLKRCV_TRST)
//-------------------------------------------------
//----- CLKSWING_CFG check
//-------------------------------------------------
if ((CLKSWING_CFG >= 2'b00) && (CLKSWING_CFG <= 2'b11))
CLKSWING_CFG_BINARY = CLKSWING_CFG;
else begin
$display("Attribute Syntax Error : The Attribute CLKSWING_CFG on IBUFDS_GTE2 instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CLKSWING_CFG);
$finish;
end
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(posedge I)
ODIV2_out <= allEqual;
// =====================
// Generate O
// =====================
always @(I)
O_out <= I & ~CEB;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$period (posedge IB, 0:0:0, notifier);
( I => O) = (100:100:100, 100:100:100);
( I => ODIV2) = (100:100:100, 100:100:100);
( IB => O) = (100:100:100, 100:100:100);
( IB => ODIV2) = (100:100:100, 100:100:100);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_GTE3.v 0000664 0000000 0000000 00000011272 12327044266 0023163 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFDS_GTE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 12/11/2012 - Initial version
// 03/22/2013 - Model added
// 03/25/2013 - Sync 5 YML & model update
// 04/12/2013 - Add attribute section
// 08/28/2013 - Add specify section
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTE3";
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
localparam [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [1:0] REFCLK_HROW_CK_SEL_BIN;
wire [1:0] REFCLK_ICNTL_RX_BIN;
wire i_in, ib_in, ceb_in;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTE3_dr.v"
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
assign i_in = I;
assign ib_in = IB;
assign ceb_in = CEB;
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG;
assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG;
always @ (trig_attr) begin
#1;
if ((REFCLK_EN_TX_PATH_REG < 1'b0) || (REFCLK_EN_TX_PATH_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute REFCLK_EN_TX_PATH on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, REFCLK_EN_TX_PATH_REG);
attr_err = 1'b1;
end
if ((REFCLK_HROW_CK_SEL_REG < 2'b00) || (REFCLK_HROW_CK_SEL_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute REFCLK_HROW_CK_SEL on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, REFCLK_HROW_CK_SEL_REG);
attr_err = 1'b1;
end
if ((REFCLK_ICNTL_RX_REG < 2'b00) || (REFCLK_ICNTL_RX_REG > 2'b11)) begin
$display("Attribute Syntax Error : The attribute REFCLK_ICNTL_RX on %s instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", MODULE_NAME, REFCLK_ICNTL_RX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
reg ODIV2_out=0;
wire O_out;
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
initial begin
allEqual = 0;
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_BIN)
2'b00: ODIV2_out <= O_out;
2'b01: ODIV2_out <= allEqual;
2'b10: ODIV2_out <= 1'b0;
2'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= O_out;
endcase
end
// =====================
// Generate O
// =====================
assign O_out = (REFCLK_EN_TX_PATH_BIN | ceb_in) ? 1'b0 : i_in;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => ODIV2) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => ODIV2) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => ODIV2) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_IBUFDISABLE.v 0000664 0000000 0000000 00000010414 12327044266 0024167 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_IBUFDISABLE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_IBUFDISABLE (O, I, IB, IBUFDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_IBUFDISABLE";
output O;
input I;
input IB;
input IBUFDISABLE;
wire i_in, ib_in, ibufdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_IBUFDISABLE_INT.v 0000664 0000000 0000000 00000010062 12327044266 0024700 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_IBUFDISABLE_INT.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_IBUFDISABLE_INT (O, I, IB, IBUFDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_IBUFDISABLE_INT";
output O;
input I;
input IB;
input IBUFDISABLE;
wire i_in, ib_in, ibufdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_INTERMDISABLE.v 0000664 0000000 0000000 00000010616 12327044266 0024444 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_INTERMDISABLE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_INTERMDISABLE (O, I, IB, IBUFDISABLE, INTERMDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_INTERMDISABLE";
output O;
input I;
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
wire i_in, ib_in, ibufdisable_in, intermdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
assign intermdisable_in = INTERMDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFDS_INTERMDISABLE_INT.v 0000664 0000000 0000000 00000010323 12327044266 0025151 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_INTERMDISABLE_INT.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_INTERMDISABLE_INT (O, I, IB, IBUFDISABLE, INTERMDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_INTERMDISABLE_INT";
output O;
input I;
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
wire i_in, ib_in, ibufdisable_in, intermdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
assign intermdisable_in = INTERMDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUFE3.v 0000664 0000000 0000000 00000011145 12327044266 0022341 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
input I,
input [3:0] OSC,
input OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "IBUFE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
// `ifndef XIL_DR
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
// `endif
wire IBUF_LOW_PWR_BIN;
wire IOSTANDARD_BIN;
wire [5:0] SIM_INPUT_BUFFER_OFFSET_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "IBUFE3_dr.v"
// `endif
wire O_out;
reg O_OSC_in;
wire O_delay;
wire I_in;
wire OSC_EN_in;
wire VREF_in;
wire [3:0] OSC_in;
wire I_delay;
wire OSC_EN_delay;
wire VREF_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) I_delay = I;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_delay = O_out;
assign I_in = I_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
assign O_out = (OSC_EN_in) ? O_OSC_in : I_in;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
#1;
trig_attr = ~trig_attr;
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
IBUF_LOW_PWR_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
always @ (trig_attr) begin
#1;
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUF_ANALOG.v 0000664 0000000 0000000 00000001743 12327044266 0023175 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2013 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Analog Buffer
// /___/ /\ Filename : IBUF_ANALOG.v
// \ \ / \ Timestamp : Wed Oct 30 16:09:20 PDT 2013
// \___\/\___\
//
// Revision:
// 10/30/13 - Initial version.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF_ANALOG (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
pulldown p (O);
buf (weak1, weak0) B1 (O, I);
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUF_IBUFDISABLE.v 0000664 0000000 0000000 00000004274 12327044266 0023747 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF_IBUFDISABLE.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF_IBUFDISABLE (O, I, IBUFDISABLE);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
input I;
input IBUFDISABLE;
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
end
"FALSE" : begin
assign O = I;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IBUF_INTERMDISABLE.v 0000664 0000000 0000000 00000004373 12327044266 0024220 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF_INTERMDISABLE (O, I, IBUFDISABLE, INTERMDISABLE);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? 1'b1 : 1'bx;
end
"FALSE" : begin
assign O = I;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ICAPE2.v 0000664 0000000 0000000 00000021244 12327044266 0022330 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 1995/2006 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.51)
// \ \ Description :
// / /
// /__/ /\ Filename : ICAPE2.v
// \ \ / \
// \__\/\__ \
//
// Revision:
// 04/30/10 - Initial version.
// 09/03/10 - Change to bus timing.
// 02/18/11 - Change DEVICE_ID default (CR593951)
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ICAPE2 (
O,
CLK,
CSIB,
I,
RDWRB
);
parameter [31:0] DEVICE_ID = 32'h03651093;
parameter ICAP_WIDTH = "X32";
parameter SIM_CFG_FILE_NAME = "NONE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output [31:0] O;
input CLK;
input CSIB;
input RDWRB;
input [31:0] I;
wire cso_b;
reg prog_b;
reg init_b;
reg [3:0] bw = 4'b0000;
wire busy_out;
reg cs_bi = 0, rdwr_bi = 0;
wire cs_b_t;
wire clk_in;
wire rdwr_b_t;
wire [31:0] dix;
reg [31:0] di;
reg [31:0] data_rbt;
reg [7:0] tmp_byte0;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg icap_idone = 0;
reg clk_osc = 0;
reg sim_file_flag;
integer icap_fd;
reg notifier;
wire delay_CLK;
wire delay_CSIB;
wire delay_RDWRB;
wire [31:0] delay_I;
tri1 p_up;
tri init_tri = (icap_idone == 0) ? init_b : p_up;
tri (weak1, strong0) done_o = p_up;
tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_RDWRB = RDWRB;
assign delay_CLK = CLK;
assign delay_CSIB = CSIB;
`endif
assign dix = (icap_idone == 1) ? delay_I : di;
assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi;
assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc;
assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi;
assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0;
always
// if (icap_idone == 0)
#1000 clk_osc <= ~clk_osc;
always @(delay_CSIB or delay_RDWRB)
if ($time > 1 && icap_idone == 0) begin
$display (" Warning : ICAPE2 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time);
end
SIM_CONFIGE2 #(
.DEVICE_ID(DEVICE_ID),
.ICAP_SUPPORT("TRUE"),
.ICAP_WIDTH(ICAP_WIDTH)
)
SIM_CONFIGE2_INST (
.CSOB(cso_b),
.DONE(done_o),
.CCLK(clk_in),
.CSB(cs_b_t),
.D(di_t),
.INITB(init_tri),
.M(3'b110),
.PROGB(prog_b),
.RDWRB(rdwr_b_t)
);
initial begin
case (ICAP_WIDTH)
"X8" : bw = 4'b0000;
"X16" : bw = 4'b0010;
"X32" : bw = 4'b0011;
default : begin
$display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAPE2 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH);
end
endcase
icap_idone = 0;
sim_file_flag = 0;
if (SIM_CFG_FILE_NAME == "NONE") begin
sim_file_flag = 1;
end
else begin
icap_fd = $fopen(SIM_CFG_FILE_NAME, "r");
if (icap_fd == 0)
begin
$display(" Error: The configure rbt data file %s for ICAPE2 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME);
sim_file_flag = 1;
end
end
init_b = 1;
prog_b = 1;
rdwr_bi = 0;
cs_bi = 1;
#600000;
@(posedge clk_in)
prog_b = 0;
@(negedge clk_in)
init_b = 0;
#600000;
@(posedge clk_in)
prog_b = 1;
@(negedge clk_in) begin
init_b = 1;
cs_bi = 0;
end
if (sim_file_flag == 0) begin
while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin
if (done_o == 0) begin
tmp_byte3 = bit_revers8(data_rbt[31:24]);
tmp_byte2 = bit_revers8(data_rbt[23:16]);
tmp_byte1 = bit_revers8(data_rbt[15:8]);
tmp_byte0 = bit_revers8(data_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tmp_byte3};
@(negedge clk_in)
di = {24'b0, tmp_byte2};
@(negedge clk_in)
di = {24'b0, tmp_byte1};
@(negedge clk_in)
di = {24'b0, tmp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tmp_byte3, tmp_byte2};
@(negedge clk_in)
di = {16'b0, tmp_byte1, tmp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0};
end
end
else begin
@(negedge clk_in);
di = 32'hFFFFFFFF;
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
end
end
$fclose(icap_fd);
#1000;
end
else begin
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'h000000DD;
@(negedge clk_in) begin
if (bw == 4'b0000)
di = 32'h00000088;
else if (bw == 4'b0010)
di = 32'h00000044;
else if (bw == 4'b0011)
di = 32'h00000022;
end
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hAA995566);
rbt_data_wr(32'h30008001);
rbt_data_wr(32'h00000005);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
#1000;
end
end
task rbt_data_wr;
input [31:0] dat_rbt;
reg [7:0] tp_byte3;
reg [7:0] tp_byte2;
reg [7:0] tp_byte1;
reg [7:0] tp_byte0;
begin
tp_byte3 = bit_revers8(dat_rbt[31:24]);
tp_byte2 = bit_revers8(dat_rbt[23:16]);
tp_byte1 = bit_revers8(dat_rbt[15:8]);
tp_byte0 = bit_revers8(dat_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tp_byte3};
@(negedge clk_in)
di = {24'b0, tp_byte2};
@(negedge clk_in)
di = {24'b0, tp_byte1};
@(negedge clk_in)
di = {24'b0, tp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tp_byte3, tp_byte2};
@(negedge clk_in)
di = {16'b0, tp_byte1, tp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0};
end
end
endtask
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
specify
( CLK => O) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
$setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
`endif //
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ICAPE3.v 0000664 0000000 0000000 00000021700 12327044266 0022326 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.5
// \ \ Description :
// / /
// /__/ /\ Filename : ICAPE3.v
// \ \ / \
// \__\/\__ \
//
// Revision:
// 10/31/12 - Initial version.
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ICAPE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] DEVICE_ID = 32'h03628093,
parameter ICAP_AUTO_SWITCH = "DISABLE",
parameter SIM_CFG_FILE_NAME = "NONE"
)(
output AVAIL,
output [31:0] O,
output PRDONE,
output PRERROR,
input CLK,
input CSIB,
input RDWRB,
input [31:0] I
);
localparam ICAP_WIDTH = "X32";
wire cso_b;
reg prog_b;
reg init_b;
reg [3:0] bw = 4'b0000;
wire busy_out;
reg cs_bi = 0, rdwr_bi = 0;
wire cs_b_t;
wire clk_in;
wire rdwr_b_t;
wire [31:0] dix;
wire dangle;
reg [31:0] di;
reg [31:0] data_rbt;
reg [7:0] tmp_byte0;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg icap_idone = 0;
reg clk_osc = 0;
reg sim_file_flag;
integer icap_fd;
reg notifier;
reg AVAIL_reg = 1'b0;
wire delay_CLK;
wire delay_CSIB;
wire delay_RDWRB;
wire [31:0] delay_I;
tri1 p_up;
tri init_tri = (icap_idone == 0) ? init_b : p_up;
tri (weak1, strong0) done_o = p_up;
tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_RDWRB = RDWRB;
assign delay_CLK = CLK;
assign delay_CSIB = CSIB;
`endif
assign dix = (icap_idone == 1) ? delay_I : di;
assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi;
assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc;
assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi;
assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0;
assign AVAIL = AVAIL_reg;
always @(posedge icap_idone)
AVAIL_reg = 1'b1;
always
// if (icap_idone == 0)
#1000 clk_osc <= ~clk_osc;
always @(delay_CSIB or delay_RDWRB)
if ($time > 1 && icap_idone == 0) begin
$display (" Warning : ICAPE3 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time);
end
SIM_CONFIGE3 #(
.DEVICE_ID(DEVICE_ID),
.ICAP_SUPPORT("TRUE"),
.ICAP_WIDTH(ICAP_WIDTH)
)
SIM_CONFIGE3_INST (
.AVAIL(dangle),
.PRDONE(PRDONE),
.PRERROR(PRERROR),
.CSOB(cso_b),
.DONE(done_o),
.CCLK(clk_in),
.CSB(cs_b_t),
.D(di_t),
.INITB(init_tri),
.M(3'b110),
.PROGB(prog_b),
.RDWRB(rdwr_b_t)
);
initial begin
case (ICAP_AUTO_SWITCH)
"DISABLE", "ENABLE" : ;
default : begin
$display("Attribute Syntax Error : The attribute ICAP_AUTO_SWITCH on instance %m is set to %s. Legal values for this attribute are DISABLE or ENABLE.", ICAP_AUTO_SWITCH);
$finish;
end
endcase
icap_idone = 0;
sim_file_flag = 0;
if (SIM_CFG_FILE_NAME == "NONE") begin
sim_file_flag = 1;
end
else begin
icap_fd = $fopen(SIM_CFG_FILE_NAME, "r");
if (icap_fd == 0)
begin
$display(" Error: The configure rbt data file %s for ICAPE3 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME);
sim_file_flag = 1;
end
end
init_b = 1;
prog_b = 1;
rdwr_bi = 0;
cs_bi = 1;
#600000;
@(posedge clk_in)
prog_b = 0;
@(negedge clk_in)
init_b = 0;
#600000;
@(posedge clk_in)
prog_b = 1;
@(negedge clk_in) begin
init_b = 1;
cs_bi = 0;
end
if (sim_file_flag == 0) begin
while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin
if (done_o == 0) begin
tmp_byte3 = bit_revers8(data_rbt[31:24]);
tmp_byte2 = bit_revers8(data_rbt[23:16]);
tmp_byte1 = bit_revers8(data_rbt[15:8]);
tmp_byte0 = bit_revers8(data_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tmp_byte3};
@(negedge clk_in)
di = {24'b0, tmp_byte2};
@(negedge clk_in)
di = {24'b0, tmp_byte1};
@(negedge clk_in)
di = {24'b0, tmp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tmp_byte3, tmp_byte2};
@(negedge clk_in)
di = {16'b0, tmp_byte1, tmp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0};
end
end
else begin
@(negedge clk_in);
di = 32'hFFFFFFFF;
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE3 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
end
end
$fclose(icap_fd);
#1000;
end
else begin
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'h000000DD;
@(negedge clk_in) begin
if (bw == 4'b0000)
di = 32'h00000088;
else if (bw == 4'b0010)
di = 32'h00000044;
else if (bw == 4'b0011)
di = 32'h00000022;
end
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hAA995566);
rbt_data_wr(32'h30008001);
rbt_data_wr(32'h00000005);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE3 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
#1000;
end
end
task rbt_data_wr;
input [31:0] dat_rbt;
reg [7:0] tp_byte3;
reg [7:0] tp_byte2;
reg [7:0] tp_byte1;
reg [7:0] tp_byte0;
begin
tp_byte3 = bit_revers8(dat_rbt[31:24]);
tp_byte2 = bit_revers8(dat_rbt[23:16]);
tp_byte1 = bit_revers8(dat_rbt[15:8]);
tp_byte0 = bit_revers8(dat_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tp_byte3};
@(negedge clk_in)
di = {24'b0, tp_byte2};
@(negedge clk_in)
di = {24'b0, tp_byte1};
@(negedge clk_in)
di = {24'b0, tp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tp_byte3, tp_byte2};
@(negedge clk_in)
di = {16'b0, tp_byte1, tp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0};
end
end
endtask
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
specify
(CLK => O) = (100:100:100, 100:100:100);
(CLK => PRDONE) = (100:100:100, 100:100:100);
(CLK => PRERROR) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
$setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
`endif //
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDDR.v 0000664 0000000 0000000 00000023531 12327044266 0022150 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/virtex4/IDDR.v,v 1.14 2008/12/03 23:49:50 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Dual Data Rate Input D Flip-Flop
// /___/ /\ Filename : IDDR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 12/20/05 - Fixed setup and hold checks.
// 04/28/06 - Added c_in into the sensitivity list (CR 219840).
// 05/29/07 - Added wire declaration for internal signals
// 04/16/08 - CR 468871 Negative SetupHold fix
// 05/06/08 - CR 455447 add XON MSGON property to support async reg
// 12/03/08 - CR 498674 added pulldown on R/S.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 08/23/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDDR (Q1, Q2, C, CE, D, R, S);
output Q1;
output Q2;
input C;
input CE;
input D;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter MSGON = "TRUE";
parameter XON = "TRUE";
`endif
pulldown P1 (R);
pulldown P2 (S);
reg q1_out = INIT_Q1, q2_out = INIT_Q2;
reg q1_out_int, q2_out_int;
reg q1_out_pipelined, q2_out_same_edge_int;
reg notifier, notifier1, notifier2;
wire notifier1x, notifier2x;
wire c_in,delay_c;
wire ce_in,delay_ce;
wire d_in,delay_d;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
tri0 GSR = glbl.GSR;
assign gsr_in = GSR;
assign Q1 = q1_out;
assign Q2 = q2_out;
wire nr, ns, ngsr;
wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable;
wire ce_c_enable1, d_c_enable1, r_c_enable1, s_c_enable1;
not (nr, R);
not (ns, S);
not (ngsr, GSR);
and (ce_c_enable, ngsr, nr, ns);
and (d_c_enable, ngsr, nr, ns, CE);
and (s_c_enable, ngsr, nr);
`ifdef XIL_TIMING
assign notifier1x = (XON == "FALSE") ? 1'bx : notifier1;
assign notifier2x = (XON == "FALSE") ? 1'bx : notifier2;
assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable;
assign d_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable;
assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr;
assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable;
`endif
initial begin
if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2);
$finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q1_out_int = INIT_Q1;
assign q1_out_pipelined = INIT_Q1;
assign q2_out_same_edge_int = INIT_Q2;
assign q2_out_int = INIT_Q2;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b0;
assign q1_out_pipelined = 1'b0;
assign q2_out_same_edge_int = 1'b0;
assign q2_out_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b1;
assign q1_out_pipelined = 1'b1;
assign q2_out_same_edge_int = 1'b1;
assign q2_out_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q1_out_int <= 1'b1;
q1_out_pipelined <= 1'b1;
q2_out_same_edge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q1_out_int <= d_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end // always @ (posedge c_in)
always @(negedge c_in) begin
if (r_in == 1'b1)
q2_out_int <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q2_out_int <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
q2_out_int <= d_in;
end
always @(c_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin
case (DDR_CLK_EDGE)
"OPPOSITE_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
q1_out <= q1_out_pipelined;
q2_out <= q2_out_same_edge_int;
end
default : begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase // case(DDR_CLK_EDGE)
end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined)
`ifndef XIL_TIMING
assign delay_c = C;
assign delay_ce = CE;
assign delay_d = D;
assign delay_r = R;
assign delay_s = S;
`endif
assign c_in = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign d_in = IS_D_INVERTED ^ delay_d;
assign r_in = delay_r;
assign s_in = delay_s;
//*** Timing Checks Start here
`ifdef XIL_TIMING
always @(notifier or notifier1x) begin
q1_out <= 1'bx;
end
always @(notifier or notifier2x) begin
q2_out <= 1'bx;
end
`endif
specify
(C => Q1) = (100:100:100, 100:100:100);
(C => Q2) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(R => Q1) = (0:0:0, 0:0:0);
(R => Q2) = (0:0:0, 0:0:0);
(S => Q1) = (0:0:0, 0:0:0);
(S => Q2) = (0:0:0, 0:0:0);
$setuphold (posedge C, posedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (posedge C, negedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (negedge C, posedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce);
$setuphold (negedge C, negedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce);
$setuphold (posedge C, posedge D &&& (d_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (posedge C, negedge D &&& (d_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (negedge C, posedge D &&& (d_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d);
$setuphold (negedge C, negedge D &&& (d_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d);
$setuphold (posedge C, posedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (posedge C, negedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (negedge C, posedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r);
$setuphold (negedge C, negedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r);
$setuphold (posedge C, posedge S &&& (s_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (posedge C, negedge S &&& (s_c_enable1!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (negedge C, posedge S &&& (s_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s);
$setuphold (negedge C, negedge S &&& (s_c_enable1!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s);
$recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier2);
$recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier2);
$period (posedge C, 0:0:0, notifier);
$period (negedge C, 0:0:0, notifier);
$width (posedge C, 0:0:0, 0, notifier);
$width (negedge C, 0:0:0, 0, notifier);
$width (posedge R, 0:0:0, 0, notifier);
$width (posedge S, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDDR
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDDRE1.v 0000664 0000000 0000000 00000013137 12327044266 0022337 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IDDRE1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IDDRE1 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter [0:0] IS_C_INVERTED = 1'b0
)(
output Q1,
output Q2,
input C,
input CB,
input D,
input R
);
// define constants
localparam MODULE_NAME = "IDDRE1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DDR_CLK_EDGE_OPPOSITE_EDGE = 0;
localparam DDR_CLK_EDGE_SAME_EDGE = 1;
localparam DDR_CLK_EDGE_SAME_EDGE_PIPELINED = 2;
`ifndef XIL_DR
localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
localparam [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
`endif
wire [1:0] DDR_CLK_EDGE_BIN;
wire IS_C_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
reg q1_out_int,q1_out_pipelined,q2_out_same_edge_int,q2_out_int;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IDDRE1_dr.v"
`endif
reg Q1_out;
reg Q2_out;
wire Q1_delay;
wire Q2_delay;
wire CB_in;
wire C_in;
wire D_in;
wire R_in;
wire CB_delay;
wire C_delay;
wire D_delay;
wire R_delay;
assign #(out_delay) Q1 = Q1_delay;
assign #(out_delay) Q2 = Q2_delay;
// inputs with no timing checks
assign #(inclk_delay) CB_delay = CB;
assign #(inclk_delay) C_delay = C;
assign #(in_delay) D_delay = D;
assign #(in_delay) R_delay = R;
assign Q1_delay = Q1_out;
assign Q2_delay = Q2_out;
assign CB_in = CB_delay;
assign C_in = C_delay ^ IS_C_INVERTED_BIN;
assign D_in = D_delay;
assign R_in = R_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign DDR_CLK_EDGE_BIN =
(DDR_CLK_EDGE_REG == "OPPOSITE_EDGE") ? DDR_CLK_EDGE_OPPOSITE_EDGE :
(DDR_CLK_EDGE_REG == "SAME_EDGE") ? DDR_CLK_EDGE_SAME_EDGE :
(DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? DDR_CLK_EDGE_SAME_EDGE_PIPELINED :
DDR_CLK_EDGE_OPPOSITE_EDGE;
assign IS_C_INVERTED_BIN = IS_C_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", MODULE_NAME, DDR_CLK_EDGE_REG);
attr_err = 1'b1;
end
if ((IS_C_INVERTED_REG < 1'b0) || (IS_C_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_C_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_C_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(glblGSR or R_in) begin
if (glblGSR == 1'b1) begin
assign q1_out_int = 0;
assign q1_out_pipelined = 0;
assign q2_out_same_edge_int = 0;
assign q2_out_int = 0;
end
else if (glblGSR == 1'b0) begin
if (R_in == 1'b1) begin
assign q1_out_int = 0;
assign q1_out_pipelined = 0;
assign q2_out_same_edge_int = 0;
assign q2_out_int = 0;
end
else if (R_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end
end
always @(posedge C_in) begin
if (R_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end
else if (R_in == 1'b0) begin
q1_out_int <= D_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end
always @(posedge CB_in) begin
if (R_in == 1'b1)
q2_out_int <= 1'b0;
else if (R_in == 1'b0)
q2_out_int <= D_in;
end
always @(C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin
case (DDR_CLK_EDGE_REG)
"OPPOSITE_EDGE" : begin
Q1_out <= q1_out_int;
Q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
Q1_out <= q1_out_int;
Q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
Q1_out <= q1_out_pipelined;
Q2_out <= q2_out_same_edge_int;
end
default : begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDRE1 instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase // case(DDR_CLK_EDGE_REG)
end // always @ (C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined)
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDDR_2CLK.v 0000664 0000000 0000000 00000025331 12327044266 0022723 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2006 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Dual Data-Rate Register with Dual Clock inputs
// /___/ /\ Filename : IDDR_2CLK.v
// \ \ / \ Timestamp : Mon Jun 26 16:44:06 PST 2006
// \___\/\___\
//
// Revision:
// 06/26/06 - Initial version.
// 05/29/07 - Added wire declaration for internal signals
// 04/15/08 - CR 468871 Negative SetupHold fix
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 08/23/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDDR_2CLK (Q1, Q2, C, CB, CE, D, R, S);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_CB_INVERTED = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output Q1;
output Q2;
input C;
input CB;
input CE;
input D;
input R;
input S;
reg q1_out = INIT_Q1, q2_out = INIT_Q2;
reg q1_out_int, q2_out_int;
reg q1_out_pipelined, q2_out_same_edge_int;
reg notifier, notifier1, notifier2;
wire c_in,delay_c;
wire cb_in,delay_cb;
wire ce_in,delay_ce;
wire d_in,delay_d;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
tri0 GSR = glbl.GSR;
`ifndef XIL_TIMING
assign delay_c = C;
assign delay_cb = CB;
assign delay_ce = CE;
assign delay_d = D;
assign delay_r = R;
assign delay_s = S;
`endif
//buf buf_c (c_in, C);
//buf buf_cb (cb_in, CB);
assign c_in = IS_C_INVERTED ^ delay_c;
assign cb_in = IS_CB_INVERTED ^ delay_cb;
buf buf_ce (ce_in, delay_ce);
//buf buf_d (d_in, D);
assign d_in = IS_D_INVERTED ^ delay_d;
buf buf_gsr (gsr_in, GSR);
buf buf_q1 (Q1, q1_out);
buf buf_q2 (Q2, q2_out);
buf buf_r (r_in, delay_r);
buf buf_s (s_in, delay_s);
initial begin
if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2);
$finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q1_out_int = INIT_Q1;
assign q1_out_pipelined = INIT_Q1;
assign q2_out_same_edge_int = INIT_Q2;
assign q2_out_int = INIT_Q2;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b0;
assign q1_out_pipelined = 1'b0;
assign q2_out_same_edge_int = 1'b0;
assign q2_out_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b1;
assign q1_out_pipelined = 1'b1;
assign q2_out_same_edge_int = 1'b1;
assign q2_out_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q1_out_int <= 1'b1;
q1_out_pipelined <= 1'b1;
q2_out_same_edge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q1_out_int <= d_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end // always @ (posedge c_in)
always @(posedge cb_in) begin
if (r_in == 1'b1)
q2_out_int <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q2_out_int <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
q2_out_int <= d_in;
end // always @ (posedge cb_in)
always @(posedge c_in or posedge cb_in, q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin
case (DDR_CLK_EDGE)
"OPPOSITE_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
q1_out <= q1_out_pipelined;
q2_out <= q2_out_same_edge_int;
end
default : begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase // case(DDR_CLK_EDGE)
end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined)
`ifndef XIL_TIMING
specify
(C => Q1) = (100, 100);
(C => Q2) = (100, 100);
(CB => Q1) = (100, 100);
(CB => Q2) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier or notifier1) begin
q1_out <= 1'bx;
end
always @(notifier or notifier2) begin
q2_out <= 1'bx;
end
specify
(C => Q1) = (100:100:100, 100:100:100);
(C => Q2) = (100:100:100, 100:100:100);
(CB => Q1) = (100:100:100, 100:100:100);
(CB => Q2) = (100:100:100, 100:100:100);
(R => Q1) = (0:0:0, 0:0:0);
(R => Q2) = (0:0:0, 0:0:0);
(S => Q1) = (0:0:0, 0:0:0);
(S => Q2) = (0:0:0, 0:0:0);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (posedge CB, posedge CE, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_ce);
$setuphold (posedge CB, negedge CE, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_ce);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (posedge CB, posedge D, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_d);
$setuphold (posedge CB, negedge D, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_d);
$setuphold (posedge C, posedge R, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (posedge C, negedge R, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (posedge CB, posedge R, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_r);
$setuphold (posedge CB, negedge R, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_r);
$setuphold (posedge C, posedge S, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (posedge C, negedge S, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (posedge CB, posedge S, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_s);
$setuphold (posedge CB, negedge S, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_s);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (negedge CB, posedge CE, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_ce);
$setuphold (negedge CB, negedge CE, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_ce);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (negedge CB, posedge D, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_d);
$setuphold (negedge CB, negedge D, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_d);
$setuphold (negedge C, posedge R, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (negedge C, negedge R, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (negedge CB, posedge R, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_r);
$setuphold (negedge CB, negedge R, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_r);
$setuphold (negedge C, posedge S, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (negedge C, negedge S, 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (negedge CB, posedge S, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_s);
$setuphold (negedge CB, negedge S, 0:0:0, 0:0:0, notifier2, , , delay_cb, delay_s);
$recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge R, posedge CB, 0:0:0, 0:0:0, notifier2);
$recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge S, posedge CB, 0:0:0, 0:0:0, notifier2);
$recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge R, negedge CB, 0:0:0, 0:0:0, notifier2);
$recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier1);
$recrem (negedge S, negedge CB, 0:0:0, 0:0:0, notifier2);
$period (posedge C, 0:0:0, notifier);
$period (posedge CB, 0:0:0, notifier);
$width (posedge C, 0:0:0, 0, notifier);
$width (posedge CB, 0:0:0, 0, notifier);
$width (posedge R, 0:0:0, 0, notifier);
$width (posedge S, 0:0:0, 0, notifier);
$period (negedge C, 0:0:0, notifier);
$period (negedge CB, 0:0:0, notifier);
$width (negedge C, 0:0:0, 0, notifier);
$width (negedge CB, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // IDDR_2CLK
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDELAYCTRL.v 0000664 0000000 0000000 00000005737 12327044266 0023072 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/virtex4/IDELAYCTRL.v,v 1.10 2007/07/25 18:30:30 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Delay Controller
// /___/ /\ Filename : IDELAYCTRL.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter and initialized outpus.
// 04/10/07 - CR 436682 fix, disable activity when rst is high
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDELAYCTRL (RDY, REFCLK, RST);
output RDY;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
input REFCLK;
input RST;
wire refclk_in;
wire rst_in;
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg lost, rdy_out = 0;
assign RDY = rdy_out;
assign refclk_in = REFCLK;
assign rst_in = RST;
always @(rst_in, lost) begin
if ((rst_in == 1'b1) || (lost == 1))
rdy_out <= 1'b0;
else if (rst_in == 1'b0 && lost == 0)
rdy_out <= 1'b1;
end
initial begin
clock_edge <= 0;
clock_high <= 0;
clock_low <= 0;
lost <= 1;
period <= 0;
end
always @(posedge refclk_in) begin
if(rst_in == 1'b0) begin
clock_edge <= $time;
if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
period <= $time - clock_edge;
else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
period <= 0;
else if ((period == 0) && (clock_edge != 0))
period <= $time - clock_edge;
end
end
always @(posedge refclk_in) begin
clock_low <= 1'b0;
clock_high <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_posedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
lost <= 1;
end
always @(posedge refclk_in) begin
clock_negedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_posedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_high <= 1'b0;
clock_low <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_negedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
lost <= 1;
end
//*** Timing Checks Start here
specify
`ifdef XIL_TIMING
(RST => RDY) = (0:0:0, 0:0:0);
$period (posedge REFCLK, 0:0:0, notifier);
`endif
(REFCLK => RDY) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDELAYCTRL
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDELAYE2.v 0000664 0000000 0000000 00000054760 12327044266 0022574 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Input Fixed or Variable Delay Element.
// /___/ /\ Filename : IDELAYE2.v
// \ \ / \ Timestamp : Sat Sep 19 14:17:57 PDT 2009
// \___\/\___\
//
// Revision:
// 09/19/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDELAYE2 (CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN, REGRST);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "IDATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter IDELAY_TYPE = "FIXED";
parameter integer IDELAY_VALUE = 0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT;
output DATAOUT;
input C;
input CE;
input CINVCTRL;
input [4:0] CNTVALUEIN;
input DATAIN;
input IDATAIN;
input INC;
input LD;
input LDPIPEEN;
input REGRST;
tri0 GSR = glbl.GSR;
real CALC_TAPDELAY ;
real INIT_DELAY;
//------------------- constants ------------------------------------
localparam MAX_DELAY_COUNT = 31;
localparam MIN_DELAY_COUNT = 0;
localparam MAX_REFCLK_FREQUENCYL = 210.0;
localparam MIN_REFCLK_FREQUENCYL = 190.0;
localparam MAX_REFCLK_FREQUENCYH = 310.0;
localparam MIN_REFCLK_FREQUENCYH = 290.0;
//------------------- variable declaration -------------------------
integer idelay_count;
integer CNTVALUEIN_INTEGER;
reg [4:0] cntvalueout_pre;
reg notifier;
reg data_mux = 0;
reg tap_out = 0;
reg DATAOUT_reg = 0;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31;
reg c_in;
wire ce_in,delay_CE,delay_C;
wire clkin_in;
wire [4:0] cntvaluein_in,delay_CNTVALUEIN;
wire datain_in,delay_DATAIN;
wire gsr_in;
wire idatain_in,delay_IDATAIN;
wire inc_in,delay_INC;
wire odatain_in;
wire ld_in,delay_LD;
wire t_in;
wire cinvctrl_in,delay_CINVCTRL;
wire ldpipeen_in,delay_LDPIPEEN;
wire regrst_in,delay_REGRST;
wire c_in_pre;
reg [4:0] qcntvalueout_reg = 5'b0;
reg [4:0] qcntvalueout_mux = 5'b0;
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
// CR 587496
// assign #INIT_DELAY DATAOUT = tap_out;
always @(tap_out)
DATAOUT_reg <= #INIT_DELAY tap_out;
assign DATAOUT = DATAOUT_reg;
assign CNTVALUEOUT = cntvalueout_pre;
`ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign delay_C = C;
assign delay_CE = CE;
assign delay_CNTVALUEIN = CNTVALUEIN;
assign delay_INC = INC;
assign delay_LD = LD;
assign delay_LDPIPEEN = LDPIPEEN;
assign delay_REGRST = REGRST;
`endif // ifndef XIL_TIMING
assign delay_CINVCTRL = CINVCTRL;
assign delay_DATAIN = DATAIN;
assign delay_IDATAIN = IDATAIN;
assign gsr_in = GSR;
assign c_in_pre = delay_C ^ IS_C_INVERTED;
assign ce_in = delay_CE;
assign cntvaluein_in = delay_CNTVALUEIN;
assign inc_in = delay_INC;
assign ld_in = delay_LD;
assign ldpipeen_in = delay_LDPIPEEN;
assign regrst_in = delay_REGRST;
assign cinvctrl_in = delay_CINVCTRL;
assign datain_in = IS_DATAIN_INVERTED ^ delay_DATAIN;
assign idatain_in = IS_IDATAIN_INVERTED ^ delay_IDATAIN;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
// For simprims, the fixed/Default Delay values are taken from the sdf.
// if (IDELAY_TYPE == "FIXED")
// assign idelay_count = 0;
// else
// assign idelay_count = IDELAY_VALUE;
case (IDELAY_TYPE)
"VAR_LOAD", "VAR_LOAD_PIPE": assign idelay_count = 0;
"FIXED", "VARIABLE" : assign idelay_count = IDELAY_VALUE;
endcase
end
else if (gsr_in == 1'b0) begin
deassign idelay_count;
end
end
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- CINVCTRL_SEL check
case (CINVCTRL_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CINVCTRL_SEL on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL);
$finish;
end
endcase
//-------- DELAY_SRC check
if (DELAY_SRC != "DATAIN" && DELAY_SRC != "IDATAIN") begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC);
$finish;
end
//-------- HIGH_PERFORMANCE_MODE check
case (HIGH_PERFORMANCE_MODE)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE);
$finish;
end
endcase
//-------- IDELAY_TYPE check
if (IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE" && IDELAY_TYPE != "VAR_LOAD" && IDELAY_TYPE != "VAR_LOAD_PIPE") begin
$display("Attribute Syntax Error : The attribute IDELAY_TYPE on IDELAYE2 instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", IDELAY_TYPE);
$finish;
end
//-------- IDELAY_VALUE check
if (IDELAY_VALUE < MIN_DELAY_COUNT || IDELAY_VALUE > MAX_DELAY_COUNT) begin
$display("Attribute Syntax Error : The attribute IDELAY_VALUE on IDELAYE2 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", IDELAY_VALUE);
$finish;
end
//-------- PIPE_SEL check
case (PIPE_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute PIPE_SEL on IDELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL);
$finish;
end
endcase
//-------- REFCLK_FREQUENCY check
if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IDELAYE2 instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0", REFCLK_FREQUENCY);
$finish;
end
//-------- SIGNAL_PATTERN check
case (SIGNAL_PATTERN)
"CLOCK", "DATA" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IDELAYE2 instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN);
$finish;
end
endcase
//-------- CALC_TAPDELAY check
INIT_DELAY = 600;
end // initial begin
// CALC_TAPDELAY value
initial begin
if ((REFCLK_FREQUENCY <= MAX_REFCLK_FREQUENCYH) && (REFCLK_FREQUENCY >= MIN_REFCLK_FREQUENCYH))
begin
CALC_TAPDELAY = 52;
end
else
begin
CALC_TAPDELAY = 78;
end
end
//----------------------------------------------------------------------
//------------------------ Dynamic clock inversion ---------------------
//----------------------------------------------------------------------
// always @(c_in_pre or cinvctrl_in) begin
// case (CINVCTRL_SEL)
// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
// "FALSE" : c_in = c_in_pre;
// endcase
// end
generate
case (CINVCTRL_SEL)
"TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
"FALSE" : always @(c_in_pre) c_in = c_in_pre;
endcase
endgenerate
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(idelay_count) begin
// Fixed CNTVALUEOUT for when in FIXED mode because of simprim.
if(IDELAY_TYPE != "FIXED")
assign cntvalueout_pre = idelay_count;
else
assign cntvalueout_pre = IDELAY_VALUE;
end
//----------------------------------------------------------------------
//-------------------------- CNTVALUEIN LOAD --------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (regrst_in == 1'b1)
qcntvalueout_reg = 5'b0;
else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin
qcntvalueout_reg = CNTVALUEIN_INTEGER;
end
end // always @(posedge c_in)
generate
case (PIPE_SEL)
"TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg;
"FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER;
endcase
endgenerate
//----------------------------------------------------------------------
//-------------------------- IDELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (IDELAY_TYPE == "VARIABLE" | IDELAY_TYPE == "VAR_LOAD" | IDELAY_TYPE == "VAR_LOAD_PIPE") begin
if (ld_in == 1'b1) begin
case (IDELAY_TYPE)
"VARIABLE" : idelay_count = IDELAY_VALUE;
"VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux;
endcase
end
else if (ld_in == 1'b0 && ce_in == 1'b1) begin
if (inc_in == 1'b1) begin
case (IDELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (idelay_count < MAX_DELAY_COUNT)
idelay_count = idelay_count + 1;
else if (idelay_count == MAX_DELAY_COUNT)
idelay_count = MIN_DELAY_COUNT;
end
endcase
end
else if (inc_in == 1'b0) begin
case (IDELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (idelay_count > MIN_DELAY_COUNT)
idelay_count = idelay_count - 1;
else if (idelay_count == MIN_DELAY_COUNT)
idelay_count = MAX_DELAY_COUNT;
end
endcase
end
end
end //
end // always @ (posedge c_in)
always @(cntvaluein_in or gsr_in) begin
case (cntvaluein_in)
5'b00000 : assign CNTVALUEIN_INTEGER = 0;
5'b00001 : assign CNTVALUEIN_INTEGER = 1;
5'b00010 : assign CNTVALUEIN_INTEGER = 2;
5'b00011 : assign CNTVALUEIN_INTEGER = 3;
5'b00100 : assign CNTVALUEIN_INTEGER = 4;
5'b00101 : assign CNTVALUEIN_INTEGER = 5;
5'b00110 : assign CNTVALUEIN_INTEGER = 6;
5'b00111 : assign CNTVALUEIN_INTEGER = 7;
5'b01000 : assign CNTVALUEIN_INTEGER = 8;
5'b01001 : assign CNTVALUEIN_INTEGER = 9;
5'b01010 : assign CNTVALUEIN_INTEGER = 10;
5'b01011 : assign CNTVALUEIN_INTEGER = 11;
5'b01100 : assign CNTVALUEIN_INTEGER = 12;
5'b01101 : assign CNTVALUEIN_INTEGER = 13;
5'b01110 : assign CNTVALUEIN_INTEGER = 14;
5'b01111 : assign CNTVALUEIN_INTEGER = 15;
5'b10000 : assign CNTVALUEIN_INTEGER = 16;
5'b10001 : assign CNTVALUEIN_INTEGER = 17;
5'b10010 : assign CNTVALUEIN_INTEGER = 18;
5'b10011 : assign CNTVALUEIN_INTEGER = 19;
5'b10100 : assign CNTVALUEIN_INTEGER = 20;
5'b10101 : assign CNTVALUEIN_INTEGER = 21;
5'b10110 : assign CNTVALUEIN_INTEGER = 22;
5'b10111 : assign CNTVALUEIN_INTEGER = 23;
5'b11000 : assign CNTVALUEIN_INTEGER = 24;
5'b11001 : assign CNTVALUEIN_INTEGER = 25;
5'b11010 : assign CNTVALUEIN_INTEGER = 26;
5'b11011 : assign CNTVALUEIN_INTEGER = 27;
5'b11100 : assign CNTVALUEIN_INTEGER = 28;
5'b11101 : assign CNTVALUEIN_INTEGER = 29;
5'b11110 : assign CNTVALUEIN_INTEGER = 30;
5'b11111 : assign CNTVALUEIN_INTEGER = 31;
endcase
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(datain_in or idatain_in) begin
case (DELAY_SRC)
"IDATAIN" : begin
data_mux <= idatain_in;
end
"DATAIN" : begin
data_mux <= datain_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on X_IODELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC);
$finish;
end
endcase // case(DELAY_SRC)
end // always @(datain_in or idatain_in)
//*********************************************************
//*** DELAY IDATA signal
//*********************************************************
assign #(DELAY_D) delay_chain_0 = data_mux;
assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0;
assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1;
assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2;
assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3;
assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4;
assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5;
assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6;
assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7;
assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8;
assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9;
assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10;
assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11;
assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12;
assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13;
assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14;
assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15;
assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16;
assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17;
assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18;
assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19;
assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20;
assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21;
assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22;
assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23;
assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24;
assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25;
assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26;
assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27;
assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28;
assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29;
assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30;
//*********************************************************
//*** assign delay
//*********************************************************
always @(idelay_count) begin
case (idelay_count)
0: assign tap_out = delay_chain_0;
1: assign tap_out = delay_chain_1;
2: assign tap_out = delay_chain_2;
3: assign tap_out = delay_chain_3;
4: assign tap_out = delay_chain_4;
5: assign tap_out = delay_chain_5;
6: assign tap_out = delay_chain_6;
7: assign tap_out = delay_chain_7;
8: assign tap_out = delay_chain_8;
9: assign tap_out = delay_chain_9;
10: assign tap_out = delay_chain_10;
11: assign tap_out = delay_chain_11;
12: assign tap_out = delay_chain_12;
13: assign tap_out = delay_chain_13;
14: assign tap_out = delay_chain_14;
15: assign tap_out = delay_chain_15;
16: assign tap_out = delay_chain_16;
17: assign tap_out = delay_chain_17;
18: assign tap_out = delay_chain_18;
19: assign tap_out = delay_chain_19;
20: assign tap_out = delay_chain_20;
21: assign tap_out = delay_chain_21;
22: assign tap_out = delay_chain_22;
23: assign tap_out = delay_chain_23;
24: assign tap_out = delay_chain_24;
25: assign tap_out = delay_chain_25;
26: assign tap_out = delay_chain_26;
27: assign tap_out = delay_chain_27;
28: assign tap_out = delay_chain_28;
29: assign tap_out = delay_chain_29;
30: assign tap_out = delay_chain_30;
31: assign tap_out = delay_chain_31;
default:
assign tap_out = delay_chain_0;
endcase
end // always @ (idelay_count)
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier) begin
tap_out <= 1'bx;
end
`endif // ifdef XIL_TIMING
specify
( C *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( C => DATAOUT) = (0:0:0, 0:0:0);
( CINVCTRL *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( CINVCTRL => DATAOUT) = (100:100:100, 100:100:100);
( DATAIN => DATAOUT) = (100:100:100, 100:100:100);
( IDATAIN => DATAOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDELAYE2
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDELAYE2_FINEDELAY.v 0000664 0000000 0000000 00000061064 12327044266 0024147 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Input Fixed or Variable Delay Element with Fine Adjustment.
// /___/ /\ Filename : IDELAYE2_FINEDELAY.v
// \ \ / \ Timestamp : Tue Feb 15 15:52:17 PST 2011
// \___\/\___\
//
// Revision:
// 02/15/11 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDELAYE2_FINEDELAY (
CNTVALUEOUT,
DATAOUT,
C,
CE,
CINVCTRL,
CNTVALUEIN,
DATAIN,
IDATAIN,
IFDLY,
INC,
LD,
LDPIPEEN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "IDATAIN";
parameter FINEDELAY = "BYPASS";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter IDELAY_TYPE = "FIXED";
parameter integer IDELAY_VALUE = 0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT;
output DATAOUT;
input C;
input CE;
input CINVCTRL;
input [4:0] CNTVALUEIN;
input DATAIN;
input IDATAIN;
input [2:0] IFDLY;
input INC;
input LD;
input LDPIPEEN;
input REGRST;
tri0 GSR = glbl.GSR;
real CALC_TAPDELAY_RD ; // regular tap delay
real CALC_TAPDELAY_FD ; // fine tap delay
real INIT_DELAY_RD;
real INIT_DELAY_FD;
//------------------- constants ------------------------------------
localparam MAX_DELAY_COUNT = 31;
localparam MIN_DELAY_COUNT = 0;
localparam MAX_REFCLK_FREQUENCYL = 210.0;
localparam MIN_REFCLK_FREQUENCYL = 190.0;
localparam MAX_REFCLK_FREQUENCYH = 310.0;
localparam MIN_REFCLK_FREQUENCYH = 290.0;
//------------------- variable declaration -------------------------
integer idelay_count;
integer CNTVALUEIN_INTEGER;
reg [4:0] cntvalueout_pre;
reg notifier;
reg data_mux = 0;
reg tap_out_rd = 0;
reg tap_out_fd = 0;
reg tap_out_final = 0;
reg DATAOUT_reg = 0;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31;
wire fine_delay_0, fine_delay_1, fine_delay_2, fine_delay_3, fine_delay_4;
reg c_in;
wire ce_in,delay_ce,delay_c;
wire clkin_in;
wire [4:0] cntvaluein_in,delay_cntvaluein;
wire datain_in,delay_datain;
wire [2:0] ifdly_in,delay_ifdly;
wire gsr_in;
wire idatain_in,delay_idatain;
wire inc_in,delay_inc;
wire odatain_in;
wire ld_in,delay_ld;
wire t_in;
wire cinvctrl_in,delay_cinvctrl;
wire ldpipeen_in,delay_ldpipeen;
wire regrst_in,delay_regrst;
wire c_in_pre;
reg [4:0] qcntvalueout_reg = 5'b0;
reg [4:0] qcntvalueout_mux = 5'b0;
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
generate
case (FINEDELAY)
"BYPASS" : always @(tap_out_rd) tap_out_final = tap_out_rd;
"ADD_DLY" : always @(tap_out_fd) tap_out_final = tap_out_fd;
endcase
endgenerate
// CR 587496
// assign #INIT_DELAY DATAOUT = tap_out_final;
always @(tap_out_final)
DATAOUT_reg <= #INIT_DELAY_RD tap_out_final;
assign DATAOUT = DATAOUT_reg;
assign CNTVALUEOUT = cntvalueout_pre;
`ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign delay_c = C;
assign delay_ce = CE;
assign delay_cntvaluein = CNTVALUEIN;
assign delay_inc = INC;
assign delay_ld = LD;
assign delay_ldpipeen = LDPIPEEN;
assign delay_regrst = REGRST;
`endif // ifndef XIL_TIMING
assign delay_cinvctrl = CINVCTRL;
assign delay_datain = DATAIN;
assign delay_ifdly = IFDLY;
assign delay_idatain = IDATAIN;
assign gsr_in = GSR;
assign c_in_pre = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign cntvaluein_in = delay_cntvaluein;
assign inc_in = delay_inc;
assign ld_in = delay_ld;
assign ldpipeen_in = delay_ldpipeen;
assign regrst_in = delay_regrst;
assign cinvctrl_in = delay_cinvctrl;
assign datain_in = IS_DATAIN_INVERTED ^ delay_datain;
assign ifdly_in = delay_ifdly;
assign idatain_in = IS_IDATAIN_INVERTED ^ delay_idatain;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
// For simprims, the fixed/Default Delay values are taken from the sdf.
if (IDELAY_TYPE == "FIXED")
assign idelay_count = 0;
else
assign idelay_count = IDELAY_VALUE;
end
else if (gsr_in == 1'b0) begin
deassign idelay_count;
end
end
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- CINVCTRL_SEL check
case (CINVCTRL_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CINVCTRL_SEL on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL);
$finish;
end
endcase
//-------- DELAY_SRC check
if (DELAY_SRC != "DATAIN" && DELAY_SRC != "IDATAIN") begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC);
$finish;
end
//-------- FINEDELAY check
if (FINEDELAY != "BYPASS" && FINEDELAY != "ADD_DLY") begin
$display("Attribute Syntax Error : The attribute FINEDELAY on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are BYPASS or ADD_DLY", FINEDELAY);
$finish;
end
//-------- HIGH_PERFORMANCE_MODE check
case (HIGH_PERFORMANCE_MODE)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE);
$finish;
end
endcase
//-------- IDELAY_TYPE check
if (IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE" && IDELAY_TYPE != "VAR_LOAD" && IDELAY_TYPE != "VAR_LOAD_PIPE") begin
$display("Attribute Syntax Error : The attribute IDELAY_TYPE on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", IDELAY_TYPE);
$finish;
end
//-------- IDELAY_VALUE check
if (IDELAY_VALUE < MIN_DELAY_COUNT || IDELAY_VALUE > MAX_DELAY_COUNT) begin
$display("Attribute Syntax Error : The attribute IDELAY_VALUE on IDELAYE2_FINEDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", IDELAY_VALUE);
$finish;
end
//-------- PIPE_SEL check
case (PIPE_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute PIPE_SEL on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL);
$finish;
end
endcase
//-------- REFCLK_FREQUENCY check
if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IDELAYE2_FINEDELAY instance %m is set to %f. Legal values for this attribute are 175.0 to 225.0", REFCLK_FREQUENCY);
$finish;
end
//-------- SIGNAL_PATTERN check
case (SIGNAL_PATTERN)
"CLOCK", "DATA" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IDELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN);
$finish;
end
endcase
//-------- CALC_TAPDELAY check
INIT_DELAY_RD = 600; //regular delay
INIT_DELAY_FD = 40; //fine delay
end // initial begin
// CALC_TAPDELAY value
initial begin
if ((REFCLK_FREQUENCY <= MAX_REFCLK_FREQUENCYH) && (REFCLK_FREQUENCY >= MIN_REFCLK_FREQUENCYH))
begin
CALC_TAPDELAY_RD = 52;
end
else
begin
CALC_TAPDELAY_RD = 78;
end
CALC_TAPDELAY_FD = 10; //fine delay
end
//----------------------------------------------------------------------
//------------------------ Dynamic clock inversion ---------------------
//----------------------------------------------------------------------
// always @(c_in_pre or cinvctrl_in) begin
// case (CINVCTRL_SEL)
// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
// "FALSE" : c_in = c_in_pre;
// endcase
// end
generate
case (CINVCTRL_SEL)
"TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
"FALSE" : always @(c_in_pre) c_in = c_in_pre;
endcase
endgenerate
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(idelay_count) begin
// Fixed CNTVALUEOUT for when in FIXED mode because of simprim.
if(IDELAY_TYPE != "FIXED")
assign cntvalueout_pre = idelay_count;
else
assign cntvalueout_pre = IDELAY_VALUE;
end
//----------------------------------------------------------------------
//-------------------------- CNTVALUEIN LOAD --------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (regrst_in == 1'b1)
qcntvalueout_reg = 5'b0;
else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin
qcntvalueout_reg = CNTVALUEIN_INTEGER;
end
end // always @(posedge c_in)
generate
case (PIPE_SEL)
"TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg;
"FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER;
endcase
endgenerate
//----------------------------------------------------------------------
//-------------------------- IDELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (IDELAY_TYPE == "VARIABLE" | IDELAY_TYPE == "VAR_LOAD" | IDELAY_TYPE == "VAR_LOAD_PIPE") begin
if (ld_in == 1'b1) begin
case (IDELAY_TYPE)
"VARIABLE" : idelay_count = IDELAY_VALUE;
"VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux;
endcase
end
else if (ld_in == 1'b0 && ce_in == 1'b1) begin
if (inc_in == 1'b1) begin
case (IDELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (idelay_count < MAX_DELAY_COUNT)
idelay_count = idelay_count + 1;
else if (idelay_count == MAX_DELAY_COUNT)
idelay_count = MIN_DELAY_COUNT;
end
endcase
end
else if (inc_in == 1'b0) begin
case (IDELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (idelay_count > MIN_DELAY_COUNT)
idelay_count = idelay_count - 1;
else if (idelay_count == MIN_DELAY_COUNT)
idelay_count = MAX_DELAY_COUNT;
end
endcase
end
end
end //
end // always @ (posedge c_in)
always @(cntvaluein_in or gsr_in) begin
case (cntvaluein_in)
5'b00000 : assign CNTVALUEIN_INTEGER = 0;
5'b00001 : assign CNTVALUEIN_INTEGER = 1;
5'b00010 : assign CNTVALUEIN_INTEGER = 2;
5'b00011 : assign CNTVALUEIN_INTEGER = 3;
5'b00100 : assign CNTVALUEIN_INTEGER = 4;
5'b00101 : assign CNTVALUEIN_INTEGER = 5;
5'b00110 : assign CNTVALUEIN_INTEGER = 6;
5'b00111 : assign CNTVALUEIN_INTEGER = 7;
5'b01000 : assign CNTVALUEIN_INTEGER = 8;
5'b01001 : assign CNTVALUEIN_INTEGER = 9;
5'b01010 : assign CNTVALUEIN_INTEGER = 10;
5'b01011 : assign CNTVALUEIN_INTEGER = 11;
5'b01100 : assign CNTVALUEIN_INTEGER = 12;
5'b01101 : assign CNTVALUEIN_INTEGER = 13;
5'b01110 : assign CNTVALUEIN_INTEGER = 14;
5'b01111 : assign CNTVALUEIN_INTEGER = 15;
5'b10000 : assign CNTVALUEIN_INTEGER = 16;
5'b10001 : assign CNTVALUEIN_INTEGER = 17;
5'b10010 : assign CNTVALUEIN_INTEGER = 18;
5'b10011 : assign CNTVALUEIN_INTEGER = 19;
5'b10100 : assign CNTVALUEIN_INTEGER = 20;
5'b10101 : assign CNTVALUEIN_INTEGER = 21;
5'b10110 : assign CNTVALUEIN_INTEGER = 22;
5'b10111 : assign CNTVALUEIN_INTEGER = 23;
5'b11000 : assign CNTVALUEIN_INTEGER = 24;
5'b11001 : assign CNTVALUEIN_INTEGER = 25;
5'b11010 : assign CNTVALUEIN_INTEGER = 26;
5'b11011 : assign CNTVALUEIN_INTEGER = 27;
5'b11100 : assign CNTVALUEIN_INTEGER = 28;
5'b11101 : assign CNTVALUEIN_INTEGER = 29;
5'b11110 : assign CNTVALUEIN_INTEGER = 30;
5'b11111 : assign CNTVALUEIN_INTEGER = 31;
endcase
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(datain_in or idatain_in) begin
case (DELAY_SRC)
"IDATAIN" : begin
data_mux <= idatain_in;
end
"DATAIN" : begin
data_mux <= datain_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on X_IODELAYE2 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC);
$finish;
end
endcase // case(DELAY_SRC)
end // always @(datain_in or idatain_in)
//*********************************************************
//*** DELAY IDATA signal
//*********************************************************
assign #(DELAY_D) delay_chain_0 = data_mux;
assign #CALC_TAPDELAY_RD delay_chain_1 = delay_chain_0;
assign #CALC_TAPDELAY_RD delay_chain_2 = delay_chain_1;
assign #CALC_TAPDELAY_RD delay_chain_3 = delay_chain_2;
assign #CALC_TAPDELAY_RD delay_chain_4 = delay_chain_3;
assign #CALC_TAPDELAY_RD delay_chain_5 = delay_chain_4;
assign #CALC_TAPDELAY_RD delay_chain_6 = delay_chain_5;
assign #CALC_TAPDELAY_RD delay_chain_7 = delay_chain_6;
assign #CALC_TAPDELAY_RD delay_chain_8 = delay_chain_7;
assign #CALC_TAPDELAY_RD delay_chain_9 = delay_chain_8;
assign #CALC_TAPDELAY_RD delay_chain_10 = delay_chain_9;
assign #CALC_TAPDELAY_RD delay_chain_11 = delay_chain_10;
assign #CALC_TAPDELAY_RD delay_chain_12 = delay_chain_11;
assign #CALC_TAPDELAY_RD delay_chain_13 = delay_chain_12;
assign #CALC_TAPDELAY_RD delay_chain_14 = delay_chain_13;
assign #CALC_TAPDELAY_RD delay_chain_15 = delay_chain_14;
assign #CALC_TAPDELAY_RD delay_chain_16 = delay_chain_15;
assign #CALC_TAPDELAY_RD delay_chain_17 = delay_chain_16;
assign #CALC_TAPDELAY_RD delay_chain_18 = delay_chain_17;
assign #CALC_TAPDELAY_RD delay_chain_19 = delay_chain_18;
assign #CALC_TAPDELAY_RD delay_chain_20 = delay_chain_19;
assign #CALC_TAPDELAY_RD delay_chain_21 = delay_chain_20;
assign #CALC_TAPDELAY_RD delay_chain_22 = delay_chain_21;
assign #CALC_TAPDELAY_RD delay_chain_23 = delay_chain_22;
assign #CALC_TAPDELAY_RD delay_chain_24 = delay_chain_23;
assign #CALC_TAPDELAY_RD delay_chain_25 = delay_chain_24;
assign #CALC_TAPDELAY_RD delay_chain_26 = delay_chain_25;
assign #CALC_TAPDELAY_RD delay_chain_27 = delay_chain_26;
assign #CALC_TAPDELAY_RD delay_chain_28 = delay_chain_27;
assign #CALC_TAPDELAY_RD delay_chain_29 = delay_chain_28;
assign #CALC_TAPDELAY_RD delay_chain_30 = delay_chain_29;
assign #CALC_TAPDELAY_RD delay_chain_31 = delay_chain_30;
//*********************************************************
//*** assign delay
//*********************************************************
always @(idelay_count) begin
case (idelay_count)
0: assign tap_out_rd = delay_chain_0;
1: assign tap_out_rd = delay_chain_1;
2: assign tap_out_rd = delay_chain_2;
3: assign tap_out_rd = delay_chain_3;
4: assign tap_out_rd = delay_chain_4;
5: assign tap_out_rd = delay_chain_5;
6: assign tap_out_rd = delay_chain_6;
7: assign tap_out_rd = delay_chain_7;
8: assign tap_out_rd = delay_chain_8;
9: assign tap_out_rd = delay_chain_9;
10: assign tap_out_rd = delay_chain_10;
11: assign tap_out_rd = delay_chain_11;
12: assign tap_out_rd = delay_chain_12;
13: assign tap_out_rd = delay_chain_13;
14: assign tap_out_rd = delay_chain_14;
15: assign tap_out_rd = delay_chain_15;
16: assign tap_out_rd = delay_chain_16;
17: assign tap_out_rd = delay_chain_17;
18: assign tap_out_rd = delay_chain_18;
19: assign tap_out_rd = delay_chain_19;
20: assign tap_out_rd = delay_chain_20;
21: assign tap_out_rd = delay_chain_21;
22: assign tap_out_rd = delay_chain_22;
23: assign tap_out_rd = delay_chain_23;
24: assign tap_out_rd = delay_chain_24;
25: assign tap_out_rd = delay_chain_25;
26: assign tap_out_rd = delay_chain_26;
27: assign tap_out_rd = delay_chain_27;
28: assign tap_out_rd = delay_chain_28;
29: assign tap_out_rd = delay_chain_29;
30: assign tap_out_rd = delay_chain_30;
31: assign tap_out_rd = delay_chain_31;
default:
assign tap_out_rd = delay_chain_0;
endcase
end // always @ (idelay_count)
//*********************************************************
//*** FINE DELAY signal
//*********************************************************
assign #(INIT_DELAY_FD) fine_delay_0 = tap_out_rd;
assign #CALC_TAPDELAY_FD fine_delay_1 = fine_delay_0;
assign #CALC_TAPDELAY_FD fine_delay_2 = fine_delay_1;
assign #CALC_TAPDELAY_FD fine_delay_3 = fine_delay_2;
assign #CALC_TAPDELAY_FD fine_delay_4 = fine_delay_3;
assign #CALC_TAPDELAY_FD fine_delay_5 = fine_delay_4;
always @(ifdly_in) begin
case (ifdly_in)
3'b000: assign tap_out_fd = fine_delay_0;
3'b001: assign tap_out_fd = fine_delay_1;
3'b010: assign tap_out_fd = fine_delay_2;
3'b011: assign tap_out_fd = fine_delay_3;
3'b100: assign tap_out_fd = fine_delay_4;
default:
assign tap_out_fd = 1'bx;
endcase
end // always @ (ifdly_in)
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier) begin
tap_out_rd <= 1'bx;
end
`endif // ifdef XIL_TIMING
specify
( C *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( C => DATAOUT) = (0:0:0, 0:0:0);
( CINVCTRL *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( CINVCTRL => DATAOUT) = (100:100:100, 100:100:100);
( DATAIN => DATAOUT) = (100:100:100, 100:100:100);
( IDATAIN => DATAOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDELAYE2_FINEDELAY
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IDELAYE3.v 0000664 0000000 0000000 00000067464 12327044266 0022602 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Input Fixed or Variable Delay Element
// /___/ /\ Filename : IDELAYE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IDELAYE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE = "NONE",
parameter DELAY_FORMAT = "TIME",
parameter DELAY_SRC = "IDATAIN",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REFCLK_FREQUENCY = 300.0,
parameter UPDATE_MODE = "ASYNC"
)(
output CASC_OUT,
output [8:0] CNTVALUEOUT,
output DATAOUT,
input CASC_IN,
input CASC_RETURN,
input CE,
input CLK,
input [8:0] CNTVALUEIN,
input DATAIN,
input EN_VTC,
input IDATAIN,
input INC,
input LOAD,
input RST
);
// define constants
localparam MODULE_NAME = "IDELAYE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
localparam MAX_DELAY_COUNT = 511;
localparam MIN_DELAY_COUNT = 0;
localparam PER_BIT_FINE_DELAY = 5;
localparam PER_BIT_MEDIUM_DELAY = 40;
localparam INTRINSIC_FINE_DELAY = 90;
localparam INTRINSIC_MEDIUM_DELAY = 40;
localparam IDATAIN_INTRINSIC_DELAY = 30;
localparam DATAIN_INTRINSIC_DELAY = 50;
localparam CASC_IN_INTRINSIC_DELAY = 50;
//localparam CASC_RET_INTRINSIC_DELAY = 50;
localparam CASC_RET_INTRINSIC_DELAY = 0;
localparam DATA_OUT_INTRINSIC_DELAY = 40;
localparam CASC_OUT_INTRINSIC_DELAY = 40;
// Parameter encodings and registers
localparam CASCADE_MASTER = 2'b11;
localparam CASCADE_NONE = 2'b00;
localparam CASCADE_SLAVE_END = 2'b01;
localparam CASCADE_SLAVE_MIDDLE = 2'b10;
localparam DELAY_FORMAT_COUNT = 1;
localparam DELAY_FORMAT_TIME = 0;
localparam DELAY_SRC_DATAIN = 1;
localparam DELAY_SRC_IDATAIN = 0;
localparam DELAY_TYPE_FIXED = 2'b00;
localparam DELAY_TYPE_VARIABLE = 2'b01;
localparam DELAY_TYPE_VAR_LOAD = 2'b10;
localparam DELAY_VALUE_0 = 0;
localparam UPDATE_MODE_ASYNC = 2'b00;
localparam UPDATE_MODE_MANUAL = 2'b01;
localparam UPDATE_MODE_SYNC = 2'b10;
`ifndef XIL_DR
localparam CASCADE_REG = CASCADE;
localparam DELAY_FORMAT_REG = DELAY_FORMAT;
localparam DELAY_SRC_REG = DELAY_SRC;
localparam DELAY_TYPE_REG = DELAY_TYPE;
localparam DELAY_VALUE_REG = DELAY_VALUE;
localparam IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam UPDATE_MODE_REG = UPDATE_MODE;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
`endif
wire [1:0] CASCADE_BIN;
wire DELAY_FORMAT_BIN;
wire DELAY_SRC_BIN;
wire [1:0] DELAY_TYPE_BIN;
//wire DELAY_VALUE_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [1:0] UPDATE_MODE_BIN;
wire [63:0] REFCLK_FREQUENCY_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IDELAYE3_dr.v"
`endif
reg CASC_OUT_reg;
reg DATAOUT_reg;
reg [8:0] CNTVALUEOUT_reg;
reg [8:0] qcntvalueout_reg = 9'b0;
reg tap_out;
reg clk_smux;
reg tap_out_casc_out_none;
reg tap_out_casc_out;
reg tap_out_data_out;
reg data_mux = 0;
wire CASC_OUT_delay;
wire DATAOUT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CASC_IN_in;
wire CASC_RETURN_in;
wire CE_in;
wire CLK_in;
wire DATAIN_in;
wire EN_VTC_in;
wire IDATAIN_in;
wire INC_in;
wire LOAD_in;
wire RST_in;
reg RST_sync1;
reg RST_sync2;
reg RST_sync3;
wire [8:0] CNTVALUEIN_in;
wire gsr_in;
reg [8:0] idelay_count_async;
reg [8:0] idelay_count_sync;
reg [8:0] cntvalue_updated;
reg [8:0] cntvalue_updated_sync;
reg [8:0] cntvalue_updated_async;
reg [8:0] cascade_mode_delay;
reg [8:0] idelay_count_pre;
reg [8:0] CNTVALUEIN_INTEGER;
time delay_value;
time delay_value_casc_out;
time delay_value_data_out;
wire CASC_IN_delay;
wire CASC_RETURN_delay;
wire CE_delay;
wire CLK_delay;
wire DATAIN_delay;
wire EN_VTC_delay;
wire IDATAIN_delay;
wire INC_delay;
wire LOAD_delay;
wire RST_delay;
wire [8:0] CNTVALUEIN_delay;
// input output assignments
assign #(out_delay) CASC_OUT = CASC_OUT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) DATAOUT = DATAOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_delay = LOAD;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) CASC_IN_delay = CASC_IN;
assign #(in_delay) CASC_RETURN_delay = CASC_RETURN;
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) IDATAIN_delay = IDATAIN;
assign CASC_OUT_delay = CASC_OUT_reg;
assign CNTVALUEOUT_delay = CNTVALUEOUT_reg;
assign DATAOUT_delay = DATAOUT_reg;
assign CASC_IN_in = CASC_IN_delay;
assign CASC_RETURN_in = CASC_RETURN_delay;
assign CE_in = CE_delay;
assign CLK_in = IS_CLK_INVERTED_BIN ? ~CLK_delay : CLK_delay;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign DATAIN_in = DATAIN_delay;
assign EN_VTC_in = EN_VTC_delay;
assign IDATAIN_in = IDATAIN_delay;
assign INC_in = INC_delay;
assign LOAD_in = LOAD_delay;
assign RST_in = IS_RST_INVERTED_BIN ? ~RST_delay : RST_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CASCADE_BIN =
(CASCADE_REG == "NONE") ? CASCADE_NONE :
(CASCADE_REG == "MASTER") ? CASCADE_MASTER :
(CASCADE_REG == "SLAVE_END") ? CASCADE_SLAVE_END :
(CASCADE_REG == "SLAVE_MIDDLE") ? CASCADE_SLAVE_MIDDLE :
CASCADE_NONE;
assign DELAY_FORMAT_BIN =
(DELAY_FORMAT_REG == "TIME") ? DELAY_FORMAT_TIME :
(DELAY_FORMAT_REG == "COUNT") ? DELAY_FORMAT_COUNT :
DELAY_FORMAT_TIME;
assign DELAY_SRC_BIN =
(DELAY_SRC_REG == "IDATAIN") ? DELAY_SRC_IDATAIN :
(DELAY_SRC_REG == "DATAIN") ? DELAY_SRC_DATAIN :
DELAY_SRC_IDATAIN;
assign DELAY_TYPE_BIN =
(DELAY_TYPE_REG == "FIXED") ? DELAY_TYPE_FIXED :
(DELAY_TYPE_REG == "VARIABLE") ? DELAY_TYPE_VARIABLE :
(DELAY_TYPE_REG == "VAR_LOAD") ? DELAY_TYPE_VAR_LOAD :
DELAY_TYPE_FIXED;
// assign DELAY_VALUE_BIN =
// (DELAY_VALUE_REG == 0) ? DELAY_VALUE_0 :
// DELAY_VALUE_0;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign REFCLK_FREQUENCY_BIN = $realtobits(REFCLK_FREQUENCY_REG);
assign UPDATE_MODE_BIN =
(UPDATE_MODE_REG == "ASYNC") ? UPDATE_MODE_ASYNC :
(UPDATE_MODE_REG == "MANUAL") ? UPDATE_MODE_MANUAL :
(UPDATE_MODE_REG == "SYNC") ? UPDATE_MODE_SYNC :
UPDATE_MODE_ASYNC;
always @ (trig_attr) begin
#1;
case (CASCADE_REG) // string
"NONE" : /* */;
"MASTER" : /* */;
"SLAVE_END" : /* */;
"SLAVE_MIDDLE" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on %s instance %m is set to %s. Legal values for this attribute are NONE, MASTER, SLAVE_END or SLAVE_MIDDLE.", MODULE_NAME, CASCADE_REG);
attr_err = 1'b1;
end
endcase
case (DELAY_FORMAT_REG) // string
"TIME" : /* */;
"COUNT" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
endcase
case (DELAY_SRC_REG) // string
"IDATAIN" : /* */;
"DATAIN" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on %s instance %m is set to %s. Legal values for this attribute are IDATAIN or DATAIN.", MODULE_NAME, DELAY_SRC_REG);
attr_err = 1'b1;
end
endcase
case (DELAY_TYPE_REG) // string
"FIXED" : /* */;
"VARIABLE" : /* */;
"VAR_LOAD" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((DELAY_VALUE_REG >= 0) && (DELAY_VALUE_REG <= 1250)) // decimal
/* */;
else begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_REG, 0);
attr_err = 1'b1;
end
case (UPDATE_MODE_REG) // string
"ASYNC" : /* */;
"MANUAL" : /* */;
"SYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CLK_INVERTED_REG == 1'b0) || (IS_CLK_INVERTED_REG == 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG == 1'b0) || (IS_RST_INVERTED_REG == 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (REFCLK_FREQUENCY_REG >= 300.0 && REFCLK_FREQUENCY_REG <= 1333.0) // float
/* */;
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME)
if ((DELAY_VALUE_REG == 0) || (REFCLK_FREQUENCY_REG == 0)) begin
idelay_count_pre = 0;
cntvalue_updated = idelay_count_pre;
end
else begin
idelay_count_pre = DELAY_VALUE_REG/2.446;
cntvalue_updated = idelay_count_pre;
end
else if (DELAY_FORMAT_BIN == DELAY_FORMAT_COUNT) begin
idelay_count_pre = DELAY_VALUE_REG;
cntvalue_updated = idelay_count_pre;
end
end
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
always @(tap_out or tap_out_data_out or tap_out_casc_out or tap_out_casc_out_none or CASCADE_REG) begin
case (CASCADE_REG)
"MASTER","SLAVE_MIDDLE" : begin
DATAOUT_reg <= #(DATA_OUT_INTRINSIC_DELAY) tap_out_data_out;
CASC_OUT_reg <= #(CASC_OUT_INTRINSIC_DELAY) tap_out_casc_out;
end
"NONE","SLAVE_END" : begin
DATAOUT_reg <= #(DATA_OUT_INTRINSIC_DELAY) tap_out;
CASC_OUT_reg <= #(CASC_OUT_INTRINSIC_DELAY) tap_out_casc_out_none;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on IDELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
end // always @(tap_out or CASC_RETURN_in)
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign gsr_in = glblGSR;
//*** GLOBAL hidden GSR pin
always @(gsr_in or RST_in) begin
if (gsr_in == 1'b1 || RST_in == 1'b1) begin
assign idelay_count_sync = idelay_count_pre;
assign idelay_count_async = idelay_count_pre;
assign cntvalue_updated_sync = idelay_count_pre;
assign cntvalue_updated_async = idelay_count_pre;
end
else if (gsr_in == 1'b0 || RST_in == 1'b0) begin
deassign idelay_count_sync;
deassign idelay_count_async;
deassign cntvalue_updated_sync;
deassign cntvalue_updated_async;
end
end
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(idelay_count_sync or idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin
case (UPDATE_MODE_REG)
"SYNC" : begin
assign CNTVALUEOUT_reg = idelay_count_sync;
assign cntvalue_updated = cntvalue_updated_sync;
end
"ASYNC" , "MANUAL" : begin
assign CNTVALUEOUT_reg = idelay_count_async;
assign cntvalue_updated = cntvalue_updated_async;
end
default: $display("Attribute Syntax Error:UPDATE_MODE_REG=%s is not valid value\n",UPDATE_MODE_REG);
endcase
end
//----------------------------------------------------------------------
//-------------------------- DELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(CLK_in or RST_in or RST_sync3 or RST_sync2 or RST_sync1) begin
if (RST_in == 1'b1 || RST_sync3 == 1'b1 || RST_sync2 == 1'b1 || RST_sync1 == 1'b1)
clk_smux <= 1'b0;
else if (RST_sync3 == 1'b0)
clk_smux <= CLK_in;
end
always @(posedge CLK_in) begin
RST_sync1 <= RST_in;
RST_sync2 <= RST_sync1;
RST_sync3 <= RST_sync2;
end
always @(posedge clk_smux) begin
if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin
case(DELAY_TYPE_REG)
"FIXED": ; //Do nothing.
"VAR_LOAD":
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_async > MIN_DELAY_COUNT)
idelay_count_async = idelay_count_async-1;
else if (idelay_count_async == MIN_DELAY_COUNT)
idelay_count_async = MAX_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b011:
begin //{
if (idelay_count_async < MAX_DELAY_COUNT)
idelay_count_async = idelay_count_async + 1;
else if (idelay_count_async == MAX_DELAY_COUNT)
idelay_count_async = MIN_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b100, 3'b101:
begin //{
idelay_count_async = CNTVALUEIN_INTEGER;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b110:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else cntvalue_updated_async = idelay_count_async;
3'b111:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else idelay_count_async = idelay_count_async + CNTVALUEIN_INTEGER;
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b INC = %b \n", LOAD_in,CE_in,INC_in);
endcase
"VARIABLE":
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_async > MIN_DELAY_COUNT)
idelay_count_async = idelay_count_async-1;
else if (idelay_count_async == MIN_DELAY_COUNT)
idelay_count_async = MAX_DELAY_COUNT;
cntvalue_updated_async = idelay_count_async;
end //}
3'b011:
begin //{
if (idelay_count_async < MAX_DELAY_COUNT)
idelay_count_async = idelay_count_async + 1;
else if (idelay_count_async == MAX_DELAY_COUNT)
idelay_count_async = MIN_DELAY_COUNT;
cntvalue_updated_async = idelay_count_async;
end //}
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b, INC = %b, DELAY_TYPE=%s \n",LOAD_in,CE_in,INC_in,DELAY_TYPE_REG);
endcase
default: $display("FAILURE: DELAY_TYPE=%s is not a valid value\n",DELAY_TYPE_REG);
endcase
end
end // always @ (posedge CLK_in)
always @(posedge data_mux) begin
if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin
if (UPDATE_MODE_BIN == UPDATE_MODE_SYNC) begin
case (DELAY_TYPE_REG)
"VAR_LOAD" : begin
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_sync > MIN_DELAY_COUNT)
idelay_count_sync = idelay_count_sync-1;
else if (idelay_count_sync == MIN_DELAY_COUNT)
idelay_count_sync = MAX_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b011:
begin //{
if (idelay_count_sync < MAX_DELAY_COUNT)
idelay_count_sync = idelay_count_sync + 1;
else if (idelay_count_sync == MAX_DELAY_COUNT)
idelay_count_sync = MIN_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b100, 3'b101:
begin //{
idelay_count_sync = CNTVALUEIN_INTEGER;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b110:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else cntvalue_updated_sync = idelay_count_sync;
3'b111:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else idelay_count_sync = idelay_count_sync + CNTVALUEIN_INTEGER;
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b INC = %b \n",LOAD_in,CE_in,INC_in);
endcase
end
default : begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE = %s on IDELAYE3 instance %m is not supported for DELAY_TYPE set to %s. ", UPDATE_MODE_REG,DELAY_TYPE_REG);
$finish;
end
endcase
end
end // UPDATE_MODE_REG
// end //else if
end //always
always @(CNTVALUEIN_in or gsr_in) begin
assign CNTVALUEIN_INTEGER = CNTVALUEIN_in;
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(DATAIN_in or IDATAIN_in or CASC_IN_in or CASCADE_REG) begin
case (CASCADE_REG)
"NONE", "MASTER" : begin
case (DELAY_SRC_REG)
"IDATAIN" : begin
data_mux <= IDATAIN_in;
end
"DATAIN" : begin
data_mux <= DATAIN_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE3 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC_REG);
$finish;
end
endcase // case(IDELAY_SRC_reg)
end
"SLAVE_END", "SLAVE_MIDDLE" : begin
data_mux <= CASC_IN_in;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on IDELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
end // always @(DATAIN_in or IDATAIN_in or CASC_IN_in)
always @ (cntvalue_updated or data_mux or CASC_RETURN_in or DELAY_FORMAT_REG) begin
if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME) begin
delay_value = (cntvalue_updated*2.446) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
cascade_mode_delay = cntvalue_updated*2.446;
delay_value_casc_out = cascade_mode_delay/2 + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
if (cascade_mode_delay % 2 == 1)
delay_value_data_out = cascade_mode_delay/2 + 1;
else
delay_value_data_out = cascade_mode_delay/2;
end else begin
delay_value = (cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
cascade_mode_delay = (cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY);
delay_value_casc_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2 + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
if (cascade_mode_delay % 2 == 1)
delay_value_data_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2 + 1;
else
delay_value_data_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2;
end
case (CASCADE_REG)
"NONE", "MASTER" : begin
case (DELAY_SRC_REG)
"IDATAIN" : begin
delay_value = delay_value + IDATAIN_INTRINSIC_DELAY;
delay_value_casc_out = delay_value_casc_out + IDATAIN_INTRINSIC_DELAY;
end
"DATAIN" : begin
delay_value = delay_value + DATAIN_INTRINSIC_DELAY;
delay_value_casc_out = delay_value_casc_out + DATAIN_INTRINSIC_DELAY;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on IDELAYE3 instance %m is set to %s. Legal values for this attribute are DATAIN or IDATAIN", DELAY_SRC_REG);
$finish;
end
endcase // case(DELAY_SRC_reg)
end
"SLAVE_END", "SLAVE_MIDDLE" : begin
delay_value = delay_value + CASC_IN_INTRINSIC_DELAY;
delay_value_casc_out = delay_value_casc_out + CASC_IN_INTRINSIC_DELAY;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on IDELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
tap_out <= #delay_value data_mux;
if (cntvalue_updated[8:3] >= 6'b011111 ) begin
tap_out_casc_out_none <= #delay_value_casc_out data_mux;
end
else begin
tap_out_casc_out_none <= 1'b0;
end
if (cntvalue_updated[8:3] == 6'b111111 ) begin
tap_out_data_out <= #(delay_value_data_out + CASC_RET_INTRINSIC_DELAY) ~CASC_RETURN_in;
tap_out_casc_out <= #delay_value_casc_out ~data_mux;
end
else begin
tap_out_data_out <= #delay_value data_mux;
tap_out_casc_out <= 1'b1;
end
end
specify
(CASC_IN => DATAOUT) = (0:0:0, 0:0:0);
(CASC_RETURN => DATAOUT) = (0:0:0, 0:0:0);
(CLK *> CNTVALUEOUT) = (0:0:0, 0:0:0);
(DATAIN => DATAOUT) = (0:0:0, 0:0:0);
(IDATAIN => DATAOUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem ( negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ILKN.v 0000664 0000000 0000000 00000177104 12327044266 0022171 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : ILKN.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ILKN #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter BYPASS = "FALSE",
parameter [1:0] CTL_RX_BURSTMAX = 2'h3,
parameter [1:0] CTL_RX_CHAN_EXT = 2'h0,
parameter [3:0] CTL_RX_LAST_LANE = 4'hB,
parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF,
parameter CTL_RX_PACKET_MODE = "TRUE",
parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0,
parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2,
parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000,
parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008,
parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000,
parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00,
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE",
parameter [1:0] CTL_TX_BURSTMAX = 2'h3,
parameter [2:0] CTL_TX_BURSTSHORT = 3'h1,
parameter [1:0] CTL_TX_CHAN_EXT = 2'h0,
parameter CTL_TX_DISABLE_SKIPWORD = "TRUE",
parameter [6:0] CTL_TX_FC_CALLEN = 7'h00,
parameter [3:0] CTL_TX_LAST_LANE = 4'hB,
parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF,
parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800,
parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0,
parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3,
parameter MODE = "TRUE",
parameter TEST_MODE_PIN_CHAR = "FALSE"
)(
output [15:0] DRP_DO,
output DRP_RDY,
output [65:0] RX_BYPASS_DATAOUT00,
output [65:0] RX_BYPASS_DATAOUT01,
output [65:0] RX_BYPASS_DATAOUT02,
output [65:0] RX_BYPASS_DATAOUT03,
output [65:0] RX_BYPASS_DATAOUT04,
output [65:0] RX_BYPASS_DATAOUT05,
output [65:0] RX_BYPASS_DATAOUT06,
output [65:0] RX_BYPASS_DATAOUT07,
output [65:0] RX_BYPASS_DATAOUT08,
output [65:0] RX_BYPASS_DATAOUT09,
output [65:0] RX_BYPASS_DATAOUT10,
output [65:0] RX_BYPASS_DATAOUT11,
output [11:0] RX_BYPASS_ENAOUT,
output [11:0] RX_BYPASS_IS_AVAILOUT,
output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT,
output [11:0] RX_BYPASS_IS_OVERFLOWOUT,
output [11:0] RX_BYPASS_IS_SYNCEDOUT,
output [11:0] RX_BYPASS_IS_SYNCWORDOUT,
output [10:0] RX_CHANOUT0,
output [10:0] RX_CHANOUT1,
output [10:0] RX_CHANOUT2,
output [10:0] RX_CHANOUT3,
output [127:0] RX_DATAOUT0,
output [127:0] RX_DATAOUT1,
output [127:0] RX_DATAOUT2,
output [127:0] RX_DATAOUT3,
output RX_ENAOUT0,
output RX_ENAOUT1,
output RX_ENAOUT2,
output RX_ENAOUT3,
output RX_EOPOUT0,
output RX_EOPOUT1,
output RX_EOPOUT2,
output RX_EOPOUT3,
output RX_ERROUT0,
output RX_ERROUT1,
output RX_ERROUT2,
output RX_ERROUT3,
output [3:0] RX_MTYOUT0,
output [3:0] RX_MTYOUT1,
output [3:0] RX_MTYOUT2,
output [3:0] RX_MTYOUT3,
output RX_OVFOUT,
output RX_SOPOUT0,
output RX_SOPOUT1,
output RX_SOPOUT2,
output RX_SOPOUT3,
output STAT_RX_ALIGNED,
output STAT_RX_ALIGNED_ERR,
output [11:0] STAT_RX_BAD_TYPE_ERR,
output STAT_RX_BURSTMAX_ERR,
output STAT_RX_BURST_ERR,
output STAT_RX_CRC24_ERR,
output [11:0] STAT_RX_CRC32_ERR,
output [11:0] STAT_RX_CRC32_VALID,
output [11:0] STAT_RX_DESCRAM_ERR,
output [11:0] STAT_RX_DIAGWORD_INTFSTAT,
output [11:0] STAT_RX_DIAGWORD_LANESTAT,
output [255:0] STAT_RX_FC_STAT,
output [11:0] STAT_RX_FRAMING_ERR,
output STAT_RX_MEOP_ERR,
output [11:0] STAT_RX_MF_ERR,
output [11:0] STAT_RX_MF_LEN_ERR,
output [11:0] STAT_RX_MF_REPEAT_ERR,
output STAT_RX_MISALIGNED,
output STAT_RX_MSOP_ERR,
output [7:0] STAT_RX_MUBITS,
output STAT_RX_MUBITS_UPDATED,
output STAT_RX_OVERFLOW_ERR,
output STAT_RX_RETRANS_CRC24_ERR,
output STAT_RX_RETRANS_DISC,
output [15:0] STAT_RX_RETRANS_LATENCY,
output STAT_RX_RETRANS_REQ,
output STAT_RX_RETRANS_RETRY_ERR,
output [7:0] STAT_RX_RETRANS_SEQ,
output STAT_RX_RETRANS_SEQ_UPDATED,
output [2:0] STAT_RX_RETRANS_STATE,
output [4:0] STAT_RX_RETRANS_SUBSEQ,
output STAT_RX_RETRANS_WDOG_ERR,
output STAT_RX_RETRANS_WRAP_ERR,
output [11:0] STAT_RX_SYNCED,
output [11:0] STAT_RX_SYNCED_ERR,
output [11:0] STAT_RX_WORD_SYNC,
output STAT_TX_BURST_ERR,
output STAT_TX_ERRINJ_BITERR_DONE,
output STAT_TX_OVERFLOW_ERR,
output STAT_TX_RETRANS_BURST_ERR,
output STAT_TX_RETRANS_BUSY,
output STAT_TX_RETRANS_RAM_PERROUT,
output [8:0] STAT_TX_RETRANS_RAM_RADDR,
output STAT_TX_RETRANS_RAM_RD_B0,
output STAT_TX_RETRANS_RAM_RD_B1,
output STAT_TX_RETRANS_RAM_RD_B2,
output STAT_TX_RETRANS_RAM_RD_B3,
output [1:0] STAT_TX_RETRANS_RAM_RSEL,
output [8:0] STAT_TX_RETRANS_RAM_WADDR,
output [643:0] STAT_TX_RETRANS_RAM_WDATA,
output STAT_TX_RETRANS_RAM_WE_B0,
output STAT_TX_RETRANS_RAM_WE_B1,
output STAT_TX_RETRANS_RAM_WE_B2,
output STAT_TX_RETRANS_RAM_WE_B3,
output STAT_TX_UNDERFLOW_ERR,
output TX_OVFOUT,
output TX_RDYOUT,
output [63:0] TX_SERDES_DATA00,
output [63:0] TX_SERDES_DATA01,
output [63:0] TX_SERDES_DATA02,
output [63:0] TX_SERDES_DATA03,
output [63:0] TX_SERDES_DATA04,
output [63:0] TX_SERDES_DATA05,
output [63:0] TX_SERDES_DATA06,
output [63:0] TX_SERDES_DATA07,
output [63:0] TX_SERDES_DATA08,
output [63:0] TX_SERDES_DATA09,
output [63:0] TX_SERDES_DATA10,
output [63:0] TX_SERDES_DATA11,
input CORE_CLK,
input CTL_RX_FORCE_RESYNC,
input CTL_RX_RETRANS_ACK,
input CTL_RX_RETRANS_ENABLE,
input CTL_RX_RETRANS_ERRIN,
input CTL_RX_RETRANS_FORCE_REQ,
input CTL_RX_RETRANS_RESET,
input CTL_RX_RETRANS_RESET_MODE,
input CTL_TX_DIAGWORD_INTFSTAT,
input [11:0] CTL_TX_DIAGWORD_LANESTAT,
input CTL_TX_ENABLE,
input CTL_TX_ERRINJ_BITERR_GO,
input [3:0] CTL_TX_ERRINJ_BITERR_LANE,
input [255:0] CTL_TX_FC_STAT,
input [7:0] CTL_TX_MUBITS,
input CTL_TX_RETRANS_ENABLE,
input CTL_TX_RETRANS_RAM_PERRIN,
input [643:0] CTL_TX_RETRANS_RAM_RDATA,
input CTL_TX_RETRANS_REQ,
input CTL_TX_RETRANS_REQ_VALID,
input [11:0] CTL_TX_RLIM_DELTA,
input CTL_TX_RLIM_ENABLE,
input [7:0] CTL_TX_RLIM_INTV,
input [11:0] CTL_TX_RLIM_MAX,
input [9:0] DRP_ADDR,
input DRP_CLK,
input [15:0] DRP_DI,
input DRP_EN,
input DRP_WE,
input LBUS_CLK,
input RX_BYPASS_FORCE_REALIGNIN,
input RX_BYPASS_RDIN,
input RX_RESET,
input [11:0] RX_SERDES_CLK,
input [63:0] RX_SERDES_DATA00,
input [63:0] RX_SERDES_DATA01,
input [63:0] RX_SERDES_DATA02,
input [63:0] RX_SERDES_DATA03,
input [63:0] RX_SERDES_DATA04,
input [63:0] RX_SERDES_DATA05,
input [63:0] RX_SERDES_DATA06,
input [63:0] RX_SERDES_DATA07,
input [63:0] RX_SERDES_DATA08,
input [63:0] RX_SERDES_DATA09,
input [63:0] RX_SERDES_DATA10,
input [63:0] RX_SERDES_DATA11,
input [11:0] RX_SERDES_RESET,
input TX_BCTLIN0,
input TX_BCTLIN1,
input TX_BCTLIN2,
input TX_BCTLIN3,
input [11:0] TX_BYPASS_CTRLIN,
input [63:0] TX_BYPASS_DATAIN00,
input [63:0] TX_BYPASS_DATAIN01,
input [63:0] TX_BYPASS_DATAIN02,
input [63:0] TX_BYPASS_DATAIN03,
input [63:0] TX_BYPASS_DATAIN04,
input [63:0] TX_BYPASS_DATAIN05,
input [63:0] TX_BYPASS_DATAIN06,
input [63:0] TX_BYPASS_DATAIN07,
input [63:0] TX_BYPASS_DATAIN08,
input [63:0] TX_BYPASS_DATAIN09,
input [63:0] TX_BYPASS_DATAIN10,
input [63:0] TX_BYPASS_DATAIN11,
input TX_BYPASS_ENAIN,
input [7:0] TX_BYPASS_GEARBOX_SEQIN,
input [3:0] TX_BYPASS_MFRAMER_STATEIN,
input [10:0] TX_CHANIN0,
input [10:0] TX_CHANIN1,
input [10:0] TX_CHANIN2,
input [10:0] TX_CHANIN3,
input [127:0] TX_DATAIN0,
input [127:0] TX_DATAIN1,
input [127:0] TX_DATAIN2,
input [127:0] TX_DATAIN3,
input TX_ENAIN0,
input TX_ENAIN1,
input TX_ENAIN2,
input TX_ENAIN3,
input TX_EOPIN0,
input TX_EOPIN1,
input TX_EOPIN2,
input TX_EOPIN3,
input TX_ERRIN0,
input TX_ERRIN1,
input TX_ERRIN2,
input TX_ERRIN3,
input [3:0] TX_MTYIN0,
input [3:0] TX_MTYIN1,
input [3:0] TX_MTYIN2,
input [3:0] TX_MTYIN3,
input TX_RESET,
input TX_SERDES_REFCLK,
input TX_SERDES_REFCLK_RESET,
input TX_SOPIN0,
input TX_SOPIN1,
input TX_SOPIN2,
input TX_SOPIN3
);
// define constants
localparam MODULE_NAME = "ILKN";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [40:1] BYPASS_REG = BYPASS;
localparam [1:0] CTL_RX_BURSTMAX_REG = CTL_RX_BURSTMAX;
localparam [1:0] CTL_RX_CHAN_EXT_REG = CTL_RX_CHAN_EXT;
localparam [3:0] CTL_RX_LAST_LANE_REG = CTL_RX_LAST_LANE;
localparam [15:0] CTL_RX_MFRAMELEN_MINUS1_REG = CTL_RX_MFRAMELEN_MINUS1;
localparam [40:1] CTL_RX_PACKET_MODE_REG = CTL_RX_PACKET_MODE;
localparam [2:0] CTL_RX_RETRANS_MULT_REG = CTL_RX_RETRANS_MULT;
localparam [3:0] CTL_RX_RETRANS_RETRY_REG = CTL_RX_RETRANS_RETRY;
localparam [15:0] CTL_RX_RETRANS_TIMER1_REG = CTL_RX_RETRANS_TIMER1;
localparam [15:0] CTL_RX_RETRANS_TIMER2_REG = CTL_RX_RETRANS_TIMER2;
localparam [11:0] CTL_RX_RETRANS_WDOG_REG = CTL_RX_RETRANS_WDOG;
localparam [7:0] CTL_RX_RETRANS_WRAP_TIMER_REG = CTL_RX_RETRANS_WRAP_TIMER;
localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR;
localparam [1:0] CTL_TX_BURSTMAX_REG = CTL_TX_BURSTMAX;
localparam [2:0] CTL_TX_BURSTSHORT_REG = CTL_TX_BURSTSHORT;
localparam [1:0] CTL_TX_CHAN_EXT_REG = CTL_TX_CHAN_EXT;
localparam [40:1] CTL_TX_DISABLE_SKIPWORD_REG = CTL_TX_DISABLE_SKIPWORD;
localparam [6:0] CTL_TX_FC_CALLEN_REG = CTL_TX_FC_CALLEN;
localparam [3:0] CTL_TX_LAST_LANE_REG = CTL_TX_LAST_LANE;
localparam [15:0] CTL_TX_MFRAMELEN_MINUS1_REG = CTL_TX_MFRAMELEN_MINUS1;
localparam [13:0] CTL_TX_RETRANS_DEPTH_REG = CTL_TX_RETRANS_DEPTH;
localparam [2:0] CTL_TX_RETRANS_MULT_REG = CTL_TX_RETRANS_MULT;
localparam [1:0] CTL_TX_RETRANS_RAM_BANKS_REG = CTL_TX_RETRANS_RAM_BANKS;
localparam [40:1] MODE_REG = MODE;
localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "ILKN_dr.v"
`endif
wire DRP_RDY_out;
wire RX_ENAOUT0_out;
wire RX_ENAOUT1_out;
wire RX_ENAOUT2_out;
wire RX_ENAOUT3_out;
wire RX_EOPOUT0_out;
wire RX_EOPOUT1_out;
wire RX_EOPOUT2_out;
wire RX_EOPOUT3_out;
wire RX_ERROUT0_out;
wire RX_ERROUT1_out;
wire RX_ERROUT2_out;
wire RX_ERROUT3_out;
wire RX_OVFOUT_out;
wire RX_SOPOUT0_out;
wire RX_SOPOUT1_out;
wire RX_SOPOUT2_out;
wire RX_SOPOUT3_out;
wire STAT_RX_ALIGNED_ERR_out;
wire STAT_RX_ALIGNED_out;
wire STAT_RX_BURSTMAX_ERR_out;
wire STAT_RX_BURST_ERR_out;
wire STAT_RX_CRC24_ERR_out;
wire STAT_RX_MEOP_ERR_out;
wire STAT_RX_MISALIGNED_out;
wire STAT_RX_MSOP_ERR_out;
wire STAT_RX_MUBITS_UPDATED_out;
wire STAT_RX_OVERFLOW_ERR_out;
wire STAT_RX_RETRANS_CRC24_ERR_out;
wire STAT_RX_RETRANS_DISC_out;
wire STAT_RX_RETRANS_REQ_out;
wire STAT_RX_RETRANS_RETRY_ERR_out;
wire STAT_RX_RETRANS_SEQ_UPDATED_out;
wire STAT_RX_RETRANS_WDOG_ERR_out;
wire STAT_RX_RETRANS_WRAP_ERR_out;
wire STAT_TX_BURST_ERR_out;
wire STAT_TX_ERRINJ_BITERR_DONE_out;
wire STAT_TX_OVERFLOW_ERR_out;
wire STAT_TX_RETRANS_BURST_ERR_out;
wire STAT_TX_RETRANS_BUSY_out;
wire STAT_TX_RETRANS_RAM_PERROUT_out;
wire STAT_TX_RETRANS_RAM_RD_B0_out;
wire STAT_TX_RETRANS_RAM_RD_B1_out;
wire STAT_TX_RETRANS_RAM_RD_B2_out;
wire STAT_TX_RETRANS_RAM_RD_B3_out;
wire STAT_TX_RETRANS_RAM_WE_B0_out;
wire STAT_TX_RETRANS_RAM_WE_B1_out;
wire STAT_TX_RETRANS_RAM_WE_B2_out;
wire STAT_TX_RETRANS_RAM_WE_B3_out;
wire STAT_TX_UNDERFLOW_ERR_out;
wire TX_OVFOUT_out;
wire TX_RDYOUT_out;
wire [10:0] RX_CHANOUT0_out;
wire [10:0] RX_CHANOUT1_out;
wire [10:0] RX_CHANOUT2_out;
wire [10:0] RX_CHANOUT3_out;
wire [11:0] RX_BYPASS_ENAOUT_out;
wire [11:0] RX_BYPASS_IS_AVAILOUT_out;
wire [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT_out;
wire [11:0] RX_BYPASS_IS_OVERFLOWOUT_out;
wire [11:0] RX_BYPASS_IS_SYNCEDOUT_out;
wire [11:0] RX_BYPASS_IS_SYNCWORDOUT_out;
wire [11:0] STAT_RX_BAD_TYPE_ERR_out;
wire [11:0] STAT_RX_CRC32_ERR_out;
wire [11:0] STAT_RX_CRC32_VALID_out;
wire [11:0] STAT_RX_DESCRAM_ERR_out;
wire [11:0] STAT_RX_DIAGWORD_INTFSTAT_out;
wire [11:0] STAT_RX_DIAGWORD_LANESTAT_out;
wire [11:0] STAT_RX_FRAMING_ERR_out;
wire [11:0] STAT_RX_MF_ERR_out;
wire [11:0] STAT_RX_MF_LEN_ERR_out;
wire [11:0] STAT_RX_MF_REPEAT_ERR_out;
wire [11:0] STAT_RX_SYNCED_ERR_out;
wire [11:0] STAT_RX_SYNCED_out;
wire [11:0] STAT_RX_WORD_SYNC_out;
wire [127:0] RX_DATAOUT0_out;
wire [127:0] RX_DATAOUT1_out;
wire [127:0] RX_DATAOUT2_out;
wire [127:0] RX_DATAOUT3_out;
wire [15:0] DRP_DO_out;
wire [15:0] STAT_RX_RETRANS_LATENCY_out;
wire [1:0] STAT_TX_RETRANS_RAM_RSEL_out;
wire [255:0] STAT_RX_FC_STAT_out;
wire [264:0] SCAN_OUT_out;
wire [2:0] STAT_RX_RETRANS_STATE_out;
wire [3:0] RX_MTYOUT0_out;
wire [3:0] RX_MTYOUT1_out;
wire [3:0] RX_MTYOUT2_out;
wire [3:0] RX_MTYOUT3_out;
wire [4:0] STAT_RX_RETRANS_SUBSEQ_out;
wire [63:0] TX_SERDES_DATA00_out;
wire [63:0] TX_SERDES_DATA01_out;
wire [63:0] TX_SERDES_DATA02_out;
wire [63:0] TX_SERDES_DATA03_out;
wire [63:0] TX_SERDES_DATA04_out;
wire [63:0] TX_SERDES_DATA05_out;
wire [63:0] TX_SERDES_DATA06_out;
wire [63:0] TX_SERDES_DATA07_out;
wire [63:0] TX_SERDES_DATA08_out;
wire [63:0] TX_SERDES_DATA09_out;
wire [63:0] TX_SERDES_DATA10_out;
wire [63:0] TX_SERDES_DATA11_out;
wire [643:0] STAT_TX_RETRANS_RAM_WDATA_out;
wire [65:0] RX_BYPASS_DATAOUT00_out;
wire [65:0] RX_BYPASS_DATAOUT01_out;
wire [65:0] RX_BYPASS_DATAOUT02_out;
wire [65:0] RX_BYPASS_DATAOUT03_out;
wire [65:0] RX_BYPASS_DATAOUT04_out;
wire [65:0] RX_BYPASS_DATAOUT05_out;
wire [65:0] RX_BYPASS_DATAOUT06_out;
wire [65:0] RX_BYPASS_DATAOUT07_out;
wire [65:0] RX_BYPASS_DATAOUT08_out;
wire [65:0] RX_BYPASS_DATAOUT09_out;
wire [65:0] RX_BYPASS_DATAOUT10_out;
wire [65:0] RX_BYPASS_DATAOUT11_out;
wire [7:0] STAT_RX_MUBITS_out;
wire [7:0] STAT_RX_RETRANS_SEQ_out;
wire [8:0] STAT_TX_RETRANS_RAM_RADDR_out;
wire [8:0] STAT_TX_RETRANS_RAM_WADDR_out;
wire DRP_RDY_delay;
wire RX_ENAOUT0_delay;
wire RX_ENAOUT1_delay;
wire RX_ENAOUT2_delay;
wire RX_ENAOUT3_delay;
wire RX_EOPOUT0_delay;
wire RX_EOPOUT1_delay;
wire RX_EOPOUT2_delay;
wire RX_EOPOUT3_delay;
wire RX_ERROUT0_delay;
wire RX_ERROUT1_delay;
wire RX_ERROUT2_delay;
wire RX_ERROUT3_delay;
wire RX_OVFOUT_delay;
wire RX_SOPOUT0_delay;
wire RX_SOPOUT1_delay;
wire RX_SOPOUT2_delay;
wire RX_SOPOUT3_delay;
wire STAT_RX_ALIGNED_ERR_delay;
wire STAT_RX_ALIGNED_delay;
wire STAT_RX_BURSTMAX_ERR_delay;
wire STAT_RX_BURST_ERR_delay;
wire STAT_RX_CRC24_ERR_delay;
wire STAT_RX_MEOP_ERR_delay;
wire STAT_RX_MISALIGNED_delay;
wire STAT_RX_MSOP_ERR_delay;
wire STAT_RX_MUBITS_UPDATED_delay;
wire STAT_RX_OVERFLOW_ERR_delay;
wire STAT_RX_RETRANS_CRC24_ERR_delay;
wire STAT_RX_RETRANS_DISC_delay;
wire STAT_RX_RETRANS_REQ_delay;
wire STAT_RX_RETRANS_RETRY_ERR_delay;
wire STAT_RX_RETRANS_SEQ_UPDATED_delay;
wire STAT_RX_RETRANS_WDOG_ERR_delay;
wire STAT_RX_RETRANS_WRAP_ERR_delay;
wire STAT_TX_BURST_ERR_delay;
wire STAT_TX_ERRINJ_BITERR_DONE_delay;
wire STAT_TX_OVERFLOW_ERR_delay;
wire STAT_TX_RETRANS_BURST_ERR_delay;
wire STAT_TX_RETRANS_BUSY_delay;
wire STAT_TX_RETRANS_RAM_PERROUT_delay;
wire STAT_TX_RETRANS_RAM_RD_B0_delay;
wire STAT_TX_RETRANS_RAM_RD_B1_delay;
wire STAT_TX_RETRANS_RAM_RD_B2_delay;
wire STAT_TX_RETRANS_RAM_RD_B3_delay;
wire STAT_TX_RETRANS_RAM_WE_B0_delay;
wire STAT_TX_RETRANS_RAM_WE_B1_delay;
wire STAT_TX_RETRANS_RAM_WE_B2_delay;
wire STAT_TX_RETRANS_RAM_WE_B3_delay;
wire STAT_TX_UNDERFLOW_ERR_delay;
wire TX_OVFOUT_delay;
wire TX_RDYOUT_delay;
wire [10:0] RX_CHANOUT0_delay;
wire [10:0] RX_CHANOUT1_delay;
wire [10:0] RX_CHANOUT2_delay;
wire [10:0] RX_CHANOUT3_delay;
wire [11:0] RX_BYPASS_ENAOUT_delay;
wire [11:0] RX_BYPASS_IS_AVAILOUT_delay;
wire [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT_delay;
wire [11:0] RX_BYPASS_IS_OVERFLOWOUT_delay;
wire [11:0] RX_BYPASS_IS_SYNCEDOUT_delay;
wire [11:0] RX_BYPASS_IS_SYNCWORDOUT_delay;
wire [11:0] STAT_RX_BAD_TYPE_ERR_delay;
wire [11:0] STAT_RX_CRC32_ERR_delay;
wire [11:0] STAT_RX_CRC32_VALID_delay;
wire [11:0] STAT_RX_DESCRAM_ERR_delay;
wire [11:0] STAT_RX_DIAGWORD_INTFSTAT_delay;
wire [11:0] STAT_RX_DIAGWORD_LANESTAT_delay;
wire [11:0] STAT_RX_FRAMING_ERR_delay;
wire [11:0] STAT_RX_MF_ERR_delay;
wire [11:0] STAT_RX_MF_LEN_ERR_delay;
wire [11:0] STAT_RX_MF_REPEAT_ERR_delay;
wire [11:0] STAT_RX_SYNCED_ERR_delay;
wire [11:0] STAT_RX_SYNCED_delay;
wire [11:0] STAT_RX_WORD_SYNC_delay;
wire [127:0] RX_DATAOUT0_delay;
wire [127:0] RX_DATAOUT1_delay;
wire [127:0] RX_DATAOUT2_delay;
wire [127:0] RX_DATAOUT3_delay;
wire [15:0] DRP_DO_delay;
wire [15:0] STAT_RX_RETRANS_LATENCY_delay;
wire [1:0] STAT_TX_RETRANS_RAM_RSEL_delay;
wire [255:0] STAT_RX_FC_STAT_delay;
wire [2:0] STAT_RX_RETRANS_STATE_delay;
wire [3:0] RX_MTYOUT0_delay;
wire [3:0] RX_MTYOUT1_delay;
wire [3:0] RX_MTYOUT2_delay;
wire [3:0] RX_MTYOUT3_delay;
wire [4:0] STAT_RX_RETRANS_SUBSEQ_delay;
wire [63:0] TX_SERDES_DATA00_delay;
wire [63:0] TX_SERDES_DATA01_delay;
wire [63:0] TX_SERDES_DATA02_delay;
wire [63:0] TX_SERDES_DATA03_delay;
wire [63:0] TX_SERDES_DATA04_delay;
wire [63:0] TX_SERDES_DATA05_delay;
wire [63:0] TX_SERDES_DATA06_delay;
wire [63:0] TX_SERDES_DATA07_delay;
wire [63:0] TX_SERDES_DATA08_delay;
wire [63:0] TX_SERDES_DATA09_delay;
wire [63:0] TX_SERDES_DATA10_delay;
wire [63:0] TX_SERDES_DATA11_delay;
wire [643:0] STAT_TX_RETRANS_RAM_WDATA_delay;
wire [65:0] RX_BYPASS_DATAOUT00_delay;
wire [65:0] RX_BYPASS_DATAOUT01_delay;
wire [65:0] RX_BYPASS_DATAOUT02_delay;
wire [65:0] RX_BYPASS_DATAOUT03_delay;
wire [65:0] RX_BYPASS_DATAOUT04_delay;
wire [65:0] RX_BYPASS_DATAOUT05_delay;
wire [65:0] RX_BYPASS_DATAOUT06_delay;
wire [65:0] RX_BYPASS_DATAOUT07_delay;
wire [65:0] RX_BYPASS_DATAOUT08_delay;
wire [65:0] RX_BYPASS_DATAOUT09_delay;
wire [65:0] RX_BYPASS_DATAOUT10_delay;
wire [65:0] RX_BYPASS_DATAOUT11_delay;
wire [7:0] STAT_RX_MUBITS_delay;
wire [7:0] STAT_RX_RETRANS_SEQ_delay;
wire [8:0] STAT_TX_RETRANS_RAM_RADDR_delay;
wire [8:0] STAT_TX_RETRANS_RAM_WADDR_delay;
wire CORE_CLK_in;
wire CTL_RX_FORCE_RESYNC_in;
wire CTL_RX_RETRANS_ACK_in;
wire CTL_RX_RETRANS_ENABLE_in;
wire CTL_RX_RETRANS_ERRIN_in;
wire CTL_RX_RETRANS_FORCE_REQ_in;
wire CTL_RX_RETRANS_RESET_MODE_in;
wire CTL_RX_RETRANS_RESET_in;
wire CTL_TX_DIAGWORD_INTFSTAT_in;
wire CTL_TX_ENABLE_in;
wire CTL_TX_ERRINJ_BITERR_GO_in;
wire CTL_TX_RETRANS_ENABLE_in;
wire CTL_TX_RETRANS_RAM_PERRIN_in;
wire CTL_TX_RETRANS_REQ_VALID_in;
wire CTL_TX_RETRANS_REQ_in;
wire CTL_TX_RLIM_ENABLE_in;
wire DRP_CLK_in;
wire DRP_EN_in;
wire DRP_WE_in;
wire LBUS_CLK_in;
wire RX_BYPASS_FORCE_REALIGNIN_in;
wire RX_BYPASS_RDIN_in;
wire RX_RESET_in;
wire SCAN_EN_N_in;
wire TEST_MODE_N_in;
wire TEST_RESET_in;
wire TX_BCTLIN0_in;
wire TX_BCTLIN1_in;
wire TX_BCTLIN2_in;
wire TX_BCTLIN3_in;
wire TX_BYPASS_ENAIN_in;
wire TX_ENAIN0_in;
wire TX_ENAIN1_in;
wire TX_ENAIN2_in;
wire TX_ENAIN3_in;
wire TX_EOPIN0_in;
wire TX_EOPIN1_in;
wire TX_EOPIN2_in;
wire TX_EOPIN3_in;
wire TX_ERRIN0_in;
wire TX_ERRIN1_in;
wire TX_ERRIN2_in;
wire TX_ERRIN3_in;
wire TX_RESET_in;
wire TX_SERDES_REFCLK_RESET_in;
wire TX_SERDES_REFCLK_in;
wire TX_SOPIN0_in;
wire TX_SOPIN1_in;
wire TX_SOPIN2_in;
wire TX_SOPIN3_in;
wire [10:0] TX_CHANIN0_in;
wire [10:0] TX_CHANIN1_in;
wire [10:0] TX_CHANIN2_in;
wire [10:0] TX_CHANIN3_in;
wire [11:0] CTL_TX_DIAGWORD_LANESTAT_in;
wire [11:0] CTL_TX_RLIM_DELTA_in;
wire [11:0] CTL_TX_RLIM_MAX_in;
wire [11:0] RX_SERDES_CLK_in;
wire [11:0] RX_SERDES_RESET_in;
wire [11:0] TX_BYPASS_CTRLIN_in;
wire [127:0] TX_DATAIN0_in;
wire [127:0] TX_DATAIN1_in;
wire [127:0] TX_DATAIN2_in;
wire [127:0] TX_DATAIN3_in;
wire [15:0] DRP_DI_in;
wire [255:0] CTL_TX_FC_STAT_in;
wire [264:0] SCAN_IN_in;
wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_in;
wire [3:0] TX_BYPASS_MFRAMER_STATEIN_in;
wire [3:0] TX_MTYIN0_in;
wire [3:0] TX_MTYIN1_in;
wire [3:0] TX_MTYIN2_in;
wire [3:0] TX_MTYIN3_in;
wire [63:0] RX_SERDES_DATA00_in;
wire [63:0] RX_SERDES_DATA01_in;
wire [63:0] RX_SERDES_DATA02_in;
wire [63:0] RX_SERDES_DATA03_in;
wire [63:0] RX_SERDES_DATA04_in;
wire [63:0] RX_SERDES_DATA05_in;
wire [63:0] RX_SERDES_DATA06_in;
wire [63:0] RX_SERDES_DATA07_in;
wire [63:0] RX_SERDES_DATA08_in;
wire [63:0] RX_SERDES_DATA09_in;
wire [63:0] RX_SERDES_DATA10_in;
wire [63:0] RX_SERDES_DATA11_in;
wire [63:0] TX_BYPASS_DATAIN00_in;
wire [63:0] TX_BYPASS_DATAIN01_in;
wire [63:0] TX_BYPASS_DATAIN02_in;
wire [63:0] TX_BYPASS_DATAIN03_in;
wire [63:0] TX_BYPASS_DATAIN04_in;
wire [63:0] TX_BYPASS_DATAIN05_in;
wire [63:0] TX_BYPASS_DATAIN06_in;
wire [63:0] TX_BYPASS_DATAIN07_in;
wire [63:0] TX_BYPASS_DATAIN08_in;
wire [63:0] TX_BYPASS_DATAIN09_in;
wire [63:0] TX_BYPASS_DATAIN10_in;
wire [63:0] TX_BYPASS_DATAIN11_in;
wire [643:0] CTL_TX_RETRANS_RAM_RDATA_in;
wire [7:0] CTL_TX_MUBITS_in;
wire [7:0] CTL_TX_RLIM_INTV_in;
wire [7:0] TX_BYPASS_GEARBOX_SEQIN_in;
wire [9:0] DRP_ADDR_in;
wire CORE_CLK_delay;
wire CTL_RX_FORCE_RESYNC_delay;
wire CTL_RX_RETRANS_ACK_delay;
wire CTL_RX_RETRANS_ENABLE_delay;
wire CTL_RX_RETRANS_ERRIN_delay;
wire CTL_RX_RETRANS_FORCE_REQ_delay;
wire CTL_RX_RETRANS_RESET_MODE_delay;
wire CTL_RX_RETRANS_RESET_delay;
wire CTL_TX_DIAGWORD_INTFSTAT_delay;
wire CTL_TX_ENABLE_delay;
wire CTL_TX_ERRINJ_BITERR_GO_delay;
wire CTL_TX_RETRANS_ENABLE_delay;
wire CTL_TX_RETRANS_RAM_PERRIN_delay;
wire CTL_TX_RETRANS_REQ_VALID_delay;
wire CTL_TX_RETRANS_REQ_delay;
wire CTL_TX_RLIM_ENABLE_delay;
wire DRP_CLK_delay;
wire DRP_EN_delay;
wire DRP_WE_delay;
wire LBUS_CLK_delay;
wire RX_BYPASS_FORCE_REALIGNIN_delay;
wire RX_BYPASS_RDIN_delay;
wire RX_RESET_delay;
wire TX_BCTLIN0_delay;
wire TX_BCTLIN1_delay;
wire TX_BCTLIN2_delay;
wire TX_BCTLIN3_delay;
wire TX_BYPASS_ENAIN_delay;
wire TX_ENAIN0_delay;
wire TX_ENAIN1_delay;
wire TX_ENAIN2_delay;
wire TX_ENAIN3_delay;
wire TX_EOPIN0_delay;
wire TX_EOPIN1_delay;
wire TX_EOPIN2_delay;
wire TX_EOPIN3_delay;
wire TX_ERRIN0_delay;
wire TX_ERRIN1_delay;
wire TX_ERRIN2_delay;
wire TX_ERRIN3_delay;
wire TX_RESET_delay;
wire TX_SERDES_REFCLK_RESET_delay;
wire TX_SERDES_REFCLK_delay;
wire TX_SOPIN0_delay;
wire TX_SOPIN1_delay;
wire TX_SOPIN2_delay;
wire TX_SOPIN3_delay;
wire [10:0] TX_CHANIN0_delay;
wire [10:0] TX_CHANIN1_delay;
wire [10:0] TX_CHANIN2_delay;
wire [10:0] TX_CHANIN3_delay;
wire [11:0] CTL_TX_DIAGWORD_LANESTAT_delay;
wire [11:0] CTL_TX_RLIM_DELTA_delay;
wire [11:0] CTL_TX_RLIM_MAX_delay;
wire [11:0] RX_SERDES_CLK_delay;
wire [11:0] RX_SERDES_RESET_delay;
wire [11:0] TX_BYPASS_CTRLIN_delay;
wire [127:0] TX_DATAIN0_delay;
wire [127:0] TX_DATAIN1_delay;
wire [127:0] TX_DATAIN2_delay;
wire [127:0] TX_DATAIN3_delay;
wire [15:0] DRP_DI_delay;
wire [255:0] CTL_TX_FC_STAT_delay;
wire [3:0] CTL_TX_ERRINJ_BITERR_LANE_delay;
wire [3:0] TX_BYPASS_MFRAMER_STATEIN_delay;
wire [3:0] TX_MTYIN0_delay;
wire [3:0] TX_MTYIN1_delay;
wire [3:0] TX_MTYIN2_delay;
wire [3:0] TX_MTYIN3_delay;
wire [63:0] RX_SERDES_DATA00_delay;
wire [63:0] RX_SERDES_DATA01_delay;
wire [63:0] RX_SERDES_DATA02_delay;
wire [63:0] RX_SERDES_DATA03_delay;
wire [63:0] RX_SERDES_DATA04_delay;
wire [63:0] RX_SERDES_DATA05_delay;
wire [63:0] RX_SERDES_DATA06_delay;
wire [63:0] RX_SERDES_DATA07_delay;
wire [63:0] RX_SERDES_DATA08_delay;
wire [63:0] RX_SERDES_DATA09_delay;
wire [63:0] RX_SERDES_DATA10_delay;
wire [63:0] RX_SERDES_DATA11_delay;
wire [63:0] TX_BYPASS_DATAIN00_delay;
wire [63:0] TX_BYPASS_DATAIN01_delay;
wire [63:0] TX_BYPASS_DATAIN02_delay;
wire [63:0] TX_BYPASS_DATAIN03_delay;
wire [63:0] TX_BYPASS_DATAIN04_delay;
wire [63:0] TX_BYPASS_DATAIN05_delay;
wire [63:0] TX_BYPASS_DATAIN06_delay;
wire [63:0] TX_BYPASS_DATAIN07_delay;
wire [63:0] TX_BYPASS_DATAIN08_delay;
wire [63:0] TX_BYPASS_DATAIN09_delay;
wire [63:0] TX_BYPASS_DATAIN10_delay;
wire [63:0] TX_BYPASS_DATAIN11_delay;
wire [643:0] CTL_TX_RETRANS_RAM_RDATA_delay;
wire [7:0] CTL_TX_MUBITS_delay;
wire [7:0] CTL_TX_RLIM_INTV_delay;
wire [7:0] TX_BYPASS_GEARBOX_SEQIN_delay;
wire [9:0] DRP_ADDR_delay;
assign #(out_delay) DRP_DO = DRP_DO_delay;
assign #(out_delay) DRP_RDY = DRP_RDY_delay;
assign #(out_delay) RX_BYPASS_DATAOUT00 = RX_BYPASS_DATAOUT00_delay;
assign #(out_delay) RX_BYPASS_DATAOUT01 = RX_BYPASS_DATAOUT01_delay;
assign #(out_delay) RX_BYPASS_DATAOUT02 = RX_BYPASS_DATAOUT02_delay;
assign #(out_delay) RX_BYPASS_DATAOUT03 = RX_BYPASS_DATAOUT03_delay;
assign #(out_delay) RX_BYPASS_DATAOUT04 = RX_BYPASS_DATAOUT04_delay;
assign #(out_delay) RX_BYPASS_DATAOUT05 = RX_BYPASS_DATAOUT05_delay;
assign #(out_delay) RX_BYPASS_DATAOUT06 = RX_BYPASS_DATAOUT06_delay;
assign #(out_delay) RX_BYPASS_DATAOUT07 = RX_BYPASS_DATAOUT07_delay;
assign #(out_delay) RX_BYPASS_DATAOUT08 = RX_BYPASS_DATAOUT08_delay;
assign #(out_delay) RX_BYPASS_DATAOUT09 = RX_BYPASS_DATAOUT09_delay;
assign #(out_delay) RX_BYPASS_DATAOUT10 = RX_BYPASS_DATAOUT10_delay;
assign #(out_delay) RX_BYPASS_DATAOUT11 = RX_BYPASS_DATAOUT11_delay;
assign #(out_delay) RX_BYPASS_ENAOUT = RX_BYPASS_ENAOUT_delay;
assign #(out_delay) RX_BYPASS_IS_AVAILOUT = RX_BYPASS_IS_AVAILOUT_delay;
assign #(out_delay) RX_BYPASS_IS_BADLYFRAMEDOUT = RX_BYPASS_IS_BADLYFRAMEDOUT_delay;
assign #(out_delay) RX_BYPASS_IS_OVERFLOWOUT = RX_BYPASS_IS_OVERFLOWOUT_delay;
assign #(out_delay) RX_BYPASS_IS_SYNCEDOUT = RX_BYPASS_IS_SYNCEDOUT_delay;
assign #(out_delay) RX_BYPASS_IS_SYNCWORDOUT = RX_BYPASS_IS_SYNCWORDOUT_delay;
assign #(out_delay) RX_CHANOUT0 = RX_CHANOUT0_delay;
assign #(out_delay) RX_CHANOUT1 = RX_CHANOUT1_delay;
assign #(out_delay) RX_CHANOUT2 = RX_CHANOUT2_delay;
assign #(out_delay) RX_CHANOUT3 = RX_CHANOUT3_delay;
assign #(out_delay) RX_DATAOUT0 = RX_DATAOUT0_delay;
assign #(out_delay) RX_DATAOUT1 = RX_DATAOUT1_delay;
assign #(out_delay) RX_DATAOUT2 = RX_DATAOUT2_delay;
assign #(out_delay) RX_DATAOUT3 = RX_DATAOUT3_delay;
assign #(out_delay) RX_ENAOUT0 = RX_ENAOUT0_delay;
assign #(out_delay) RX_ENAOUT1 = RX_ENAOUT1_delay;
assign #(out_delay) RX_ENAOUT2 = RX_ENAOUT2_delay;
assign #(out_delay) RX_ENAOUT3 = RX_ENAOUT3_delay;
assign #(out_delay) RX_EOPOUT0 = RX_EOPOUT0_delay;
assign #(out_delay) RX_EOPOUT1 = RX_EOPOUT1_delay;
assign #(out_delay) RX_EOPOUT2 = RX_EOPOUT2_delay;
assign #(out_delay) RX_EOPOUT3 = RX_EOPOUT3_delay;
assign #(out_delay) RX_ERROUT0 = RX_ERROUT0_delay;
assign #(out_delay) RX_ERROUT1 = RX_ERROUT1_delay;
assign #(out_delay) RX_ERROUT2 = RX_ERROUT2_delay;
assign #(out_delay) RX_ERROUT3 = RX_ERROUT3_delay;
assign #(out_delay) RX_MTYOUT0 = RX_MTYOUT0_delay;
assign #(out_delay) RX_MTYOUT1 = RX_MTYOUT1_delay;
assign #(out_delay) RX_MTYOUT2 = RX_MTYOUT2_delay;
assign #(out_delay) RX_MTYOUT3 = RX_MTYOUT3_delay;
assign #(out_delay) RX_OVFOUT = RX_OVFOUT_delay;
assign #(out_delay) RX_SOPOUT0 = RX_SOPOUT0_delay;
assign #(out_delay) RX_SOPOUT1 = RX_SOPOUT1_delay;
assign #(out_delay) RX_SOPOUT2 = RX_SOPOUT2_delay;
assign #(out_delay) RX_SOPOUT3 = RX_SOPOUT3_delay;
assign #(out_delay) STAT_RX_ALIGNED = STAT_RX_ALIGNED_delay;
assign #(out_delay) STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_delay;
assign #(out_delay) STAT_RX_BAD_TYPE_ERR = STAT_RX_BAD_TYPE_ERR_delay;
assign #(out_delay) STAT_RX_BURSTMAX_ERR = STAT_RX_BURSTMAX_ERR_delay;
assign #(out_delay) STAT_RX_BURST_ERR = STAT_RX_BURST_ERR_delay;
assign #(out_delay) STAT_RX_CRC24_ERR = STAT_RX_CRC24_ERR_delay;
assign #(out_delay) STAT_RX_CRC32_ERR = STAT_RX_CRC32_ERR_delay;
assign #(out_delay) STAT_RX_CRC32_VALID = STAT_RX_CRC32_VALID_delay;
assign #(out_delay) STAT_RX_DESCRAM_ERR = STAT_RX_DESCRAM_ERR_delay;
assign #(out_delay) STAT_RX_DIAGWORD_INTFSTAT = STAT_RX_DIAGWORD_INTFSTAT_delay;
assign #(out_delay) STAT_RX_DIAGWORD_LANESTAT = STAT_RX_DIAGWORD_LANESTAT_delay;
assign #(out_delay) STAT_RX_FC_STAT = STAT_RX_FC_STAT_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR = STAT_RX_FRAMING_ERR_delay;
assign #(out_delay) STAT_RX_MEOP_ERR = STAT_RX_MEOP_ERR_delay;
assign #(out_delay) STAT_RX_MF_ERR = STAT_RX_MF_ERR_delay;
assign #(out_delay) STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_delay;
assign #(out_delay) STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_delay;
assign #(out_delay) STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_delay;
assign #(out_delay) STAT_RX_MSOP_ERR = STAT_RX_MSOP_ERR_delay;
assign #(out_delay) STAT_RX_MUBITS = STAT_RX_MUBITS_delay;
assign #(out_delay) STAT_RX_MUBITS_UPDATED = STAT_RX_MUBITS_UPDATED_delay;
assign #(out_delay) STAT_RX_OVERFLOW_ERR = STAT_RX_OVERFLOW_ERR_delay;
assign #(out_delay) STAT_RX_RETRANS_CRC24_ERR = STAT_RX_RETRANS_CRC24_ERR_delay;
assign #(out_delay) STAT_RX_RETRANS_DISC = STAT_RX_RETRANS_DISC_delay;
assign #(out_delay) STAT_RX_RETRANS_LATENCY = STAT_RX_RETRANS_LATENCY_delay;
assign #(out_delay) STAT_RX_RETRANS_REQ = STAT_RX_RETRANS_REQ_delay;
assign #(out_delay) STAT_RX_RETRANS_RETRY_ERR = STAT_RX_RETRANS_RETRY_ERR_delay;
assign #(out_delay) STAT_RX_RETRANS_SEQ = STAT_RX_RETRANS_SEQ_delay;
assign #(out_delay) STAT_RX_RETRANS_SEQ_UPDATED = STAT_RX_RETRANS_SEQ_UPDATED_delay;
assign #(out_delay) STAT_RX_RETRANS_STATE = STAT_RX_RETRANS_STATE_delay;
assign #(out_delay) STAT_RX_RETRANS_SUBSEQ = STAT_RX_RETRANS_SUBSEQ_delay;
assign #(out_delay) STAT_RX_RETRANS_WDOG_ERR = STAT_RX_RETRANS_WDOG_ERR_delay;
assign #(out_delay) STAT_RX_RETRANS_WRAP_ERR = STAT_RX_RETRANS_WRAP_ERR_delay;
assign #(out_delay) STAT_RX_SYNCED = STAT_RX_SYNCED_delay;
assign #(out_delay) STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_delay;
assign #(out_delay) STAT_RX_WORD_SYNC = STAT_RX_WORD_SYNC_delay;
assign #(out_delay) STAT_TX_BURST_ERR = STAT_TX_BURST_ERR_delay;
assign #(out_delay) STAT_TX_ERRINJ_BITERR_DONE = STAT_TX_ERRINJ_BITERR_DONE_delay;
assign #(out_delay) STAT_TX_OVERFLOW_ERR = STAT_TX_OVERFLOW_ERR_delay;
assign #(out_delay) STAT_TX_RETRANS_BURST_ERR = STAT_TX_RETRANS_BURST_ERR_delay;
assign #(out_delay) STAT_TX_RETRANS_BUSY = STAT_TX_RETRANS_BUSY_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_PERROUT = STAT_TX_RETRANS_RAM_PERROUT_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RADDR = STAT_TX_RETRANS_RAM_RADDR_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B0 = STAT_TX_RETRANS_RAM_RD_B0_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B1 = STAT_TX_RETRANS_RAM_RD_B1_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B2 = STAT_TX_RETRANS_RAM_RD_B2_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RD_B3 = STAT_TX_RETRANS_RAM_RD_B3_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_RSEL = STAT_TX_RETRANS_RAM_RSEL_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WADDR = STAT_TX_RETRANS_RAM_WADDR_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WDATA = STAT_TX_RETRANS_RAM_WDATA_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B0 = STAT_TX_RETRANS_RAM_WE_B0_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B1 = STAT_TX_RETRANS_RAM_WE_B1_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B2 = STAT_TX_RETRANS_RAM_WE_B2_delay;
assign #(out_delay) STAT_TX_RETRANS_RAM_WE_B3 = STAT_TX_RETRANS_RAM_WE_B3_delay;
assign #(out_delay) STAT_TX_UNDERFLOW_ERR = STAT_TX_UNDERFLOW_ERR_delay;
assign #(out_delay) TX_OVFOUT = TX_OVFOUT_delay;
assign #(out_delay) TX_RDYOUT = TX_RDYOUT_delay;
assign #(out_delay) TX_SERDES_DATA00 = TX_SERDES_DATA00_delay;
assign #(out_delay) TX_SERDES_DATA01 = TX_SERDES_DATA01_delay;
assign #(out_delay) TX_SERDES_DATA02 = TX_SERDES_DATA02_delay;
assign #(out_delay) TX_SERDES_DATA03 = TX_SERDES_DATA03_delay;
assign #(out_delay) TX_SERDES_DATA04 = TX_SERDES_DATA04_delay;
assign #(out_delay) TX_SERDES_DATA05 = TX_SERDES_DATA05_delay;
assign #(out_delay) TX_SERDES_DATA06 = TX_SERDES_DATA06_delay;
assign #(out_delay) TX_SERDES_DATA07 = TX_SERDES_DATA07_delay;
assign #(out_delay) TX_SERDES_DATA08 = TX_SERDES_DATA08_delay;
assign #(out_delay) TX_SERDES_DATA09 = TX_SERDES_DATA09_delay;
assign #(out_delay) TX_SERDES_DATA10 = TX_SERDES_DATA10_delay;
assign #(out_delay) TX_SERDES_DATA11 = TX_SERDES_DATA11_delay;
// inputs with no timing checks
assign #(inclk_delay) CORE_CLK_delay = CORE_CLK;
assign #(inclk_delay) DRP_CLK_delay = DRP_CLK;
assign #(inclk_delay) LBUS_CLK_delay = LBUS_CLK;
assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK;
assign #(inclk_delay) TX_SERDES_REFCLK_delay = TX_SERDES_REFCLK;
assign #(in_delay) CTL_RX_FORCE_RESYNC_delay = CTL_RX_FORCE_RESYNC;
assign #(in_delay) CTL_RX_RETRANS_ACK_delay = CTL_RX_RETRANS_ACK;
assign #(in_delay) CTL_RX_RETRANS_ENABLE_delay = CTL_RX_RETRANS_ENABLE;
assign #(in_delay) CTL_RX_RETRANS_ERRIN_delay = CTL_RX_RETRANS_ERRIN;
assign #(in_delay) CTL_RX_RETRANS_FORCE_REQ_delay = CTL_RX_RETRANS_FORCE_REQ;
assign #(in_delay) CTL_RX_RETRANS_RESET_MODE_delay = CTL_RX_RETRANS_RESET_MODE;
assign #(in_delay) CTL_RX_RETRANS_RESET_delay = CTL_RX_RETRANS_RESET;
assign #(in_delay) CTL_TX_DIAGWORD_INTFSTAT_delay = CTL_TX_DIAGWORD_INTFSTAT;
assign #(in_delay) CTL_TX_DIAGWORD_LANESTAT_delay = CTL_TX_DIAGWORD_LANESTAT;
assign #(in_delay) CTL_TX_ENABLE_delay = CTL_TX_ENABLE;
assign #(in_delay) CTL_TX_ERRINJ_BITERR_GO_delay = CTL_TX_ERRINJ_BITERR_GO;
assign #(in_delay) CTL_TX_ERRINJ_BITERR_LANE_delay = CTL_TX_ERRINJ_BITERR_LANE;
assign #(in_delay) CTL_TX_FC_STAT_delay = CTL_TX_FC_STAT;
assign #(in_delay) CTL_TX_MUBITS_delay = CTL_TX_MUBITS;
assign #(in_delay) CTL_TX_RETRANS_ENABLE_delay = CTL_TX_RETRANS_ENABLE;
assign #(in_delay) CTL_TX_RETRANS_RAM_PERRIN_delay = CTL_TX_RETRANS_RAM_PERRIN;
assign #(in_delay) CTL_TX_RETRANS_RAM_RDATA_delay = CTL_TX_RETRANS_RAM_RDATA;
assign #(in_delay) CTL_TX_RETRANS_REQ_VALID_delay = CTL_TX_RETRANS_REQ_VALID;
assign #(in_delay) CTL_TX_RETRANS_REQ_delay = CTL_TX_RETRANS_REQ;
assign #(in_delay) CTL_TX_RLIM_DELTA_delay = CTL_TX_RLIM_DELTA;
assign #(in_delay) CTL_TX_RLIM_ENABLE_delay = CTL_TX_RLIM_ENABLE;
assign #(in_delay) CTL_TX_RLIM_INTV_delay = CTL_TX_RLIM_INTV;
assign #(in_delay) CTL_TX_RLIM_MAX_delay = CTL_TX_RLIM_MAX;
assign #(in_delay) DRP_ADDR_delay = DRP_ADDR;
assign #(in_delay) DRP_DI_delay = DRP_DI;
assign #(in_delay) DRP_EN_delay = DRP_EN;
assign #(in_delay) DRP_WE_delay = DRP_WE;
assign #(in_delay) RX_BYPASS_FORCE_REALIGNIN_delay = RX_BYPASS_FORCE_REALIGNIN;
assign #(in_delay) RX_BYPASS_RDIN_delay = RX_BYPASS_RDIN;
assign #(in_delay) RX_RESET_delay = RX_RESET;
assign #(in_delay) RX_SERDES_DATA00_delay = RX_SERDES_DATA00;
assign #(in_delay) RX_SERDES_DATA01_delay = RX_SERDES_DATA01;
assign #(in_delay) RX_SERDES_DATA02_delay = RX_SERDES_DATA02;
assign #(in_delay) RX_SERDES_DATA03_delay = RX_SERDES_DATA03;
assign #(in_delay) RX_SERDES_DATA04_delay = RX_SERDES_DATA04;
assign #(in_delay) RX_SERDES_DATA05_delay = RX_SERDES_DATA05;
assign #(in_delay) RX_SERDES_DATA06_delay = RX_SERDES_DATA06;
assign #(in_delay) RX_SERDES_DATA07_delay = RX_SERDES_DATA07;
assign #(in_delay) RX_SERDES_DATA08_delay = RX_SERDES_DATA08;
assign #(in_delay) RX_SERDES_DATA09_delay = RX_SERDES_DATA09;
assign #(in_delay) RX_SERDES_DATA10_delay = RX_SERDES_DATA10;
assign #(in_delay) RX_SERDES_DATA11_delay = RX_SERDES_DATA11;
assign #(in_delay) RX_SERDES_RESET_delay = RX_SERDES_RESET;
assign #(in_delay) TX_BCTLIN0_delay = TX_BCTLIN0;
assign #(in_delay) TX_BCTLIN1_delay = TX_BCTLIN1;
assign #(in_delay) TX_BCTLIN2_delay = TX_BCTLIN2;
assign #(in_delay) TX_BCTLIN3_delay = TX_BCTLIN3;
assign #(in_delay) TX_BYPASS_CTRLIN_delay = TX_BYPASS_CTRLIN;
assign #(in_delay) TX_BYPASS_DATAIN00_delay = TX_BYPASS_DATAIN00;
assign #(in_delay) TX_BYPASS_DATAIN01_delay = TX_BYPASS_DATAIN01;
assign #(in_delay) TX_BYPASS_DATAIN02_delay = TX_BYPASS_DATAIN02;
assign #(in_delay) TX_BYPASS_DATAIN03_delay = TX_BYPASS_DATAIN03;
assign #(in_delay) TX_BYPASS_DATAIN04_delay = TX_BYPASS_DATAIN04;
assign #(in_delay) TX_BYPASS_DATAIN05_delay = TX_BYPASS_DATAIN05;
assign #(in_delay) TX_BYPASS_DATAIN06_delay = TX_BYPASS_DATAIN06;
assign #(in_delay) TX_BYPASS_DATAIN07_delay = TX_BYPASS_DATAIN07;
assign #(in_delay) TX_BYPASS_DATAIN08_delay = TX_BYPASS_DATAIN08;
assign #(in_delay) TX_BYPASS_DATAIN09_delay = TX_BYPASS_DATAIN09;
assign #(in_delay) TX_BYPASS_DATAIN10_delay = TX_BYPASS_DATAIN10;
assign #(in_delay) TX_BYPASS_DATAIN11_delay = TX_BYPASS_DATAIN11;
assign #(in_delay) TX_BYPASS_ENAIN_delay = TX_BYPASS_ENAIN;
assign #(in_delay) TX_BYPASS_GEARBOX_SEQIN_delay = TX_BYPASS_GEARBOX_SEQIN;
assign #(in_delay) TX_BYPASS_MFRAMER_STATEIN_delay = TX_BYPASS_MFRAMER_STATEIN;
assign #(in_delay) TX_CHANIN0_delay = TX_CHANIN0;
assign #(in_delay) TX_CHANIN1_delay = TX_CHANIN1;
assign #(in_delay) TX_CHANIN2_delay = TX_CHANIN2;
assign #(in_delay) TX_CHANIN3_delay = TX_CHANIN3;
assign #(in_delay) TX_DATAIN0_delay = TX_DATAIN0;
assign #(in_delay) TX_DATAIN1_delay = TX_DATAIN1;
assign #(in_delay) TX_DATAIN2_delay = TX_DATAIN2;
assign #(in_delay) TX_DATAIN3_delay = TX_DATAIN3;
assign #(in_delay) TX_ENAIN0_delay = TX_ENAIN0;
assign #(in_delay) TX_ENAIN1_delay = TX_ENAIN1;
assign #(in_delay) TX_ENAIN2_delay = TX_ENAIN2;
assign #(in_delay) TX_ENAIN3_delay = TX_ENAIN3;
assign #(in_delay) TX_EOPIN0_delay = TX_EOPIN0;
assign #(in_delay) TX_EOPIN1_delay = TX_EOPIN1;
assign #(in_delay) TX_EOPIN2_delay = TX_EOPIN2;
assign #(in_delay) TX_EOPIN3_delay = TX_EOPIN3;
assign #(in_delay) TX_ERRIN0_delay = TX_ERRIN0;
assign #(in_delay) TX_ERRIN1_delay = TX_ERRIN1;
assign #(in_delay) TX_ERRIN2_delay = TX_ERRIN2;
assign #(in_delay) TX_ERRIN3_delay = TX_ERRIN3;
assign #(in_delay) TX_MTYIN0_delay = TX_MTYIN0;
assign #(in_delay) TX_MTYIN1_delay = TX_MTYIN1;
assign #(in_delay) TX_MTYIN2_delay = TX_MTYIN2;
assign #(in_delay) TX_MTYIN3_delay = TX_MTYIN3;
assign #(in_delay) TX_RESET_delay = TX_RESET;
assign #(in_delay) TX_SERDES_REFCLK_RESET_delay = TX_SERDES_REFCLK_RESET;
assign #(in_delay) TX_SOPIN0_delay = TX_SOPIN0;
assign #(in_delay) TX_SOPIN1_delay = TX_SOPIN1;
assign #(in_delay) TX_SOPIN2_delay = TX_SOPIN2;
assign #(in_delay) TX_SOPIN3_delay = TX_SOPIN3;
assign DRP_DO_delay = DRP_DO_out;
assign DRP_RDY_delay = DRP_RDY_out;
assign RX_BYPASS_DATAOUT00_delay = RX_BYPASS_DATAOUT00_out;
assign RX_BYPASS_DATAOUT01_delay = RX_BYPASS_DATAOUT01_out;
assign RX_BYPASS_DATAOUT02_delay = RX_BYPASS_DATAOUT02_out;
assign RX_BYPASS_DATAOUT03_delay = RX_BYPASS_DATAOUT03_out;
assign RX_BYPASS_DATAOUT04_delay = RX_BYPASS_DATAOUT04_out;
assign RX_BYPASS_DATAOUT05_delay = RX_BYPASS_DATAOUT05_out;
assign RX_BYPASS_DATAOUT06_delay = RX_BYPASS_DATAOUT06_out;
assign RX_BYPASS_DATAOUT07_delay = RX_BYPASS_DATAOUT07_out;
assign RX_BYPASS_DATAOUT08_delay = RX_BYPASS_DATAOUT08_out;
assign RX_BYPASS_DATAOUT09_delay = RX_BYPASS_DATAOUT09_out;
assign RX_BYPASS_DATAOUT10_delay = RX_BYPASS_DATAOUT10_out;
assign RX_BYPASS_DATAOUT11_delay = RX_BYPASS_DATAOUT11_out;
assign RX_BYPASS_ENAOUT_delay = RX_BYPASS_ENAOUT_out;
assign RX_BYPASS_IS_AVAILOUT_delay = RX_BYPASS_IS_AVAILOUT_out;
assign RX_BYPASS_IS_BADLYFRAMEDOUT_delay = RX_BYPASS_IS_BADLYFRAMEDOUT_out;
assign RX_BYPASS_IS_OVERFLOWOUT_delay = RX_BYPASS_IS_OVERFLOWOUT_out;
assign RX_BYPASS_IS_SYNCEDOUT_delay = RX_BYPASS_IS_SYNCEDOUT_out;
assign RX_BYPASS_IS_SYNCWORDOUT_delay = RX_BYPASS_IS_SYNCWORDOUT_out;
assign RX_CHANOUT0_delay = RX_CHANOUT0_out;
assign RX_CHANOUT1_delay = RX_CHANOUT1_out;
assign RX_CHANOUT2_delay = RX_CHANOUT2_out;
assign RX_CHANOUT3_delay = RX_CHANOUT3_out;
assign RX_DATAOUT0_delay = RX_DATAOUT0_out;
assign RX_DATAOUT1_delay = RX_DATAOUT1_out;
assign RX_DATAOUT2_delay = RX_DATAOUT2_out;
assign RX_DATAOUT3_delay = RX_DATAOUT3_out;
assign RX_ENAOUT0_delay = RX_ENAOUT0_out;
assign RX_ENAOUT1_delay = RX_ENAOUT1_out;
assign RX_ENAOUT2_delay = RX_ENAOUT2_out;
assign RX_ENAOUT3_delay = RX_ENAOUT3_out;
assign RX_EOPOUT0_delay = RX_EOPOUT0_out;
assign RX_EOPOUT1_delay = RX_EOPOUT1_out;
assign RX_EOPOUT2_delay = RX_EOPOUT2_out;
assign RX_EOPOUT3_delay = RX_EOPOUT3_out;
assign RX_ERROUT0_delay = RX_ERROUT0_out;
assign RX_ERROUT1_delay = RX_ERROUT1_out;
assign RX_ERROUT2_delay = RX_ERROUT2_out;
assign RX_ERROUT3_delay = RX_ERROUT3_out;
assign RX_MTYOUT0_delay = RX_MTYOUT0_out;
assign RX_MTYOUT1_delay = RX_MTYOUT1_out;
assign RX_MTYOUT2_delay = RX_MTYOUT2_out;
assign RX_MTYOUT3_delay = RX_MTYOUT3_out;
assign RX_OVFOUT_delay = RX_OVFOUT_out;
assign RX_SOPOUT0_delay = RX_SOPOUT0_out;
assign RX_SOPOUT1_delay = RX_SOPOUT1_out;
assign RX_SOPOUT2_delay = RX_SOPOUT2_out;
assign RX_SOPOUT3_delay = RX_SOPOUT3_out;
assign STAT_RX_ALIGNED_ERR_delay = STAT_RX_ALIGNED_ERR_out;
assign STAT_RX_ALIGNED_delay = STAT_RX_ALIGNED_out;
assign STAT_RX_BAD_TYPE_ERR_delay = STAT_RX_BAD_TYPE_ERR_out;
assign STAT_RX_BURSTMAX_ERR_delay = STAT_RX_BURSTMAX_ERR_out;
assign STAT_RX_BURST_ERR_delay = STAT_RX_BURST_ERR_out;
assign STAT_RX_CRC24_ERR_delay = STAT_RX_CRC24_ERR_out;
assign STAT_RX_CRC32_ERR_delay = STAT_RX_CRC32_ERR_out;
assign STAT_RX_CRC32_VALID_delay = STAT_RX_CRC32_VALID_out;
assign STAT_RX_DESCRAM_ERR_delay = STAT_RX_DESCRAM_ERR_out;
assign STAT_RX_DIAGWORD_INTFSTAT_delay = STAT_RX_DIAGWORD_INTFSTAT_out;
assign STAT_RX_DIAGWORD_LANESTAT_delay = STAT_RX_DIAGWORD_LANESTAT_out;
assign STAT_RX_FC_STAT_delay = STAT_RX_FC_STAT_out;
assign STAT_RX_FRAMING_ERR_delay = STAT_RX_FRAMING_ERR_out;
assign STAT_RX_MEOP_ERR_delay = STAT_RX_MEOP_ERR_out;
assign STAT_RX_MF_ERR_delay = STAT_RX_MF_ERR_out;
assign STAT_RX_MF_LEN_ERR_delay = STAT_RX_MF_LEN_ERR_out;
assign STAT_RX_MF_REPEAT_ERR_delay = STAT_RX_MF_REPEAT_ERR_out;
assign STAT_RX_MISALIGNED_delay = STAT_RX_MISALIGNED_out;
assign STAT_RX_MSOP_ERR_delay = STAT_RX_MSOP_ERR_out;
assign STAT_RX_MUBITS_UPDATED_delay = STAT_RX_MUBITS_UPDATED_out;
assign STAT_RX_MUBITS_delay = STAT_RX_MUBITS_out;
assign STAT_RX_OVERFLOW_ERR_delay = STAT_RX_OVERFLOW_ERR_out;
assign STAT_RX_RETRANS_CRC24_ERR_delay = STAT_RX_RETRANS_CRC24_ERR_out;
assign STAT_RX_RETRANS_DISC_delay = STAT_RX_RETRANS_DISC_out;
assign STAT_RX_RETRANS_LATENCY_delay = STAT_RX_RETRANS_LATENCY_out;
assign STAT_RX_RETRANS_REQ_delay = STAT_RX_RETRANS_REQ_out;
assign STAT_RX_RETRANS_RETRY_ERR_delay = STAT_RX_RETRANS_RETRY_ERR_out;
assign STAT_RX_RETRANS_SEQ_UPDATED_delay = STAT_RX_RETRANS_SEQ_UPDATED_out;
assign STAT_RX_RETRANS_SEQ_delay = STAT_RX_RETRANS_SEQ_out;
assign STAT_RX_RETRANS_STATE_delay = STAT_RX_RETRANS_STATE_out;
assign STAT_RX_RETRANS_SUBSEQ_delay = STAT_RX_RETRANS_SUBSEQ_out;
assign STAT_RX_RETRANS_WDOG_ERR_delay = STAT_RX_RETRANS_WDOG_ERR_out;
assign STAT_RX_RETRANS_WRAP_ERR_delay = STAT_RX_RETRANS_WRAP_ERR_out;
assign STAT_RX_SYNCED_ERR_delay = STAT_RX_SYNCED_ERR_out;
assign STAT_RX_SYNCED_delay = STAT_RX_SYNCED_out;
assign STAT_RX_WORD_SYNC_delay = STAT_RX_WORD_SYNC_out;
assign STAT_TX_BURST_ERR_delay = STAT_TX_BURST_ERR_out;
assign STAT_TX_ERRINJ_BITERR_DONE_delay = STAT_TX_ERRINJ_BITERR_DONE_out;
assign STAT_TX_OVERFLOW_ERR_delay = STAT_TX_OVERFLOW_ERR_out;
assign STAT_TX_RETRANS_BURST_ERR_delay = STAT_TX_RETRANS_BURST_ERR_out;
assign STAT_TX_RETRANS_BUSY_delay = STAT_TX_RETRANS_BUSY_out;
assign STAT_TX_RETRANS_RAM_PERROUT_delay = STAT_TX_RETRANS_RAM_PERROUT_out;
assign STAT_TX_RETRANS_RAM_RADDR_delay = STAT_TX_RETRANS_RAM_RADDR_out;
assign STAT_TX_RETRANS_RAM_RD_B0_delay = STAT_TX_RETRANS_RAM_RD_B0_out;
assign STAT_TX_RETRANS_RAM_RD_B1_delay = STAT_TX_RETRANS_RAM_RD_B1_out;
assign STAT_TX_RETRANS_RAM_RD_B2_delay = STAT_TX_RETRANS_RAM_RD_B2_out;
assign STAT_TX_RETRANS_RAM_RD_B3_delay = STAT_TX_RETRANS_RAM_RD_B3_out;
assign STAT_TX_RETRANS_RAM_RSEL_delay = STAT_TX_RETRANS_RAM_RSEL_out;
assign STAT_TX_RETRANS_RAM_WADDR_delay = STAT_TX_RETRANS_RAM_WADDR_out;
assign STAT_TX_RETRANS_RAM_WDATA_delay = STAT_TX_RETRANS_RAM_WDATA_out;
assign STAT_TX_RETRANS_RAM_WE_B0_delay = STAT_TX_RETRANS_RAM_WE_B0_out;
assign STAT_TX_RETRANS_RAM_WE_B1_delay = STAT_TX_RETRANS_RAM_WE_B1_out;
assign STAT_TX_RETRANS_RAM_WE_B2_delay = STAT_TX_RETRANS_RAM_WE_B2_out;
assign STAT_TX_RETRANS_RAM_WE_B3_delay = STAT_TX_RETRANS_RAM_WE_B3_out;
assign STAT_TX_UNDERFLOW_ERR_delay = STAT_TX_UNDERFLOW_ERR_out;
assign TX_OVFOUT_delay = TX_OVFOUT_out;
assign TX_RDYOUT_delay = TX_RDYOUT_out;
assign TX_SERDES_DATA00_delay = TX_SERDES_DATA00_out;
assign TX_SERDES_DATA01_delay = TX_SERDES_DATA01_out;
assign TX_SERDES_DATA02_delay = TX_SERDES_DATA02_out;
assign TX_SERDES_DATA03_delay = TX_SERDES_DATA03_out;
assign TX_SERDES_DATA04_delay = TX_SERDES_DATA04_out;
assign TX_SERDES_DATA05_delay = TX_SERDES_DATA05_out;
assign TX_SERDES_DATA06_delay = TX_SERDES_DATA06_out;
assign TX_SERDES_DATA07_delay = TX_SERDES_DATA07_out;
assign TX_SERDES_DATA08_delay = TX_SERDES_DATA08_out;
assign TX_SERDES_DATA09_delay = TX_SERDES_DATA09_out;
assign TX_SERDES_DATA10_delay = TX_SERDES_DATA10_out;
assign TX_SERDES_DATA11_delay = TX_SERDES_DATA11_out;
assign CORE_CLK_in = CORE_CLK_delay;
assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay;
assign CTL_RX_RETRANS_ACK_in = CTL_RX_RETRANS_ACK_delay;
assign CTL_RX_RETRANS_ENABLE_in = CTL_RX_RETRANS_ENABLE_delay;
assign CTL_RX_RETRANS_ERRIN_in = CTL_RX_RETRANS_ERRIN_delay;
assign CTL_RX_RETRANS_FORCE_REQ_in = CTL_RX_RETRANS_FORCE_REQ_delay;
assign CTL_RX_RETRANS_RESET_MODE_in = CTL_RX_RETRANS_RESET_MODE_delay;
assign CTL_RX_RETRANS_RESET_in = CTL_RX_RETRANS_RESET_delay;
assign CTL_TX_DIAGWORD_INTFSTAT_in = CTL_TX_DIAGWORD_INTFSTAT_delay;
assign CTL_TX_DIAGWORD_LANESTAT_in = CTL_TX_DIAGWORD_LANESTAT_delay;
assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay;
assign CTL_TX_ERRINJ_BITERR_GO_in = CTL_TX_ERRINJ_BITERR_GO_delay;
assign CTL_TX_ERRINJ_BITERR_LANE_in = CTL_TX_ERRINJ_BITERR_LANE_delay;
assign CTL_TX_FC_STAT_in = CTL_TX_FC_STAT_delay;
assign CTL_TX_MUBITS_in = CTL_TX_MUBITS_delay;
assign CTL_TX_RETRANS_ENABLE_in = CTL_TX_RETRANS_ENABLE_delay;
assign CTL_TX_RETRANS_RAM_PERRIN_in = CTL_TX_RETRANS_RAM_PERRIN_delay;
assign CTL_TX_RETRANS_RAM_RDATA_in = CTL_TX_RETRANS_RAM_RDATA_delay;
assign CTL_TX_RETRANS_REQ_VALID_in = CTL_TX_RETRANS_REQ_VALID_delay;
assign CTL_TX_RETRANS_REQ_in = CTL_TX_RETRANS_REQ_delay;
assign CTL_TX_RLIM_DELTA_in = CTL_TX_RLIM_DELTA_delay;
assign CTL_TX_RLIM_ENABLE_in = CTL_TX_RLIM_ENABLE_delay;
assign CTL_TX_RLIM_INTV_in = CTL_TX_RLIM_INTV_delay;
assign CTL_TX_RLIM_MAX_in = CTL_TX_RLIM_MAX_delay;
assign DRP_ADDR_in = DRP_ADDR_delay;
assign DRP_CLK_in = DRP_CLK_delay;
assign DRP_DI_in = DRP_DI_delay;
assign DRP_EN_in = DRP_EN_delay;
assign DRP_WE_in = DRP_WE_delay;
assign LBUS_CLK_in = LBUS_CLK_delay;
assign RX_BYPASS_FORCE_REALIGNIN_in = RX_BYPASS_FORCE_REALIGNIN_delay;
assign RX_BYPASS_RDIN_in = RX_BYPASS_RDIN_delay;
assign RX_RESET_in = RX_RESET_delay;
assign RX_SERDES_CLK_in = RX_SERDES_CLK_delay;
assign RX_SERDES_DATA00_in = RX_SERDES_DATA00_delay;
assign RX_SERDES_DATA01_in = RX_SERDES_DATA01_delay;
assign RX_SERDES_DATA02_in = RX_SERDES_DATA02_delay;
assign RX_SERDES_DATA03_in = RX_SERDES_DATA03_delay;
assign RX_SERDES_DATA04_in = RX_SERDES_DATA04_delay;
assign RX_SERDES_DATA05_in = RX_SERDES_DATA05_delay;
assign RX_SERDES_DATA06_in = RX_SERDES_DATA06_delay;
assign RX_SERDES_DATA07_in = RX_SERDES_DATA07_delay;
assign RX_SERDES_DATA08_in = RX_SERDES_DATA08_delay;
assign RX_SERDES_DATA09_in = RX_SERDES_DATA09_delay;
assign RX_SERDES_DATA10_in = RX_SERDES_DATA10_delay;
assign RX_SERDES_DATA11_in = RX_SERDES_DATA11_delay;
assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay;
assign TX_BCTLIN0_in = TX_BCTLIN0_delay;
assign TX_BCTLIN1_in = TX_BCTLIN1_delay;
assign TX_BCTLIN2_in = TX_BCTLIN2_delay;
assign TX_BCTLIN3_in = TX_BCTLIN3_delay;
assign TX_BYPASS_CTRLIN_in = TX_BYPASS_CTRLIN_delay;
assign TX_BYPASS_DATAIN00_in = TX_BYPASS_DATAIN00_delay;
assign TX_BYPASS_DATAIN01_in = TX_BYPASS_DATAIN01_delay;
assign TX_BYPASS_DATAIN02_in = TX_BYPASS_DATAIN02_delay;
assign TX_BYPASS_DATAIN03_in = TX_BYPASS_DATAIN03_delay;
assign TX_BYPASS_DATAIN04_in = TX_BYPASS_DATAIN04_delay;
assign TX_BYPASS_DATAIN05_in = TX_BYPASS_DATAIN05_delay;
assign TX_BYPASS_DATAIN06_in = TX_BYPASS_DATAIN06_delay;
assign TX_BYPASS_DATAIN07_in = TX_BYPASS_DATAIN07_delay;
assign TX_BYPASS_DATAIN08_in = TX_BYPASS_DATAIN08_delay;
assign TX_BYPASS_DATAIN09_in = TX_BYPASS_DATAIN09_delay;
assign TX_BYPASS_DATAIN10_in = TX_BYPASS_DATAIN10_delay;
assign TX_BYPASS_DATAIN11_in = TX_BYPASS_DATAIN11_delay;
assign TX_BYPASS_ENAIN_in = TX_BYPASS_ENAIN_delay;
assign TX_BYPASS_GEARBOX_SEQIN_in = TX_BYPASS_GEARBOX_SEQIN_delay;
assign TX_BYPASS_MFRAMER_STATEIN_in = TX_BYPASS_MFRAMER_STATEIN_delay;
assign TX_CHANIN0_in = TX_CHANIN0_delay;
assign TX_CHANIN1_in = TX_CHANIN1_delay;
assign TX_CHANIN2_in = TX_CHANIN2_delay;
assign TX_CHANIN3_in = TX_CHANIN3_delay;
assign TX_DATAIN0_in = TX_DATAIN0_delay;
assign TX_DATAIN1_in = TX_DATAIN1_delay;
assign TX_DATAIN2_in = TX_DATAIN2_delay;
assign TX_DATAIN3_in = TX_DATAIN3_delay;
assign TX_ENAIN0_in = TX_ENAIN0_delay;
assign TX_ENAIN1_in = TX_ENAIN1_delay;
assign TX_ENAIN2_in = TX_ENAIN2_delay;
assign TX_ENAIN3_in = TX_ENAIN3_delay;
assign TX_EOPIN0_in = TX_EOPIN0_delay;
assign TX_EOPIN1_in = TX_EOPIN1_delay;
assign TX_EOPIN2_in = TX_EOPIN2_delay;
assign TX_EOPIN3_in = TX_EOPIN3_delay;
assign TX_ERRIN0_in = TX_ERRIN0_delay;
assign TX_ERRIN1_in = TX_ERRIN1_delay;
assign TX_ERRIN2_in = TX_ERRIN2_delay;
assign TX_ERRIN3_in = TX_ERRIN3_delay;
assign TX_MTYIN0_in = TX_MTYIN0_delay;
assign TX_MTYIN1_in = TX_MTYIN1_delay;
assign TX_MTYIN2_in = TX_MTYIN2_delay;
assign TX_MTYIN3_in = TX_MTYIN3_delay;
assign TX_RESET_in = TX_RESET_delay;
assign TX_SERDES_REFCLK_RESET_in = TX_SERDES_REFCLK_RESET_delay;
assign TX_SERDES_REFCLK_in = TX_SERDES_REFCLK_delay;
assign TX_SOPIN0_in = TX_SOPIN0_delay;
assign TX_SOPIN1_in = TX_SOPIN1_delay;
assign TX_SOPIN2_in = TX_SOPIN2_delay;
assign TX_SOPIN3_in = TX_SOPIN3_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((BYPASS_REG != "FALSE") &&
(BYPASS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BYPASS_REG);
attr_err = 1'b1;
end
if ((CTL_RX_PACKET_MODE_REG != "TRUE") &&
(CTL_RX_PACKET_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CTL_RX_PACKET_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CTL_RX_PACKET_MODE_REG);
attr_err = 1'b1;
end
if ((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(CTL_TEST_MODE_PIN_CHAR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CTL_TEST_MODE_PIN_CHAR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if ((CTL_TX_DISABLE_SKIPWORD_REG != "TRUE") &&
(CTL_TX_DISABLE_SKIPWORD_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CTL_TX_DISABLE_SKIPWORD on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CTL_TX_DISABLE_SKIPWORD_REG);
attr_err = 1'b1;
end
if ((MODE_REG != "TRUE") &&
(MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, MODE_REG);
attr_err = 1'b1;
end
if ((TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(TEST_MODE_PIN_CHAR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TEST_MODE_PIN_CHAR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign SCAN_EN_N_in = 1'b1; // tie off
assign SCAN_IN_in = 265'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign TEST_MODE_N_in = 1'b1; // tie off
assign TEST_RESET_in = 1'b1; // tie off
SIP_ILKN SIP_ILKN_INST (
.BYPASS (BYPASS_REG),
.CTL_RX_BURSTMAX (CTL_RX_BURSTMAX_REG),
.CTL_RX_CHAN_EXT (CTL_RX_CHAN_EXT_REG),
.CTL_RX_LAST_LANE (CTL_RX_LAST_LANE_REG),
.CTL_RX_MFRAMELEN_MINUS1 (CTL_RX_MFRAMELEN_MINUS1_REG),
.CTL_RX_PACKET_MODE (CTL_RX_PACKET_MODE_REG),
.CTL_RX_RETRANS_MULT (CTL_RX_RETRANS_MULT_REG),
.CTL_RX_RETRANS_RETRY (CTL_RX_RETRANS_RETRY_REG),
.CTL_RX_RETRANS_TIMER1 (CTL_RX_RETRANS_TIMER1_REG),
.CTL_RX_RETRANS_TIMER2 (CTL_RX_RETRANS_TIMER2_REG),
.CTL_RX_RETRANS_WDOG (CTL_RX_RETRANS_WDOG_REG),
.CTL_RX_RETRANS_WRAP_TIMER (CTL_RX_RETRANS_WRAP_TIMER_REG),
.CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG),
.CTL_TX_BURSTMAX (CTL_TX_BURSTMAX_REG),
.CTL_TX_BURSTSHORT (CTL_TX_BURSTSHORT_REG),
.CTL_TX_CHAN_EXT (CTL_TX_CHAN_EXT_REG),
.CTL_TX_DISABLE_SKIPWORD (CTL_TX_DISABLE_SKIPWORD_REG),
.CTL_TX_FC_CALLEN (CTL_TX_FC_CALLEN_REG),
.CTL_TX_LAST_LANE (CTL_TX_LAST_LANE_REG),
.CTL_TX_MFRAMELEN_MINUS1 (CTL_TX_MFRAMELEN_MINUS1_REG),
.CTL_TX_RETRANS_DEPTH (CTL_TX_RETRANS_DEPTH_REG),
.CTL_TX_RETRANS_MULT (CTL_TX_RETRANS_MULT_REG),
.CTL_TX_RETRANS_RAM_BANKS (CTL_TX_RETRANS_RAM_BANKS_REG),
.MODE (MODE_REG),
.TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG),
.DRP_DO (DRP_DO_out),
.DRP_RDY (DRP_RDY_out),
.RX_BYPASS_DATAOUT00 (RX_BYPASS_DATAOUT00_out),
.RX_BYPASS_DATAOUT01 (RX_BYPASS_DATAOUT01_out),
.RX_BYPASS_DATAOUT02 (RX_BYPASS_DATAOUT02_out),
.RX_BYPASS_DATAOUT03 (RX_BYPASS_DATAOUT03_out),
.RX_BYPASS_DATAOUT04 (RX_BYPASS_DATAOUT04_out),
.RX_BYPASS_DATAOUT05 (RX_BYPASS_DATAOUT05_out),
.RX_BYPASS_DATAOUT06 (RX_BYPASS_DATAOUT06_out),
.RX_BYPASS_DATAOUT07 (RX_BYPASS_DATAOUT07_out),
.RX_BYPASS_DATAOUT08 (RX_BYPASS_DATAOUT08_out),
.RX_BYPASS_DATAOUT09 (RX_BYPASS_DATAOUT09_out),
.RX_BYPASS_DATAOUT10 (RX_BYPASS_DATAOUT10_out),
.RX_BYPASS_DATAOUT11 (RX_BYPASS_DATAOUT11_out),
.RX_BYPASS_ENAOUT (RX_BYPASS_ENAOUT_out),
.RX_BYPASS_IS_AVAILOUT (RX_BYPASS_IS_AVAILOUT_out),
.RX_BYPASS_IS_BADLYFRAMEDOUT (RX_BYPASS_IS_BADLYFRAMEDOUT_out),
.RX_BYPASS_IS_OVERFLOWOUT (RX_BYPASS_IS_OVERFLOWOUT_out),
.RX_BYPASS_IS_SYNCEDOUT (RX_BYPASS_IS_SYNCEDOUT_out),
.RX_BYPASS_IS_SYNCWORDOUT (RX_BYPASS_IS_SYNCWORDOUT_out),
.RX_CHANOUT0 (RX_CHANOUT0_out),
.RX_CHANOUT1 (RX_CHANOUT1_out),
.RX_CHANOUT2 (RX_CHANOUT2_out),
.RX_CHANOUT3 (RX_CHANOUT3_out),
.RX_DATAOUT0 (RX_DATAOUT0_out),
.RX_DATAOUT1 (RX_DATAOUT1_out),
.RX_DATAOUT2 (RX_DATAOUT2_out),
.RX_DATAOUT3 (RX_DATAOUT3_out),
.RX_ENAOUT0 (RX_ENAOUT0_out),
.RX_ENAOUT1 (RX_ENAOUT1_out),
.RX_ENAOUT2 (RX_ENAOUT2_out),
.RX_ENAOUT3 (RX_ENAOUT3_out),
.RX_EOPOUT0 (RX_EOPOUT0_out),
.RX_EOPOUT1 (RX_EOPOUT1_out),
.RX_EOPOUT2 (RX_EOPOUT2_out),
.RX_EOPOUT3 (RX_EOPOUT3_out),
.RX_ERROUT0 (RX_ERROUT0_out),
.RX_ERROUT1 (RX_ERROUT1_out),
.RX_ERROUT2 (RX_ERROUT2_out),
.RX_ERROUT3 (RX_ERROUT3_out),
.RX_MTYOUT0 (RX_MTYOUT0_out),
.RX_MTYOUT1 (RX_MTYOUT1_out),
.RX_MTYOUT2 (RX_MTYOUT2_out),
.RX_MTYOUT3 (RX_MTYOUT3_out),
.RX_OVFOUT (RX_OVFOUT_out),
.RX_SOPOUT0 (RX_SOPOUT0_out),
.RX_SOPOUT1 (RX_SOPOUT1_out),
.RX_SOPOUT2 (RX_SOPOUT2_out),
.RX_SOPOUT3 (RX_SOPOUT3_out),
.SCAN_OUT (SCAN_OUT_out),
.STAT_RX_ALIGNED (STAT_RX_ALIGNED_out),
.STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out),
.STAT_RX_BAD_TYPE_ERR (STAT_RX_BAD_TYPE_ERR_out),
.STAT_RX_BURSTMAX_ERR (STAT_RX_BURSTMAX_ERR_out),
.STAT_RX_BURST_ERR (STAT_RX_BURST_ERR_out),
.STAT_RX_CRC24_ERR (STAT_RX_CRC24_ERR_out),
.STAT_RX_CRC32_ERR (STAT_RX_CRC32_ERR_out),
.STAT_RX_CRC32_VALID (STAT_RX_CRC32_VALID_out),
.STAT_RX_DESCRAM_ERR (STAT_RX_DESCRAM_ERR_out),
.STAT_RX_DIAGWORD_INTFSTAT (STAT_RX_DIAGWORD_INTFSTAT_out),
.STAT_RX_DIAGWORD_LANESTAT (STAT_RX_DIAGWORD_LANESTAT_out),
.STAT_RX_FC_STAT (STAT_RX_FC_STAT_out),
.STAT_RX_FRAMING_ERR (STAT_RX_FRAMING_ERR_out),
.STAT_RX_MEOP_ERR (STAT_RX_MEOP_ERR_out),
.STAT_RX_MF_ERR (STAT_RX_MF_ERR_out),
.STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out),
.STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out),
.STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out),
.STAT_RX_MSOP_ERR (STAT_RX_MSOP_ERR_out),
.STAT_RX_MUBITS (STAT_RX_MUBITS_out),
.STAT_RX_MUBITS_UPDATED (STAT_RX_MUBITS_UPDATED_out),
.STAT_RX_OVERFLOW_ERR (STAT_RX_OVERFLOW_ERR_out),
.STAT_RX_RETRANS_CRC24_ERR (STAT_RX_RETRANS_CRC24_ERR_out),
.STAT_RX_RETRANS_DISC (STAT_RX_RETRANS_DISC_out),
.STAT_RX_RETRANS_LATENCY (STAT_RX_RETRANS_LATENCY_out),
.STAT_RX_RETRANS_REQ (STAT_RX_RETRANS_REQ_out),
.STAT_RX_RETRANS_RETRY_ERR (STAT_RX_RETRANS_RETRY_ERR_out),
.STAT_RX_RETRANS_SEQ (STAT_RX_RETRANS_SEQ_out),
.STAT_RX_RETRANS_SEQ_UPDATED (STAT_RX_RETRANS_SEQ_UPDATED_out),
.STAT_RX_RETRANS_STATE (STAT_RX_RETRANS_STATE_out),
.STAT_RX_RETRANS_SUBSEQ (STAT_RX_RETRANS_SUBSEQ_out),
.STAT_RX_RETRANS_WDOG_ERR (STAT_RX_RETRANS_WDOG_ERR_out),
.STAT_RX_RETRANS_WRAP_ERR (STAT_RX_RETRANS_WRAP_ERR_out),
.STAT_RX_SYNCED (STAT_RX_SYNCED_out),
.STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out),
.STAT_RX_WORD_SYNC (STAT_RX_WORD_SYNC_out),
.STAT_TX_BURST_ERR (STAT_TX_BURST_ERR_out),
.STAT_TX_ERRINJ_BITERR_DONE (STAT_TX_ERRINJ_BITERR_DONE_out),
.STAT_TX_OVERFLOW_ERR (STAT_TX_OVERFLOW_ERR_out),
.STAT_TX_RETRANS_BURST_ERR (STAT_TX_RETRANS_BURST_ERR_out),
.STAT_TX_RETRANS_BUSY (STAT_TX_RETRANS_BUSY_out),
.STAT_TX_RETRANS_RAM_PERROUT (STAT_TX_RETRANS_RAM_PERROUT_out),
.STAT_TX_RETRANS_RAM_RADDR (STAT_TX_RETRANS_RAM_RADDR_out),
.STAT_TX_RETRANS_RAM_RD_B0 (STAT_TX_RETRANS_RAM_RD_B0_out),
.STAT_TX_RETRANS_RAM_RD_B1 (STAT_TX_RETRANS_RAM_RD_B1_out),
.STAT_TX_RETRANS_RAM_RD_B2 (STAT_TX_RETRANS_RAM_RD_B2_out),
.STAT_TX_RETRANS_RAM_RD_B3 (STAT_TX_RETRANS_RAM_RD_B3_out),
.STAT_TX_RETRANS_RAM_RSEL (STAT_TX_RETRANS_RAM_RSEL_out),
.STAT_TX_RETRANS_RAM_WADDR (STAT_TX_RETRANS_RAM_WADDR_out),
.STAT_TX_RETRANS_RAM_WDATA (STAT_TX_RETRANS_RAM_WDATA_out),
.STAT_TX_RETRANS_RAM_WE_B0 (STAT_TX_RETRANS_RAM_WE_B0_out),
.STAT_TX_RETRANS_RAM_WE_B1 (STAT_TX_RETRANS_RAM_WE_B1_out),
.STAT_TX_RETRANS_RAM_WE_B2 (STAT_TX_RETRANS_RAM_WE_B2_out),
.STAT_TX_RETRANS_RAM_WE_B3 (STAT_TX_RETRANS_RAM_WE_B3_out),
.STAT_TX_UNDERFLOW_ERR (STAT_TX_UNDERFLOW_ERR_out),
.TX_OVFOUT (TX_OVFOUT_out),
.TX_RDYOUT (TX_RDYOUT_out),
.TX_SERDES_DATA00 (TX_SERDES_DATA00_out),
.TX_SERDES_DATA01 (TX_SERDES_DATA01_out),
.TX_SERDES_DATA02 (TX_SERDES_DATA02_out),
.TX_SERDES_DATA03 (TX_SERDES_DATA03_out),
.TX_SERDES_DATA04 (TX_SERDES_DATA04_out),
.TX_SERDES_DATA05 (TX_SERDES_DATA05_out),
.TX_SERDES_DATA06 (TX_SERDES_DATA06_out),
.TX_SERDES_DATA07 (TX_SERDES_DATA07_out),
.TX_SERDES_DATA08 (TX_SERDES_DATA08_out),
.TX_SERDES_DATA09 (TX_SERDES_DATA09_out),
.TX_SERDES_DATA10 (TX_SERDES_DATA10_out),
.TX_SERDES_DATA11 (TX_SERDES_DATA11_out),
.CORE_CLK (CORE_CLK_in),
.CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in),
.CTL_RX_RETRANS_ACK (CTL_RX_RETRANS_ACK_in),
.CTL_RX_RETRANS_ENABLE (CTL_RX_RETRANS_ENABLE_in),
.CTL_RX_RETRANS_ERRIN (CTL_RX_RETRANS_ERRIN_in),
.CTL_RX_RETRANS_FORCE_REQ (CTL_RX_RETRANS_FORCE_REQ_in),
.CTL_RX_RETRANS_RESET (CTL_RX_RETRANS_RESET_in),
.CTL_RX_RETRANS_RESET_MODE (CTL_RX_RETRANS_RESET_MODE_in),
.CTL_TX_DIAGWORD_INTFSTAT (CTL_TX_DIAGWORD_INTFSTAT_in),
.CTL_TX_DIAGWORD_LANESTAT (CTL_TX_DIAGWORD_LANESTAT_in),
.CTL_TX_ENABLE (CTL_TX_ENABLE_in),
.CTL_TX_ERRINJ_BITERR_GO (CTL_TX_ERRINJ_BITERR_GO_in),
.CTL_TX_ERRINJ_BITERR_LANE (CTL_TX_ERRINJ_BITERR_LANE_in),
.CTL_TX_FC_STAT (CTL_TX_FC_STAT_in),
.CTL_TX_MUBITS (CTL_TX_MUBITS_in),
.CTL_TX_RETRANS_ENABLE (CTL_TX_RETRANS_ENABLE_in),
.CTL_TX_RETRANS_RAM_PERRIN (CTL_TX_RETRANS_RAM_PERRIN_in),
.CTL_TX_RETRANS_RAM_RDATA (CTL_TX_RETRANS_RAM_RDATA_in),
.CTL_TX_RETRANS_REQ (CTL_TX_RETRANS_REQ_in),
.CTL_TX_RETRANS_REQ_VALID (CTL_TX_RETRANS_REQ_VALID_in),
.CTL_TX_RLIM_DELTA (CTL_TX_RLIM_DELTA_in),
.CTL_TX_RLIM_ENABLE (CTL_TX_RLIM_ENABLE_in),
.CTL_TX_RLIM_INTV (CTL_TX_RLIM_INTV_in),
.CTL_TX_RLIM_MAX (CTL_TX_RLIM_MAX_in),
.DRP_ADDR (DRP_ADDR_in),
.DRP_CLK (DRP_CLK_in),
.DRP_DI (DRP_DI_in),
.DRP_EN (DRP_EN_in),
.DRP_WE (DRP_WE_in),
.LBUS_CLK (LBUS_CLK_in),
.RX_BYPASS_FORCE_REALIGNIN (RX_BYPASS_FORCE_REALIGNIN_in),
.RX_BYPASS_RDIN (RX_BYPASS_RDIN_in),
.RX_RESET (RX_RESET_in),
.RX_SERDES_CLK (RX_SERDES_CLK_in),
.RX_SERDES_DATA00 (RX_SERDES_DATA00_in),
.RX_SERDES_DATA01 (RX_SERDES_DATA01_in),
.RX_SERDES_DATA02 (RX_SERDES_DATA02_in),
.RX_SERDES_DATA03 (RX_SERDES_DATA03_in),
.RX_SERDES_DATA04 (RX_SERDES_DATA04_in),
.RX_SERDES_DATA05 (RX_SERDES_DATA05_in),
.RX_SERDES_DATA06 (RX_SERDES_DATA06_in),
.RX_SERDES_DATA07 (RX_SERDES_DATA07_in),
.RX_SERDES_DATA08 (RX_SERDES_DATA08_in),
.RX_SERDES_DATA09 (RX_SERDES_DATA09_in),
.RX_SERDES_DATA10 (RX_SERDES_DATA10_in),
.RX_SERDES_DATA11 (RX_SERDES_DATA11_in),
.RX_SERDES_RESET (RX_SERDES_RESET_in),
.SCAN_EN_N (SCAN_EN_N_in),
.SCAN_IN (SCAN_IN_in),
.TEST_MODE_N (TEST_MODE_N_in),
.TEST_RESET (TEST_RESET_in),
.TX_BCTLIN0 (TX_BCTLIN0_in),
.TX_BCTLIN1 (TX_BCTLIN1_in),
.TX_BCTLIN2 (TX_BCTLIN2_in),
.TX_BCTLIN3 (TX_BCTLIN3_in),
.TX_BYPASS_CTRLIN (TX_BYPASS_CTRLIN_in),
.TX_BYPASS_DATAIN00 (TX_BYPASS_DATAIN00_in),
.TX_BYPASS_DATAIN01 (TX_BYPASS_DATAIN01_in),
.TX_BYPASS_DATAIN02 (TX_BYPASS_DATAIN02_in),
.TX_BYPASS_DATAIN03 (TX_BYPASS_DATAIN03_in),
.TX_BYPASS_DATAIN04 (TX_BYPASS_DATAIN04_in),
.TX_BYPASS_DATAIN05 (TX_BYPASS_DATAIN05_in),
.TX_BYPASS_DATAIN06 (TX_BYPASS_DATAIN06_in),
.TX_BYPASS_DATAIN07 (TX_BYPASS_DATAIN07_in),
.TX_BYPASS_DATAIN08 (TX_BYPASS_DATAIN08_in),
.TX_BYPASS_DATAIN09 (TX_BYPASS_DATAIN09_in),
.TX_BYPASS_DATAIN10 (TX_BYPASS_DATAIN10_in),
.TX_BYPASS_DATAIN11 (TX_BYPASS_DATAIN11_in),
.TX_BYPASS_ENAIN (TX_BYPASS_ENAIN_in),
.TX_BYPASS_GEARBOX_SEQIN (TX_BYPASS_GEARBOX_SEQIN_in),
.TX_BYPASS_MFRAMER_STATEIN (TX_BYPASS_MFRAMER_STATEIN_in),
.TX_CHANIN0 (TX_CHANIN0_in),
.TX_CHANIN1 (TX_CHANIN1_in),
.TX_CHANIN2 (TX_CHANIN2_in),
.TX_CHANIN3 (TX_CHANIN3_in),
.TX_DATAIN0 (TX_DATAIN0_in),
.TX_DATAIN1 (TX_DATAIN1_in),
.TX_DATAIN2 (TX_DATAIN2_in),
.TX_DATAIN3 (TX_DATAIN3_in),
.TX_ENAIN0 (TX_ENAIN0_in),
.TX_ENAIN1 (TX_ENAIN1_in),
.TX_ENAIN2 (TX_ENAIN2_in),
.TX_ENAIN3 (TX_ENAIN3_in),
.TX_EOPIN0 (TX_EOPIN0_in),
.TX_EOPIN1 (TX_EOPIN1_in),
.TX_EOPIN2 (TX_EOPIN2_in),
.TX_EOPIN3 (TX_EOPIN3_in),
.TX_ERRIN0 (TX_ERRIN0_in),
.TX_ERRIN1 (TX_ERRIN1_in),
.TX_ERRIN2 (TX_ERRIN2_in),
.TX_ERRIN3 (TX_ERRIN3_in),
.TX_MTYIN0 (TX_MTYIN0_in),
.TX_MTYIN1 (TX_MTYIN1_in),
.TX_MTYIN2 (TX_MTYIN2_in),
.TX_MTYIN3 (TX_MTYIN3_in),
.TX_RESET (TX_RESET_in),
.TX_SERDES_REFCLK (TX_SERDES_REFCLK_in),
.TX_SERDES_REFCLK_RESET (TX_SERDES_REFCLK_RESET_in),
.TX_SOPIN0 (TX_SOPIN0_in),
.TX_SOPIN1 (TX_SOPIN1_in),
.TX_SOPIN2 (TX_SOPIN2_in),
.TX_SOPIN3 (TX_SOPIN3_in),
.GSR (glblGSR)
);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/INBUF.v 0000664 0000000 0000000 00000013251 12327044266 0022267 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : INBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module INBUF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
input [3:0] OSC,
input OSC_EN,
input PAD,
input VREF
);
// define constants
localparam MODULE_NAME = "INBUF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam ISTANDARD_UNUSED = 0;
// `ifndef XIL_DR
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] ISTANDARD_REG = ISTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
// `endif
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire ISTANDARD_BIN;
wire [5:0] SIM_INPUT_BUFFER_OFFSET_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "INBUF_dr.v"
// `endif
wire O_out;
reg O_OSC_in;
wire O_delay;
wire OSC_EN_in;
wire PAD_in;
wire VREF_in;
wire [3:0] OSC_in;
wire OSC_EN_delay;
wire PAD_delay;
wire VREF_delay;
wire [3:0] OSC_delay;
// input output assignments
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) PAD_delay = PAD;
assign #(in_delay) VREF_delay = VREF;
assign O_delay = O_out;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign PAD_in = PAD_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
assign O_out = (OSC_EN_in === 1'b1) ? O_OSC_in : PAD_in;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
// if (OSC_EN_in === 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= 1'bx;
// end
end
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign ISTANDARD_BIN =
(ISTANDARD_REG == "UNUSED") ? ISTANDARD_UNUSED :
ISTANDARD_UNUSED;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
always @ (trig_attr) begin
#1;
if ((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((ISTANDARD_REG != "UNUSED") && (ISTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute ISTANDARD on %s instance %m is set to %s. Legal values for this attribute are UNUSED.", MODULE_NAME, ISTANDARD_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
specify
(PAD => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/INV.v 0000664 0000000 0000000 00000002155 12327044266 0022061 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/X_INV.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Inverter
// /___/ /\ Filename : INV.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module INV (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
not n1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IN_FIFO.v 0000664 0000000 0000000 00000025262 12327044266 0022542 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fujisan IN FIFO
// /__/ /\ Filename : IN_FIFO.v
// \ \ / \
// \__\/\__ \
//
// Date: Comment:
// 08MAR2010 Initial UNI/UNP/SIM version from yml
// 03JUN2010 yml update
// 29JUN2010 enable encrypted rtl
// 10AUG2010 yml, rtl update
// 29SEP2010 minor cleanup
// add width checks, full path support
// 28OCT2010 rtl update
// 05NOV2010 update defaults
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP, make default
// 21SEP2011 625537 period checks on RDCLK, WRCLK
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IN_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "IN_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [7:0] Q0;
output [7:0] Q1;
output [7:0] Q2;
output [7:0] Q3;
output [7:0] Q4;
output [7:0] Q5;
output [7:0] Q6;
output [7:0] Q7;
output [7:0] Q8;
output [7:0] Q9;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [3:0] D0;
input [3:0] D1;
input [3:0] D2;
input [3:0] D3;
input [3:0] D4;
input [3:0] D7;
input [3:0] D8;
input [3:0] D9;
input [7:0] D5;
input [7:0] D6;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
$finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
$finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_4_X_8" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_4_X_8 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
$finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
$finish;
end
endcase
end
wire [7:0] delay_Q0;
wire [7:0] delay_Q1;
wire [7:0] delay_Q2;
wire [7:0] delay_Q3;
wire [7:0] delay_Q4;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire [7:0] delay_Q7;
wire [7:0] delay_Q8;
wire [7:0] delay_Q9;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [3:0] delay_D0;
wire [3:0] delay_D1;
wire [3:0] delay_D2;
wire [3:0] delay_D3;
wire [3:0] delay_D4;
wire [3:0] delay_D7;
wire [3:0] delay_D8;
wire [3:0] delay_D9;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_IN_FIFO IN_FIFO_INST
(
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // IN_FIFO
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUF.v 0000664 0000000 0000000 00000004266 12327044266 0022276 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.11 2009/08/21 23:55:43 harikr Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF (O, IO, I, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO)= (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS.v 0000664 0000000 0000000 00000011153 12327044266 0022516 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/26/07 - Add else to handle x case for o_out (CR 424214).
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 03/19/09 - CR 511590 - Added Z condition handling
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 10/14/09 - CR 535630 - Added DIFF_TERM attribute.
// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures.
// 12/01/10 - CR 584500 - added attribute SLEW
// 08/08/11 - CR 616816 - ncsim compile error during XIL_TIMING
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/28/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS (O, IO, IOB, I, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
localparam MODULE_NAME = "IOBUFDS";
output O;
inout IO, IOB;
input I, T;
wire i_in, io_in, iob_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
reg DQS_BIAS_BINARY = 1'b0;
wire t_or_gts;
tri0 GTS = glbl.GTS;
assign i_in = I;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on %s instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", MODULE_NAME, IOSTANDARD);
end
end
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((io_in === 1'bx) || (iob_in == 1'bx))
o_out <= 1'bx;
end
// assign O = (t_in === 1'b0) ? 1'b1 : ((t_in === 1'b1) ? o_out : 1'bx));
assign O = o_out;
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDSE3.v 0000664 0000000 0000000 00000014274 12327044266 0022715 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IOBUFDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDSE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
inout IO,
inout IOB,
input I,
input [3:0] OSC,
input [1:0] OSC_EN,
input T,
input VREF
);
// define constants
localparam MODULE_NAME = "IOBUFDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
//localparam signed [6:0] SIM_INPUT_BUFFER_OFFSET = -7'd50;
// Parameter encodings and registers
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire IOSTANDARD_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
reg O_out;
wire IO_out;
wire IOB_out;
reg O_OSC_in;
wire O_delay;
wire I_in;
wire IO_in;
wire IOB_in;
wire VREF_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire I_delay;
wire IOB_delay_I;
wire IO_delay_I;
wire IO_delay_O;
wire IOB_delay_O;
wire VREF_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
wire ts;
integer OSC_int = 0;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 B1 (IO_out, I_in, ts);
notif0 N1 (IOB_out, I_in, ts);
assign #(out_delay) O = O_delay;
assign #(out_delay) IO = IO_delay_O;
assign #(out_delay) IOB = IOB_delay_O;
// inputs with no timing checks
assign #(in_delay) IOB_delay_I = IOB;
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign #(in_delay) IO_delay_I = IO;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
//assign O_delay = O_out;
assign IO_delay_O = IO_out;
assign IOB_delay_O = IOB_out;
assign I_in = I_delay;
assign T_in = T_delay;
assign IO_in = IO_delay_I;
assign IOB_in = IOB_delay_I;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
assign O_delay = (OSC_EN_in == 2'b11) ? O_OSC_in : (OSC_EN_in == 2'b10 || OSC_EN_in == 2'b01) ? 1'bx : O_out;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= 1'bx;
end
initial begin
#1;
trig_attr = ~trig_attr;
end
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
IBUF_LOW_PWR_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
always @ (trig_attr) begin
#1;
if ((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(IO_in or IOB_in or DQS_BIAS_BIN) begin
if (IO_in == 1'b1 && IOB_in == 1'b0)
O_out <= 1'b1;
else if (IO_in == 1'b0 && IOB_in == 1'b1)
O_out <= 1'b0;
else if ((IO_in === 1'bz || IO_in == 1'b0) && (IOB_in === 1'bz || IOB_in == 1'b1))
if (DQS_BIAS_BIN == 1'b1)
O_out <= 1'b0;
else
O_out <= 1'bx;
else if ((IO_in === 1'bx) || (IOB_in === 1'bx))
O_out <= 1'bx;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS_DCIEN.v 0000664 0000000 0000000 00000013715 12327044266 0023426 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DCIEN.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DCIEN (O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IOBUFDS_DCIEN";
output O;
inout IO;
inout IOB;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input T;
wire i_in, io_in, iob_in, ibufdisable_in, dcitermdisable_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
wire t_or_gts;
wire not_t_or_ibufdisable;
tri0 GTS = glbl.GTS;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((not_t_or_ibufdisable === 1'b1) ? 1'b1 : ((not_t_or_ibufdisable === 1'b0) ? o_out : 1'bx));
assign dcitermdisable_in = DCITERMDISABLE;
assign i_in = I;
assign ibufdisable_in = IBUFDISABLE;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
assign not_t_or_ibufdisable = ~t_in || ibufdisable_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on IOBUFDS_DCIEN instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD);
end
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (io_in === 1'bx || iob_in === 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS_DIFF_OUT.v 0000664 0000000 0000000 00000006363 12327044266 0024044 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT.v
// \ \ / \ Timestamp : Tue May 26 17:09:31 PDT 2009
// \___\/\___\
//
// Revision:
// 05/26/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT (O, OB, IO, IOB, I, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
output OB;
inout IO;
inout IOB;
input I;
input TM;
input TS;
wire t1, t2;
tri0 GTS = glbl.GTS;
reg O_out, OB_out;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
assign O = O_out;
assign OB = OB_out;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase // case(IBUF_LOW_PWR)
end
always @(IO or IOB) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_out = IO;
OB_out = ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_out = IO;
OB_out = ~IO;
end
else begin
O_out = 1'bx;
OB_out = 1'bx;
end
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IO) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IOB => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS_DIFF_OUT_DCIEN.v 0000664 0000000 0000000 00000011522 12327044266 0024737 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT_DCIEN (O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
inout IO;
inout IOB;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input TM;
input TS;
wire t1, t2;
wire T_OR_IBUFDISABLE_1;
wire T_OR_IBUFDISABLE_2;
tri0 GTS = glbl.GTS;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
reg O_int, OB_int;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(IO or IOB) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_int = IO;
OB_int = ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_int = IO;
OB_int = ~IO;
end
else begin
O_int = 1'bx;
OB_int = 1'bx;
end
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE;
assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx;
assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx;
end
"FALSE" : begin
assign O = O_int;
assign OB = OB_int;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS_DIFF_OUT_INTERMDISABLE.v 0000664 0000000 0000000 00000011520 12327044266 0026075 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
inout IO;
inout IOB;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input TM;
input TS;
wire t1, t2;
wire T_OR_IBUFDISABLE_1;
wire T_OR_IBUFDISABLE_2;
tri0 GTS = glbl.GTS;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
reg O_int, OB_int;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(IO or IOB) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_int = IO;
OB_int = ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_int = IO;
OB_int = ~IO;
end
else begin
O_int = 1'bx;
OB_int = 1'bx;
end
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE;
assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx;
assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx;
end
"FALSE" : begin
assign O = O_int;
assign OB = OB_int;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => OB) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFDS_INTERMDISABLE.v 0000664 0000000 0000000 00000014027 12327044266 0024563 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_INTERMDISABLE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_INTERMDISABLE (O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IOBUFDS_INTERMDISABLE";
output O;
inout IO;
inout IOB;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input T;
wire i_in, io_in, iob_in, ibufdisable_in, intermdisable_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
wire t_or_gts;
wire not_t_or_ibufdisable;
// wire disable_out;
tri0 GTS = glbl.GTS;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((not_t_or_ibufdisable === 1'b1) ? 1'b1 : ((not_t_or_ibufdisable === 1'b0) ? o_out : 1'bx));
assign intermdisable_in = INTERMDISABLE;
assign i_in = I;
assign ibufdisable_in = IBUFDISABLE;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
// assign disable_out = intermdisable_in && ibufdisable_in;
assign not_t_or_ibufdisable = ~t_in || ibufdisable_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on IOBUFDS_DCIEN instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD);
end
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (io_in === 1'bx || iob_in === 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUFE3.v 0000664 0000000 0000000 00000012512 12327044266 0022457 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IOBUFE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUFE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DRIVE = 12,
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
inout IO,
input I,
input [3:0] OSC,
input OSC_EN,
input T,
input VREF
);
// define constants
localparam MODULE_NAME = "IOBUFE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
//localparam signed [6:0] SIM_INPUT_BUFFER_OFFSET = -7'd50;
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
// `ifndef XIL_DR
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam [4:0] DRIVE_REG = DRIVE;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
// `endif
wire IBUF_LOW_PWR_BIN;
wire IOSTANDARD_BIN;
wire [4:0] DRIVE_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "IOBUFE3_dr.v"
// `endif
wire O_out;
reg O_OSC_in;
wire O_delay;
wire I_in;
wire T_in;
wire IO_in;
wire IO_out;
wire OSC_EN_in;
wire VREF_in;
wire [3:0] OSC_in;
wire I_delay;
wire T_delay;
wire IO_delay_O;
wire IO_delay_I;
wire OSC_EN_delay;
wire VREF_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign #(in_delay) IO_delay_I = IO;
assign #(in_delay) IO = IO_delay_O;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_delay = O_out;
assign IO_delay_O = IO_out;
assign I_in = I_delay;
assign T_in = T_delay;
assign IO_in = IO_delay_I;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
wire ts;
integer OSC_int = 0;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 T1 (IO_out, I_in, ts);
assign O_out = (OSC_EN_in) ? O_OSC_in : IO_in;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
#1;
trig_attr = ~trig_attr;
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign DRIVE_BIN = DRIVE_REG;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
IBUF_LOW_PWR_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
always @ (trig_attr) begin
#1;
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if ((DRIVE_REG < 2) || (DRIVE_REG > 24)) begin
$display("Attribute Syntax Error : The attribute DRIVE on %s instance %m is set to %d. Legal values for this attribute are 2 to 24.", MODULE_NAME, DRIVE_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUF_DCIEN.v 0000664 0000000 0000000 00000006034 12327044266 0023173 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_DCIEN.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_DCIEN (O, IO, DCITERMDISABLE, I, IBUFDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input T;
wire ts;
wire T_OR_IBUFDISABLE;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
and a1 (disable_out, DCITERMDISABLE, IBUFDISABLE);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end // initial begin
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/IOBUF_INTERMDISABLE.v 0000664 0000000 0000000 00000005717 12327044266 0024342 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_INTERMDISABLE (O, IO, I, IBUFDISABLE, INTERMDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input T;
wire ts;
wire T_OR_IBUFDISABLE;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end // initial begin
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? 1'b1 : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ISERDES.v 0000664 0000000 0000000 00000125363 12327044266 0022532 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Input Deserializer
// /___/ /\ Filename : ISERDES.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 03/18/05 - Changed SIM_TAPDELAY_VALUE to 75 from 78.
// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV
// 07/19/06 - CR 234556 fix. Added SIM_DELAY_D, SIM_SETUP_D_CLK and SIM_HOLD_D_CLK
// 10/13/06 - CR 424503 fix. False setup/hold warnings during post ngd simulation
// 10/13/06 - Fixed CR 426606
// 06/06/07 - Added wire declaration for internal signals
// 07/02/07 - CR 441960 -- made some params into localparams
// 04/15/08 - CR 468871 Negative SetupHold fix
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR);
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKDIV;
input D;
input DLYCE;
input DLYINC;
input DLYRST;
input OCLK;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter IOBDELAY_TYPE = "DEFAULT";
parameter integer IOBDELAY_VALUE = 0;
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
parameter integer SIM_DELAY_D = 0;
parameter integer SIM_SETUP_D_CLK = 0;
parameter integer SIM_HOLD_D_CLK = 0;
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
localparam DELAY_D = (IOBDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
integer delay_count, delay_count_int;
integer clk_change_time, data_change_time;
integer return_code = 0;
//-----------------------------------------------------------------
//-------------- Function xsetuphold_chk -------------------------
//-----------------------------------------------------------------
function xsetuphold_chk;
input integer clk_time;
input integer data_time;
begin
xsetuphold_chk = 0;
if(data_time > clk_time)
begin
// CR 424503
// if((data_time - clk_time) <= SIM_HOLD_D_CLK)
if((data_time - clk_time) < SIM_HOLD_D_CLK)
begin
// write_hold_message;
$display ("** Error %m \$hold(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_HOLD_D_CLK);
xsetuphold_chk = 2;
end
end
else
begin
// CR 424503
// if((clk_time - data_time) <= SIM_SETUP_D_CLK)
if((clk_time - data_time) < SIM_SETUP_D_CLK)
begin
// write_setup_message;
$display ("** Error %m \$setup(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_SETUP_D_CLK);
xsetuphold_chk = 1;
end
end
end
endfunction
tri0 GSR = glbl.GSR;
reg [1:0] sel;
reg [3:0] data_width_int;
reg bts_q1, bts_q2, bts_q3;
reg c23, c45, c67;
reg ce1r, ce2r;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg ice, memmux, q2pmux;
reg mux, mux1, muxc;
reg notifier;
reg clkdiv_int, clkdivmux;
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg num_ce_int;
reg qr1, qr2, qhc1, qhc2, qlc1, qlc2;
reg shiftn2_in, shiftn1_in;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg serdes_mode_int, data_rate_int, bitslip_enable_int;
reg d_delay, o_delay;
wire shiftout1_out, shiftout2_out;
wire [1:0] sel1;
wire [2:0] bsmux;
wire [3:0] selrnk3;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31,
delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35,
delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39,
delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43,
delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47,
delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51,
delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55,
delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59,
delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63;
wire bitslip_in;
wire ce1_in;
wire ce2_in;
wire clk_in;
wire clkdiv_in;
wire d_in;
wire dlyce_in;
wire dlyinc_in;
wire dlyrst_in;
wire gsr_in;
wire oclk_in;
wire rev_in;
wire sr_in;
wire shiftin1_in;
wire shiftin2_in;
buf b_o (O, o_out);
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_bitslip (bitslip_in, BITSLIP);
buf b_ce1 (ce1_in, CE1);
buf b_ce2 (ce2_in, CE2);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d (d_in, D);
buf b_dlyce (dlyce_in, DLYCE);
buf b_dlyinc (dlyinc_in, DLYINC);
buf b_dlyrst (dlyrst_in, DLYRST);
buf b_gsr (gsr_in, GSR);
buf b_oclk (oclk_in, OCLK);
buf b_rev (rev_in, REV);
buf b_sr (sr_in, SR);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
// WARNING !!!: This model may not work properly if the
// following parameters are changed.
// xilinx_internal_parameter on
parameter integer SIM_TAPDELAY_VALUE = 75;
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ffice = 300;
localparam mxice = 60;
// Delay parameter assignment
localparam ffbsc = 300;
localparam mxbsc = 60;
localparam mxinp1_my = 0;
// xilinx_internal_parameter off
initial begin
// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------
if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin
$display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration.");
$finish;
end
else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin
$display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground.");
$finish;
end
// ------------------------------------------------------------------------------------
if (IOBDELAY_VALUE < 0 || IOBDELAY_VALUE > 63) begin
$display("Attribute Syntax Error : The attribute IOBDELAY_VALUE on ISERDES instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IOBDELAY_VALUE);
$finish;
end
if (IOBDELAY_TYPE != "DEFAULT" && IOBDELAY_TYPE != "FIXED" && IOBDELAY_TYPE != "VARIABLE") begin
$display("Attribute Syntax Error : The attribute IOBDELAY_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IOBDELAY_TYPE);
$finish;
end
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
$finish;
end
endcase // case(DATA_RATE)
case (BITSLIP_ENABLE)
"FALSE" : bitslip_enable_int <= 1'b0;
"TRUE" : bitslip_enable_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE);
$finish;
end
endcase // case(BITSLIP_ENABLE)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDES instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
$finish;
end
endcase // case(NUM_CE)
end // initial begin
assign sel1 = {serdes_mode_int, data_rate_int};
assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00};
assign bsmux = {bitslip_enable_int, data_rate_int, muxc};
// GSR
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
if (IOBDELAY_TYPE == "DEFAULT")
assign delay_count = 0;
else
assign delay_count = IOBDELAY_VALUE;
assign bts_q3 = 1'b0;
assign bts_q2 = 1'b0;
assign bts_q1 = 1'b0;
assign clkdiv_int = 1'b0;
assign ce1r = 1'b0;
assign ce2r = 1'b0;
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
end
else if (gsr_in == 1'b0) begin
deassign delay_count;
deassign bts_q3;
deassign bts_q2;
deassign bts_q1;
deassign clkdiv_int;
deassign ce1r;
deassign ce2r;
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
end // if (gsr_in == 1'b0)
end // always @ (gsr_in)
// IDELAY
always @(posedge clkdiv_in) begin
if (IOBDELAY_TYPE == "VARIABLE") begin
if (dlyrst_in == 1'b1) begin
delay_count = IOBDELAY_VALUE;
end
else if (dlyrst_in == 1'b0 && dlyce_in == 1'b1) begin
if (dlyinc_in == 1'b1) begin
if (delay_count < 63)
delay_count = delay_count + 1;
else if (delay_count == 63)
delay_count = 0;
end
else if (dlyinc_in == 1'b0) begin
if (delay_count > 0)
delay_count = delay_count - 1;
else if (delay_count == 0)
delay_count = 63;
end
end
end // if (IOBDELAY_TYPE == "VARIABLE")
end // always @ (posedge clkdiv_in)
// delay chain
assign #DELAY_D delay_chain_0 = d_in;
assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0;
assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1;
assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2;
assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3;
assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4;
assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5;
assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6;
assign #SIM_TAPDELAY_VALUE delay_chain_8 = delay_chain_7;
assign #SIM_TAPDELAY_VALUE delay_chain_9 = delay_chain_8;
assign #SIM_TAPDELAY_VALUE delay_chain_10 = delay_chain_9;
assign #SIM_TAPDELAY_VALUE delay_chain_11 = delay_chain_10;
assign #SIM_TAPDELAY_VALUE delay_chain_12 = delay_chain_11;
assign #SIM_TAPDELAY_VALUE delay_chain_13 = delay_chain_12;
assign #SIM_TAPDELAY_VALUE delay_chain_14 = delay_chain_13;
assign #SIM_TAPDELAY_VALUE delay_chain_15 = delay_chain_14;
assign #SIM_TAPDELAY_VALUE delay_chain_16 = delay_chain_15;
assign #SIM_TAPDELAY_VALUE delay_chain_17 = delay_chain_16;
assign #SIM_TAPDELAY_VALUE delay_chain_18 = delay_chain_17;
assign #SIM_TAPDELAY_VALUE delay_chain_19 = delay_chain_18;
assign #SIM_TAPDELAY_VALUE delay_chain_20 = delay_chain_19;
assign #SIM_TAPDELAY_VALUE delay_chain_21 = delay_chain_20;
assign #SIM_TAPDELAY_VALUE delay_chain_22 = delay_chain_21;
assign #SIM_TAPDELAY_VALUE delay_chain_23 = delay_chain_22;
assign #SIM_TAPDELAY_VALUE delay_chain_24 = delay_chain_23;
assign #SIM_TAPDELAY_VALUE delay_chain_25 = delay_chain_24;
assign #SIM_TAPDELAY_VALUE delay_chain_26 = delay_chain_25;
assign #SIM_TAPDELAY_VALUE delay_chain_27 = delay_chain_26;
assign #SIM_TAPDELAY_VALUE delay_chain_28 = delay_chain_27;
assign #SIM_TAPDELAY_VALUE delay_chain_29 = delay_chain_28;
assign #SIM_TAPDELAY_VALUE delay_chain_30 = delay_chain_29;
assign #SIM_TAPDELAY_VALUE delay_chain_31 = delay_chain_30;
assign #SIM_TAPDELAY_VALUE delay_chain_32 = delay_chain_31;
assign #SIM_TAPDELAY_VALUE delay_chain_33 = delay_chain_32;
assign #SIM_TAPDELAY_VALUE delay_chain_34 = delay_chain_33;
assign #SIM_TAPDELAY_VALUE delay_chain_35 = delay_chain_34;
assign #SIM_TAPDELAY_VALUE delay_chain_36 = delay_chain_35;
assign #SIM_TAPDELAY_VALUE delay_chain_37 = delay_chain_36;
assign #SIM_TAPDELAY_VALUE delay_chain_38 = delay_chain_37;
assign #SIM_TAPDELAY_VALUE delay_chain_39 = delay_chain_38;
assign #SIM_TAPDELAY_VALUE delay_chain_40 = delay_chain_39;
assign #SIM_TAPDELAY_VALUE delay_chain_41 = delay_chain_40;
assign #SIM_TAPDELAY_VALUE delay_chain_42 = delay_chain_41;
assign #SIM_TAPDELAY_VALUE delay_chain_43 = delay_chain_42;
assign #SIM_TAPDELAY_VALUE delay_chain_44 = delay_chain_43;
assign #SIM_TAPDELAY_VALUE delay_chain_45 = delay_chain_44;
assign #SIM_TAPDELAY_VALUE delay_chain_46 = delay_chain_45;
assign #SIM_TAPDELAY_VALUE delay_chain_47 = delay_chain_46;
assign #SIM_TAPDELAY_VALUE delay_chain_48 = delay_chain_47;
assign #SIM_TAPDELAY_VALUE delay_chain_49 = delay_chain_48;
assign #SIM_TAPDELAY_VALUE delay_chain_50 = delay_chain_49;
assign #SIM_TAPDELAY_VALUE delay_chain_51 = delay_chain_50;
assign #SIM_TAPDELAY_VALUE delay_chain_52 = delay_chain_51;
assign #SIM_TAPDELAY_VALUE delay_chain_53 = delay_chain_52;
assign #SIM_TAPDELAY_VALUE delay_chain_54 = delay_chain_53;
assign #SIM_TAPDELAY_VALUE delay_chain_55 = delay_chain_54;
assign #SIM_TAPDELAY_VALUE delay_chain_56 = delay_chain_55;
assign #SIM_TAPDELAY_VALUE delay_chain_57 = delay_chain_56;
assign #SIM_TAPDELAY_VALUE delay_chain_58 = delay_chain_57;
assign #SIM_TAPDELAY_VALUE delay_chain_59 = delay_chain_58;
assign #SIM_TAPDELAY_VALUE delay_chain_60 = delay_chain_59;
assign #SIM_TAPDELAY_VALUE delay_chain_61 = delay_chain_60;
assign #SIM_TAPDELAY_VALUE delay_chain_62 = delay_chain_61;
assign #SIM_TAPDELAY_VALUE delay_chain_63 = delay_chain_62;
// assign delay
always @(delay_count_int) begin
case (delay_count_int)
0: assign d_delay = delay_chain_0;
1: assign d_delay = delay_chain_1;
2: assign d_delay = delay_chain_2;
3: assign d_delay = delay_chain_3;
4: assign d_delay = delay_chain_4;
5: assign d_delay = delay_chain_5;
6: assign d_delay = delay_chain_6;
7: assign d_delay = delay_chain_7;
8: assign d_delay = delay_chain_8;
9: assign d_delay = delay_chain_9;
10: assign d_delay = delay_chain_10;
11: assign d_delay = delay_chain_11;
12: assign d_delay = delay_chain_12;
13: assign d_delay = delay_chain_13;
14: assign d_delay = delay_chain_14;
15: assign d_delay = delay_chain_15;
16: assign d_delay = delay_chain_16;
17: assign d_delay = delay_chain_17;
18: assign d_delay = delay_chain_18;
19: assign d_delay = delay_chain_19;
20: assign d_delay = delay_chain_20;
21: assign d_delay = delay_chain_21;
22: assign d_delay = delay_chain_22;
23: assign d_delay = delay_chain_23;
24: assign d_delay = delay_chain_24;
25: assign d_delay = delay_chain_25;
26: assign d_delay = delay_chain_26;
27: assign d_delay = delay_chain_27;
28: assign d_delay = delay_chain_28;
29: assign d_delay = delay_chain_29;
30: assign d_delay = delay_chain_30;
31: assign d_delay = delay_chain_31;
32: assign d_delay = delay_chain_32;
33: assign d_delay = delay_chain_33;
34: assign d_delay = delay_chain_34;
35: assign d_delay = delay_chain_35;
36: assign d_delay = delay_chain_36;
37: assign d_delay = delay_chain_37;
38: assign d_delay = delay_chain_38;
39: assign d_delay = delay_chain_39;
40: assign d_delay = delay_chain_40;
41: assign d_delay = delay_chain_41;
42: assign d_delay = delay_chain_42;
43: assign d_delay = delay_chain_43;
44: assign d_delay = delay_chain_44;
45: assign d_delay = delay_chain_45;
46: assign d_delay = delay_chain_46;
47: assign d_delay = delay_chain_47;
48: assign d_delay = delay_chain_48;
49: assign d_delay = delay_chain_49;
50: assign d_delay = delay_chain_50;
51: assign d_delay = delay_chain_51;
52: assign d_delay = delay_chain_52;
53: assign d_delay = delay_chain_53;
54: assign d_delay = delay_chain_54;
55: assign d_delay = delay_chain_55;
56: assign d_delay = delay_chain_56;
57: assign d_delay = delay_chain_57;
58: assign d_delay = delay_chain_58;
59: assign d_delay = delay_chain_59;
60: assign d_delay = delay_chain_60;
61: assign d_delay = delay_chain_61;
62: assign d_delay = delay_chain_62;
63: assign d_delay = delay_chain_63;
default:
assign d_delay = delay_chain_0;
endcase
end // always @ (delay_count_int)
// to workaround the glitches generated by mux of assign delay above
always @(delay_count)
delay_count_int <= #0 delay_count;
// Mux to O and o_delay
always @(d_in or d_delay) begin
case (IOBDELAY)
"NONE" : begin
o_delay <= d_in;
o_out <= d_in;
end
"IBUF" : begin
o_delay <= d_in;
o_out <= d_delay;
end
"IFD" : begin
o_delay <= d_delay;
o_out <= d_in;
end
"BOTH" : begin
o_delay <= d_delay;
o_out <= d_delay;
end
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDES instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
end // always @ (d_in or d_delay)
// 1st rank of registers
// Asynchronous Operation
always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
// 1st flop in rank 1 that is full featured
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1))
q1rnk1 <= # ffinp SRVAL_Q1;
else if (rev_in == 1'b1)
q1rnk1 <= # ffinp !SRVAL_Q1;
else if (ice == 1'b1)
q1rnk1 <= # ffinp o_delay;
end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
always @(posedge clk_in or posedge sr_in) begin
// rest of flops which are not full featured and don't have clock options
if (sr_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clk_in or sr_in)
// 2nd flop in rank 1
// Asynchronous Operation
always @(negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1))
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (rev_in == 1'b1)
q2nrnk1 <= # ffinp !SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp o_delay;
end // always @ (negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 4th flop in rank 1 operating on the posedge for networking
// Asynchronous Operation
always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1))
q2prnk1 <= # ffinp SRVAL_Q4;
else if (rev_in == 1'b1)
q2prnk1 <= # ffinp !SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 3rd flop in 2nd rank which is full featured and has
// a choice of being clocked by oclk or clk
// Asynchronous Operation
always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1))
q1prnk1 <= # ffinp SRVAL_Q3;
else if (rev_in == 1'b1)
q1prnk1 <= # ffinp !SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @(posedge memmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge memmux or posedge sr_in)
//////////////////////////////////////////
// Mux elements for the 1st rank
////////////////////////////////////////
// Optional inverter for q2p (4th flop in rank1)
always @ (memmux) begin
case (INTERFACE_TYPE)
"MEMORY" : q2pmux <= # mxinp1 !memmux;
"NETWORKING" : q2pmux <= # mxinp1 memmux;
default: q2pmux <= # mxinp1 !memmux;
endcase
end // always @ (memmux)
// 4 clock muxs in first rank
always @(clk_in or oclk_in) begin
case (INTERFACE_TYPE)
"MEMORY" : memmux <= # mxinp1 oclk_in;
"NETWORKING" : memmux <= # mxinp1 clk_in;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE);
$finish;
end
endcase // case(INTERFACE_TYPE)
end // always @(clk_in or oclk_in)
// data input mux for q3, q4, q5 and q6
always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in;
default : dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2)
always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1;
default : dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1)
always @(data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1;
default : dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(DATA_RATE)
end
always @(data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1;
default : dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(DATA_RATE)
end
// 2nd rank of registers
// clkdivmux to pass clkdiv_int or CLKDIV to rank 2
always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin
case (bitslip_enable_int)
1'b0 : clkdivmux <= # mxinp1 clkdiv_in;
1'b1 : clkdivmux <= # mxinp1 clkdiv_int;
default : clkdivmux <= # mxinp1 clkdiv_in;
endcase // case(BITSLIP_ENABLE)
end // always @(clkdiv_int or clkdiv_in)
// Asynchronous Operation
always @(posedge clkdivmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q2rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q2rnk2 <= # ffinp dataq2rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux or sr_in)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1;
3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1;
default : dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @(bsmux or q1prnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1;
3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1;
default : dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1prnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1;
3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1;
default : dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1;
3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1;
default : dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1;
3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1;
default : dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1;
3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1;
default : dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1)
// 3rd rank of registers
// Asynchronous Operation
always @(posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Outputs
assign shiftout2_out = q5rnk1;
assign shiftout1_out = q6rnk1;
always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00 : q1_out <= # mxinp1_my q1prnk1;
4'b0X01 : q1_out <= # mxinp1_my q1rnk1;
4'b0X10 : q1_out <= # mxinp1_my q1rnk1;
4'b10XX : q1_out <= # mxinp1_my q1rnk2;
4'b11XX : q1_out <= # mxinp1_my q1rnk3;
default : q1_out <= # mxinp1_my q1rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3)
always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00 : q2_out <= # mxinp1_my q2prnk1;
4'b0X01 : q2_out <= # mxinp1_my q2prnk1;
4'b0X10 : q2_out <= # mxinp1_my q2nrnk1;
4'b10XX : q2_out <= # mxinp1_my q2rnk2;
4'b11XX : q2_out <= # mxinp1_my q2rnk3;
default : q2_out <= # mxinp1_my q2rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3)
always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin
case (bitslip_enable_int)
1'b0 : q3_out <= # mxinp1_my q3rnk2;
1'b1 : q3_out <= # mxinp1_my q3rnk3;
endcase // case(BITSLIP_ENABLE)
end // always @ (q3rnk2 or q3rnk3)
always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin
casex (bitslip_enable_int)
1'b0 : q4_out <= # mxinp1_my q4rnk2;
1'b1 : q4_out <= # mxinp1_my q4rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q4rnk2 or q4rnk3)
always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin
casex (bitslip_enable_int)
1'b0 : q5_out <= # mxinp1_my q5rnk2;
1'b1 : q5_out <= # mxinp1_my q5rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q5rnk2 or q5rnk3)
always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin
casex (bitslip_enable_int)
1'b0 : q6_out <= # mxinp1_my q6rnk2;
1'b1 : q6_out <= # mxinp1_my q6rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q6rnk2 or q6rnk3)
// Set value of counter in bitslip controller
always @(data_rate_int or data_width_int) begin
casex ({data_rate_int, data_width_int})
5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default : begin
$display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
$finish;
end
endcase
end // always @ (data_rate_int or data_width_int)
///////////////////////////////////////////
// Bit slip controler
///////////////////////////////////////////
// Divide by 2 - 8 counter
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b0) begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (posedge qr2 or negedge clk_in)
// Synchronous Operation
always @ (negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b1) begin
clkdiv_int <= # ffbsc clkdiv_int;
bts_q1 <= # ffbsc bts_q1;
bts_q2 <= # ffbsc bts_q2;
bts_q3 <= # ffbsc bts_q3;
end
else begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (negedge clk_in)
// 4:1 selector mux and divider selections
always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin
case (sel)
2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2));
2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3));
2'b11 : mux <= # mxbsc !bts_q3;
default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
endcase
end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3)
// Bitslip control logic
// Low speed control flop
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv_in) begin
if (qr1 == 1'b1) begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (bitslip_in == 1'b0) begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip_in & mux1);
end
end // always @ (posedge qr1 or posedge clkdiv_in)
// Mux to select between sdr "1" and ddr "0"
always @ (data_rate_int or qlc1) begin
case (data_rate_int)
1'b0 : mux1 <= # mxbsc qlc1;
1'b1 : mux1 <= # mxbsc 1'b1;
endcase
end
// High speed control flop
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end // always @ (posedge qr2 or negedge clk_in)
// Mux that drives control line of mux in front
// of 2nd rank of flops
always @ (data_rate_int or mux1) begin
case (data_rate_int)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
// Asynchronous set flops
// Low speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qr1 <= # ffbsc 1'b1;
else
qr1 <= # ffbsc 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or negedge clk_in) begin
if (sr_in == 1'b1)
qr2 <= # ffbsc 1'b1;
else
qr2 <= # ffbsc qr1;
end // always @ (posedge sr_in or negedge clk_in)
/////////////////////////////////////////////
// ICE
///////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else begin
ce1r <= # ffice ce1_in;
ce2r <= # ffice ce2_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Output mux ice
always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin
case ({num_ce_int, clkdiv_in})
2'b00 : ice <= # mxice ce1_in;
2'b01 : ice <= # mxice ce1_in;
// 426606
2'b10 : ice <= # mxice ce2r;
2'b11 : ice <= # mxice ce1r;
default : ice <= # mxice ce1_in;
endcase
end
//*** Timing Checks Start here
//-------------------------------------------------------------------
//
//-------------------------------------------------------------------
always @(posedge CLK) begin
clk_change_time = $time;
return_code = xsetuphold_chk(clk_change_time, data_change_time);
end
always @(d_delay) begin
data_change_time = $time;
return_code = xsetuphold_chk(clk_change_time, data_change_time);
end
`ifndef XIL_TIMING
assign bitslip_in = BITSLIP;
assign clk_in = CLK;
assign ce1_in = CE1;
assign ce2_in = CE2;
assign clkdiv_in = CLKDIV;
assign d_in = D;
assign dlyinc_in = DLYINC;
assign dlyce_in = DLYCE;
assign dlyrst_in = DLYRST;
`endif
specify
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(D => O) = (0:0:0, 0:0:0);
(SR => Q1) = (0:0:0, 0:0:0);
(SR => Q2) = (0:0:0, 0:0:0);
(SR => Q3) = (0:0:0, 0:0:0);
(SR => Q4) = (0:0:0, 0:0:0);
(SR => Q5) = (0:0:0, 0:0:0);
(SR => Q6) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
$setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
$setuphold (posedge CLKDIV, posedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in);
$setuphold (posedge CLKDIV, negedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in);
$setuphold (posedge CLKDIV, posedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in);
$setuphold (posedge CLKDIV, negedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in);
$setuphold (posedge CLKDIV, posedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in);
$setuphold (posedge CLKDIV, negedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge OCLK, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge OCLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge REV, posedge OCLK, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge OCLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge OCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // ISERDES
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ISERDESE1.v 0000664 0000000 0000000 00000146155 12327044266 0022722 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2007 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Source Synchronous Input Deserializer for Virtex6
// /___/ /\ Filename : ISERDESE1.v
// \ \ / \ Timestamp : Tue May 26 15:42:08 PDT 2009
// \___\/\___\
//
// Revision:
// 05/26/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDESE1 (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB, RST, SHIFTIN1, SHIFTIN2);
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter DYN_CLKDIV_INV_EN = "FALSE";
parameter DYN_CLK_INV_EN = "FALSE";
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter integer NUM_CE = 2;
parameter IOBDELAY = "NONE";
parameter OFB_USED = "FALSE";
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// O: o output
// Q1: q1 output
// Q2: q2 output
// Q3: q3 output
// Q4: q4 output
// Q5: q5 output
// Q6: q6 output
// SHIFTOUT1: carry out data
// SHIFTOUT2: carry out data
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
// D: Input from pad
// CE1: main clock enable input
// CE2: 2nd clock enable input for serdes
// BITSLIP: Manage bitslip controller
// SHIFTIN1: Carry in data
// SHIFTIN2: Carry in data
// CLK: High speed clock or strobe
// CLKB: High speed inverted clock or strobe
// Primary use is QDR
// CLKDIV: Divided clock from H clock row or OCLKDIV for memory applications
// OCLK: High speed output clock
// OCLKB: High speed inverted output clock
// Primary use is oversampling
// RST: Set/Reset control.
// CLKDIV: Low speed clock to drive counter for delay element
//
// DYNCLKSEL: Dynamically change polarity of CLK
// DYNCLKDIVSEL: Dynamically change polarity of CLKDIV
// DYNOCLKSEL: Dynamically change polarity of OCLK
// OFB: Feedback input from the OQ portion of the output
//
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input D;
input DDLY;
input DYNCLKDIVSEL;
input DYNCLKSEL;
input OCLK;
input OFB;
input RST;
input SHIFTIN1;
input SHIFTIN2;
//
wire [1:0] SRTYPE, DDR_CLK_EDGE;
wire SERDES;
wire TFB;
// CR 541284 wire OVERSAMPLE, RANK12_DLY, RANK23_DLY;
wire RANK12_DLY, RANK23_DLY;
wire D_EMU;
assign SRTYPE = 2'b00;
assign SERDES = 1'b1;
assign DDR_CLK_EDGE = 2'b11;
assign TFB = 1'b0;
// CR 541284 assign OVERSAMPLE = 1'b0;
reg OVERSAMPLE = 1'b0;
assign RANK12_DLY = 1'b0;
assign RANK23_DLY = 1'b0;
assign D_EMU = 1'b0;
// Output signals
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
wire shiftout1_out, shiftout2_out;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg memmux, q2pmux;
reg clkmux1, clkmux2, clkmux3, clkmux4;
reg clkoimux, oclkoimux, clkdivoimux;
reg clkboimux, oclkboimux = 0, clkdivboimux;
reg clkdivmux1, clkdivmux2;
reg ddr3clkmux;
reg rank3clkmux;
reg c23, c45, c67;
reg [1:0] sel;
wire [3:0] selrnk3;
wire [4:0] cntr;
wire [1:0] sel1;
wire [3:0] bsmux;
wire ice;
wire muxc;
wire clkdiv_int;
wire [1:0] clkdivsel;
wire bitslip_en;
wire int_typ;
wire [1:0] os_en;
wire [2:0] rank2_cksel;
reg data_in;
reg o_out_pre_fb = 0, o_delay_pre_fb = 0;
reg data_rate_int;
reg [3:0] data_width_int;
reg dyn_clkdiv_inv_int, dyn_clk_inv_int, dyn_oclk_inv_int;
reg ofb_used_int, num_ce_int, serdes_mode_int;
reg [1:0] interface_type_int;
reg notifier;
// Other signals
tri0 GSR = glbl.GSR;
buf b_o (O, o_out);
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
wire bitslip_in, ce1_in, ce2_in, clk_in, clkb_in, clkdiv_in,
d_in, ddly_in, dynclkdivsel_in, dynclksel_in, dynoclksel_in, oclk_in,
oclkb_in, ofb_in, rst_in, shiftin1_in, shiftin2_in;
`ifndef XIL_TIMING
assign bitslip_in = BITSLIP;
assign ce1_in = CE1;
assign ce2_in = CE2;
assign clk_in = CLK;
assign clkb_in = CLKB;
assign clkdiv_in = CLKDIV;
assign d_in = D;
assign ddly_in = DDLY;
assign dynclkdivsel_in = DYNCLKDIVSEL;
assign dynclksel_in = DYNCLKSEL;
// CR 518368
// assign dynoclksel_in = DYNOCLKSEL;
assign oclk_in = OCLK;
// CR 507371
// assign oclkb_in = OCLKB;
assign ofb_in = OFB;
assign rst_in = RST;
assign shiftin1_in = SHIFTIN1;
assign shiftin2_in = SHIFTIN2;
`endif // `ifndef XIL_TIMING
task INTERFACE_TYPE_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10\n");
$display("MEMORY SDR None\n");
$display("MEMORY DDR 4\n");
end
endtask // INTERFACE_TYPE_msg
// CR 541284
task OVERSAMPLE_DDR_SDR_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("OVERSAMPLE SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("OVERSAMPLE DDR 4, 6, 8, 10\n");
end
endtask // OVERSAMPLE_DDR_SDR_msg
initial begin
//-------------------------------------------------
//----- DATA_RATE check
//-------------------------------------------------
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
$finish;
end
endcase // case(DATA_RATE)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DYN_CLKDIV_INV_EN check
//-------------------------------------------------
case (DYN_CLKDIV_INV_EN)
"FALSE" : dyn_clkdiv_inv_int <= 1'b0;
"TRUE" : dyn_clkdiv_inv_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN);
$finish;
end
endcase // case(DYN_CLKDIV_INV_EN)
//-------------------------------------------------
//----- DYN_CLK_INV_EN check
//-------------------------------------------------
case (DYN_CLK_INV_EN)
"FALSE" : dyn_clk_inv_int <= 1'b0;
"TRUE" : dyn_clk_inv_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN);
$finish;
end
endcase // case(DYN_CLK_INV_EN)
//-------------------------------------------------
//----- OFB_USED check
//-------------------------------------------------
case (OFB_USED)
"FALSE" : ofb_used_int <= 1'b0;
"TRUE" : ofb_used_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED);
$finish;
end
endcase // case(OFB_USED)
//-------------------------------------------------
//----- NUM_CE check
//-------------------------------------------------
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
$finish;
end
endcase // case(NUM_CE)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"MEMORY" : begin
interface_type_int <= 2'b00;
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : INTERFACE_TYPE_msg;
endcase // DATA_RATE
end
"NETWORKING" : begin
interface_type_int <= 2'b01;
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
"MEMORY_QDR" :
interface_type_int <= 2'b10;
"MEMORY_DDR3" :
interface_type_int <= 2'b11;
// CR 541284
"OVERSAMPLE" : begin
OVERSAMPLE <= 1'b1;
interface_type_int <= 2'b01;
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : OVERSAMPLE_DDR_SDR_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10 : ;
default : OVERSAMPLE_DDR_SDR_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE);
$finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
//-------------------------------------------------
end // initial begin
//-------------------------------------------------
assign int_typ = interface_type_int[1] | interface_type_int[0];
assign bitslip_en = interface_type_int[0];
// CR 541284
assign os_en = {int_typ, OVERSAMPLE}; // {int_typ, OVERSAMPLE};
assign sel1 = {serdes_mode_int, data_rate_int}; // {SERDES_MODE,DATA_RATE};
// CR 541284
assign rank2_cksel = {interface_type_int, OVERSAMPLE}; // {interface_type_int, OVERSAMPLE};
assign selrnk3 = {1'b1, bitslip_en, 2'b11}; // {SERDES,bitslip_en, DDR_CLK_EDGE};
// CR 541284
assign bsmux = {bitslip_en, data_rate_int, muxc, OVERSAMPLE}; // {bitslip_en,DATA_RATE,muxc, OVERSAMPLE};
assign cntr = {data_rate_int, data_width_int}; // {DATA_RATE,DATA_WIDTH};
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ht0 = 800;
localparam fftco = 300;
localparam mxdly = 60;
localparam cnstdly = 80;
// GSR
always @(GSR) begin
if (GSR == 1'b1) begin
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
assign ddr3clkmux = 1'b1;
end
else if (GSR == 1'b0) begin
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
deassign ddr3clkmux;
end // if (GSR == 1'b0)
end // always @ (GSR)
//-------------------------------------------------
// Input to ISERDES
//-------------------------------------------------
always @(d_in or ddly_in) begin
case (IOBDELAY)
"NONE" : begin
o_out_pre_fb <= d_in;
o_delay_pre_fb <= d_in;
end
"IBUF" : begin
o_out_pre_fb <= ddly_in;
o_delay_pre_fb <= d_in;
end
"IFD" : begin
o_out_pre_fb <= d_in;
o_delay_pre_fb <= ddly_in;
end
"BOTH" : begin
o_out_pre_fb <= ddly_in;
o_delay_pre_fb <= ddly_in;
end
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE1 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
end // always @ (d_in or ddly_in)
generate
case (OFB_USED)
"TRUE" : always @(ofb_in)
begin
o_out <= ofb_in;
data_in <= ofb_in;
end
"FALSE" : begin
always @(o_out_pre_fb) o_out <= o_out_pre_fb;
always @(o_delay_pre_fb) data_in <= o_delay_pre_fb;
end
endcase
endgenerate
//------------------------------------------------------
// High Speed Clock Generation and Polarity Control
//------------------------------------------------------
// Optional inverter for clk
generate
case (DYN_CLK_INV_EN)
"FALSE" : always @(clk_in) clkoimux <= clk_in;
"TRUE" :
// CR 523086
always @ (dynclksel_in or clk_in or clkb_in) begin
case (dynclksel_in)
1'b0: clkoimux <= clkb_in;
1'b1: clkoimux <= clk_in;
endcase
end
endcase
endgenerate
// Optional inverter for clkb
generate
case (DYN_CLK_INV_EN)
"FALSE" : always @(clkb_in) clkboimux <= clkb_in;
"TRUE" :
// CR 523086
always @ (dynclksel_in or clkb_in or clk_in) begin
case (dynclksel_in)
1'b0: clkboimux <= clk_in;
1'b1: clkboimux <= clkb_in;
endcase
end
endcase
endgenerate
// CR 518368
// Optional inverter for oclk
/*
generate
case (DYN_OCLK_INV_EN)
"FALSE" : always @(oclk_in) oclkoimux <= oclk_in;
"TRUE" :
always @ (dynoclksel_in or oclk_in) begin
case (dynoclksel_in)
1'b0: oclkoimux <= oclk_in;
1'b1: oclkoimux <= ~oclk_in;
endcase
end
endcase
endgenerate
*/
always @(oclk_in) oclkoimux <= oclk_in;
//CR 507371
// Optional inverter for oclkb
/*
generate
case (DYN_OCLK_INV_EN)
"FALSE" : always @(oclkb_in) oclkboimux <= oclkb_in;
"TRUE" :
always @ (dynoclksel_in or oclkb_in) begin
case (dynoclksel_in)
1'b0: oclkboimux <= oclkb_in;
1'b1: oclkboimux <= ~oclkb_in;
endcase
end
endcase
endgenerate
*/
// Optional inverter for clkdiv
generate
case (DYN_CLKDIV_INV_EN)
"FALSE" : always @(clkdiv_in) clkdivoimux <= clkdiv_in;
"TRUE" :
always @ (dynclkdivsel_in or clkdiv_in) begin
case (dynclkdivsel_in)
1'b0: clkdivoimux <= clkdiv_in;
1'b1: clkdivoimux <= ~clkdiv_in;
endcase
end
endcase
endgenerate
// clkmux for 2nd flop in rank1
generate
case (INTERFACE_TYPE)
"MEMORY" : always @(clkboimux) clkmux2 <= clkboimux;
"NETWORKING" : always @(clkboimux) clkmux2 <= clkboimux;
"MEMORY_QDR" : always @(clkboimux) clkmux2 <= clkboimux;
"MEMORY_DDR3" : always @(clkboimux) clkmux2 <= clkboimux;
endcase
endgenerate
// clkmux for 3rd flop in rank1
always @ (os_en or oclkoimux or clkoimux) begin
case (os_en)
2'b00: clkmux3 <= oclkoimux;
2'b01: clkmux3 <= oclkoimux;
2'b10: clkmux3 <= clkoimux;
2'b11: clkmux3 <= oclkoimux;
endcase
end
//clkmux for 4th flop in rank1
always @ (os_en or oclkoimux or clkoimux or oclkboimux) begin
case(os_en)
2'b00: clkmux4 <= ~oclkoimux;
2'b01: clkmux4 <= ~oclkoimux;
2'b10: clkmux4 <= clkoimux;
2'b11: clkmux4 <= oclkboimux;
default: clkmux4 <= ~oclkoimux;
endcase
end
// Rest of clock muxs in first rank
always @ (int_typ or oclkoimux or clkoimux) begin
case (int_typ)
1'b0: memmux <= # mxinp1 oclkoimux;
1'b1: memmux <= # mxinp1 clkoimux;
default: memmux <= # mxinp1 oclkoimux;
endcase
end
//-------------------------------------------------
// 1st rank of registers -- Synchronous Operation
//-------------------------------------------------
// Uses the positive edge of CLK
// This includes the 1st, 6th, 7th and 8th flops in rank 1
// These flops are designated as q1rnk1, q5rnk1, q6rnk1
// and q6prnk1. q1rnk1 is full featured.
// q5rnk1, q6rnk1 and q6prnk1 are not.
always @ (posedge clkoimux) begin
if(rst_in == 1'b1) begin
q1rnk1 <= # ffinp SRVAL_Q1;
end
else if (ice == 1'b1) begin
q1rnk1 <= # ffinp data_in;
end
if(rst_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clkoimux)
// 2nd flop in rank 1, designated q2nrnk1, that is full featured
// and operates only on the negative edge of CLK or positive
// edge of CLKB
always @ (posedge clkmux2) begin
if(rst_in == 1'b1)
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp data_in;
end // always @ (posedge clkmux2)
// 3rd, 4th, 5th and 6th flops in rank1
// The 3rd and 4th flops are full featured while
// The 5th and 6th flops only have reset. The flops are
// designated as q1prnk1, q2prnk1, q3rnk1 and q4rnk1.
// These 4 flops can be driven from CLK or OCLK. This
// function is implemented by the clk mux called
// "memmux". Flops q1prnk1, q3rnk1 and q4rnk1 are
// driven of the positive edge of memmux. Flop q2prnk1
// is further driven by the optional inverter mux named
// "q2pmux" that allows it to be driven off either the
// positive or negative edge of memmux.
//
always @ (posedge clkmux3) begin
if(rst_in == 1'b1)
q1prnk1 <= # ffinp SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge clkmux3)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @ (posedge memmux) begin
if(rst_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge clkmux2)
// 4th flop in rank 1 (q2prnk1). This is a full featured flop
// that for memory is clocked on the negative edge of OCLK
// and for networking is clocked on the positive edge of CLK
always @ (posedge clkmux4) begin
if(rst_in == 1'b1)
q2prnk1 <= # ffinp SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge clkmux4)
//-------------------------------------------------
// Mux elements for the 1st rank
//-------------------------------------------------
// data input mux for q3, q4, q5 and q6
always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00: dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01: dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10: dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11: dataq3rnk1 <= # mxinp1 shiftin1_in;
default: dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in)
always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00: dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01: dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10: dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11: dataq4rnk1 <= # mxinp1 q3rnk1;
default: dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in)
always @ (data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0: dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1: dataq5rnk1 <= # mxinp1 q4rnk1;
default: dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(data_rate_int)
end // always @ (data_rate_int or q3rnk1 or q4rnk1)
always @ (data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0: dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1: dataq6rnk1 <= # mxinp1 q5rnk1;
default: dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(data_rate_int)
end // always @ (data_rate_int or q4rnk1 or q5rnk1)
//-------------------------------------------------
// 2nd rank of registers -- Synchronous Operation
//-------------------------------------------------
// DDR3 Divide By 2 CKT
always @ (negedge clkoimux) begin
if(rst_in)
ddr3clkmux <= 1'b0;
else if (INTERFACE_TYPE == "MEMORY_DDR3")
ddr3clkmux <= ~ddr3clkmux;
else
ddr3clkmux <= ddr3clkmux;
end // always @ (negedge clkoimux)
// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2
always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr) begin
case (rank2_cksel)
3'b000: clkdivmux1 <= # mxinp1 clkdivoimux;
3'b010: begin
case (cntr)
5'b00100: clkdivmux1 <= # mxinp1 ~clkdiv_int;
5'b10010: clkdivmux1 <= # mxinp1 ~clkdiv_int;
default: clkdivmux1 <= # mxinp1 clkdiv_int;
endcase
end
3'b100: clkdivmux1 <= # mxinp1 clkdivoimux;
3'b110: #1 clkdivmux1 <= # mxinp1 ddr3clkmux;
3'b011: clkdivmux1 <= # mxinp1 clkoimux;
// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time);
endcase // case (rank2_cksel)
end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr)
// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2
always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or oclkoimux or cntr) begin
case (rank2_cksel)
3'b000: clkdivmux2 <= # mxinp1 clkdivoimux;
3'b010: begin
case (cntr)
5'b00100: clkdivmux2 <= # mxinp1 ~clkdiv_int;
5'b10010: clkdivmux2 <= # mxinp1 ~clkdiv_int;
default: clkdivmux2 <= # mxinp1 clkdiv_int;
endcase
end
3'b100: clkdivmux2 <= # mxinp1 clkdivoimux;
3'b110: #1 clkdivmux2 <= #mxinp1 ddr3clkmux;
3'b011: clkdivmux2 <= # mxinp1 oclkoimux;
// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time);
endcase // case (rank2_cksel)
end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux)
// Synchronous Operation
always @ (posedge clkdivmux1) begin
if(rst_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux1)
always @ (posedge clkdivmux2) begin
if(rst_in == 1'b1) begin
q2rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
end
else begin
q2rnk2 <= # ffinp dataq2rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
end
end // always @ (posedge clkdivmux2)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
4'b00X0: dataq1rnk2 <= # mxinp2 q2prnk1;
4'b1000: dataq1rnk2 <= # mxinp2 q2prnk1;
4'b1010: dataq1rnk2 <= # mxinp2 q1prnk1;
4'bX1X0: dataq1rnk2 <= # mxinp2 q1rnk1;
4'bXXX1: dataq1rnk2 <= # mxinp2 q1rnk1;
default: dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1) begin
casex (bsmux)
4'b00X0: dataq2rnk2 <= # mxinp2 q1prnk1;
4'b1000: dataq2rnk2 <= # mxinp2 q1prnk1;
4'b1010: dataq2rnk2 <= # mxinp2 q4rnk1;
4'bX1X0: dataq2rnk2 <= # mxinp2 q1prnk1;
4'bXXX0: dataq2rnk2 <= # mxinp2 q2nrnk1;
default: dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1)
always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1) begin
casex (bsmux)
4'b00X0: dataq3rnk2 <= # mxinp2 q4rnk1;
4'b1000: dataq3rnk2 <= # mxinp2 q4rnk1;
4'b1010: dataq3rnk2 <= # mxinp2 q3rnk1;
4'bX1X0: dataq3rnk2 <= # mxinp2 q3rnk1;
4'bXXX1: dataq3rnk2 <= # mxinp2 q1prnk1;
default: dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1)
always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1) begin
casex (bsmux)
4'b00X0: dataq4rnk2 <= # mxinp2 q3rnk1;
4'b1000: dataq4rnk2 <= # mxinp2 q3rnk1;
4'b1010: dataq4rnk2 <= # mxinp2 q6rnk1;
4'bX1X0: dataq4rnk2 <= # mxinp2 q4rnk1;
4'bXXX1: dataq4rnk2 <= # mxinp2 q2prnk1;
default: dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1)
always @ (bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
4'b00X0: dataq5rnk2 <= # mxinp2 q6rnk1;
4'b1000: dataq5rnk2 <= # mxinp2 q6rnk1;
4'b1010: dataq5rnk2 <= # mxinp2 q5rnk1;
4'bX1X0: dataq5rnk2 <= # mxinp2 q5rnk1;
default: dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q5rnk1 or q6rnk1)
always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
4'b00X0: dataq6rnk2 <= # mxinp2 q5rnk1;
4'b1000: dataq6rnk2 <= # mxinp2 q5rnk1;
4'b1010: dataq6rnk2 <= # mxinp2 q6prnk1;
4'bX1X0: dataq6rnk2 <= # mxinp2 q6rnk1;
default: dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex (bsmux)
end // always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1)
//-------------------------------------------------
// 3rd rank of registers -- Synchronous Operation
//-------------------------------------------------
// clkdivmuxs to pass CLK or CLKDIV to rank 3
always @ (OVERSAMPLE or clkdivoimux or clkoimux) begin
case (OVERSAMPLE)
1'b0: rank3clkmux <= # mxinp1 clkdivoimux;
1'b1: rank3clkmux <= # mxinp1 clkoimux;
default: rank3clkmux <= # mxinp1 clkdivoimux;
endcase // case (OVERSAMPLE)
end // always @ (OVERSAMPLE or clkdivoimux or clkoimux)
// Synchronous Operation
always @ (posedge rank3clkmux) begin
if(rst_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge rank3clkmux)
//-------------------------------------------------
// Outputs
//-------------------------------------------------
assign shiftout1_out = q6rnk1;
assign shiftout2_out = q5rnk1;
always @ (selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00: q1_out <= # mxinp1 q1prnk1;
4'b0X01: q1_out <= # mxinp1 q1rnk1;
4'b0X10: q1_out <= # mxinp1 q1rnk1;
4'b10XX: q1_out <= # mxinp1 q1rnk2;
4'b11XX: q1_out <= # mxinp1 q1rnk3;
default: q1_out <= # mxinp1 q1rnk2;
endcase
end
always @ (selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00: q2_out <= # mxinp1 q2prnk1;
4'b0X01: q2_out <= # mxinp1 q2prnk1;
4'b0X10: q2_out <= # mxinp1 q2nrnk1;
4'b10XX: q2_out <= # mxinp1 q2rnk2;
4'b11XX: q2_out <= # mxinp1 q2rnk3;
default: q2_out <= # mxinp1 q2rnk2;
endcase
end
always @ (bitslip_en or q3rnk2 or q3rnk3) begin
case (bitslip_en)
1'b0: q3_out <= # mxinp1 q3rnk2;
1'b1: q3_out <= # mxinp1 q3rnk3;
default: q3_out <= # mxinp1 q3rnk2;
endcase
end
always @ (bitslip_en or q4rnk2 or q4rnk3) begin
casex (bitslip_en)
1'b0: q4_out <= # mxinp1 q4rnk2;
1'b1: q4_out <= # mxinp1 q4rnk3;
default: q4_out <= # mxinp1 q4rnk2;
endcase
end
always @ (bitslip_en or q5rnk2 or q5rnk3) begin
casex (bitslip_en)
1'b0: q5_out <= # mxinp1 q5rnk2;
1'b1: q5_out <= # mxinp1 q5rnk3;
default: q5_out <= # mxinp1 q5rnk2;
endcase
end
always @ (bitslip_en or q6rnk2 or q6rnk3) begin
casex (bitslip_en)
1'b0: q6_out <= # mxinp1 q6rnk2;
1'b1: q6_out <= # mxinp1 q6rnk3;
default: q6_out <= # mxinp1 q6rnk2;
endcase
end
// Instantiate Bitslip controller
bscntrl_iserdese1_vlog bsc (.c23(c23), .c45(c45), .c67(c67), .sel(sel),
.DATA_RATE(data_rate_int), .bitslip(bitslip_in),
.clk(!clkoimux), .clkdiv(clkdivoimux), .r(rst_in),
.clkdiv_int(clkdiv_int), .muxc(muxc)
);
// Set value of counter in bitslip controller
always @ (cntr or c23 or c45 or c67 or sel)
begin
casex (cntr)
5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default: $display("DATA_WIDTH %b and DATA_RATE %b at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
endcase
end
// Instantiate clock enable circuit
ice_iserdese1_vlog cec (.ce1(ce1_in), .ce2(ce2_in), .NUM_CE(num_ce_int),
.clkdiv(rank3clkmux), .r(rst_in), .ice(ice)
);
`ifndef XIL_TIMING
specify
(CLK => Q1) = (100:100:100, 100:100:100);
(CLK => Q2) = (100:100:100, 100:100:100);
(CLK => Q3) = (100:100:100, 100:100:100);
(CLK => Q4) = (100:100:100, 100:100:100);
(CLK => Q5) = (100:100:100, 100:100:100);
(CLK => Q6) = (100:100:100, 100:100:100);
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
(D => O) = (0, 0);
(DDLY => O) = (0, 0);
(OFB => O) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
specify
(D => O) = (0:0:0, 0:0:0);
(DDLY => O) = (0:0:0, 0:0:0);
(OFB => O) = (0:0:0, 0:0:0);
(CLK => Q1) = (100:100:100, 100:100:100);
(CLK => Q2) = (100:100:100, 100:100:100);
(CLK => Q3) = (100:100:100, 100:100:100);
(CLK => Q4) = (100:100:100, 100:100:100);
(CLK => Q5) = (100:100:100, 100:100:100);
(CLK => Q6) = (100:100:100, 100:100:100);
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
(RST => Q1) = (0:0:0, 0:0:0);
(RST => Q2) = (0:0:0, 0:0:0);
(RST => Q3) = (0:0:0, 0:0:0);
(RST => Q4) = (0:0:0, 0:0:0);
(RST => Q5) = (0:0:0, 0:0:0);
(RST => Q6) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier, , , clk_in, ddly_in);
$setuphold (posedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier, , , clk_in, ddly_in);
$setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier, , , clk_in, ofb_in);
$setuphold (posedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier, , , clk_in, ofb_in);
$setuphold (posedge CLKB, posedge D, 0:0:0, 0:0:0, notifier, , , clkb_in, d_in);
$setuphold (posedge CLKB, negedge D, 0:0:0, 0:0:0, notifier, , , clkb_in, d_in);
$setuphold (posedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier, , , clkb_in, ddly_in);
$setuphold (posedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier, , , clkb_in, ddly_in);
$setuphold (posedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkb_in, ce1_in);
$setuphold (posedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkb_in, ce1_in);
$setuphold (posedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier, , , clkb_in, ofb_in);
$setuphold (posedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier, , , clkb_in, ofb_in);
$setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
$setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
//-- SYNC
$setuphold (posedge CLK, posedge RST, 0:0:0, 0:0:0, notifier, , , clk_in, rst_in);
$setuphold (posedge CLK, negedge RST, 0:0:0, 0:0:0, notifier, , , clk_in, rst_in);
$setuphold (posedge CLKB, posedge RST, 0:0:0, 0:0:0, notifier, , , clkb_in, rst_in);
$setuphold (posedge CLKB, negedge RST, 0:0:0, 0:0:0, notifier, , , clkb_in, rst_in);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rst_in);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rst_in);
$setuphold (posedge OCLK, posedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in);
$setuphold (posedge OCLK, negedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in);
$setuphold (negedge OCLK, posedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in);
$setuphold (negedge OCLK, negedge RST, 0:0:0, 0:0:0, notifier, , , oclk_in, rst_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKB, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge OCLK, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKB, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge OCLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKB, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge OCLK, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // ISERDESE1
`timescale 1ps/1ps
///////////////////////////////////////////////////////
//
// Bit slip controller
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// bitslip: Activates bitslip controller
// clk: High speed forwarded clock
// clkdiv: Low speed from clock divider in H clock row
// r: Generates resest for flops
//
//
// Outputs:
// clkdiv_int: Generates clock same frequency as clkdiv
// muxc: Controls mux in 2nd rank for DDR bitslip
//
//
// Programmable options
//
// DATA_RATE: Selects between sdr "1" and ddr "0" operation
// c23: Selector between divide by 2 and divide by 3
// c45: Selector between divide by 4 and divide by 5
// c67: Selector between divide by 6 and divide by 7
// sel: Mux selector with following table:
// 00: Divide by 2 or 3
// 01: Divide by 4 or 5
// 10: Divide by 6 or 7
// 11: Divide by 8
//
////////////////////////////////////////////////////////////////////////////////
//
module bscntrl_iserdese1_vlog (c23, c45, c67, sel, DATA_RATE,
bitslip,
clk, clkdiv, r,
clkdiv_int,muxc
);
// programmable points
input c23, c45, c67, DATA_RATE;
input [1:0] sel;
// regular inputs
input clk, r, clkdiv;
input bitslip;
// Programmable Test Attributes
wire SRTYPE;
assign SRTYPE = 1'b0;
// outputs
output clkdiv_int, muxc;
reg clkdiv_int;
reg q1, q2, q3;
reg mux;
reg qhc1, qhc2, qlc1, qlc2;
reg qr1, qr2;
reg mux1, muxc;
//////////////////////////////////////////////////
//
// Delay parameter assignment
//
/////////////////////////////////////////////////
localparam ffbsc = 300;
localparam mxbsc = 60;
////////////////////////////////////////////////////
//
// Initialization of flops through GSR
//
///////////////////////////////////////////////////
`ifdef SW_NO_ISERDES_TEST
`else
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign q3 = 1'b0;
assign q2 = 1'b0;
assign q1 = 1'b0;
assign clkdiv_int = 1'b0;
end
else
begin
deassign q3;
deassign q2;
deassign q1;
deassign clkdiv_int;
end
end
`endif
//////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
///////////////////////////////
//
// Divide by 2 - 8 counter
//
////////////////////////////////
// Asynchronous Operation
always @ (posedge qr2 or posedge clk)
begin
if (qr2 & SRTYPE)
begin
clkdiv_int <= # ffbsc 1'b0;
q1 <= # ffbsc 1'b0;
q2 <= # ffbsc 1'b0;
q3 <= # ffbsc 1'b0;
end
else if (qhc1 & SRTYPE)
begin
clkdiv_int <= # ffbsc clkdiv_int;
q1 <= # ffbsc q1;
q2 <= # ffbsc q2;
q3 <= # ffbsc q3;
end
else if (SRTYPE)
begin
q3 <= # ffbsc q2;
q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1);
q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end
// Synchronous Operation
always @ (posedge clk)
begin
if (qr2 & !SRTYPE)
begin
clkdiv_int <= # ffbsc 1'b0;
q1 <= # ffbsc 1'b0;
q2 <= # ffbsc 1'b0;
q3 <= # ffbsc 1'b0;
end
else if (qhc1 & !SRTYPE)
begin
clkdiv_int <= # ffbsc clkdiv_int;
q1 <= # ffbsc q1;
q2 <= # ffbsc q2;
q3 <= # ffbsc q3;
end
else if (!SRTYPE)
begin
q3 <= # ffbsc q2;
q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1);
q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end
//////////////////////////////////////////
// 4:1 selector mux and divider selections
//////////////////////////////////////////
always @ (sel or c23 or c45 or c67 or clkdiv_int or q1 or q2 or q3)
begin
case (sel)
2'b00: mux <= # mxbsc !(clkdiv_int | (c23 & q1));
2'b01: mux <= # mxbsc !(q1 | (c45 & q2));
2'b10: mux <= # mxbsc !(q2 | (c67 & q3));
2'b11: mux <= # mxbsc !q3;
default: mux <= # mxbsc !(clkdiv_int | (c23 & q1));
endcase
end
///////////////////////////////////
//
// Bitslip control logic
//
///////////////////////////////////
/////////////////////
// Low speed control flop
///////////////////////
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv)
begin
begin
if (qr1 & SRTYPE)
begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (!bitslip & SRTYPE)
begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else if (SRTYPE)
begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip & mux1);
end
end
end
// Synchronous Operation
always @ (posedge clkdiv)
begin
begin
if (qr1 & !SRTYPE)
begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (!bitslip & !SRTYPE)
begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else if (!SRTYPE)
begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip & mux1);
end
end
end
/////////////////////////////////////////////
// Mux to select between sdr "1" and ddr "0"
/////////////////////////////////////////////
always @ (qlc1 or DATA_RATE)
begin
case (DATA_RATE)
1'b0: mux1 <= # mxbsc qlc1;
1'b1: mux1 <= # mxbsc 1'b1;
endcase
end
/////////////////////////
// High speed control flop
/////////////////////////
// Asynchronous Operation
always @ (posedge qr2 or posedge clk)
begin
begin
if (qr2 & SRTYPE)
begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else if (SRTYPE)
begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end
end
// Synchronous Operation
always @ (posedge clk)
begin
begin
if (qr2 & !SRTYPE)
begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else if (!SRTYPE)
begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end
end
/////////////////////////////////////////////
// Mux that drives control line of mux in front
// of 2nd rank of flops
//////////////////////////////////////////
always @ (mux1 or DATA_RATE)
begin
case (DATA_RATE)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
/////////////////////////////
// Asynchronous set flops
/////////////////////////////
/////////////////////
// Low speed reset flop
///////////////////////
// Asynchronous Operation
always @ (posedge r or posedge clkdiv)
begin
if (r & SRTYPE)
begin
qr1 <= # ffbsc 1'b1;
end
else if (SRTYPE)
begin
qr1 <= # ffbsc 1'b0;
end
end
// Synchronous Operation
always @ (posedge clkdiv)
begin
if (r & !SRTYPE)
begin
qr1 <= # ffbsc 1'b1;
end
else if (!SRTYPE)
begin
qr1 <= # ffbsc 1'b0;
end
end
/////////////////////
// High speed reset flop
///////////////////////
// Asynchronous Operation
always @ (posedge r or posedge clk)
begin
if (r & SRTYPE)
begin
qr2 <= # ffbsc 1'b1;
end
else if (SRTYPE)
begin
qr2 <= # ffbsc qr1;
end
end
// Synchronous Operation
always @ (posedge clk)
begin
if (r & !SRTYPE)
begin
qr2 <= # ffbsc 1'b1;
end
else if (!SRTYPE)
begin
qr2 <= # ffbsc qr1;
end
end
///////////////////////
endmodule
`timescale 1ps/1ps
//
///////////////////////////////////////////////////////
//
// Input Clock Enable Circuit
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs: ce1: 1st and default clock enable
// ce2: 2nd clock enable used for serdes memory cases
// r: Synchronous reset
// clkdiv: Low speed output clock generated off the DCM
//
//
//
// Outputs: intce: Clock enable
//
//
// Programmable options
//
// NUM_CE: 0: ce1 only, 1: ce1 and ce2
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module ice_iserdese1_vlog (ce1, ce2, NUM_CE,
clkdiv, r,
ice
);
// regular inputs
input ce1, ce2;
input clkdiv, r;
// programmable points
input NUM_CE;
// programmable test points
// Synchronus RST
wire SRTYPE;
assign SRTYPE = 1'b0;
// output
output ice;
reg ce1r, ce2r, ice;
wire [1:0] cesel;
assign cesel = {NUM_CE,clkdiv};
//////////////////////////////////////////////////
//
// Delay parameters
//
/////////////////////
localparam ffice = 300;
localparam mxice = 60;
////////////////////////////////////////////////////
//
// Initialization of flops through GSR
//
///////////////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign ce1r = 1'b0;
assign ce2r = 1'b0;
end
else
begin
deassign ce1r;
deassign ce2r;
end
end
//////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv or posedge r)
begin
if (r & SRTYPE)
begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else if (SRTYPE)
begin
ce1r <= # ffice ce1;
ce2r <= # ffice ce2;
end
end
// Synchronous Operation
always @ (posedge clkdiv)
begin
if (r & !SRTYPE)
begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else if (!SRTYPE)
begin
ce1r <= # ffice ce1;
ce2r <= # ffice ce2;
end
end
// Output mux
always @ (cesel or ce1 or ce1r or ce2r)
begin
case (cesel)
2'b00: ice <= # mxice ce1;
2'b01: ice <= # mxice ce1;
2'b10: ice <= # mxice ce2r;
2'b11: ice <= # mxice ce1r;
default: ice <= # mxice ce1;
endcase
end
///////////////////////
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ISERDESE2.v 0000664 0000000 0000000 00000065602 12327044266 0022720 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Input Deserializer for Virtex7
// /___/ /\ Filename : ISERDESE2.v
// \ \ / \ Timestamp : Tue Jan 19 16:29:39 PST 2010
// \___\/\___\
//
// Revision:
// 01/19/10 - Initial version.
// 03/24/11 - Sync-up
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDESE2 (
O,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
SHIFTOUT1,
SHIFTOUT2,
BITSLIP,
CE1,
CE2,
CLK,
CLKB,
CLKDIV,
CLKDIVP,
D,
DDLY,
DYNCLKDIVSEL,
DYNCLKSEL,
OCLK,
OCLKB,
OFB,
RST,
SHIFTIN1,
SHIFTIN2
);
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter DYN_CLKDIV_INV_EN = "FALSE";
parameter DYN_CLK_INV_EN = "FALSE";
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter [0:0] IS_CLKB_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
parameter [0:0] IS_OCLK_INVERTED = 1'b0;
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter integer NUM_CE = 2;
parameter OFB_USED = "FALSE";
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input CLKDIVP;
input D;
input DDLY;
input DYNCLKDIVSEL;
input DYNCLKSEL;
input OCLK;
input OCLKB;
input OFB;
input RST;
input SHIFTIN1;
input SHIFTIN2;
tri0 GSR = glbl.GSR;
reg INTERFACE_TYPE_BINARY;
reg IOBDELAY_BINARY;
reg [0:0] DATA_RATE_BINARY;
reg [0:0] DYN_CLKDIV_INV_EN_BINARY;
reg [0:0] DYN_CLK_INV_EN_BINARY;
reg [0:0] INIT_Q1_BINARY;
reg [0:0] INIT_Q2_BINARY;
reg [0:0] INIT_Q3_BINARY;
reg [0:0] INIT_Q4_BINARY;
reg [0:0] NUM_CE_BINARY;
reg [0:0] SERDES_MODE_BINARY;
reg [1:0] OFB_USED_BINARY;
reg [3:0] DATA_WIDTH_BINARY;
reg data_in = 0;
reg o_out_pre_fb = 0, o_delay_pre_fb = 0;
reg o_out = 0;
reg notifier;
// wire O_OUT;
wire Q1_OUT;
wire Q2_OUT;
wire Q3_OUT;
wire Q4_OUT;
wire Q5_OUT;
wire Q6_OUT;
wire Q7_OUT;
wire Q8_OUT;
wire SHIFTOUT1_OUT;
wire SHIFTOUT2_OUT;
wire BITSLIP_IN;
wire CE1_IN;
wire CE2_IN;
wire CLKB_IN;
wire CLKDIVP_IN;
wire CLKDIV_IN;
wire CLK_IN;
wire DDLY_IN;
wire DYNCLKDIVSEL_IN;
wire DYNCLKSEL_IN;
wire D_IN;
wire OCLKB_IN;
wire OCLK_IN;
wire OFB_IN;
wire RST_IN;
wire SHIFTIN1_IN;
wire SHIFTIN2_IN;
wire BITSLIP_INDELAY;
wire CE1_INDELAY;
wire CE2_INDELAY;
wire CLKB_INDELAY;
wire CLKDIVP_INDELAY;
wire CLKDIV_INDELAY;
wire CLK_INDELAY;
wire DDLY_INDELAY;
wire DYNCLKDIVSEL_INDELAY;
wire DYNCLKSEL_INDELAY;
wire D_INDELAY;
wire OCLKB_INDELAY;
wire OCLK_INDELAY;
wire OFB_INDELAY;
wire RST_INDELAY;
wire SHIFTIN1_INDELAY;
wire SHIFTIN2_INDELAY;
//---------------------------------------
buf B_O (O, O_OUT);
buf B_Q1 (Q1, Q1_OUT);
buf B_Q2 (Q2, Q2_OUT);
buf B_Q3 (Q3, Q3_OUT);
buf B_Q4 (Q4, Q4_OUT);
buf B_Q5 (Q5, Q5_OUT);
buf B_Q6 (Q6, Q6_OUT);
buf B_Q7 (Q7, Q7_OUT);
buf B_Q8 (Q8, Q8_OUT);
buf B_SHIFTOUT1 (SHIFTOUT1, SHIFTOUT1_OUT);
buf B_SHIFTOUT2 (SHIFTOUT2, SHIFTOUT2_OUT);
buf B_BITSLIP (BITSLIP_IN, BITSLIP);
buf B_CE1 (CE1_IN, CE1);
buf B_CE2 (CE2_IN, CE2);
buf B_CLK (CLK_IN, CLK);
buf B_CLKB (CLKB_IN, CLKB);
buf B_CLKDIV (CLKDIV_IN, CLKDIV);
buf B_CLKDIVP (CLKDIVP_IN, CLKDIVP);
buf B_D (D_IN, D);
buf B_DDLY (DDLY_IN, DDLY);
buf B_DYNCLKDIVSEL (DYNCLKDIVSEL_IN, DYNCLKDIVSEL);
buf B_DYNCLKSEL (DYNCLKSEL_IN, DYNCLKSEL);
buf B_OCLK (OCLK_IN, OCLK);
buf B_OCLKB (OCLKB_IN, OCLKB);
buf B_OFB (OFB_IN, OFB);
buf B_RST (RST_IN, RST);
buf B_SHIFTIN1 (SHIFTIN1_IN, SHIFTIN1);
buf B_SHIFTIN2 (SHIFTIN2_IN, SHIFTIN2);
wire delay_O;
wire delay_Q1;
wire delay_Q2;
wire delay_Q3;
wire delay_Q4;
wire delay_Q5;
wire delay_Q6;
wire delay_Q7;
wire delay_Q8;
wire delay_SHIFTOUT1;
wire delay_SHIFTOUT2;
wire delay_BITSLIP,BITSLIP_in;
wire delay_CE1,CE1_in;
wire delay_CE2,CE2_in;
wire delay_CLK,CLK_inv,CLK_in;
wire delay_CLKB,CLKB_inv,CLKB_in;
wire delay_CLKDIV,CLKDIV_inv,CLKDIV_in;
wire delay_CLKDIVP,CLKDIVP_inv,CLKDIVP_in;
wire delay_D,D_inv,D_in;
wire delay_DDLY,DDLY_in;
wire delay_DYNCLKDIVSEL,DYNCLKDIVSEL_in;
wire delay_DYNCLKSEL,DYNCLKSEL_in;
wire delay_OCLK,OCLK_inv,OCLK_in;
wire delay_OCLKB,OCLKB_inv,OCLKB_in;
wire delay_OFB,OFB_in;
wire delay_RST,RST_in;
wire delay_SHIFTIN1,SHIFTIN1_in;
wire delay_SHIFTIN2,SHIFTIN2_in;
assign #(out_delay) O_OUT = o_out;
assign #(out_delay) Q1_OUT = delay_Q1;
assign #(out_delay) Q2_OUT = delay_Q2;
assign #(out_delay) Q3_OUT = delay_Q3;
assign #(out_delay) Q4_OUT = delay_Q4;
assign #(out_delay) Q5_OUT = delay_Q5;
assign #(out_delay) Q6_OUT = delay_Q6;
assign #(out_delay) Q7_OUT = delay_Q7;
assign #(out_delay) Q8_OUT = delay_Q8;
assign #(out_delay) SHIFTOUT1_OUT = delay_SHIFTOUT1;
assign #(out_delay) SHIFTOUT2_OUT = delay_SHIFTOUT2;
`ifndef XIL_TIMING // unisim
assign #(in_delay) delay_BITSLIP = BITSLIP;
assign #(in_delay) delay_CE1 = CE1;
assign #(in_delay) delay_CE2 = CE2;
assign #(INCLK_DELAY) delay_CLK = CLK;
assign #(INCLK_DELAY) delay_CLKB = CLKB;
assign #(INCLK_DELAY) delay_CLKDIV = CLKDIV;
assign #(INCLK_DELAY) delay_CLKDIVP = CLKDIVP;
assign #(in_delay) delay_D = D;
assign #(in_delay) delay_DDLY = DDLY;
assign #(in_delay) delay_DYNCLKDIVSEL = DYNCLKDIVSEL;
assign #(in_delay) delay_DYNCLKSEL = DYNCLKSEL;
assign #(INCLK_DELAY) delay_OCLK = OCLK;
assign #(INCLK_DELAY) delay_OCLKB = OCLKB;
assign #(in_delay) delay_OFB = OFB;
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SHIFTIN1 = SHIFTIN1;
assign #(in_delay) delay_SHIFTIN2 = SHIFTIN2;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL;
assign delay_DYNCLKSEL = DYNCLKSEL;
assign delay_OCLK = OCLK;
assign delay_OCLKB = OCLKB;
assign delay_SHIFTIN1 = SHIFTIN1;
assign delay_SHIFTIN2 = SHIFTIN2;
`endif
//`ifdef XIL_TIMING //Simprim
assign BITSLIP_in = delay_BITSLIP;
assign CE1_in = delay_CE1;
assign CE2_in = delay_CE2;
assign DDLY_in = delay_DDLY;
assign DYNCLKDIVSEL_in = delay_DYNCLKDIVSEL;
assign DYNCLKSEL_in = delay_DYNCLKSEL;
assign OFB_in = delay_OFB;
assign RST_in = delay_RST;
assign SHIFTIN1_in = delay_SHIFTIN1;
assign SHIFTIN2_in = delay_SHIFTIN2;
//`endif
assign CLK_in = IS_CLK_INVERTED ^ delay_CLK;
assign CLKB_in = IS_CLKB_INVERTED ^ delay_CLKB;
assign CLKDIV_in = IS_CLKDIV_INVERTED ^ delay_CLKDIV;
assign CLKDIVP_in = IS_CLKDIVP_INVERTED ^ delay_CLKDIVP;
assign D_in = IS_D_INVERTED ^ delay_D;
assign OCLK_in = IS_OCLK_INVERTED ^ delay_OCLK;
assign OCLKB_in = IS_OCLKB_INVERTED ^ delay_OCLKB;
assign #(INCLK_DELAY) CLKB_INDELAY = CLKB_IN;
assign #(INCLK_DELAY) CLKDIVP_INDELAY = CLKDIVP_IN;
assign #(INCLK_DELAY) CLKDIV_INDELAY = CLKDIV_IN;
assign #(INCLK_DELAY) CLK_INDELAY = CLK_IN;
assign #(INCLK_DELAY) OCLKB_INDELAY = OCLKB_IN;
assign #(INCLK_DELAY) OCLK_INDELAY = OCLK_IN;
assign #(in_delay) BITSLIP_INDELAY = BITSLIP_IN;
assign #(in_delay) CE1_INDELAY = CE1_IN;
assign #(in_delay) CE2_INDELAY = CE2_IN;
assign #(in_delay) DDLY_INDELAY = DDLY_IN;
assign #(in_delay) DYNCLKDIVSEL_INDELAY = DYNCLKDIVSEL_IN;
assign #(in_delay) DYNCLKSEL_INDELAY = DYNCLKSEL_IN;
assign #(in_delay) D_INDELAY = D_IN;
assign #(in_delay) OFB_INDELAY = OFB_IN;
assign #(in_delay) RST_INDELAY = RST_IN;
assign #(in_delay) SHIFTIN1_INDELAY = SHIFTIN1_IN;
assign #(in_delay) SHIFTIN2_INDELAY = SHIFTIN2_IN;
assign delay_DYNCLKDIVSEL = DYNCLKDIVSEL_INDELAY;
assign delay_DYNCLKSEL = DYNCLKSEL_INDELAY;
// assign delay_OCLK = OCLK_INDELAY;
// assign delay_OCLKB = OCLKB_INDELAY;
// assign delay_RST = RST_INDELAY;
// assign delay_SHIFTIN1 = SHIFTIN1_INDELAY;
// assign delay_SHIFTIN2 = SHIFTIN2_INDELAY;
//----------------------------------------------------------
//------------------------- TASKS --------------------------
//----------------------------------------------------------
task INTERFACE_TYPE_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10, 14\n");
$display("MEMORY SDR None\n");
$display("MEMORY DDR 4\n");
end
endtask // INTERFACE_TYPE_msg
task OVERSAMPLE_DDR_SDR_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("OVERSAMPLE SDR none\n");
$display("OVERSAMPLE DDR 4\n");
end
endtask // OVERSAMPLE_DDR_SDR_msg
//----------------------------------------------------------
//------------------ Parameter Checks ----------------------
//----------------------------------------------------------
initial begin
//-------------------------------------------------
//----- DATA_RATE check
//-------------------------------------------------
case (DATA_RATE)
"SDR", "DDR" :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
$finish;
end
endcase // case(DATA_RATE)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10, 14 :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, 10 or 14", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DYN_CLKDIV_INV_EN check
//-------------------------------------------------
case (DYN_CLKDIV_INV_EN)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN);
$finish;
end
endcase // case(DYN_CLKDIV_INV_EN)
//-------------------------------------------------
//----- DYN_CLK_INV_EN check
//-------------------------------------------------
case (DYN_CLK_INV_EN)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN);
$finish;
end
endcase // case(DYN_CLK_INV_EN)
//-------------------------------------------------
//----- IOBDELAY check
//-------------------------------------------------
case (IOBDELAY)
"NONE", "IBUF", "IFD", "BOTH" :;
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
//-------------------------------------------------
//----- OFB_USED check
//-------------------------------------------------
case (OFB_USED)
"TRUE", "FALSE" :;
default : begin
$display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED);
$finish;
end
endcase // case(OFB_USED)
//-------------------------------------------------
//----- NUM_CE check
//-------------------------------------------------
case (NUM_CE)
1, 2 :;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE2 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
$finish;
end
endcase // case(NUM_CE)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"MEMORY" : begin
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : INTERFACE_TYPE_msg;
endcase // DATA_RATE
end
"NETWORKING" : begin
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10, 14 : ;
default : INTERFACE_TYPE_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
"MEMORY_DDR3" :;
"MEMORY_QDR" :;
"OVERSAMPLE" : begin
case(DATA_RATE)
"SDR" : OVERSAMPLE_DDR_SDR_msg;
"DDR" :
case(DATA_WIDTH)
4 : ;
default : OVERSAMPLE_DDR_SDR_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
end
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE);
$finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER", "SLAVE" :;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE2 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
end // initial begin
// CR 574021
//-------------------------------------------------
// Input to ISERDES
//-------------------------------------------------
always @(D_in or DDLY_in) begin
case (IOBDELAY)
"NONE" : begin
o_out_pre_fb <= D_in;
o_delay_pre_fb <= D_in;
end
"IBUF" : begin
o_out_pre_fb <= DDLY_in;
o_delay_pre_fb <= D_in;
end
"IFD" : begin
o_out_pre_fb <= D_in;
o_delay_pre_fb <= DDLY_in;
end
"BOTH" : begin
o_out_pre_fb <= DDLY_in;
o_delay_pre_fb <= DDLY_in;
end
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE2 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
end // always @ (D_in or DDLY_in)
generate
case (OFB_USED)
"TRUE" : always @(OFB_in)
begin
o_out <= OFB_in;
data_in <= OFB_in;
end
"FALSE" : begin
always @(o_out_pre_fb) o_out <= o_out_pre_fb;
always @(o_delay_pre_fb) data_in <= o_delay_pre_fb;
end
endcase
endgenerate
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
B_ISERDESE2 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN (DYN_CLK_INV_EN),
.INIT_Q1 (INIT_Q1),
.INIT_Q2 (INIT_Q2),
.INIT_Q3 (INIT_Q3),
.INIT_Q4 (INIT_Q4),
.INTERFACE_TYPE (INTERFACE_TYPE),
.IOBDELAY (IOBDELAY),
.NUM_CE (NUM_CE),
.OFB_USED (OFB_USED),
.SERDES_MODE (SERDES_MODE),
.SRVAL_Q1 (SRVAL_Q1),
.SRVAL_Q2 (SRVAL_Q2),
.SRVAL_Q3 (SRVAL_Q3),
.SRVAL_Q4 (SRVAL_Q4))
B_ISERDESE2_INST (
.O (delay_O),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.SHIFTOUT1 (delay_SHIFTOUT1),
.SHIFTOUT2 (delay_SHIFTOUT2),
.BITSLIP (BITSLIP_in),
.CE1 (CE1_in),
.CE2 (CE2_in),
.CLK (CLK_in),
.CLKB (CLKB_in),
.CLKDIV (CLKDIV_in),
.CLKDIVP (CLKDIVP_in),
.D (data_in),
.DDLY (DDLY_in),
.DYNCLKDIVSEL (DYNCLKDIVSEL_in),
.DYNCLKSEL (DYNCLKSEL_in),
.OCLK (OCLK_in),
.OCLKB (OCLKB_in),
.OFB (OFB_in),
.RST (RST_in),
.SHIFTIN1 (SHIFTIN1_in),
.SHIFTIN2 (SHIFTIN2_in),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKB, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (negedge CLKDIVP, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKB, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge CLKDIVP, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CE1);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_D);
$setuphold (posedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_DDLY);
$setuphold (posedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OFB);
$setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CE1);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_D);
$setuphold (posedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_DDLY);
$setuphold (posedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OFB);
$setuphold (posedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_CE1);
$setuphold (posedge CLKB, negedge D, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_D);
$setuphold (posedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_DDLY);
$setuphold (posedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_OFB);
$setuphold (posedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_CE1);
$setuphold (posedge CLKB, posedge D, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_D);
$setuphold (posedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_DDLY);
$setuphold (posedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_OFB);
$setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_BITSLIP);
$setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE1);
$setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE2);
$setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_BITSLIP);
$setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE1);
$setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE2);
$setuphold (posedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE1);
$setuphold (posedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE2);
$setuphold (posedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE1);
$setuphold (posedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE2);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (posedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_RST);
$setuphold (posedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_RST);
$setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CE1);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_D);
$setuphold (negedge CLK, negedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_DDLY);
$setuphold (negedge CLK, negedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OFB);
$setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CE1);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_D);
$setuphold (negedge CLK, posedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_DDLY);
$setuphold (negedge CLK, posedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OFB);
$setuphold (negedge CLKB, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_CE1);
$setuphold (negedge CLKB, negedge D, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_D);
$setuphold (negedge CLKB, negedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_DDLY);
$setuphold (negedge CLKB, negedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_OFB);
$setuphold (negedge CLKB, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_CE1);
$setuphold (negedge CLKB, posedge D, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_D);
$setuphold (negedge CLKB, posedge DDLY, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_DDLY);
$setuphold (negedge CLKB, posedge OFB, 0:0:0, 0:0:0, notifier,,, delay_CLKB, delay_OFB);
$setuphold (negedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_BITSLIP);
$setuphold (negedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE1);
$setuphold (negedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE2);
$setuphold (negedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_BITSLIP);
$setuphold (negedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE1);
$setuphold (negedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_CE2);
$setuphold (negedge CLKDIVP, negedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE1);
$setuphold (negedge CLKDIVP, negedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE2);
$setuphold (negedge CLKDIVP, posedge CE1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE1);
$setuphold (negedge CLKDIVP, posedge CE2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_CE2);
$setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (negedge CLKDIVP, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_RST);
$setuphold (negedge CLKDIVP, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIVP, delay_RST);
`endif
( CLK => Q1) = (100:100:100, 100:100:100);
( CLK => Q2) = (100:100:100, 100:100:100);
( CLK => Q3) = (100:100:100, 100:100:100);
( CLK => Q4) = (100:100:100, 100:100:100);
( CLK => Q5) = (100:100:100, 100:100:100);
( CLK => Q6) = (100:100:100, 100:100:100);
( CLK => Q7) = (100:100:100, 100:100:100);
( CLK => Q8) = (100:100:100, 100:100:100);
( CLKDIV => Q1) = (100:100:100, 100:100:100);
( CLKDIV => Q2) = (100:100:100, 100:100:100);
( CLKDIV => Q3) = (100:100:100, 100:100:100);
( CLKDIV => Q4) = (100:100:100, 100:100:100);
( CLKDIV => Q5) = (100:100:100, 100:100:100);
( CLKDIV => Q6) = (100:100:100, 100:100:100);
( CLKDIV => Q7) = (100:100:100, 100:100:100);
( CLKDIV => Q8) = (100:100:100, 100:100:100);
( CLKDIVP => Q1) = (100:100:100, 100:100:100);
( CLKDIVP => Q2) = (100:100:100, 100:100:100);
( CLKDIVP => Q3) = (100:100:100, 100:100:100);
( CLKDIVP => Q4) = (100:100:100, 100:100:100);
( CLKDIVP => Q5) = (100:100:100, 100:100:100);
( CLKDIVP => Q6) = (100:100:100, 100:100:100);
( CLKDIVP => Q7) = (100:100:100, 100:100:100);
( CLKDIVP => Q8) = (100:100:100, 100:100:100);
( D => O) = (100:100:100, 100:100:100);
( OFB => O) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ISERDESE3.v 0000664 0000000 0000000 00000024225 12327044266 0022715 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : ISERDESE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ISERDESE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter FIFO_ENABLE = "FALSE",
parameter FIFO_SYNC_MODE = "FALSE",
parameter IDDR_MODE = "FALSE",
parameter [0:0] IS_CLK_B_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0
)(
output FIFO_EMPTY,
output [7:0] Q,
input CLK,
input CLKDIV,
input CLK_B,
input D,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input RST
);
// define constants
localparam MODULE_NAME = "ISERDESE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
localparam [40:1] FIFO_ENABLE_REG = FIFO_ENABLE;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [40:1] IDDR_MODE_REG = IDDR_MODE;
localparam [0:0] IS_CLK_B_INVERTED_REG = IS_CLK_B_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`endif
localparam [40:1] DDR_DIS_DQS_REG = "FALSE";
wire IS_CLK_B_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "ISERDESE3_dr.v"
`endif
wire FIFO_EMPTY_out;
wire [7:0] Q_out;
wire FIFO_EMPTY_delay;
wire [7:0] Q_delay;
wire CLKDIV_in;
wire CLK_B_in;
wire CLK_in;
wire D_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire RST_in;
wire CLKDIV_delay;
wire CLK_B_delay;
wire CLK_delay;
wire D_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire RST_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) Q = Q_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLKDIV_delay = CLKDIV;
assign #(inclk_delay) CLK_B_delay = CLK_B;
assign #(inclk_delay) CLK_delay = CLK;
assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(in_delay) D_delay = D;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign Q_delay = Q_out;
assign CLKDIV_in = CLKDIV_delay;
assign CLK_B_in = CLK_B_delay ^ IS_CLK_B_INVERTED_BIN;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign D_in = D_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLK_B_INVERTED_BIN = IS_CLK_B_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 2) &&
(DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", MODULE_NAME, DDR_CLK_EDGE_REG);
attr_err = 1'b1;
end
if ((FIFO_ENABLE_REG != "FALSE") &&
(FIFO_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIFO_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIFO_ENABLE_REG);
attr_err = 1'b1;
end
if ((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIFO_SYNC_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((IDDR_MODE_REG != "FALSE") &&
(IDDR_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute IDDR_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, IDDR_MODE_REG);
attr_err = 1'b1;
end
if ((IS_CLK_B_INVERTED_REG < 1'b0) || (IS_CLK_B_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_B_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_B_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG < 1'b0) || (IS_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign IFD_CE_in = 1'b0; // tie off
SIP_ISERDESE3 SIP_ISERDESE3_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DDR_CLK_EDGE (DDR_CLK_EDGE_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.FIFO_ENABLE (FIFO_ENABLE_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.IDDR_MODE (IDDR_MODE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.Q (Q_out),
.CLK (CLK_in),
.CLKDIV (CLKDIV_in),
.CLK_B (CLK_B_in),
.D (D_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.RST (RST_in),
.GSR (glblGSR)
);
specify
(CLK *> Q) = (0:0:0, 0:0:0);
(CLK_B *> Q) = (0:0:0, 0:0:0);
(FIFO_RD_CLK *> Q) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => FIFO_EMPTY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (negedge CLK_B, 0:0:0, notifier);
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge CLK_B, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$recrem ( negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_B_delay);
$recrem ( negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$recrem ( negedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_B_delay);
$recrem ( negedge RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, FIFO_RD_CLK_delay);
$recrem ( posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_B_delay);
$recrem ( posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$recrem ( posedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_B_delay);
$recrem ( posedge RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, FIFO_RD_CLK_delay);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,,, CLK_delay, D_delay);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,,, CLK_delay, D_delay);
$setuphold (negedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier,,, CLK_B_delay, D_delay);
$setuphold (negedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier,,, CLK_B_delay, D_delay);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,,, CLK_delay, D_delay);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,,, CLK_delay, D_delay);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$setuphold (posedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier,,, CLK_B_delay, D_delay);
$setuphold (posedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier,,, CLK_B_delay, D_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK_B, 0:0:0, 0, notifier);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge CLK_B, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ISERDES_NODELAY.v 0000664 0000000 0000000 00000070712 12327044266 0023702 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Source Synchronous Input Deserializer without delay element
// /___/ /\ Filename : ISERDES_NODELAY.v
// \ \ / \ Timestamp : Fri Oct 21 10:31:45 PDT 2005
// \___\/\___\
//
// Revision:
// 10/21/05 - Initial version.
// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real)
// 06/16/06 - Added new port CLKB
// 10/13/06 - Fixed CR 426606
// 07/07/07 - Added wire declaration for internal signals
// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations
// 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations
// 01/12/11 - CR 589496 changed some internal parameters to localparams
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter INIT_Q3 = 1'b0;
parameter INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input D;
input OCLK;
input RST;
input SHIFTIN1;
input SHIFTIN2;
localparam SRVAL_Q1 = 1'b0;
localparam SRVAL_Q2 = 1'b0;
localparam SRVAL_Q3 = 1'b0;
localparam SRVAL_Q4 = 1'b0;
tri0 GSR = glbl.GSR;
reg [1:0] sel;
reg [3:0] data_width_int;
reg bts_q1, bts_q2, bts_q3;
reg c23, c45, c67;
reg ce1r, ce2r;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg ice, memmux, q2pmux;
reg mux, mux1, muxc;
reg notifier;
reg clkdiv_int, clkdivmux;
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg num_ce_int;
reg qr1, qr2, qhc1, qhc2, qlc1, qlc2;
reg shiftn2_in, shiftn1_in;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg serdes_mode_int, data_rate_int, bitslip_enable_int;
wire o_delay;
reg rev_in = 0;
wire shiftout1_out, shiftout2_out;
wire [1:0] sel1;
wire [2:0] bsmux;
wire [3:0] selrnk3;
wire bitslip_in;
wire ce1_in;
wire ce2_in;
wire clk_in;
wire clkb_in;
wire clkdiv_in;
wire d_in;
wire dlyce_in;
wire dlyinc_in;
wire dlyrst_in;
wire gsr_in;
wire oclk_in;
wire sr_in;
wire shiftin1_in;
wire shiftin2_in;
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_bitslip (bitslip_in, BITSLIP);
buf b_ce1 (ce1_in, CE1);
buf b_ce2 (ce2_in, CE2);
buf b_clk (clk_in, CLK);
buf b_clkb (clkb_in, CLKB);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d (d_in, D);
buf b_gsr (gsr_in, GSR);
buf b_oclk (oclk_in, OCLK);
buf b_sr (sr_in, RST);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
// WARNING !!!: This model may not work properly if the
// following parameters are changed.
// xilinx_internal_parameter on
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ffice = 300;
localparam mxice = 60;
// Delay parameter assignment
localparam ffbsc = 300;
localparam mxbsc = 60;
localparam mxinp1_my = 0;
// xilinx_internal_parameter off
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
task CR454107_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10\n");
$display("MEMORY SDR None\n");
$display("MEMORY DDR 4\n");
end
endtask // CR454107_msg
initial begin
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
case (INTERFACE_TYPE)
"NETWORKING" :
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
"MEMORY" :
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : CR454107_msg;
endcase // DATA_RATE
default : ;
endcase // INTERFACE_TYPE
// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------
if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin
$display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration.");
$finish;
end
else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin
$display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground.");
$finish;
end
//------------------------------------------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
$finish;
end
endcase // case(DATA_RATE)
case (BITSLIP_ENABLE)
"FALSE" : bitslip_enable_int <= 1'b0;
"TRUE" : bitslip_enable_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE);
$finish;
end
endcase // case(BITSLIP_ENABLE)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
$finish;
end
endcase // case(NUM_CE)
end // initial begin
assign sel1 = {serdes_mode_int, data_rate_int};
assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00};
assign bsmux = {bitslip_enable_int, data_rate_int, muxc};
// GSR
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
assign bts_q3 = 1'b0;
assign bts_q2 = 1'b0;
assign bts_q1 = 1'b0;
assign clkdiv_int = 1'b0;
assign ce1r = 1'b0;
assign ce2r = 1'b0;
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
end
else if (gsr_in == 1'b0) begin
deassign bts_q3;
deassign bts_q2;
deassign bts_q1;
deassign clkdiv_int;
deassign ce1r;
deassign ce2r;
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
end // if (gsr_in == 1'b0)
end // always @ (gsr_in)
// to workaround the glitches generated by mux of assign delay above
// always @(delay_count)
// delay_count_int <= #0 delay_count;
assign o_delay = d_in;
// 1st rank of registers
// Asynchronous Operation
always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
// 1st flop in rank 1 that is full featured
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1))
q1rnk1 <= # ffinp SRVAL_Q1;
else if (rev_in == 1'b1)
q1rnk1 <= # ffinp !SRVAL_Q1;
else if (ice == 1'b1)
q1rnk1 <= # ffinp o_delay;
end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
always @(posedge clk_in or posedge sr_in) begin
// rest of flops which are not full featured and don't have clock options
if (sr_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clk_in or sr_in)
// 2nd flop in rank 1
// Asynchronous Operation
always @(posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1))
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (rev_in == 1'b1)
q2nrnk1 <= # ffinp !SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp o_delay;
end // always @ (posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 4th flop in rank 1 operating on the posedge for networking
// Asynchronous Operation
always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1))
q2prnk1 <= # ffinp SRVAL_Q4;
else if (rev_in == 1'b1)
q2prnk1 <= # ffinp !SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 3rd flop in 2nd rank which is full featured and has
// a choice of being clocked by oclk or clk
// Asynchronous Operation
always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1))
q1prnk1 <= # ffinp SRVAL_Q3;
else if (rev_in == 1'b1)
q1prnk1 <= # ffinp !SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @(posedge memmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge memmux or posedge sr_in)
//////////////////////////////////////////
// Mux elements for the 1st rank
////////////////////////////////////////
// Optional inverter for q2p (4th flop in rank1)
always @ (memmux) begin
case (INTERFACE_TYPE)
"MEMORY" : q2pmux <= # mxinp1 !memmux;
"NETWORKING" : q2pmux <= # mxinp1 memmux;
default: q2pmux <= # mxinp1 !memmux;
endcase
end // always @ (memmux)
// 4 clock muxs in first rank
always @(clk_in or oclk_in) begin
case (INTERFACE_TYPE)
"MEMORY" : memmux <= # mxinp1 oclk_in;
"NETWORKING" : memmux <= # mxinp1 clk_in;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE);
$finish;
end
endcase // case(INTERFACE_TYPE)
end // always @(clk_in or oclk_in)
// data input mux for q3, q4, q5 and q6
always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in;
default : dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2)
always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1;
default : dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1)
always @(data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1;
default : dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(DATA_RATE)
end
always @(data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1;
default : dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(DATA_RATE)
end
// 2nd rank of registers
// clkdivmux to pass clkdiv_int or CLKDIV to rank 2
always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin
case (bitslip_enable_int)
1'b0 : clkdivmux <= # mxinp1 clkdiv_in;
1'b1 : clkdivmux <= # mxinp1 clkdiv_int;
default : clkdivmux <= # mxinp1 clkdiv_in;
endcase // case(BITSLIP_ENABLE)
end // always @(clkdiv_int or clkdiv_in)
// Asynchronous Operation
always @(posedge clkdivmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q2rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q2rnk2 <= # ffinp dataq2rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux or sr_in)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1;
3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1;
default : dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @(bsmux or q1prnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1;
3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1;
default : dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1prnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1;
3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1;
default : dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1;
3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1;
default : dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1;
3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1;
default : dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1;
3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1;
default : dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1)
// 3rd rank of registers
// Asynchronous Operation
always @(posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Outputs
assign shiftout2_out = q5rnk1;
assign shiftout1_out = q6rnk1;
always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00 : q1_out <= # mxinp1_my q1prnk1;
4'b0X01 : q1_out <= # mxinp1_my q1rnk1;
4'b0X10 : q1_out <= # mxinp1_my q1rnk1;
4'b10XX : q1_out <= # mxinp1_my q1rnk2;
4'b11XX : q1_out <= # mxinp1_my q1rnk3;
default : q1_out <= # mxinp1_my q1rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3)
always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00 : q2_out <= # mxinp1_my q2prnk1;
4'b0X01 : q2_out <= # mxinp1_my q2prnk1;
4'b0X10 : q2_out <= # mxinp1_my q2nrnk1;
4'b10XX : q2_out <= # mxinp1_my q2rnk2;
4'b11XX : q2_out <= # mxinp1_my q2rnk3;
default : q2_out <= # mxinp1_my q2rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3)
always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin
case (bitslip_enable_int)
1'b0 : q3_out <= # mxinp1_my q3rnk2;
1'b1 : q3_out <= # mxinp1_my q3rnk3;
endcase // case(BITSLIP_ENABLE)
end // always @ (q3rnk2 or q3rnk3)
always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin
casex (bitslip_enable_int)
1'b0 : q4_out <= # mxinp1_my q4rnk2;
1'b1 : q4_out <= # mxinp1_my q4rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q4rnk2 or q4rnk3)
always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin
casex (bitslip_enable_int)
1'b0 : q5_out <= # mxinp1_my q5rnk2;
1'b1 : q5_out <= # mxinp1_my q5rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q5rnk2 or q5rnk3)
always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin
casex (bitslip_enable_int)
1'b0 : q6_out <= # mxinp1_my q6rnk2;
1'b1 : q6_out <= # mxinp1_my q6rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q6rnk2 or q6rnk3)
// Set value of counter in bitslip controller
always @(data_rate_int or data_width_int) begin
casex ({data_rate_int, data_width_int})
5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default : begin
$display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
$finish;
end
endcase
end // always @ (data_rate_int or data_width_int)
///////////////////////////////////////////
// Bit slip controler
///////////////////////////////////////////
// Divide by 2 - 8 counter
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b0) begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (posedge qr2 or negedge clk_in)
// Synchronous Operation
always @ (negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b1) begin
clkdiv_int <= # ffbsc clkdiv_int;
bts_q1 <= # ffbsc bts_q1;
bts_q2 <= # ffbsc bts_q2;
bts_q3 <= # ffbsc bts_q3;
end
else begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (negedge clk_in)
// 4:1 selector mux and divider selections
always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin
case (sel)
2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2));
2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3));
2'b11 : mux <= # mxbsc !bts_q3;
default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
endcase
end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3)
// Bitslip control logic
// Low speed control flop
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv_in) begin
if (qr1 == 1'b1) begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (bitslip_in == 1'b0) begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip_in & mux1);
end
end // always @ (posedge qr1 or posedge clkdiv_in)
// Mux to select between sdr "1" and ddr "0"
always @ (data_rate_int or qlc1) begin
case (data_rate_int)
1'b0 : mux1 <= # mxbsc qlc1;
1'b1 : mux1 <= # mxbsc 1'b1;
endcase
end
// High speed control flop
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end // always @ (posedge qr2 or negedge clk_in)
// Mux that drives control line of mux in front
// of 2nd rank of flops
always @ (data_rate_int or mux1) begin
case (data_rate_int)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
// Asynchronous set flops
// Low speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qr1 <= # ffbsc 1'b1;
else
qr1 <= # ffbsc 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or negedge clk_in) begin
if (sr_in == 1'b1)
qr2 <= # ffbsc 1'b1;
else
qr2 <= # ffbsc qr1;
end // always @ (posedge sr_in or negedge clk_in)
/////////////////////////////////////////////
// ICE
///////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else begin
ce1r <= # ffice ce1_in;
ce2r <= # ffice ce2_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Output mux ice
always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin
case ({num_ce_int, clkdiv_in})
2'b00 : ice <= # mxice ce1_in;
2'b01 : ice <= # mxice ce1_in;
// 426606
2'b10 : ice <= # mxice ce2r;
2'b11 : ice <= # mxice ce1r;
default : ice <= # mxice ce1_in;
endcase
end
//*** Timing Checks Start here
specify
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ISERDES_NODELAY
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/JTAG_SIME2.v 0000664 0000000 0000000 00000071555 12327044266 0023063 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Jtag TAP Controler for VIRTEX7
// /___/ /\ Filename : JTAG_SIME2.v
// \ \ / \ Timestamp : Mon May 17 17:10:29 PDT 2010
// \___\/\___\
//
// Revision:
// 05/17/10 - Initial version.
// 11/30/11 - 632642 - Updated supported devices and corresponding IDCODES.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/05/12 - Updated the simulation model (CR 667100).
// 07/23/12 - Fixed IRLengthMax (CR 669116).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module JTAG_SIME2( TDO, TCK, TDI, TMS);
output TDO;
input TCK, TDI, TMS;
reg TDO;
reg notifier;
parameter PART_NAME = "7A8";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
localparam TestLogicReset = 4'h0,
RunTestIdle = 4'h1,
SelectDRScan = 4'h2,
CaptureDR = 4'h3,
ShiftDR = 4'h4,
Exit1DR = 4'h5,
PauseDR = 4'h6,
Exit2DR = 4'h7,
UpdateDR = 4'h8,
SelectIRScan = 4'h9,
CaptureIR = 4'ha,
ShiftIR = 4'hb,
Exit1IR = 4'hc,
PauseIR = 4'hd,
Exit2IR = 4'he,
UpdateIR = 4'hf;
localparam DELAY_SIG = 1;
reg TRST = 0;
reg [3:0] CurrentState = TestLogicReset;
reg [14*8:0] jtag_state_name = "TestLogicReset";
reg [14*8:0] jtag_instruction_name = "IDCODE";
//----------------- Virtex4 Specific Constants ---------
// localparam IRLengthMax = 10;
localparam IRLengthMax = 24;
localparam IDLength = 32;
reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 24'b010001010001010001010001,
BYPASS_INSTR = 24'b111111111111111111111111,
IDCODE_INSTR = 24'b001001001001001001001001,
USER1_INSTR = 24'b000010100100100100100100,
USER2_INSTR = 24'b000011100100100100100100,
USER3_INSTR = 24'b100010100100100100100100,
USER4_INSTR = 24'b100011100100100100100100;
// localparam IRLength = 10;
localparam IRLength = (
(PART_NAME == "7A8") || (PART_NAME == "7a8") ||
(PART_NAME == "7A15") || (PART_NAME == "7a15") ||
(PART_NAME == "7A20") || (PART_NAME == "7a20") ||
(PART_NAME == "7A30T") || (PART_NAME == "7a30t") ||
(PART_NAME == "7A50T") || (PART_NAME == "7a50t") ||
(PART_NAME == "7A100T") || (PART_NAME == "7a100t") ||
(PART_NAME == "7A200T") || (PART_NAME == "7a200t") ||
(PART_NAME == "7A350T") || (PART_NAME == "7a350t") ||
(PART_NAME == "7K30T") || (PART_NAME == "7k30t") ||
(PART_NAME == "7K70T") || (PART_NAME == "7k70t") ||
(PART_NAME == "7K125T") || (PART_NAME == "7k125t") ||
(PART_NAME == "7K160T") || (PART_NAME == "7k160t") ||
(PART_NAME == "7K235T") || (PART_NAME == "7k235t") ||
(PART_NAME == "7K290T") || (PART_NAME == "7k290t") ||
(PART_NAME == "7K325T") || (PART_NAME == "7k325t") ||
(PART_NAME == "7K355T") || (PART_NAME == "7k355t")) ? 6 : (
(PART_NAME == "7K410T") || (PART_NAME == "7k410t") ||
(PART_NAME == "7K420T") || (PART_NAME == "7k420t") ||
(PART_NAME == "7K480T") || (PART_NAME == "7k480t") ||
(PART_NAME == "7V160T") || (PART_NAME == "7v160t") ||
(PART_NAME == "7V450T") || (PART_NAME == "7v450t") ||
(PART_NAME == "7V585T") || (PART_NAME == "7v585t") ||
(PART_NAME == "7V855T") || (PART_NAME == "7v855t") ||
(PART_NAME == "7VX80T") || (PART_NAME == "7vx80t") ||
(PART_NAME == "7VX82T") || (PART_NAME == "7vx82t") ||
(PART_NAME == "7VX330T") || (PART_NAME == "7vx330t") ||
(PART_NAME == "7VX410T") || (PART_NAME == "7vx410t") ||
(PART_NAME == "7VX415T") || (PART_NAME == "7vx415t") ||
(PART_NAME == "7VX485T") || (PART_NAME == "7vx485t") ||
(PART_NAME == "7VX550T") || (PART_NAME == "7vx550t") ||
(PART_NAME == "7VX690T") || (PART_NAME == "7vx690t") ||
(PART_NAME == "7VX980T") || (PART_NAME == "7vx980t")) ? 18 : (
(PART_NAME == "7VX1140") || (PART_NAME == "7vx1140") ||
(PART_NAME == "7V1500") || (PART_NAME == "7v1500") ||
(PART_NAME == "7V2000") || (PART_NAME == "7v2000")) ? 24 : (
(PART_NAME == "7Z010") || (PART_NAME == "7z010") ||
(PART_NAME == "7Z020") || (PART_NAME == "7z020") ||
(PART_NAME == "7Z030") || (PART_NAME == "7z030") ||
(PART_NAME == "7Z045") || (PART_NAME == "7z045")) ? 6 : 24 ;
//----------------- local reg -------------------------------
reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0;
reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0;
reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig;
reg [IRLength-1:0] IRcontent_sig;
reg [IDLength-1:0] IDCODEval_sig;
reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0,
USER1_sig = 0, USER2_sig = 0,
USER3_sig = 0, USER4_sig = 0;
reg TDO_latch;
reg Tlrst_sig = 1;
reg TlrstN_sig = 1;
reg IRegLastBit_sig = 0, IDregLastBit_sig = 0;
reg Rti_sig = 0;
//-------------------------------------------------------------
reg [IRLength-1:0] NextIRreg;
reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ;
reg [IDLength-1:0] IDreg;
//####################################################################
//##### Initialize #####
//####################################################################
initial begin
case (PART_NAME)
"7A8", "7a8" : IDCODEval_sig <= 32'h03628093;
"7A15", "7a15" : IDCODEval_sig <= 32'h03627093;
"7A20", "7a20" : IDCODEval_sig <= 32'h03622093;
"7A30T", "7a30t" : IDCODEval_sig <= 32'h0362D093;
"7A50T", "7a50t" : IDCODEval_sig <= 32'h0362C093;
"7A100T", "7a100t" : IDCODEval_sig <= 32'h03631093;
"7A200T", "7a200t" : IDCODEval_sig <= 32'h03636093;
"7A350T", "7a350t" : IDCODEval_sig <= 32'h0363B093;
"7K30T", "7k30t" : IDCODEval_sig <= 32'h03642093;
"7K70T", "7k70t" : IDCODEval_sig <= 32'h03647093;
"7K125T", "7k125t" : IDCODEval_sig <= 32'h0365C093;
"7K160T", "7k160t" : IDCODEval_sig <= 32'h0364C093;
"7K235T", "7k235t" : IDCODEval_sig <= 32'h0365B093;
"7K290T", "7k290t" : IDCODEval_sig <= 32'h0365D093;
"7K325T", "7k325t" : IDCODEval_sig <= 32'h03651093;
"7K355T", "7k355t" : IDCODEval_sig <= 32'h03747093;
"7K410T", "7k410t" : IDCODEval_sig <= 32'h03656093;
"7K420T", "7k420t" : IDCODEval_sig <= 32'h03752093;
"7K480T", "7k480t" : IDCODEval_sig <= 32'h03751093;
"7V160T", "7v160t" : IDCODEval_sig <= 32'h03662093;
"7V450T", "7v450t" : IDCODEval_sig <= 32'h0366C093;
"7V585T", "7v585t" : IDCODEval_sig <= 32'h03671093;
"7V855T", "7v855t" : IDCODEval_sig <= 32'h03676093;
"7VX80T", "7vx80t" : IDCODEval_sig <= 32'h03680093;
"7VX82T", "7vx82t" : IDCODEval_sig <= 32'h03681093;
"7VX330T", "7vx330t" : IDCODEval_sig <= 32'h03667093;
"7VX410T", "7vx410t" : IDCODEval_sig <= 32'h0369B093;
"7VX415T", "7vx415t" : IDCODEval_sig <= 32'h03682093;
"7VX485T", "7vx485t" : IDCODEval_sig <= 32'h03687093;
"7VX550T", "7vx550t" : IDCODEval_sig <= 32'h03692093;
"7VX690T", "7vx690t" : IDCODEval_sig <= 32'h03691093;
"7VX980T", "7vx980t" : IDCODEval_sig <= 32'h03696093;
"7VX1140", "7vx1140" : IDCODEval_sig <= 32'h036D5093;
"7V1500", "7v1500" : IDCODEval_sig <= 32'h036B1093;
"7V2000", "7v2000" : IDCODEval_sig <= 32'h036B3093;
"7Z010", "7z010" : IDCODEval_sig <= 32'h03722093;
"7Z020", "7z020" : IDCODEval_sig <= 32'h03727093;
"7Z030", "7z030" : IDCODEval_sig <= 32'h0372C093;
"7Z045", "7z045" : IDCODEval_sig <= 32'h03731093;
default : begin
$display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIME2 instance %m is set to %s. The legal values for this attributes are 7A8, 7A15, 7A20, 7A30T, 7A50T, 7A100T, 7A200T, 7A350T, 7K30T, 7K70T, 7K125T, 7K160T, 7K235T, 7K290T, 7K325T, 7K355T, 7K410T, 7K420T, 7K480T, 7V160T, 7V450T, 7V585T, 7V855T, 7VX80T, 7VX82T, 7VX330T, 7VX410T, 7VX415T, 7VX485T, 7VX550T, 7VX690T, 7VX980T, 7VX1140, 7V1500, 7V2000, 7Z010, 7Z020, 7Z030 or 7Z045.", PART_NAME);
end
endcase // case(PART_NAME)
ir_int <= IR_CAPTURE_VAL[IRLength-1:0];
end // initial begin
//####################################################################
//##### JtagTapSM #####
//####################################################################
always@(posedge TCK or posedge TRST)
begin
if(TRST) begin
CurrentState = TestLogicReset;
end
else begin
case(CurrentState)
TestLogicReset:
begin
if(TMS == 0) begin
CurrentState = RunTestIdle;
jtag_state_name = "RunTestIdle";
end
end
RunTestIdle:
begin
if(TMS == 1) begin
CurrentState = SelectDRScan;
jtag_state_name = "SelectDRScan";
end
end
//-------------------------------
// ------ DR path ---------------
// -------------------------------
SelectDRScan:
begin
if(TMS == 0) begin
CurrentState = CaptureDR;
jtag_state_name = "CaptureDR";
end
else if(TMS == 1) begin
CurrentState = SelectIRScan;
jtag_state_name = "SelectIRScan";
end
end
CaptureDR:
begin
if(TMS == 0) begin
CurrentState = ShiftDR;
jtag_state_name = "ShiftDR";
end
else if(TMS == 1) begin
CurrentState = Exit1DR;
jtag_state_name = "Exit1DR";
end
end
ShiftDR:
begin
if(IRcontent_sig == BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
BypassReg = TDI;
if(TMS == 1) begin
CurrentState = Exit1DR;
jtag_state_name = "Exit1DR";
end
end
Exit1DR:
begin
if(TMS == 0) begin
CurrentState = PauseDR;
jtag_state_name = "PauseDR";
end
else if(TMS == 1) begin
CurrentState = UpdateDR;
jtag_state_name = "UpdateDR";
end
end
PauseDR:
begin
if(TMS == 1) begin
CurrentState = Exit2DR;
jtag_state_name = "Exit2DR";
end
end
Exit2DR:
begin
if(TMS == 0) begin
CurrentState = ShiftDR;
jtag_state_name = "ShiftDR";
end
else if(TMS == 1) begin
CurrentState = UpdateDR;
jtag_state_name = "UpdateDR";
end
end
UpdateDR:
begin
if(TMS == 0) begin
CurrentState = RunTestIdle;
jtag_state_name = "RunTestIdle";
end
else if(TMS == 1) begin
CurrentState = SelectDRScan;
jtag_state_name = "SelectDRScan";
end
end
//-------------------------------
// ------ IR path ---------------
// -------------------------------
SelectIRScan:
begin
if(TMS == 0) begin
CurrentState = CaptureIR;
jtag_state_name = "CaptureIR";
end
else if(TMS == 1) begin
CurrentState = TestLogicReset;
jtag_state_name = "TestLogicReset";
end
end
CaptureIR:
begin
if(TMS == 0) begin
CurrentState = ShiftIR;
jtag_state_name = "ShiftIR";
end
else if(TMS == 1) begin
CurrentState = Exit1IR;
jtag_state_name = "Exit1IR";
end
end
ShiftIR:
begin
// ClkIR_sig = 1;
if(TMS == 1) begin
CurrentState = Exit1IR;
jtag_state_name = "Exit1IR";
end
end
Exit1IR:
begin
if(TMS == 0) begin
CurrentState = PauseIR;
jtag_state_name = "PauseIR";
end
else if(TMS == 1) begin
CurrentState = UpdateIR;
jtag_state_name = "UpdateIR";
end
end
PauseIR:
begin
if(TMS == 1) begin
CurrentState = Exit2IR;
jtag_state_name = "Exit2IR";
end
end
Exit2IR:
begin
if(TMS == 0) begin
CurrentState = ShiftIR;
jtag_state_name = "ShiftIR";
end
else if(TMS == 1) begin
CurrentState = UpdateIR;
jtag_state_name = "UpdateIR";
end
end
UpdateIR:
begin
//-- FP
// ClkIR_sig = 1;
if(TMS == 0) begin
CurrentState = RunTestIdle;
jtag_state_name = "RunTestIdle";
end
else if(TMS == 1) begin
CurrentState = SelectDRScan;
jtag_state_name = "SelectDRScan";
end
end
endcase // case(CurrentState)
end // else
end // always
//--------------------------------------------------------
always@(CurrentState, TCK, TRST)
begin
ClkIR_sig = 1;
if(TRST == 1 ) begin
Tlrst_sig = #DELAY_SIG 1;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
else if(TRST == 0) begin
case (CurrentState)
TestLogicReset: begin
Tlrst_sig = #DELAY_SIG 1;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
RunTestIdle: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 1;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
CaptureDR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 1;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
ShiftDR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 1;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
UpdateDR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 1;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
CaptureIR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
ClkIR_sig = TCK;
end
ShiftIR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 1;
UpdateIR_sig = #DELAY_SIG 0;
ClkIR_sig = TCK;
end
UpdateIR: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 1;
end
default: begin
Tlrst_sig = #DELAY_SIG 0;
Rti_sig = #DELAY_SIG 0;
CaptureDR_sig = #DELAY_SIG 0;
ShiftDR_sig = #DELAY_SIG 0;
UpdateDR_sig = #DELAY_SIG 0;
ShiftIR_sig = #DELAY_SIG 0;
UpdateIR_sig = #DELAY_SIG 0;
end
endcase
end
end // always(CurrentState)
//-----------------------------------------------------
always@(TCK)
begin
// ClkIR_sig = ShiftIR_sig & TCK;
ClkUpdateIR_sig = UpdateIR_sig & ~TCK;
end // always
always@(TCK)
begin
ClkID_sig = IDCODE_sig & TCK;
end // always
// RESET
always@(Tlrst_sig)
begin
glbl.JTAG_RESET_GLBL <= Tlrst_sig;
end
// RUNTEST
always@(Rti_sig)
begin
glbl.JTAG_RUNTEST_GLBL <= Rti_sig;
end
//-------------- TCK NEGATIVE EDGE activities ----------
always@(negedge TCK, negedge UpdateDR_sig)
begin
if(TCK == 0) begin
glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig;
glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig;
TlrstN_sig <= Tlrst_sig;
end
glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig;
end // always
//--####################################################################
//--##### JtagIR #####
//--####################################################################
always@(posedge ClkIR_sig) begin
NextIRreg = {TDI, ir_int[IRLength-1:1]};
if ((TRST== 0) && (TlrstN_sig == 0)) begin
if(ShiftIR_sig == 1) begin
ir_int = NextIRreg;
IRegLastBit_sig = ir_int[0];
end
else begin
ir_int = IR_CAPTURE_VAL;
IRegLastBit_sig = ir_int[0];
end
end
end //always
//--------------------------------------------------------
always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or
posedge TRST) begin
if ((TRST== 1) || (TlrstN_sig == 1)) begin
IRcontent_sig = IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)];
IRegLastBit_sig = ir_int[0];
end
else if( (TRST == 0) && (TlrstN_sig == 0)) begin
IRcontent_sig = ir_int;
end
end //always
//--####################################################################
//--##### JtagDecodeIR #####
//--####################################################################
always@(IRcontent_sig) begin
case(IRcontent_sig)
// IR_CAPTURE_VAL : begin
// ;
// jtag_instruction_name = "IR_CAPTURE";
// end
BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "BYPASS";
// if BYPASS instruction, set BYPASS signal to 1
BYPASS_sig <= 1;
IDCODE_sig <= 0;
USER1_sig <= 0;
USER2_sig <= 0;
USER3_sig <= 0;
USER4_sig <= 0;
end
IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "IDCODE";
// if IDCODE instruction, set IDCODE signal to 1
BYPASS_sig <= 0;
IDCODE_sig <= 1;
USER1_sig <= 0;
USER2_sig <= 0;
USER3_sig <= 0;
USER4_sig <= 0;
end
USER1_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "USER1";
// if USER1 instruction, set USER1 signal to 1
BYPASS_sig <= 0;
IDCODE_sig <= 0;
USER1_sig <= 1;
USER2_sig <= 0;
USER3_sig <= 0;
USER4_sig <= 0;
end
USER2_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "USER2";
// if USER2 instruction, set USER2 signal to 1
BYPASS_sig <= 0;
IDCODE_sig <= 0;
USER1_sig <= 0;
USER2_sig <= 1;
USER3_sig <= 0;
USER4_sig <= 0;
end
USER3_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "USER3";
// if USER3 instruction, set USER3 signal to 1
BYPASS_sig <= 0;
USER1_sig <= 0;
USER2_sig <= 0;
IDCODE_sig <= 0;
USER3_sig <= 1;
USER4_sig <= 0;
end
USER4_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)] : begin
jtag_instruction_name = "USER4";
// if USER4 instruction, set USER4 signal to 1
BYPASS_sig <= 0;
IDCODE_sig <= 0;
USER1_sig <= 0;
USER2_sig <= 0;
USER3_sig <= 0;
USER4_sig <= 1;
end
default : begin
jtag_instruction_name = "UNKNOWN";
// if UNKNOWN instruction, set all signals to 0
BYPASS_sig <= 0;
IDCODE_sig <= 0;
USER1_sig <= 0;
USER2_sig <= 0;
USER3_sig <= 0;
USER4_sig <= 0;
end
endcase
end //always
//--####################################################################
//--##### JtagIDCODE #####
//--####################################################################
always@(posedge ClkID_sig) begin
// reg [(IDLength -1) : 0] IDreg;
if(ShiftDR_sig == 1) begin
IDreg = IDreg >> 1;
IDreg[IDLength -1] = TDI;
end
else
IDreg = IDCODEval_sig;
IDregLastBit_sig = IDreg[0];
end // always
//--####################################################################
//--##### JtagSetGlobalSignals #####
//--####################################################################
always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin
if(Tlrst_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= 0;
glbl.JTAG_SEL2_GLBL <= 0;
glbl.JTAG_SEL3_GLBL <= 0;
glbl.JTAG_SEL4_GLBL <= 0;
end
else if(Tlrst_sig == 0) begin
if(USER1_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= USER1_sig;
glbl.JTAG_SEL2_GLBL <= 0;
glbl.JTAG_SEL3_GLBL <= 0;
glbl.JTAG_SEL4_GLBL <= 0;
end
else if(USER2_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= 0;
glbl.JTAG_SEL2_GLBL <= 1;
glbl.JTAG_SEL3_GLBL <= 0;
glbl.JTAG_SEL4_GLBL <= 0;
end
else if(USER3_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= 0;
glbl.JTAG_SEL2_GLBL <= 0;
glbl.JTAG_SEL3_GLBL <= 1;
glbl.JTAG_SEL4_GLBL <= 0;
end
else if(USER4_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= 0;
glbl.JTAG_SEL2_GLBL <= 0;
glbl.JTAG_SEL3_GLBL <= 0;
glbl.JTAG_SEL4_GLBL <= 1;
end
else if(ClkUpdateIR_sig == 1) begin
glbl.JTAG_SEL1_GLBL <= 0;
glbl.JTAG_SEL2_GLBL <= 0;
glbl.JTAG_SEL3_GLBL <= 0;
glbl.JTAG_SEL4_GLBL <= 0;
end
end
end //always
//--####################################################################
//--##### OUTPUT #####
//--####################################################################
assign glbl.JTAG_TDI_GLBL = TDI;
assign glbl.JTAG_TCK_GLBL = TCK;
assign glbl.JTAG_TMS_GLBL = TMS;
always@(CurrentState, IRcontent_sig, BypassReg,
IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL,
glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL,
glbl.JTAG_USER_TDO4_GLBL)
begin
case (CurrentState)
ShiftIR: begin
TDO_latch <= IRegLastBit_sig;
end
ShiftDR: begin
if(IRcontent_sig == IDCODE_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= IDregLastBit_sig;
else if(IRcontent_sig == BYPASS_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= BypassReg;
else if(IRcontent_sig == USER1_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= glbl.JTAG_USER_TDO1_GLBL;
else if(IRcontent_sig == USER2_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= glbl.JTAG_USER_TDO2_GLBL;
else if(IRcontent_sig == USER3_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= glbl.JTAG_USER_TDO3_GLBL;
else if(IRcontent_sig == USER4_INSTR[IRLengthMax - 1 : (IRLengthMax - IRLength)])
TDO_latch <= glbl.JTAG_USER_TDO4_GLBL;
else
TDO_latch <= 1'bz;
end
default : begin
TDO_latch <= 1'bz;
end
endcase // case(PART_NAME)
end // always
always@(negedge TCK)
begin
// 213980 NCsim compile error fix
TDO <= # 6000 TDO_latch;
end // always
//--####################################################################
//--##### Timing #####
//--####################################################################
`ifdef XIL_TIMING
specify
// 213980 NCsim compile error fix
// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000);
$setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier);
$setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier);
$setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier);
$setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier);
endspecify
`endif // `ifdef XIL_TIMING
endmodule // JTAG_SIME2
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/KEEPER.v 0000664 0000000 0000000 00000002046 12327044266 0022377 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/KEEPER.v,v 1.5 2007/05/23 21:43:39 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Weak Keeper
// /___/ /\ Filename : KEEPER.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module KEEPER (O);
inout O;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
reg in;
always @(O)
if (O)
in <= 1;
else
in <= 0;
buf (pull1, pull0) B1 (O, in);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LDCE.v 0000664 0000000 0000000 00000014254 12327044266 0022137 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Transparent Data Latch with Asynchronous Clear and Gate Enable
// /___/ /\ Filename : LDCE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_G_INVERTED = 1'b0
)(
output Q,
input CLR,
input D,
input G,
input GE
);
wire D_dly, G_dly, GE_dly, CLR_dly;
wire G_in, CLR_in;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
`ifdef XIL_TIMING
wire ngsr, nrst, in_out;
wire in_clk_enable, ce_clk_enable, rst_clk_enable;
wire in_clk_enable1, ce_clk_enable1, rst_clk_enable1;
wire tl_enable, tl_enable1;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nrst, CLR_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nrst, GE_dly);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, GE_dly);
and (tl_enable, ngsr, nrst);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable1 = (MSGON =="FALSE") ? 1'b0 : tl_enable;
`else
assign notifier1 = 1'bx;
`endif
assign Q = q_out;
always @(GSR or CLR_in) begin
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
rst_int = CLR_in;
set_int = 0;
end
end
latchsre_ldce (o_out, G_in, D_dly, set_int, rst_int, GE_dly, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign G_dly = G;
assign GE_dly = GE;
assign CLR_dly = CLR;
assign D_dly = D;
`endif
assign G_in = IS_G_INVERTED ^ G_dly;
assign CLR_in = IS_CLR_INVERTED ^ CLR_dly;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(CLR => Q) = (0:0:0, 0:0:0);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
$recrem (negedge CLR, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,CLR_dly, G_dly);
$recrem (negedge CLR, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,CLR_dly, G_dly);
$recrem (posedge CLR, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,CLR_dly, G_dly);
$recrem (posedge CLR, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,CLR_dly, G_dly);
$setuphold (negedge G, negedge CLR, 0:0:0, 0:0:0, notifier,,, G_dly, CLR_dly);
$setuphold (negedge G, negedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (negedge G, negedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (negedge G, posedge CLR, 0:0:0, 0:0:0, notifier,,, G_dly, CLR_dly);
$setuphold (negedge G, posedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (negedge G, posedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (posedge G, negedge CLR, 0:0:0, 0:0:0, notifier,,, G_dly, CLR_dly);
$setuphold (posedge G, negedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (posedge G, negedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (posedge G, posedge CLR, 0:0:0, 0:0:0, notifier,,, G_dly, CLR_dly);
$setuphold (posedge G, posedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (posedge G, posedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$width (posedge G, 0:0:0, 0, notifier);
$width (negedge G, 0:0:0, 0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
$width (negedge CLR, 0:0:0, 0, notifier);
$period (posedge G, 0:0:0, notifier);
$period (negedge G, 0:0:0, notifier);
$recrem (negedge GE, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,GE_dly, G_dly);
$recrem (negedge GE, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,GE_dly, G_dly);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldce (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LDPE.v 0000664 0000000 0000000 00000013541 12327044266 0022152 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Transparent Data Latch with Asynchronous Preset and Gate Enable
// /___/ /\ Filename : LDPE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDPE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_PRE_INVERTED = 1'b0,
parameter [0:0] IS_G_INVERTED = 1'b0
)(
output Q,
input D,
input G,
input GE,
input PRE
);
wire D_dly, G_dly, GE_dly, PRE_dly;
wire G_in, PRE_in;
reg q_out = INIT;
reg notifier;
wire notifier1;
reg rst_int, set_int;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
wire ngsr, nset, in_out;
wire in_clk_enable, ce_clk_enable, rst_clk_enable;
wire in_clk_enable1, ce_clk_enable1, rst_clk_enable1;
wire tl_enable, tl_enable1;
not (nset, PRE_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nset, GE_dly);
and (ce_clk_enable, ngsr, nset, in_out);
and (rst_clk_enable, ngsr, GE_dly);
and (tl_enable, ngsr, nset);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : in_clk_enable;
assign ce_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_clk_enable;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable1 = (MSGON =="FALSE") ? 1'b0 : tl_enable;
`else
assign notifier1 = 1'bx;
`endif
assign Q = q_out;
always @(GSR or PRE_in) begin
if (GSR)
if (INIT) begin
set_int = 1;
rst_int = 0;
end
else begin
rst_int = 1;
set_int = 0;
end
else begin
rst_int = 0;
set_int = PRE_in;
end
end
latchsre_ldpe (o_out, G_in, D_dly, set_int, rst_int, GE_dly, notifier1);
always @(o_out)
q_out = o_out;
`ifndef XIL_TIMING
assign G_dly = G;
assign GE_dly = GE;
assign D_dly = D;
assign PRE_dly = PRE;
`endif
assign G_in = IS_G_INVERTED ^ G_dly;
assign PRE_in = IS_PRE_INVERTED ^ PRE_dly;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(PRE => Q) = (0:0:0, 0:0:0);
(negedge PRE *> (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE *> (Q +: 1)) = (0:0:0, 0:0:0);
$setuphold (negedge G, posedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (negedge G, negedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (negedge G, posedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (negedge G, negedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$recrem (negedge PRE, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,PRE_dly, G_dly);
$recrem (negedge GE, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,GE_dly, G_dly);
$period (posedge G, 0:0:0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (negedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
$width (posedge PRE, 0:0:0, 0, notifier);
$setuphold (posedge G, posedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (posedge G, negedge GE &&& ce_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,GE_dly);
$setuphold (posedge G, posedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$setuphold (posedge G, negedge D &&& in_clk_enable1, 0:0:0, 0:0:0, notifier,,,G_dly,D_dly);
$recrem (posedge PRE, negedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,PRE_dly, G_dly);
$recrem (negedge PRE, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,PRE_dly, G_dly);
$recrem (posedge PRE, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,PRE_dly, G_dly);
$recrem (negedge GE, posedge G &&& tl_enable1, 0:0:0, 0:0:0, notifier,,,GE_dly, G_dly);
$period (negedge G, 0:0:0, notifier);
$width (negedge PRE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldpe (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT1.v 0000664 0000000 0000000 00000003030 12327044266 0022143 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT1.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.60)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 1-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT1.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 05/12/11 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT1 (O, I0);
parameter INIT = 2'h0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0;
wire out, a0;
buf b0 (a0, I0);
x_lut1_mux2 (O, INIT[1], INIT[0], a0);
specify
(I0 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive x_lut1_mux2 (o, d1, d0, s0);
output o;
input d1, d0;
input s0;
table
// d1 d0 s0 : o;
? 1 0 : 1;
? 0 0 : 0;
1 ? 1 : 1;
0 ? 1 : 0;
0 0 x : 0;
1 1 x : 1;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT2.v 0000664 0000000 0000000 00000004111 12327044266 0022145 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT2.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 2-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT2.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT2 (O, I0, I1);
parameter INIT = 4'h0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1;
wire out, a0, a1;
buf b0 (a0, I0);
buf b1 (a1, I1);
x_lut2_mux4 (O, INIT[3], INIT[2], INIT[1], INIT[0], a1, a0);
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive x_lut2_mux4 (o, d3, d2, d1, d0, s1, s0);
output o;
input d3, d2, d1, d0;
input s1, s0;
table
// d3 d2 d1 d0 s1 s0 : o;
? ? ? 1 0 0 : 1;
? ? ? 0 0 0 : 0;
? ? 1 ? 0 1 : 1;
? ? 0 ? 0 1 : 0;
? 1 ? ? 1 0 : 1;
? 0 ? ? 1 0 : 0;
1 ? ? ? 1 1 : 1;
0 ? ? ? 1 1 : 0;
? ? 0 0 0 x : 0;
? ? 1 1 0 x : 1;
0 0 ? ? 1 x : 0;
1 1 ? ? 1 x : 1;
? 0 ? 0 x 0 : 0;
? 1 ? 1 x 0 : 1;
0 ? 0 ? x 1 : 0;
1 ? 1 ? x 1 : 1;
0 0 0 0 x x : 0;
1 1 1 1 x x : 1;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT3.v 0000664 0000000 0000000 00000004407 12327044266 0022156 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT3.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT3.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT3 (O, I0, I1, I2);
parameter INIT = 8'h00;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2;
wire out0, out1, a0, a1, a2;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
x_lut3_mux4 (out1, INIT[7], INIT[6], INIT[5], INIT[4], a1, a0);
x_lut3_mux4 (out0, INIT[3], INIT[2], INIT[1], INIT[0], a1, a0);
x_lut3_mux4 (O, 1'b0, 1'b0, out1, out0, 1'b0, a2);
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive x_lut3_mux4 (o, d3, d2, d1, d0, s1, s0);
output o;
input d3, d2, d1, d0;
input s1, s0;
table
// d3 d2 d1 d0 s1 s0 : o;
? ? ? 1 0 0 : 1;
? ? ? 0 0 0 : 0;
? ? 1 ? 0 1 : 1;
? ? 0 ? 0 1 : 0;
? 1 ? ? 1 0 : 1;
? 0 ? ? 1 0 : 0;
1 ? ? ? 1 1 : 1;
0 ? ? ? 1 1 : 0;
? ? 0 0 0 x : 0;
? ? 1 1 0 x : 1;
0 0 ? ? 1 x : 0;
1 1 ? ? 1 x : 1;
? 0 ? 0 x 0 : 0;
? 1 ? 1 x 0 : 1;
0 ? 0 ? x 1 : 0;
1 ? 1 ? x 1 : 1;
0 0 0 0 x x : 0;
1 1 1 1 x x : 1;
endtable
endprimitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT4.v 0000664 0000000 0000000 00000005143 12327044266 0022155 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT4.v,v 1.10 2007/06/05 00:00:54 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 4-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT4.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf.
// 03/11/05 - Add LOC paramter;
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT4 (O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2, I3;
wire a0, a1, a2, a3;
wire o_out_tmp;
reg o_out;
reg tmp;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
buf b3 (a3, I3);
buf b4 (O, o_out_tmp);
assign o_out_tmp = o_out;
always @( a3 or a2 or a1 or a0 ) begin
tmp = a0 ^ a1 ^ a2 ^ a3;
if ( tmp == 0 || tmp == 1)
o_out = INIT[{a3, a2, a1, a0}];
else
o_out = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {a1, a0}),
lut4_mux4 ( INIT[11:8], {a1, a0}),
lut4_mux4 ( INIT[7:4], {a1, a0}),
lut4_mux4 ( INIT[3:0], {a1, a0}) }, {a3, a2});
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] ^ d[1]) == 0 && (d[2] ^ d[3]) == 0 && (d[0] ^ d[2]) == 0)
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] == d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] == d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] == d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] == d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT5.v 0000664 0000000 0000000 00000010420 12327044266 0022150 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT5.v,v 1.11 2007/06/05 00:00:54 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 5-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT5.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace premitive with function; Remove buf.
// 01/07/06 - Add LOC Parameter (CR 222733)
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT5 (O, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2, I3, I4;
wire a0, a1, a2, a3, a4;
wire o_out_tmp;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
buf b3 (a3, I3);
buf b4 (a4, I4);
buf b5 (O, o_out_tmp);
reg o_out;
reg tmp;
assign o_out_tmp= o_out;
always @( a4 or a3 or a2 or a1 or a0 ) begin
tmp = a0 ^ a1 ^ a2 ^ a3 ^ a4;
if ( tmp == 0 || tmp == 1)
o_out = INIT[{a4, a3, a2, a1, a0}];
else
o_out = lut4_mux4 (
{ lut6_mux8 ( INIT[31:24], {a2, a1, a0}),
lut6_mux8 ( INIT[23:16], {a2, a1, a0}),
lut6_mux8 ( INIT[15:8], {a2, a1, a0}),
lut6_mux8 ( INIT[7:0], {a2, a1, a0}) }, { a4, a3});
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I4 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] ^ d[1]) == 0 && (d[2] ^ d[3]) == 0 && (d[0] ^ d[2]) == 0)
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] == d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] == d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] == d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] == d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT6.v 0000664 0000000 0000000 00000007730 12327044266 0022163 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT6.v,v 1.11 2007/06/05 00:00:54 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 6-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT6.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace premitive with function; Remove buf.
// 01/07/06 - Add LOC Parameter (CR 222733)
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT6 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2, I3, I4, I5;
wire a0, a1, a2, a3, a4, a5;
wire o_out_tmp;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
buf b3 (a3, I3);
buf b4 (a4, I4);
buf b5 (a5, I5);
buf b6 (O, o_out_tmp);
reg o_out;
reg tmp;
assign o_out_tmp = o_out;
always @( a5 or a4 or a3 or a2 or a1 or a0 ) begin
tmp = a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5;
if ( tmp == 0 || tmp == 1)
o_out = INIT[{a5, a4, a3, a2, a1, a0}];
else
o_out = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {a2, a1, a0}),
lut6_mux8 ( INIT[55:48], {a2, a1, a0}),
lut6_mux8 ( INIT[47:40], {a2, a1, a0}),
lut6_mux8 ( INIT[39:32], {a2, a1, a0}),
lut6_mux8 ( INIT[31:24], {a2, a1, a0}),
lut6_mux8 ( INIT[23:16], {a2, a1, a0}),
lut6_mux8 ( INIT[15:8], {a2, a1, a0}),
lut6_mux8 ( INIT[7:0], {a2, a1, a0}) }, {a5, a4, a3});
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I4 => O) = (0:0:0, 0:0:0);
(I5 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/LUT6_2.v 0000664 0000000 0000000 00000013021 12327044266 0022372 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/rainier/LUT6_2.v,v 1.4 2007/06/19 19:47:31 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.18)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 6-input Look-Up-Table with Two Outputs
// /___/ /\ Filename : LUT6_2.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 08/08/06 - Initial version.
// 06/04/07 - Change timescale form 100ps/10ps to 1ps/1ps.
// Add wire definition.
// 06/19/07 - Add LOC parameter (CR 441956).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
input I0, I1, I2, I3, I4, I5;
output O5, O6;
reg [63:0] init_reg = INIT;
reg [31:0] init_l, init_h;
reg O_l, O_h, tmp;
reg O5_o, O6_o;
wire I0_i, I1_i, I2_i, I3_i, I4_i, I5_i;
buf bo5 (O5, O5_o);
buf bo6 (O6, O6_o);
buf bi0 (I0_i, I0);
buf bi1 (I1_i, I1);
buf bi2 (I2_i, I2);
buf bi3 (I3_i, I3);
buf bi4 (I4_i, I4);
buf bi5 (I5_i, I5);
initial begin
init_l = init_reg[31:0];
init_h = init_reg[63:32];
end
always @(I5_i or O_l or O_h) begin
O5_o = O_l;
if (I5_i == 1)
O6_o = O_h;
else if (I5_i == 0)
O6_o = O_l;
else begin
if (O_h == 0 && O_l == 0)
O6_o = 1'b0;
else if (O_h == 1 && O_l == 1)
O6_o = 1'b1;
else
O6_o = 1'bx;
end
end
always @( I4_i or I3_i or I2_i or I1_i or I0_i ) begin
tmp = I0_i ^ I1_i ^ I2_i ^ I3_i ^ I4_i;
if ( tmp == 0 || tmp == 1) begin
O_l = init_l[{I4_i, I3_i, I2_i, I1_i, I0_i}];
O_h = init_h[{I4_i, I3_i, I2_i, I1_i, I0_i}];
end
else begin
O_l = lut4_mux4 (
{ lut6_mux8 ( init_l[31:24], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[23:16], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[15:8], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[7:0], {I2_i, I1_i, I0_i}) }, { I4_i, I3_i});
O_h = lut4_mux4 (
{ lut6_mux8 ( init_h[31:24], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[23:16], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[15:8], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[7:0], {I2_i, I1_i, I0_i}) }, { I4_i, I3_i});
end
end
specify
(I0 => O5) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I5 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
(I5 => O6) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) )
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MASTER_JTAG.v 0000664 0000000 0000000 00000002026 12327044266 0023222 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : MASTER_JTAG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06/17/13 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MASTER_JTAG
`ifdef XIL_TIMING //Simprim adding LOC only
#(
parameter LOC = "UNPLACED"
)
`endif
(
output TDO,
input TCK,
input TDI,
input TMS
);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MMCME2_ADV.v 0000664 0000000 0000000 00000437326 12327044266 0023053 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Phase Lock Loop Clock
// /___/ /\ Filename : MMCME2_ADV.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 07/07/08 - Initial version.
// 09/19/08 - Change CLKFBOUT_MULT to CLKFBOUT_MULT_F
// CLKOUT0_DIVIDE to CLKOUT0_DIVIDE_F
// 10/03/08 - Initial all signals.
// 10/30/08 - Clock source switching without reset (CR492263).
// 11/18/08 - Add timing check for DADDR[6:5].
// 12/02/08 - Fix bug of Duty cycle calculation (CR498696)
// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137)
// 12/09/08 - Enable output at CLKFBOUT_MULT_F*8 for fraction mode (CR499322)
// 01/08/09 - Add phase and duty cycle checks for fraction divide (CR501181)
// 01/09/09 - make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137)
// 01/14/09 - Fine phase shift wrap around to 0 after 56 times;
// - PSEN to PSDONE change to 12 PSCLK; RST minpusle to 5ns;
// - add pulldown to PWRDWN pin. (CR503425)
// 01/14/09 - increase clkout_en_time for fraction mode (CR499322)
// 01/21/09 - align CLKFBOUT to CLKIN for fraction mode (CR504602)
// 01/27/09 - update DRP register address (CR505271)
// 01/28/09 - assign clkout_en0 and clkout_en1 to 0 when RST=1 (CR505767)
// 02/03/09 - Fix bug in clkfb fine phase shift.
// - Add delay to clkout_en0_tmp (CR506530).
// 02/05/09 - Add ps_in_ps calculation to clkvco_delay when clkfb_fps_en=1.
// - round clk_ht clk_lt for duty_cycle (CR506531)
// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1601 and 399 to cover the rounded
// error (CR507969)
// 02/25/09 - round clk_ht clk_lt for duty_cycle (509386)
// 02/26/09 - Fix for clkin and clkfbin stop case (CR503425)
// 03/04/09 - Fix for CLOCK_HOLD (CR510820).
// 03/27/09 - set default 1 to CLKINSEL pin (CR516951)
// 04/13/09 - Check vco reange when CLKINSEL not connected (CR516951)
// 04/22/09 - Add reset to clkinstopped related signals (CR519102)
// 04/27/09 - Make duty cycle of fraction mode 50/50 (CR519505)
// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120)
// 07/23/09 - fix bug in clkout0_dly (CR527643)
// 07/27/09 - Do divide when period_avg > 0 (CR528090)
// - Change DIVCLK_DIVIDE to 80 (CR525904)
// - Add initial lock setting (CR524523)
// - Update RES CP setting (CR524522)
// 07/31/09 - Add if else to handle the fracion and nonfraction for clkout_en.
// 08/10/09 - Calculate clkin_lost_val after lock_period=1 (CR528520).
// 08/15/09 - Update LFHF (CR524522)
// 08/19/09 - Set clkfb_lost_val initial value (CR531354)
// 08/28/09 - add clkin_period_tmp_t to handle period_avg calculation
// when clkin has jitter (CR528520)
// 09/11/09 - Change CLKIN_FREQ_MIN to 10 Mhz (CR532774)
// 10/01/09 - Change CLKIN_FREQ_MAX to 800Mhz (CR535076)
// Add reset check for clock switchover (CR534900)
// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ
// MAX & MIN to parameter (CR535828)
// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662)
// 10/22/09 - Add period_vco_mf for clkvco_delay calculation (CR536951)
// Add cmpvco to compensate period_vco rounded error (CR537073)
// 12/02/09 - not stop clkvco_lk when jitter (CR538717)
// 01/08/10 - Change minimum RST pulse width from 5 ns to 1.5 ns
// Add 1 ns delay to locked_out_tmp when RST=1 (CR543857)
// 01/19/10 - make change to clkvoc_lk_tmp to handle M=1 case (CR544970)
// 02/09/10 - Add global PLL_LOCKG (CR547918)
// 02/23/10 - Not use edge for locked_out_tmp (CR549667)
// 03/04/10 - Change CLKFBOUT_MULT_F range to 5-64 (CR551618)
// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618)
// 03/24/10 - Add SIM_DEVICE attribute
// 04/07/10 - Generate clkvco_ps_tmp2_en correctly when ps_lock_dly rising
// and clkout_ps=1 case; increase lock_period time to 10 (CR556468)
// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966)
// 07/28/10 - Update ref parameter values (CR569260)
// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324)
// 09/03/10 - use %f for M_MIN and M_MAX (CR574247)
// 09/09/10 - Change to bus timing.
// 09/26/10 - Add RST to LOCKED timing path (CR567807)
// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003)
// 03/08/11 - Support fraction mode phase shifting with phase parameter
// setting (CR596402)
// 04/26/11 - Support fraction mode phase shifting with DRP(CR607989)
// 05/24/11 - Set frac_wf_f to 1 when divide=2.125 (CR611840)
// 06/06/11 - set period_vco_half_rm2 to 0 when period_vco=0 (CR613021)
// 06/08/11 - Disable clk0 fraction mode when CLKOUT0_DIVIDE_F in range
// greater than 1 and less than 2. Add DRC check for it (608893)
// 08/03/11 - use clk0_frac instead of clk0_sfrac (CR 618600)
// 10/26/11 - Add spectrum attributes. Add DRC check for samples CLKIN
// period with parameter setting (CR631150)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/22/12 - Modify DRC (638094).
// 03/01/12 - fraction enable for m/d (CR 648429)
// 03/07/12 - added vcoflag (CR 638088, CR 636493)
// 04/19/12 - 654951 - rounding issue with clk_out_para_cal
// 05/03/12 - ncsim issue with clkfb_frac_en (CR 655792)
// 05/03/12 - jittery clock (CR 652401)
// 05/03/12 - incorrect period (CR 654951)
// 05/10/12 - fractional divide calculation issue (CR 658151)
// 05/18/12 - fractional divide calculation issue (CR 660657)
// 06/11/12 - update cp and res settings (CR 664278)
// 06/20/12 - modify reset drc (CR 643540)
// 09/06/12 - 655711 - modify displayed MAX on CLK_DUTY_CYCLE
// 12/12/12 - fix clk_osc process for ncsim (CR 676829)
// 04/04/13 - fix clkvco_frac_en for DRP (CR 709093)
// 04/09/13 - Added DRP monitor (CR 695630).
// 05/03/13 - 670208 Fractional clock alignment issue
// 05/31/13 - 720783 - revert clock alignment fix
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_ADV # (
`ifdef XIL_TIMING
parameter real VCOCLK_FREQ_MAX = 1600.0,
parameter real VCOCLK_FREQ_MIN = 600.0,
parameter real CLKIN_FREQ_MAX = 1066.0,
parameter real CLKIN_FREQ_MIN = 10.0,
parameter real CLKPFD_FREQ_MAX = 550.0,
parameter real CLKPFD_FREQ_MIN = 10.0,
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter CLKFBOUT_USE_FINE_PS = "FALSE",
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter CLKOUT0_USE_FINE_PS = "FALSE",
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUT1_USE_FINE_PS = "FALSE",
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter CLKOUT6_USE_FINE_PS = "FALSE",
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PSEN_INVERTED = 1'b0,
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter integer SS_MOD_PERIOD = 10000,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKFBSTOPPED,
output CLKINSTOPPED,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output [15:0] DO,
output DRDY,
output LOCKED,
output PSDONE,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PSCLK,
input PSEN,
input PSINCDEC,
input PWRDWN,
input RST
);
`ifndef XIL_TIMING
localparam real VCOCLK_FREQ_MAX = 1600.0;
localparam real VCOCLK_FREQ_MIN = 600.0;
localparam real CLKIN_FREQ_MAX = 1066.0;
localparam real CLKIN_FREQ_MIN = 10.0;
localparam real CLKPFD_FREQ_MAX = 550.0;
localparam real CLKPFD_FREQ_MIN = 10.0;
`endif //
localparam MODULE_NAME = "MMCME2_ADV";
localparam VCOCLK_FREQ_TARGET = 1000;
localparam M_MIN = 2.000;
localparam M_MAX = 64.000;
localparam D_MIN = 1;
localparam D_MAX = 106;
localparam O_MIN = 1;
localparam O_MAX = 128;
localparam O_MAX_HT_LT = 64;
localparam REF_CLK_JITTER_MAX = 1000;
localparam REF_CLK_JITTER_SCALE = 0.1;
localparam MAX_FEEDBACK_DELAY = 10.0;
localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
localparam ps_max = 55;
localparam OSC_P2 = 250;
real CLKOUT0_DIVIDE_F_RND;
real CLKFBOUT_MULT_F_RND;
tri0 GSR = glbl.GSR;
tri1 p_up;
wire glock;
integer pchk_tmp1, pchk_tmp2;
integer clkfb_div_frac_int, clk0_div_frac_int, clkfb_div_fint, clk0_div_fint, clkvco_div_fint;
integer clkfb_div_fint_tmp1, clkfb_div_fint_odd;
integer clk0_div_fint_tmp1, clk0_div_fint_odd;
real clkfb_div_frac, clk0_div_frac, clkvco_div_frac, clkfb_div_check, clkfb_div_check_diff, clk0_div_check, clk0_div_check_diff;
reg clk0_frac_out, clkfbm1_frac_out;
reg clk0_nf_out, clkfbm1_nf_out;
integer clk0_frac_en;
integer clkfb_frac_en;
integer clkfb_div_check_int, clk0_div_check_int, clkfb_div_adj, clk0_div_adj;
integer clkvco_frac_en;
integer ps_in_init;
reg psdone_out, psdone_out1;
integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en;
integer clk5_fps_en, clk6_fps_en, clkfb_fps_en, fps_en;
reg clkinstopped_out;
reg clkin_hold_f = 0;
reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0;
integer period_avg_stpi = 0, period_avg_stp = 0;
real tmp_stp1, tmp_stp2;
reg pd_stp_p = 0;
reg vco_stp_f = 0;
reg psen_w = 0;
reg clkinstopped_out_dly = 0;
reg clkinstopped_out1 = 0;
reg clkfbstopped_out1 = 0;
reg clkfb_stop_tmp, clkfbstopped_out, clkin_stop_tmp;
reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0;
reg rst_clkinstopped_rc = 0;
reg rst_clkinstopped_lk, rst_clkfbstopped_lk;
integer clkin_lost_cnt, clkfb_lost_cnt;
reg clkinstopped_hold = 0;
integer ps_in_ps, ps_cnt;
integer ps_in_ps_neg, ps_cnt_neg;
reg clkout_ps, clkout_ps_tmp1, clkout_ps_tmp2;
time clkout_ps_eg = 0;
time clkout_ps_peg = 0;
time clkout_ps_w = 0;
reg clkvco_ps_tmp1, clkvco_ps_tmp2;
reg clkvco_ps_tmp2_en;
integer clkout4_cascade_int;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drdy_out, drdy_out1;
reg drp_lock;
integer drp_lock_lat = 4;
integer drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [160:0] tmp_string;
reg rst_in;
reg pwron_int;
wire orig_rst_in,rst_in_o;
wire locked_out;
reg locked_out1;
reg locked_out_tmp;
wire clk0_out, clkfbm1_out;
reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out;
reg clkfb_out;
reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1;
integer clkout_en_val, clkout_en_t;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
reg clkvco_lk_osc, clkvco, clkvco_lk_tmp, clkvco_lk_tmp_en;
reg clkvco_ps_tmp2_pg;
reg clkvco_lk_dly_tmp;
reg clkvco_lk_en;
reg clkvco_lk;
reg fbclk_tmp;
reg clk_osc, clkin_p, clkfb_p;
reg clkinstopped_vco_f;
time rst_edge, rst_ht;
reg fb_delay_found, fb_delay_found_tmp;
reg clkfb_tst;
real fb_delay_max;
time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay, fbm1_comp_delay_tmp;
time dly_tmp1, tmp_ps_val2;
integer dly_tmp_int, tmp_ps_val1;
time clkin_edge, delay_edge;
real period_clkin, clkin_period_tmp;
integer clkin_period_tmp_t;
integer clkin_period [4:0];
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
real period_vco_rl;
integer period_vco_half_rm1, period_vco_half_rm2;
real cmpvco = 0.0;
real clkvco_pdrm;
integer period_vco_mf;
integer period_vco_tmp;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco_max, period_vco_min;
integer period_vco1, period_vco2, period_vco3, period_vco4;
integer period_vco5, period_vco6, period_vco7;
integer period_vco_target, period_vco_target_half;
integer period_fb, period_avg;
integer clk0_frac_lt, clk0_frac_ht;
integer clkfb_frac_lt, clkfb_frac_ht;
integer period_ps, period_ps_old;
reg ps_lock, ps_lock_dly;
real clkvco_freq_init_chk, clkfbm1pm_rl;
real tmp_real;
integer ik0, ik1, ik2, ik3, ik4, ib, i, j;
integer md_product, m_product, m_product2, clkin_stop_max, clkfb_stop_max;
integer mf_product, clk0f_product;
integer clkin_lost_val, clkfb_lost_val, clkin_lost_val_lk;
time pll_locked_delay, clkin_dly_t, clkfb_dly_t;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2;
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock;
integer clkin_jit, REF_CLK_JITTER_MAX_tmp;
wire init_trig, clkpll_r, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clk6in;
reg clkpll_tmp1, clkpll;
wire clkfbm1in, clkfbm1ps_en;
reg chk_ok;
wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en;
reg [7:0] clkout_mux, clkout_ps_mux;
wire [7:0] clk0_sel_mux, clkfb_sel_mux;
reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel;
reg [2:0] clk0pmf_sel, clk0pmr_sel, clkfbm1pmf_sel, clkfbm1pmr_sel;
reg clkfbout_frac_wf_r, clk0_frac_wf_r, clk0_frac_wf_f, clkfbout_frac_wf_f;
reg clkfbin_edge, clkfbin_nocnt;
reg [2:0] clkfb_frac, clk0_frac;
integer clkfbm1_odd_frac, clk0_odd_frac;
real tmp_fbp;
real tmp_f0p;
integer tmp_fbo, tmp_fbq;
integer tmp_f0o, tmp_f0q;
real clk0_f_div;
reg [5:0] clkfbin_ht, clkfbin_lt;
reg [2:0] clk5fpm_sel, clk6fpm_sel;
wire [2:0] clk0pm_sel1, clk5pm_sel1, clk6pm_sel1, clkfbm1pm_sel1;
reg [2:0] clk6pm_sel, clkfbm1pm_sel;
reg [2:0] clkfbm1r_sel, clk0pm_fsel, clk0pm_rsel, clkfbm1f_sel;
integer clk0pm_sel_int, clkfbm1pm_sel_int;
reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge, clk6_edge;
reg clkfbm1_edge, clkfbm2_edge, clkind_edge;
reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt;
reg clk6_nocnt, clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt;
reg clkfbtmp_nocnti;
reg clkind_edgei, clkind_nocnti;
reg [5:0] clkfbm1_fht, clkfbm1_flt;
reg [5:0] clk0_fht, clk0_flt;
reg [5:0] clk0_dly_cnt, clkout0_dly;
reg [5:0] clk1_dly_cnt, clkout1_dly;
reg [5:0] clk2_dly_cnt, clkout2_dly;
reg [5:0] clk3_dly_cnt, clkout3_dly;
reg [5:0] clk4_dly_cnt, clkout4_dly;
reg [5:0] clk5_dly_cnt, clkout5_dly;
reg [5:0] clk6_dly_cnt, clkout6_dly;
reg [6:0] clk0_ht, clk0_lt;
reg [6:0] clk1_ht, clk1_lt;
reg [6:0] clk2_ht, clk2_lt;
reg [6:0] clk3_ht, clk3_lt;
reg [6:0] clk4_ht, clk4_lt;
reg [6:0] clk5_ht, clk5_lt;
reg [6:0] clk6_ht, clk6_lt;
reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly;
reg [6:0] clkfbm1_ht, clkfbm1_lt;
reg [6:0] clkfbm2_ht, clkfbm2_lt;
reg [7:0] clkind_ht, clkind_lt;
reg [7:0] clkind_hti, clkind_lti;
reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1;
reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1;
reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1;
reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1;
reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1;
reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1;
reg [7:0] clk6_ht1, clk6_cnt, clk6_div, clk6_div1;
reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1;
real clkfbm1_f_div, clkfbm1_div_t;
integer clkfbm1_div_t_int;
reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti;
reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1;
reg [7:0] clkind_div, clkind_divi, clkind_div1, clkind_cnt, clkind_ht1;
reg clkind_out, clkind_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
wire clkinsel_tmp;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
reg init_chk;
reg rst_clkinsel_flag = 0;
reg clkout0_out, clkout1_out, clkout2_out, clkout3_out, clkout4_out;
reg clkout5_out, clkout6_out;
reg clkfbm2_out, clkfbm2_out_tmp, clk6_out;
reg notifier;
wire [15:0] do_out, di_in;
reg [15:0] do_out1;
wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in;
wire clkinsel_in1;
wire psen_in, psclk_in, psincdec_in, pwrdwn_in;
wire pwrdwn_in1;
reg pwrdwn_in1_h = 0;
reg rst_input_r_h = 0;
reg pchk_clr = 0;
reg psincdec_chg = 0;
reg psincdec_chg_tmp = 0;
wire [6:0] daddr_in;
wire rst_input;
wire rst_input_r;
reg startup_wait_sig;
wire delay_PSINCDEC, delay_PSEN, delay_PSCLK, delay_DCLK, delay_DWE;
wire delay_DEN;
wire [15:0] delay_DI;
wire [6:0] delay_DADDR;
real clkfb_sdivide;
integer clkfb_sdivide_int, clkfb_sevent_part_high;
integer clkfb_sevent_part_low, clkfb_sodd, clkfb_sodd_and_frac;
integer clkfb_slt, clkfb_sht, clkfb_sfrac_2;
reg [2:0] clkfbpmf_sel, clkfbpmr_sel;
real clkfb_sa, clkfb_sb, clkfb_sphase;
integer clkfb_sdt_tmp;
integer clkfb_sdt, clkfb_pm_rise_overwriting, clkfb_pm_fall_overwriting;
integer clkfb_pm_fall_overwriting_2nd, clkfb_pm_rise_overwriting_2nd;
real clk0_sdivide;
integer clk0_sdivide_int, clk0_sevent_part_high;
integer clk0_sevent_part_low, clk0_sodd, clk0_sodd_and_frac;
integer clk0_slt, clk0_sht, clk0_sfrac_2;
// reg [2:0] clk0pmf_sel, clk0pmr_sel;
reg clk0out_frac_wf_r, clk0out_frac_wf_f;
real clk0_sa, clk0_sb, clk0_sphase;
integer clk0_sdt_tmp, clk0_sdt, clk0_pm_rise_overwriting, clk0_pm_fall_overwriting;
integer clk0_pm_fall_overwriting_2nd, clk0_pm_rise_overwriting_2nd;
reg vcoflag = 0;
reg [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED;
reg [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED;
reg [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED;
reg [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`ifndef XIL_TIMING
assign CLKINSTOPPED = clkinstopped_out1;
assign CLKFBSTOPPED = clkfbstopped_out1;
assign clkin1_in = CLKIN1;
assign clkin2_in = CLKIN2;
assign clkfb_in = CLKFBIN;
assign clkinsel_in = ((CLKINSEL === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG;
assign rst_input_r = RST ^ IS_RST_INVERTED_REG;
assign daddr_in = DADDR;
assign di_in = DI;
assign dwe_in = DWE;
assign den_in = DEN;
assign dclk_in = DCLK;
assign psclk_in = PSCLK;
assign psen_in = PSEN ^ IS_PSEN_INVERTED_REG;
assign psincdec_in = PSINCDEC ^ IS_PSINCDEC_INVERTED_REG;
assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_REG;
assign LOCKED = locked_out1;
assign DRDY = drdy_out1;
assign DO = do_out1;
assign PSDONE = psdone_out1;
`endif
`ifdef XIL_TIMING
buf b_LOCK (LOCKED, locked_out_tmp);
buf b_DRDY (DRDY, drdy_out);
buf b_DO[15:0] (DO, do_out);
buf b_PSDONE (PSDONE, psdone_out);
buf b_CLKIN1 (clkin1_in, CLKIN1);
buf b_CLKIN2 (clkin2_in, CLKIN2);
buf b_CLKSRC (clkinsel_in1, CLKINSEL);
assign clkinsel_in = ((clkinsel_in1 === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG;
buf b_CLKFB (clkfb_in, CLKFBIN);
buf b_RST (rst_input_r, RST ^ IS_RST_INVERTED_REG);
buf b_DADDR[6:0] (daddr_in, delay_DADDR);
buf b_DI[15:0] (di_in, delay_DI);
buf b_DWE (dwe_in, delay_DWE);
buf b_DEN (den_in, delay_DEN);
buf b_DCLK (dclk_in, delay_DCLK);
buf b_CLKINSTOPPED (CLKINSTOPPED, clkinstopped_out1);
buf b_CLKFBSTOPPED ( CLKFBSTOPPED, clkfbstopped_out1);
buf b_PSCLK (psclk_in, delay_PSCLK);
buf b_PSEN (psen_in, delay_PSEN ^ IS_PSEN_INVERTED_REG);
buf b_PSINCDEC (psincdec_in, delay_PSINCDEC ^ IS_PSINCDEC_INVERTED_REG);
buf b_PWRDWN (pwrdwn_in, PWRDWN ^ IS_PWRDWN_INVERTED_REG);
`endif // `ifdef XIL_TIMING
//drp monitor
reg den_r1 = 1'b0;
reg den_r2 = 1'b0;
reg dwe_r1 = 1'b0;
reg dwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge dclk_in)
begin
// pipeline the DEN and DWE
den_r1 <= den_in;
dwe_r1 <= dwe_in;
den_r2 <= den_r1;
dwe_r2 <= dwe_r1;
// Check - if DEN or DWE is more than 1 DCLK
if ((den_r1 == 1'b1) && (den_r2 == 1'b1))
begin
$display("DRC Error : DEN is high for more than 1 DCLK on %m instance");
$finish;
end
if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1))
begin
$display("DRC Error : DWE is high for more than 1 DCLK on %m instance");
$finish;
end
//After the 1st DEN pulse, check the DEN and DRDY.
case (sfsm)
FSM_IDLE:
begin
if(den_in == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DEN, 4 cases can happen
// DEN DRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(den_in === 1'b1 && drdy_out1 === 1'b0)
begin
$display("DRC Error : DEN is enabled before DRDY returns on %m instance");
$finish;
end
//Add the check for another DWE pulse
if ((dwe_in === 1'b1) && (den_in === 1'b0))
begin
$display("DRC Error : DWE is enabled before DRDY returns on %m instance");
$finish;
end
if ((drdy_out1 === 1'b1) && (den_in === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((drdy_out1 === 1'b1) && (den_in === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge DCLK)
//end drp monitor
`ifndef XIL_TIMING
always @(locked_out_tmp)
locked_out1 = locked_out_tmp;
always @(drdy_out)
drdy_out1 = drdy_out;
always @(do_out)
do_out1 = do_out;
always @(psdone_out)
psdone_out1 = psdone_out;
`endif // `ifndef XIL_TIMING
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the %s, the simulator resolution must be set to 1ps or smaller.", MODULE_NAME);
$finish;
end
end
initial begin
case (STARTUP_WAIT)
"FALSE" : startup_wait_sig = 0;
"TRUE" : startup_wait_sig = 1;
default : begin
$display("Attribute Syntax Error : The Attribute STARTUP_WAIT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, STARTUP_WAIT);
$finish;
end
endcase
case (BANDWIDTH)
"OPTIMIZED" : ;
"HIGH" : ;
"LOW" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BANDWIDTH on %s instance %m is set to %s. Legal values for this attribute are OPTIMIZED, HIGH, or LOW.", MODULE_NAME, BANDWIDTH);
$finish;
end
endcase
case (CLKFBOUT_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKFBOUT_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT0_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT0_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT1_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT1_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT2_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT2_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT3_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT3_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT4_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT4_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT5_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT5_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT6_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT6_USE_FINE_PS);
$finish;
end
endcase
clkin_hold_f = 0;
// case (CLOCK_HOLD)
// "FALSE" : clkin_hold_f = 0;
// "TRUE" : clkin_hold_f = 1;
// default : begin
// $display("Attribute Syntax Error : The Attribute CLOCK_HOLD on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLOCK_HOLD);
// $finish;
// end
// endcase
case (CLKOUT4_CASCADE)
"FALSE" : clkout4_cascade_int = 0;
"TRUE" : clkout4_cascade_int = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_CASCADE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT4_CASCADE);
$finish;
end
endcase
case (COMPENSATION)
"ZHOLD" : ;
"BUF_IN" : ;
"EXTERNAL" : ;
"INTERNAL" : ;
default : begin
$display("Attribute Syntax Error : The Attribute COMPENSATION on %s instance %m is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL, or INTERNAL.", MODULE_NAME, COMPENSATION);
$finish;
end
endcase
CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F + 0.0625) * 8.0)) / 8.0;
CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F + 0.0625) * 8.0)) / 8.0;
if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F) begin
$display(" Warning : parameter CLKFBOUT_MULT_F of %s instance %m is not set to a resolution of .125 (%f) and is being rounded down to (%f).", MODULE_NAME, CLKFBOUT_MULT_F, CLKFBOUT_MULT_F_RND);
end
else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F) begin
$display(" Warning : parameter CLKFBOUT_MULT_F of %s instance %m is not set to a resolution of .125 (%f) and is being rounded up to (%f).", MODULE_NAME, CLKFBOUT_MULT_F, CLKFBOUT_MULT_F_RND);
end
if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F) begin
$display(" Warning : parameter CLKOUT0_DIVIDE_F of %s instance %m is not set to a resolution of .125 (%f) and is being rounded down to (%f).", MODULE_NAME, CLKOUT0_DIVIDE_F, CLKOUT0_DIVIDE_F_RND);
end
else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F) begin
$display(" Warning : parameter CLKOUT0_DIVIDE_F of %s instance %m is not set to a resolution of .125 (%f) and is being rounded up to (%f).", MODULE_NAME, CLKOUT0_DIVIDE_F, CLKOUT0_DIVIDE_F_RND);
end
clkfbm1_f_div = CLKFBOUT_MULT_F_RND;
clkfb_div_fint = $rtoi(CLKFBOUT_MULT_F_RND);
clkfb_div_frac = CLKFBOUT_MULT_F_RND - clkfb_div_fint;
clkfb_div_check = 8.0 * clkfb_div_frac;
clkfb_div_check_int = 8.0 * clkfb_div_frac;
clkfb_div_check_diff = clkfb_div_check - clkfb_div_check_int;
if (clkfb_div_frac > 0.000)
clkfb_frac_en = 1;
else
clkfb_frac_en = 0;
if (clkfb_frac_en == 1 && clkfb_div_check_diff == 0.000)
clkfb_div_adj = 0;
else
clkfb_div_adj = 1;
if (clkfb_frac_en)
clkfbm1_div_t = clkfbm1_f_div;
else
clkfbm1_div_t = clkfbm1_div;
clkfb_div_frac_int = $rtoi(8.0 * clkfb_div_frac);
clkfb_div_fint_tmp1 = clkfb_div_fint / 2;
clkfb_div_fint_odd = clkfb_div_fint - clkfb_div_fint_tmp1 -clkfb_div_fint_tmp1;
clkfb_sdivide = CLKFBOUT_MULT_F_RND;
clkfb_sdivide_int = clkfb_div_fint;
clkfb_frac = clkfb_div_frac_int;
clkfb_sevent_part_high = clkfb_div_fint_tmp1;
clkfb_sevent_part_low = clkfb_sevent_part_high;
clkfb_sodd = clkfb_div_fint_odd;
clkfb_sodd_and_frac = 8 * clkfb_sodd + clkfb_frac;
if (clkfb_sodd_and_frac > 9)
clkfbm1_lt = clkfb_sevent_part_high;
else
clkfbm1_lt = clkfb_sevent_part_high - 1;
if (clkfb_sodd_and_frac > 8)
clkfbm1_ht = clkfb_sevent_part_low;
else
clkfbm1_ht = clkfb_sevent_part_low - 1;
clkfb_sfrac_2 = clkfb_div_frac_int / 2;
clkfbpmf_sel = 4 * clkfb_sodd + clkfb_sfrac_2;
clkfbpmr_sel = 3'b0;
if (CLKFBOUT_MULT_F_RND == 2.125)
clkfbout_frac_wf_f = 1;
else begin
if (clkfb_sodd_and_frac >= 2 && clkfb_sodd_and_frac <= 9)
clkfbout_frac_wf_f = 1;
else
clkfbout_frac_wf_f = 0;
end
if (clkfb_sodd_and_frac >= 1 && clkfb_sodd_and_frac <= 8)
clkfbout_frac_wf_r = 1;
else
clkfbout_frac_wf_r = 0;
if (CLKFBOUT_PHASE < 0.000)
clkfb_sphase = CLKFBOUT_PHASE + 360;
else
clkfb_sphase = CLKFBOUT_PHASE;
clkfb_sdt = $rtoi(CLKFBOUT_PHASE * clkfb_sdivide / 360.0);
clkfb_sa = CLKFBOUT_PHASE * clkfb_sdivide / 360.0 - clkfb_sdt;
clkfb_sb = clkfb_sa;
clkfb_pm_rise_overwriting = $rtoi(8.0 * clkfb_sb);
if (clkfb_pm_rise_overwriting > 7)
clkfb_pm_rise_overwriting_2nd = clkfb_pm_rise_overwriting - 8;
else
clkfb_pm_rise_overwriting_2nd = clkfb_pm_rise_overwriting;
clkfb_pm_fall_overwriting = clkfbpmf_sel + clkfb_pm_rise_overwriting_2nd;
if (clkfb_pm_fall_overwriting > 7)
clkfb_pm_fall_overwriting_2nd = clkfb_pm_fall_overwriting - 8;
else
clkfb_pm_fall_overwriting_2nd = clkfb_pm_fall_overwriting;
clkfb_sdt_tmp = clkfb_sdt;
if (clkfb_pm_rise_overwriting > 7)
clkfb_sdt = clkfb_sdt_tmp + 1;
// mf_product = clkfb_div_fint * 8 + clkfb_div_frac_int;
clk0_f_div = CLKOUT0_DIVIDE_F_RND;
clk0_div_fint = $rtoi(CLKOUT0_DIVIDE_F_RND);
clk0_div_frac = CLKOUT0_DIVIDE_F_RND - clk0_div_fint;
if (clk0_div_frac > 0.000 && clk0_div_fint >= 2)
clk0_frac_en = 1;
else
clk0_frac_en = 0;
clk0_div_check = 8.0 * clk0_div_frac;
clk0_div_check_int = 8.0 * clk0_div_frac;
clk0_div_check_diff = clk0_div_check - clk0_div_check_int;
if (clk0_frac_en == 1 && clk0_div_check_diff == 0.000)
clk0_div_adj = 0;
else
clk0_div_adj = 1;
clk0_div_frac_int = $rtoi(clk0_div_frac * 8);
clk0_div_fint_tmp1 = clk0_div_fint / 2;
clk0_div_fint_odd = clk0_div_fint - clk0_div_fint_tmp1 -clk0_div_fint_tmp1;
clk0_sdivide = CLKOUT0_DIVIDE_F_RND;
clk0_sdivide_int = clk0_div_fint;
clk0_frac = clk0_div_frac_int;
clk0_sevent_part_high = clk0_div_fint_tmp1;
clk0_sevent_part_low = clk0_sevent_part_high;
clk0_sodd = clk0_div_fint_odd;
// clk0_sodd_and_frac = 8 * clk0_sodd + clk0_sfrac;
clk0_sodd_and_frac = 8 * clk0_sodd + clk0_frac;
if (clk0_sodd_and_frac > 9)
clk0_lt = clk0_sevent_part_high;
else
clk0_lt = clk0_sevent_part_high - 1;
if (clk0_sodd_and_frac > 8)
clk0_ht = clk0_sevent_part_low;
else
clk0_ht = clk0_sevent_part_low - 1;
clk0_sfrac_2 = clk0_div_frac_int / 2;
clk0pmf_sel = 4 * clk0_sodd + clk0_sfrac_2;
clk0pmr_sel = 3'b0;
if (CLKOUT0_DIVIDE_F_RND == 2.125)
clk0_frac_wf_f = 1;
else begin
if (clk0_sodd_and_frac >= 2 && clk0_sodd_and_frac <= 9)
clk0_frac_wf_f = 1;
else
clk0_frac_wf_f = 0;
end
if (clk0_sodd_and_frac >= 1 && clk0_sodd_and_frac <= 8)
clk0_frac_wf_r = 1;
else
clk0_frac_wf_r = 0;
if (CLKOUT0_PHASE < 0.000)
clk0_sphase = CLKOUT0_PHASE + 360;
else
clk0_sphase = CLKOUT0_PHASE;
clk0_sdt = $rtoi(CLKOUT0_PHASE * clk0_sdivide / 360.0);
clk0_sa = CLKOUT0_PHASE * clk0_sdivide / 360.0 - clk0_sdt;
clk0_sb = clk0_sa;
clk0_pm_rise_overwriting = $rtoi(8.0 * clk0_sb);
if (clk0_pm_rise_overwriting > 7)
clk0_pm_rise_overwriting_2nd = clk0_pm_rise_overwriting - 8;
else
clk0_pm_rise_overwriting_2nd = clk0_pm_rise_overwriting;
clk0_pm_fall_overwriting = clk0pmf_sel + clk0_pm_rise_overwriting_2nd;
if (clk0_pm_fall_overwriting > 7)
clk0_pm_fall_overwriting_2nd = clk0_pm_fall_overwriting - 8;
else
clk0_pm_fall_overwriting_2nd = clk0_pm_fall_overwriting;
clk0_sdt_tmp = clk0_sdt;
if (clk0_pm_rise_overwriting > 7)
clk0_sdt = clk0_sdt_tmp + 1;
ps_in_init = 0;
ps_in_ps = ps_in_init;
ps_cnt = 0;
if (CLKFBOUT_USE_FINE_PS == "TRUE") begin
// if (clkfb_frac_en == 1) begin
// $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on %s instance %m is set to %s. This attribute should be set to FALSE when CLKFBOUT_MULT_F has fraction part.", MODULE_NAME, CLKFBOUT_USE_FINE_PS);
// $finish;
// end
// else
clkfb_fps_en = 1;
end
else
clkfb_fps_en = 0;
if (CLKOUT0_USE_FINE_PS == "TRUE") begin
// if (clk0_frac_en == 1) begin
// $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on %s instance %m is set to %s. This attribute should be set to FALSE when CLKOUT0_DIVIDE has fraction part.", MODULE_NAME, CLKOUT0_USE_FINE_PS);
// $finish;
// end
// else
clk0_fps_en = 1;
end
else
clk0_fps_en = 0;
if (CLKOUT1_USE_FINE_PS == "TRUE")
clk1_fps_en = 1;
else
clk1_fps_en = 0;
if (CLKOUT2_USE_FINE_PS == "TRUE")
clk2_fps_en = 1;
else
clk2_fps_en = 0;
if (CLKOUT3_USE_FINE_PS == "TRUE")
clk3_fps_en = 1;
else
clk3_fps_en = 0;
if (CLKOUT4_USE_FINE_PS == "TRUE")
clk4_fps_en = 1;
else
clk4_fps_en = 0;
if (CLKOUT5_USE_FINE_PS == "TRUE")
clk5_fps_en = 1;
else
clk5_fps_en = 0;
if (CLKOUT6_USE_FINE_PS == "TRUE")
clk6_fps_en = 1;
else
clk6_fps_en = 0;
fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en
|| clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfb_fps_en;
tmp_string = "CLKOUT0_DIVIDE_F";
chk_ok = para_real_range_chk(CLKOUT0_DIVIDE_F_RND, tmp_string, 1.000, 128.000);
if (CLKOUT0_DIVIDE_F_RND > 1.0000 && CLKOUT0_DIVIDE_F_RND < 2.0000)
$display("Attribute Syntax Error : The Attribute CLKOUT0_DIVIDE_F on %s instance %m is set to %f. Values in range of greater than 1 and less than 2 are not allowed.", MODULE_NAME, CLKOUT0_DIVIDE_F_RND);
tmp_string = "CLKOUT0_PHASE";
// if (clk0_frac_en == 0)
chk_ok = para_real_range_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0);
// else
// if (CLKOUT0_PHASE != 0.0) begin
// $display("Attribute Syntax Error : The Attribute CLKOUT0_PHASE on %s instance %m is set to %f. This attribute should be set to 0.0 when CLKOUT0_DIVIDE_F has fraction part.", MODULE_NAME, CLKOUT0_PHASE);
// $finish;
// end
tmp_string = "CLKOUT0_DUTY_CYCLE";
if (clk0_frac_en == 0)
chk_ok = para_real_range_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.001, 0.999);
else
if (CLKOUT0_DUTY_CYCLE != 0.5) begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_DUTY_CYCLE on %s instance %m is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part.", MODULE_NAME, CLKOUT0_DUTY_CYCLE);
$finish;
end
tmp_string = "CLKOUT1_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT1_PHASE";
chk_ok = para_real_range_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT2_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT2_PHASE";
chk_ok = para_real_range_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT3_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT3_PHASE";
chk_ok = para_real_range_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT4_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT4_PHASE";
chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT5_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT5_PHASE";
chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT6_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT6_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT6_PHASE";
chk_ok = para_real_range_chk(CLKOUT6_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT6_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk(CLKFBOUT_MULT_F_RND, tmp_string, 2.000, 64.000);
tmp_string = "CLKFBOUT_PHASE";
// if (clkfb_frac_en == 0)
chk_ok = para_real_range_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0);
// else
// if (CLKFBOUT_PHASE != 0.0) begin
// $display("Attribute Syntax Error : The Attribute CLKFBOUT_PHASE on %s instance %m is set to %f. This attribute should be set to 0.0 when CLKFBOUT_MULT_F has fraction part.", MODULE_NAME, CLKFBOUT_PHASE);
// $finish;
// end
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, D_MAX);
tmp_string = "REF_JITTER1";
chk_ok = para_real_range_chk (REF_JITTER1, tmp_string, 0.000, 0.999);
tmp_string = "REF_JITTER2";
chk_ok = para_real_range_chk (REF_JITTER2, tmp_string, 0.000, 0.999);
// if (BANDWIDTH === "LOW")
// pll_lfhf = 2'b11;
// else
pll_lfhf = 2'b00;
if (BANDWIDTH === "LOW")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
3 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
4 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
5 : begin pll_cp = 4'b0010; pll_res = 4'b0111; end
6 : begin pll_cp = 4'b0010; pll_res = 4'b1011; end
7 : begin pll_cp = 4'b0010; pll_res = 4'b1101; end
8 : begin pll_cp = 4'b0010; pll_res = 4'b0011; end
9 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end
10 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end
11 : begin pll_cp = 4'b0010; pll_res = 4'b1001; end
12 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
13 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
14 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
15 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
16 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end
17 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end
18 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end
19 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
20 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
21 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
22 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
23 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
24 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
25 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
26 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
27 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
28 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
29 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
30 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
31 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
32 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
33 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
34 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
35 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
36 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
37 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
38 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
39 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
40 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
41 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
42 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
43 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
44 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
45 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
46 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
47 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
48 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
49 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
50 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
51 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
52 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
53 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
54 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
55 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
56 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
57 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
58 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
59 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
60 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
62 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
63 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
64 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
endcase
else if (BANDWIDTH === "HIGH")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100; pll_res = 4'b1111; end
3 : begin pll_cp = 4'b0101; pll_res = 4'b1011; end
4 : begin pll_cp = 4'b0111; pll_res = 4'b0111; end
5 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end
6 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end
7 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end
8 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end
9 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end
10 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
11 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
12 : begin pll_cp = 4'b1101; pll_res = 4'b0001; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
38 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
39 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
41 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
47 : begin pll_cp = 4'b0111; pll_res = 4'b0001; end
48 : begin pll_cp = 4'b0111; pll_res = 4'b0001; end
49 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
50 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
51 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
52 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
53 : begin pll_cp = 4'b0110; pll_res = 4'b0001; end
54 : begin pll_cp = 4'b0110; pll_res = 4'b0001; end
55 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
56 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
57 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
58 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
59 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
60 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
62 : begin pll_cp = 4'b0100; pll_res = 4'b1010; end
63 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
64 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
endcase
else if (BANDWIDTH === "OPTIMIZED")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100; pll_res = 4'b1111; end
3 : begin pll_cp = 4'b0101; pll_res = 4'b1011; end
4 : begin pll_cp = 4'b0111; pll_res = 4'b0111; end
5 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end
6 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end
7 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end
8 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end
9 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end
10 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
11 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
12 : begin pll_cp = 4'b1101; pll_res = 4'b0001; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
38 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
39 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
41 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
47 : begin pll_cp = 4'b0111; pll_res = 4'b0001; end
48 : begin pll_cp = 4'b0111; pll_res = 4'b0001; end
49 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
50 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
51 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
52 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
53 : begin pll_cp = 4'b0110; pll_res = 4'b0001; end
54 : begin pll_cp = 4'b0110; pll_res = 4'b0001; end
55 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
56 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
57 : begin pll_cp = 4'b0101; pll_res = 4'b0110; end
58 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
59 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
60 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
62 : begin pll_cp = 4'b0100; pll_res = 4'b1010; end
63 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
64 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
endcase
case (clkfb_div_fint)
1 : begin drp_lock_ref_dly = 5'b00110;
drp_lock_fb_dly = 5'b00110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
2 : begin drp_lock_ref_dly = 5'b00110;
drp_lock_fb_dly = 5'b00110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
3 : begin drp_lock_ref_dly = 5'b01000;
drp_lock_fb_dly = 5'b01000;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
4 : begin drp_lock_ref_dly = 5'b01011;
drp_lock_fb_dly = 5'b01011;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
5 : begin drp_lock_ref_dly = 5'b01110;
drp_lock_fb_dly = 5'b01110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
6 : begin drp_lock_ref_dly = 5'b10001;
drp_lock_fb_dly = 5'b10001;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
7 : begin drp_lock_ref_dly = 5'b10011;
drp_lock_fb_dly = 5'b10011;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
8 : begin drp_lock_ref_dly = 5'b10110;
drp_lock_fb_dly = 5'b10110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
9 : begin drp_lock_ref_dly = 5'b11001;
drp_lock_fb_dly = 5'b11001;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
10 : begin drp_lock_ref_dly = 5'b11100;
drp_lock_fb_dly = 5'b11100;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
11 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1110000100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
12 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1100111001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
13 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1011101110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
14 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1010111100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
15 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1010001010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
16 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1001110001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
17 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000111111;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
18 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000100110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
19 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000001101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
20 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111110100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
21 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111011011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
22 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111000010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
23 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110101001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
24 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110010000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
25 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110010000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
26 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101110111;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
27 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101011110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
28 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101011110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
29 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101000101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
30 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101000101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
31 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
32 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
33 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
34 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
35 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
36 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
37 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
38 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
39 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
40 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
41 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
42 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
43 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
44 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
45 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
46 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
47 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
48 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
49 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
50 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
51 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
52 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
53 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
54 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
55 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
56 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
57 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
58 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
59 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
60 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
61 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
62 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
63 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
64 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
endcase
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, tmp_string);
if(clk0_frac_en == 0) begin
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE, tmp_string);
end
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string);
period_vco_max = 1000000 / VCOCLK_FREQ_MIN;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clk0f_product = CLKOUT0_DIVIDE_F_RND * 8;
pll_lock_time = 12;
lock_period_time = 10;
if (clkfb_frac_en == 1) begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT_F_RND * 8;
clkout_en_val = mf_product - 2;
m_product2 = clkfb_div_fint / 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT_F_RND * 8;
m_product2 = clkfb_div_fint / 2;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
clkfb_stop_max = 3;
clkin_stop_max = DIVCLK_DIVIDE + 1;
REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE);
clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE);
clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE);
clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE);
clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE);
clk_out_para_cal (clk6_ht, clk6_lt, clk6_nocnt, clk6_edge, CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE);
clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50);
tmp_string = "CLKOUT1_PHASE";
clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string);
tmp_string = "CLKOUT2_PHASE";
clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string);
tmp_string = "CLKOUT3_PHASE";
clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string);
tmp_string = "CLKOUT4_PHASE";
clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string);
tmp_string = "CLKOUT5_PHASE";
clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string);
tmp_string = "CLKOUT6_PHASE";
clkout_dly_cal (clkout6_dly, clk6pm_sel, CLKOUT6_DIVIDE, CLKOUT6_PHASE, tmp_string);
if (clkfb_frac_en == 1) begin
clkfbm1_fht = clkfb_div_fint /2;
clkfbm1_flt = clkfb_div_fint /2;
if (clkfb_div_fint_odd > 0) begin
clkfbm1r_sel = (8 + clkfb_div_frac_int) / 2;
clkfbm1f_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
end
else begin
clkfbm1f_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1r_sel = clkfb_div_frac_int / 2;
end
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_real_cal (clkfbm1_dly, clkfbm1pm_sel, CLKFBOUT_MULT_F_RND, CLKFBOUT_PHASE, tmp_string);
end
else begin
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_real_cal (clkfbm1_dly, clkfbm1pm_sel, clkfb_div_fint, CLKFBOUT_PHASE, tmp_string);
end
if (clk0_frac_en == 1) begin
clk0_fht = clk0_div_fint /2;
clk0_flt = clk0_div_fint /2;
if (clk0_div_fint_odd > 0) begin
clk0pm_rsel = (8 + clk0_div_frac_int) / 2;
clk0pm_fsel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
end
else begin
clk0pm_fsel = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_rsel = clk0_div_frac_int / 2;
end
tmp_string = "CLKOUT0_PHASE";
clkout_dly_real_cal (clkout0_dly, clk0pm_sel, CLKOUT0_DIVIDE_F_RND, CLKOUT0_PHASE, tmp_string);
end
else begin
tmp_string = "CLKOUT0_PHASE";
clkout_dly_real_cal (clkout0_dly, clk0pm_sel, clk0_div_fint, CLKOUT0_PHASE, tmp_string);
end
if (clk0_frac_en == 0) begin
clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, clk0_div_fint, CLKOUT0_DUTY_CYCLE);
end
if (clkfb_frac_en == 0) begin
clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50);
end
clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, 1, 0.50);
clkind_div = DIVCLK_DIVIDE;
dr_sram[6] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]};
dr_sram[7] = {2'bx, clk0pmf_sel[2:0], clk0_frac_wf_f, 2'b0, clk5_edge,
clk5_nocnt, clkout5_dly[5:0]};
dr_sram[8] = {clk0pmr_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {1'bx, clk0_frac[2:0], clk0_frac_en, clk0_frac_wf_r, 2'b0,
clk0_edge, clk0_nocnt, clkout0_dly[5:0]};
dr_sram[10] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {6'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]};
dr_sram[12] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]};
dr_sram[13] = {6'bx, 2'b0, clk2_edge, clk2_nocnt, clkout2_dly[5:0]};
dr_sram[14] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]};
dr_sram[15] = {6'bx, 2'b0, clk3_edge, clk3_nocnt, clkout3_dly[5:0]};
dr_sram[16] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]};
dr_sram[17] = {6'bx, 2'b0, clk4_edge, clk4_nocnt, clkout4_dly[5:0]};
dr_sram[18] = {clk6pm_sel[2:0], 1'b1, clk6_ht[5:0], clk6_lt[5:0]};
dr_sram[19] = {2'bx, clkfbpmf_sel[2:0], clkfbout_frac_wf_f, 2'b0,
clk6_edge, clk6_nocnt, clkout6_dly[5:0]};
dr_sram[20] = {clkfbpmr_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]};
dr_sram[21] = {1'bx, clkfb_frac[2:0], clkfb_frac_en,
clkfbout_frac_wf_r, 2'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]};
dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]};
dr_sram[23] = {2'bx, clkfbin_edge, clkfbin_nocnt, clkfbin_ht[5:0], clkfbin_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
dr_sram[116] = {5'bx, 6'b0, 5'b00001};
end
initial begin
clkpll_jitter_unlock = 0;
clkinstopped_vco_f = 0;
rst_clkfbstopped = 0;
rst_clkinstopped = 0;
rst_clkfbstopped_lk = 0;
rst_clkinstopped_lk = 0;
clkfb_stop_tmp = 0;
clkin_stop_tmp = 0;
clkout_ps = 0;
clkout_ps_tmp1 = 0;
clkout_ps_tmp2 = 0;
clkvco_ps_tmp1 = 0;
clkvco_ps_tmp2 = 0;
clkvco_ps_tmp2_en = 0;
clkvco_lk_osc = 0;
clkvco_lk_en = 0;
clkvco_lk_tmp = 0;
clkvco_lk_dly_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
clkind_edgei = 0;
clkind_nocnti = 0;
clkind_hti = 0;
clkind_lti = 0;
clkind_divi = 1;
ps_lock = 0;
ps_lock_dly = 0;
psdone_out = 0;
psdone_out1 = 0;
rst_in = 0;
clkinstopped_out = 0;
clkfbstopped_out = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_period_tmp_t = 0;
period_avg = 0;
period_fb = 0;
clkin_lost_val = 500;
clkfb_lost_val = 500;
clkin_lost_val_lk = 500;
fb_delay = 0;
clkfbm1_div = 1;
clkfbm2_div = 1;
clkfbm1_div1 = 0;
clkfbm2_div1 = 0;
clkvco_delay = 0;
val_tmp = 0;
dly_tmp = 0;
fbm1_comp_delay = 0;
clkfbm1pm_rl = 0;
period_vco = 0;
period_vco1 = 0;
period_vco2 = 0;
period_vco3 = 0;
period_vco4 = 0;
period_vco5 = 0;
period_vco6 = 0;
period_vco7 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
period_ps = 0;
period_ps_old = 0;
clkfb_frac_ht = 0;
clkfb_frac_lt = 0;
clk0_frac_ht = 0;
clk0_frac_lt = 0;
clkvco_rm_cnt = 0;
fb_delay_found = 0;
fb_delay_found_tmp = 0;
clkin_edge = 0;
delay_edge = 0;
fbclk_tmp = 0;
clkfb_tst = 0;
clkout_en = 0;
clkout_en0 = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
clkout_mux = 8'b0;
clkout_ps_mux = 8'b0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
rst_edge = 0;
rst_ht = 0;
drdy_out = 0;
drdy_out1 = 0;
locked_out1 = 0;
locked_out_tmp = 0;
do_out1 = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 0;
clkout0_out = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clk2_dly_cnt = 6'b0;
clk3_dly_cnt = 6'b0;
clk4_dly_cnt = 6'b0;
clk5_dly_cnt = 6'b0;
clk6_dly_cnt = 6'b0;
clkfbm1_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clk2_cnt = 8'b0;
clk3_cnt = 8'b0;
clk4_cnt = 8'b0;
clk5_cnt = 8'b0;
clk6_cnt = 8'b0;
clkfbm1_cnt = 8'b0;
clkfbm2_cnt = 8'b0;
clkind_cnt = 8'b0;
clkout0_out = 0;
clkout1_out = 0;
clkout2_out = 0;
clkout3_out = 0;
clkout4_out = 0;
clkout5_out = 0;
clkout6_out = 0;
clk0_nf_out = 0;
clk0_frac_out = 0;
clk1_out = 0;
clk2_out = 0;
clk3_out = 0;
clk4_out = 0;
clk5_out = 0;
clk6_out = 0;
clkfb_out = 0;
clkfbm1_nf_out = 0;
clkfbm1_frac_out = 0;
clkfbm2_out = 0;
clkfbm2_out_tmp = 0;
clkind_out = 0;
clkind_out_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
assign CLKOUT6 = clkout6_out;
assign CLKOUT5 = clkout5_out;
assign CLKOUT4 = clkout4_out;
assign CLKOUT3 = clkout3_out;
assign CLKOUT2 = clkout2_out;
assign CLKOUT1 = clkout1_out;
assign CLKOUT0 = clkout0_out;
assign CLKFBOUT = clkfb_out;
assign CLKOUT3B = ~clkout3_out;
assign CLKOUT2B = ~clkout2_out;
assign CLKOUT1B = ~clkout1_out;
assign CLKOUT0B = ~clkout0_out;
assign CLKFBOUTB = ~clkfb_out;
assign #1 clkinsel_tmp = clkinsel_in;
assign glock = (startup_wait_sig) ? locked_out_tmp : 1;
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial begin
init_chk = 0;
#1;
init_chk = 1;
end
always @(clkinsel_in or posedge init_chk ) begin
if ($time > 1 && rst_in === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin
$display("Input Error : Input clock can only be switched when RST=1. CLKINSEL on %s instance %m at time %t changed when RST low, which should change at RST high.", MODULE_NAME, $time);
$finish;
end
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (clkinsel_in === 1 && $time > 1 || clkinsel_in !== 0 && init_chk == 1) begin
if (CLKIN1_PERIOD > clkin_chk_t1 || CLKIN1_PERIOD < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
else if (clkinsel_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin
if (CLKIN2_PERIOD > clkin_chk_t1 || CLKIN2_PERIOD < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
period_clkin = (clkinsel_in === 0) ? CLKIN2_PERIOD : CLKIN1_PERIOD;
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE);
if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX);
$finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX);
$finish;
end
end
end
assign init_trig = 1;
assign clkpll_r = (clkinsel_in) ? clkin1_in : clkin2_in;
assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0;
assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkpll_r or posedge rst_input)
if (rst_input)
rst_in <= 1;
else
rst_in <= rst_input ;
assign rst_in_o = (rst_in || rst_clkfbstopped || rst_clkinstopped);
//simprim_rst_h
always @(posedge pwrdwn_in1 or posedge pchk_clr)
if (pwrdwn_in1)
pwrdwn_in1_h <= 1;
else if (pchk_clr)
pwrdwn_in1_h <= 0;
always @(posedge rst_input_r or posedge pchk_clr)
if (rst_input_r)
rst_input_r_h <= 1;
else if (pchk_clr)
rst_input_r_h <= 0;
always @(rst_input )
if (rst_input==1) begin
rst_edge = $time;
pchk_clr = 0;
end
else if (rst_input==0 && rst_edge > 1) begin
rst_ht = $time - rst_edge;
if (rst_ht < 1500) begin
if (rst_input_r_h == 1 && pwrdwn_in1_h == 1)
$display("Input Error : RST and PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0)
$display("Input Error : RST on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1)
$display("Input Error : PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
end
pchk_clr = 1;
end
//endsimprim_rst_h
//
// DRP port read and write
//
assign do_out = dr_sram[daddr_lat];
always @(posedge dclk_in or posedge GSR)
if (GSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 0;
end
else begin
if (den_in == 1) begin
valid_daddr = addr_is_valid(daddr_in);
if (drp_lock == 1) begin
// $display(" Warning : DEN is high at %s instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP.", MODULE_NAME, $time);
end
else begin
drp_lock <= 1;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
daddr_lat <= daddr_in;
end
if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 ||
daddr_in == 7'b1001110 || daddr_in == 7'b0101000 ||
(daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) ||
(daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin
end
else begin
$display(" Warning : Address DADDR=%b is unsupported at %s instance %m at time %t.", MODULE_NAME, DADDR, $time);
end
if (dwe_in == 1) begin // write process
if (rst_input == 1) begin
if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 ||
daddr_in == 7'b1001110 || daddr_in == 7'b0101000 ||
(daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) ||
(daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin
dr_sram[daddr_in] <= di_in;
end
if (daddr_in == 7'b0001001) begin
clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in);
clk0_frac[2:0] <= di_in[14:12];
clk0_frac_en <= di_in[11];
end
if (daddr_in == 7'b0001000) begin
clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in, clk0_frac_en);
clk0pmr_sel[2:0] <= di_in[15:13];
end
if (daddr_in == 7'b0001011)
clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in);
if (daddr_in == 7'b0001010)
clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0001101)
clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in);
if (daddr_in == 7'b0001100)
clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0001111)
clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in);
if (daddr_in == 7'b0001110)
clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0010001)
clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in);
if (daddr_in == 7'b0010000)
clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0010011) begin
clkout_delay_para_drp (clkout6_dly, clk6_nocnt, clk6_edge, di_in, daddr_in);
clkfbpmf_sel[2:0] <= di_in[13:11];
end
if (daddr_in == 7'b0010010)
clkout_hl_para_drp (clk6_lt, clk6_ht, clk6pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0000111) begin
clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in);
clk0pmf_sel[2:0] <= di_in[13:11];
end
if (daddr_in == 7'b0000110)
clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in, 1'b0);
if (daddr_in == 7'b0010101) begin
clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in);
clkfbtmp_nocnti = di_in[6];
clkfb_frac[2:0] <= di_in[14:12];
clkfb_frac_en <= di_in[11];
end
if (daddr_in == 7'b0010100) begin
clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in, clkfb_frac_en);
clkfbpmr_sel[2:0] <= di_in[15:13];
clkfbtmp_lti = {2'b00, di_in[5:0]};
clkfbtmp_hti = {2'b00, di_in[11:6]};
// if (clkfbtmp_nocnti == 1)
// clkfbtmp_divi = 8'b00000001;
// else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0)
// clkfbtmp_divi = 8'b10000000;
// else if (di_in[5:0] == 6'b0)
// clkfbtmp_divi = 64 + clkfbtmp_hti;
// else if (di_in[11:6] == 6'b0)
// clkfbtmp_divi = 64 + clkfbtmp_lti;
// else
// clkfbtmp_divi = clkfbtmp_hti + clkfbtmp_lti;
clkfbtmp_divi = clkfbm1_ht + clkfbm1_lt;
if (((clkfbtmp_divi > M_MAX) || (clkfbtmp_divi < M_MIN)) && (clkfb_frac_en == 1'b0))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %h and over the range of %f to %f.", MODULE_NAME, daddr_in, di_in, clkfbtmp_divi, $time, M_MIN, M_MAX);
end
if (daddr_in == 7'b0010110) begin
clkind_lti = {2'b00, di_in[5:0]};
clkind_hti = {2'b00, di_in[11:6]};
clkind_lt <= clkind_lti;
clkind_ht <= clkind_hti;
clkind_nocnt <= di_in[12];
clkind_nocnti = di_in[12];
clkind_edgei = di_in[13];
clkind_edge <= di_in[13];
if (di_in[12] == 1)
clkind_divi = 8'b00000001;
else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0)
clkind_divi = 8'b10000000;
else if (di_in[5:0] == 6'b0)
clkind_divi = 64 + clkind_hti;
else if (di_in[11:6] == 6'b0)
clkind_divi = 64 + clkind_lti;
else
clkind_divi = clkind_hti + clkind_lti;
clkind_div <= clkind_divi;
if (clkind_divi > D_MAX || (clkind_divi < 1 && clkind_nocnti == 0))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to %d.", MODULE_NAME, daddr_in, di_in, clkind_divi, $time, D_MAX);
end
end
else begin
$display(" Error : RST is low at %s instance %m at time %t. RST need to be high when change %s paramters through DRP.", MODULE_NAME, $time, MODULE_NAME);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
end
else begin
drp_lock <= 0;
drdy_out <= 1;
drp_lock_lat_cnt <= 0;
end
end
if (drdy_out == 1) drdy_out <= 0;
end
function addr_is_valid;
input [6:0] daddr_funcin;
begin
addr_is_valid = 1;
for (i=0; i<=6; i=i+1)
if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
addr_is_valid = 0;
end
endfunction
// end process drp;
//
// determine clock period
//
always @(posedge clkpll_r or posedge rst_in or posedge rst_clkinsel_flag)
if (rst_in || rst_clkinsel_flag)
begin
clkin_period[0] <= 1000 * period_clkin;
clkin_period[1] <= 1000 * period_clkin;
clkin_period[2] <= 1000 * period_clkin;
clkin_period[3] <= 1000 * period_clkin;
clkin_period[4] <= 1000 * period_clkin;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end
else begin
clkin_edge <= $time;
if (clkin_edge != 0 && clkinstopped_out == 0 && rst_clkinsel_flag == 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0)
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
end
if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0)
pll_locked_tm <= 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(posedge pll_locked_tmp1)
if (clkinsel_in === 0) begin
pchk_tmp1 = CLKIN2_PERIOD * 1100;
pchk_tmp2 = CLKIN2_PERIOD * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN2 period and attribute CLKIN2_PERIOD on %s instance %m are not same.", MODULE_NAME);
end
end
else begin
pchk_tmp1 = CLKIN1_PERIOD * 1100;
pchk_tmp2 = CLKIN1_PERIOD * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN1 period and attribute CLKIN1_PERIOD on %s instance %m are not same.", MODULE_NAME);
end
end
//always @(m_product or mf_product or clkfb_frac_en)
always @(negedge rst_in)
if (clkfb_frac_en == 0) begin
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
clkout_en_val = mf_product - 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
if (clkout_en0_tmp==0 )
clkout_en0 = 0;
else begin
if (clkfb_frac_en == 1) begin
if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
else begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in_o )
if (rst_in_o)
clkout_en = 0;
else
clkout_en = clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 = pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_in)
if (rst_in) begin
assign pll_locked_tmp2 = 0;
assign clkout_en0 = 0;
assign clkout_en1 = 0;
end
else begin
deassign pll_locked_tmp2;
deassign clkout_en0;
deassign clkout_en1;
end
assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0;
always @(rst_in or locked_out)
if (rst_in == 1)
locked_out_tmp <= #1000 0;
else
locked_out_tmp <= locked_out;
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4] or period_avg ) begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp_t = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp_t = clkin_period[1] - clkin_period[0];
if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2]
+ clkin_period[3] + clkin_period[4])/5;
end
// assign clkinstopped_hold = (clkin_hold_f == 1) ? clkinstopped_out : 0;
always @(clkinstopped_out_dly or rst_in)
if (rst_in)
clkinstopped_hold = 0;
else begin
if (clkinstopped_out)
clkinstopped_hold <= #1 1;
else begin
if (clkin_hold_f)
clkinstopped_hold = 0;
end
end
always @(posedge clkinstopped_out) begin
period_avg_stpi <= period_avg;
pd_stp_p <= #1 1;
@(negedge clkvco)
pd_stp_p <= #1 0;
end
always @(negedge clkvco or posedge rst_in or posedge pd_stp_p)
if (rst_in) begin
period_avg_stp <= 1000;
vco_stp_f <= 0;
end
else if (pd_stp_p)
period_avg_stp <= period_avg_stpi;
else begin
if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin
if (period_vco > 1739)
vco_stp_f <= 1;
else begin
period_avg_stp <= period_avg_stp + 1;
end
end
end
always @(period_avg or lock_period or clkind_div)
if (period_avg > 500 && lock_period == 1) begin
clkin_lost_val = ((period_avg * 1.5) / 500) - 1;
clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1;
end
always @(clkfb_frac_en or clkfbm1_f_div or clkfbm1_div)
begin
if (clkfb_frac_en)
clkfbm1_div_t = clkfbm1_f_div;
else
clkfbm1_div_t = clkfbm1_div;
end
always @(period_avg or clkind_div or clkfbm1_div_t or clkinstopped_hold
or period_avg_stp or posedge rst_clkinstopped_rc)
if (period_avg > 0 ) begin
md_product = clkind_div * clkfbm1_div_t;
m_product = clkfbm1_div_t;
m_product2 = clkfbm1_div_t / 2;
clkvco_div_fint = $rtoi(clkfbm1_div_t/clkind_div);
clkvco_div_frac = (clkfbm1_div_t/clkind_div) - clkvco_div_fint;
if (clkvco_div_frac > 0.000)
clkvco_frac_en = 1;
else
clkvco_frac_en = 0;
period_fb = period_avg * clkind_div;
period_vco_tmp = period_fb / clkfbm1_div_t;
period_vco_rl = 1.0 * period_fb / clkfbm1_div_t;
clkvco_pdrm = (period_avg * clkind_div / clkfbm1_div_t) - period_vco_tmp;
period_vco_mf = period_avg * 8;
if (clkinstopped_hold == 1) begin
if (clkin_hold_f) begin
period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
end
else begin
period_vco = period_avg_stp * clkind_div /clkfbm1_div_t;
period_vco_rl = period_avg_stp * clkind_div /clkfbm1_div_t;
end
end
else
period_vco = period_vco_tmp;
clkfbm1_div_t_int = $rtoi(clkfbm1_div_t);
period_vco_rm = period_fb % clkfbm1_div_t_int;
if (period_vco_rm > 1) begin
if (period_vco_rm > m_product2) begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
if (period_vco_half_rm < 1)
period_vco_half_rm2 = 0;
else
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbm1_div_t;
clkin_dly_t = period_avg * (clkind_div + 1.25);
clkfb_dly_t = period_fb * 2.25 ;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco3 = period_vco * 3/ 8;
period_vco4 = period_vco / 2;
period_vco5 = period_vco * 5 / 8;
period_vco6 = period_vco *3 / 4;
period_vco7 = period_vco * 7 / 8;
end
always @(clkfbm1_ht or clkfbm1_lt or clkfb_frac or clkfb_frac_en or clkfbpmf_sel)
if (clkfb_frac_en == 1 && clkfb_div_adj == 1) begin
if (clkfbpmf_sel < 4) begin
clkfbm1_odd_frac = clkfb_frac;
tmp_fbo = 0.0;
tmp_fbq = 2 * clkfbm1_lt - clkfbm1_ht + 1;
end
else if (clkfbpmf_sel > 4 ) begin
clkfbm1_odd_frac = clkfb_frac + 8;
tmp_fbo = 1.0;
tmp_fbq = 2 * clkfbm1_lt - clkfbm1_ht;
end
else begin
clkfbm1_odd_frac = clkfb_frac + 8;
tmp_fbo = 1.0;
tmp_fbq = 2.0 * clkfbm1_lt - clkfbm1_ht + 1.0;
end
tmp_fbp = clkfbm1_odd_frac / 8.0 - tmp_fbo;
clkfbm1_f_div = 2.0 * tmp_fbq + tmp_fbp + tmp_fbo;
clkfb_div_fint = $rtoi(clkfbm1_f_div);
clkfb_div_frac = clkfbm1_f_div - clkfb_div_fint;
clkfb_div_frac_int = $rtoi(clkfb_div_frac * 8);
clkfb_div_fint_tmp1 = clkfb_div_fint / 2;
clkfb_div_fint_odd = clkfb_div_fint - clkfb_div_fint_tmp1 -clkfb_div_fint_tmp1;
clkfbm1_fht = clkfb_div_fint /2;
clkfbm1_flt = clkfb_div_fint /2;
if (clkfb_div_fint_odd > 0) begin
clkfbm1r_sel = (8 + clkfb_div_frac_int) / 2;
clkfbm1f_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
end
else begin
clkfbm1f_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1r_sel = clkfb_div_frac_int / 2;
end
end
always @(clkfbm1_div_t) begin
mf_product = clkfbm1_div_t * 8;
end
always @(clk0_ht or clk0_lt or clk0_frac or clk0_frac_en or clk0pmf_sel)
if (clk0_frac_en == 1 && clk0_div_adj == 1) begin
if (clk0pmf_sel < 4) begin
clk0_odd_frac = clk0_frac;
tmp_f0o = 0.0;
tmp_f0q = 2 * clk0_lt - clk0_ht + 1;
end
else if (clk0pmf_sel > 4 ) begin
clk0_odd_frac = clk0_frac + 8;
tmp_f0o = 1.0;
tmp_f0q = 2 * clk0_lt - clk0_ht;
end
else begin
clk0_odd_frac = clk0_frac + 8;
tmp_f0o = 1.0;
tmp_f0q = 2.0 * clk0_lt - clk0_ht + 1.0;
end
tmp_f0p = clk0_odd_frac / 8.0 - tmp_f0o;
clk0_f_div = 2.0 * tmp_f0q + tmp_f0p + tmp_f0o;
clk0_div_fint = $rtoi(clk0_f_div);
clk0_div_frac = clk0_f_div - clk0_div_fint;
clk0_div_frac_int = $rtoi(clk0_div_frac * 8);
clk0_div_fint_tmp1 = clk0_div_fint / 2;
clk0_div_fint_odd = clk0_div_fint - clk0_div_fint_tmp1 -clk0_div_fint_tmp1;
clk0_fht = clk0_div_fint /2;
clk0_flt = clk0_div_fint /2;
if (clk0_div_fint_odd > 0) begin
clk0pm_rsel = (8 + clk0_div_frac_int) / 2;
clk0pm_fsel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
end
else begin
clk0pm_fsel = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_rsel = clk0_div_frac_int / 2;
end
end
always @(period_vco_rl or clkfbm1_fht or clkfbm1_flt or clkfbm1r_sel or clkfbm1pm_sel_int) begin
clkfb_frac_ht = period_vco_rl * clkfbm1_fht + (period_vco_rl * clkfbm1pm_sel_int) / 8;
clkfb_frac_lt = period_vco_rl * clkfbm1_flt + (period_vco_rl * clkfbm1r_sel) / 8;
end
always @(period_vco_rl or clk0_fht or clk0_flt or clk0pm_sel_int or clk0pm_rsel) begin
clk0_frac_ht = period_vco_rl * clk0_fht + (period_vco_rl * clk0pm_sel_int) / 8;
clk0_frac_lt = period_vco_rl * clk0_flt + (period_vco_rl * clk0pm_rsel) / 8;
end
always @(period_vco or ps_in_ps)
if (fps_en == 1) begin
period_ps_old = period_ps;
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && psincdec_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @( clkpll_r )
clkpll_tmp1 <= #(period_avg) clkpll_r;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(posedge clkinstopped_out or posedge rst_in)
if ( rst_in)
clkinstopped_vco_f <= 0;
else begin
clkinstopped_vco_f <= 1;
@(negedge clkinstopped_out or posedge rst_in )
if (rst_in)
clkinstopped_vco_f <= 0;
else begin
@(posedge clkpll);
@(posedge clkpll)
clkinstopped_vco_f <= 0;
end
end
always @(posedge clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out1 <= 0;
else begin
clkinstopped_out1 <= 1;
if (clkin_hold_f == 1) begin
@(posedge locked_out or posedge rst_in)
clkinstopped_out1 <= 0;
end
else begin
if (clkinsel_in == 1)
$display(" Warning : input CLKIN1 of %s on instance %m is stopped. Reset is required for %s when input clock returns.", MODULE_NAME, MODULE_NAME);
else
$display(" Warning : input CLKIN2 of %s on instance %m is stopped. Reset is required for %s when input clock returns.", MODULE_NAME, MODULE_NAME);
end
end
always @(posedge clkfbstopped_out or posedge rst_in)
if (rst_in)
clkfbstopped_out1 <= 0;
else begin
clkfbstopped_out1 <= 1;
@(posedge locked_out)
clkfbstopped_out1 <= 0;
end
always @(clkout_en_t)
if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val)
rst_clkinstopped_tm = 1;
else
rst_clkinstopped_tm = 0;
always @(negedge clkinstopped_out or posedge rst_in)
if (rst_in)
rst_clkinstopped <= 0;
else
if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin
@(posedge rst_clkinstopped_tm)
rst_clkinstopped <= #period_vco4 1;
@(negedge rst_clkinstopped_tm ) begin
rst_clkinstopped <= #period_vco5 0;
rst_clkinstopped_rc <= #period_vco6 1;
rst_clkinstopped_rc <= #period_vco7 0;
end
end
always @(posedge clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out_dly <= 0;
else begin
clkinstopped_out_dly <= 1;
if (clkin_hold_f == 1) begin
@(negedge rst_clkinstopped_rc or posedge rst_in)
clkinstopped_out_dly <= 0;
end
end
always @(clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out_dly2 <= 0;
else
clkinstopped_out_dly2 <= #2 clkinstopped_out;
always @(negedge rst_clkinstopped or posedge rst_in)
if (rst_in)
rst_clkinstopped_lk <= 0;
else begin
rst_clkinstopped_lk <= 1;
@(posedge locked_out)
rst_clkinstopped_lk <= 0;
end
always @(clkinstopped_vco_f or clkinstopped_out1 or clkvco_lk or
clkvco_lk_tmp or rst_in)
if (rst_in)
clkvco_lk = 0;
else begin
if (clkinstopped_out1 == 1 && clkin_stop_f == 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else if (clkinstopped_vco_f == 1 && period_vco_half > 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else
clkvco_lk = clkvco_lk_tmp;
end
always @(posedge clkpll)
if (clkfb_frac_en == 1 || clkvco_frac_en == 1) begin
if (pll_locked_tm ==1 ) begin
clkvco_lk_tmp <= 1;
cmpvco = 0.0;
for (ik1=1; ik1 < mf_product; ik1=ik1+1) begin
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( cmpvco >= 1.0 ) begin
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco - 1.0 + clkvco_pdrm;
end
else if ( cmpvco <= -1.0 ) begin
#(period_vco_half_rm2) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + 1.0 + clkvco_pdrm;
end
else begin
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + clkvco_pdrm;
end
clkout_en_t <= ik1;
end
clkout_en_t <= ik1;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
else begin
if (pll_locked_tm ==1) begin
clkvco_lk_tmp <= 1;
clkvco_rm_cnt = 0;
clkout_en_t <= 0;
vcoflag = 0;
if ( period_vco_cmp_flag == 1) begin
vcoflag = 1;
for (ik2=1; ik2 < m_product; ik2=ik2+1) begin
clkout_en_t <= ik2;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
// #(period_vco_half1) clkvco_lk_tmp <= 1;
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik2;
end
else if ( period_vco_cmp_flag == 2 ) begin
vcoflag = 1;
for (ik3=1; ik3 < m_product; ik3=ik3+1) begin
clkout_en_t <= ik3;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik3;
end
else begin
vcoflag = 1;
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
end
#(period_vco_half) clkvco_lk_tmp <= 0;
// if (clkpll == 1) begin
if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) begin
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
end
always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or clkfbm1pm_rl
or lock_period or ps_in_ps )
if (lock_period == 1) begin
if (clkfb_frac_en == 1) begin
// fbm1_comp_delay = 0;
// val_tmp = period_vco * mf_product ;
// val_tmp = period_vco_mf;
val_tmp = period_avg * DIVCLK_DIVIDE;
fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl);
end
else begin
val_tmp = period_avg * DIVCLK_DIVIDE;
fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl);
end
dly_tmp1 = fb_delay + fbm1_comp_delay;
dly_tmp_int = 1;
if (clkfb_fps_en == 1) begin
if (ps_in_ps < 0) begin
tmp_ps_val1 = -1 * ps_in_ps;
tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0;
if (tmp_ps_val2 > dly_tmp1 ) begin
dly_tmp_int = -1;
dly_tmp = tmp_ps_val2 - dly_tmp1;
end
else if (tmp_ps_val2 == dly_tmp1 ) begin
dly_tmp_int = 0;
dly_tmp = 0;
end
else begin
dly_tmp_int = 1;
dly_tmp = dly_tmp1 - tmp_ps_val2;
end
end
else
dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0;
end
else
dly_tmp = dly_tmp1;
if (dly_tmp_int < 0)
clkvco_delay = dly_tmp;
else begin
if (clkfb_frac_en == 1 && dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
end
always @(period_vco or ps_in_ps )
if (fps_en == 1) begin
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && psincdec_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @(clkfbm1pm_sel)
case (clkfbm1pm_sel)
3'b000 : clkfbm1pm_rl = 0.0;
3'b001 : clkfbm1pm_rl = 0.125;
3'b010 : clkfbm1pm_rl = 0.25;
3'b011 : clkfbm1pm_rl = 0.375;
3'b100 : clkfbm1pm_rl = 0.50;
3'b101 : clkfbm1pm_rl = 0.625;
3'b110 : clkfbm1pm_rl = 0.75;
3'b111 : clkfbm1pm_rl = 0.875;
endcase
always @(clkvco_lk)
clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk;
always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm)
if ( pll_locked_tm && vco_stp_f == 0) begin
if (dly_tmp == 0)
clkvco = clkvco_lk;
else
clkvco = clkvco_lk_dly_tmp;
end
else
clkvco = 0;
always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge or clk0_frac_en)
if (clk0_frac_en == 0)
clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge);
always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge)
clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge);
always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge)
clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge);
always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge)
clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge);
always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge)
clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge);
always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge)
clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge);
always @(clk6_ht or clk6_lt or clk6_nocnt or init_trig or clk6_edge)
clkout_pm_cal(clk6_ht1, clk6_div, clk6_div1, clk6_ht, clk6_lt, clk6_nocnt, clk6_edge);
always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfb_frac_en)
if (clkfb_frac_en == 0) begin
clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge);
end
always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge)
clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge);
always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge)
clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge);
always @(posedge psclk_in or posedge rst_in)
if (rst_in) begin
ps_in_ps <= ps_in_init;
ps_cnt <= 0;
psen_w <= 0;
end
else if (fps_en == 1) begin
if (psen_in) begin
if (psen_w == 1)
$display(" Error : PSEN on %s instance %m is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period.", MODULE_NAME, $time);
psen_w <= 1;
if (ps_lock == 1)
$display(" Warning : Please wait for PSDONE signal on %s instance %m at time %t before adjusting the Phase Shift.", MODULE_NAME, $time);
else if (psincdec_in == 1) begin
if (ps_cnt < ps_max)
ps_cnt <= ps_cnt + 1;
else
ps_cnt <= 0;
if (ps_in_ps < ps_max)
ps_in_ps <= ps_in_ps + 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
else if (psincdec_in == 0) begin
ps_cnt_neg = (-1) * ps_cnt;
ps_in_ps_neg = (-1) * ps_in_ps;
if (ps_cnt_neg < ps_max)
ps_cnt <= ps_cnt - 1;
else
ps_cnt <= 0;
if (ps_in_ps_neg < ps_max)
ps_in_ps <= ps_in_ps - 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
end
else
psen_w <= 0;
if ( psdone_out == 1)
ps_lock <= 0;
end
always @(posedge ps_lock )
if (fps_en == 1) begin
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
begin
psdone_out = 1;
@(posedge psclk_in);
psdone_out = 0;
end
end
always @(rst_in_o)
if (rst_in_o) begin
assign clkout_mux = 8'b0;
assign clkout_ps_mux = 8'b0;
assign clkout_ps = 0;
assign clkout_ps_tmp1 = 0;
assign clkout_ps_tmp2 = 0;
assign clk0_frac_out = 0;
assign clkfbm1_frac_out = 0;
end
else begin
deassign clkout_mux;
deassign clkout_ps_mux;
deassign clkout_ps;
deassign clkout_ps_tmp1;
deassign clkout_ps_tmp2;
deassign clk0_frac_out;
deassign clkfbm1_frac_out;
end
always @(rst_clkinstopped)
if (rst_clkinstopped) begin
assign clkfb_frac_ht = 50;
assign clkfb_frac_lt = 50;
end
else begin
deassign clkfb_frac_ht;
deassign clkfb_frac_lt;
end
//always @(clkvco or clkout_en )
always @(clkvco)
if (clkout_en) begin
clkout_mux[0] = clkvco;
clkout_mux[1] <= #(period_vco1) clkvco;
clkout_mux[2] <= #(period_vco2) clkvco;
clkout_mux[3] <= #(period_vco3) clkvco;
clkout_mux[4] <= #(period_vco4) clkvco;
clkout_mux[5] <= #(period_vco5) clkvco;
clkout_mux[6] <= #(period_vco6) clkvco;
clkout_mux[7] <= #(period_vco7) clkvco;
end
always @(clkout_ps or clkout_en )
if (clkout_en) begin
clkout_ps_mux[0] = clkout_ps;
clkout_ps_mux[1] <= #(period_vco1) clkout_ps;
clkout_ps_mux[2] <= #(period_vco2) clkout_ps;
clkout_ps_mux[3] <= #(period_vco3) clkout_ps;
clkout_ps_mux[4] <= #(period_vco4) clkout_ps;
clkout_ps_mux[5] <= #(period_vco5) clkout_ps;
clkout_ps_mux[6] <= #(period_vco6) clkout_ps;
clkout_ps_mux[7] <= #(period_vco7) clkout_ps;
end
always @(clkvco or clkout_en )
if ( fps_en == 1) begin
clkvco_ps_tmp1 <= #(period_ps) clkvco;
clkvco_ps_tmp2 <= #(period_ps_old) clkvco;
end
always @(negedge clkout_ps)
clkout_ps_eg <= $time;
always @(posedge clkout_ps)
clkout_ps_peg <= $time;
always @(ps_lock)
ps_lock_dly <= #1 ps_lock;
always @(posedge ps_lock_dly)
if ((period_ps - period_ps_old) > period_vco_half ) begin
if (clkout_ps == 0) begin
if (clkvco_ps_tmp2 == 1) begin
clkout_ps_w = $time - clkout_ps_eg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(negedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
else begin
if (clkvco_ps_tmp2 == 0) begin
clkout_ps_w = $time - clkout_ps_peg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(posedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
@(posedge clkvco_ps_tmp2);
@(negedge clkvco_ps_tmp2)
if (clkvco_ps_tmp1 == 0)
clkvco_ps_tmp2_en <= 0;
else
@(negedge clkvco_ps_tmp1)
clkvco_ps_tmp2_en <= 0;
end
always @(clkvco or clkvco_ps_tmp1 or clkvco_ps_tmp2 or clkvco_ps_tmp2_en )
if (fps_en == 1) begin
if (ps_in_ps == 0 )
clkout_ps = clkvco;
else if (clkvco_ps_tmp2_en == 1)
clkout_ps = clkvco_ps_tmp2;
else
clkout_ps = clkvco_ps_tmp1;
end
assign clk0_sel_mux = (clk0_fps_en == 1) ? clkout_ps_mux : clkout_mux;
assign clkfb_sel_mux = (clkfb_fps_en == 1) ? clkout_ps_mux : clkout_mux;
assign clk0in = (clk0_fps_en == 1) ? clkout_ps_mux[clk0pm_sel] : clkout_mux[clk0pm_sel1];
assign clk1in = (clk1_fps_en == 1) ? clkout_ps_mux[clk1pm_sel] : clkout_mux[clk1pm_sel];
assign clk2in = (clk2_fps_en == 1) ? clkout_ps_mux[clk2pm_sel] : clkout_mux[clk2pm_sel];
assign clk3in = (clk3_fps_en == 1) ? clkout_ps_mux[clk3pm_sel] : clkout_mux[clk3pm_sel];
assign clk4in = (clk4_fps_en == 1) ? clkout_ps_mux[clk4pm_sel] : ((clkout4_cascade_int == 1) ? clk6_out : clkout_mux[clk4pm_sel]);
assign clk5in = (clk5_fps_en == 1) ? clkout_ps_mux[clk5pm_sel] : clkout_mux[clk5pm_sel];
assign clk6in = (clk6_fps_en == 1) ? clkout_ps_mux[clk6pm_sel] : clkout_mux[clk6pm_sel];
assign clkfbm1in = (clkfb_fps_en == 1) ? clkout_ps_mux[clkfbm1pm_sel] : clkout_mux[clkfbm1pm_sel1];
assign clkfbm1pm_sel1 = clkfbm1pm_sel;
assign clk0pm_sel1 = clk0pm_sel;
assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0;
assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0;
assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0;
assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0;
assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0;
assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0;
assign clk6ps_en = (clk6_dly_cnt == clkout6_dly) ? clkout_en : 0;
assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0;
always @(posedge clk0in)
if (clk0ps_en && clk0_frac_en) begin
clk0_frac_out <= 1;
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
#(clk0_frac_ht) clk0_frac_out <= 0;
#(clk0_frac_lt) clk0_frac_out <= 1;
end
#(clk0_frac_ht) clk0_frac_out <= 0;
#(clk0_frac_lt - period_vco1);
end
always @(posedge clkfbm1in)
if (clkfbm1ps_en && clkfb_frac_en) begin
clkfbm1_frac_out <= 1;
for (ib=1; ib < 8; ib=ib+1) begin
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt) clkfbm1_frac_out <= 1;
end
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt - period_vco1);
end
else
clkfbm1_frac_out <= 0;
always @(negedge clk0in or posedge rst_in_o)
if (rst_in_o)
clk0_dly_cnt <= 6'b0;
// else if (clkout_en == 1 && clk0_frac_en == 0) begin
else if (clkout_en == 1 ) begin
if (clk0_dly_cnt < clkout0_dly)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in_o)
if (rst_in_o)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clkout1_dly && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
always @(negedge clk2in or posedge rst_in_o)
if (rst_in_o)
clk2_dly_cnt <= 6'b0;
else
if (clk2_dly_cnt < clkout2_dly && clkout_en ==1)
clk2_dly_cnt <= clk2_dly_cnt + 1;
always @(negedge clk3in or posedge rst_in_o)
if (rst_in_o)
clk3_dly_cnt <= 6'b0;
else
if (clk3_dly_cnt < clkout3_dly && clkout_en ==1)
clk3_dly_cnt <= clk3_dly_cnt + 1;
always @(negedge clk4in or posedge rst_in_o)
if (rst_in_o)
clk4_dly_cnt <= 6'b0;
else
if (clk4_dly_cnt < clkout4_dly && clkout_en ==1)
clk4_dly_cnt <= clk4_dly_cnt + 1;
always @(negedge clk5in or posedge rst_in_o)
if (rst_in_o)
clk5_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk5_dly_cnt < clkout5_dly)
clk5_dly_cnt <= clk5_dly_cnt + 1;
end
always @(negedge clk6in or posedge rst_in_o)
if (rst_in_o)
clk6_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk6_dly_cnt < clkout6_dly)
clk6_dly_cnt <= clk6_dly_cnt + 1;
end
always @(negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o)
clkfbm1_dly_cnt <= 6'b0;
// else if (clkout_en == 1 && clkfb_frac_en == 0) begin
else if (clkout_en == 1 ) begin
if (clkfbm1_dly_cnt < clkfbm1_dly)
clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
end
always @(posedge clk0in or negedge clk0in or posedge rst_in_o)
if (rst_in_o) begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
else if (clk0ps_en && clk0_frac_en == 0) begin
if (clk0_cnt < clk0_div1)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 8'b0;
if (clk0_cnt < clk0_ht1)
clk0_nf_out <= 1;
else
clk0_nf_out <= 0;
end
else begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
assign clk0_out = (clk0_frac_en) ? clk0_frac_out : clk0_nf_out;
always @(posedge clk1in or negedge clk1in or posedge rst_in_o)
if (rst_in_o) begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
else if (clk1ps_en) begin
if (clk1_cnt < clk1_div1)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 8'b0;
if (clk1_cnt < clk1_ht1)
clk1_out <= 1;
else
clk1_out <= 0;
end
else begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
always @(posedge clk2in or negedge clk2in or posedge rst_in_o)
if (rst_in_o) begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
else if (clk2ps_en) begin
if (clk2_cnt < clk2_div1)
clk2_cnt <= clk2_cnt + 1;
else
clk2_cnt <= 8'b0;
if (clk2_cnt < clk2_ht1)
clk2_out <= 1;
else
clk2_out <= 0;
end
else begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
always @(posedge clk3in or negedge clk3in or posedge rst_in_o)
if (rst_in_o) begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
else if (clk3ps_en) begin
if (clk3_cnt < clk3_div1)
clk3_cnt <= clk3_cnt + 1;
else
clk3_cnt <= 8'b0;
if (clk3_cnt < clk3_ht1)
clk3_out <= 1;
else
clk3_out <= 0;
end
else begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
always @(posedge clk4in or negedge clk4in or posedge rst_in_o)
if (rst_in_o) begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
else if (clk4ps_en) begin
if (clk4_cnt < clk4_div1)
clk4_cnt <= clk4_cnt + 1;
else
clk4_cnt <= 8'b0;
if (clk4_cnt < clk4_ht1)
clk4_out <= 1;
else
clk4_out <= 0;
end
else begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
always @(posedge clk5in or negedge clk5in or posedge rst_in_o)
if (rst_in_o) begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
// else if (clk5ps_en && clk0_frac_en == 0) begin
else if (clk5ps_en ) begin
if (clk5_cnt < clk5_div1)
clk5_cnt <= clk5_cnt + 1;
else
clk5_cnt <= 8'b0;
if (clk5_cnt < clk5_ht1)
clk5_out <= 1;
else
clk5_out <= 0;
end
else begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
always @(posedge clk6in or negedge clk6in or posedge rst_in_o)
if (rst_in_o) begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
// else if (clk6ps_en && clkfb_frac_en == 0) begin
else if (clk6ps_en ) begin
if (clk6_cnt < clk6_div1)
clk6_cnt <= clk6_cnt + 1;
else
clk6_cnt <= 8'b0;
if (clk6_cnt < clk6_ht1)
clk6_out <= 1;
else
clk6_out <= 0;
end
else begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o) begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
else if (clkfbm1ps_en && clkfb_frac_en == 0) begin
if (clkfbm1_cnt < clkfbm1_div1)
clkfbm1_cnt <= clkfbm1_cnt + 1;
else
clkfbm1_cnt <= 8'b0;
if (clkfbm1_cnt < clkfbm1_ht1)
clkfbm1_nf_out <= 1;
else
clkfbm1_nf_out <= 0;
end
else begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
assign clkfbm1_out = (clkfb_frac_en) ? clkfbm1_frac_out : clkfbm1_nf_out;
always @(posedge clkfb_in or negedge clkfb_in or posedge rst_in)
if (rst_in) begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
else if (clkout_en) begin
if (clkfbm2_cnt < clkfbm2_div1)
clkfbm2_cnt <= clkfbm2_cnt + 1;
else
clkfbm2_cnt <= 8'b0;
if (clkfbm2_cnt < clkfbm2_ht1)
clkfbm2_out <= 1;
else
clkfbm2_out <= 0;
end
else begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
always @(posedge clkpll_r or negedge clkpll_r or posedge rst_in)
if (rst_in) begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
else if (clkout_en) begin
if (clkind_cnt < clkind_div1)
clkind_cnt <= clkind_cnt + 1;
else
clkind_cnt <= 8'b0;
if (clkind_cnt < clkind_ht1)
clkind_out <= 1;
else
clkind_out <= 0;
end
else begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
always @(clk0_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout0_out = clk0_out;
else
clkout0_out = clkfb_tst;
always @(clk1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout1_out = clk1_out;
else
clkout1_out = clkfb_tst;
always @(clk2_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout2_out = clk2_out;
else
clkout2_out = clkfb_tst;
always @(clk3_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout3_out = clk3_out;
else
clkout3_out = clkfb_tst;
always @(clk4_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout4_out = clk4_out;
else
clkout4_out = clkfb_tst;
always @(clk5_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout5_out = clk5_out;
else
clkout5_out = clkfb_tst;
always @(clk6_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout6_out = clk6_out;
else
clkout6_out = clkfb_tst;
always @(clkfbm1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkfb_out = clkfbm1_out;
else
clkfb_out = clkfb_tst;
//
// determine feedback delay
//
// always @(rst_in)
// if (rst_in)
// assign clkfb_tst = 0;
// else
// deassign clkfb_tst;
always @(posedge clkpll_r )
if (fb_delay_found_tmp == 0 && pwron_int == 0 && rst_in == 0) begin
clkfb_tst <= 1'b1;
end
else
clkfb_tst <= 1'b0;
always @( posedge clkfb_tst or posedge rst_in )
if (rst_in)
delay_edge <= 0;
else
delay_edge <= $time;
always @(posedge clkfb_in or posedge rst_in )
if (rst_in) begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
else
if (fb_delay_found_tmp ==0 ) begin
if ( delay_edge != 0)
fb_delay <= ($time - delay_edge);
else
fb_delay <= 0;
fb_delay_found_tmp <= 1;
end
always @(rst_in)
if (rst_in)
assign fb_delay_found = 0;
else
deassign fb_delay_found;
always @(fb_delay_found_tmp or clkvco_delay )
if (clkvco_delay == 0)
fb_delay_found <= #1000 fb_delay_found_tmp;
else
fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp;
always @(fb_delay)
if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning : The feedback delay on %s instance %m at time %t is %f ns. It is over the maximun value %f ns.", MODULE_NAME, MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max);
end
//
// generate unlock signal
//
always begin
if (rst_in)
clk_osc = 0;
else
clk_osc = ~clk_osc;
#OSC_P2;
end
always @(posedge clkpll_r or negedge clkpll_r) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge clkfb_in or negedge clkfb_in) begin
clkfb_p <= 1;
clkfb_p <= #100 0;
end
always @(posedge clk_osc or posedge rst_in or posedge clkin_p)
if (rst_in == 1) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out == 1) begin
@(posedge clkpll_r) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out <= 0;
end
else
clkinstopped_out <= 1;
end
always @(posedge clk_osc or posedge rst_in or posedge clkfb_p)
if (rst_in == 1 || clkfb_p == 1) begin
clkfbstopped_out <= 0;
clkfb_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfb_lost_cnt < clkfb_lost_val) begin
clkfb_lost_cnt <= clkfb_lost_cnt + 1;
clkfbstopped_out <= 0;
end
else
clkfbstopped_out <= 1;
end
always @(clkin_jit or rst_in )
if (rst_in)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2 && clkfbstopped_out == 0 && clkinstopped_out == 0) begin
if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// tasks
task clkout_dly_real_cal;
output [5:0] clkout_dly;
output [2:0] clkpm_sel;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
// integer clkdiv;
real clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clkout_dly_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
clkout_dly_tmp = $rtoi(clk_dly_rl);
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of %s", clk_ps_name, MODULE_NAME, clk_ps, MODULE_NAME);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
clk_dly_rem = clk_dly_rl - clkout_dly;
if (clk_dly_rem < 0.125)
clkpm_sel = 0;
else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25)
clkpm_sel = 1;
else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375)
clkpm_sel = 2;
else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5)
clkpm_sel = 3;
else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625)
clkpm_sel = 4;
else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75)
clkpm_sel = 5;
else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875)
clkpm_sel = 6;
else if (clk_dly_rem >= 0.875 )
clkpm_sel = 7;
if (clk_ps < 0.0)
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0;
else
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv;
if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, MODULE_NAME, clk_ps, clk_ps_rl);
end
endtask
task clkout_dly_cal;
output [5:0] clkout_dly;
output [2:0] clkpm_sel;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
integer clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clkout_dly_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
clkout_dly_tmp = $rtoi(clk_dly_rl);
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of %s", clk_ps_name, MODULE_NAME, clk_ps, MODULE_NAME);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
clk_dly_rem = clk_dly_rl - clkout_dly;
if (clk_dly_rem < 0.125)
clkpm_sel = 0;
else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25)
clkpm_sel = 1;
else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375)
clkpm_sel = 2;
else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5)
clkpm_sel = 3;
else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625)
clkpm_sel = 4;
else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75)
clkpm_sel = 5;
else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875)
clkpm_sel = 6;
else if (clk_dly_rem >= 0.875 )
clkpm_sel = 7;
if (clk_ps < 0.0)
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0;
else
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv;
if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, MODULE_NAME, clk_ps, clk_ps_rl);
end
endtask
task clk_out_para_cal;
output [6:0] clk_ht;
output [6:0] clk_lt;
output clk_nocnt;
output clk_edge;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
integer CLKOUT_DIVIDE;
real CLKOUT_DUTY_CYCLE;
real tmp_value, tmp_value0, tmp_value_rm;
integer tmp_value_round, tmp_value1, tmp_value_r;
real tmp_value2;
real tmp_value_rm1, tmp_value_r1;
integer tmp_value_r2;
begin
tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE;
tmp_value_r = $rtoi(tmp_value0);
tmp_value_rm = tmp_value0 - tmp_value_r;
if (tmp_value_rm < 0.1)
tmp_value = tmp_value_r * 1.0;
else if (tmp_value_rm > 0.9)
tmp_value = 1.0 * tmp_value_r + 1.0;
else begin
tmp_value_r1 = tmp_value0 * 2.0;
tmp_value_r2 = $rtoi(tmp_value_r1);
tmp_value_rm1 = tmp_value_r1 - tmp_value_r2;
if (tmp_value_rm1 > 0.995)
tmp_value = tmp_value0 + 0.002;
else
tmp_value = tmp_value0;
end
tmp_value_round = tmp_value * 2.0;
tmp_value1 = tmp_value_round % 2;
tmp_value2 = CLKOUT_DIVIDE - tmp_value;
if ((tmp_value2) >= O_MAX_HT_LT) begin
clk_lt = 7'b1000000;
end
else begin
if (tmp_value2 < 1.0)
clk_lt = 1;
else
if ( tmp_value1 != 0)
clk_lt = $rtoi(tmp_value2) + 1;
else
clk_lt = $rtoi(tmp_value2);
end
if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT)
clk_ht = 7'b1000000;
else
clk_ht = CLKOUT_DIVIDE - clk_lt;
clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0;
if ( tmp_value < 1.0)
clk_edge = 1;
else if (tmp_value1 != 0)
clk_edge = 1;
else
clk_edge = 0;
end
endtask
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.0;
CLK_DUTY_CYCLE_MIN_rnd = 0.0;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
end
CLK_DUTY_CYCLE_CHK = 1.0;
CLK_DUTY_CYCLE_MAX = 1.0;
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
end
clkout_duty_chk = 1'b1;
end
endfunction
function para_int_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
integer para_in;
integer range_low;
integer range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on %s instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, MODULE_NAME, para_in, range_low, range_high);
$finish;
end
para_int_range_chk = 1'b1;
end
endfunction
function para_real_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
real para_in;
real range_low;
real range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on %s instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, MODULE_NAME, para_in, range_low, range_high);
$finish;
end
para_real_range_chk = 1'b0;
end
endfunction
task clkout_pm_cal;
output [7:0] clk_ht1;
output [7:0] clk_div;
output [7:0] clk_div1;
input [6:0] clk_ht;
input [6:0] clk_lt;
input clk_nocnt;
input clk_edge;
begin
if (clk_nocnt ==1) begin
clk_div = 8'b00000001;
clk_div1 = 8'b00000001;
clk_ht1 = 8'b00000001;
end
else begin
if ( clk_edge == 1)
clk_ht1 = 2 * clk_ht + 1;
else
clk_ht1 = 2 * clk_ht;
clk_div = clk_ht + clk_lt ;
clk_div1 = 2 * clk_div -1;
end
end
endtask
task clkout_delay_para_drp;
output [5:0] clkout_dly;
output clk_nocnt;
output clk_edge;
input [15:0] di_in;
input [6:0] daddr_in;
begin
clkout_dly = di_in[5:0];
clk_nocnt = di_in[6];
clk_edge = di_in[7];
end
endtask
task clkout_hl_para_drp;
output [6:0] clk_lt;
output [6:0] clk_ht;
output [2:0] clkpm_sel;
input [15:0] di_in_tmp;
input [6:0] daddr_in_tmp;
input clk_frac_en;
begin
// if (di_in_tmp[12] != 1) begin
// $display(" Error : %s on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", MODULE_NAME, di_in_tmp, daddr_in_tmp, $time);
// end
if (( di_in_tmp[5:0] == 6'b0) && (clk_frac_en == 1'b0))
clk_lt = 7'b1000000;
else
clk_lt = { 1'b0, di_in_tmp[5:0]};
if ((di_in_tmp[11:6] == 6'b0) && (clk_frac_en == 1'b0))
clk_ht = 7'b1000000;
else
clk_ht = { 1'b0, di_in_tmp[11:6]};
clkpm_sel = di_in_tmp[15:13];
end
endtask
specify
(CLKIN1 => LOCKED) = (100:100:100, 100:100:100);
(CLKIN2 => LOCKED) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(RST => LOCKED) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(PSCLK => PSDONE) = (100:100:100, 100:100:100);
(RST => CLKFBSTOPPED) = (100:100:100, 100:100:100);
(RST => CLKINSTOPPED) = (100:100:100, 100:100:100);
(DCLK => DO) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKIN2, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge PSCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, delay_PSCLK, delay_PSEN);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, delay_PSCLK, delay_PSINCDEC);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, delay_PSCLK, delay_PSEN);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, delay_PSCLK, delay_PSINCDEC);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MMCME2_BASE.v 0000664 0000000 0000000 00000011452 12327044266 0023137 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.11)
// \ \ Description :
// / /
// /__/ /\ Filename : MMCME2_BASE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/27/10 - Initial version
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_BASE (
CLKFBOUT,
CLKFBOUTB,
CLKOUT0,
CLKOUT0B,
CLKOUT1,
CLKOUT1B,
CLKOUT2,
CLKOUT2B,
CLKOUT3,
CLKOUT3B,
CLKOUT4,
CLKOUT5,
CLKOUT6,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter real CLKFBOUT_MULT_F = 5.000;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter real CLKOUT0_DIVIDE_F = 1.000;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter CLKOUT4_CASCADE = "FALSE";
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer CLKOUT6_DIVIDE = 1;
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
parameter real CLKOUT6_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CLKFBOUT;
output CLKFBOUTB;
output CLKOUT0;
output CLKOUT0B;
output CLKOUT1;
output CLKOUT1B;
output CLKOUT2;
output CLKOUT2B;
output CLKOUT3;
output CLKOUT3B;
output CLKOUT4;
output CLKOUT5;
output CLKOUT6;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
MMCME2_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.REF_JITTER1(REF_JITTER1)
)
mmcm_adv_1 (
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.CLKFBSTOPPED(OPEN_FBS),
.CLKINSTOPPED(OPEN_INS),
.PSDONE(OPEN_PSDONE),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MMCME3_ADV.v 0000664 0000000 0000000 00000433323 12327044266 0023045 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : MMCME3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/21/2013 - YML changes
// 03/22/2013 - 708090 - Change error to Warning
// 03/27/2013 - Update with writer notation
// 04/04/2013 - 709484 - Add PFD check
// 04/04/2013 - 709093 - Fix periods after DRP
// 04/12/2013 - invertible pin changes
// 04/22/2013 - 713991 - Fix cddcdone assertion
// 04/24/2013 - 709726 - fix vcoflag
// 05/07/2013 - 714319 - fix phase warning
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter real CLKIN_FREQ_MAX = 1066.0,
parameter real CLKIN_FREQ_MIN = 10.0,
parameter real CLKPFD_FREQ_MAX = 550.0,
parameter real CLKPFD_FREQ_MIN = 10.0,
parameter real VCOCLK_FREQ_MAX = 1600.0,
parameter real VCOCLK_FREQ_MIN = 600.0,
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter CLKFBOUT_USE_FINE_PS = "FALSE",
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter CLKOUT0_USE_FINE_PS = "FALSE",
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUT1_USE_FINE_PS = "FALSE",
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter CLKOUT6_USE_FINE_PS = "FALSE",
parameter COMPENSATION = "AUTO",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN2_INVERTED = 1'b0,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PSEN_INVERTED = 1'b0,
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter integer SS_MOD_PERIOD = 10000,
parameter STARTUP_WAIT = "FALSE"
)(
output CDDCDONE,
output CLKFBOUT,
output CLKFBOUTB,
output CLKFBSTOPPED,
output CLKINSTOPPED,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output [15:0] DO,
output DRDY,
output LOCKED,
output PSDONE,
input CDDCREQ,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PSCLK,
input PSEN,
input PSINCDEC,
input PWRDWN,
input RST
);
tri0 GSR = glbl.GSR;
tri1 p_up;
wire glock;
localparam MODULE_NAME = "MMCME3_ADV";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
`ifndef XIL_TIMING
localparam real CLKIN_FREQ_MAX = 1066.0;
localparam real CLKIN_FREQ_MIN = 10.0;
localparam real CLKPFD_FREQ_MAX = 550.0;
localparam real CLKPFD_FREQ_MIN = 10.0;
localparam real VCOCLK_FREQ_MAX = 1600.0;
localparam real VCOCLK_FREQ_MIN = 600.0;
`endif //
localparam VCOCLK_FREQ_TARGET = 1000;
localparam M_MIN = 2.000;
localparam M_MAX = 64.000;
localparam D_MIN = 1;
localparam D_MAX = 106;
localparam O_MIN = 1;
localparam O_MAX = 128;
localparam O_MAX_HT_LT = 64;
localparam REF_CLK_JITTER_MAX = 1000;
localparam REF_CLK_JITTER_SCALE = 0.1;
localparam MAX_FEEDBACK_DELAY = 10.0;
localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
localparam ps_max = 55;
localparam OSC_P2 = 250;
`ifndef XIL_DR
localparam [72:1] BANDWIDTH_REG = BANDWIDTH;
localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F;
localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE;
localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS;
localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD;
localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD;
localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX;
localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN;
localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F;
localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE;
localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE;
localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS;
localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE;
localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE;
localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE;
localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS;
localparam [7:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE;
localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE;
localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE;
localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS;
localparam [7:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE;
localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE;
localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE;
localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS;
localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE;
localparam [7:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE;
localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE;
localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE;
localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS;
localparam [7:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE;
localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE;
localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE;
localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS;
localparam [7:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE;
localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE;
localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE;
localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS;
localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX;
localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN;
localparam [64:1] COMPENSATION_REG = COMPENSATION;
localparam [6:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_CLKIN2_INVERTED_REG = IS_CLKIN2_INVERTED;
localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED;
localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED;
localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REF_JITTER1_REG = REF_JITTER1;
localparam real REF_JITTER2_REG = REF_JITTER2;
localparam [40:1] SS_EN_REG = SS_EN;
localparam [88:1] SS_MODE_REG = SS_MODE;
localparam [15:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD;
localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT;
localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX;
localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN;
`endif
wire IS_CLKFBIN_INVERTED_BIN;
wire IS_CLKIN1_INVERTED_BIN;
wire IS_CLKIN2_INVERTED_BIN;
wire IS_CLKINSEL_INVERTED_BIN;
wire IS_PSEN_INVERTED_BIN;
wire IS_PSINCDEC_INVERTED_BIN;
wire IS_PWRDWN_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr =1'b0;
reg attr_err = 1'b0;
reg trig_attr_chk;
`ifdef XIL_DR
`include "MMCME3_ADV_dr.v"
`endif
wire CDDCREQ_in;
wire CLKFBIN_in;
wire CLKIN1_in;
wire CLKIN2_in;
wire CLKINSEL_in;
wire CLKINSEL_int;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire PSCLK_in;
wire PSEN_in;
wire PSINCDEC_in;
wire PWRDWN_in;
wire RST_in;
wire [15:0] DI_in;
wire [6:0] DADDR_in;
wire CDDCREQ_delay;
wire CLKFBIN_delay;
wire CLKIN1_delay;
wire CLKIN2_delay;
wire CLKINSEL_delay;
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire PSCLK_delay;
wire PSEN_delay;
wire PSINCDEC_delay;
wire PWRDWN_delay;
wire RST_delay;
wire [15:0] DI_delay;
wire [6:0] DADDR_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DCLK_delay = DCLK;
assign #(inclk_delay) PSCLK_delay = PSCLK;
assign #(in_delay) DADDR_delay = DADDR;
assign #(in_delay) DEN_delay = DEN;
assign #(in_delay) DI_delay = DI;
assign #(in_delay) DWE_delay = DWE;
assign #(in_delay) PSEN_delay = PSEN;
assign #(in_delay) PSINCDEC_delay = PSINCDEC;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) CDDCREQ_delay = CDDCREQ;
assign #(in_delay) CLKFBIN_delay = CLKFBIN;
assign #(in_delay) CLKIN1_delay = CLKIN1;
assign #(in_delay) CLKIN2_delay = CLKIN2;
assign #(in_delay) CLKINSEL_delay = CLKINSEL;
assign #(in_delay) PWRDWN_delay = PWRDWN;
assign #(in_delay) RST_delay = RST;
assign CDDCREQ_in = CDDCREQ_delay;
assign CLKFBIN_in = CLKFBIN_delay ^ IS_CLKFBIN_INVERTED_BIN;
assign CLKIN1_in = CLKIN1_delay ^ IS_CLKIN1_INVERTED_BIN;
assign CLKIN2_in = CLKIN2_delay ^ IS_CLKIN2_INVERTED_BIN;
assign CLKINSEL_int = CLKINSEL_delay ^ IS_CLKINSEL_INVERTED_BIN;
assign CLKINSEL_in = (CLKINSEL_int === 0) ? 0 : 1;
assign DADDR_in = DADDR_delay;
assign DCLK_in = DCLK_delay;
assign DEN_in = DEN_delay;
assign DI_in = DI_delay;
assign DWE_in = DWE_delay;
assign PSCLK_in = PSCLK_delay;
assign PSEN_in = PSEN_delay ^ IS_PSEN_INVERTED_BIN;
assign PSINCDEC_in = PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_BIN;
assign PWRDWN_in = PWRDWN_delay ^ IS_PWRDWN_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
integer pchk_tmp1, pchk_tmp2;
integer clkfb_div_frac_int, clk0_div_frac_int, clkfb_div_fint, clk0_div_fint, clkvco_div_fint;
integer clkfb_div_fint_tmp1, clkfb_div_fint_odd;
integer clk0_div_fint_tmp1, clk0_div_fint_odd;
real clkfb_div_frac, clk0_div_frac, clkvco_div_frac, clkfb_div_check, clkfb_div_check_diff, clk0_div_check, clk0_div_check_diff;
reg clk0_frac_out, clkfbm1_frac_out;
reg clk0_nf_out, clkfbm1_nf_out;
integer clk0_frac_en;
integer clkfb_frac_en;
integer clkfb_div_check_int, clk0_div_check_int, clkfb_div_adj, clk0_div_adj;
integer clkvco_frac_en;
integer ps_in_init;
reg psdone_out, psdone_out1;
integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en;
integer clk5_fps_en, clk6_fps_en, clkfb_fps_en, fps_en;
reg clkinstopped_out;
reg clkin_hold_f = 0;
reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0;
integer period_avg_stpi = 0, period_avg_stp = 0;
real tmp_stp1, tmp_stp2;
reg pd_stp_p = 0;
reg vco_stp_f = 0;
reg psen_w = 0;
reg clkinstopped_out_dly = 0;
reg clkinstopped_out1 = 0;
reg clkfbstopped_out1 = 0;
reg clkfb_stop_tmp, clkfbstopped_out, clkin_stop_tmp;
reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0;
reg rst_clkinstopped_rc = 0;
reg rst_clkinstopped_lk, rst_clkfbstopped_lk;
integer clkin_lost_cnt, clkfb_lost_cnt;
reg clkinstopped_hold = 0;
integer ps_in_ps, ps_cnt;
integer ps_in_ps_neg, ps_cnt_neg;
reg clkout_ps, clkout_ps_tmp1, clkout_ps_tmp2;
time clkout_ps_eg = 0;
time clkout_ps_peg = 0;
time clkout_ps_w = 0;
reg clkvco_ps_tmp1, clkvco_ps_tmp2;
reg clkvco_ps_tmp2_en;
integer clkout4_cascade_int;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drdy_out, drdy_out1;
reg drp_lock;
integer drp_lock_lat = 4;
integer drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [160:0] tmp_string;
reg rst_int;
reg pwron_int;
wire orig_rst_in,rst_in_o;
wire locked_out;
reg locked_out1;
reg locked_out_tmp;
wire clk0_out, clkfbm1_out;
reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out;
reg clkfb_out;
reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1;
integer clkout_en_val, clkout_en_t;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
reg clkvco_lk_osc, clkvco, clkvco_lk_tmp, clkvco_lk_tmp_en;
reg clkvco_ps_tmp2_pg;
reg clkvco_lk_dly_tmp;
reg clkvco_lk_en;
reg clkvco_lk;
reg fbclk_tmp;
reg clk_osc, clkin_p, clkfb_p;
reg clkinstopped_vco_f;
time rst_edge, rst_ht;
reg fb_delay_found, fb_delay_found_tmp;
reg clkfb_tst;
real fb_delay_max;
time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay, fbm1_comp_delay_tmp;
time dly_tmp1, tmp_ps_val2;
integer dly_tmp_int, tmp_ps_val1;
time clkin_edge, delay_edge;
real period_clkin, clkin_period_tmp;
integer clkin_period_tmp_t;
integer clkin_period [4:0];
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
real period_vco_rl;
integer period_vco_half_rm1, period_vco_half_rm2;
real cmpvco = 0.0;
real clkvco_pdrm;
integer period_vco_mf;
integer period_vco_tmp;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco_max, period_vco_min;
integer period_vco1, period_vco2, period_vco3, period_vco4;
integer period_vco5, period_vco6, period_vco7;
integer period_vco_target, period_vco_target_half;
integer period_fb, period_avg;
integer clk0_frac_lt, clk0_frac_ht;
integer clkfb_frac_lt, clkfb_frac_ht;
integer period_ps, period_ps_old;
reg ps_lock, ps_lock_dly;
real clkvco_freq_init_chk, clkfbm1pm_rl;
real clkpfd_freq_init_chk;
real tmp_real;
integer ik0, ik1, ik2, ik3, ik4, ib, i, j;
integer md_product, m_product, m_product2, clkin_stop_max, clkfb_stop_max;
integer mf_product, clk0f_product;
integer clkin_lost_val, clkfb_lost_val, clkin_lost_val_lk;
time pll_locked_delay, clkin_dly_t, clkfb_dly_t;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2;
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock;
integer clkin_jit, REF_CLK_JITTER_MAX_tmp;
wire init_trig, clkpll_r, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clk6in;
reg clkpll_tmp1, clkpll;
wire clkfbm1in, clkfbm1ps_en;
reg chk_ok;
wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en;
reg [7:0] clkout_mux, clkout_ps_mux;
wire [7:0] clk0_sel_mux, clkfb_sel_mux;
reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel;
reg [2:0] clk0pmf_sel, clk0pmr_sel, clkfbm1pmf_sel, clkfbm1pmr_sel;
reg clkfbout_frac_wf_r, clk0_frac_wf_r, clk0_frac_wf_f, clkfbout_frac_wf_f;
reg clkfbin_edge, clkfbin_nocnt;
reg [2:0] clkfb_frac, clk0_frac;
reg clk0_cddcen, clk1_cddcen, clk2_cddcen, clk3_cddcen, clk4_cddcen, clk5_cddcen, clk6_cddcen;
integer clkfbm1_odd_frac, clk0_odd_frac;
real tmp_fbp;
real tmp_f0p;
integer tmp_fbo, tmp_fbq;
integer tmp_f0o, tmp_f0q;
real clk0_f_div;
reg [5:0] clkfbin_ht, clkfbin_lt;
reg [2:0] clk5fpm_sel, clk6fpm_sel;
wire [2:0] clk0pm_sel1, clk5pm_sel1, clk6pm_sel1, clkfbm1pm_sel1;
reg [2:0] clk6pm_sel, clkfbm1pm_sel;
reg [2:0] clkfbm1r_sel, clk0pm_fsel, clk0pm_rsel, clkfbm1f_sel;
integer clk0pm_sel_int, clkfbm1pm_sel_int;
reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge, clk6_edge;
reg clkfbm1_edge, clkfbm2_edge, clkind_edge;
reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt;
reg clk6_nocnt, clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt;
reg clkfbtmp_nocnti;
reg clkind_edgei, clkind_nocnti;
reg [5:0] clkfbm1_fht, clkfbm1_flt;
reg [5:0] clk0_fht, clk0_flt;
reg [5:0] clk0_dly_cnt, clkout0_dly;
reg [5:0] clk1_dly_cnt, clkout1_dly;
reg [5:0] clk2_dly_cnt, clkout2_dly;
reg [5:0] clk3_dly_cnt, clkout3_dly;
reg [5:0] clk4_dly_cnt, clkout4_dly;
reg [5:0] clk5_dly_cnt, clkout5_dly;
reg [5:0] clk6_dly_cnt, clkout6_dly;
reg [6:0] clk0_ht, clk0_lt;
reg [6:0] clk1_ht, clk1_lt;
reg [6:0] clk2_ht, clk2_lt;
reg [6:0] clk3_ht, clk3_lt;
reg [6:0] clk4_ht, clk4_lt;
reg [6:0] clk5_ht, clk5_lt;
reg [6:0] clk6_ht, clk6_lt;
reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly;
reg [6:0] clkfbm1_ht, clkfbm1_lt;
reg [6:0] clkfbm2_ht, clkfbm2_lt;
reg [7:0] clkind_ht, clkind_lt;
reg [7:0] clkind_hti, clkind_lti;
reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1;
reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1;
reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1;
reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1;
reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1;
reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1;
reg [7:0] clk6_ht1, clk6_cnt, clk6_div, clk6_div1;
reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1;
real clkfbm1_f_div, clkfbm1_div_t;
integer clkfbm1_div_t_int;
reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti;
reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1;
reg [7:0] clkind_div, clkind_divi, clkind_div1, clkind_cnt, clkind_ht1;
reg clkind_out, clkind_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
wire clkinsel_tmp;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
reg init_chk;
reg rst_clkinsel_flag = 0;
reg clkout0_out, clkout1_out, clkout2_out, clkout3_out, clkout4_out;
reg clkout5_out, clkout6_out;
reg clkfbm2_out, clkfbm2_out_tmp, clk6_out;
wire [15:0] do_out;
reg [15:0] do_out1;
wire pwrdwn_in1;
reg pwrdwn_in1_h = 0;
reg rst_input_r_h = 0;
reg pchk_clr = 0;
reg psincdec_chg = 0;
reg psincdec_chg_tmp = 0;
wire rst_input;
reg startup_wait_sig;
real clkfb_sdivide;
integer clkfb_sdivide_int, clkfb_sevent_part_high;
integer clkfb_sevent_part_low, clkfb_sodd, clkfb_sodd_and_frac;
integer clkfb_slt, clkfb_sht, clkfb_sfrac_2;
reg [2:0] clkfbpmf_sel, clkfbpmr_sel;
real clkfb_sa, clkfb_sb, clkfb_sphase;
integer clkfb_sdt_tmp;
integer clkfb_sdt, clkfb_pm_rise_overwriting, clkfb_pm_fall_overwriting;
integer clkfb_pm_fall_overwriting_2nd, clkfb_pm_rise_overwriting_2nd;
real clk0_sdivide;
integer clk0_sdivide_int, clk0_sevent_part_high;
integer clk0_sevent_part_low, clk0_sodd, clk0_sodd_and_frac;
integer clk0_slt, clk0_sht, clk0_sfrac_2;
reg clk0out_frac_wf_r, clk0out_frac_wf_f;
real clk0_sa, clk0_sb, clk0_sphase;
integer clk0_sdt_tmp, clk0_sdt, clk0_pm_rise_overwriting, clk0_pm_fall_overwriting;
integer clk0_pm_fall_overwriting_2nd, clk0_pm_rise_overwriting_2nd;
reg vcoflag = 0;
reg cddcdone_out;
assign CLKINSTOPPED = clkinstopped_out1;
assign CLKFBSTOPPED = clkfbstopped_out1;
assign IS_CLKFBIN_INVERTED_BIN = IS_CLKFBIN_INVERTED_REG;
assign IS_CLKIN1_INVERTED_BIN = IS_CLKIN1_INVERTED_REG;
assign IS_CLKIN2_INVERTED_BIN = IS_CLKIN2_INVERTED_REG;
assign IS_CLKINSEL_INVERTED_BIN = IS_CLKINSEL_INVERTED_REG;
assign IS_PSEN_INVERTED_BIN = IS_PSEN_INVERTED_REG;
assign IS_PSINCDEC_INVERTED_BIN = IS_PSINCDEC_INVERTED_REG;
assign IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign LOCKED = locked_out1;
assign DRDY = drdy_out1;
assign DO = do_out1;
assign PSDONE = psdone_out1;
assign CDDCDONE = cddcdone_out;
always @(locked_out_tmp)
locked_out1 = locked_out_tmp;
always @(drdy_out)
drdy_out1 = drdy_out;
always @(do_out)
do_out1 = do_out;
always @(psdone_out)
psdone_out1 = psdone_out;
initial begin
#1;
trig_attr = ~trig_attr;
trig_attr_chk = 1'b1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the %s, the simulator resolution must be set to 1ps or smaller.", MODULE_NAME);
$finish;
end
end
always @(trig_attr) begin
#1;
case (STARTUP_WAIT_REG)
"FALSE" : startup_wait_sig = 0;
"TRUE" : startup_wait_sig = 1;
default : begin
$display("Attribute Syntax Error : The Attribute STARTUP_WAIT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, STARTUP_WAIT_REG);
attr_err = 1'b1;
end
endcase
case (BANDWIDTH_REG)
"OPTIMIZED" : ;
"HIGH" : ;
"LOW" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BANDWIDTH on %s instance %m is set to %s. Legal values for this attribute are OPTIMIZED, HIGH, or LOW.", MODULE_NAME, BANDWIDTH_REG);
attr_err = 1'b1;
end
endcase
case (CLKFBOUT_USE_FINE_PS_REG)
"FALSE" : clkfb_fps_en = 0;
"TRUE" : clkfb_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT0_USE_FINE_PS_REG)
"FALSE" : clk0_fps_en = 0;
"TRUE" : clk0_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT1_USE_FINE_PS_REG)
"FALSE" : clk1_fps_en = 0;
"TRUE" : clk1_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT2_USE_FINE_PS_REG)
"FALSE" : clk2_fps_en = 0;
"TRUE" : clk2_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT3_USE_FINE_PS_REG)
"FALSE" : clk3_fps_en = 0;
"TRUE" : clk3_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT4_USE_FINE_PS_REG)
"FALSE" : clk4_fps_en = 0;
"TRUE" : clk4_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT5_USE_FINE_PS_REG)
"FALSE" : clk5_fps_en = 0;
"TRUE" : clk5_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT6_USE_FINE_PS_REG)
"FALSE" : clk6_fps_en = 0;
"TRUE" : clk6_fps_en = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG);
attr_err = 1'b1;
end
endcase
case (CLKOUT4_CASCADE_REG)
"FALSE" : clkout4_cascade_int = 0;
"TRUE" : clkout4_cascade_int = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_CASCADE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKOUT4_CASCADE_REG);
attr_err = 1'b1;
end
endcase
case (COMPENSATION_REG)
"AUTO" : ;
"ZHOLD" : ;
"BUF_IN" : ;
"EXTERNAL" : ;
"INTERNAL" : ;
default : begin
$display("Attribute Syntax Error : The Attribute COMPENSATION on %s instance %m is set to %s. Legal values for this attribute are AUTO, ZHOLD, BUF_IN, EXTERNAL, or INTERNAL.", MODULE_NAME, COMPENSATION_REG);
attr_err = 1'b1;
end
endcase
if (attr_err == 1'b1) $finish;
clkfbm1_f_div = CLKFBOUT_MULT_F_REG;
clkfb_div_fint = $rtoi(CLKFBOUT_MULT_F_REG);
clkfb_div_frac = CLKFBOUT_MULT_F_REG - clkfb_div_fint;
clkfb_div_check = clkfb_div_frac/ 0.125;
clkfb_div_check_int = clkfb_div_frac/ 0.125;
clkfb_div_check_diff = clkfb_div_check - clkfb_div_check_int;
if (clkfb_div_frac > 0.000)
clkfb_frac_en = 1;
else
clkfb_frac_en = 0;
if (clkfb_frac_en == 1 && clkfb_div_check_diff == 0.000)
clkfb_div_adj = 0;
else
clkfb_div_adj = 1;
if (clkfb_frac_en)
clkfbm1_div_t = clkfbm1_f_div;
else
clkfbm1_div_t = clkfbm1_div;
clkfb_div_frac_int = $rtoi(clkfb_div_frac * 8);
clkfb_div_fint_tmp1 = clkfb_div_fint / 2;
clkfb_div_fint_odd = clkfb_div_fint - clkfb_div_fint_tmp1 -clkfb_div_fint_tmp1;
clkfb_sdivide = CLKFBOUT_MULT_F_REG;
clkfb_sdivide_int = clkfb_div_fint;
clkfb_frac = clkfb_div_frac_int;
clkfb_sevent_part_high = clkfb_div_fint_tmp1;
clkfb_sevent_part_low = clkfb_sevent_part_high;
clkfb_sodd = clkfb_div_fint_odd;
clkfb_sodd_and_frac = 8 * clkfb_sodd + clkfb_frac;
if (clkfb_sodd_and_frac > 9)
clkfbm1_lt = clkfb_sevent_part_high;
else
clkfbm1_lt = clkfb_sevent_part_high - 1;
if (clkfb_sodd_and_frac > 8)
clkfbm1_ht = clkfb_sevent_part_low;
else
clkfbm1_ht = clkfb_sevent_part_low - 1;
clkfb_sfrac_2 = clkfb_div_frac_int / 2;
clkfbpmf_sel = 4 * clkfb_sodd + clkfb_sfrac_2;
clkfbpmr_sel = 3'b0;
if (CLKFBOUT_MULT_F_REG == 2.125)
clkfbout_frac_wf_f = 1;
else begin
if (clkfb_sodd_and_frac >= 2 && clkfb_sodd_and_frac <= 9)
clkfbout_frac_wf_f = 1;
else
clkfbout_frac_wf_f = 0;
end
if (clkfb_sodd_and_frac >= 1 && clkfb_sodd_and_frac <= 8)
clkfbout_frac_wf_r = 1;
else
clkfbout_frac_wf_r = 0;
if (CLKFBOUT_PHASE_REG < 0.000)
clkfb_sphase = CLKFBOUT_PHASE_REG + 360;
else
clkfb_sphase = CLKFBOUT_PHASE_REG;
clkfb_sdt = $rtoi(CLKFBOUT_PHASE_REG * clkfb_sdivide / 360.0);
clkfb_sa = CLKFBOUT_PHASE_REG * clkfb_sdivide / 360.0 - clkfb_sdt;
clkfb_sb = clkfb_sa;
clkfb_pm_rise_overwriting = $rtoi(clkfb_sb / 0.125);
if (clkfb_pm_rise_overwriting > 7)
clkfb_pm_rise_overwriting_2nd = clkfb_pm_rise_overwriting - 8;
else
clkfb_pm_rise_overwriting_2nd = clkfb_pm_rise_overwriting;
clkfb_pm_fall_overwriting = clkfbpmf_sel + clkfb_pm_rise_overwriting_2nd;
if (clkfb_pm_fall_overwriting > 7)
clkfb_pm_fall_overwriting_2nd = clkfb_pm_fall_overwriting - 8;
else
clkfb_pm_fall_overwriting_2nd = clkfb_pm_fall_overwriting;
clkfb_sdt_tmp = clkfb_sdt;
if (clkfb_pm_rise_overwriting > 7)
clkfb_sdt = clkfb_sdt_tmp + 1;
// mf_product = clkfb_div_fint * 8 + clkfb_div_frac_int;
clk0_div_fint = $rtoi(CLKOUT0_DIVIDE_F_REG);
clk0_div_frac = CLKOUT0_DIVIDE_F_REG - clk0_div_fint;
if (clk0_div_frac > 0.000 && clk0_div_fint >= 2)
clk0_frac_en = 1;
else
clk0_frac_en = 0;
clk0_div_check = clk0_div_frac/ 0.125;
clk0_div_check_int = clk0_div_frac/ 0.125;
clk0_div_check_diff = clk0_div_check - clk0_div_check_int;
if (clk0_frac_en == 1 && clk0_div_check_diff == 0.000)
clk0_div_adj = 0;
else
clk0_div_adj = 1;
clk0_div_frac_int = $rtoi(clk0_div_frac * 8);
clk0_div_fint_tmp1 = clk0_div_fint / 2;
clk0_div_fint_odd = clk0_div_fint - clk0_div_fint_tmp1 -clk0_div_fint_tmp1;
clk0_sdivide = CLKOUT0_DIVIDE_F_REG;
clk0_sdivide_int = clk0_div_fint;
clk0_frac = clk0_div_frac_int;
clk0_sevent_part_high = clk0_div_fint_tmp1;
clk0_sevent_part_low = clk0_sevent_part_high;
clk0_sodd = clk0_div_fint_odd;
clk0_sodd_and_frac = 8 * clk0_sodd + clk0_frac;
if (clk0_sodd_and_frac > 9)
clk0_lt = clk0_sevent_part_high;
else
clk0_lt = clk0_sevent_part_high - 1;
if (clk0_sodd_and_frac > 8)
clk0_ht = clk0_sevent_part_low;
else
clk0_ht = clk0_sevent_part_low - 1;
clk0_sfrac_2 = clk0_div_frac_int / 2;
clk0pmf_sel = 4 * clk0_sodd + clk0_sfrac_2;
clk0pmr_sel = 3'b0;
if (CLKOUT0_DIVIDE_F_REG == 2.125)
clk0_frac_wf_f = 1;
else begin
if (clk0_sodd_and_frac >= 2 && clk0_sodd_and_frac <= 9)
clk0_frac_wf_f = 1;
else
clk0_frac_wf_f = 0;
end
if (clk0_sodd_and_frac >= 1 && clk0_sodd_and_frac <= 8)
clk0_frac_wf_r = 1;
else
clk0_frac_wf_r = 0;
if (CLKOUT0_PHASE_REG < 0.000)
clk0_sphase = CLKOUT0_PHASE_REG + 360;
else
clk0_sphase = CLKOUT0_PHASE_REG;
clk0_sdt = $rtoi(CLKOUT0_PHASE_REG * clk0_sdivide / 360.0);
clk0_sa = CLKOUT0_PHASE_REG * clk0_sdivide / 360.0 - clk0_sdt;
clk0_sb = clk0_sa;
clk0_pm_rise_overwriting = $rtoi(clk0_sb / 0.125);
if (clk0_pm_rise_overwriting > 7)
clk0_pm_rise_overwriting_2nd = clk0_pm_rise_overwriting - 8;
else
clk0_pm_rise_overwriting_2nd = clk0_pm_rise_overwriting;
clk0_pm_fall_overwriting = clk0pmf_sel + clk0_pm_rise_overwriting_2nd;
if (clk0_pm_fall_overwriting > 7)
clk0_pm_fall_overwriting_2nd = clk0_pm_fall_overwriting - 8;
else
clk0_pm_fall_overwriting_2nd = clk0_pm_fall_overwriting;
clk0_sdt_tmp = clk0_sdt;
if (clk0_pm_rise_overwriting > 7)
clk0_sdt = clk0_sdt_tmp + 1;
ps_in_init = 0;
ps_in_ps = ps_in_init;
ps_cnt = 0;
fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en
|| clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfb_fps_en;
tmp_string = "CLKOUT0_DIVIDE_F";
chk_ok = para_real_range_chk(CLKOUT0_DIVIDE_F_REG, tmp_string, 1.000, 128.000);
if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000)
$display("Attribute Syntax Error : The Attribute CLKOUT0_DIVIDE_F on %s instance %m is set to %f. Values in range of greater than 1 and less than 2 are not allowed.", MODULE_NAME, CLKOUT0_DIVIDE_F_REG);
tmp_string = "CLKOUT0_PHASE";
chk_ok = para_real_range_chk(CLKOUT0_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT0_DUTY_CYCLE";
if (clk0_frac_en == 0)
chk_ok = para_real_range_chk(CLKOUT0_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
else
if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_DUTY_CYCLE on %s instance %m is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part.", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
$finish;
end
tmp_string = "CLKOUT1_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT1_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT1_PHASE";
chk_ok = para_real_range_chk(CLKOUT1_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT1_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT2_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT2_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT2_PHASE";
chk_ok = para_real_range_chk(CLKOUT2_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT2_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT3_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT3_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT3_PHASE";
chk_ok = para_real_range_chk(CLKOUT3_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT3_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT4_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT4_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT4_PHASE";
chk_ok = para_real_range_chk(CLKOUT4_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT5_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT5_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT5_PHASE";
chk_ok = para_real_range_chk(CLKOUT5_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT6_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT6_DIVIDE_REG, tmp_string, 1, 128);
tmp_string = "CLKOUT6_PHASE";
chk_ok = para_real_range_chk(CLKOUT6_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT6_DUTY_CYCLE_REG, tmp_string, 0.001, 0.999);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk(CLKFBOUT_MULT_F_REG, tmp_string, 2.000, 64.000);
tmp_string = "CLKFBOUT_PHASE";
chk_ok = para_real_range_chk(CLKFBOUT_PHASE_REG, tmp_string, -360.0, 360.0);
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, 1, D_MAX);
tmp_string = "REF_JITTER1";
chk_ok = para_real_range_chk (REF_JITTER1_REG, tmp_string, 0.000, 0.999);
tmp_string = "REF_JITTER2";
chk_ok = para_real_range_chk (REF_JITTER2_REG, tmp_string, 0.000, 0.999);
pll_lfhf = 2'b00;
if (BANDWIDTH_REG === "HIGH")
case (clkfb_div_fint)
2 : begin pll_cp = 32'd4 ; pll_res = 32'd15 ; end
3 : begin pll_cp = 32'd5 ; pll_res = 32'd11 ; end
4 : begin pll_cp = 32'd7 ; pll_res = 32'd7 ; end
5 : begin pll_cp = 32'd13 ; pll_res = 32'd7 ; end
6 : begin pll_cp = 32'd14 ; pll_res = 32'd11 ; end
7 : begin pll_cp = 32'd14 ; pll_res = 32'd13 ; end
8 : begin pll_cp = 32'd15 ; pll_res = 32'd3 ; end
9 : begin pll_cp = 32'd14 ; pll_res = 32'd5 ; end
10 : begin pll_cp = 32'd15 ; pll_res = 32'd5 ; end
11 : begin pll_cp = 32'd15 ; pll_res = 32'd9 ; end
12 : begin pll_cp = 32'd13 ; pll_res = 32'd1 ; end
13 : begin pll_cp = 32'd14 ; pll_res = 32'd1 ; end
14 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
15 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
16 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
17 : begin pll_cp = 32'd14 ; pll_res = 32'd6 ; end
18 : begin pll_cp = 32'd15 ; pll_res = 32'd6 ; end
19 : begin pll_cp = 32'd14 ; pll_res = 32'd10 ; end
20 : begin pll_cp = 32'd14 ; pll_res = 32'd10 ; end
21 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
22 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
23 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
24 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
25 : begin pll_cp = 32'd7 ; pll_res = 32'd2 ; end
26 : begin pll_cp = 32'd7 ; pll_res = 32'd2 ; end
27 : begin pll_cp = 32'd14 ; pll_res = 32'd10; end
28 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
29 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
30 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
31 : begin pll_cp = 32'd4 ; pll_res = 32'd4 ; end
32 : begin pll_cp = 32'd13 ; pll_res = 32'd6 ; end
33 : begin pll_cp = 32'd13 ; pll_res = 32'd6 ; end
34 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
35 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
36 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
37 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
38 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
39 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
40 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
41 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
42 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
43 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
44 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
45 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
46 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
47 : begin pll_cp = 32'd7 ; pll_res = 32'd1 ; end
48 : begin pll_cp = 32'd7 ; pll_res = 32'd1 ; end
49 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
50 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
51 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
52 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
53 : begin pll_cp = 32'd6 ; pll_res = 32'd1 ; end
54 : begin pll_cp = 32'd6 ; pll_res = 32'd1 ; end
55 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
56 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
57 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
58 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
59 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
60 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
61 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
62 : begin pll_cp = 32'd4 ; pll_res = 32'd10 ; end
63 : begin pll_cp = 32'd3 ; pll_res = 32'd12 ; end
64 : begin pll_cp = 32'd3 ; pll_res = 32'd12 ; end
endcase
else if (BANDWIDTH_REG === "LOW")
case (clkfb_div_fint)
2 : begin pll_cp = 32'd2 ; pll_res = 32'd15 ; end
3 : begin pll_cp = 32'd2 ; pll_res = 32'd15 ; end
4 : begin pll_cp = 32'd2 ; pll_res = 32'd15 ; end
5 : begin pll_cp = 32'd2 ; pll_res = 32'd7 ; end
6 : begin pll_cp = 32'd2 ; pll_res = 32'd11 ; end
7 : begin pll_cp = 32'd2 ; pll_res = 32'd13 ; end
8 : begin pll_cp = 32'd2 ; pll_res = 32'd3 ; end
9 : begin pll_cp = 32'd2 ; pll_res = 32'd5 ; end
10 : begin pll_cp = 32'd2 ; pll_res = 32'd5 ; end
11 : begin pll_cp = 32'd2 ; pll_res = 32'd9 ; end
12 : begin pll_cp = 32'd2 ; pll_res = 32'd14 ; end
13 : begin pll_cp = 32'd2 ; pll_res = 32'd14 ; end
14 : begin pll_cp = 32'd2 ; pll_res = 32'd14 ; end
15 : begin pll_cp = 32'd2 ; pll_res = 32'd14 ; end
16 : begin pll_cp = 32'd2 ; pll_res = 32'd1 ; end
17 : begin pll_cp = 32'd2 ; pll_res = 32'd1 ; end
18 : begin pll_cp = 32'd2 ; pll_res = 32'd1 ; end
19 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
20 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
21 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
22 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
23 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
24 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
25 : begin pll_cp = 32'd2 ; pll_res = 32'd6 ; end
26 : begin pll_cp = 32'd2 ; pll_res = 32'd10 ; end
27 : begin pll_cp = 32'd2 ; pll_res = 32'd10 ; end
28 : begin pll_cp = 32'd2 ; pll_res = 32'd10 ; end
29 : begin pll_cp = 32'd2 ; pll_res = 32'd10 ; end
30 : begin pll_cp = 32'd2 ; pll_res = 32'd10 ; end
31 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
32 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
33 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
34 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
35 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
36 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
37 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
38 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
39 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
40 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
41 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
42 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
43 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
44 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
45 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
46 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
47 : begin pll_cp = 32'd2 ; pll_res = 32'd12 ; end
48 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
49 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
50 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
51 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
52 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
53 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
54 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
55 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
56 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
57 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
58 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
59 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
60 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
61 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
62 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
63 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
64 : begin pll_cp = 32'd2 ; pll_res = 32'd2 ; end
endcase
else if (BANDWIDTH_REG === "OPTIMIZED")
case (clkfb_div_fint)
2 : begin pll_cp = 32'd4 ; pll_res = 32'd15 ; end
3 : begin pll_cp = 32'd5 ; pll_res = 32'd11 ; end
4 : begin pll_cp = 32'd7 ; pll_res = 32'd7 ; end
5 : begin pll_cp = 32'd13 ; pll_res = 32'd7 ; end
6 : begin pll_cp = 32'd14 ; pll_res = 32'd11 ; end
7 : begin pll_cp = 32'd14 ; pll_res = 32'd13 ; end
8 : begin pll_cp = 32'd15 ; pll_res = 32'd3 ; end
9 : begin pll_cp = 32'd14 ; pll_res = 32'd5 ; end
10 : begin pll_cp = 32'd15 ; pll_res = 32'd5 ; end
11 : begin pll_cp = 32'd15 ; pll_res = 32'd9 ; end
12 : begin pll_cp = 32'd13 ; pll_res = 32'd1 ; end
13 : begin pll_cp = 32'd14 ; pll_res = 32'd1 ; end
14 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
15 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
16 : begin pll_cp = 32'd15 ; pll_res = 32'd1 ; end
17 : begin pll_cp = 32'd14 ; pll_res = 32'd6 ; end
18 : begin pll_cp = 32'd15 ; pll_res = 32'd6 ; end
19 : begin pll_cp = 32'd14 ; pll_res = 32'd10 ; end
20 : begin pll_cp = 32'd14 ; pll_res = 32'd10 ; end
21 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
22 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
23 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
24 : begin pll_cp = 32'd15 ; pll_res = 32'd10 ; end
25 : begin pll_cp = 32'd7 ; pll_res = 32'd2 ; end
26 : begin pll_cp = 32'd7 ; pll_res = 32'd2 ; end
27 : begin pll_cp = 32'd14 ; pll_res = 32'd10 ; end
28 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
29 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
30 : begin pll_cp = 32'd6 ; pll_res = 32'd2 ; end
31 : begin pll_cp = 32'd4 ; pll_res = 32'd4 ; end
32 : begin pll_cp = 32'd13 ; pll_res = 32'd6 ; end
33 : begin pll_cp = 32'd13 ; pll_res = 32'd6 ; end
34 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
35 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
36 : begin pll_cp = 32'd5 ; pll_res = 32'd2 ; end
37 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
38 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
39 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
40 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
41 : begin pll_cp = 32'd3 ; pll_res = 32'd4 ; end
42 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
43 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
44 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
45 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
46 : begin pll_cp = 32'd2 ; pll_res = 32'd8 ; end
47 : begin pll_cp = 32'd7 ; pll_res = 32'd1 ; end
48 : begin pll_cp = 32'd7 ; pll_res = 32'd1 ; end
49 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
50 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
51 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
52 : begin pll_cp = 32'd4 ; pll_res = 32'd12 ; end
53 : begin pll_cp = 32'd6 ; pll_res = 32'd1 ; end
54 : begin pll_cp = 32'd6 ; pll_res = 32'd1 ; end
55 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
56 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
57 : begin pll_cp = 32'd5 ; pll_res = 32'd6 ; end
58 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
59 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
60 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
61 : begin pll_cp = 32'd2 ; pll_res = 32'd4 ; end
62 : begin pll_cp = 32'd4 ; pll_res = 32'd10 ; end
63 : begin pll_cp = 32'd3 ; pll_res = 32'd12 ; end
64 : begin pll_cp = 32'd3 ; pll_res = 32'd12 ; end
endcase
case (clkfb_div_fint)
1 : begin drp_lock_ref_dly = 32'd6;
drp_lock_fb_dly = 32'd6;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
2 : begin drp_lock_ref_dly = 32'd6;
drp_lock_fb_dly = 32'd6;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
3 : begin drp_lock_ref_dly = 32'd8;
drp_lock_fb_dly = 32'd8;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
4 : begin drp_lock_ref_dly = 32'd11;
drp_lock_fb_dly = 32'd11;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
5 : begin drp_lock_ref_dly = 32'd14;
drp_lock_fb_dly = 32'd14;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
6 : begin drp_lock_ref_dly = 32'd17;
drp_lock_fb_dly = 32'd17;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
7 : begin drp_lock_ref_dly = 32'd19;
drp_lock_fb_dly = 32'd19;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
8 : begin drp_lock_ref_dly = 32'd22;
drp_lock_fb_dly = 32'd22;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
9 : begin drp_lock_ref_dly = 32'd25;
drp_lock_fb_dly = 32'd25;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
10 : begin drp_lock_ref_dly = 32'd28;
drp_lock_fb_dly = 32'd28;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
11 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd900;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
12 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd825;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
13 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd750;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
14 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd700;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
15 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd650;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
16 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd625;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
17 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd575;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
18 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd550;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
19 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd525;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
20 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd500;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
21 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd475;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
22 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd450;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
23 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd425;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
24 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd400;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
25 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd400;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
26 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd375;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
27 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd350;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
28 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd350;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
29 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd325;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
30 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd325;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
31 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
32 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
33 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
34 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
35 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
36 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
37 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
38 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
39 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
40 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
41 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
42 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
43 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
44 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
45 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
46 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
47 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
48 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
49 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
50 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
51 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
52 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
53 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
54 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
55 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
56 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
57 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
58 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
59 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
60 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
61 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
62 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
63 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
64 : begin drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1; end
endcase
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_REG, tmp_string, M_MIN, M_MAX);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string);
if(clk0_frac_en == 0) begin
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_REG, CLKOUT0_DUTY_CYCLE_REG, tmp_string);
end
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string);
period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clk0f_product = CLKOUT0_DIVIDE_F_REG * 8;
pll_lock_time = 12;
lock_period_time = 10;
if (clkfb_frac_en == 1) begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE_REG;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT_F_REG * 8;
clkout_en_val = mf_product - 2;
m_product2 = clkfb_div_fint / 2;
clkout_en_time = mf_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time;
lock_cnt_max = locked_en_time + 16;
end
else begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE_REG;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT_F_REG * 8;
m_product2 = clkfb_div_fint / 2;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time;
lock_cnt_max = locked_en_time + 16;
end
clkfb_stop_max = 3;
clkin_stop_max = DIVCLK_DIVIDE_REG + 1;
REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG);
clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG);
clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG);
clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG);
clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG);
clk_out_para_cal (clk6_ht, clk6_lt, clk6_nocnt, clk6_edge, CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG);
clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE_REG, 0.50);
tmp_string = "CLKOUT1_PHASE";
clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, tmp_string);
tmp_string = "CLKOUT2_PHASE";
clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, tmp_string);
tmp_string = "CLKOUT3_PHASE";
clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, tmp_string);
tmp_string = "CLKOUT4_PHASE";
clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, tmp_string);
tmp_string = "CLKOUT5_PHASE";
clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, tmp_string);
tmp_string = "CLKOUT6_PHASE";
clkout_dly_cal (clkout6_dly, clk6pm_sel, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, tmp_string);
if (clkfb_frac_en == 1) begin
clkfbm1_fht = clkfb_div_fint /2;
clkfbm1_flt = clkfb_div_fint /2;
if (clkfb_div_fint_odd > 0) begin
clkfbm1r_sel = (8 + clkfb_div_frac_int) / 2;
clkfbm1f_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
end
else begin
clkfbm1f_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1r_sel = clkfb_div_frac_int / 2;
end
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_real_cal (clkfbm1_dly, clkfbm1pm_sel, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, tmp_string);
end
else begin
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_real_cal (clkfbm1_dly, clkfbm1pm_sel, clkfb_div_fint, CLKFBOUT_PHASE_REG, tmp_string);
end
if (clk0_frac_en == 1) begin
clk0_fht = clk0_div_fint /2;
clk0_flt = clk0_div_fint /2;
if (clk0_div_fint_odd > 0) begin
clk0pm_rsel = (8 + clk0_div_frac_int) / 2;
clk0pm_fsel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
end
else begin
clk0pm_fsel = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_rsel = clk0_div_frac_int / 2;
end
tmp_string = "CLKOUT0_PHASE";
clkout_dly_real_cal (clkout0_dly, clk0pm_sel, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, tmp_string);
end
else begin
tmp_string = "CLKOUT0_PHASE";
clkout_dly_real_cal (clkout0_dly, clk0pm_sel, clk0_div_fint, CLKOUT0_PHASE_REG, tmp_string);
end
if (clk0_frac_en == 0) begin
clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, clk0_div_fint, CLKOUT0_DUTY_CYCLE_REG);
end
if (clkfb_frac_en == 0) begin
clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50);
end
clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, 1, 0.50);
clkind_div = DIVCLK_DIVIDE_REG;
dr_sram[6] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]};
dr_sram[7] = {clk0pmf_sel[2:0], clk0_frac_wf_f, 1'bx, clk5_cddcen, 2'b0, clk5_edge,
clk5_nocnt, clkout5_dly[5:0]};
dr_sram[8] = {clk0pmr_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {clk0_cddcen, clk0_frac[2:0], clk0_frac_en, clk0_frac_wf_r, 2'b0,
clk0_edge, clk0_nocnt, clkout0_dly[5:0]};
dr_sram[10] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {5'bx, clk1_cddcen, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]};
dr_sram[12] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]};
dr_sram[13] = {5'bx, clk2_cddcen, 2'b0, clk2_edge, clk2_nocnt, clkout2_dly[5:0]};
dr_sram[14] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]};
dr_sram[15] = {5'bx, clk3_cddcen, 2'b0, clk3_edge, clk3_nocnt, clkout3_dly[5:0]};
dr_sram[16] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]};
dr_sram[17] = {5'bx, clk4_cddcen, 2'b0, clk4_edge, clk4_nocnt, clkout4_dly[5:0]};
dr_sram[18] = {clk6pm_sel[2:0], 1'b1, clk6_ht[5:0], clk6_lt[5:0]};
dr_sram[19] = {clkfbpmf_sel[2:0], clkfbout_frac_wf_f, 1'bx,clk6_cddcen,
2'b00, clk6_edge, clk6_nocnt, clkout6_dly[5:0]};
dr_sram[20] = {clkfbpmr_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]};
dr_sram[21] = {1'bx, clkfb_frac[2:0], clkfb_frac_en,
clkfbout_frac_wf_r, 2'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]};
dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]};
dr_sram[23] = {2'bx, clkfbin_edge, clkfbin_nocnt, clkfbin_ht[5:0], clkfbin_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
end
initial begin
clkpll_jitter_unlock = 0;
clkinstopped_vco_f = 0;
rst_clkfbstopped = 0;
rst_clkinstopped = 0;
rst_clkfbstopped_lk = 0;
rst_clkinstopped_lk = 0;
clkfb_stop_tmp = 0;
clkin_stop_tmp = 0;
clkout_ps = 0;
clkout_ps_tmp1 = 0;
clkout_ps_tmp2 = 0;
clkvco_ps_tmp1 = 0;
clkvco_ps_tmp2 = 0;
clkvco_ps_tmp2_en = 0;
clkvco_lk_osc = 0;
clkvco_lk_en = 0;
clkvco_lk_tmp = 0;
clkvco_lk_dly_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
clkind_edgei = 0;
clkind_nocnti = 0;
clkind_hti = 0;
clkind_lti = 0;
clkind_divi = 1;
ps_lock = 0;
ps_lock_dly = 0;
psdone_out = 0;
psdone_out1 = 0;
rst_int = 0;
clkinstopped_out = 0;
clkfbstopped_out = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_period_tmp_t = 0;
period_avg = 0;
period_fb = 0;
clkin_lost_val = 500;
clkfb_lost_val = 500;
clkin_lost_val_lk = 500;
fb_delay = 0;
clkfbm1_div = 1;
clkfbm2_div = 1;
clkfbm1_div1 = 0;
clkfbm2_div1 = 0;
clkvco_delay = 0;
val_tmp = 0;
dly_tmp = 0;
fbm1_comp_delay = 0;
clkfbm1pm_rl = 0;
period_vco = 0;
period_vco1 = 0;
period_vco2 = 0;
period_vco3 = 0;
period_vco4 = 0;
period_vco5 = 0;
period_vco6 = 0;
period_vco7 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
period_ps = 0;
period_ps_old = 0;
clkfb_frac_ht = 0;
clkfb_frac_lt = 0;
clk0_frac_ht = 0;
clk0_frac_lt = 0;
clkvco_rm_cnt = 0;
fb_delay_found = 0;
fb_delay_found_tmp = 0;
clkin_edge = 0;
delay_edge = 0;
fbclk_tmp = 0;
clkfb_tst = 0;
clkout_en = 0;
clkout_en0 = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
clkout_mux = 8'b0;
clkout_ps_mux = 8'b0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
rst_edge = 0;
rst_ht = 0;
drdy_out = 0;
drdy_out1 = 0;
cddcdone_out = 0;
locked_out1 = 0;
locked_out_tmp = 0;
do_out1 = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 0;
clkout0_out = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clk2_dly_cnt = 6'b0;
clk3_dly_cnt = 6'b0;
clk4_dly_cnt = 6'b0;
clk5_dly_cnt = 6'b0;
clk6_dly_cnt = 6'b0;
clkfbm1_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clk2_cnt = 8'b0;
clk3_cnt = 8'b0;
clk4_cnt = 8'b0;
clk5_cnt = 8'b0;
clk6_cnt = 8'b0;
clkfbm1_cnt = 8'b0;
clkfbm2_cnt = 8'b0;
clkind_cnt = 8'b0;
clkout0_out = 0;
clkout1_out = 0;
clkout2_out = 0;
clkout3_out = 0;
clkout4_out = 0;
clkout5_out = 0;
clkout6_out = 0;
clk0_nf_out = 0;
clk0_frac_out = 0;
clk1_out = 0;
clk2_out = 0;
clk3_out = 0;
clk4_out = 0;
clk5_out = 0;
clk6_out = 0;
clkfb_out = 0;
clkfbm1_nf_out = 0;
clkfbm1_frac_out = 0;
clkfbm2_out = 0;
clkfbm2_out_tmp = 0;
clkind_out = 0;
clkind_out_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
assign CLKOUT6 = clkout6_out;
assign CLKOUT5 = clkout5_out;
assign CLKOUT4 = clkout4_out;
assign CLKOUT3 = clkout3_out;
assign CLKOUT2 = clkout2_out;
assign CLKOUT1 = clkout1_out;
assign CLKOUT0 = clkout0_out;
assign CLKFBOUT = clkfb_out;
assign CLKOUT3B = ~clkout3_out;
assign CLKOUT2B = ~clkout2_out;
assign CLKOUT1B = ~clkout1_out;
assign CLKOUT0B = ~clkout0_out;
assign CLKFBOUTB = ~clkfb_out;
assign #1 clkinsel_tmp = CLKINSEL_in;
assign glock = (startup_wait_sig) ? locked_out_tmp : 1;
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial begin
init_chk = 0;
#1;
init_chk = 1;
end
always @(CLKINSEL_in or posedge init_chk ) begin
if(trig_attr_chk)
begin
if ($time > 1 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin
$display("Input Error : Input clock can only be switched when RST=1. CLKINSEL on %s instance %m at time %t changed when RST low, which should change at RST high.", MODULE_NAME, $time);
$finish;
end
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin
if (CLKIN1_PERIOD_REG > clkin_chk_t1 || CLKIN1_PERIOD_REG < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin
if (CLKIN2_PERIOD_REG > clkin_chk_t1 || CLKIN2_PERIOD_REG < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG;
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_REG) / (period_clkin * DIVCLK_DIVIDE_REG);
if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
$finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
$finish;
end
end
clkpfd_freq_init_chk = (1000.0) / (period_clkin * DIVCLK_DIVIDE_REG);
if (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted PFD frequency range.", clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG);
$finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted PFD frequency range.", clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG);
$finish;
end
end
end
end
assign init_trig = 1;
assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in;
assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0;
assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkpll_r or posedge rst_input)
if (rst_input)
rst_int <= 1;
else
rst_int <= rst_input ;
assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped);
//simprim_rst_h
always @(posedge pwrdwn_in1 or posedge pchk_clr)
if (pwrdwn_in1)
pwrdwn_in1_h <= 1;
else if (pchk_clr)
pwrdwn_in1_h <= 0;
always @(posedge RST_in or posedge pchk_clr)
if (RST_in)
rst_input_r_h <= 1;
else if (pchk_clr)
rst_input_r_h <= 0;
always @(rst_input )
if (rst_input==1) begin
rst_edge = $time;
pchk_clr = 0;
end
else if (rst_input==0 && rst_edge > 1) begin
rst_ht = $time - rst_edge;
if (rst_ht < 1500) begin
if (rst_input_r_h == 1 && pwrdwn_in1_h == 1)
$display("Input Error : RST and PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0)
$display("Input Error : RST on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1)
$display("Input Error : PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
end
pchk_clr = 1;
end
//endsimprim_rst_h
//
// DRP port read and write
//
assign do_out = dr_sram[daddr_lat];
always @(posedge DCLK_in or posedge GSR or CDDCREQ_in)
if (GSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 0;
end
else begin
if (DEN_in == 1) begin
valid_daddr = addr_is_valid(DADDR_in);
if (drp_lock == 1) begin
$display(" Warning : DEN is high at %s instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", MODULE_NAME, $time);
end
else begin
drp_lock <= 1;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
daddr_lat <= DADDR_in;
end
if (valid_daddr && ( DADDR_in == 7'b1001111 ||
DADDR_in == 7'b1001110 || DADDR_in == 7'b0101000 ||
(DADDR_in >= 7'b0011000 && DADDR_in <= 7'b0011010) ||
(DADDR_in >= 7'b0000110 && DADDR_in <= 7'b0010110))) begin
end
else begin
$display(" Warning : Address DADDR=%b is unsupported at %s instance %m at time %t. ", DADDR_in, MODULE_NAME, $time);
end
if (DWE_in == 1) begin // write process
if (rst_input == 1 || CDDCREQ_in == 1) begin
if (valid_daddr && ( DADDR_in == 7'b1001111 ||
DADDR_in == 7'b1001110 || DADDR_in == 7'b0101000 ||
(DADDR_in >= 7'b0011000 && DADDR_in <= 7'b0011010) ||
(DADDR_in >= 7'b0000110 && DADDR_in <= 7'b0010110))) begin
dr_sram[DADDR_in] <= DI_in;
end
if (DADDR_in == 7'b0001001) begin
clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, DI_in, DADDR_in);
clk0_frac[2:0] <= DI_in[14:12];
clk0_frac_en <= DI_in[11];
end
if (DADDR_in == 7'b0001000) begin
clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, DI_in, DADDR_in);
clk0pmr_sel[2:0] <= DI_in[15:13];
end
if (DADDR_in == 7'b0001011)
clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, DI_in, DADDR_in);
if (DADDR_in == 7'b0001010)
clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0001101)
clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, DI_in, DADDR_in);
if (DADDR_in == 7'b0001100)
clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0001111)
clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, DI_in, DADDR_in);
if (DADDR_in == 7'b0001110)
clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0010001)
clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, DI_in, DADDR_in);
if (DADDR_in == 7'b0010000)
clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0010011) begin
clkout_delay_para_drp (clkout6_dly, clk6_nocnt, clk6_edge, DI_in, DADDR_in);
clkfbpmf_sel[2:0] <= DI_in[13:11];
end
if (DADDR_in == 7'b0010010)
clkout_hl_para_drp (clk6_lt, clk6_ht, clk6pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0000111) begin
clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, DI_in, DADDR_in);
clk0pmf_sel[2:0] <= DI_in[13:11];
end
if (DADDR_in == 7'b0000110)
clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, DI_in, DADDR_in);
if (DADDR_in == 7'b0010101) begin
clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, DI_in, DADDR_in);
clkfbtmp_nocnti = DI_in[6];
clkfb_frac[2:0] <= DI_in[14:12];
clkfb_frac_en <= DI_in[11];
end
if (DADDR_in == 7'b0010100) begin
clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, DI_in, DADDR_in);
clkfbpmr_sel[2:0] <= DI_in[15:13];
clkfbtmp_lti = {2'b00, DI_in[5:0]};
clkfbtmp_hti = {2'b00, DI_in[11:6]};
if (clkfbtmp_nocnti == 1)
clkfbtmp_divi = 8'b00000001;
else if (DI_in[5:0] == 6'b0 && DI_in[11:6] == 6'b0)
clkfbtmp_divi = 8'b10000000;
else if (DI_in[5:0] == 6'b0)
clkfbtmp_divi = 64 + clkfbtmp_hti;
else if (DI_in[11:6] == 6'b0)
clkfbtmp_divi = 64 + clkfbtmp_lti;
else
clkfbtmp_divi = clkfbtmp_hti + clkfbtmp_lti;
if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %h and over the range of %f to %f.", DADDR_in, DI_in, clkfbtmp_divi, MODULE_NAME, $time, M_MIN, M_MAX);
end
if (DADDR_in == 7'b0010110) begin
clkind_lti = {2'b00, DI_in[5:0]};
clkind_hti = {2'b00, DI_in[11:6]};
clkind_lt <= clkind_lti;
clkind_ht <= clkind_hti;
clkind_nocnt <= DI_in[12];
clkind_nocnti = DI_in[12];
clkind_edgei = DI_in[13];
clkind_edge <= DI_in[13];
if (DI_in[12] == 1)
clkind_divi = 8'b00000001;
else if (DI_in[5:0] == 6'b0 && DI_in[11:6] == 6'b0)
clkind_divi = 8'b10000000;
else if (DI_in[5:0] == 6'b0)
clkind_divi = 64 + clkind_hti;
else if (DI_in[11:6] == 6'b0)
clkind_divi = 64 + clkind_lti;
else
clkind_divi = clkind_hti + clkind_lti;
clkind_div <= clkind_divi;
if (clkind_divi > D_MAX || (clkind_divi < 1 && clkind_nocnti == 0))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to %d.", DADDR_in, DI_in, clkind_divi, MODULE_NAME, $time, D_MAX);
end
end
else begin
$display(" Error : RST is low at %s instance %m at time %t. RST need to be high when change %s paramters through DRP. ", MODULE_NAME, $time, MODULE_NAME);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
end
else begin
drp_lock <= 0;
drdy_out <= 1;
drp_lock_lat_cnt <= 0;
end
end
if (drdy_out == 1) drdy_out <= 0;
end
always @(posedge CDDCREQ_in or negedge CDDCREQ_in)
begin
if (CDDCREQ_in == 1'b1)
cddcdone_out <= 1'b0;
else
begin
@(posedge clkpll)
@(posedge clkpll)
cddcdone_out <= ~CDDCREQ_in;
end
end
function addr_is_valid;
input [6:0] daddr_funcin;
begin
addr_is_valid = 1;
for (i=0; i<=6; i=i+1)
if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
addr_is_valid = 0;
end
endfunction
// end process drp;
//
// determine clock period
//
always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag)
if (rst_int || rst_clkinsel_flag)
begin
clkin_period[0] <= period_vco_target;
clkin_period[1] <= period_vco_target;
clkin_period[2] <= period_vco_target;
clkin_period[3] <= period_vco_target;
clkin_period[4] <= period_vco_target;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end
else begin
clkin_edge <= $time;
if (clkin_edge != 0 && clkinstopped_out == 0 && rst_clkinsel_flag == 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0)
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
end
if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0)
pll_locked_tm <= 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(posedge pll_locked_tmp1)
if (CLKINSEL_in === 0) begin
pchk_tmp1 = CLKIN2_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN2_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN2 period and attribute CLKIN2_PERIOD on %s instance %m are not same.", MODULE_NAME);
end
end
else begin
pchk_tmp1 = CLKIN1_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN1_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN1 period and attribute CLKIN1_PERIOD on %s instance %m are not same.", MODULE_NAME);
end
end
always @(negedge rst_int)
if (clkfb_frac_en == 0) begin
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
clkout_en_val = mf_product - 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
if (clkout_en0_tmp==0 )
clkout_en0 = 0;
else begin
if (clkfb_frac_en == 1) begin
if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
else begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in_o )
if (rst_in_o)
clkout_en = 0;
else
clkout_en = clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 = pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_int)
if (rst_int) begin
assign pll_locked_tmp2 = 0;
assign clkout_en0 = 0;
assign clkout_en1 = 0;
end
else begin
deassign pll_locked_tmp2;
deassign clkout_en0;
deassign clkout_en1;
end
assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0;
always @(rst_int or locked_out)
if (rst_int == 1)
locked_out_tmp <= #1000 0;
else
locked_out_tmp <= locked_out;
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4] or period_avg ) begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp_t = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp_t = clkin_period[1] - clkin_period[0];
if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2]
+ clkin_period[3] + clkin_period[4])/5;
end
always @(clkinstopped_out_dly or rst_int)
if (rst_int)
clkinstopped_hold = 0;
else begin
if (clkinstopped_out)
clkinstopped_hold <= #1 1;
else begin
if (clkin_hold_f)
clkinstopped_hold = 0;
end
end
always @(posedge clkinstopped_out) begin
period_avg_stpi <= period_avg;
pd_stp_p <= #1 1;
@(negedge clkvco)
pd_stp_p <= #1 0;
end
always @(negedge clkvco or posedge rst_int or posedge pd_stp_p)
if (rst_int) begin
period_avg_stp <= 1000;
vco_stp_f <= 0;
end
else if (pd_stp_p)
period_avg_stp <= period_avg_stpi;
else begin
if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin
if (period_vco > 1739)
vco_stp_f <= 1;
else begin
period_avg_stp <= period_avg_stp + 1;
end
end
end
always @(period_avg or lock_period or clkind_div)
if (period_avg > 500 && lock_period == 1) begin
clkin_lost_val = ((period_avg * 1.5) / 500) - 1;
clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1;
end
always @(clkfb_frac_en or clkfbm1_f_div or clkfbm1_div)
if (clkfb_frac_en)
clkfbm1_div_t = clkfbm1_f_div;
else
clkfbm1_div_t = clkfbm1_div;
always @(period_avg or clkind_div or clkfbm1_div_t or clkinstopped_hold
or period_avg_stp or posedge rst_clkinstopped_rc)
if (period_avg > 0 ) begin
md_product = clkind_div * clkfbm1_div_t;
m_product = clkfbm1_div_t;
m_product2 = clkfbm1_div_t / 2;
clkvco_div_fint = $rtoi(clkfbm1_div_t/clkind_div);
clkvco_div_frac = (clkfbm1_div_t/clkind_div) - clkvco_div_fint;
if (clkvco_div_frac > 0.000)
clkvco_frac_en = 1;
else
clkvco_frac_en = 0;
period_fb = period_avg * clkind_div;
period_vco_tmp = period_fb / clkfbm1_div_t;
period_vco_rl = 1.0 * period_fb / clkfbm1_div_t;
clkvco_pdrm = (period_avg * clkind_div / clkfbm1_div_t) - period_vco_tmp;
period_vco_mf = period_avg * 8;
if (clkinstopped_hold == 1) begin
if (clkin_hold_f) begin
period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
end
else begin
period_vco = period_avg_stp * clkind_div /clkfbm1_div_t;
period_vco_rl = period_avg_stp * clkind_div /clkfbm1_div_t;
end
end
else
period_vco = period_vco_tmp;
clkfbm1_div_t_int = $rtoi(clkfbm1_div_t);
period_vco_rm = period_fb % clkfbm1_div_t_int;
if (period_vco_rm > 1) begin
if (period_vco_rm > m_product2) begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
if (period_vco_half_rm < 1)
period_vco_half_rm2 = 0;
else
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbm1_div_t;
clkin_dly_t = period_avg * (clkind_div + 1.25);
clkfb_dly_t = period_fb * 2.25 ;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco3 = period_vco * 3/ 8;
period_vco4 = period_vco / 2;
period_vco5 = period_vco * 5 / 8;
period_vco6 = period_vco *3 / 4;
period_vco7 = period_vco * 7 / 8;
end
always @(clkfbm1_ht or clkfbm1_lt or clkfb_frac or clkfb_frac_en or clkfbpmf_sel)
if (clkfb_frac_en == 1 && clkfb_div_adj == 1) begin
if (clkfbpmf_sel < 4) begin
clkfbm1_odd_frac = clkfb_frac;
tmp_fbo = 0.0;
tmp_fbq = 2 * clkfbm1_lt - clkfbm1_ht + 1;
end
else if (clkfbpmf_sel > 4 ) begin
clkfbm1_odd_frac = clkfb_frac + 8;
tmp_fbo = 1.0;
tmp_fbq = 2 * clkfbm1_lt - clkfbm1_ht;
end
else begin
clkfbm1_odd_frac = clkfb_frac + 8;
tmp_fbo = 1.0;
tmp_fbq = 2.0 * clkfbm1_lt - clkfbm1_ht + 1.0;
end
tmp_fbp = clkfbm1_odd_frac / 8.0 - tmp_fbo;
clkfbm1_f_div = 2.0 * tmp_fbq + tmp_fbp + tmp_fbo;
clkfb_div_fint = $rtoi(clkfbm1_f_div);
clkfb_div_frac = clkfbm1_f_div - clkfb_div_fint;
clkfb_div_frac_int = $rtoi(clkfb_div_frac * 8);
clkfb_div_fint_tmp1 = clkfb_div_fint / 2;
clkfb_div_fint_odd = clkfb_div_fint - clkfb_div_fint_tmp1 -clkfb_div_fint_tmp1;
clkfbm1_fht = clkfb_div_fint /2;
clkfbm1_flt = clkfb_div_fint /2;
if (clkfb_div_fint_odd > 0) begin
clkfbm1r_sel = (8 + clkfb_div_frac_int) / 2;
clkfbm1f_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
end
else begin
clkfbm1f_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1r_sel = clkfb_div_frac_int / 2;
end
end
always @(clkfbm1_f_div or clkfb_frac_en)
if (clkfb_frac_en == 1)
mf_product = clkfbm1_f_div * 8;
always @(clk0_ht or clk0_lt or clk0_frac or clk0_frac_en or clk0pmf_sel)
if (clk0_frac_en == 1 && clk0_div_adj == 1) begin
if (clk0pmf_sel < 4) begin
clk0_odd_frac = clk0_frac;
tmp_f0o = 0.0;
tmp_f0q = 2 * clk0_lt - clk0_ht + 1;
end
else if (clk0pmf_sel > 4 ) begin
clk0_odd_frac = clk0_frac + 8;
tmp_f0o = 1.0;
tmp_f0q = 2 * clk0_lt - clk0_ht;
end
else begin
clk0_odd_frac = clk0_frac + 8;
tmp_f0o = 1.0;
tmp_f0q = 2.0 * clk0_lt - clk0_ht + 1.0;
end
tmp_f0p = clk0_odd_frac / 8.0 - tmp_f0o;
clk0_f_div = 2.0 * tmp_f0q + tmp_f0p + tmp_f0o;
clk0_div_fint = $rtoi(clk0_f_div);
clk0_div_frac = clk0_f_div - clk0_div_fint;
clk0_div_frac_int = $rtoi(clk0_div_frac * 8);
clk0_div_fint_tmp1 = clk0_div_fint / 2;
clk0_div_fint_odd = clk0_div_fint - clk0_div_fint_tmp1 -clk0_div_fint_tmp1;
clk0_fht = clk0_div_fint /2;
clk0_flt = clk0_div_fint /2;
if (clk0_div_fint_odd > 0) begin
clk0pm_rsel = (8 + clk0_div_frac_int) / 2;
clk0pm_fsel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
end
else begin
clk0pm_fsel = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_rsel = clk0_div_frac_int / 2;
end
end
always @(period_vco_rl or clkfbm1_fht or clkfbm1_flt or clkfbm1r_sel or clkfbm1pm_sel_int) begin
clkfb_frac_ht = period_vco_rl * clkfbm1_fht + (period_vco_rl * clkfbm1pm_sel_int) / 8;
clkfb_frac_lt = period_vco_rl * clkfbm1_flt + (period_vco_rl * clkfbm1r_sel) / 8;
end
always @(period_vco_rl or clk0_fht or clk0_flt or clk0pm_sel_int or clk0pm_rsel) begin
clk0_frac_ht = period_vco_rl * clk0_fht + (period_vco_rl * clk0pm_sel_int) / 8;
clk0_frac_lt = period_vco_rl * clk0_flt + (period_vco_rl * clk0pm_rsel) / 8;
end
always @(period_vco or ps_in_ps)
if (fps_en == 1) begin
period_ps_old = period_ps;
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && PSINCDEC_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @( clkpll_r )
clkpll_tmp1 <= #(period_avg) clkpll_r;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(posedge clkinstopped_out or posedge rst_int)
if ( rst_int)
clkinstopped_vco_f <= 0;
else begin
clkinstopped_vco_f <= 1;
@(negedge clkinstopped_out or posedge rst_int )
if (rst_int)
clkinstopped_vco_f <= 0;
else begin
@(posedge clkpll);
@(posedge clkpll)
clkinstopped_vco_f <= 0;
end
end
always @(posedge clkinstopped_out or posedge rst_int)
if (rst_int)
clkinstopped_out1 <= 0;
else begin
clkinstopped_out1 <= 1;
if (clkin_hold_f == 1) begin
@(posedge locked_out or posedge rst_int)
clkinstopped_out1 <= 0;
end
else begin
if (CLKINSEL_in == 1)
$display(" Warning : input CLKIN1 of %s on instance %m is stopped. Reset is required for %s when input clock returns.", MODULE_NAME, MODULE_NAME);
else
$display(" Warning : input CLKIN2 of %s on instance %m is stopped. Reset is required for %s when input clock returns.", MODULE_NAME, MODULE_NAME);
end
end
always @(posedge clkfbstopped_out or posedge rst_int)
if (rst_int)
clkfbstopped_out1 <= 0;
else begin
clkfbstopped_out1 <= 1;
@(posedge locked_out)
clkfbstopped_out1 <= 0;
end
always @(clkout_en_t)
if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val)
rst_clkinstopped_tm = 1;
else
rst_clkinstopped_tm = 0;
always @(negedge clkinstopped_out or posedge rst_int)
if (rst_int)
rst_clkinstopped <= 0;
else
if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin
@(posedge rst_clkinstopped_tm)
rst_clkinstopped <= #period_vco4 1;
@(negedge rst_clkinstopped_tm ) begin
rst_clkinstopped <= #period_vco5 0;
rst_clkinstopped_rc <= #period_vco6 1;
rst_clkinstopped_rc <= #period_vco7 0;
end
end
always @(posedge clkinstopped_out or posedge rst_int)
if (rst_int)
clkinstopped_out_dly <= 0;
else begin
clkinstopped_out_dly <= 1;
if (clkin_hold_f == 1) begin
@(negedge rst_clkinstopped_rc or posedge rst_int)
clkinstopped_out_dly <= 0;
end
end
always @(clkinstopped_out or posedge rst_int)
if (rst_int)
clkinstopped_out_dly2 <= 0;
else
clkinstopped_out_dly2 <= #2 clkinstopped_out;
always @(negedge rst_clkinstopped or posedge rst_int)
if (rst_int)
rst_clkinstopped_lk <= 0;
else begin
rst_clkinstopped_lk <= 1;
@(posedge locked_out)
rst_clkinstopped_lk <= 0;
end
always @(clkinstopped_vco_f or clkinstopped_out1 or clkvco_lk or
clkvco_lk_tmp or rst_int)
if (rst_int)
clkvco_lk = 0;
else begin
if (clkinstopped_out1 == 1 && clkin_stop_f == 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else if (clkinstopped_vco_f == 1 && period_vco_half > 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else
clkvco_lk = clkvco_lk_tmp;
end
always @(posedge clkpll)
if (clkfb_frac_en == 1 || clkvco_frac_en == 1) begin
if (pll_locked_tm ==1 ) begin
clkvco_lk_tmp <= 1;
cmpvco = 0.0;
for (ik1=1; ik1 < mf_product; ik1=ik1+1) begin
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( cmpvco >= 1.0 ) begin
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco - 1.0 + clkvco_pdrm;
end
else if ( cmpvco <= -1.0 ) begin
#(period_vco_half_rm2) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + 1.0 + clkvco_pdrm;
end
else begin
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + clkvco_pdrm;
end
clkout_en_t <= ik1;
end
clkout_en_t <= ik1;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
else begin
if (pll_locked_tm ==1) begin
clkvco_lk_tmp <= 1;
clkvco_rm_cnt = 0;
clkout_en_t <= 0;
vcoflag = 0;
if ( period_vco_cmp_flag == 1) begin
vcoflag = 1;
for (ik2=1; ik2 < m_product; ik2=ik2+1) begin
clkout_en_t <= ik2;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
// #(period_vco_half1) clkvco_lk_tmp <= 1;
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik2;
end
else if ( period_vco_cmp_flag == 2 ) begin
vcoflag = 1;
for (ik3=1; ik3 < m_product; ik3=ik3+1) begin
clkout_en_t <= ik3;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik3;
end
else begin
vcoflag = 1;
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
end
#(period_vco_half) clkvco_lk_tmp <= 0;
if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) begin
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
end
always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or clkfbm1pm_rl
or lock_period or ps_in_ps )
if (lock_period == 1) begin
if (clkfb_frac_en == 1) begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl);
end
else begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl);
end
dly_tmp1 = fb_delay + fbm1_comp_delay;
dly_tmp_int = 1;
if (clkfb_fps_en == 1) begin
if (ps_in_ps < 0) begin
tmp_ps_val1 = -1 * ps_in_ps;
tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0;
if (tmp_ps_val2 > dly_tmp1 ) begin
dly_tmp_int = -1;
dly_tmp = tmp_ps_val2 - dly_tmp1;
end
else if (tmp_ps_val2 == dly_tmp1 ) begin
dly_tmp_int = 0;
dly_tmp = 0;
end
else begin
dly_tmp_int = 1;
dly_tmp = dly_tmp1 - tmp_ps_val2;
end
end
else
dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0;
end
else
dly_tmp = dly_tmp1;
if (dly_tmp_int < 0)
clkvco_delay = dly_tmp;
else begin
if (clkfb_frac_en == 1 && dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
end
always @(period_vco or ps_in_ps )
if (fps_en == 1) begin
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && PSINCDEC_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @(clkfbm1pm_sel)
case (clkfbm1pm_sel)
3'b000 : clkfbm1pm_rl = 0.0;
3'b001 : clkfbm1pm_rl = 0.125;
3'b010 : clkfbm1pm_rl = 0.25;
3'b011 : clkfbm1pm_rl = 0.375;
3'b100 : clkfbm1pm_rl = 0.50;
3'b101 : clkfbm1pm_rl = 0.625;
3'b110 : clkfbm1pm_rl = 0.75;
3'b111 : clkfbm1pm_rl = 0.875;
endcase
always @(clkvco_lk)
clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk;
always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm)
if ( pll_locked_tm && vco_stp_f == 0) begin
if (dly_tmp == 0)
clkvco = clkvco_lk;
else
clkvco = clkvco_lk_dly_tmp;
end
else
clkvco = 0;
always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge or clk0_frac_en)
if (clk0_frac_en == 0)
clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge);
always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge)
clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge);
always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge)
clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge);
always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge)
clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge);
always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge)
clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge);
always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge)
clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge);
always @(clk6_ht or clk6_lt or clk6_nocnt or init_trig or clk6_edge)
clkout_pm_cal(clk6_ht1, clk6_div, clk6_div1, clk6_ht, clk6_lt, clk6_nocnt, clk6_edge);
always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfb_frac_en)
if (clkfb_frac_en == 0) begin
clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge);
end
always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge)
clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge);
always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge)
clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge);
always @(posedge PSCLK_in or posedge rst_int)
if (rst_int) begin
ps_in_ps <= ps_in_init;
ps_cnt <= 0;
psen_w <= 0;
end
else if (fps_en == 1) begin
if (PSEN_in) begin
if (psen_w == 1)
$display(" Error : PSEN on %s instance %m is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period.", MODULE_NAME, $time);
psen_w <= 1;
if (ps_lock == 1)
$display(" Warning : Please wait for PSDONE signal on %s instance %m at time %t before adjusting the Phase Shift.", MODULE_NAME, $time);
else if (PSINCDEC_in == 1) begin
if (ps_cnt < ps_max)
ps_cnt <= ps_cnt + 1;
else
ps_cnt <= 0;
if (ps_in_ps < ps_max)
ps_in_ps <= ps_in_ps + 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
else if (PSINCDEC_in == 0) begin
ps_cnt_neg = (-1) * ps_cnt;
ps_in_ps_neg = (-1) * ps_in_ps;
if (ps_cnt_neg < ps_max)
ps_cnt <= ps_cnt - 1;
else
ps_cnt <= 0;
if (ps_in_ps_neg < ps_max)
ps_in_ps <= ps_in_ps - 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
end
else
psen_w <= 0;
if ( psdone_out == 1)
ps_lock <= 0;
end
always @(posedge ps_lock )
if (fps_en == 1) begin
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
begin
psdone_out = 1;
@(posedge PSCLK_in);
psdone_out = 0;
end
end
always @(rst_in_o)
if (rst_in_o) begin
assign clkout_mux = 8'b0;
assign clkout_ps_mux = 8'b0;
assign clkout_ps = 0;
assign clkout_ps_tmp1 = 0;
assign clkout_ps_tmp2 = 0;
assign clk0_frac_out = 0;
assign clkfbm1_frac_out = 0;
end
else begin
deassign clkout_mux;
deassign clkout_ps_mux;
deassign clkout_ps;
deassign clkout_ps_tmp1;
deassign clkout_ps_tmp2;
deassign clk0_frac_out;
deassign clkfbm1_frac_out;
end
always @(rst_clkinstopped)
if (rst_clkinstopped) begin
assign clkfb_frac_ht = 50;
assign clkfb_frac_lt = 50;
end
else begin
deassign clkfb_frac_ht;
deassign clkfb_frac_lt;
end
//always @(clkvco or clkout_en )
always @(clkvco)
if (clkout_en) begin
clkout_mux[0] = clkvco;
clkout_mux[1] <= #(period_vco1) clkvco;
clkout_mux[2] <= #(period_vco2) clkvco;
clkout_mux[3] <= #(period_vco3) clkvco;
clkout_mux[4] <= #(period_vco4) clkvco;
clkout_mux[5] <= #(period_vco5) clkvco;
clkout_mux[6] <= #(period_vco6) clkvco;
clkout_mux[7] <= #(period_vco7) clkvco;
end
always @(clkout_ps or clkout_en )
if (clkout_en) begin
clkout_ps_mux[0] = clkout_ps;
clkout_ps_mux[1] <= #(period_vco1) clkout_ps;
clkout_ps_mux[2] <= #(period_vco2) clkout_ps;
clkout_ps_mux[3] <= #(period_vco3) clkout_ps;
clkout_ps_mux[4] <= #(period_vco4) clkout_ps;
clkout_ps_mux[5] <= #(period_vco5) clkout_ps;
clkout_ps_mux[6] <= #(period_vco6) clkout_ps;
clkout_ps_mux[7] <= #(period_vco7) clkout_ps;
end
always @(clkvco or clkout_en )
if ( fps_en == 1) begin
clkvco_ps_tmp1 <= #(period_ps) clkvco;
clkvco_ps_tmp2 <= #(period_ps_old) clkvco;
end
always @(negedge clkout_ps)
clkout_ps_eg <= $time;
always @(posedge clkout_ps)
clkout_ps_peg <= $time;
always @(ps_lock)
ps_lock_dly <= #1 ps_lock;
always @(posedge ps_lock_dly)
if ((period_ps - period_ps_old) > period_vco_half ) begin
if (clkout_ps == 0) begin
if (clkvco_ps_tmp2 == 1) begin
clkout_ps_w = $time - clkout_ps_eg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(negedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
else begin
if (clkvco_ps_tmp2 == 0) begin
clkout_ps_w = $time - clkout_ps_peg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(posedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
@(posedge clkvco_ps_tmp2);
@(negedge clkvco_ps_tmp2)
if (clkvco_ps_tmp1 == 0)
clkvco_ps_tmp2_en <= 0;
else
@(negedge clkvco_ps_tmp1)
clkvco_ps_tmp2_en <= 0;
end
always @(clkvco or clkvco_ps_tmp1 or clkvco_ps_tmp2 or clkvco_ps_tmp2_en )
if (fps_en == 1) begin
if (ps_in_ps == 0 )
clkout_ps = clkvco;
else if (clkvco_ps_tmp2_en == 1)
clkout_ps = clkvco_ps_tmp2;
else
clkout_ps = clkvco_ps_tmp1;
end
assign clk0_sel_mux = (clk0_fps_en == 1) ? clkout_ps_mux : clkout_mux;
assign clkfb_sel_mux = (clkfb_fps_en == 1) ? clkout_ps_mux : clkout_mux;
assign clk0in = (clk0_fps_en == 1) ? clkout_ps_mux[clk0pm_sel] : clkout_mux[clk0pm_sel1];
assign clk1in = (clk1_fps_en == 1) ? clkout_ps_mux[clk1pm_sel] : clkout_mux[clk1pm_sel];
assign clk2in = (clk2_fps_en == 1) ? clkout_ps_mux[clk2pm_sel] : clkout_mux[clk2pm_sel];
assign clk3in = (clk3_fps_en == 1) ? clkout_ps_mux[clk3pm_sel] : clkout_mux[clk3pm_sel];
assign clk4in = (clk4_fps_en == 1) ? clkout_ps_mux[clk4pm_sel] : ((clkout4_cascade_int == 1) ? clk6_out : clkout_mux[clk4pm_sel]);
assign clk5in = (clk5_fps_en == 1) ? clkout_ps_mux[clk5pm_sel] : clkout_mux[clk5pm_sel];
assign clk6in = (clk6_fps_en == 1) ? clkout_ps_mux[clk6pm_sel] : clkout_mux[clk6pm_sel];
assign clkfbm1in = (clkfb_fps_en == 1) ? clkout_ps_mux[clkfbm1pm_sel] : clkout_mux[clkfbm1pm_sel1];
assign clkfbm1pm_sel1 = clkfbm1pm_sel;
assign clk0pm_sel1 = clk0pm_sel;
assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0;
assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0;
assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0;
assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0;
assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0;
assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0;
assign clk6ps_en = (clk6_dly_cnt == clkout6_dly) ? clkout_en : 0;
assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0;
/*always @(posedge clk0in)
if (clk0ps_en && clk0_frac_en) begin
clk0_frac_out <= 1;
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
#(clk0_frac_ht) clk0_frac_out <= 0;
#(clk0_frac_lt) clk0_frac_out <= 1;
end
#(clk0_frac_ht) clk0_frac_out <= 0;
#(clk0_frac_lt - period_vco1);
end*/
always @(posedge clk0in)
if (clkout_en && clk0_frac_en) begin
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
clk0_frac_out <= 1;
#(clk0_frac_ht - 2);
@(posedge clk0_sel_mux[0] or posedge clk0_sel_mux[1] or posedge clk0_sel_mux[2] or posedge clk0_sel_mux[3] or posedge clk0_sel_mux[4]
or posedge clk0_sel_mux[5] or posedge clk0_sel_mux[6] or posedge clk0_sel_mux[7]);
clk0_frac_out <= 0;
#(clk0_frac_lt - 2);
@(posedge clk0_sel_mux[0] or posedge clk0_sel_mux[1] or posedge clk0_sel_mux[2] or posedge clk0_sel_mux[3] or posedge clk0_sel_mux[4]
or posedge clk0_sel_mux[5] or posedge clk0_sel_mux[6] or posedge clk0_sel_mux[7]);
end
clk0_frac_out <= 1;
#(clk0_frac_ht - 2);
@(posedge clk0_sel_mux[0] or posedge clk0_sel_mux[1] or posedge clk0_sel_mux[2] or posedge clk0_sel_mux[3] or posedge clk0_sel_mux[4]
or posedge clk0_sel_mux[5] or posedge clk0_sel_mux[6] or posedge clk0_sel_mux[7]);
clk0_frac_out <= 0;
#(clk0_frac_lt - 2);
end
/*always @(posedge clkfbm1in)
if (clkfbm1ps_en && clkfb_frac_en) begin
clkfbm1_frac_out <= 1;
for (ib=1; ib < 8; ib=ib+1) begin
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt) clkfbm1_frac_out <= 1;
end
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt - period_vco1);
end
else
clkfbm1_frac_out <= 0;*/
always @(posedge clkfbm1in)
if (clkout_en && clkfb_frac_en) begin
clkfbm1_frac_out <= 1;
for (ib=1; ib < 8; ib=ib+1) begin
#(clkfb_frac_ht - 2);
@(posedge clkfb_sel_mux[0] or posedge clkfb_sel_mux[1] or posedge clkfb_sel_mux[2] or posedge clkfb_sel_mux[3] or posedge clkfb_sel_mux[4]
or posedge clkfb_sel_mux[5] or posedge clkfb_sel_mux[6] or posedge clkfb_sel_mux[7]);
clkfbm1_frac_out <= 0;
#(clkfb_frac_lt - 2);
@(posedge clkfb_sel_mux[0] or posedge clkfb_sel_mux[1] or posedge clkfb_sel_mux[2] or posedge clkfb_sel_mux[3] or posedge clkfb_sel_mux[4]
or posedge clkfb_sel_mux[5] or posedge clkfb_sel_mux[6] or posedge clkfb_sel_mux[7]);
clkfbm1_frac_out <= 1;
end
#(clkfb_frac_ht - 2);
@(posedge clkfb_sel_mux[0] or posedge clkfb_sel_mux[1] or posedge clkfb_sel_mux[2] or posedge clkfb_sel_mux[3] or posedge clkfb_sel_mux[4]
or posedge clkfb_sel_mux[5] or posedge clkfb_sel_mux[6] or posedge clkfb_sel_mux[7]);
clkfbm1_frac_out <= 0;
#(clkfb_frac_lt - 2);
end
else
clkfbm1_frac_out <= 0;
always @(negedge clk0in or posedge rst_in_o)
if (rst_in_o)
clk0_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk0_dly_cnt < clkout0_dly)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in_o)
if (rst_in_o)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clkout1_dly && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
always @(negedge clk2in or posedge rst_in_o)
if (rst_in_o)
clk2_dly_cnt <= 6'b0;
else
if (clk2_dly_cnt < clkout2_dly && clkout_en ==1)
clk2_dly_cnt <= clk2_dly_cnt + 1;
always @(negedge clk3in or posedge rst_in_o)
if (rst_in_o)
clk3_dly_cnt <= 6'b0;
else
if (clk3_dly_cnt < clkout3_dly && clkout_en ==1)
clk3_dly_cnt <= clk3_dly_cnt + 1;
always @(negedge clk4in or posedge rst_in_o)
if (rst_in_o)
clk4_dly_cnt <= 6'b0;
else
if (clk4_dly_cnt < clkout4_dly && clkout_en ==1)
clk4_dly_cnt <= clk4_dly_cnt + 1;
always @(negedge clk5in or posedge rst_in_o)
if (rst_in_o)
clk5_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk5_dly_cnt < clkout5_dly)
clk5_dly_cnt <= clk5_dly_cnt + 1;
end
always @(negedge clk6in or posedge rst_in_o)
if (rst_in_o)
clk6_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk6_dly_cnt < clkout6_dly)
clk6_dly_cnt <= clk6_dly_cnt + 1;
end
always @(negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o)
clkfbm1_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clkfbm1_dly_cnt < clkfbm1_dly)
clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
end
always @(posedge clk0in or negedge clk0in or posedge rst_in_o)
if (rst_in_o) begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
else if (clk0ps_en && clk0_frac_en == 0) begin
if (clk0_cnt < clk0_div1)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 8'b0;
if (clk0_cnt < clk0_ht1)
clk0_nf_out <= 1;
else
clk0_nf_out <= 0;
end
else begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
assign clk0_out = (clk0_frac_en) ? clk0_frac_out : clk0_nf_out;
always @(posedge clk1in or negedge clk1in or posedge rst_in_o)
if (rst_in_o) begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
else if (clk1ps_en) begin
if (clk1_cnt < clk1_div1)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 8'b0;
if (clk1_cnt < clk1_ht1)
clk1_out <= 1;
else
clk1_out <= 0;
end
else begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
always @(posedge clk2in or negedge clk2in or posedge rst_in_o)
if (rst_in_o) begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
else if (clk2ps_en) begin
if (clk2_cnt < clk2_div1)
clk2_cnt <= clk2_cnt + 1;
else
clk2_cnt <= 8'b0;
if (clk2_cnt < clk2_ht1)
clk2_out <= 1;
else
clk2_out <= 0;
end
else begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
always @(posedge clk3in or negedge clk3in or posedge rst_in_o)
if (rst_in_o) begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
else if (clk3ps_en) begin
if (clk3_cnt < clk3_div1)
clk3_cnt <= clk3_cnt + 1;
else
clk3_cnt <= 8'b0;
if (clk3_cnt < clk3_ht1)
clk3_out <= 1;
else
clk3_out <= 0;
end
else begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
always @(posedge clk4in or negedge clk4in or posedge rst_in_o)
if (rst_in_o) begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
else if (clk4ps_en) begin
if (clk4_cnt < clk4_div1)
clk4_cnt <= clk4_cnt + 1;
else
clk4_cnt <= 8'b0;
if (clk4_cnt < clk4_ht1)
clk4_out <= 1;
else
clk4_out <= 0;
end
else begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
always @(posedge clk5in or negedge clk5in or posedge rst_in_o)
if (rst_in_o) begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
// else if (clk5ps_en && clk0_frac_en == 0) begin
else if (clk5ps_en ) begin
if (clk5_cnt < clk5_div1)
clk5_cnt <= clk5_cnt + 1;
else
clk5_cnt <= 8'b0;
if (clk5_cnt < clk5_ht1)
clk5_out <= 1;
else
clk5_out <= 0;
end
else begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
always @(posedge clk6in or negedge clk6in or posedge rst_in_o)
if (rst_in_o) begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
else if (clk6ps_en ) begin
if (clk6_cnt < clk6_div1)
clk6_cnt <= clk6_cnt + 1;
else
clk6_cnt <= 8'b0;
if (clk6_cnt < clk6_ht1)
clk6_out <= 1;
else
clk6_out <= 0;
end
else begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o) begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
else if (clkfbm1ps_en && clkfb_frac_en == 0) begin
if (clkfbm1_cnt < clkfbm1_div1)
clkfbm1_cnt <= clkfbm1_cnt + 1;
else
clkfbm1_cnt <= 8'b0;
if (clkfbm1_cnt < clkfbm1_ht1)
clkfbm1_nf_out <= 1;
else
clkfbm1_nf_out <= 0;
end
else begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
assign clkfbm1_out = (clkfb_frac_en) ? clkfbm1_frac_out : clkfbm1_nf_out;
always @(posedge CLKFBIN_in or negedge CLKFBIN_in or posedge rst_int)
if (rst_int) begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
else if (clkout_en) begin
if (clkfbm2_cnt < clkfbm2_div1)
clkfbm2_cnt <= clkfbm2_cnt + 1;
else
clkfbm2_cnt <= 8'b0;
if (clkfbm2_cnt < clkfbm2_ht1)
clkfbm2_out <= 1;
else
clkfbm2_out <= 0;
end
else begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
always @(posedge clkpll_r or negedge clkpll_r or posedge rst_int)
if (rst_int) begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
else if (clkout_en) begin
if (clkind_cnt < clkind_div1)
clkind_cnt <= clkind_cnt + 1;
else
clkind_cnt <= 8'b0;
if (clkind_cnt < clkind_ht1)
clkind_out <= 1;
else
clkind_out <= 0;
end
else begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
always @(clk0_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout0_out = clk0_out;
else
clkout0_out = clkfb_tst;
always @(clk1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout1_out = clk1_out;
else
clkout1_out = clkfb_tst;
always @(clk2_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout2_out = clk2_out;
else
clkout2_out = clkfb_tst;
always @(clk3_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout3_out = clk3_out;
else
clkout3_out = clkfb_tst;
always @(clk4_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout4_out = clk4_out;
else
clkout4_out = clkfb_tst;
always @(clk5_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout5_out = clk5_out;
else
clkout5_out = clkfb_tst;
always @(clk6_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout6_out = clk6_out;
else
clkout6_out = clkfb_tst;
always @(clkfbm1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkfb_out = clkfbm1_out;
else
clkfb_out = clkfb_tst;
//
// determine feedback delay
//
always @(posedge clkpll_r )
if (fb_delay_found_tmp == 0 && pwron_int == 0 && rst_int == 0) begin
clkfb_tst <= 1'b1;
end
else
clkfb_tst <= 1'b0;
always @( posedge clkfb_tst or posedge rst_int )
if (rst_int)
delay_edge <= 0;
else
delay_edge <= $time;
always @(posedge CLKFBIN_in or posedge rst_int )
if (rst_int) begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
else
if (fb_delay_found_tmp ==0 ) begin
if ( delay_edge != 0)
fb_delay <= ($time - delay_edge);
else
fb_delay <= 0;
fb_delay_found_tmp <= 1;
end
always @(rst_int)
if (rst_int)
assign fb_delay_found = 0;
else
deassign fb_delay_found;
always @(fb_delay_found_tmp or clkvco_delay )
if (clkvco_delay == 0)
fb_delay_found <= #1000 fb_delay_found_tmp;
else
fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp;
always @(fb_delay)
if (rst_int==0 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning : The feedback delay on %s instance %m at time %t is %f ns. It is over the maximum value %f ns.", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max);
end
//
// generate unlock signal
//
always begin
if (rst_int)
clk_osc = 0;
else
clk_osc = ~clk_osc;
#OSC_P2;
end
always @(posedge clkpll_r or negedge clkpll_r) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge CLKFBIN_in or negedge CLKFBIN_in) begin
clkfb_p <= 1;
clkfb_p <= #100 0;
end
always @(posedge clk_osc or posedge rst_int or posedge clkin_p)
if (rst_int == 1) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out == 1) begin
@(posedge clkpll_r) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out <= 0;
end
else
clkinstopped_out <= 1;
end
always @(posedge clk_osc or posedge rst_int or posedge clkfb_p)
if (rst_int == 1 || clkfb_p == 1) begin
clkfbstopped_out <= 0;
clkfb_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfb_lost_cnt < clkfb_lost_val) begin
clkfb_lost_cnt <= clkfb_lost_cnt + 1;
clkfbstopped_out <= 0;
end
else
clkfbstopped_out <= 1;
end
always @(clkin_jit or rst_int )
if (rst_int)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2 && clkfbstopped_out == 0 && clkinstopped_out == 0) begin
if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// tasks
task clkout_dly_real_cal;
output [5:0] clkout_dly;
output [2:0] clkpm_sel;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
real clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clk_rl_tmp_1000;
real clk_rl_tmp;
integer clkout_dly_tmp;
integer clkpm_sel_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
clk_rl_tmp_1000 = clk_dly_rl * 1000.0;
clk_rl_tmp = clk_rl_tmp_1000 / 1000.0;
clkout_dly_tmp = $rtoi(clk_dly_rl);
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of %s", clk_ps_name, MODULE_NAME, clk_ps, MODULE_NAME);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
clk_dly_rem = clk_rl_tmp - clkout_dly;
if (clk_dly_rem < 0.125)
clkpm_sel_tmp = 0;
else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25)
clkpm_sel_tmp = 1;
else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375)
clkpm_sel_tmp = 2;
else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5)
clkpm_sel_tmp = 3;
else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625)
clkpm_sel_tmp = 4;
else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75)
clkpm_sel_tmp = 5;
else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875)
clkpm_sel_tmp = 6;
else if (clk_dly_rem >= 0.875)
clkpm_sel_tmp = 7;
else if (clk_dly_rem == 1.000) // only for rounding issues
clkpm_sel_tmp = 8;
if(clkpm_sel_tmp == 8)
clkpm_sel = 0;
else
clkpm_sel = clkpm_sel_tmp;
if (clk_ps < 0.0)
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel_tmp)* 360.0 / clkdiv - 360.0;
else
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel_tmp) * 360.0 / clkdiv;
if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, MODULE_NAME, clk_ps, clk_ps_rl);
end
endtask
task clkout_dly_cal;
output [5:0] clkout_dly;
output [2:0] clkpm_sel;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
integer clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clk_rl_tmp_1000;
real clk_rl_tmp;
integer clkout_dly_tmp;
integer clkpm_sel_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
clk_rl_tmp_1000 = clk_dly_rl * 1000.0;
clk_rl_tmp = clk_rl_tmp_1000 / 1000.0;
clkout_dly_tmp = $rtoi(clk_dly_rl);
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of %s", clk_ps_name, MODULE_NAME, clk_ps, MODULE_NAME);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
clk_dly_rem = clk_rl_tmp - clkout_dly;
if (clk_dly_rem < 0.125)
clkpm_sel_tmp = 0;
else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25)
clkpm_sel_tmp = 1;
else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375)
clkpm_sel_tmp = 2;
else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5)
clkpm_sel_tmp = 3;
else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625)
clkpm_sel_tmp = 4;
else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75)
clkpm_sel_tmp = 5;
else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875)
clkpm_sel_tmp = 6;
else if (clk_dly_rem >= 0.875 && clk_dly_rem < 1.000)
clkpm_sel_tmp = 7;
else if (clk_dly_rem == 1.000) //only for rounding issues
clkpm_sel_tmp = 8;
if(clkpm_sel_tmp == 8)
clkpm_sel = 0;
else
clkpm_sel = clkpm_sel_tmp;
if (clk_ps < 0.0)
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel_tmp)* 360.0 / clkdiv - 360.0;
else
clk_ps_rl = (clkout_dly + (0.125 * clkpm_sel_tmp)) * 360.0 / clkdiv;
if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, MODULE_NAME, clk_ps, clk_ps_rl);
end
endtask
task clk_out_para_cal;
output [6:0] clk_ht;
output [6:0] clk_lt;
output clk_nocnt;
output clk_edge;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
integer CLKOUT_DIVIDE;
real CLKOUT_DUTY_CYCLE;
real tmp_value, tmp_value0, tmp_value_rm;
integer tmp_value_round, tmp_value1, tmp_value_r;
real tmp_value2;
real tmp_value_rm1, tmp_value_r1;
integer tmp_value_r2;
begin
tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE;
tmp_value_r = $rtoi(tmp_value0);
tmp_value_rm = tmp_value0 - tmp_value_r;
if (tmp_value_rm < 0.1)
tmp_value = tmp_value_r * 1.0;
else if (tmp_value_rm > 0.9)
tmp_value = 1.0 * tmp_value_r + 1.0;
else begin
tmp_value_r1 = tmp_value0 * 2.0;
tmp_value_r2 = $rtoi(tmp_value_r1);
tmp_value_rm1 = tmp_value_r1 - tmp_value_r2;
if (tmp_value_rm1 > 0.995)
tmp_value = tmp_value0 + 0.002;
else
tmp_value = tmp_value0;
end
tmp_value_round = tmp_value * 2.0;
tmp_value1 = tmp_value_round % 2;
tmp_value2 = CLKOUT_DIVIDE - tmp_value;
if ((tmp_value2) >= O_MAX_HT_LT) begin
clk_lt = 7'b1000000;
end
else begin
if (tmp_value2 < 1.0)
clk_lt = 1;
else
if ( tmp_value1 != 0)
clk_lt = $rtoi(tmp_value2) + 1;
else
clk_lt = $rtoi(tmp_value2);
end
if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT)
clk_ht = 7'b1000000;
else
clk_ht = CLKOUT_DIVIDE - clk_lt;
clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0;
if ( tmp_value < 1.0)
clk_edge = 1;
else if (tmp_value1 != 0)
clk_edge = 1;
else
clk_edge = 0;
end
endtask
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.0;
CLK_DUTY_CYCLE_MIN_rnd = 0.0;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
end
CLK_DUTY_CYCLE_MAX = 1.0;
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
end
clkout_duty_chk = 1'b1;
end
endfunction
function para_int_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
integer para_in;
integer range_low;
integer range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on %s instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, MODULE_NAME, para_in, range_low, range_high);
$finish;
end
para_int_range_chk = 1'b1;
end
endfunction
function para_real_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
real para_in;
real range_low;
real range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on %s instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, MODULE_NAME, para_in, range_low, range_high);
$finish;
end
para_real_range_chk = 1'b0;
end
endfunction
task clkout_pm_cal;
output [7:0] clk_ht1;
output [7:0] clk_div;
output [7:0] clk_div1;
input [6:0] clk_ht;
input [6:0] clk_lt;
input clk_nocnt;
input clk_edge;
begin
if (clk_nocnt ==1) begin
clk_div = 8'b00000001;
clk_div1 = 8'b00000001;
clk_ht1 = 8'b00000001;
end
else begin
if ( clk_edge == 1)
clk_ht1 = 2 * clk_ht + 1;
else
clk_ht1 = 2 * clk_ht;
clk_div = clk_ht + clk_lt ;
clk_div1 = 2 * clk_div -1;
end
end
endtask
task clkout_delay_para_drp;
output [5:0] clkout_dly;
output clk_nocnt;
output clk_edge;
input [15:0] di_in;
input [6:0] daddr_in;
begin
clkout_dly = di_in[5:0];
clk_nocnt = di_in[6];
clk_edge = di_in[7];
end
endtask
task clkout_hl_para_drp;
output [6:0] clk_lt;
output [6:0] clk_ht;
output [2:0] clkpm_sel;
input [15:0] di_in_tmp;
input [6:0] daddr_in_tmp;
begin
if (di_in_tmp[12] != 1) begin
$display(" Error : %s on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", MODULE_NAME, di_in_tmp, daddr_in_tmp, $time);
end
if ( di_in_tmp[5:0] == 6'b0)
clk_lt = 7'b1000000;
else
clk_lt = { 1'b0, di_in_tmp[5:0]};
if (di_in_tmp[11:6] == 6'b0)
clk_ht = 7'b1000000;
else
clk_ht = { 1'b0, di_in_tmp[11:6]};
clkpm_sel = di_in_tmp[15:13];
end
endtask
specify
(CLKIN1 => CLKFBOUT) = (0:0:0, 0:0:0);
(CLKIN1 => CLKFBOUTB) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT0) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT0B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT1) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT1B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT2) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT2B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT3) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT3B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT4) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT5) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT6) = (0:0:0, 0:0:0);
(CLKIN2 => CLKFBOUT) = (0:0:0, 0:0:0);
(CLKIN2 => CLKFBOUTB) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT0) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT0B) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT1) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT1B) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT2) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT2B) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT3) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT3B) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT4) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT5) = (0:0:0, 0:0:0);
(CLKIN2 => CLKOUT6) = (0:0:0, 0:0:0);
(DCLK *> DO) = (0:0:0, 0:0:0);
(DCLK => DRDY) = (0:0:0, 0:0:0);
(PSCLK => PSDONE) = (0:0:0, 0:0:0);
(RST => CLKFBSTOPPED) = (0:0:0, 0:0:0);
(RST => CLKINSTOPPED) = (0:0:0, 0:0:0);
(RST => LOCKED) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKIN2, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (negedge PSCLK, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKIN2, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge PSCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge CLKIN2, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge PSCLK, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge CLKIN2, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge PSCLK, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MMCME3_BASE.v 0000664 0000000 0000000 00000020242 12327044266 0023135 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : MMCME3_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME3_BASE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input PWRDWN,
input RST
);
tri0 glblGSR = glbl.GSR;
localparam MODULE_NAME = "MMCME3_BASE";
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
wire IS_CLKFBIN_INVERTED_BIN;
wire IS_CLKIN1_INVERTED_BIN;
wire IS_PWRDWN_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire CLKFBIN_in;
wire CLKIN1_in;
wire PWRDWN_in;
wire RST_in;
assign CLKFBIN_in = CLKFBIN ^ IS_CLKFBIN_INVERTED_BIN;
assign CLKIN1_in = CLKIN1 ^ IS_CLKIN1_INVERTED_BIN;
assign PWRDWN_in = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign RST_in = RST ^ IS_RST_INVERTED_BIN;
assign IS_CLKFBIN_INVERTED_BIN = IS_CLKFBIN_INVERTED_REG;
assign IS_CLKIN1_INVERTED_BIN = IS_CLKIN1_INVERTED_REG;
assign IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
wire OPEN_CDDCDONE;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
MMCME3_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.REF_JITTER1(REF_JITTER1)
)
mmcm_adv_1 (
.CDDCDONE (OPEN_CDDCDONE),
.CDDCREQ (1'b0),
.CLKFBIN (CLKFBIN_in),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKIN1 (CLKIN1_in),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.CLKFBSTOPPED(OPEN_FBS),
.CLKINSTOPPED(OPEN_INS),
.PSDONE(OPEN_PSDONE),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN_in),
.RST (RST_in)
);
specify
(CLKIN1 => CLKFBOUT) = (0:0:0, 0:0:0);
(CLKIN1 => CLKFBOUTB) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT0) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT0B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT1) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT1B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT2) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT2B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT3) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT3B) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT4) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT5) = (0:0:0, 0:0:0);
(CLKIN1 => CLKOUT6) = (0:0:0, 0:0:0);
(RST => LOCKED) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MUXCY.v 0000664 0000000 0000000 00000003307 12327044266 0022332 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Multiplexer for Carry Logic with General Output
// /___/ /\ Filename : MUXCY.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXCY (O, CI, DI, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input CI, DI, S;
reg O_out;
always @(CI or DI or S)
if (S)
O_out = CI;
else
O_out = DI;
assign O = O_out;
`ifdef XIL_TIMING
specify
(CI => O) = (0:0:0, 0:0:0);
(DI => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MUXF7.v 0000664 0000000 0000000 00000003310 12327044266 0022265 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF7.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF7.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF7 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MUXF8.v 0000664 0000000 0000000 00000003330 12327044266 0022270 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF8.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF8.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF8 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/MUXF9.v 0000664 0000000 0000000 00000002310 12327044266 0022266 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description :
// / /
// /__/ /\ Filename : MUXF9.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/unified/chen/g2ltw/g2ltw.pl
// Revision: 1.0
// 09/26/12 - 680234 - ncsim compile error
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MUXF9
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I0,
input I1,
input S
);
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUF.v 0000664 0000000 0000000 00000003176 12327044266 0022164 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Output Buffer
// /___/ /\ Filename : OBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module OBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
input I;
tri0 GTS = glbl.GTS;
bufif0 B1 (O, I, GTS);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFDS.v 0000664 0000000 0000000 00000003652 12327044266 0022412 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/OBUFDS.v,v 1.6 2005/07/21 23:37:03 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFDS.v
// \ \ / \ Timestamp : Tue Mar 1 14:57:54 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/01/05 - Added global GTS.
// 03/01/05 - Added LOC parameter.
// 05/23/05 - Declared tri0 GTS.
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module OBUFDS (O, OB, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O, OB;
input I;
tri0 GTS = glbl.GTS;
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
bufif0 (O, I, GTS);
notif0 (OB, I, GTS);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFDS_GTE3.v 0000664 0000000 0000000 00000005700 12327044266 0023170 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFDS_GTE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 12/11/2012 - Initial version
// 03/22/2013 - Model added
// 03/25/2013 - Sync 5 YML & model update
// 04/12/2013 - Add attribute section
// 08/28/2013 - Remove REFCLKOUT_CLKOUT_SEL, Add specify section
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE3";
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [4:0] REFCLK_ICNTL_TX_BIN;
tri0 GTS = glbl.GTS;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE3_dr.v"
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG;
always @ (trig_attr) begin
#1;
if ((REFCLK_EN_TX_PATH_REG < 1'b0) || (REFCLK_EN_TX_PATH_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute REFCLK_EN_TX_PATH on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, REFCLK_EN_TX_PATH_REG);
attr_err = 1'b1;
end
if ((REFCLK_ICNTL_TX_REG < 5'b00000) || (REFCLK_ICNTL_TX_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute REFCLK_ICNTL_TX on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
wire t1;
wire t2;
or O1 (t1, GTS, CEB);
or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1);
bufif0 B1 (O, I, t2);
notif0 N1 (OB, I, t2);
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFDS_GTE3_ADV.v 0000664 0000000 0000000 00000006237 12327044266 0023670 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFDS_GTE3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 08/28/2013 - Initial model
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTE3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input [3:0] I,
input [1:0] RXRECCLK_SEL
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE3_ADV";
reg I_delay;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [4:0] REFCLK_ICNTL_TX_BIN;
tri0 GTS = glbl.GTS;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE3_ADV_dr.v"
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG;
always @ (trig_attr) begin
#1;
if ((REFCLK_EN_TX_PATH_REG < 1'b0) || (REFCLK_EN_TX_PATH_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute REFCLK_EN_TX_PATH on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, REFCLK_EN_TX_PATH_REG);
attr_err = 1'b1;
end
if ((REFCLK_ICNTL_TX_REG < 5'b00000) || (REFCLK_ICNTL_TX_REG > 5'b11111)) begin
$display("Attribute Syntax Error : The attribute REFCLK_ICNTL_TX on %s instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
wire t1;
wire t2;
or O1 (t1, GTS, CEB);
or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1);
// =====================
// Generate I_delay
// =====================
always @(*) begin
case (RXRECCLK_SEL)
2'b00: I_delay <= I[0];
2'b01: I_delay <= I[1];
2'b10: I_delay <= I[2];
2'b11: I_delay <= I[3];
default : I_delay <= I[0];
endcase
end
bufif0 B1 (O, I_delay, t2);
notif0 N1 (OB, I_delay, t2);
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFT.v 0000664 0000000 0000000 00000003711 12327044266 0022303 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT.v,v 1.8.140.2 2009/03/24 23:20:17 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Output Buffer
// /___/ /\ Filename : OBUFT.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module OBUFT (O, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (O, I, ts);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFTDS.v 0000664 0000000 0000000 00000003704 12327044266 0022534 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS (O, OB, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O, OB;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFTDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFTDSE3.v 0000664 0000000 0000000 00000005657 12327044266 0022735 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFTDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDSE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter IOSTANDARD = "DEFAULT"
)(
output O,
output OB,
input I,
input T
);
// define constants
localparam MODULE_NAME = "OBUFTDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
// `ifndef XIL_DR
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
// `endif
wire IOSTANDARD_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFTDSE3_dr.v"
`endif
wire OB_out;
wire O_out;
wire OB_delay;
wire O_delay;
wire I_in;
wire T_in;
wire I_delay;
wire T_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) OB = OB_delay;
// inputs with no timing checks
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign OB_delay = OB_out;
assign O_delay = O_out;
assign I_in = I_delay;
assign T_in = T_delay;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 B1 (O_out, I_in, ts);
notif0 N1 (OB_out, I_in, ts);
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
always @ (trig_attr) begin
#1;
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFTDS_DCIEN.v 0000664 0000000 0000000 00000003412 12327044266 0023432 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 06/10/11 - CR 584500 - added attribute SLEW
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T);
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
output OB;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFTE3.v 0000664 0000000 0000000 00000006225 12327044266 0022476 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFTE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFTE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DRIVE = 12,
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input T
);
// define constants
localparam MODULE_NAME = "OBUFTE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
// `ifndef XIL_DR
localparam [4:0] DRIVE_REG = DRIVE;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
// `endif
wire [4:0] DRIVE_BIN;
wire IOSTANDARD_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "OBUFTE3_dr.v"
// `endif
wire O_out;
wire O_delay;
wire I_in;
wire T_in;
wire I_delay;
wire T_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign O_delay = O_out;
assign I_in = I_delay;
assign T_in = T_delay;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 T1 (O_out, I_in, ts);
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign DRIVE_BIN = DRIVE_REG;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
always @ (trig_attr) begin
#1;
if ((DRIVE_REG < 2) || (DRIVE_REG > 24)) begin
$display("Attribute Syntax Error : The attribute DRIVE on %s instance %m is set to %d. Legal values for this attribute are 2 to 24.", MODULE_NAME, DRIVE_REG);
attr_err = 1'b1;
end
if ((IOSTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute IOSTANDARD on %s instance %m is set to %s. Legal values for this attribute are DEFAULT.", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OBUFT_DCIEN.v 0000664 0000000 0000000 00000003024 12327044266 0023202 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Output Buffer
// /___/ /\ Filename : OBUFT_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFT_DCIEN (O, DCITERMDISABLE, I, T);
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (O, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ODDR.v 0000664 0000000 0000000 00000021435 12327044266 0022157 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Dual Data Rate Output D Flip-Flop
// /___/ /\ Filename : ODDR.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outputs.
// 05/29/07 - Added wire declaration for internal signals
// 04/17/08 - CR 468871 Negative SetupHold fix
// 05/12/08 - CR 455447 add XON MSGON property to support async reg
// 12/03/08 - CR 498674 added pulldown on R/S.
// 07/28/09 - CR 527698 According to holistic, CE has to be high for both rise/fall CLK
// - If CE is low on the rising edge, it has an effect of no change in the falling CLK.
// 06/23/10 - CR 566394 Removed extra recrem checks
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR 591320 fixed SU/H checks in OPPOSITE edge mode.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ODDR (Q, C, CE, D1, D2, R, S);
output Q;
input C;
input CE;
input D1;
input D2;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter MSGON = "TRUE";
parameter XON = "TRUE";
`endif
localparam MODULE_NAME = "ODDR";
pulldown P1 (R);
pulldown P2 (S);
reg q_out = INIT, qd2_posedge_int;
`ifdef XIL_TIMING
reg notifier;
wire notifierx;
`endif
tri0 GSR = glbl.GSR;
wire c_in,delay_c;
wire ce_in,delay_ce;
wire d1_in,delay_d1;
wire d2_in,delay_d2;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
assign gsr_in = GSR;
assign Q = q_out;
`ifdef XIL_TIMING
wire nr, ns, ngsr;
wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable;
wire ce_c_enable1, d1_c_enable1, d2_c_enable1, d2_c_enable2, r_c_enable1, s_c_enable1;
not (nr, R);
not (ns, S);
not (ngsr, GSR);
and (ce_c_enable, ngsr, nr, ns);
and (d_c_enable, ngsr, nr, ns, CE);
and (s_c_enable, ngsr, nr);
assign notifierx = (XON == "FALSE") ? 1'bx : notifier;
assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable;
assign d1_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable;
assign d2_c_enable1 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "OPPOSITE_EDGE")) ? 1'b0 : d_c_enable; // SAME_EDGE case, D2 to posedge C
assign d2_c_enable2 = ((MSGON =="FALSE") && (DDR_CLK_EDGE == "SAME_EDGE")) ? 1'b0 : d_c_enable; // OPPOSITE_EDGE case, D2 to negedge C
assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr;
assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable;
`endif
initial begin
if ((INIT != 0) && (INIT != 1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT);
$finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE);
$finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q_out = INIT;
assign qd2_posedge_int = INIT;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b0;
assign qd2_posedge_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b1;
assign qd2_posedge_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q_out;
deassign qd2_posedge_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q_out;
deassign qd2_posedge_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q_out <= 1'b0;
qd2_posedge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q_out <= 1'b1;
qd2_posedge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q_out <= d1_in;
qd2_posedge_int <= d2_in;
end
// CR 527698
else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin
qd2_posedge_int <= q_out;
end
end // always @ (posedge c_in)
always @(negedge c_in) begin
if (r_in == 1'b1)
q_out <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q_out <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
if (DDR_CLK_EDGE == "SAME_EDGE")
q_out <= qd2_posedge_int;
else if (DDR_CLK_EDGE == "OPPOSITE_EDGE")
q_out <= d2_in;
end
end // always @ (negedge c_in)
`ifndef XIL_TIMING
assign delay_c = C;
assign delay_ce = CE;
assign delay_d1 = D1;
assign delay_d2 = D2;
assign delay_r = R;
assign delay_s = S;
`endif
assign c_in = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign d1_in = IS_D1_INVERTED ^ delay_d1;
assign d2_in = IS_D2_INVERTED ^ delay_d2;
assign r_in = delay_r;
assign s_in = delay_s;
//*** Timing Checks Start here
`ifdef XIL_TIMING
always @(notifierx) begin
q_out <= 1'bx;
end
`endif
specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(R => Q) = (0:0:0, 0:0:0);
(S => Q) = (0:0:0, 0:0:0);
$setuphold (posedge C, posedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, negedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, posedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, negedge CE &&& (ce_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, posedge D1 &&& (d1_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (posedge C, negedge D1 &&& (d1_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (posedge C, posedge D2 &&& (d2_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (posedge C, negedge D2 &&& (d2_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (negedge C, posedge D2 &&& (d2_c_enable2!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (negedge C, negedge D2 &&& (d2_c_enable2!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d2);
$setuphold (posedge C, posedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (posedge C, negedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (negedge C, posedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (negedge C, negedge R &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_r);
$setuphold (posedge C, posedge S &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (posedge C, negedge S &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (negedge C, posedge S &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (negedge C, negedge S &&& (r_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_s);
$setuphold (negedge C, posedge D1 &&& (d1_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$setuphold (negedge C, negedge D1 &&& (d1_c_enable1!=0), 0:0:0, 0:0:0, notifier, , , delay_c, delay_d1);
$recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier);
$recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier);
$recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier);
$recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$period (negedge C, 0:0:0, notifier);
$width (posedge C, 0:0:0, 0, notifier);
$width (negedge C, 0:0:0, 0, notifier);
$width (posedge R, 0:0:0, 0, notifier);
$width (posedge S, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ODDRE1.v 0000664 0000000 0000000 00000012140 12327044266 0022336 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : ODDRE1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ODDRE1 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D1_INVERTED = 1'b0,
parameter [0:0] IS_D2_INVERTED = 1'b0,
parameter [0:0] SRVAL = 1'b0
)(
output Q,
input C,
input D1,
input D2,
input SR
);
// define constants
localparam MODULE_NAME = "ODDRE1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
localparam [0:0] IS_D1_INVERTED_REG = IS_D1_INVERTED;
localparam [0:0] IS_D2_INVERTED_REG = IS_D2_INVERTED;
localparam [0:0] SRVAL_REG = SRVAL;
`endif
wire IS_C_INVERTED_BIN;
wire IS_D1_INVERTED_BIN;
wire IS_D2_INVERTED_BIN;
wire SRVAL_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "ODDRE1_dr.v"
`endif
reg Q_out,QD2_posedge_int;
reg R_sync1 = 1'b0;
reg R_sync2 = 1'b0;
reg R_sync3 = 1'b0;
wire Q_delay;
wire C_in;
wire D1_in;
wire D2_in;
wire SR_in;
wire C_delay;
wire D1_delay;
wire D2_delay;
wire SR_delay;
assign #(out_delay) Q = Q_delay;
// inputs with no timing checks
assign #(inclk_delay) C_delay = C;
assign #(in_delay) D1_delay = D1;
assign #(in_delay) D2_delay = D2;
assign #(in_delay) SR_delay = SR;
assign Q_delay = Q_out;
assign C_in = C_delay ^ IS_C_INVERTED_BIN;
assign D1_in = D1_delay ^ IS_D1_INVERTED_BIN;
assign D2_in = D2_delay ^ IS_D2_INVERTED_BIN;
assign SR_in = SR_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_C_INVERTED_BIN = IS_C_INVERTED_REG;
assign IS_D1_INVERTED_BIN = IS_D1_INVERTED_REG;
assign IS_D2_INVERTED_BIN = IS_D2_INVERTED_REG;
assign SRVAL_BIN = SRVAL_REG;
always @ (trig_attr) begin
#1;
if ((IS_C_INVERTED_REG < 1'b0) || (IS_C_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_C_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_C_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_D1_INVERTED_REG < 1'b0) || (IS_D1_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_D1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_D1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_D2_INVERTED_REG < 1'b0) || (IS_D2_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_D2_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_D2_INVERTED_REG);
attr_err = 1'b1;
end
if ((SRVAL_REG < 1'b0) || (SRVAL_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute SRVAL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, SRVAL_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(posedge C_in) begin
R_sync1 <= SR_in;
R_sync2 <= R_sync1;
R_sync3 <= R_sync2;
end
always @ (glblGSR or SR_in or R_sync1 or R_sync2 or R_sync3) begin
if (glblGSR == 1'b1) begin
assign Q_out = SRVAL_REG;
assign QD2_posedge_int = SRVAL_REG;
end
else if (glblGSR == 1'b0) begin
if (SR_in == 1'b1 || R_sync1 == 1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1 ) begin
assign Q_out = SRVAL_REG;
assign QD2_posedge_int = SRVAL_REG;
end
else if (R_sync3 == 1'b0) begin
deassign Q_out;
deassign QD2_posedge_int;
end
end
end
always @(posedge C_in) begin
if (SR_in == 1'b1 || R_sync1 ==1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1) begin
Q_out <= SRVAL_REG;
QD2_posedge_int <= SRVAL_REG;
end
else if (R_sync3 == 1'b0) begin
Q_out <= D1_in;
QD2_posedge_int <= D2_in;
end
end
always @(negedge C_in) begin
if (SR_in == 1'b1 || R_sync1 == 1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1)
Q_out <= SRVAL_REG;
else if (R_sync3 == 1'b0) begin
Q_out <= QD2_posedge_int;
end
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ODELAYE2.v 0000664 0000000 0000000 00000054547 12327044266 0022605 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Onput Fixed or Variable Delay Element.
// /___/ /\ Filename : ODELAYE2.v
// \ \ / \ Timestamp : Mon Sep 21 08:48:13 PDT 2009
// \___\/\___\
//
// Revision:
// 09/21/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ODELAYE2 (CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN, REGRST);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
parameter ODELAY_TYPE = "FIXED";
parameter integer ODELAY_VALUE = 0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (ODELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT;
output DATAOUT;
input C;
input CE;
input CINVCTRL;
input CLKIN;
input [4:0] CNTVALUEIN;
input INC;
input LD;
input LDPIPEEN;
input ODATAIN;
input REGRST;
tri0 GSR = glbl.GSR;
real CALC_TAPDELAY ;
real INIT_DELAY;
//------------------- constants ------------------------------------
localparam MAX_DELAY_COUNT = 31;
localparam MIN_DELAY_COUNT = 0;
localparam MAX_REFCLK_FREQUENCYL = 210.0;
localparam MIN_REFCLK_FREQUENCYL = 190.0;
localparam MAX_REFCLK_FREQUENCYH = 310.0;
localparam MIN_REFCLK_FREQUENCYH = 290.0;
//------------------- variable declaration -------------------------
integer odelay_count;
integer CNTVALUEIN_INTEGER;
reg [4:0] cntvalueout_pre;
reg notifier;
reg data_mux = 0;
reg tap_out = 0;
reg DATAOUT_reg = 0;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31;
reg c_in;
wire c_in_pre,delay_C;
wire ce_in,delay_CE;
wire cinvctrl_in,delay_CINVCTRL;
wire clkin_in,delay_CLKIN;
wire [4:0] cntvaluein_in,delay_CNTVALUEIN;
wire odatain_in,delay_ODATAIN;
wire gsr_in;
wire inc_in,delay_INC;
wire ld_in,delay_LD;
wire ldpipeen_in,delay_LDPIPEEN;
wire regrst_in,delay_REGRST;
reg [4:0] qcntvalueout_reg = 5'b0;
reg [4:0] qcntvalueout_mux = 5'b0;
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
// CR 587496
// assign #INIT_DELAY DATAOUT = tap_out;
always @(tap_out)
DATAOUT_reg <= #INIT_DELAY tap_out;
assign DATAOUT = DATAOUT_reg;
assign CNTVALUEOUT = cntvalueout_pre;
`ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign delay_C = C;
assign delay_CE = CE;
assign delay_CNTVALUEIN = CNTVALUEIN;
assign delay_INC = INC;
assign delay_LD = LD;
assign delay_LDPIPEEN = LDPIPEEN;
assign delay_REGRST = REGRST;
`endif // ifndef XIL_TIMING
assign delay_CINVCTRL = CINVCTRL;
assign delay_CLKIN = CLKIN;
assign delay_ODATAIN = ODATAIN;
assign gsr_in = GSR;
assign c_in_pre = IS_C_INVERTED ^ delay_C;
assign ce_in = delay_CE;
assign cntvaluein_in = delay_CNTVALUEIN;
assign inc_in = delay_INC;
assign ld_in = delay_LD;
assign ldpipeen_in = delay_LDPIPEEN;
assign regrst_in = delay_REGRST;
assign cinvctrl_in = delay_CINVCTRL;
assign clkin_in = delay_CLKIN;
assign odatain_in = IS_ODATAIN_INVERTED ^ delay_ODATAIN;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
// For simprims, the fixed Delay values are taken from the sdf.
// if (ODELAY_TYPE == "FIXED")
// assign odelay_count = 0;
// else
// assign odelay_count = ODELAY_VALUE;
case (ODELAY_TYPE)
"VAR_LOAD", "VAR_LOAD_PIPE": assign odelay_count = 0;
"FIXED", "VARIABLE" : assign odelay_count = ODELAY_VALUE;
endcase
end
else if (gsr_in == 1'b0) begin
deassign odelay_count;
end
end
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- CINVCTRL_SEL check
case (CINVCTRL_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CINVCTRL_SEL on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL);
$finish;
end
endcase
//-------- DELAY_SRC check
if (DELAY_SRC != "ODATAIN" && DELAY_SRC != "CLKIN") begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2 instance %m is set to %s. Legal values for this attribute are ODATAIN or CLKIN", DELAY_SRC);
$finish;
end
//-------- HIGH_PERFORMANCE_MODE check
case (HIGH_PERFORMANCE_MODE)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE);
$finish;
end
endcase
//-------- ODELAY_TYPE check
if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOAD" && ODELAY_TYPE != "VAR_LOAD_PIPE") begin
$display("Attribute Syntax Error : The attribute ODELAY_TYPE on ODELAYE2 instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", ODELAY_TYPE);
$finish;
end
//-------- ODELAY_VALUE check
if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin
$display("Attribute Syntax Error : The attribute ODELAY_VALUE on ODELAYE2 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE);
$finish;
end
//-------- PIPE_SEL check
case (PIPE_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute PIPE_SEL on ODELAYE2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL);
$finish;
end
endcase
//-------- REFCLK_FREQUENCY check
if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on ODELAYE2 instance %m is set to %f. Legal values for this attribute are either between 190.0 and 210.0, or between 290.0 and 310.0", REFCLK_FREQUENCY);
$finish;
end
//-------- SIGNAL_PATTERN check
case (SIGNAL_PATTERN)
"CLOCK", "DATA" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on ODELAYE2 instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN);
$finish;
end
endcase
//-------- CALC_TAPDELAY check
INIT_DELAY = 600;
end // initial begin
// CALC_TAPDELAY value
initial begin
if ((REFCLK_FREQUENCY <= MAX_REFCLK_FREQUENCYH) && (REFCLK_FREQUENCY >= MIN_REFCLK_FREQUENCYH))
begin
CALC_TAPDELAY = 52;
end
else
begin
CALC_TAPDELAY = 78;
end
end
//----------------------------------------------------------------------
//------------------------ Dynamic clock inversion ---------------------
//----------------------------------------------------------------------
// always @(c_in_pre or cinvctrl_in) begin
// case (CINVCTRL_SEL)
// "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
// "FALSE" : c_in = c_in_pre;
// endcase
// end
generate
case (CINVCTRL_SEL)
"TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
"FALSE" : always @(c_in_pre) c_in = c_in_pre;
endcase
endgenerate
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(odelay_count) begin
// Fixed CNTVALUEOUT for when in FIXED mode because of simprim.
if(ODELAY_TYPE != "FIXED")
assign cntvalueout_pre = odelay_count;
else
assign cntvalueout_pre = ODELAY_VALUE;
end
//----------------------------------------------------------------------
//-------------------------- CNTVALUEIN LOAD --------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (regrst_in == 1'b1)
qcntvalueout_reg = 5'b0;
else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin
qcntvalueout_reg = CNTVALUEIN_INTEGER;
end
end // always @(posedge c_in)
generate
case (PIPE_SEL)
"TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg;
"FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER;
endcase
endgenerate
//----------------------------------------------------------------------
//-------------------------- ODELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOAD" | ODELAY_TYPE == "VAR_LOAD_PIPE") begin
if (ld_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE" : odelay_count = ODELAY_VALUE;
"VAR_LOAD", "VAR_LOAD_PIPE" : odelay_count = qcntvalueout_mux;
endcase
end
else if (ld_in == 1'b0 && ce_in == 1'b1) begin
if (inc_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count < MAX_DELAY_COUNT)
odelay_count = odelay_count + 1;
else if (odelay_count == MAX_DELAY_COUNT)
odelay_count = MIN_DELAY_COUNT;
end
endcase
end
else if (inc_in == 1'b0) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count > MIN_DELAY_COUNT)
odelay_count = odelay_count - 1;
else if (odelay_count == MIN_DELAY_COUNT)
odelay_count = MAX_DELAY_COUNT;
end
endcase
end
end
end //
end // always @ (posedge c_in)
always @(cntvaluein_in or gsr_in) begin
case (cntvaluein_in)
5'b00000 : assign CNTVALUEIN_INTEGER = 0;
5'b00001 : assign CNTVALUEIN_INTEGER = 1;
5'b00010 : assign CNTVALUEIN_INTEGER = 2;
5'b00011 : assign CNTVALUEIN_INTEGER = 3;
5'b00100 : assign CNTVALUEIN_INTEGER = 4;
5'b00101 : assign CNTVALUEIN_INTEGER = 5;
5'b00110 : assign CNTVALUEIN_INTEGER = 6;
5'b00111 : assign CNTVALUEIN_INTEGER = 7;
5'b01000 : assign CNTVALUEIN_INTEGER = 8;
5'b01001 : assign CNTVALUEIN_INTEGER = 9;
5'b01010 : assign CNTVALUEIN_INTEGER = 10;
5'b01011 : assign CNTVALUEIN_INTEGER = 11;
5'b01100 : assign CNTVALUEIN_INTEGER = 12;
5'b01101 : assign CNTVALUEIN_INTEGER = 13;
5'b01110 : assign CNTVALUEIN_INTEGER = 14;
5'b01111 : assign CNTVALUEIN_INTEGER = 15;
5'b10000 : assign CNTVALUEIN_INTEGER = 16;
5'b10001 : assign CNTVALUEIN_INTEGER = 17;
5'b10010 : assign CNTVALUEIN_INTEGER = 18;
5'b10011 : assign CNTVALUEIN_INTEGER = 19;
5'b10100 : assign CNTVALUEIN_INTEGER = 20;
5'b10101 : assign CNTVALUEIN_INTEGER = 21;
5'b10110 : assign CNTVALUEIN_INTEGER = 22;
5'b10111 : assign CNTVALUEIN_INTEGER = 23;
5'b11000 : assign CNTVALUEIN_INTEGER = 24;
5'b11001 : assign CNTVALUEIN_INTEGER = 25;
5'b11010 : assign CNTVALUEIN_INTEGER = 26;
5'b11011 : assign CNTVALUEIN_INTEGER = 27;
5'b11100 : assign CNTVALUEIN_INTEGER = 28;
5'b11101 : assign CNTVALUEIN_INTEGER = 29;
5'b11110 : assign CNTVALUEIN_INTEGER = 30;
5'b11111 : assign CNTVALUEIN_INTEGER = 31;
endcase
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(clkin_in or odatain_in) begin
case (DELAY_SRC)
"ODATAIN" : begin
data_mux <= odatain_in;
end
"CLKIN" : begin
data_mux <= clkin_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2 instance %m is set to %s. Legal values for this attribute are CLKIN or ODATAIN", DELAY_SRC);
$finish;
end
endcase // case(DELAY_SRC)
end // always @(datain_in or idatain_in)
//*********************************************************
//*** DELAY IDATA signal
//*********************************************************
assign #(DELAY_D) delay_chain_0 = data_mux;
assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0;
assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1;
assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2;
assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3;
assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4;
assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5;
assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6;
assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7;
assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8;
assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9;
assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10;
assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11;
assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12;
assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13;
assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14;
assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15;
assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16;
assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17;
assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18;
assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19;
assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20;
assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21;
assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22;
assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23;
assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24;
assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25;
assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26;
assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27;
assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28;
assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29;
assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30;
//*********************************************************
//*** assign delay
//*********************************************************
always @(odelay_count) begin
case (odelay_count)
0: assign tap_out = delay_chain_0;
1: assign tap_out = delay_chain_1;
2: assign tap_out = delay_chain_2;
3: assign tap_out = delay_chain_3;
4: assign tap_out = delay_chain_4;
5: assign tap_out = delay_chain_5;
6: assign tap_out = delay_chain_6;
7: assign tap_out = delay_chain_7;
8: assign tap_out = delay_chain_8;
9: assign tap_out = delay_chain_9;
10: assign tap_out = delay_chain_10;
11: assign tap_out = delay_chain_11;
12: assign tap_out = delay_chain_12;
13: assign tap_out = delay_chain_13;
14: assign tap_out = delay_chain_14;
15: assign tap_out = delay_chain_15;
16: assign tap_out = delay_chain_16;
17: assign tap_out = delay_chain_17;
18: assign tap_out = delay_chain_18;
19: assign tap_out = delay_chain_19;
20: assign tap_out = delay_chain_20;
21: assign tap_out = delay_chain_21;
22: assign tap_out = delay_chain_22;
23: assign tap_out = delay_chain_23;
24: assign tap_out = delay_chain_24;
25: assign tap_out = delay_chain_25;
26: assign tap_out = delay_chain_26;
27: assign tap_out = delay_chain_27;
28: assign tap_out = delay_chain_28;
29: assign tap_out = delay_chain_29;
30: assign tap_out = delay_chain_30;
31: assign tap_out = delay_chain_31;
default:
assign tap_out = delay_chain_0;
endcase
end // always @ (odelay_count)
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier) begin
tap_out <= 1'bx;
end
`endif // ifdef XIL_TIMING
specify
( C *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( C => DATAOUT) = (100:100:100, 100:100:100);
( CINVCTRL *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( CINVCTRL => DATAOUT) = (100:100:100, 100:100:100);
( CLKIN => DATAOUT) = (100:100:100, 100:100:100);
( ODATAIN => DATAOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CE);
$setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_C, delay_INC);
$setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LD);
$setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_CNTVALUEIN);
$setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_C, delay_LDPIPEEN);
$setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
$setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_C, delay_REGRST);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODELAYE2
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ODELAYE2_FINEDELAY.v 0000664 0000000 0000000 00000060274 12327044266 0024157 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / Onput Fixed or Variable Delay Element with Fine Adjustment.
// /___/ /\ Filename : ODELAYE2_FINEDELAY.v
// \ \ / \ Timestamp : Tue Feb 15 15:52:17 PST 2011
// \___\/\___\
//
// Revision:
// 02/15/11 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ODELAYE2_FINEDELAY (
CNTVALUEOUT,
DATAOUT,
C,
CE,
CINVCTRL,
CLKIN,
CNTVALUEIN,
INC,
LD,
LDPIPEEN,
ODATAIN,
OFDLY,
REGRST
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
parameter FINEDELAY = "BYPASS";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
parameter ODELAY_TYPE = "FIXED";
parameter integer ODELAY_VALUE = 0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (ODELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT;
output DATAOUT;
input C;
input CE;
input CINVCTRL;
input CLKIN;
input [4:0] CNTVALUEIN;
input INC;
input LD;
input LDPIPEEN;
input ODATAIN;
input [2:0] OFDLY;
input REGRST;
tri0 GSR = glbl.GSR;
real CALC_TAPDELAY_RD ; // regular tap delay
real CALC_TAPDELAY_FD ; // fine tap delay
real INIT_DELAY_RD;
real INIT_DELAY_FD;
//------------------- constants ------------------------------------
localparam MAX_DELAY_COUNT = 31;
localparam MIN_DELAY_COUNT = 0;
localparam MAX_REFCLK_FREQUENCYL = 210.0;
localparam MIN_REFCLK_FREQUENCYL = 190.0;
localparam MAX_REFCLK_FREQUENCYH = 310.0;
localparam MIN_REFCLK_FREQUENCYH = 290.0;
//------------------- variable declaration -------------------------
integer odelay_count;
integer CNTVALUEIN_INTEGER;
reg [4:0] cntvalueout_pre;
reg notifier;
reg data_mux = 0;
reg tap_out_rd = 0;
reg tap_out_fd = 0;
reg tap_out_final = 0;
reg DATAOUT_reg = 0;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31;
wire fine_delay_0, fine_delay_1, fine_delay_2, fine_delay_3, fine_delay_4;
reg c_in;
wire c_in_pre,delay_c;
wire ce_in,delay_ce;
wire cinvctrl_in,delay_cinvctrl;
wire clkin_in,delay_clkin;
wire [4:0] cntvaluein_in,delay_cntvaluein;
wire odatain_in,delay_odatain;
wire ofdly_in,delay_ofdly;
wire gsr_in;
wire inc_in,delay_inc;
wire ld_in,delay_ld;
wire ldpipeen_in,delay_ldpipeen;
wire regrst_in,delay_regrst;
reg [4:0] qcntvalueout_reg = 5'b0;
reg [4:0] qcntvalueout_mux = 5'b0;
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
generate
case (FINEDELAY)
"BYPASS" : always @(tap_out_rd) tap_out_final = tap_out_rd;
"ADD_DLY" : always @(tap_out_fd) tap_out_final = tap_out_fd;
endcase
endgenerate
// CR 587496
// assign #INIT_DELAY DATAOUT = tap_out_final;
always @(tap_out_final)
DATAOUT_reg <= #INIT_DELAY_RD tap_out_final;
assign DATAOUT = DATAOUT_reg;
assign CNTVALUEOUT = cntvalueout_pre;
`ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign delay_c = C;
assign delay_ce = CE;
assign delay_cntvaluein = CNTVALUEIN;
assign delay_inc = INC;
assign delay_ld = LD;
assign delay_ldpipeen = LDPIPEEN;
assign delay_regrst = REGRST;
`endif // ifndef XIL_TIMING
assign delay_cinvctrl = CINVCTRL;
assign delay_clkin = CLKIN;
assign delay_odatain = ODATAIN;
assign delay_ofdly = OFDLY;
assign gsr_in = GSR;
assign c_in_pre = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign cntvaluein_in = delay_cntvaluein;
assign inc_in = delay_inc;
assign ld_in = delay_ld;
assign ldpipeen_in = delay_ldpipeen;
assign regrst_in = delay_regrst;
assign cinvctrl_in = delay_cinvctrl;
assign clkin_in = delay_clkin;
assign odatain_in = IS_ODATAIN_INVERTED ^ delay_odatain;
assign ofdly_in = delay_ofdly;
//*** GLOBAL hidden GSR pin
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
// For simprims, the fixed Delay values are taken from the sdf.
if (ODELAY_TYPE == "FIXED")
assign odelay_count = 0;
else
assign odelay_count = ODELAY_VALUE;
end
else if (gsr_in == 1'b0) begin
deassign odelay_count;
end
end
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- CINVCTRL_SEL check
case (CINVCTRL_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CINVCTRL_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CINVCTRL_SEL);
$finish;
end
endcase
//-------- DELAY_SRC check
if (DELAY_SRC != "ODATAIN" && DELAY_SRC != "CLKIN") begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are ODATAIN or CLKIN", DELAY_SRC);
$finish;
end
//-------- FINEDELAY check
if (FINEDELAY != "BYPASS" && FINEDELAY != "ADD_DLY") begin
$display("Attribute Syntax Error : The attribute FINEDELAY on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are BYPASS or ADD_DLY", FINEDELAY);
$finish;
end
//-------- HIGH_PERFORMANCE_MODE check
case (HIGH_PERFORMANCE_MODE)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE);
$finish;
end
endcase
//-------- ODELAY_TYPE check
if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOAD" && ODELAY_TYPE != "VAR_LOAD_PIPE") begin
$display("Attribute Syntax Error : The attribute ODELAY_TYPE on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOAD or VAR_LOAD_PIPE", ODELAY_TYPE);
$finish;
end
//-------- ODELAY_VALUE check
if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin
$display("Attribute Syntax Error : The attribute ODELAY_VALUE on ODELAYE2_FINEDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE);
$finish;
end
//-------- PIPE_SEL check
case (PIPE_SEL)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute PIPE_SEL on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PIPE_SEL);
$finish;
end
endcase
//-------- REFCLK_FREQUENCY check
if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on ODELAYE2_FINEDELAY instance %m is set to %f. Legal values for this attribute are 175.0 to 225.0", REFCLK_FREQUENCY);
$finish;
end
//-------- SIGNAL_PATTERN check
case (SIGNAL_PATTERN)
"CLOCK", "DATA" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN);
$finish;
end
endcase
//-------- CALC_TAPDELAY_RD check
INIT_DELAY_RD = 600; //regular delay
INIT_DELAY_FD = 40; //fine delay
end // initial begin
// CALC_TAPDELAY_RD value
initial begin
if ((REFCLK_FREQUENCY <= MAX_REFCLK_FREQUENCYH) && (REFCLK_FREQUENCY >= MIN_REFCLK_FREQUENCYH))
begin
CALC_TAPDELAY_RD = 52;
end
else
begin
CALC_TAPDELAY_RD = 78;
end
CALC_TAPDELAY_FD = 10; //fine delay
end
//----------------------------------------------------------------------
//------------------------ Dynamic clock inversion ---------------------
//----------------------------------------------------------------------
generate
case (CINVCTRL_SEL)
"TRUE" : always @(c_in_pre or cinvctrl_in) c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre);
"FALSE" : always @(c_in_pre) c_in = c_in_pre;
endcase
endgenerate
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(odelay_count) begin
// Fixed CNTVALUEOUT for when in FIXED mode because of simprim.
if(ODELAY_TYPE != "FIXED")
assign cntvalueout_pre = odelay_count;
else
assign cntvalueout_pre = ODELAY_VALUE;
end
//----------------------------------------------------------------------
//-------------------------- CNTVALUEIN LOAD --------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (regrst_in == 1'b1)
qcntvalueout_reg = 5'b0;
else if (regrst_in == 1'b0 && ldpipeen_in == 1'b1) begin
qcntvalueout_reg = CNTVALUEIN_INTEGER;
end
end // always @(posedge c_in)
generate
case (PIPE_SEL)
"TRUE" : always @(qcntvalueout_reg) qcntvalueout_mux <= qcntvalueout_reg;
"FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER;
endcase
endgenerate
//----------------------------------------------------------------------
//-------------------------- ODELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(posedge c_in) begin
if (ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOAD" | ODELAY_TYPE == "VAR_LOAD_PIPE") begin
if (ld_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE" : odelay_count = ODELAY_VALUE;
"VAR_LOAD", "VAR_LOAD_PIPE" : odelay_count = qcntvalueout_mux;
endcase
end
else if (ld_in == 1'b0 && ce_in == 1'b1) begin
if (inc_in == 1'b1) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count < MAX_DELAY_COUNT)
odelay_count = odelay_count + 1;
else if (odelay_count == MAX_DELAY_COUNT)
odelay_count = MIN_DELAY_COUNT;
end
endcase
end
else if (inc_in == 1'b0) begin
case (ODELAY_TYPE)
"VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" : begin
if (odelay_count > MIN_DELAY_COUNT)
odelay_count = odelay_count - 1;
else if (odelay_count == MIN_DELAY_COUNT)
odelay_count = MAX_DELAY_COUNT;
end
endcase
end
end
end //
end // always @ (posedge c_in)
always @(cntvaluein_in or gsr_in) begin
case (cntvaluein_in)
5'b00000 : assign CNTVALUEIN_INTEGER = 0;
5'b00001 : assign CNTVALUEIN_INTEGER = 1;
5'b00010 : assign CNTVALUEIN_INTEGER = 2;
5'b00011 : assign CNTVALUEIN_INTEGER = 3;
5'b00100 : assign CNTVALUEIN_INTEGER = 4;
5'b00101 : assign CNTVALUEIN_INTEGER = 5;
5'b00110 : assign CNTVALUEIN_INTEGER = 6;
5'b00111 : assign CNTVALUEIN_INTEGER = 7;
5'b01000 : assign CNTVALUEIN_INTEGER = 8;
5'b01001 : assign CNTVALUEIN_INTEGER = 9;
5'b01010 : assign CNTVALUEIN_INTEGER = 10;
5'b01011 : assign CNTVALUEIN_INTEGER = 11;
5'b01100 : assign CNTVALUEIN_INTEGER = 12;
5'b01101 : assign CNTVALUEIN_INTEGER = 13;
5'b01110 : assign CNTVALUEIN_INTEGER = 14;
5'b01111 : assign CNTVALUEIN_INTEGER = 15;
5'b10000 : assign CNTVALUEIN_INTEGER = 16;
5'b10001 : assign CNTVALUEIN_INTEGER = 17;
5'b10010 : assign CNTVALUEIN_INTEGER = 18;
5'b10011 : assign CNTVALUEIN_INTEGER = 19;
5'b10100 : assign CNTVALUEIN_INTEGER = 20;
5'b10101 : assign CNTVALUEIN_INTEGER = 21;
5'b10110 : assign CNTVALUEIN_INTEGER = 22;
5'b10111 : assign CNTVALUEIN_INTEGER = 23;
5'b11000 : assign CNTVALUEIN_INTEGER = 24;
5'b11001 : assign CNTVALUEIN_INTEGER = 25;
5'b11010 : assign CNTVALUEIN_INTEGER = 26;
5'b11011 : assign CNTVALUEIN_INTEGER = 27;
5'b11100 : assign CNTVALUEIN_INTEGER = 28;
5'b11101 : assign CNTVALUEIN_INTEGER = 29;
5'b11110 : assign CNTVALUEIN_INTEGER = 30;
5'b11111 : assign CNTVALUEIN_INTEGER = 31;
endcase
end
//*********************************************************
//*** SELECT IDATA signal
//*********************************************************
always @(clkin_in or odatain_in) begin
case (DELAY_SRC)
"ODATAIN" : begin
data_mux <= odatain_in;
end
"CLKIN" : begin
data_mux <= clkin_in;
end
default : begin
$display("Attribute Syntax Error : The attribute DELAY_SRC on ODELAYE2_FINEDELAY instance %m is set to %s. Legal values for this attribute are CLKIN or ODATAIN", DELAY_SRC);
$finish;
end
endcase // case(DELAY_SRC)
end // always @(datain_in or idatain_in)
//*********************************************************
//*** DELAY IDATA signal
//*********************************************************
assign #(DELAY_D) delay_chain_0 = data_mux;
assign #CALC_TAPDELAY_RD delay_chain_1 = delay_chain_0;
assign #CALC_TAPDELAY_RD delay_chain_2 = delay_chain_1;
assign #CALC_TAPDELAY_RD delay_chain_3 = delay_chain_2;
assign #CALC_TAPDELAY_RD delay_chain_4 = delay_chain_3;
assign #CALC_TAPDELAY_RD delay_chain_5 = delay_chain_4;
assign #CALC_TAPDELAY_RD delay_chain_6 = delay_chain_5;
assign #CALC_TAPDELAY_RD delay_chain_7 = delay_chain_6;
assign #CALC_TAPDELAY_RD delay_chain_8 = delay_chain_7;
assign #CALC_TAPDELAY_RD delay_chain_9 = delay_chain_8;
assign #CALC_TAPDELAY_RD delay_chain_10 = delay_chain_9;
assign #CALC_TAPDELAY_RD delay_chain_11 = delay_chain_10;
assign #CALC_TAPDELAY_RD delay_chain_12 = delay_chain_11;
assign #CALC_TAPDELAY_RD delay_chain_13 = delay_chain_12;
assign #CALC_TAPDELAY_RD delay_chain_14 = delay_chain_13;
assign #CALC_TAPDELAY_RD delay_chain_15 = delay_chain_14;
assign #CALC_TAPDELAY_RD delay_chain_16 = delay_chain_15;
assign #CALC_TAPDELAY_RD delay_chain_17 = delay_chain_16;
assign #CALC_TAPDELAY_RD delay_chain_18 = delay_chain_17;
assign #CALC_TAPDELAY_RD delay_chain_19 = delay_chain_18;
assign #CALC_TAPDELAY_RD delay_chain_20 = delay_chain_19;
assign #CALC_TAPDELAY_RD delay_chain_21 = delay_chain_20;
assign #CALC_TAPDELAY_RD delay_chain_22 = delay_chain_21;
assign #CALC_TAPDELAY_RD delay_chain_23 = delay_chain_22;
assign #CALC_TAPDELAY_RD delay_chain_24 = delay_chain_23;
assign #CALC_TAPDELAY_RD delay_chain_25 = delay_chain_24;
assign #CALC_TAPDELAY_RD delay_chain_26 = delay_chain_25;
assign #CALC_TAPDELAY_RD delay_chain_27 = delay_chain_26;
assign #CALC_TAPDELAY_RD delay_chain_28 = delay_chain_27;
assign #CALC_TAPDELAY_RD delay_chain_29 = delay_chain_28;
assign #CALC_TAPDELAY_RD delay_chain_30 = delay_chain_29;
assign #CALC_TAPDELAY_RD delay_chain_31 = delay_chain_30;
//*********************************************************
//*** assign delay
//*********************************************************
always @(odelay_count) begin
case (odelay_count)
0: assign tap_out_rd = delay_chain_0;
1: assign tap_out_rd = delay_chain_1;
2: assign tap_out_rd = delay_chain_2;
3: assign tap_out_rd = delay_chain_3;
4: assign tap_out_rd = delay_chain_4;
5: assign tap_out_rd = delay_chain_5;
6: assign tap_out_rd = delay_chain_6;
7: assign tap_out_rd = delay_chain_7;
8: assign tap_out_rd = delay_chain_8;
9: assign tap_out_rd = delay_chain_9;
10: assign tap_out_rd = delay_chain_10;
11: assign tap_out_rd = delay_chain_11;
12: assign tap_out_rd = delay_chain_12;
13: assign tap_out_rd = delay_chain_13;
14: assign tap_out_rd = delay_chain_14;
15: assign tap_out_rd = delay_chain_15;
16: assign tap_out_rd = delay_chain_16;
17: assign tap_out_rd = delay_chain_17;
18: assign tap_out_rd = delay_chain_18;
19: assign tap_out_rd = delay_chain_19;
20: assign tap_out_rd = delay_chain_20;
21: assign tap_out_rd = delay_chain_21;
22: assign tap_out_rd = delay_chain_22;
23: assign tap_out_rd = delay_chain_23;
24: assign tap_out_rd = delay_chain_24;
25: assign tap_out_rd = delay_chain_25;
26: assign tap_out_rd = delay_chain_26;
27: assign tap_out_rd = delay_chain_27;
28: assign tap_out_rd = delay_chain_28;
29: assign tap_out_rd = delay_chain_29;
30: assign tap_out_rd = delay_chain_30;
31: assign tap_out_rd = delay_chain_31;
default:
assign tap_out_rd = delay_chain_0;
endcase
end // always @ (odelay_count)
//*********************************************************
//*** FINE DELAY signal
//*********************************************************
assign #(INIT_DELAY_FD) fine_delay_0 = tap_out_rd;
assign #CALC_TAPDELAY_FD fine_delay_1 = fine_delay_0;
assign #CALC_TAPDELAY_FD fine_delay_2 = fine_delay_1;
assign #CALC_TAPDELAY_FD fine_delay_3 = fine_delay_2;
assign #CALC_TAPDELAY_FD fine_delay_4 = fine_delay_3;
assign #CALC_TAPDELAY_FD fine_delay_5 = fine_delay_4;
always @(ofdly_in) begin
case (ofdly_in)
3'b000: assign tap_out_fd = fine_delay_0;
3'b001: assign tap_out_fd = fine_delay_1;
3'b010: assign tap_out_fd = fine_delay_2;
3'b011: assign tap_out_fd = fine_delay_3;
3'b100: assign tap_out_fd = fine_delay_4;
default:
assign tap_out_fd = 1'bx;
endcase
end // always @ (ofdly_in)
`ifdef XIL_TIMING
//*** Timing Checks Start here
always @(notifier) begin
tap_out_rd <= 1'bx;
end
`endif // ifdef XIL_TIMING
specify
( C *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( C => DATAOUT) = (100:100:100, 100:100:100);
( CINVCTRL *> CNTVALUEOUT) = (100:100:100, 100:100:100);
( CINVCTRL => DATAOUT) = (100:100:100, 100:100:100);
( CLKIN => DATAOUT) = (100:100:100, 100:100:100);
( ODATAIN => DATAOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (posedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (posedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (posedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (posedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (posedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (posedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (posedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (posedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (posedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (posedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ce);
$setuphold (negedge C, posedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (negedge C, negedge INC, 0:0:0, 0:0:0, notifier, , , delay_c, delay_inc);
$setuphold (negedge C, posedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (negedge C, negedge LD, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ld);
$setuphold (negedge C, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (negedge C, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_cntvaluein);
$setuphold (negedge C, posedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (negedge C, negedge LDPIPEEN, 0:0:0, 0:0:0, notifier, , , delay_c, delay_ldpipeen);
$setuphold (negedge C, posedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
$setuphold (negedge C, negedge REGRST, 0:0:0, 0:0:0, notifier, , , delay_c, delay_regrst);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODELAYE2_FINEDELAY
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ODELAYE3.v 0000664 0000000 0000000 00000063036 12327044266 0022577 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Input Fixed or Variable Delay Element
// /___/ /\ Filename : ODELAYE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ODELAYE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE = "NONE",
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REFCLK_FREQUENCY = 300.0,
parameter UPDATE_MODE = "ASYNC"
)(
output CASC_OUT,
output [8:0] CNTVALUEOUT,
output DATAOUT,
input CASC_IN,
input CASC_RETURN,
input CE,
input CLK,
input [8:0] CNTVALUEIN,
input EN_VTC,
input ODATAIN,
input INC,
input LOAD,
input RST
);
// define constants
localparam MODULE_NAME = "ODELAYE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
localparam MAX_DELAY_COUNT = 511;
localparam MIN_DELAY_COUNT = 0;
localparam PER_BIT_FINE_DELAY = 5;
localparam PER_BIT_MEDIUM_DELAY = 40;
localparam INTRINSIC_FINE_DELAY = 90;
localparam INTRINSIC_MEDIUM_DELAY = 40;
localparam ODATAIN_INTRINSIC_DELAY = 50;
localparam CASC_IN_INTRINSIC_DELAY = 50;
//localparam CASC_RET_INTRINSIC_DELAY = 50;
localparam CASC_RET_INTRINSIC_DELAY = 0;
localparam DATA_OUT_INTRINSIC_DELAY = 40;
localparam CASC_OUT_INTRINSIC_DELAY = 40;
// Parameter encodings and registers
localparam CASCADE_MASTER = 2'b11;
localparam CASCADE_NONE = 2'b00;
localparam CASCADE_SLAVE_END = 2'b01;
localparam CASCADE_SLAVE_MIDDLE = 2'b10;
localparam DELAY_FORMAT_COUNT = 1;
localparam DELAY_FORMAT_TIME = 0;
localparam DELAY_TYPE_FIXED = 2'b00;
localparam DELAY_TYPE_VARIABLE = 2'b01;
localparam DELAY_TYPE_VAR_LOAD = 2'b10;
localparam DELAY_VALUE_0 = 0;
localparam UPDATE_MODE_ASYNC = 2'b00;
localparam UPDATE_MODE_MANUAL = 2'b01;
localparam UPDATE_MODE_SYNC = 2'b10;
`ifndef XIL_DR
localparam CASCADE_REG = CASCADE;
localparam DELAY_FORMAT_REG = DELAY_FORMAT;
localparam DELAY_TYPE_REG = DELAY_TYPE;
localparam DELAY_VALUE_REG = DELAY_VALUE;
localparam IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam UPDATE_MODE_REG = UPDATE_MODE;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
`endif
wire [1:0] CASCADE_BIN;
wire DELAY_FORMAT_BIN;
wire [1:0] DELAY_TYPE_BIN;
//wire DELAY_VALUE_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [1:0] UPDATE_MODE_BIN;
wire [63:0] REFCLK_FREQUENCY_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "ODELAYE3_dr.v"
`endif
reg CASC_OUT_reg;
reg DATAOUT_reg;
reg [8:0] CNTVALUEOUT_reg;
reg [8:0] qcntvalueout_reg = 9'b0;
reg tap_out;
reg clk_smux;
reg tap_out_casc_out_none;
reg tap_out_casc_out;
reg tap_out_data_out;
reg data_mux = 0;
wire CASC_OUT_delay;
wire DATAOUT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CASC_IN_in;
wire CASC_RETURN_in;
wire CE_in;
wire CLK_in;
wire EN_VTC_in;
wire ODATAIN_in;
wire INC_in;
wire LOAD_in;
wire RST_in;
reg RST_sync1;
reg RST_sync2;
reg RST_sync3;
wire [8:0] CNTVALUEIN_in;
wire gsr_in;
reg [8:0] idelay_count_async;
reg [8:0] idelay_count_sync;
reg [8:0] cntvalue_updated;
reg [8:0] cntvalue_updated_sync;
reg [8:0] cntvalue_updated_async;
reg [8:0] cascade_mode_delay;
reg [8:0] idelay_count_pre;
reg [8:0] CNTVALUEIN_INTEGER;
time delay_value;
time delay_value_casc_out;
time delay_value_data_out;
wire CASC_IN_delay;
wire CASC_RETURN_delay;
wire CE_delay;
wire CLK_delay;
wire EN_VTC_delay;
wire ODATAIN_delay;
wire INC_delay;
wire LOAD_delay;
wire RST_delay;
wire [8:0] CNTVALUEIN_delay;
// input output assignments
assign #(out_delay) CASC_OUT = CASC_OUT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) DATAOUT = DATAOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_delay = LOAD;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) CASC_IN_delay = CASC_IN;
assign #(in_delay) CASC_RETURN_delay = CASC_RETURN;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) ODATAIN_delay = ODATAIN;
assign CASC_OUT_delay = CASC_OUT_reg;
assign CNTVALUEOUT_delay = CNTVALUEOUT_reg;
assign DATAOUT_delay = DATAOUT_reg;
assign CASC_IN_in = CASC_IN_delay;
assign CASC_RETURN_in = CASC_RETURN_delay;
assign CE_in = CE_delay;
assign CLK_in = IS_CLK_INVERTED_BIN ? ~CLK_delay : CLK_delay;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign EN_VTC_in = EN_VTC_delay;
assign ODATAIN_in = ODATAIN_delay;
assign INC_in = INC_delay;
assign LOAD_in = LOAD_delay;
assign RST_in = IS_RST_INVERTED_BIN ? ~RST_delay : RST_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CASCADE_BIN =
(CASCADE_REG == "NONE") ? CASCADE_NONE :
(CASCADE_REG == "MASTER") ? CASCADE_MASTER :
(CASCADE_REG == "SLAVE_END") ? CASCADE_SLAVE_END :
(CASCADE_REG == "SLAVE_MIDDLE") ? CASCADE_SLAVE_MIDDLE :
CASCADE_NONE;
assign DELAY_FORMAT_BIN =
(DELAY_FORMAT_REG == "TIME") ? DELAY_FORMAT_TIME :
(DELAY_FORMAT_REG == "COUNT") ? DELAY_FORMAT_COUNT :
DELAY_FORMAT_TIME;
assign DELAY_TYPE_BIN =
(DELAY_TYPE_REG == "FIXED") ? DELAY_TYPE_FIXED :
(DELAY_TYPE_REG == "VARIABLE") ? DELAY_TYPE_VARIABLE :
(DELAY_TYPE_REG == "VAR_LOAD") ? DELAY_TYPE_VAR_LOAD :
DELAY_TYPE_FIXED;
// assign DELAY_VALUE_BIN =
// (DELAY_VALUE_REG == 0) ? DELAY_VALUE_0 :
// DELAY_VALUE_0;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign REFCLK_FREQUENCY_BIN = $realtobits(REFCLK_FREQUENCY_REG);
assign UPDATE_MODE_BIN =
(UPDATE_MODE_REG == "ASYNC") ? UPDATE_MODE_ASYNC :
(UPDATE_MODE_REG == "MANUAL") ? UPDATE_MODE_MANUAL :
(UPDATE_MODE_REG == "SYNC") ? UPDATE_MODE_SYNC :
UPDATE_MODE_ASYNC;
always @ (trig_attr) begin
#1;
case (CASCADE_REG) // string
"NONE" : /* */;
"MASTER" : /* */;
"SLAVE_END" : /* */;
"SLAVE_MIDDLE" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on %s instance %m is set to %s. Legal values for this attribute are NONE, MASTER, SLAVE_END or SLAVE_MIDDLE.", MODULE_NAME, CASCADE_REG);
attr_err = 1'b1;
end
endcase
case (DELAY_FORMAT_REG) // string
"TIME" : /* */;
"COUNT" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
endcase
case (DELAY_TYPE_REG) // string
"FIXED" : /* */;
"VARIABLE" : /* */;
"VAR_LOAD" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((DELAY_VALUE_REG >= 0) && (DELAY_VALUE_REG <= 1250)) // decimal
/* */;
else begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_REG, 0);
attr_err = 1'b1;
end
case (UPDATE_MODE_REG) // string
"ASYNC" : /* */;
"MANUAL" : /* */;
"SYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CLK_INVERTED_REG == 1'b0) || (IS_CLK_INVERTED_REG == 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG == 1'b0) || (IS_RST_INVERTED_REG == 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (REFCLK_FREQUENCY_REG >= 300.0 && REFCLK_FREQUENCY_REG <= 1333.0) // float
/* */;
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME)
if ((DELAY_VALUE_REG == 0) || (REFCLK_FREQUENCY_REG == 0)) begin
idelay_count_pre = 0;
cntvalue_updated = idelay_count_pre;
end
else begin
idelay_count_pre = DELAY_VALUE_REG/2.446;
cntvalue_updated = idelay_count_pre;
end
else if (DELAY_FORMAT_BIN == DELAY_FORMAT_COUNT) begin
idelay_count_pre = DELAY_VALUE_REG;
cntvalue_updated = idelay_count_pre;
end
end
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
always @(tap_out or tap_out_data_out or tap_out_casc_out or tap_out_casc_out_none or CASCADE_REG) begin
case (CASCADE_REG)
"MASTER","SLAVE_MIDDLE" : begin
DATAOUT_reg <= #(DATA_OUT_INTRINSIC_DELAY) tap_out_data_out;
CASC_OUT_reg <= #(CASC_OUT_INTRINSIC_DELAY) tap_out_casc_out;
end
"NONE","SLAVE_END" : begin
DATAOUT_reg <= #(DATA_OUT_INTRINSIC_DELAY) tap_out;
CASC_OUT_reg <= #(CASC_OUT_INTRINSIC_DELAY) tap_out_casc_out_none;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on ODELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
end // always @(tap_out or CASC_RETURN_in)
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign gsr_in = glblGSR;
//*** GLOBAL hidden GSR pin
always @(gsr_in or RST_in) begin
if (gsr_in == 1'b1 || RST_in == 1'b1) begin
assign idelay_count_sync = idelay_count_pre;
assign idelay_count_async = idelay_count_pre;
assign cntvalue_updated_sync = idelay_count_pre;
assign cntvalue_updated_async = idelay_count_pre;
end
else if (gsr_in == 1'b0 || RST_in == 1'b0) begin
deassign idelay_count_sync;
deassign idelay_count_async;
deassign cntvalue_updated_sync;
deassign cntvalue_updated_async;
end
end
//----------------------------------------------------------------------
//------------------------ CNTVALUEOUT ---------------------
//----------------------------------------------------------------------
always @(idelay_count_sync or idelay_count_async or cntvalue_updated_async or cntvalue_updated_sync or UPDATE_MODE_REG) begin
case (UPDATE_MODE_REG)
"SYNC" : begin
assign CNTVALUEOUT_reg = idelay_count_sync;
assign cntvalue_updated = cntvalue_updated_sync;
end
"ASYNC" , "MANUAL" : begin
assign CNTVALUEOUT_reg = idelay_count_async;
assign cntvalue_updated = cntvalue_updated_async;
end
default: $display("Attribute Syntax Error:UPDATE_MODE_REG=%s is not valid value\n",UPDATE_MODE_REG);
endcase
end
//----------------------------------------------------------------------
//-------------------------- DELAY_COUNT ----------------------------
//----------------------------------------------------------------------
always @(CLK_in or RST_in or RST_sync3 or RST_sync2 or RST_sync1) begin
if (RST_in == 1'b1 || RST_sync3 == 1'b1 || RST_sync2 == 1'b1 || RST_sync1 == 1'b1)
clk_smux <= 1'b0;
else if (RST_sync3 == 1'b0)
clk_smux <= CLK_in;
end
always @(posedge CLK_in) begin
RST_sync1 <= RST_in;
RST_sync2 <= RST_sync1;
RST_sync3 <= RST_sync2;
end
always @(posedge clk_smux) begin
if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin
case(DELAY_TYPE_REG)
"FIXED": ; //Do nothing.
"VAR_LOAD":
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_async > MIN_DELAY_COUNT)
idelay_count_async = idelay_count_async-1;
else if (idelay_count_async == MIN_DELAY_COUNT)
idelay_count_async = MAX_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b011:
begin //{
if (idelay_count_async < MAX_DELAY_COUNT)
idelay_count_async = idelay_count_async + 1;
else if (idelay_count_async == MAX_DELAY_COUNT)
idelay_count_async = MIN_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b100, 3'b101:
begin //{
idelay_count_async = CNTVALUEIN_INTEGER;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_async = idelay_count_async;
end //}
3'b110:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else cntvalue_updated_async = idelay_count_async;
3'b111:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else idelay_count_async = idelay_count_async + CNTVALUEIN_INTEGER;
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b INC = %b \n", LOAD_in,CE_in,INC_in);
endcase
"VARIABLE":
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_async > MIN_DELAY_COUNT)
idelay_count_async = idelay_count_async-1;
else if (idelay_count_async == MIN_DELAY_COUNT)
idelay_count_async = MAX_DELAY_COUNT;
cntvalue_updated_async = idelay_count_async;
end //}
3'b011:
begin //{
if (idelay_count_async < MAX_DELAY_COUNT)
idelay_count_async = idelay_count_async + 1;
else if (idelay_count_async == MAX_DELAY_COUNT)
idelay_count_async = MIN_DELAY_COUNT;
cntvalue_updated_async = idelay_count_async;
end //}
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b, INC = %b, DELAY_TYPE=%s \n",LOAD_in,CE_in,INC_in,DELAY_TYPE_REG);
endcase
default: $display("FAILURE: DELAY_TYPE=%s is not a valid value\n",DELAY_TYPE_REG);
endcase
end
end // always @ (posedge CLK_in)
always @(posedge data_mux) begin
if (RST_in == 1'b0 && RST_sync1 == 1'b0 && RST_sync2 == 1'b0 && RST_sync3 == 1'b0) begin
if (UPDATE_MODE_BIN == UPDATE_MODE_SYNC) begin
case (DELAY_TYPE_REG)
"VAR_LOAD" : begin
casex({LOAD_in, CE_in, INC_in})
3'b000: ; //Do nothing.
3'b001: ; //Do nothing.
3'b010:
begin //{
if (idelay_count_sync > MIN_DELAY_COUNT)
idelay_count_sync = idelay_count_sync-1;
else if (idelay_count_sync == MIN_DELAY_COUNT)
idelay_count_sync = MAX_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b011:
begin //{
if (idelay_count_sync < MAX_DELAY_COUNT)
idelay_count_sync = idelay_count_sync + 1;
else if (idelay_count_sync == MAX_DELAY_COUNT)
idelay_count_sync = MIN_DELAY_COUNT;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b100, 3'b101:
begin //{
idelay_count_sync = CNTVALUEIN_INTEGER;
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL)
cntvalue_updated_sync = idelay_count_sync;
end //}
3'b110:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else cntvalue_updated_sync = idelay_count_sync;
3'b111:
if(UPDATE_MODE_BIN != UPDATE_MODE_MANUAL) $display("FAILURE: Invalid scenario. LOAD = 1, CE = 1 INC = 0 is not valid for UPDATE_MODE=%s and DELAY_TYPE=%s\n",UPDATE_MODE_REG,DELAY_TYPE_REG);
else idelay_count_sync = idelay_count_sync + CNTVALUEIN_INTEGER;
default: $display("FAILURE: Invalid scenario. LOAD = %b, CE = %b INC = %b \n",LOAD_in,CE_in,INC_in);
endcase
end
default : begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE = %s on ODELAYE3 instance %m is not supported for DELAY_TYPE set to %s. ", UPDATE_MODE_REG,DELAY_TYPE_REG);
$finish;
end
endcase
end
end // UPDATE_MODE_REG
// end //else if
end //always
always @(CNTVALUEIN_in or gsr_in) begin
assign CNTVALUEIN_INTEGER = CNTVALUEIN_in;
end
//*********************************************************
//*** SELECT DATA signal
//*********************************************************
always @(ODATAIN_in or CASC_IN_in or CASCADE_REG) begin
case (CASCADE_REG)
"NONE", "MASTER" : begin
data_mux <= ODATAIN_in;
end
"SLAVE_END", "SLAVE_MIDDLE" : begin
data_mux <= CASC_IN_in;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on ODELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
end // always @(ODATAIN_in or CASC_IN_in)
always @ (cntvalue_updated or data_mux or CASC_RETURN_in or DELAY_FORMAT_REG) begin
if (DELAY_FORMAT_BIN == DELAY_FORMAT_TIME) begin
delay_value = (cntvalue_updated*2.446) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
cascade_mode_delay = cntvalue_updated*2.446;
delay_value_casc_out = cascade_mode_delay/2 + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
if (cascade_mode_delay % 2 == 1)
delay_value_data_out = cascade_mode_delay/2 + 1;
else
delay_value_data_out = cascade_mode_delay/2;
end else begin
delay_value = (cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY) + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
cascade_mode_delay = (cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY);
delay_value_casc_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2 + INTRINSIC_FINE_DELAY + INTRINSIC_MEDIUM_DELAY ;
if (cascade_mode_delay % 2 == 1)
delay_value_data_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2 + 1;
else
delay_value_data_out = ((cntvalue_updated[2:0] * PER_BIT_FINE_DELAY)+(cntvalue_updated[8:3] * PER_BIT_MEDIUM_DELAY))/2;
end
case (CASCADE_REG)
"NONE", "MASTER" : begin
delay_value = delay_value + ODATAIN_INTRINSIC_DELAY;
delay_value_casc_out = delay_value_casc_out + ODATAIN_INTRINSIC_DELAY;
end
"SLAVE_END", "SLAVE_MIDDLE" : begin
delay_value = delay_value + CASC_IN_INTRINSIC_DELAY;
delay_value_casc_out = delay_value_casc_out + CASC_IN_INTRINSIC_DELAY;
end
default : begin
$display("Attribute Syntax Error : The attribute CASCADE on IDELAYE3 instance %m is set to %s. Legal values for this attribute are NONE or MASTER or SLAVE_END or SLAVE_MIDDLE", CASCADE_REG);
$finish;
end
endcase // case(CASCADE_REG)
tap_out <= #delay_value data_mux;
if (cntvalue_updated[8:3] >= 6'b011111 ) begin
tap_out_casc_out_none <= #delay_value_casc_out data_mux;
end
else begin
tap_out_casc_out_none <= 1'b0;
end
if (cntvalue_updated[8:3] == 6'b111111 ) begin
tap_out_data_out <= #(delay_value_data_out + CASC_RET_INTRINSIC_DELAY) ~CASC_RETURN_in;
tap_out_casc_out <= #delay_value_casc_out ~data_mux;
end
else begin
tap_out_data_out <= #delay_value data_mux;
tap_out_casc_out <= 1'b1;
end
end
specify
(CASC_IN => DATAOUT) = (0:0:0, 0:0:0);
(CASC_RETURN => DATAOUT) = (0:0:0, 0:0:0);
(CLK *> CNTVALUEOUT) = (0:0:0, 0:0:0);
(ODATAIN => DATAOUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem ( negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OR2L.v 0000664 0000000 0000000 00000003030 12327044266 0022134 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1 (L.33)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Latch used as 2-input OR Gate
// /___/ /\ Filename : OR2L.v
// \ \ / \ Timestamp : Tue Feb 26 11:11:42 PST 2008
// \___\/\___\
//
// Revision:
// 02/26/08 - Initial version.
// 04/01/08 - Add GSR.
// 02/19/09 - Order port name (CR509139)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OR2L #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_SRI_INVERTED = 1'b0
)(
output O,
input DI,
input SRI
);
tri0 GSR = glbl.GSR;
wire o_out;
wire SRI_in;
assign O = (GSR) ? 0 : o_out;
or O1 (o_out, SRI_in, DI);
assign SRI_in = IS_SRI_INVERTED ^ SRI;
`ifdef XIL_TIMING
specify
(DI => O) = (0:0:0, 0:0:0);
(SRI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OSERDES.v 0000664 0000000 0000000 00000073717 12327044266 0022545 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDES.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV
// 08/21/06 - CR 210819 -- Added timing checks for DDR mode
// 06/06/07 - Fixed timescale values
// 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode.
// 04/16/08 - CR 468871 Negative SetupHold fix
// 04/23/09 - CR 516748 simprim only fix
// 06/01/09 - CR 523601 simprim only (timing) fix for Tristate Output
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ,
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
tri0 GSR = glbl.GSR;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
input T4;
input TCE;
reg c23, c45, c67;
reg t1r, t2r, t3r, t4r;
reg io_sdata_edge, io_odata_edge, io_ddr_data;
reg iot_sdata_edge, iot_odata_edge, iot_ddr_data;
reg data1, data2, data3, data4, data5, data6;
reg serdes_mode_int, serdes_int;
reg data_rate_oq_int, ddr_clk_edge_int;
reg [1:0] data_rate_tq_int, tristate_width_int;
reg [1:0] sel;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg q0, q1, q2, q3;
reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg qt1, qt2, qt2n;
reg load, qhr, qlr, mux;
reg data1t, data2t;
reg oq_out = INIT_OQ, tq_out = INIT_TQ;
reg [3:0] data_width_int;
reg notifier;
wire oqsr, oqrev;
wire tqsr, tqrev;
wire c2p, c3;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] sel_tri;
wire [6:0] seltq;
wire [3:0] seloq;
wire clk_in;
wire clkdiv_in;
wire d1_in;
wire d2_in;
wire d3_in;
wire d4_in;
wire d5_in;
wire d6_in;
wire gsr_in;
wire oce_in;
wire sr_in;
wire rev_in;
wire shiftin1_in;
wire shiftin2_in;
wire t1_in;
wire t2_in;
wire t3_in;
wire t4_in;
wire tce_in;
wire shiftout1_out;
wire shiftout2_out;
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tq (TQ, tq_out);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d1 (d1_in, D1);
buf b_d2 (d2_in, D2);
buf b_d3 (d3_in, D3);
buf b_d4 (d4_in, D4);
buf b_d5 (d5_in, D5);
buf b_d6 (d6_in, D6);
buf b_gsr (gsr_in, GSR);
buf b_oce (oce_in, OCE);
buf b_r (sr_in, SR);
buf b_s (rev_in, REV);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
buf b_t1 (t1_in, T1);
buf b_t2 (t2_in, T2);
buf b_t3 (t3_in, T3);
buf b_t4 (t4_in, T4);
buf b_tce (tce_in, TCE);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
localparam io_ffd = 1; // clock to out delay for flip flops driven by clk
localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv
localparam io_mxd = 1; // 60 ps mux delay
localparam io_mxr1 = 1; // mux before 2nd rank of flops
// Programmable load generator
localparam ffdcnt = 1;
localparam mxdcnt = 1;
// CR 516748
// localparam ffrst = 145; // clock to out delay for flop in PLSG
localparam ffrst = 45; // clock to out delay for flop in PLSG
// Tristate output delays
localparam iot_ffd = 1;
// CR 523601
// localparam iot_mxd = 1;
localparam iot_mxd = 20;
/////////////////////////////////////////////////////////////
always @(gsr_in)
if (gsr_in) begin
assign oq_out = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
assign d6rnk2 = 1'b0;
assign d5rnk2 = 1'b0;
assign d4rnk2 = 1'b0;
assign d3rnk2 = 1'b0;
assign d6r = 1'b0;
assign d5r = 1'b0;
assign d4r = 1'b0;
assign d3r = 1'b0;
assign d2r = 1'b0;
assign d1r = 1'b0;
// PLG
assign q3 = 1'b0;
assign q2 = 1'b0;
assign q1 = 1'b0;
assign q0 = 1'b0;
// Tristate output
assign tq_out = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
assign t4r = 1'b0;
assign t3r = 1'b0;
assign t2r = 1'b0;
assign t1r = 1'b0;
end
else begin
deassign oq_out;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
// PLG
deassign q3;
deassign q2;
deassign q1;
deassign q0;
// Tristate output
deassign tq_out;
deassign qt1;
deassign qt2;
deassign qt2n;
deassign t4r;
deassign t3r;
deassign t2r;
deassign t1r;
end
initial begin
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
serdes_int <= 1'b1; // SERDES = TRUE
ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
$finish;
end
endcase // case(DATA_RATE_OQ)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
$finish;
end
endcase // case(DATA_RATE_TQ)
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
$finish;
end
endcase // case(TRISTATE_WIDTH)
end // initial begin
assign shiftout1_out = d3rnk2 & serdes_mode_int;
assign shiftout2_out = d4rnk2 & serdes_mode_int;
assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int);
assign c3 = !c2p;
assign sel1_4 = {serdes_int, load, data_rate_oq_int};
assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int};
// Tristate output
assign sel_tri = {load, data_rate_tq_int, tristate_width_int};
assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev};
assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev};
assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ);
assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ);
assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ);
assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ);
// 3 flops to create DDR operations of 4 latches
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d1rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d1rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d1rnk2 <= # io_ffd data1;
else if (oce_in == 1'b0) // to match with HW
d1rnk2 <= # io_ffd oq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2rnk2 <= # io_ffd data2;
else if (oce_in == 1'b0) // to match with HW
d2rnk2 <= # io_ffd oq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2nrnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2nrnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2nrnk2 <= # io_ffd d2rnk2;
else if (oce_in == 1'b0) // to match with HW
d2nrnk2 <= # io_ffd oq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge clk_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d3rnk2 <= # io_ffd 1'b0;
d4rnk2 <= # io_ffd 1'b0;
d5rnk2 <= # io_ffd 1'b0;
d6rnk2 <= # io_ffd 1'b0;
end
else begin
d3rnk2 <= # io_ffd data3;
d4rnk2 <= # io_ffd data4;
d5rnk2 <= # io_ffd data5;
d6rnk2 <= # io_ffd data6;
end
end // always @ (posedge clk_in or posedge sr_in)
// First rank of flops for input data
// asynchronous operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d1r <= # io_ffcd 1'b0;
d2r <= # io_ffcd 1'b0;
d3r <= # io_ffcd 1'b0;
d4r <= # io_ffcd 1'b0;
d5r <= # io_ffcd 1'b0;
d6r <= # io_ffcd 1'b0;
end
else begin
d1r <= # io_ffcd d1_in;
d2r <= # io_ffcd d2_in;
d3r <= # io_ffcd d3_in;
d4r <= # io_ffcd d4_in;
d5r <= # io_ffcd d5_in;
d6r <= # io_ffcd d6_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin
casex (sel1_4)
3'b100: data1 <= # io_mxr1 d3rnk2;
3'b110: data1 <= # io_mxr1 d1r;
3'b101: data1 <= # io_mxr1 d2rnk2;
3'b111: data1 <= # io_mxr1 d1r;
default: data1 <= # io_mxr1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin
casex (sel1_4)
3'b100: data2 <= # io_mxr1 d4rnk2;
3'b110: data2 <= # io_mxr1 d2r;
3'b101: data2 <= # io_mxr1 d3rnk2;
3'b111: data2 <= # io_mxr1 d2r;
default: data2 <= # io_mxr1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin
casex (sel1_4)
3'b100: data3 <= # io_mxr1 d5rnk2;
3'b110: data3 <= # io_mxr1 d3r;
3'b101: data3 <= # io_mxr1 d4rnk2;
3'b111: data3 <= # io_mxr1 d3r;
default: data3 <= # io_mxr1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin
casex (sel1_4)
3'b100: data4 <= # io_mxr1 d6rnk2;
3'b110: data4 <= # io_mxr1 d4r;
3'b101: data4 <= # io_mxr1 d5rnk2;
3'b111: data4 <= # io_mxr1 d4r;
default: data4 <= # io_mxr1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin
casex (sel5_6)
4'b1000: data5 <= # io_mxr1 shiftin1_in;
4'b1010: data5 <= # io_mxr1 d5r;
4'b1001: data5 <= # io_mxr1 d6rnk2;
4'b1011: data5 <= # io_mxr1 d5r;
4'b1100: data5 <= # io_mxr1 1'b0;
4'b1110: data5 <= # io_mxr1 d5r;
4'b1101: data5 <= # io_mxr1 d6rnk2;
4'b1111: data5 <= # io_mxr1 d5r;
default: data5 <= # io_mxr1 shiftin1_in;
endcase
end
always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin
casex (sel5_6)
4'b1000: data6 <= # io_mxr1 shiftin2_in;
4'b1010: data6 <= # io_mxr1 d6r;
4'b1001: data6 <= # io_mxr1 shiftin1_in;
4'b1011: data6 <= # io_mxr1 d6r;
4'b1100: data6 <= # io_mxr1 1'b0;
4'b1110: data6 <= # io_mxr1 d6r;
4'b1101: data6 <= # io_mxr1 1'b0;
4'b1111: data6 <= # io_mxr1 d6r;
default: data6 <= # io_mxr1 shiftin2_in;
endcase
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin
io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @(clk_in or d1rnk2 or d2rnk2) begin
case (clk_in)
1'b0: io_odata_edge <= # io_mxd d2rnk2;
1'b1: io_odata_edge <= # io_mxd d1rnk2;
default: io_odata_edge <= # io_mxd d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin
io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin
casex (seloq)
4'bXX01: oq_out <= # io_mxd 1'b1;
4'bXX10: oq_out <= # io_mxd 1'b0;
4'bXX11: oq_out <= # io_mxd 1'b0;
4'b0000: oq_out <= # io_mxd oq_out;
4'b0100: oq_out <= # io_mxd oq_out;
4'b1000: oq_out <= # io_mxd io_ddr_data;
4'b1100: oq_out <= # io_mxd d1rnk2;
default: oq_out <= # io_mxd io_ddr_data;
endcase
end
// Set value of counter in bitslip controller
always @ (data_rate_oq_int or data_width_int) begin
casex ({data_rate_oq_int, data_width_int})
5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end
5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end
5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end
default: begin
$display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0);
$finish;
end
endcase
end // always @ (data_rate_oq_int or data_width_int)
///////////////////////////////////////////////////////////////
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//////////////////////////////////////////////////////////////////
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk_in) begin
if (qhr) begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end // always @ (posedge qhr or posedge clk_in)
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qlr <= # ffrst 1'b1;
else
qlr <= # ffrst 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clk_in) begin
if (sr_in == 1'b1)
qhr <= # ffdcnt 1'b1;
else
qhr <= # ffdcnt qlr;
end // always @ (posedge sr_in or posedge clk_in)
///////////////////////////////////////////////////////
//
// Tristate Output cell
//
////////////////////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
// Representation of top latch
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt1 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt1 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt1 <= # iot_ffd data1t;
else if (tce_in == 1'b0)
qt1 <= # iot_ffd tq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2 <= # iot_ffd data2t;
else if (tce_in == 1'b0)
qt2 <= # iot_ffd tq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2n <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2n <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2n <= # iot_ffd qt2;
else if (tce_in == 1'b0)
qt2n <= # iot_ffd tq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// First rank of flops
// asynchronous reset operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
t1r <= # iot_ffd 1'b0;
t2r <= # iot_ffd 1'b0;
t3r <= # iot_ffd 1'b0;
t4r <= # iot_ffd 1'b0;
end
else begin
t1r <= # iot_ffd t1_in;
t2r <= # iot_ffd t2_in;
t3r <= # iot_ffd t3_in;
t4r <= # iot_ffd t4_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Data Muxs for tristate otuput signals
always @ (sel_tri or t1_in or t1r or t3r) begin
casex (sel_tri)
5'b00000: data1t <= # iot_mxd t1_in;
5'b10000: data1t <= # iot_mxd t1_in;
5'bX0000: data1t <= # iot_mxd t1_in;
5'b00100: data1t <= # iot_mxd t1_in;
5'b10100: data1t <= # iot_mxd t1_in;
5'bX0100: data1t <= # iot_mxd t1_in;
5'b01001: data1t <= # iot_mxd t1_in;
5'b11001: data1t <= # iot_mxd t1_in;
5'b01010: data1t <= # iot_mxd t3r;
5'b11010: data1t <= # iot_mxd t1r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel_tri or t2_in or t2r or t4r) begin
casex (sel_tri)
5'b00000: data2t <= # iot_mxd t2_in;
5'b00100: data2t <= # iot_mxd t2_in;
5'b10000: data2t <= # iot_mxd t2_in;
5'b10100: data2t <= # iot_mxd t2_in;
5'bX0000: data2t <= # iot_mxd t2_in;
5'bX0100: data2t <= # iot_mxd t2_in;
5'b00X00: data2t <= # iot_mxd t2_in;
5'b10X00: data2t <= # iot_mxd t2_in;
5'bX0X00: data2t <= # iot_mxd t2_in;
5'b01001: data2t <= # iot_mxd t2_in;
5'b11001: data2t <= # iot_mxd t2_in;
5'bX1001: data2t <= # iot_mxd t2_in;
5'b01010: data2t <= # iot_mxd t4r;
5'b11010: data2t <= # iot_mxd t2r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// Logic to generate same edge data from qt1, qt3;
always @ (clk_in or c3 or qt1 or qt2n) begin
iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3);
end
// Mux to create opposite edge DDR function
always @ (clk_in or qt1 or qt2) begin
case (clk_in)
1'b0: iot_odata_edge <= # iot_mxd qt2;
1'b1: iot_odata_edge <= # iot_mxd qt1;
default: iot_odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin
iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs. Those modes are not support in this model.
always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin
casex (seltq)
7'bX01XX01: tq_out <= # iot_mxd 1'b1;
7'bX10XX01: tq_out <= # iot_mxd 1'b1;
7'bX01XX10: tq_out <= # iot_mxd 1'b0;
7'bX10XX10: tq_out <= # iot_mxd 1'b0;
7'bX01XX11: tq_out <= # iot_mxd 1'b0;
7'bX10XX11: tq_out <= # iot_mxd 1'b0;
7'bX0000XX: tq_out <= # iot_mxd data1t;
7'b0010000: tq_out <= # iot_mxd tq_out;
7'b0100100: tq_out <= # iot_mxd tq_out;
7'b0101000: tq_out <= # iot_mxd tq_out;
7'b1010000: tq_out <= # iot_mxd qt1;
7'b1100100: tq_out <= # iot_mxd iot_ddr_data;
7'b1101000: tq_out <= # iot_mxd iot_ddr_data;
default: tq_out <= # iot_mxd iot_ddr_data;
endcase
end
//*** Timing Checks Start here
`ifndef XIL_TIMING
assign clk_in = CLK;
assign oce_in = OCE;
assign tce_in = TCE;
assign clkdiv_in = CLKDIV;
assign d1_in = D1;
assign d2_in = D2;
assign d3_in = D3;
assign d4_in = D4;
assign d5_in = D5;
assign d6_in = D6;
assign rev_in = REV;
assign sr_in = SR;
assign t1_in = T1;
assign t2_in = T2;
assign t3_in = T3;
assign t4_in = T4;
`endif
specify
(CLK => OQ) = (100:100:100, 100:100:100);
(CLK => TQ) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(SR => OQ) = (0:0:0, 0:0:0);
(REV => OQ) = (0:0:0, 0:0:0);
(T1 => TQ) = (0:0:0, 0:0:0);
(SR => TQ) = (0:0:0, 0:0:0);
(REV => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
// CR 210819
$setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (negedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$recrem (negedge REV, negedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, negedge CLK, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // OSERDES
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OSERDESE1.v 0000664 0000000 0000000 00000220761 12327044266 0022724 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDESE1.v
// \ \ / \ Timestamp : Tue Sep 16 15:30:44 PDT 2008
// \___\/\___\
//
// Revision:
// 09/16/08 - Initial version.
// 12/05/08 - IR 495397.
// 01/13/09 - IR 503429.
// 01/15/09 - IR 503783 CLKPERF is not inverted for OFB/ofb_out.
// 02/06/09 - CR 507373 Removed IOCLKGLITCH and CLKB
// 02/26/09 - CR 510489 fixed SHIFTIN2_in
// 03/16/09 - CR 512140 and 512139 -- sdf load errors
// 01/27/10 - CR 546419 Updated specify block
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 09/04/12 - 676501 CLK -> OFB specify path missing
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDESE1 (OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ,
CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TCE, WC);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter integer DDR3_DATA = 1;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter INTERFACE_TYPE = "DEFAULT";
parameter integer ODELAY_USED = 0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
output OCBEXTEND;
output OFB;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TFB;
output TQ;
input CLK;
input CLKDIV;
input CLKPERF;
input CLKPERFDELAY;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input OCE;
input ODV;
input RST;
input SHIFTIN1;
input SHIFTIN2;
input T1;
input T2;
input T3;
input T4;
input TCE;
input WC;
//
wire SERDES, DDR_CLK_EDGE;
wire [5:0] SRTYPE;
wire WC_DELAY;
wire [4:0] SELFHEAL;
wire load;
wire qmux1, qmux, tmux1, tmux2;
wire data1, data2, triin1, triin2;
wire d2rnk2;
wire CLKD;
wire CLKDIVD;
wire iodelay_state;
// attribute
reg data_rate_int;
reg [3:0] data_width_int;
reg [1:0] tristate_width_int;
reg data_rate_oq_int;
reg [1:0] data_rate_tq_int;
reg ddr3_data_int;
reg interface_type_int;
reg odelay_used_int;
reg serdes_mode_int;
// Output signals
wire ioclkglitch_out, ocbextend_out, ofb_out, oq_out, tq_out, shiftout1_out, shiftout2_out;
// Other signals
tri0 GSR = glbl.GSR;
reg notifier;
wire CLK_in;
wire CLKDIV_in;
wire CLKPERF_in;
wire CLKPERFDELAY_in;
wire D1_in;
wire D2_in;
wire D3_in;
wire D4_in;
wire D5_in;
wire D6_in;
wire OCE_in;
wire ODV_in;
wire RST_in;
wire SHIFTIN1_in;
wire SHIFTIN2_in;
wire T1_in;
wire T2_in;
wire T3_in;
wire T4_in;
wire TCE_in;
wire WC_in;
`ifndef XIL_TIMING
assign CLK_in = CLK;
assign CLKDIV_in = CLKDIV;
assign D1_in = D1;
assign D2_in = D2;
assign D3_in = D3;
assign D4_in = D4;
assign D5_in = D5;
assign D6_in = D6;
assign OCE_in = OCE;
assign T1_in = T1;
assign T2_in = T2;
assign T3_in = T3;
assign T4_in = T4;
assign TCE_in = TCE;
assign WC_in = WC;
`endif // `ifndef XIL_TIMING
assign CLKPERF_in = CLKPERF;
// assign CLKPERFDELAY_in = CLKPERFDELAY;
// IR 495397 & IR 499954
// assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
generate
case (ODELAY_USED)
0: assign CLKPERFDELAY_in = CLKPERF;
1: assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
endcase
endgenerate
assign SHIFTIN1_in = SHIFTIN1;
assign SHIFTIN2_in = SHIFTIN2;
assign ODV_in = ODV;
assign RST_in = RST;
buf b_ocbextend (OCBEXTEND, ocbextend_out);
buf b_ofb (OFB, ofb_out);
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tfb (TFB, tfb_out);
buf b_tq (TQ, tq_out);
initial begin
//-------------------------------------------------
//----- DATA_RATE_OQ check
//-------------------------------------------------
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
$finish;
end
endcase // case(DATA_RATE_OQ)
//-------------------------------------------------
//----- DATA_RATE_TQ check
//-------------------------------------------------
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
$finish;
end
endcase // case(DATA_RATE_TQ)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DDR3_DATA check
//-------------------------------------------------
case (DDR3_DATA)
0 : ddr3_data_int <= 1'b0;
1 : ddr3_data_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute DDR3_DATA on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 0 or 1", DDR3_DATA);
$finish;
end
endcase // case(DDR3_DATA)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"DEFAULT" : interface_type_int <= 1'b0;
"MEMORY_DDR3" : interface_type_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, or MEMORY_DDR3", INTERFACE_TYPE);
$finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- ODELAY_USED check
//-------------------------------------------------
case (ODELAY_USED)
// "FALSE" : odelay_used_int <= 1'b0;
// "TRUE" : odelay_used_int <= 1'b1;
0 : odelay_used_int <= 1'b0;
1 : odelay_used_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute ODELAY_USED on OSERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", ODELAY_USED);
$finish;
end
endcase // case(ODELAY_USED)
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
//-------------------------------------------------
//----- TRISTATE_WIDTH check
//-------------------------------------------------
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
$finish;
end
endcase // case(TRISTATE_WIDTH)
//-------------------------------------------------
end // initial begin
//-------------------------------------------------
assign SERDES = 1'b1;
assign SRTYPE = 6'b111111;
assign DDR_CLK_EDGE = 1'b1;
assign WC_DELAY = 1'b0;
assign SELFHEAL = 5'b00000;
assign #0 CLKD = CLK;
assign #0 CLKDIVD = CLKDIV;
assign #10 ofb_out = (ODELAY_USED == 1)? CLKPERF : oq_out;
assign #10 tfb_out = iodelay_state;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
defparam dfront.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam datao.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam dfront.FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
defparam dfront.MXD = 1; // mux delay
defparam dfront.MXR1 = 1; // mux before 2nd rank of flops
// Programmable load generator
defparam dfront.ldgen.ffdcnt = 1;
defparam dfront.ldgen.mxdcnt = 1;
defparam dfront.ldgen.FFRST = 145; // clock to out delay for flop in PLSG
// Tristate output delays
defparam tfront.ffd = 1; // clock to out delay for flip flops
defparam tfront.mxd = 1; // mux delay
defparam trio.ffd = 1; // clock to out delay for flip flops
defparam trio.mxd = 1; // mux delay
//------------------------------------------------------------------
// Instantiate output data section
//------------------------------------------------------------------
rank12d_oserdese1_vlog dfront (.D1(D1_in), .D2(D2_in), .D3(D3_in), .D4(D4_in), .D5(D5_in), .D6(D6_in),
.d2rnk2(d2rnk2),
.SHIFTIN1(SHIFTIN1_in), .SHIFTIN2(SHIFTIN2_in),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .OCE(OCE_in),
.data1(data1), .data2(data2), .SHIFTOUT1(shiftout1_out), .SHIFTOUT2(shiftout2_out),
.DATA_RATE_OQ(data_rate_oq_int), .DATA_WIDTH(data_width_int),
.SERDES_MODE(serdes_mode_int), .load(load),
.IOCLK_GLITCH(ioclkglitch_out),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ));
trif_oserdese1_vlog tfront (.T1(T1_in), .T2(T2_in), .T3(T3_in), .T4(T4_in), .load(load),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.data1(triin1), .data2(triin2));
txbuffer_oserdese1_vlog DDR3FIFO (.iodelay_state(iodelay_state), .qmux1(qmux1), .qmux2(qmux2), .tmux1(tmux1), .tmux2(tmux2),
.d1(data1), .d2(data2), .t1(triin1), .t2(triin2), .trif(tq_out),
.WC(WC_in), .ODV(ODV_in), .extra(ocbextend_out),
.clk(CLK_in), .clkdiv(CLKDIV_in), .bufo(CLKPERFDELAY_in), .bufop(CLKPERF_in), .rst(RST_in),
.ODELAY_USED(odelay_used_int), .DDR3_DATA(ddr3_data_int),
.DDR3_MODE(interface_type_int));
dout_oserdese1_vlog datao (.data1(qmux1), .data2(qmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .OCE(OCE_in),
.OQ(oq_out), .d2rnk2(d2rnk2),
.DATA_RATE_OQ(data_rate_oq_int),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ),
.DDR3_MODE(interface_type_int));
tout_oserdese1_vlog trio (.data1(tmux1), .data2(tmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.TQ(tq_out), .DDR3_MODE(interface_type_int));
`ifndef XIL_TIMING
specify
( CLK => OFB) = (100, 100);
( CLK => OQ) = (100, 100);
( CLK => TQ) = (100, 100);
( CLKPERF => OQ) = (100, 100);
( CLKPERF => TQ) = (100, 100);
( CLKPERFDELAY => OQ) = (100, 100);
( CLKPERFDELAY => TQ) = (100, 100);
( T1 => TQ) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
specify
( CLK => OFB) = (100:100:100, 100:100:100);
( CLK => OQ) = (100:100:100, 100:100:100);
( CLK => TQ) = (100:100:100, 100:100:100);
( CLKPERF => OQ) = (100:100:100, 100:100:100);
( CLKPERF => TQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => OQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => TQ) = (100:100:100, 100:100:100);
( T1 => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, negedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, posedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // OSERDESE1
`timescale 1ps/1ps
/////////////////////////////////////////////////////////
//
// module selfheal_oserdese1_vlog
//
///////////////////////////////////////////////////////
//
// Self healing circuit for Mt Blanc
// This model ONLY works for SERDES operation!!
//
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// dq3 - dq0: Data from load counter
// CLKDIV: Divided clock from PLL
// srint: RESET from load generator
// rst: Set/Reset control
//
//
//
// Outputs:
// SHO: Data output
//
//
//
// Programmable Points
// SELFHEAL: String of 5 bits. 1 as enable and 4 as compare
// Test attributes in model
//
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module selfheal_oserdese1_vlog (dq3, dq2, dq1, dq0,
CLKDIV, srint, rst,
SHO);
input dq3, dq2, dq1, dq0;
input CLKDIV, srint, rst;
output SHO;
reg shr;
reg SHO;
wire clkint;
wire error;
wire rst_in, rst_self_heal;
// Programmable Points
wire [4:0] SELFHEAL;
assign SELFHEAL = 5'b00000;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 10; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 10; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 10; // 60 ps mux delay
parameter MXR1 = 10;
/////////////////////////////////////////
assign clkint = CLKDIV & SELFHEAL[4];
assign error = (((~SELFHEAL[4] ^ SELFHEAL[3]) ^ dq3) | ((~SELFHEAL[4] ^ SELFHEAL[2]) ^ dq2) | ((~SELFHEAL[4] ^ SELFHEAL[1]) ^ dq1) | ((~SELFHEAL[4] ^ SELFHEAL[0]) ^ dq0));
assign rst_in = (~SELFHEAL[4] | ~srint);
assign rst_self_heal = (rst | ~shr);
/////////////////////////////////////////
// Reset Flop
////////////////////////////////////////
always @ (posedge clkint or posedge rst)
begin
begin
if (rst)
begin
shr <= # FFD 1'b0;
end
else begin
shr <= #FFD rst_in;
end
end
end
// Self heal flop
always @ (posedge clkint or posedge rst_self_heal)
begin
begin
if (rst_self_heal)
begin
SHO <= 1'b0;
end
else
begin
SHO <= # FFD error;
end
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module plg_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// c23: Selects between divide by 2 or 3
// c45: Selects between divide by 4 or 5
// c67: Selects between divide by 6 or 7
// sel: Selects which divide function is chosen
// 00:2 or 3, 01:4 or 5, 10:6 or 7, 11:8
// clk: High speed clock from DCM
// clkdiv: Low speed clock from DCM
// rst: Reset
//
//
//
// Outputs:
//
// load: Loads serdes register at terminal count
//
//
// Test attributes:
// INIT_LOADCNT: 4-bits to init counter
// SRTYPE: 1-bit to control synchronous or asynchronous operation
// SELFHEAL: 5-bits to control self healing feature
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module plg_oserdese1_vlog (c23, c45, c67, sel,
clk, clkdiv, rst,
load, IOCLK_GLITCH);
input c23, c45, c67;
input [1:0] sel;
input clk, clkdiv, rst;
output load;
output IOCLK_GLITCH;
wire SRTYPE;
wire [3:0] INIT_LOADCNT;
wire [4:0] SELFHEAL;
assign SRTYPE = 1'b1;
assign INIT_LOADCNT = 4'b0000;
assign SELFHEAL = 5'b00000;
reg q0, q1, q2, q3;
reg qhr, qlr;
reg load, mux;
wire cntrrst;
assign cntrrst = IOCLK_GLITCH | rst;
// Parameters for gate delays
parameter ffdcnt = 1;
parameter mxdcnt = 1;
parameter FFRST = 145; // clock to out delay for flop in PLSG
//////////////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign q3 = INIT_LOADCNT[3];
assign q2 = INIT_LOADCNT[2];
assign q1 = INIT_LOADCNT[1];
assign q0 = INIT_LOADCNT[0];
end
else
begin
deassign q3;
deassign q2;
deassign q1;
deassign q0;
end
end
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk)
begin
if (qhr & !SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (!SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (qhr & SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clkdiv)
begin
if (cntrrst & !SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (!SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// synchronous reset
always @ (posedge clkdiv)
begin
if (cntrrst & SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// High speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clk)
begin
if (cntrrst & !SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (!SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (cntrrst & SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
selfheal_oserdese1_vlog fixcntr (.dq3(q3), .dq2(q2), .dq1(q1), .dq0(q0),
.CLKDIV(clkdiv), .srint(qlr), .rst(rst),
.SHO(IOCLK_GLITCH));
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module rank12d_oserdese1_vlog
//
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
//
////////////////////////////////////////////////////////
//
// Inputs:
// D1: Data input 1
// D2: Data input 2
// D3: Data input 3
// D4: Data input 4
// D5: Data input 5
// D6: Data input 6
// C: High speed clock from DCM
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLKDIV: Low speed divided clock from DCM
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
//
//
//
// Outputs:
// data1: Data output mux for top flop
// data2: Data output mux for bottom flop
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// load: Used for the tristate when combined into a single model
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// DATA_WIDTH: Input data width,
// 4-bits, values can be from 2 to 10
// SERDES_MODE: Denotes master (0) or slave (1)
// SIM_X_INPUT: This attribute is NOT SUPPORTED in this model!!!
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// INIT_ORANK1: Init value for 6 registers in 1st rank (6-bits)
// INIT_ORANK2_PARTIAL: Init value for bottom 4 registers in the 2nd rank (4-bits)
// INIT_LOADCNT: Init value for the load counter (4-bits)
// The other 2 registers in the load counter have init bits, but are
// not supported in this model
// SERDES: Indicates that SERDES mode is chosen
// SLEFHEAL: 5-bit to set self heal circuit
//
//
////////////////////////////////////////////////////////////////////////////////
//
module rank12d_oserdese1_vlog (D1, D2, D3, D4, D5, D6, d2rnk2,
SHIFTIN1, SHIFTIN2,
C, CLKDIV, SR, OCE,
data1, data2, SHIFTOUT1, SHIFTOUT2,
DATA_RATE_OQ, DATA_WIDTH,
SERDES_MODE, load,
IOCLK_GLITCH,
INIT_OQ, SRVAL_OQ);
input D1, D2, D3, D4, D5, D6;
input d2rnk2;
input SHIFTIN1, SHIFTIN2;
input C, CLKDIV, SR, OCE;
input INIT_OQ, SRVAL_OQ;
output data1, data2;
output SHIFTOUT1, SHIFTOUT2;
output load;
output IOCLK_GLITCH;
// Programmable Points
input DATA_RATE_OQ;
input [3:0] DATA_WIDTH;
input SERDES_MODE;
wire DDR_CLK_EDGE, SERDES;
wire [3:0] SRTYPE;
wire [4:0] SELFHEAL;
wire [3:0] INIT_ORANK2_PARTIAL;
wire [5:0] INIT_ORANK1;
assign DDR_CLK_EDGE = 1'b1;
assign SERDES = 1'b1;
assign SRTYPE = 4'b1111;
assign SELFHEAL = 5'b00000;
assign INIT_ORANK2_PARTIAL = 4'b0000;
assign INIT_ORANK1 = 6'b000000;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg data1, data2, data3, data4, data5, data6;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
reg [1:0] sel;
wire C2p, C3;
wire loadint;
wire [3:0] seloq;
wire oqsr, oqrev;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] plgcnt;
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign plgcnt = {DATA_RATE_OQ,DATA_WIDTH};
assign sel1_4 = {SERDES,loadint,DATA_RATE_OQ};
assign sel5_6 = {SERDES,SERDES_MODE,loadint,DATA_RATE_OQ};
assign load = loadint;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign d6rnk2 = INIT_ORANK2_PARTIAL[3];
assign d5rnk2 = INIT_ORANK2_PARTIAL[2];
assign d4rnk2 = INIT_ORANK2_PARTIAL[1];
assign d3rnk2 = INIT_ORANK2_PARTIAL[0];
assign d6r = INIT_ORANK1[5];
assign d5r = INIT_ORANK1[4];
assign d4r = INIT_ORANK1[3];
assign d3r = INIT_ORANK1[2];
assign d2r = INIT_ORANK1[1];
assign d1r = INIT_ORANK1[0];
end
else
begin
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
end
end
/////////////////////////////////////////
// Assign shiftout1 and shiftout2
assign SHIFTOUT1 = d3rnk2 & SERDES_MODE;
assign SHIFTOUT2 = d4rnk2 & SERDES_MODE;
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (!SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
///////////////////////////////////////////////////
// First rank of flops for input data
//////////////////////////////////////////////////
// asynchronous operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (!SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// synchronous operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2)
begin
casex (sel1_4)
3'b100: data1 <= # MXR1 d3rnk2;
3'b110: data1 <= # MXR1 d1r;
3'b101: data1 <= # MXR1 d2rnk2;
3'b111: data1 <= # MXR1 d1r;
default: data1 <= # MXR1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2)
begin
casex (sel1_4)
3'b100: data2 <= # MXR1 d4rnk2;
3'b110: data2 <= # MXR1 d2r;
3'b101: data2 <= # MXR1 d3rnk2;
3'b111: data2 <= # MXR1 d2r;
default: data2 <= # MXR1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2)
begin
casex (sel1_4)
3'b100: data3 <= # MXR1 d5rnk2;
3'b110: data3 <= # MXR1 d3r;
3'b101: data3 <= # MXR1 d4rnk2;
3'b111: data3 <= # MXR1 d3r;
default: data3 <= # MXR1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2)
begin
casex (sel1_4)
3'b100: data4 <= # MXR1 d6rnk2;
3'b110: data4 <= # MXR1 d4r;
3'b101: data4 <= # MXR1 d5rnk2;
3'b111: data4 <= # MXR1 d4r;
default: data4 <= # MXR1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or SHIFTIN1)
begin
casex (sel5_6)
4'b1000: data5 <= # MXR1 SHIFTIN1;
4'b1010: data5 <= # MXR1 d5r;
4'b1001: data5 <= # MXR1 d6rnk2;
4'b1011: data5 <= # MXR1 d5r;
4'b1100: data5 <= # MXR1 1'b0;
4'b1110: data5 <= # MXR1 d5r;
4'b1101: data5 <= # MXR1 d6rnk2;
4'b1111: data5 <= # MXR1 d5r;
default: data5 <= # MXR1 SHIFTIN1;
endcase
end
always @ (sel5_6 or D6 or d6r or SHIFTIN1 or SHIFTIN2)
begin
casex (sel5_6)
4'b1000: data6 <= # MXR1 SHIFTIN2;
4'b1010: data6 <= # MXR1 d6r;
4'b1001: data6 <= # MXR1 SHIFTIN1;
4'b1011: data6 <= # MXR1 d6r;
4'b1100: data6 <= # MXR1 1'b0;
4'b1110: data6 <= # MXR1 d6r;
4'b1101: data6 <= # MXR1 1'b0;
4'b1111: data6 <= # MXR1 d6r;
default: data6 <= # MXR1 SHIFTIN2;
endcase
end
// instantiate programmable load generator
plg_oserdese1_vlog ldgen (.c23(c23), .c45(c45), .c67(c67), .sel(sel),
.clk(C), .clkdiv(CLKDIV), .rst(SR),
.load(loadint), .IOCLK_GLITCH(IOCLK_GLITCH));
// Set value of counter in programmable load generator
always @ (plgcnt or c23 or c45 or c67 or sel)
begin
casex (plgcnt)
5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default: $display("DATA_WIDTH %b and DATA_RATE_OQ %b at %t is an illegal value", DATA_WIDTH, DATA_RATE_OQ, $time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module trif_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// T1, T2, T3, T4: tristate inputs
// load: Programmable load generator output
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// C, C2: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// CLKDIV: Low speed clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module trif_oserdese1_vlog (T1, T2, T3, T4, load,
C, CLKDIV, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
data1, data2);
input T1, T2, T3, T4, load;
input C, CLKDIV, SR, TCE;
input [1:0] TRISTATE_WIDTH;
input [1:0] DATA_RATE_TQ;
input INIT_TQ, SRVAL_TQ;
output data1, data2;
wire DDR_CLK_EDGE;
wire [3:0] INIT_TRANK1;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
assign INIT_TRANK1 = 4'b0000;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg data1, data2;
reg sdata_edge, odata_edge, ddr_data;
wire C2p, C3;
wire load;
wire [6:0] tqsel;
wire [4:0] sel;
assign sel = {load,DATA_RATE_TQ,TRISTATE_WIDTH};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign t1r = INIT_TRANK1[0];
assign t2r = INIT_TRANK1[1];
assign t3r = INIT_TRANK1[2];
assign t4r = INIT_TRANK1[3];
end
else
begin
deassign t1r;
deassign t2r;
deassign t3r;
deassign t4r;
end
end
// First rank of flops
// asynchronous reset operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (!SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// synchronous reset operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// Data Muxs for tristate otuput signals
always @ (sel or T1 or t1r or t3r)
begin
casex (sel)
5'b00000: data1 <= # mxd T1;
5'b10000: data1 <= # mxd T1;
5'bX0000: data1 <= # mxd T1;
5'b00100: data1 <= # mxd T1;
5'b10100: data1 <= # mxd T1;
5'bX0100: data1 <= # mxd T1;
5'b01001: data1 <= # mxd T1;
5'b11001: data1 <= # mxd T1;
5'b01010: data1 <= # mxd t3r;
5'b11010: data1 <= # mxd t1r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel or T2 or t2r or t4r)
begin
casex (sel)
5'b00000: data2 <= # mxd T2;
5'b00100: data2 <= # mxd T2;
5'b10000: data2 <= # mxd T2;
5'b10100: data2 <= # mxd T2;
5'bX0000: data2 <= # mxd T2;
5'bX0100: data2 <= # mxd T2;
5'b00X00: data2 <= # mxd T2;
5'b10X00: data2 <= # mxd T2;
5'bX0X00: data2 <= # mxd T2;
5'b01001: data2 <= # mxd T2;
5'b11001: data2 <= # mxd T2;
5'bX1001: data2 <= # mxd T2;
5'b01010: data2 <= # mxd t4r;
5'b11010: data2 <= # mxd t2r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module txbuffer_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// FIFO and Control circuit for OSERDES
module txbuffer_oserdese1_vlog (iodelay_state, qmux1, qmux2, tmux1, tmux2,
d1, d2, t1, t2, trif,
WC, ODV, extra,
clk, clkdiv, bufo, bufop, rst,
ODELAY_USED, DDR3_DATA,
DDR3_MODE);
input d1, d2, t1, t2;
input trif;
input WC, ODV;
input rst;
input clk, clkdiv, bufo, bufop;
input ODELAY_USED, DDR3_DATA;
input DDR3_MODE;
output iodelay_state, extra;
output qmux1, qmux2, tmux1, tmux2;
wire WC_DELAY;
assign WC_DELAY = 1'b0;
wire rd_gap1;
wire rst_bufo_p, rst_bufg_p;
wire rst_bufo_rc, rst_bufg_wc, rst_cntr, rst_bufop_rc;
wire [1:0] qwc, qrd;
wire bufo_out;
fifo_tdpipe_oserdese1_vlog data1 (.muxout(inv_qmux1), .din(~d1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog data2 (.muxout(inv_qmux2), .din(~d2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris1 (.muxout(inv_tmux1), .din(~t1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris2 (.muxout(inv_tmux2), .din(~t2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
wire qmux1 = ~inv_qmux1;
wire qmux2 = ~inv_qmux2;
wire tmux1 = ~inv_tmux1;
wire tmux2 = ~inv_tmux2;
fifo_reset_oserdese1_vlog rstckt (.rst_bufo_p(rst_bufo_p), .rst_bufo_rc(rst_bufo_rc),
.rst_bufg_p(rst_bufg_p), .rst_bufg_wc(rst_bufg_wc),
.rst_cntr(rst_cntr),
.bufg_clk(clk), .bufo_clk(bufo), .clkdiv(clkdiv), .rst(rst),
.divide_2(WC_DELAY), .bufop_clk(bufop), .rst_bufop_rc(rst_bufop_rc)
);
fifo_addr_oserdese1_vlog addcntr (.qwc(qwc), .qrd(qrd), .rd_gap1(rd_gap1), .rst_bufg_wc(rst_bufg_wc), .rst_bufo_rc(rst_bufo_rc), .bufg_clk(clk), .bufo_clk(bufo),
.data(DDR3_DATA), .extra(extra), .rst_bufop_rc(rst_bufop_rc), .bufop_clk(bufop)
);
iodlyctrl_npre_oserdese1_vlog idlyctrl (.iodelay_state(iodelay_state), .bufo_out(bufo_out), .rst_cntr(rst_cntr),
.wc(WC), .trif(trif),
.rst(rst_bufg_p), .bufg_clk(clk), .bufo_clk(bufo), .bufg_clkdiv(clkdiv),
.ddr3_dimm(ODELAY_USED), .wl6(WC_DELAY)
);
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_tdpipe_oserdese1_vlog
//
////////////////////////////////////////////////////////
// FIFO for write path
module fifo_tdpipe_oserdese1_vlog (muxout, din, qwc, qrd,
rd_gap1,
bufg_clk, bufo_clk, rst_bufo_p, rst_bufg_p,
DDR3_DATA, extra, ODV, DDR3_MODE
);
input din;
input [1:0] qwc, qrd;
input rd_gap1;
input rst_bufo_p, rst_bufg_p;
input bufg_clk, bufo_clk;
input DDR3_DATA, ODV;
input extra;
input DDR3_MODE;
output muxout;
reg muxout;
reg qout1, qout2;
reg qout_int, qout_int2;
reg [4:1] fifo;
reg cin1;
reg omux;
wire [2:0] sel;
reg pipe1, pipe2;
wire selqoi, selqoi2;
wire [2:0] selmuxout;
// 4 flops that make up the basic FIFO. They are all clocked
// off of fast BUFG. The first flop is the top flop in the chain.
// The CE input is used to mux the inputs. If the flop is selected,
// CE is high and it takes data from the output of the mux. If the
// flop is not selected, it retains its data.
always @ (posedge bufg_clk or posedge rst_bufg_p)
begin
if (rst_bufg_p)
begin
fifo <= #10 4'b0000;
end
else if (!qwc[1] & !qwc[0])
begin
fifo <= #10 {fifo[4:2],din};
end
else if (!qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4:3],din,fifo[1]};
end
else if (qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4],din,fifo[2:1]};
end
else if (qwc[1] & !qwc[0])
begin
fifo <= #10 {din,fifo[3:1]};
end
end
// Capture stage top
// This is the top flop of the "3 flops" for ODDR. This flop, along with the read
// counter will be clocked off of bufo. A 4:1 mux wil decode the outputs of the
// read counter and load the write data. A subsequent 2:1 mux will decode between
// the fifo and the legacy operation
// OMUX
always @ (qrd or fifo)
begin
case (qrd)
2'b00: omux <= #10 fifo[1];
2'b01: omux <= #10 fifo[2];
2'b10: omux <= #10 fifo[4];
2'b11: omux <= #10 fifo[3];
default: omux <= #10 fifo[1];
endcase
end
always @ (posedge bufo_clk or posedge rst_bufo_p)
begin
if (rst_bufo_p)
begin
qout_int <= #10 1'b0;
qout_int2 <= #10 1'b0;
end
else
begin
qout_int <= #10 omux;
qout_int2 <= #10 qout_int;
end
end
assign #10 selqoi = ODV | rd_gap1;
always @ (selqoi or qout_int or omux)
begin
case(selqoi)
1'b0: qout1 <= #10 omux;
1'b1: qout1 <= #10 qout_int;
default: qout1 <= #10 omux;
endcase
end
assign #10 selqoi2 = ODV & rd_gap1;
always @ (selqoi2 or qout_int2 or qout_int)
begin
case(selqoi2)
1'b0: qout2 <= #10 qout_int;
1'b1: qout2 <= #10 qout_int2;
default qout2 <= #10 qout_int;
endcase
end
assign #14 selmuxout = {DDR3_MODE,DDR3_DATA,extra};
always @ (selmuxout or din or omux or qout1 or qout2)
begin
case (selmuxout)
3'b000: muxout = #1 din;
3'b001: muxout = #1 din;
3'b010: muxout = #1 din;
3'b011: muxout = #1 din;
3'b100: muxout = #1 omux;
3'b101: muxout = #1 omux;
3'b110: muxout = #1 qout1;
3'b111: muxout = #1 qout2;
default: muxout = #10 din;
endcase
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_reset_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// TX FIFO reset
//
// This design performs 2 functions. One function is to reset all the
// flops in the TX FIFO. The other function is to respond to the signal
// rst_cntr. This signal comes from iodlyctrl and will be used to initiate an
// orderly transition to switch the DQ/DQS I/O from and read to a write.
// This process is required only for DDR3 DIMM support because the IODELAY
// is used for both the inputs and the outputs. The signal from the
// squelch circuit is a present fabric output. An additional input
// indicating that a write command was issued will be
// required for all I/O to support this signal.
//
// This design uses an asynchronous reset to reset all flops. After the
// reset is disabled, a 0 is propagated through the pipe stages to terminate
// the reset. The first 2 flops run off of the clkdiv domain. Their output
// feeds a latch to cross between the clkdiv and bufg_clk domain. The pipe
// stage for the bufg_clk domain is 3 deep, where the last flop is the
// reset signal for the bufg_clk domain. The 2nd flop of the bufg_clk pipe
// is fed to 2 flops that are in the bufo_clk domain. The 2 flops are
// to resolve metastability between the 2 clock domains.
//
// The circuit to enable an orderly transition from read to write uses the
// PREAMBLE_SYNCHED output of a portion of the squelch circuit. This pulse
// will initiate the reset sequence and also generate an enable which will
// switch the IODELAY from an IDELAY to an ODELAY. Timing is as specified in
// the "State of the Union" presentation.
//
//
module fifo_reset_oserdese1_vlog (rst_bufo_p, rst_bufo_rc,
rst_bufg_p, rst_bufg_wc,
rst_cntr,
bufg_clk, bufo_clk, clkdiv, rst,
divide_2, bufop_clk, rst_bufop_rc
);
input rst_cntr;
input rst;
input bufg_clk, bufo_clk, clkdiv;
input bufop_clk;
// Memory cell input to support divide by 1 operation
input divide_2;
output rst_bufo_p, rst_bufo_rc;
output rst_bufg_p, rst_bufg_wc;
output rst_bufop_rc;
reg [1:0] clkdiv_pipe;
reg bufg_pipe;
reg rst_cntr_reg;
reg [2:0] bufo_rst_p, bufo_rst_rc;
reg [1:0] bufop_rst_rc;
reg [1:0] bufg_rst_p, bufg_rst_wc;
wire bufg_clkdiv_latch, ltint1, ltint2, ltint3;
wire latch_in;
// 2 stage pipe for clkdiv domain to allow user to properly
// time everything
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
rst_cntr_reg <= #10 1'b0;
end
else
begin
rst_cntr_reg <= #10 rst_cntr;
end
end
always @ (posedge clkdiv or posedge rst)
begin
if (rst)
begin
clkdiv_pipe <= #10 2'b11;
end
else
begin
clkdiv_pipe <= #10 {clkdiv_pipe[0],1'b0};
end
end
// Latch to compensate for clkdiv and bufg_clk clock skew
// Built of actual gates
assign #1 latch_in = clkdiv_pipe[1];
assign #1 bufg_clkdiv_latch = !(ltint1 && ltint3);
assign #1 ltint1 = !(latch_in && bufg_clk);
assign #1 ltint2 = !(ltint1 && bufg_clk);
assign #1 ltint3 = !(bufg_clkdiv_latch && ltint2);
// BUFG flop to register latch signal
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_pipe <= #10 1'b1;
end
else
begin
bufg_pipe <= #10 bufg_clkdiv_latch;
end
end
// BUFG clock domain resests
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_rst_p <= #10 2'b11;
end
else
begin
bufg_rst_p <= #10 {bufg_rst_p[0],bufg_pipe};
end
end
always @ (posedge bufg_clk or posedge rst_cntr or posedge rst)
begin
if (rst || rst_cntr)
begin
bufg_rst_wc <= #10 2'b11;
end
else
begin
bufg_rst_wc <= #10 {bufg_rst_wc[0],bufg_pipe};
end
end
// BUFO clock domain Resets
always @ (posedge bufo_clk or posedge rst)
begin
if (rst)
begin
bufo_rst_p <= #10 3'b111;
end
else
begin
bufo_rst_p <= #10 {bufo_rst_p[1:0],bufg_pipe};
end
end
always @ (posedge bufo_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufo_rst_rc <= #10 3'b111;
end
else
begin
bufo_rst_rc <= #10 {bufo_rst_rc[1:0],bufg_pipe};
end
end
always @ (posedge bufop_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufop_rst_rc <= #10 2'b11;
end
else
begin
bufop_rst_rc <= #10 {bufop_rst_rc[0],bufg_pipe};
end
end
// final reset assignments
assign rst_bufo_rc = bufo_rst_rc[1];
assign rst_bufo_p = bufo_rst_p[1];
assign rst_bufop_rc = bufop_rst_rc[1];
assign rst_bufg_wc = bufg_rst_wc[1];
assign rst_bufg_p = bufg_rst_p[1];
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_addr_oserdese1_vlog
//
////////////////////////////////////////////////////////
// Read and Write address generators for TX FIFO
//
// This circuit contains 2 greycode read and write address generators
// that will be used with the TX FIFO. Both counters generate a
// count sequence of 00 -> 01 -> 11 -> 10 -> 00.
module fifo_addr_oserdese1_vlog (qwc, qrd, rd_gap1, rst_bufg_wc, rst_bufo_rc, bufg_clk, bufo_clk,
data, extra, rst_bufop_rc, bufop_clk
);
input bufg_clk, bufo_clk;
input rst_bufo_rc, rst_bufg_wc;
input rst_bufop_rc;
input data; // mc to tell if I/O is DDR3 DQ or DQS
input bufop_clk;
output qwc, qrd;
output rd_gap1, extra;
reg [1:0] qwc;
reg [1:0] qrd;
reg stop_rd, rd_gap1, extra;
reg rd_cor, rd_cor_cnt, rd_cor_cnt1;
wire qwc0_latch, qwc1_latch;
wire li01, li02, li03;
wire li11, li12, li13;
wire qwc0_latchn, qwc1_latchn;
wire li01n, li02n, li03n;
wire li11n, li12n, li13n;
reg stop_rdn, rd_cor_cntn, rd_cor_cnt1n, stop_rc;
reg [1:0] qwcd;
reg [1:0] qrdd;
reg stop_rdd, rd_gap1d, extrad;
reg rd_cord, rd_cor_cntd, rd_cor_cnt1d;
wire qwcd0_latch, qwcd1_latch;
wire li01d, li02d, li03d;
wire li11d, li12d, li13d;
// Write counter
// The write counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The write counter is initialized
// to 11 and the read counter will be initialized to 00. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The write counter is clocked off of the bufg clock
always @ (posedge bufg_clk or posedge rst_bufg_wc)
begin
if (rst_bufg_wc)
begin
qwc <= # 10 2'b11;
end
else if (qwc[1] ^ qwc[0])
begin
qwc[1] <= # 10 ~qwc[1];
qwc[0] <= # 10 qwc[0];
end
else
begin
qwc[1] <= # 10 qwc[1];
qwc[0] <= # 10 ~qwc[0];
end
end
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
qrd <= # 10 2'b00;
end
else if (stop_rd && !data)
begin
qrd <= #10 qrd;
end
else if (qrd[1] ^ qrd[0])
begin
qrd[1] <= # 10 ~qrd[1];
qrd[0] <= # 10 qrd[0];
end
else
begin
qrd[1] <= # 10 qrd[1];
qrd[0] <= # 10 ~qrd[0];
end
end
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
rd_gap1 <= # 10 1'b0;
end
// else if ((qwc1_latch && qwc0_latch) && (qrd[0] ^ qrd[1]))
else if ((qwc1_latch && qwc0_latch) && (qrd[0]))
begin
rd_gap1 <= # 10 1'b1;
end
else
begin
rd_gap1 <= # 10 rd_gap1;
end
end
// Looking for 11
assign #1 qwc0_latch = !(li01 & li03);
assign #1 li01 = !(qwc[0] & bufo_clk);
assign #1 li02 = !(li01 & bufo_clk);
assign #1 li03 = !(qwc0_latch & li02);
assign #1 qwc1_latch = !(li11 & li13);
assign #1 li11 = !(qwc[1] & bufo_clk);
assign #1 li12 = !(li11 & bufo_clk);
assign #1 li13 = !(qwc1_latch & li12);
// The following counter is to match the control counter to see if the
// read counter did a hold after reset. This knowledge will enable the
// computation of the 'extra' output. This in turn can add the
// proper number of pipe stages to the output. The circuit must use
// the output of BUFO and not be modified by ODELAY. This is because
// the control pins PP clock was not modified by BUFO. If the
// control pins PP clock was modified by BUFO, the reset must be done
// with this in mind.
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
qrdd <= # 10 2'b00;
end
else if (qrdd[1] ^ qrdd[0])
begin
qrdd[1] <= # 10 ~qrdd[1];
qrdd[0] <= # 10 qrdd[0];
end
else
begin
qrdd[1] <= # 10 qrdd[1];
qrdd[0] <= # 10 ~qrdd[0];
end
end
// Looking for 11
assign #1 qwcd0_latch = !(li01d & li03d);
assign #1 li01d = !(qwc[0] & bufop_clk);
assign #1 li02d = !(li01d & bufop_clk);
assign #1 li03d = !(qwcd0_latch & li02d);
assign #1 qwcd1_latch = !(li11d & li13d);
assign #1 li11d = !(qwc[1] & bufop_clk);
assign #1 li12d = !(li11d & bufop_clk);
assign #1 li13d = !(qwcd1_latch & li12d);
// Circuit to fix read address counters in non data pins
always @ (posedge bufop_clk or posedge rst_bufo_rc)
begin
if (rst_bufop_rc)
begin
stop_rd <= # 10 1'b0;
rd_cor_cnt <= #10 1'b0;
rd_cor_cnt1 <= #10 1'b0;
end
else if (((qwcd1_latch && qwcd0_latch) && (qrdd[0] ^ qrdd[1]) && !rd_cor_cnt1))
begin
stop_rd <= #10 1'b1;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
else
begin
stop_rd <= #10 1'b0;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
end
// Circuit to inform data if control counters habe been fixed
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
extra <= #10 1'b0;
end
else if (stop_rd)
begin
extra <= #10 1'b1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module iodlyctrl_npre_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Circuit to automatically switch IODELAY from IDELAY to ODELAY using knowledge
// of write command. This circuit forces the user to wait 3 extra CLK/CLK# cycles
// when performing a read to write turnaround. The JEDEC DDR3 spec states that
// the turnaround can be done in 2 clock cycles. This circuit requires 5 clock
// cycles.
// This circuit is only used for a DDR3 appplication that uses DIMMs
module iodlyctrl_npre_oserdese1_vlog (iodelay_state, bufo_out, rst_cntr,
wc, trif,
rst, bufg_clk, bufo_clk, bufg_clkdiv,
ddr3_dimm, wl6
);
input wc;
input trif;
input rst;
input bufo_clk, bufg_clk, bufg_clkdiv;
input ddr3_dimm, wl6;
output iodelay_state, rst_cntr;
output bufo_out;
reg qw0cd, qw1cd;
reg turn, turn_p1;
reg rst_cntr;
reg w_to_w;
reg [2:0] wtw_cntr;
reg cmd0, cmd0_n6, cmd0_6, cmd1;
wire wr_cmd0;
wire lt0int1, lt0int2, lt0int3;
wire lt1int1, lt1int2, lt1int3;
wire latch_in;
reg qwcd;
assign bufo_out = bufo_clk;
// create turn signal for IODELAY
assign iodelay_state = (trif && ~w_to_w) & ((~turn && ~turn_p1) || ~ddr3_dimm);
// Registers to detect write command
// Registers using bufg clkdiv
always @ (posedge bufg_clkdiv)
begin
if (rst)
begin
qwcd <= #10 0;
end
else
begin
qwcd <= #10 wc;
end
end
// Latch to allow skew between CLK and CLKDIV from BUFGs
assign #1 wr_cmd0 = !(lt0int1 && lt0int3);
assign #1 lt0int1 = !(qwcd && bufg_clk);
assign #1 lt0int2 = !(lt0int1 && bufg_clk);
assign #1 lt0int3 = !(wr_cmd0 && lt0int2);
always @ (posedge bufg_clk)
begin
if (rst)
begin
cmd0_n6 <= #10 1'b0;
cmd0_6 <= #10 1'b0;
end
else
begin
cmd0_n6 <= #10 wr_cmd0;
cmd0_6 <= #10 cmd0_n6;
end
end
// mux to add extra pipe stage for WL = 6
always @ (cmd0_n6 or wl6 or cmd0_6)
begin
case (wl6)
1'b0: cmd0 <= #10 cmd0_n6;
1'b1: cmd0 <= #10 cmd0_6;
default: cmd0 <= #10 cmd0_n6;
endcase
end
// Turn IODELAY and reset FIFO read/write counters
//always @ (posedge bufg_clk)
// begin
// if (rst)
//
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (w_to_w)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else if (cmd0 && !turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b1;
// end
// else if (~trif)
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
turn <= #10 1'b0;
end
else
begin
turn <= #10 (w_to_w || (cmd0 && ~turn) ||
(~wtw_cntr[2] && turn));
end
end
begin
if (rst)
begin
rst_cntr <= #10 1'b0;
end
else
begin
rst_cntr <= #10 (~w_to_w && (cmd0 && ~turn));
end
end
end
always @ (posedge bufg_clk)
begin
if (rst)
begin
turn_p1 <= #10 1'b0;
end
else
begin
turn_p1 <= #10 turn;
end
end
// Detect multiple write commands and don"t turn IODELAY
//always @ (posedge bufg_clk)
// begin
// if (rst)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (cmd0 && turn_p1)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 3'b000;
// end
// else if (wtw_cntr == 3'b101)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (w_to_w)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 wtw_cntr + 1;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
w_to_w <= #10 1'b0;
end
else
begin
w_to_w <= #10 ((cmd0 && turn_p1) ||
(w_to_w && (~wtw_cntr[2] || ~wtw_cntr[1])));
end
end
end
always @ (posedge bufg_clk)
begin
if (!(w_to_w || turn) || (cmd0 && turn_p1))
begin
wtw_cntr <= #10 3'b000;
end
else if (w_to_w || turn_p1)
begin
wtw_cntr <= #10 wtw_cntr + 1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// MODULE dout_oserdese1_vlog
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
/////////////////////////////////////////////////////////
//
// Inputs:
// data1: Data from FIFO
// data2: Data input FIFO
// CLK: High speed clock from DCM
// BUFO: Clock from performance path
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
//
//
//
// Outputs:
// OQ: Data output
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// INIT_OQ: Init OQ output "flop"
// SRVAL_OQ: This bit to controls value of SR input.
// Only the last 3 flops (d1rnk2, d2rnk2 and d2nrnk2)
// are affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only respond to
// this pin as a reset. Their function cannot be
// changed. SR is '1' for SET and '0' for RESET.
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// DDR_CLK_EDGE: Controls use of 2 or 3 flops for single case. Default to 1 for
// SERDES operation
//
//
///////////////////////////////////////////////////////////////////////////////
//
module dout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, OCE,
OQ, d2rnk2,
DATA_RATE_OQ,
INIT_OQ, SRVAL_OQ,
DDR3_MODE);
input data1, data2;
input CLK, SR, OCE;
input BUFO;
input INIT_OQ, SRVAL_OQ;
input DDR3_MODE;
output OQ;
output d2rnk2;
// Programmable Points
input DATA_RATE_OQ;
wire DDR_CLK_EDGE;
wire [3:0] SRTYPE;
assign DDR_CLK_EDGE = 1'b1;
assign SRTYPE = 4'b1111;
reg d1rnk2, d2rnk2, d2nrnk2;
reg OQ;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
wire C;
wire C2p, C3;
wire [3:0] seloq;
wire oqsr, oqrev;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign OQ = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
end
else
begin
deassign OQ;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
end
end
/////////////////////////////////////////
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (C or C3 or d1rnk2 or d2nrnk2)
begin
sdata_edge <= # MXD (d1rnk2 & C) | (d2nrnk2 & C3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @ (C or d1rnk2 or d2rnk2)
begin
case (C)
1'b0: odata_edge <= # MXD d2rnk2;
1'b1: odata_edge <= # MXD d1rnk2;
default: odata_edge <= # MXD d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # MXD (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or ddr_data or OQ)
begin
casex (seloq)
4'bXX01: OQ <= # MXD 1'b1;
4'bXX10: OQ <= # MXD 1'b0;
4'bXX11: OQ <= # MXD 1'b0;
4'bX000: OQ <= # MXD ddr_data;
4'bX100: OQ <= # MXD d1rnk2;
default: OQ <= # MXD ddr_data;
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module tout_oserdese1_vlog
//
// Tristate Output cell for Mt Blanc
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// data1, data2: tristate inputs
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLK: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// BUFO: Performance path clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module tout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
TQ, DDR3_MODE);
input data1, data2;
input CLK, BUFO, SR, TCE;
input [1:0] DATA_RATE_TQ, TRISTATE_WIDTH;
input INIT_TQ, SRVAL_TQ;
input DDR3_MODE;
output TQ;
wire DDR_CLK_EDGE;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
reg TQ;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg sdata_edge, odata_edge, ddr_data;
wire C;
wire C2p, C3;
wire load;
wire [5:0] tqsel;
wire tqsr, tqrev;
wire [4:0] sel;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign tqsr = (!SRTYPE[0] & SR & !SRVAL_TQ) | (!SRTYPE[0] & SRVAL_TQ);
assign tqrev = (!SRTYPE[0] & SR & SRVAL_TQ) | (!SRTYPE[0] & !SRVAL_TQ);
assign tqsel = {TCE,DATA_RATE_TQ,TRISTATE_WIDTH,tqsr};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign TQ = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
end
else
begin
deassign TQ;
deassign qt1;
deassign qt2;
deassign qt2n;
end
end
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// Logic to generate same edge data from qt1, qt3;
always @ (C or C3 or qt1 or qt2n)
begin
sdata_edge <= # mxd (qt1 & C) | (qt2n & C3);
end
// Mux to create opposite edge DDR function
always @ (C or qt1 or qt2)
begin
case (C)
1'b0: odata_edge <= # mxd qt2;
1'b1: odata_edge <= # mxd qt1;
default: odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # mxd (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs.
always @ (tqsel or data1 or ddr_data or qt1 or TQ)
begin
casex (tqsel)
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX0000X: TQ <= # mxd data1;
// 6'b001000: TQ <= # mxd TQ;
// 6'b010010: TQ <= # mxd TQ;
// 6'b010100: TQ <= # mxd TQ;
6'bX01000: TQ <= # mxd qt1;
6'bX10010: TQ <= # mxd ddr_data;
6'bX10100: TQ <= # mxd ddr_data;
default: TQ <= # mxd ddr_data;
endcase
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OSERDESE2.v 0000664 0000000 0000000 00000042725 12327044266 0022727 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer Virtex7
// /___/ /\ Filename : OSERDESE2.v
// \ \ / \ Timestamp : Fri Jan 29 14:59:32 PST 2010
// \___\/\___\
//
// Revision:
// 01/29/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDESE2 (
OFB,
OQ,
SHIFTOUT1,
SHIFTOUT2,
TBYTEOUT,
TFB,
TQ,
CLK,
CLKDIV,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
OCE,
RST,
SHIFTIN1,
SHIFTIN2,
T1,
T2,
T3,
T4,
TBYTEIN,
TCE
);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter [0:0] IS_D3_INVERTED = 1'b0;
parameter [0:0] IS_D4_INVERTED = 1'b0;
parameter [0:0] IS_D5_INVERTED = 1'b0;
parameter [0:0] IS_D6_INVERTED = 1'b0;
parameter [0:0] IS_D7_INVERTED = 1'b0;
parameter [0:0] IS_D8_INVERTED = 1'b0;
parameter [0:0] IS_T1_INVERTED = 1'b0;
parameter [0:0] IS_T2_INVERTED = 1'b0;
parameter [0:0] IS_T3_INVERTED = 1'b0;
parameter [0:0] IS_T4_INVERTED = 1'b0;
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter TBYTE_CTL = "FALSE";
parameter TBYTE_SRC = "FALSE";
parameter integer TRISTATE_WIDTH = 4;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output OFB;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TBYTEOUT;
output TFB;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input D7;
input D8;
input OCE;
input RST;
input SHIFTIN1;
input SHIFTIN2;
input T1;
input T2;
input T3;
input T4;
input TBYTEIN;
input TCE;
reg DATA_RATE_OQ_BINARY;
reg DATA_WIDTH_BINARY;
reg LOC_BINARY;
reg [0:0] INIT_OQ_BINARY;
reg [0:0] INIT_TQ_BINARY;
reg [0:0] SERDES_MODE_BINARY;
reg [0:0] SRVAL_OQ_BINARY;
reg [0:0] SRVAL_TQ_BINARY;
reg [0:0] TBYTE_CTL_BINARY;
reg [0:0] TBYTE_SRC_BINARY;
reg [0:0] TRISTATE_WIDTH_BINARY;
reg [5:0] DATA_RATE_TQ_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
wire OFB_OUT;
wire OQ_OUT;
wire SHIFTOUT1_OUT;
wire SHIFTOUT2_OUT;
wire TBYTEOUT_OUT;
wire TFB_OUT;
wire TQ_OUT;
wire CLKDIV_IN;
wire CLK_IN;
wire D1_IN;
wire D2_IN;
wire D3_IN;
wire D4_IN;
wire D5_IN;
wire D6_IN;
wire D7_IN;
wire D8_IN;
wire OCE_IN;
wire RST_IN;
wire SHIFTIN1_IN;
wire SHIFTIN2_IN;
wire T1_IN;
wire T2_IN;
wire T3_IN;
wire T4_IN;
wire TBYTEIN_IN;
wire TCE_IN;
wire CLKDIV_INDELAY;
wire CLK_INDELAY;
wire D1_INDELAY;
wire D2_INDELAY;
wire D3_INDELAY;
wire D4_INDELAY;
wire D5_INDELAY;
wire D6_INDELAY;
wire D7_INDELAY;
wire D8_INDELAY;
wire OCE_INDELAY;
wire RST_INDELAY;
wire SHIFTIN1_INDELAY;
wire SHIFTIN2_INDELAY;
wire T1_INDELAY;
wire T2_INDELAY;
wire T3_INDELAY;
wire T4_INDELAY;
wire TBYTEIN_INDELAY;
wire TCE_INDELAY;
wire delay_OFB,OFB_out;
wire delay_OQ,OQ_out;
wire delay_SHIFTOUT1,SHIFTOUT1_out;
wire delay_SHIFTOUT2,SHIFTOUT2_out;
wire delay_TBYTEOUT,TBYTEOUT_out;
wire delay_TFB,TFB_out;
wire delay_TQ,TQ_out;
wire delay_CLK,CLK_in;
wire delay_CLKDIV,CLKDIV_in;
wire delay_D1,D1_in;
wire delay_D2,D2_in;
wire delay_D3,D3_in;
wire delay_D4,D4_in;
wire delay_D5,D5_in;
wire delay_D6,D6_in;
wire delay_D7,D7_in;
wire delay_D8,D8_in;
wire delay_OCE,OCE_in;
wire delay_RST,RST_in;
wire delay_SHIFTIN1,SHIFTIN1_in;
wire delay_SHIFTIN2,SHIFTIN2_in;
wire delay_T1,T1_in;
wire delay_T2,T2_in;
wire delay_T3,T3_in;
wire delay_T4,T4_in;
wire delay_TBYTEIN,TBYTEIN_in;
wire delay_TCE,TCE_in;
assign #(out_delay) OFB = delay_OFB;
assign #(out_delay) OQ = delay_OQ;
assign #(out_delay) SHIFTOUT1 = delay_SHIFTOUT1;
assign #(out_delay) SHIFTOUT2 = delay_SHIFTOUT2;
assign #(out_delay) TBYTEOUT = delay_TBYTEOUT;
assign #(out_delay) TFB = delay_TFB;
assign #(out_delay) TQ = delay_TQ;
assign delay_OFB = OFB_out;
assign delay_OQ = OQ_out;
assign delay_SHIFTOUT1 = SHIFTOUT1_out;
assign delay_SHIFTOUT2 = SHIFTOUT2_out;
assign delay_TBYTEOUT = TBYTEOUT_out;
assign delay_TFB = TFB_out;
assign delay_TQ = TQ_out;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CLKDIV = CLKDIV;
assign #(INCLK_DELAY) delay_CLK = CLK;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_OCE = OCE;
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SHIFTIN1 = SHIFTIN1;
assign #(in_delay) delay_SHIFTIN2 = SHIFTIN2;
assign #(in_delay) delay_T1 = T1;
assign #(in_delay) delay_T2 = T2;
assign #(in_delay) delay_T3 = T3;
assign #(in_delay) delay_T4 = T4;
assign #(in_delay) delay_TBYTEIN = TBYTEIN;
assign #(in_delay) delay_TCE = TCE;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
// assign delay_RST = RST;
assign delay_SHIFTIN1 = SHIFTIN1;
assign delay_SHIFTIN2 = SHIFTIN2;
assign delay_TBYTEIN = TBYTEIN;
`endif
assign CLKDIV_in = IS_CLKDIV_INVERTED ^ delay_CLKDIV;
assign CLK_in = IS_CLK_INVERTED ^ delay_CLK;
assign D1_in = IS_D1_INVERTED ^ delay_D1;
assign D2_in = IS_D2_INVERTED ^ delay_D2;
assign D3_in = IS_D3_INVERTED ^ delay_D3;
assign D4_in = IS_D4_INVERTED ^ delay_D4;
assign D5_in = IS_D5_INVERTED ^ delay_D5;
assign D6_in = IS_D6_INVERTED ^ delay_D6;
assign D7_in = IS_D7_INVERTED ^ delay_D7;
assign D8_in = IS_D8_INVERTED ^ delay_D8;
assign OCE_in = delay_OCE;
assign RST_in = delay_RST;
assign SHIFTIN1_in = delay_SHIFTIN1;
assign SHIFTIN2_in = delay_SHIFTIN2;
assign T1_in = IS_T1_INVERTED ^ delay_T1;
assign T2_in = IS_T2_INVERTED ^ delay_T2;
assign T3_in = IS_T3_INVERTED ^ delay_T3;
assign T4_in = IS_T4_INVERTED ^ delay_T4;
assign TBYTEIN_in = delay_TBYTEIN;
assign TCE_in = delay_TCE;
assign SHIFTIN1_in = delay_SHIFTIN1;
assign SHIFTIN2_in = delay_SHIFTIN2;
assign TBYTEIN_in = delay_TBYTEIN;
initial begin
//-------------------------------------------------
//----- DATA_RATE_OQ check
//-------------------------------------------------
case (DATA_RATE_OQ)
"SDR", "DDR" :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
$finish;
end
endcase // case(DATA_RATE_OQ)
//-------------------------------------------------
//----- DATA_RATE_TQ check
//-------------------------------------------------
case (DATA_RATE_TQ)
"BUF", "DDR", "SDR" :;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are BUF, SDR, or DDR", DATA_RATE_TQ);
$finish;
end
endcase // case(DATA_RATE_TQ)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10, 14 : ;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE2 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, 10 or 14", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE) // {mem_slave}
"MASTER", "SLAVE" :;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE2 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
//-------------------------------------------------
//----- TRISTATE_WIDTH check
//-------------------------------------------------
case (TRISTATE_WIDTH) // {mem_twidth4}
1,2,4 : ;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE2 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
$finish;
end
endcase // case(TRISTATE_WIDTH)
//-------------------------------------------------
//----- DATA_RATE_OQ/DATA_WIDTH Combination
//-------------------------------------------------
case (DATA_RATE_OQ)
"SDR" , "DDR" : ;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE2 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
$finish;
end
endcase // case(DATA_RATE_OQ/DATA_WIDTH)
//-------------------------------------------------
end // initial begin
B_OSERDESE2 #(
.DATA_RATE_OQ (DATA_RATE_OQ),
.DATA_RATE_TQ (DATA_RATE_TQ),
.DATA_WIDTH (DATA_WIDTH),
.INIT_OQ (INIT_OQ),
.INIT_TQ (INIT_TQ),
.SERDES_MODE (SERDES_MODE),
.SRVAL_OQ (SRVAL_OQ),
.SRVAL_TQ (SRVAL_TQ),
.TBYTE_CTL (TBYTE_CTL),
.TBYTE_SRC (TBYTE_SRC),
.TRISTATE_WIDTH (TRISTATE_WIDTH))
B_OSERDESE2_INST (
.OFB (OFB_out),
.OQ (OQ_out),
.SHIFTOUT1 (SHIFTOUT1_out),
.SHIFTOUT2 (SHIFTOUT2_out),
.TBYTEOUT (TBYTEOUT_out),
.TFB (TFB_out),
.TQ (TQ_out),
.CLK (CLK_in),
.CLKDIV (CLKDIV_in),
.D1 (D1_in),
.D2 (D2_in),
.D3 (D3_in),
.D4 (D4_in),
.D5 (D5_in),
.D6 (D6_in),
.D7 (D7_in),
.D8 (D8_in),
.OCE (OCE_in),
.RST (RST_in),
.SHIFTIN1 (SHIFTIN1_in),
.SHIFTIN2 (SHIFTIN2_in),
.T1 (T1_in),
.T2 (T2_in),
.T3 (T3_in),
.T4 (T4_in),
.TBYTEIN (TBYTEIN_in),
.TCE (TCE_in),
.GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OCE);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_T1);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_TCE);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OCE);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_T1);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_TCE);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D1);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D2);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D3);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D4);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D5);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D6);
$setuphold (posedge CLKDIV, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D7);
$setuphold (posedge CLKDIV, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D8);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T1);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T2);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T3);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T4);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D1);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D2);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D3);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D4);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D5);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D6);
$setuphold (posedge CLKDIV, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D7);
$setuphold (posedge CLKDIV, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D8);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T1);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T2);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T3);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T4);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OCE);
$setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_T1);
$setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_TCE);
$setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_OCE);
$setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_T1);
$setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_TCE);
$setuphold (negedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D1);
$setuphold (negedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D2);
$setuphold (negedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D3);
$setuphold (negedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D4);
$setuphold (negedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D5);
$setuphold (negedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D6);
$setuphold (negedge CLKDIV, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D7);
$setuphold (negedge CLKDIV, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D8);
$setuphold (negedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T1);
$setuphold (negedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T2);
$setuphold (negedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T3);
$setuphold (negedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T4);
$setuphold (negedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D1);
$setuphold (negedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D2);
$setuphold (negedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D3);
$setuphold (negedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D4);
$setuphold (negedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D5);
$setuphold (negedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D6);
$setuphold (negedge CLKDIV, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D7);
$setuphold (negedge CLKDIV, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_D8);
$setuphold (negedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T1);
$setuphold (negedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T2);
$setuphold (negedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T3);
$setuphold (negedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_T4);
$setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
$setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, delay_CLKDIV, delay_RST);
`endif
( CLK => OFB) = (100:100:100, 100:100:100);
( CLK => OQ) = (100:100:100, 100:100:100);
( CLK => TFB) = (100:100:100, 100:100:100);
( CLK => TQ) = (100:100:100, 100:100:100);
( T1 => TBYTEOUT) = (100:100:100, 100:100:100);
( T1 => TQ) = (100:100:100, 100:100:100);
( TBYTEIN => TQ) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OSERDESE3.v 0000664 0000000 0000000 00000020763 12327044266 0022726 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OSERDESE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OSERDESE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter ODDR_MODE = "FALSE",
parameter OSERDES_D_BYPASS = "FALSE",
parameter OSERDES_T_BYPASS = "FALSE"
)(
output OQ,
output T_OUT,
input CLK,
input CLKDIV,
input [7:0] D,
input RST,
input T
);
// define constants
localparam MODULE_NAME = "OSERDESE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLKDIV_INVERTED_REG = IS_CLKDIV_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [40:1] ODDR_MODE_REG = ODDR_MODE;
localparam [40:1] OSERDES_D_BYPASS_REG = OSERDES_D_BYPASS;
localparam [40:1] OSERDES_T_BYPASS_REG = OSERDES_T_BYPASS;
`endif
localparam [64:1] TBYTE_CTL_REG = "T";
wire IS_CLKDIV_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OSERDESE3_dr.v"
`endif
wire OQ_out;
wire T_OUT_out;
wire OQ_delay;
wire T_OUT_delay;
wire CLKDIV_in;
wire CLK_in;
wire OFD_CE_in;
wire RST_in;
wire T_in;
wire [7:0] D_in;
wire CLKDIV_delay;
wire CLK_delay;
wire RST_delay;
wire T_delay;
wire [7:0] D_delay;
assign #(out_delay) OQ = OQ_delay;
assign #(out_delay) T_OUT = T_OUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLKDIV_delay = CLKDIV;
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) D_delay = D;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) T_delay = T;
assign OQ_delay = OQ_out;
assign T_OUT_delay = T_OUT_out;
assign CLKDIV_in = CLKDIV_delay ^ IS_CLKDIV_INVERTED_BIN;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign D_in = D_delay;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign T_in = T_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLKDIV_INVERTED_BIN = IS_CLKDIV_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 2) &&
(DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((INIT_REG < 1'b0) || (INIT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((IS_CLKDIV_INVERTED_REG < 1'b0) || (IS_CLKDIV_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLKDIV_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLKDIV_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG < 1'b0) || (IS_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((ODDR_MODE_REG != "FALSE") &&
(ODDR_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ODDR_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ODDR_MODE_REG);
attr_err = 1'b1;
end
if ((OSERDES_D_BYPASS_REG != "FALSE") &&
(OSERDES_D_BYPASS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute OSERDES_D_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OSERDES_D_BYPASS_REG);
attr_err = 1'b1;
end
if ((OSERDES_T_BYPASS_REG != "FALSE") &&
(OSERDES_T_BYPASS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute OSERDES_T_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OSERDES_T_BYPASS_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign OFD_CE_in = 1'b0; // tie off
SIP_OSERDESE3 SIP_OSERDESE3_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.INIT (INIT_REG),
.ODDR_MODE (ODDR_MODE_REG),
.OSERDES_D_BYPASS (OSERDES_D_BYPASS_REG),
.OSERDES_T_BYPASS (OSERDES_T_BYPASS_REG),
.TBYTE_CTL (TBYTE_CTL_REG),
.OQ (OQ_out),
.T_OUT (T_OUT_out),
.CLK (CLK_in),
.CLKDIV (CLKDIV_in),
.D (D_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.T (T_in),
.GSR (glblGSR)
);
specify
(CLK => OQ) = (0:0:0, 0:0:0);
(CLKDIV => OQ) = (0:0:0, 0:0:0);
(CLKDIV => T_OUT) = (0:0:0, 0:0:0);
(D *> OQ) = (0:0:0, 0:0:0);
(D *> T_OUT) = (0:0:0, 0:0:0);
(T => T_OUT) = (0:0:0, 0:0:0);
(negedge RST => (OQ +: 0)) = (0:0:0, 0:0:0);
(posedge RST => (OQ +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$recrem ( negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, negedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$recrem ( negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( negedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$recrem ( posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, negedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$recrem ( posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, CLK_delay);
$recrem ( posedge RST, posedge CLKDIV, 0:0:0, 0:0:0, notifier,,, RST_delay, CLKDIV_delay);
$setuphold (negedge CLKDIV, negedge D, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, D_delay);
$setuphold (negedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$setuphold (negedge CLKDIV, posedge D, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, D_delay);
$setuphold (negedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$setuphold (posedge CLKDIV, negedge D, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, D_delay);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$setuphold (posedge CLKDIV, posedge D, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, D_delay);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_delay, RST_delay);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/OUT_FIFO.v 0000664 0000000 0000000 00000027607 12327044266 0022710 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan OUT FIFO
// /__/ /\ Filename : OUT_FIFO.v
// \ \ / \
// \__\/\__ \
//
// Date: Comment:
// 15MAR2010 Initial UNI/UNP/SIM version from yml
// 03JUN2010 yml update
// 10JUN2010 yml update
// 29JUN2010 enable encrypted rtl
// 10AUG2010 yml, rtl update
// 28SEP2010 minor clean up
// add width checks
// 28OCT2010 rtl update
// 05NOV2010 update defaults
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP, make default
// 21SEP2011 625537 period checks on RDCLK, WRCLK
// 16FEB2012 645871 add conditions to RDEN -> Q delays
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OUT_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_8_X_4";
parameter OUTPUT_DISABLE = "FALSE";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "OUT_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [3:0] Q0;
output [3:0] Q1;
output [3:0] Q2;
output [3:0] Q3;
output [3:0] Q4;
output [3:0] Q7;
output [3:0] Q8;
output [3:0] Q9;
output [7:0] Q5;
output [7:0] Q6;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [7:0] D0;
input [7:0] D1;
input [7:0] D2;
input [7:0] D3;
input [7:0] D4;
input [7:0] D5;
input [7:0] D6;
input [7:0] D7;
input [7:0] D8;
input [7:0] D9;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] OUTPUT_DISABLE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
$finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
$finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_8_X_4" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_8_X_4 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
$finish;
end
endcase
case (OUTPUT_DISABLE)
"FALSE" : OUTPUT_DISABLE_BINARY <= 1'b0;
"TRUE" : OUTPUT_DISABLE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_DISABLE);
$finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
$finish;
end
endcase
end
wire [3:0] delay_Q0;
wire [3:0] delay_Q1;
wire [3:0] delay_Q2;
wire [3:0] delay_Q3;
wire [3:0] delay_Q4;
wire [3:0] delay_Q7;
wire [3:0] delay_Q8;
wire [3:0] delay_Q9;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [7:0] delay_D0;
wire [7:0] delay_D1;
wire [7:0] delay_D2;
wire [7:0] delay_D3;
wire [7:0] delay_D4;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire [7:0] delay_D7;
wire [7:0] delay_D8;
wire [7:0] delay_D9;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_OUT_FIFO OUT_FIFO_INST (
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.OUTPUT_DISABLE (OUTPUT_DISABLE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q0) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q1) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q2) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q3) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q4) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q5) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q6) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q7) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q8) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // OUT_FIFO
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PCIE_2_1.v 0000664 0000000 0000000 00001654003 12327044266 0022614 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : PCIE_2_1.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module PCIE_2_1 (
CFGAERECRCCHECKEN,
CFGAERECRCGENEN,
CFGAERROOTERRCORRERRRECEIVED,
CFGAERROOTERRCORRERRREPORTINGEN,
CFGAERROOTERRFATALERRRECEIVED,
CFGAERROOTERRFATALERRREPORTINGEN,
CFGAERROOTERRNONFATALERRRECEIVED,
CFGAERROOTERRNONFATALERRREPORTINGEN,
CFGBRIDGESERREN,
CFGCOMMANDBUSMASTERENABLE,
CFGCOMMANDINTERRUPTDISABLE,
CFGCOMMANDIOENABLE,
CFGCOMMANDMEMENABLE,
CFGCOMMANDSERREN,
CFGDEVCONTROL2ARIFORWARDEN,
CFGDEVCONTROL2ATOMICEGRESSBLOCK,
CFGDEVCONTROL2ATOMICREQUESTEREN,
CFGDEVCONTROL2CPLTIMEOUTDIS,
CFGDEVCONTROL2CPLTIMEOUTVAL,
CFGDEVCONTROL2IDOCPLEN,
CFGDEVCONTROL2IDOREQEN,
CFGDEVCONTROL2LTREN,
CFGDEVCONTROL2TLPPREFIXBLOCK,
CFGDEVCONTROLAUXPOWEREN,
CFGDEVCONTROLCORRERRREPORTINGEN,
CFGDEVCONTROLENABLERO,
CFGDEVCONTROLEXTTAGEN,
CFGDEVCONTROLFATALERRREPORTINGEN,
CFGDEVCONTROLMAXPAYLOAD,
CFGDEVCONTROLMAXREADREQ,
CFGDEVCONTROLNONFATALREPORTINGEN,
CFGDEVCONTROLNOSNOOPEN,
CFGDEVCONTROLPHANTOMEN,
CFGDEVCONTROLURERRREPORTINGEN,
CFGDEVSTATUSCORRERRDETECTED,
CFGDEVSTATUSFATALERRDETECTED,
CFGDEVSTATUSNONFATALERRDETECTED,
CFGDEVSTATUSURDETECTED,
CFGERRAERHEADERLOGSETN,
CFGERRCPLRDYN,
CFGINTERRUPTDO,
CFGINTERRUPTMMENABLE,
CFGINTERRUPTMSIENABLE,
CFGINTERRUPTMSIXENABLE,
CFGINTERRUPTMSIXFM,
CFGINTERRUPTRDYN,
CFGLINKCONTROLASPMCONTROL,
CFGLINKCONTROLAUTOBANDWIDTHINTEN,
CFGLINKCONTROLBANDWIDTHINTEN,
CFGLINKCONTROLCLOCKPMEN,
CFGLINKCONTROLCOMMONCLOCK,
CFGLINKCONTROLEXTENDEDSYNC,
CFGLINKCONTROLHWAUTOWIDTHDIS,
CFGLINKCONTROLLINKDISABLE,
CFGLINKCONTROLRCB,
CFGLINKCONTROLRETRAINLINK,
CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
CFGLINKSTATUSBANDWIDTHSTATUS,
CFGLINKSTATUSCURRENTSPEED,
CFGLINKSTATUSDLLACTIVE,
CFGLINKSTATUSLINKTRAINING,
CFGLINKSTATUSNEGOTIATEDWIDTH,
CFGMGMTDO,
CFGMGMTRDWRDONEN,
CFGMSGDATA,
CFGMSGRECEIVED,
CFGMSGRECEIVEDASSERTINTA,
CFGMSGRECEIVEDASSERTINTB,
CFGMSGRECEIVEDASSERTINTC,
CFGMSGRECEIVEDASSERTINTD,
CFGMSGRECEIVEDDEASSERTINTA,
CFGMSGRECEIVEDDEASSERTINTB,
CFGMSGRECEIVEDDEASSERTINTC,
CFGMSGRECEIVEDDEASSERTINTD,
CFGMSGRECEIVEDERRCOR,
CFGMSGRECEIVEDERRFATAL,
CFGMSGRECEIVEDERRNONFATAL,
CFGMSGRECEIVEDPMASNAK,
CFGMSGRECEIVEDPMETO,
CFGMSGRECEIVEDPMETOACK,
CFGMSGRECEIVEDPMPME,
CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
CFGMSGRECEIVEDUNLOCK,
CFGPCIELINKSTATE,
CFGPMCSRPMEEN,
CFGPMCSRPMESTATUS,
CFGPMCSRPOWERSTATE,
CFGPMRCVASREQL1N,
CFGPMRCVENTERL1N,
CFGPMRCVENTERL23N,
CFGPMRCVREQACKN,
CFGROOTCONTROLPMEINTEN,
CFGROOTCONTROLSYSERRCORRERREN,
CFGROOTCONTROLSYSERRFATALERREN,
CFGROOTCONTROLSYSERRNONFATALERREN,
CFGSLOTCONTROLELECTROMECHILCTLPULSE,
CFGTRANSACTION,
CFGTRANSACTIONADDR,
CFGTRANSACTIONTYPE,
CFGVCTCVCMAP,
DBGSCLRA,
DBGSCLRB,
DBGSCLRC,
DBGSCLRD,
DBGSCLRE,
DBGSCLRF,
DBGSCLRG,
DBGSCLRH,
DBGSCLRI,
DBGSCLRJ,
DBGSCLRK,
DBGVECA,
DBGVECB,
DBGVECC,
DRPDO,
DRPRDY,
LL2BADDLLPERR,
LL2BADTLPERR,
LL2LINKSTATUS,
LL2PROTOCOLERR,
LL2RECEIVERERR,
LL2REPLAYROERR,
LL2REPLAYTOERR,
LL2SUSPENDOK,
LL2TFCINIT1SEQ,
LL2TFCINIT2SEQ,
LL2TXIDLE,
LNKCLKEN,
MIMRXRADDR,
MIMRXREN,
MIMRXWADDR,
MIMRXWDATA,
MIMRXWEN,
MIMTXRADDR,
MIMTXREN,
MIMTXWADDR,
MIMTXWDATA,
MIMTXWEN,
PIPERX0POLARITY,
PIPERX1POLARITY,
PIPERX2POLARITY,
PIPERX3POLARITY,
PIPERX4POLARITY,
PIPERX5POLARITY,
PIPERX6POLARITY,
PIPERX7POLARITY,
PIPETX0CHARISK,
PIPETX0COMPLIANCE,
PIPETX0DATA,
PIPETX0ELECIDLE,
PIPETX0POWERDOWN,
PIPETX1CHARISK,
PIPETX1COMPLIANCE,
PIPETX1DATA,
PIPETX1ELECIDLE,
PIPETX1POWERDOWN,
PIPETX2CHARISK,
PIPETX2COMPLIANCE,
PIPETX2DATA,
PIPETX2ELECIDLE,
PIPETX2POWERDOWN,
PIPETX3CHARISK,
PIPETX3COMPLIANCE,
PIPETX3DATA,
PIPETX3ELECIDLE,
PIPETX3POWERDOWN,
PIPETX4CHARISK,
PIPETX4COMPLIANCE,
PIPETX4DATA,
PIPETX4ELECIDLE,
PIPETX4POWERDOWN,
PIPETX5CHARISK,
PIPETX5COMPLIANCE,
PIPETX5DATA,
PIPETX5ELECIDLE,
PIPETX5POWERDOWN,
PIPETX6CHARISK,
PIPETX6COMPLIANCE,
PIPETX6DATA,
PIPETX6ELECIDLE,
PIPETX6POWERDOWN,
PIPETX7CHARISK,
PIPETX7COMPLIANCE,
PIPETX7DATA,
PIPETX7ELECIDLE,
PIPETX7POWERDOWN,
PIPETXDEEMPH,
PIPETXMARGIN,
PIPETXRATE,
PIPETXRCVRDET,
PIPETXRESET,
PL2L0REQ,
PL2LINKUP,
PL2RECEIVERERR,
PL2RECOVERY,
PL2RXELECIDLE,
PL2RXPMSTATE,
PL2SUSPENDOK,
PLDBGVEC,
PLDIRECTEDCHANGEDONE,
PLINITIALLINKWIDTH,
PLLANEREVERSALMODE,
PLLINKGEN2CAP,
PLLINKPARTNERGEN2SUPPORTED,
PLLINKUPCFGCAP,
PLLTSSMSTATE,
PLPHYLNKUPN,
PLRECEIVEDHOTRST,
PLRXPMSTATE,
PLSELLNKRATE,
PLSELLNKWIDTH,
PLTXPMSTATE,
RECEIVEDFUNCLVLRSTN,
TL2ASPMSUSPENDCREDITCHECKOK,
TL2ASPMSUSPENDREQ,
TL2ERRFCPE,
TL2ERRHDR,
TL2ERRMALFORMED,
TL2ERRRXOVERFLOW,
TL2PPMSUSPENDOK,
TRNFCCPLD,
TRNFCCPLH,
TRNFCNPD,
TRNFCNPH,
TRNFCPD,
TRNFCPH,
TRNLNKUP,
TRNRBARHIT,
TRNRD,
TRNRDLLPDATA,
TRNRDLLPSRCRDY,
TRNRECRCERR,
TRNREOF,
TRNRERRFWD,
TRNRREM,
TRNRSOF,
TRNRSRCDSC,
TRNRSRCRDY,
TRNTBUFAV,
TRNTCFGREQ,
TRNTDLLPDSTRDY,
TRNTDSTRDY,
TRNTERRDROP,
USERRSTN,
CFGAERINTERRUPTMSGNUM,
CFGDEVID,
CFGDSBUSNUMBER,
CFGDSDEVICENUMBER,
CFGDSFUNCTIONNUMBER,
CFGDSN,
CFGERRACSN,
CFGERRAERHEADERLOG,
CFGERRATOMICEGRESSBLOCKEDN,
CFGERRCORN,
CFGERRCPLABORTN,
CFGERRCPLTIMEOUTN,
CFGERRCPLUNEXPECTN,
CFGERRECRCN,
CFGERRINTERNALCORN,
CFGERRINTERNALUNCORN,
CFGERRLOCKEDN,
CFGERRMALFORMEDN,
CFGERRMCBLOCKEDN,
CFGERRNORECOVERYN,
CFGERRPOISONEDN,
CFGERRPOSTEDN,
CFGERRTLPCPLHEADER,
CFGERRURN,
CFGFORCECOMMONCLOCKOFF,
CFGFORCEEXTENDEDSYNCON,
CFGFORCEMPS,
CFGINTERRUPTASSERTN,
CFGINTERRUPTDI,
CFGINTERRUPTN,
CFGINTERRUPTSTATN,
CFGMGMTBYTEENN,
CFGMGMTDI,
CFGMGMTDWADDR,
CFGMGMTRDENN,
CFGMGMTWRENN,
CFGMGMTWRREADONLYN,
CFGMGMTWRRW1CASRWN,
CFGPCIECAPINTERRUPTMSGNUM,
CFGPMFORCESTATE,
CFGPMFORCESTATEENN,
CFGPMHALTASPML0SN,
CFGPMHALTASPML1N,
CFGPMSENDPMETON,
CFGPMTURNOFFOKN,
CFGPMWAKEN,
CFGPORTNUMBER,
CFGREVID,
CFGSUBSYSID,
CFGSUBSYSVENDID,
CFGTRNPENDINGN,
CFGVENDID,
CMRSTN,
CMSTICKYRSTN,
DBGMODE,
DBGSUBMODE,
DLRSTN,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
FUNCLVLRSTN,
LL2SENDASREQL1,
LL2SENDENTERL1,
LL2SENDENTERL23,
LL2SENDPMACK,
LL2SUSPENDNOW,
LL2TLPRCV,
MIMRXRDATA,
MIMTXRDATA,
PIPECLK,
PIPERX0CHANISALIGNED,
PIPERX0CHARISK,
PIPERX0DATA,
PIPERX0ELECIDLE,
PIPERX0PHYSTATUS,
PIPERX0STATUS,
PIPERX0VALID,
PIPERX1CHANISALIGNED,
PIPERX1CHARISK,
PIPERX1DATA,
PIPERX1ELECIDLE,
PIPERX1PHYSTATUS,
PIPERX1STATUS,
PIPERX1VALID,
PIPERX2CHANISALIGNED,
PIPERX2CHARISK,
PIPERX2DATA,
PIPERX2ELECIDLE,
PIPERX2PHYSTATUS,
PIPERX2STATUS,
PIPERX2VALID,
PIPERX3CHANISALIGNED,
PIPERX3CHARISK,
PIPERX3DATA,
PIPERX3ELECIDLE,
PIPERX3PHYSTATUS,
PIPERX3STATUS,
PIPERX3VALID,
PIPERX4CHANISALIGNED,
PIPERX4CHARISK,
PIPERX4DATA,
PIPERX4ELECIDLE,
PIPERX4PHYSTATUS,
PIPERX4STATUS,
PIPERX4VALID,
PIPERX5CHANISALIGNED,
PIPERX5CHARISK,
PIPERX5DATA,
PIPERX5ELECIDLE,
PIPERX5PHYSTATUS,
PIPERX5STATUS,
PIPERX5VALID,
PIPERX6CHANISALIGNED,
PIPERX6CHARISK,
PIPERX6DATA,
PIPERX6ELECIDLE,
PIPERX6PHYSTATUS,
PIPERX6STATUS,
PIPERX6VALID,
PIPERX7CHANISALIGNED,
PIPERX7CHARISK,
PIPERX7DATA,
PIPERX7ELECIDLE,
PIPERX7PHYSTATUS,
PIPERX7STATUS,
PIPERX7VALID,
PL2DIRECTEDLSTATE,
PLDBGMODE,
PLDIRECTEDLINKAUTON,
PLDIRECTEDLINKCHANGE,
PLDIRECTEDLINKSPEED,
PLDIRECTEDLINKWIDTH,
PLDIRECTEDLTSSMNEW,
PLDIRECTEDLTSSMNEWVLD,
PLDIRECTEDLTSSMSTALL,
PLDOWNSTREAMDEEMPHSOURCE,
PLRSTN,
PLTRANSMITHOTRST,
PLUPSTREAMPREFERDEEMPH,
SYSRSTN,
TL2ASPMSUSPENDCREDITCHECK,
TL2PPMSUSPENDREQ,
TLRSTN,
TRNFCSEL,
TRNRDSTRDY,
TRNRFCPRET,
TRNRNPOK,
TRNRNPREQ,
TRNTCFGGNT,
TRNTD,
TRNTDLLPDATA,
TRNTDLLPSRCRDY,
TRNTECRCGEN,
TRNTEOF,
TRNTERRFWD,
TRNTREM,
TRNTSOF,
TRNTSRCDSC,
TRNTSRCRDY,
TRNTSTR,
USERCLK,
USERCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [11:0] AER_BASE_PTR = 12'h140;
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [15:0] AER_CAP_ID = 16'h0001;
parameter AER_CAP_MULTIHEADER = "FALSE";
parameter [11:0] AER_CAP_NEXTPTR = 12'h178;
parameter AER_CAP_ON = "FALSE";
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000;
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
parameter [3:0] AER_CAP_VERSION = 4'h2;
parameter ALLOW_X8_GEN2 = "FALSE";
parameter [31:0] BAR0 = 32'hFFFFFF00;
parameter [31:0] BAR1 = 32'hFFFF0000;
parameter [31:0] BAR2 = 32'hFFFF000C;
parameter [31:0] BAR3 = 32'hFFFFFFFF;
parameter [31:0] BAR4 = 32'h00000000;
parameter [31:0] BAR5 = 32'h00000000;
parameter [7:0] CAPABILITIES_PTR = 8'h40;
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
parameter integer CFG_ECRC_ERR_CPLSTAT = 0;
parameter [23:0] CLASS_CODE = 24'h000000;
parameter CMD_INTX_IMPLEMENTED = "TRUE";
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
parameter [6:0] CRM_MODULE_RSTS = 7'h00;
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0;
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0;
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
parameter integer DEV_CAP_RSVD_14_12 = 0;
parameter integer DEV_CAP_RSVD_17_16 = 0;
parameter integer DEV_CAP_RSVD_31_29 = 0;
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
parameter DISABLE_BAR_FILTERING = "FALSE";
parameter DISABLE_ERR_MSG = "FALSE";
parameter DISABLE_ID_CHECK = "FALSE";
parameter DISABLE_LANE_REVERSAL = "FALSE";
parameter DISABLE_LOCKED_FILTER = "FALSE";
parameter DISABLE_PPM_FILTER = "FALSE";
parameter DISABLE_RX_POISONED_RESP = "FALSE";
parameter DISABLE_RX_TC_FILTER = "FALSE";
parameter DISABLE_SCRAMBLING = "FALSE";
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
parameter [11:0] DSN_BASE_PTR = 12'h100;
parameter [15:0] DSN_CAP_ID = 16'h0003;
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C;
parameter DSN_CAP_ON = "TRUE";
parameter [3:0] DSN_CAP_VERSION = 4'h1;
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
parameter ENTER_RVRY_EI_L0 = "TRUE";
parameter EXIT_LOOPBACK_ON_EI = "TRUE";
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
parameter [7:0] HEADER_TYPE = 8'h00;
parameter [4:0] INFER_EI = 5'h00;
parameter [7:0] INTERRUPT_PIN = 8'h01;
parameter INTERRUPT_STAT_AUTO = "TRUE";
parameter IS_SWITCH = "FALSE";
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF;
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE";
parameter integer LINK_CAP_ASPM_SUPPORT = 1;
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
parameter integer LINK_CAP_RSVD_23 = 0;
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
parameter integer LINK_CONTROL_RCB = 0;
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
parameter MPS_FORCE = "FALSE";
parameter [7:0] MSIX_BASE_PTR = 8'h9C;
parameter [7:0] MSIX_CAP_ID = 8'h11;
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
parameter MSIX_CAP_ON = "FALSE";
parameter integer MSIX_CAP_PBA_BIR = 0;
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
parameter [7:0] MSI_BASE_PTR = 8'h48;
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
parameter [7:0] MSI_CAP_ID = 8'h05;
parameter integer MSI_CAP_MULTIMSGCAP = 0;
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
parameter MSI_CAP_ON = "FALSE";
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
parameter integer N_FTS_COMCLK_GEN1 = 255;
parameter integer N_FTS_COMCLK_GEN2 = 255;
parameter integer N_FTS_GEN1 = 255;
parameter integer N_FTS_GEN2 = 255;
parameter [7:0] PCIE_BASE_PTR = 8'h60;
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C;
parameter PCIE_CAP_ON = "TRUE";
parameter integer PCIE_CAP_RSVD_15_14 = 0;
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
parameter integer PCIE_REVISION = 2;
parameter integer PL_AUTO_CONFIG = 0;
parameter PL_FAST_TRAIN = "FALSE";
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000;
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0;
parameter PM_ASPM_FASTEXIT = "FALSE";
parameter [7:0] PM_BASE_PTR = 8'h40;
parameter integer PM_CAP_AUXCURRENT = 0;
parameter PM_CAP_D1SUPPORT = "TRUE";
parameter PM_CAP_D2SUPPORT = "TRUE";
parameter PM_CAP_DSI = "FALSE";
parameter [7:0] PM_CAP_ID = 8'h01;
parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
parameter PM_CAP_ON = "TRUE";
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
parameter PM_CAP_PME_CLOCK = "FALSE";
parameter integer PM_CAP_RSVD_04 = 0;
parameter integer PM_CAP_VERSION = 3;
parameter PM_CSR_B2B3 = "FALSE";
parameter PM_CSR_BPCCEN = "FALSE";
parameter PM_CSR_NOSOFTRST = "TRUE";
parameter [7:0] PM_DATA0 = 8'h01;
parameter [7:0] PM_DATA1 = 8'h01;
parameter [7:0] PM_DATA2 = 8'h01;
parameter [7:0] PM_DATA3 = 8'h01;
parameter [7:0] PM_DATA4 = 8'h01;
parameter [7:0] PM_DATA5 = 8'h01;
parameter [7:0] PM_DATA6 = 8'h01;
parameter [7:0] PM_DATA7 = 8'h01;
parameter [1:0] PM_DATA_SCALE0 = 2'h1;
parameter [1:0] PM_DATA_SCALE1 = 2'h1;
parameter [1:0] PM_DATA_SCALE2 = 2'h1;
parameter [1:0] PM_DATA_SCALE3 = 2'h1;
parameter [1:0] PM_DATA_SCALE4 = 2'h1;
parameter [1:0] PM_DATA_SCALE5 = 2'h1;
parameter [1:0] PM_DATA_SCALE6 = 2'h1;
parameter [1:0] PM_DATA_SCALE7 = 2'h1;
parameter PM_MF = "FALSE";
parameter [11:0] RBAR_BASE_PTR = 12'h178;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00;
parameter [15:0] RBAR_CAP_ID = 16'h0015;
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0;
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000;
parameter RBAR_CAP_ON = "FALSE";
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000;
parameter [3:0] RBAR_CAP_VERSION = 4'h1;
parameter [2:0] RBAR_NUM = 3'h1;
parameter integer RECRC_CHK = 0;
parameter RECRC_CHK_TRIM = "FALSE";
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
parameter [1:0] RP_AUTO_SPD = 2'h1;
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F;
parameter SELECT_DLL_IF = "FALSE";
parameter SIM_VERSION = "1.0";
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
parameter integer SPARE_BIT0 = 0;
parameter integer SPARE_BIT1 = 0;
parameter integer SPARE_BIT2 = 0;
parameter integer SPARE_BIT3 = 0;
parameter integer SPARE_BIT4 = 0;
parameter integer SPARE_BIT5 = 0;
parameter integer SPARE_BIT6 = 0;
parameter integer SPARE_BIT7 = 0;
parameter integer SPARE_BIT8 = 0;
parameter [7:0] SPARE_BYTE0 = 8'h00;
parameter [7:0] SPARE_BYTE1 = 8'h00;
parameter [7:0] SPARE_BYTE2 = 8'h00;
parameter [7:0] SPARE_BYTE3 = 8'h00;
parameter [31:0] SPARE_WORD0 = 32'h00000000;
parameter [31:0] SPARE_WORD1 = 32'h00000000;
parameter [31:0] SPARE_WORD2 = 32'h00000000;
parameter [31:0] SPARE_WORD3 = 32'h00000000;
parameter SSL_MESSAGE_AUTO = "FALSE";
parameter TECRC_EP_INV = "FALSE";
parameter TL_RBYPASS = "FALSE";
parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
parameter TL_TFC_DISABLE = "FALSE";
parameter TL_TX_CHECKS_DISABLE = "FALSE";
parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
parameter TRN_DW = "FALSE";
parameter TRN_NP_FC = "FALSE";
parameter UPCONFIG_CAPABLE = "TRUE";
parameter UPSTREAM_FACING = "TRUE";
parameter UR_ATOMIC = "TRUE";
parameter UR_CFG1 = "TRUE";
parameter UR_INV_REQ = "TRUE";
parameter UR_PRS_RESPONSE = "TRUE";
parameter USER_CLK2_DIV2 = "FALSE";
parameter integer USER_CLK_FREQ = 3;
parameter USE_RID_PINS = "FALSE";
parameter VC0_CPL_INFINITE = "TRUE";
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
parameter integer VC0_TOTAL_CREDITS_CD = 127;
parameter integer VC0_TOTAL_CREDITS_CH = 31;
parameter integer VC0_TOTAL_CREDITS_NPD = 24;
parameter integer VC0_TOTAL_CREDITS_NPH = 12;
parameter integer VC0_TOTAL_CREDITS_PD = 288;
parameter integer VC0_TOTAL_CREDITS_PH = 32;
parameter integer VC0_TX_LASTPACKET = 31;
parameter [11:0] VC_BASE_PTR = 12'h10C;
parameter [15:0] VC_CAP_ID = 16'h0002;
parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
parameter VC_CAP_ON = "FALSE";
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
parameter [3:0] VC_CAP_VERSION = 4'h1;
parameter [11:0] VSEC_BASE_PTR = 12'h128;
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
parameter [15:0] VSEC_CAP_ID = 16'h000B;
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140;
parameter VSEC_CAP_ON = "FALSE";
parameter [3:0] VSEC_CAP_VERSION = 4'h1;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CFGAERECRCCHECKEN;
output CFGAERECRCGENEN;
output CFGAERROOTERRCORRERRRECEIVED;
output CFGAERROOTERRCORRERRREPORTINGEN;
output CFGAERROOTERRFATALERRRECEIVED;
output CFGAERROOTERRFATALERRREPORTINGEN;
output CFGAERROOTERRNONFATALERRRECEIVED;
output CFGAERROOTERRNONFATALERRREPORTINGEN;
output CFGBRIDGESERREN;
output CFGCOMMANDBUSMASTERENABLE;
output CFGCOMMANDINTERRUPTDISABLE;
output CFGCOMMANDIOENABLE;
output CFGCOMMANDMEMENABLE;
output CFGCOMMANDSERREN;
output CFGDEVCONTROL2ARIFORWARDEN;
output CFGDEVCONTROL2ATOMICEGRESSBLOCK;
output CFGDEVCONTROL2ATOMICREQUESTEREN;
output CFGDEVCONTROL2CPLTIMEOUTDIS;
output CFGDEVCONTROL2IDOCPLEN;
output CFGDEVCONTROL2IDOREQEN;
output CFGDEVCONTROL2LTREN;
output CFGDEVCONTROL2TLPPREFIXBLOCK;
output CFGDEVCONTROLAUXPOWEREN;
output CFGDEVCONTROLCORRERRREPORTINGEN;
output CFGDEVCONTROLENABLERO;
output CFGDEVCONTROLEXTTAGEN;
output CFGDEVCONTROLFATALERRREPORTINGEN;
output CFGDEVCONTROLNONFATALREPORTINGEN;
output CFGDEVCONTROLNOSNOOPEN;
output CFGDEVCONTROLPHANTOMEN;
output CFGDEVCONTROLURERRREPORTINGEN;
output CFGDEVSTATUSCORRERRDETECTED;
output CFGDEVSTATUSFATALERRDETECTED;
output CFGDEVSTATUSNONFATALERRDETECTED;
output CFGDEVSTATUSURDETECTED;
output CFGERRAERHEADERLOGSETN;
output CFGERRCPLRDYN;
output CFGINTERRUPTMSIENABLE;
output CFGINTERRUPTMSIXENABLE;
output CFGINTERRUPTMSIXFM;
output CFGINTERRUPTRDYN;
output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
output CFGLINKCONTROLBANDWIDTHINTEN;
output CFGLINKCONTROLCLOCKPMEN;
output CFGLINKCONTROLCOMMONCLOCK;
output CFGLINKCONTROLEXTENDEDSYNC;
output CFGLINKCONTROLHWAUTOWIDTHDIS;
output CFGLINKCONTROLLINKDISABLE;
output CFGLINKCONTROLRCB;
output CFGLINKCONTROLRETRAINLINK;
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
output CFGLINKSTATUSBANDWIDTHSTATUS;
output CFGLINKSTATUSDLLACTIVE;
output CFGLINKSTATUSLINKTRAINING;
output CFGMGMTRDWRDONEN;
output CFGMSGRECEIVED;
output CFGMSGRECEIVEDASSERTINTA;
output CFGMSGRECEIVEDASSERTINTB;
output CFGMSGRECEIVEDASSERTINTC;
output CFGMSGRECEIVEDASSERTINTD;
output CFGMSGRECEIVEDDEASSERTINTA;
output CFGMSGRECEIVEDDEASSERTINTB;
output CFGMSGRECEIVEDDEASSERTINTC;
output CFGMSGRECEIVEDDEASSERTINTD;
output CFGMSGRECEIVEDERRCOR;
output CFGMSGRECEIVEDERRFATAL;
output CFGMSGRECEIVEDERRNONFATAL;
output CFGMSGRECEIVEDPMASNAK;
output CFGMSGRECEIVEDPMETO;
output CFGMSGRECEIVEDPMETOACK;
output CFGMSGRECEIVEDPMPME;
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
output CFGMSGRECEIVEDUNLOCK;
output CFGPMCSRPMEEN;
output CFGPMCSRPMESTATUS;
output CFGPMRCVASREQL1N;
output CFGPMRCVENTERL1N;
output CFGPMRCVENTERL23N;
output CFGPMRCVREQACKN;
output CFGROOTCONTROLPMEINTEN;
output CFGROOTCONTROLSYSERRCORRERREN;
output CFGROOTCONTROLSYSERRFATALERREN;
output CFGROOTCONTROLSYSERRNONFATALERREN;
output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
output CFGTRANSACTION;
output CFGTRANSACTIONTYPE;
output DBGSCLRA;
output DBGSCLRB;
output DBGSCLRC;
output DBGSCLRD;
output DBGSCLRE;
output DBGSCLRF;
output DBGSCLRG;
output DBGSCLRH;
output DBGSCLRI;
output DBGSCLRJ;
output DBGSCLRK;
output DRPRDY;
output LL2BADDLLPERR;
output LL2BADTLPERR;
output LL2PROTOCOLERR;
output LL2RECEIVERERR;
output LL2REPLAYROERR;
output LL2REPLAYTOERR;
output LL2SUSPENDOK;
output LL2TFCINIT1SEQ;
output LL2TFCINIT2SEQ;
output LL2TXIDLE;
output LNKCLKEN;
output MIMRXREN;
output MIMRXWEN;
output MIMTXREN;
output MIMTXWEN;
output PIPERX0POLARITY;
output PIPERX1POLARITY;
output PIPERX2POLARITY;
output PIPERX3POLARITY;
output PIPERX4POLARITY;
output PIPERX5POLARITY;
output PIPERX6POLARITY;
output PIPERX7POLARITY;
output PIPETX0COMPLIANCE;
output PIPETX0ELECIDLE;
output PIPETX1COMPLIANCE;
output PIPETX1ELECIDLE;
output PIPETX2COMPLIANCE;
output PIPETX2ELECIDLE;
output PIPETX3COMPLIANCE;
output PIPETX3ELECIDLE;
output PIPETX4COMPLIANCE;
output PIPETX4ELECIDLE;
output PIPETX5COMPLIANCE;
output PIPETX5ELECIDLE;
output PIPETX6COMPLIANCE;
output PIPETX6ELECIDLE;
output PIPETX7COMPLIANCE;
output PIPETX7ELECIDLE;
output PIPETXDEEMPH;
output PIPETXRATE;
output PIPETXRCVRDET;
output PIPETXRESET;
output PL2L0REQ;
output PL2LINKUP;
output PL2RECEIVERERR;
output PL2RECOVERY;
output PL2RXELECIDLE;
output PL2SUSPENDOK;
output PLDIRECTEDCHANGEDONE;
output PLLINKGEN2CAP;
output PLLINKPARTNERGEN2SUPPORTED;
output PLLINKUPCFGCAP;
output PLPHYLNKUPN;
output PLRECEIVEDHOTRST;
output PLSELLNKRATE;
output RECEIVEDFUNCLVLRSTN;
output TL2ASPMSUSPENDCREDITCHECKOK;
output TL2ASPMSUSPENDREQ;
output TL2ERRFCPE;
output TL2ERRMALFORMED;
output TL2ERRRXOVERFLOW;
output TL2PPMSUSPENDOK;
output TRNLNKUP;
output TRNRECRCERR;
output TRNREOF;
output TRNRERRFWD;
output TRNRSOF;
output TRNRSRCDSC;
output TRNRSRCRDY;
output TRNTCFGREQ;
output TRNTDLLPDSTRDY;
output TRNTERRDROP;
output USERRSTN;
output [11:0] DBGVECC;
output [11:0] PLDBGVEC;
output [11:0] TRNFCCPLD;
output [11:0] TRNFCNPD;
output [11:0] TRNFCPD;
output [127:0] TRNRD;
output [12:0] MIMRXRADDR;
output [12:0] MIMRXWADDR;
output [12:0] MIMTXRADDR;
output [12:0] MIMTXWADDR;
output [15:0] CFGMSGDATA;
output [15:0] DRPDO;
output [15:0] PIPETX0DATA;
output [15:0] PIPETX1DATA;
output [15:0] PIPETX2DATA;
output [15:0] PIPETX3DATA;
output [15:0] PIPETX4DATA;
output [15:0] PIPETX5DATA;
output [15:0] PIPETX6DATA;
output [15:0] PIPETX7DATA;
output [1:0] CFGLINKCONTROLASPMCONTROL;
output [1:0] CFGLINKSTATUSCURRENTSPEED;
output [1:0] CFGPMCSRPOWERSTATE;
output [1:0] PIPETX0CHARISK;
output [1:0] PIPETX0POWERDOWN;
output [1:0] PIPETX1CHARISK;
output [1:0] PIPETX1POWERDOWN;
output [1:0] PIPETX2CHARISK;
output [1:0] PIPETX2POWERDOWN;
output [1:0] PIPETX3CHARISK;
output [1:0] PIPETX3POWERDOWN;
output [1:0] PIPETX4CHARISK;
output [1:0] PIPETX4POWERDOWN;
output [1:0] PIPETX5CHARISK;
output [1:0] PIPETX5POWERDOWN;
output [1:0] PIPETX6CHARISK;
output [1:0] PIPETX6POWERDOWN;
output [1:0] PIPETX7CHARISK;
output [1:0] PIPETX7POWERDOWN;
output [1:0] PL2RXPMSTATE;
output [1:0] PLLANEREVERSALMODE;
output [1:0] PLRXPMSTATE;
output [1:0] PLSELLNKWIDTH;
output [1:0] TRNRDLLPSRCRDY;
output [1:0] TRNRREM;
output [2:0] CFGDEVCONTROLMAXPAYLOAD;
output [2:0] CFGDEVCONTROLMAXREADREQ;
output [2:0] CFGINTERRUPTMMENABLE;
output [2:0] CFGPCIELINKSTATE;
output [2:0] PIPETXMARGIN;
output [2:0] PLINITIALLINKWIDTH;
output [2:0] PLTXPMSTATE;
output [31:0] CFGMGMTDO;
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
output [3:0] TRNTDSTRDY;
output [4:0] LL2LINKSTATUS;
output [5:0] PLLTSSMSTATE;
output [5:0] TRNTBUFAV;
output [63:0] DBGVECA;
output [63:0] DBGVECB;
output [63:0] TL2ERRHDR;
output [63:0] TRNRDLLPDATA;
output [67:0] MIMRXWDATA;
output [68:0] MIMTXWDATA;
output [6:0] CFGTRANSACTIONADDR;
output [6:0] CFGVCTCVCMAP;
output [7:0] CFGINTERRUPTDO;
output [7:0] TRNFCCPLH;
output [7:0] TRNFCNPH;
output [7:0] TRNFCPH;
output [7:0] TRNRBARHIT;
input CFGERRACSN;
input CFGERRATOMICEGRESSBLOCKEDN;
input CFGERRCORN;
input CFGERRCPLABORTN;
input CFGERRCPLTIMEOUTN;
input CFGERRCPLUNEXPECTN;
input CFGERRECRCN;
input CFGERRINTERNALCORN;
input CFGERRINTERNALUNCORN;
input CFGERRLOCKEDN;
input CFGERRMALFORMEDN;
input CFGERRMCBLOCKEDN;
input CFGERRNORECOVERYN;
input CFGERRPOISONEDN;
input CFGERRPOSTEDN;
input CFGERRURN;
input CFGFORCECOMMONCLOCKOFF;
input CFGFORCEEXTENDEDSYNCON;
input CFGINTERRUPTASSERTN;
input CFGINTERRUPTN;
input CFGINTERRUPTSTATN;
input CFGMGMTRDENN;
input CFGMGMTWRENN;
input CFGMGMTWRREADONLYN;
input CFGMGMTWRRW1CASRWN;
input CFGPMFORCESTATEENN;
input CFGPMHALTASPML0SN;
input CFGPMHALTASPML1N;
input CFGPMSENDPMETON;
input CFGPMTURNOFFOKN;
input CFGPMWAKEN;
input CFGTRNPENDINGN;
input CMRSTN;
input CMSTICKYRSTN;
input DBGSUBMODE;
input DLRSTN;
input DRPCLK;
input DRPEN;
input DRPWE;
input FUNCLVLRSTN;
input LL2SENDASREQL1;
input LL2SENDENTERL1;
input LL2SENDENTERL23;
input LL2SENDPMACK;
input LL2SUSPENDNOW;
input LL2TLPRCV;
input PIPECLK;
input PIPERX0CHANISALIGNED;
input PIPERX0ELECIDLE;
input PIPERX0PHYSTATUS;
input PIPERX0VALID;
input PIPERX1CHANISALIGNED;
input PIPERX1ELECIDLE;
input PIPERX1PHYSTATUS;
input PIPERX1VALID;
input PIPERX2CHANISALIGNED;
input PIPERX2ELECIDLE;
input PIPERX2PHYSTATUS;
input PIPERX2VALID;
input PIPERX3CHANISALIGNED;
input PIPERX3ELECIDLE;
input PIPERX3PHYSTATUS;
input PIPERX3VALID;
input PIPERX4CHANISALIGNED;
input PIPERX4ELECIDLE;
input PIPERX4PHYSTATUS;
input PIPERX4VALID;
input PIPERX5CHANISALIGNED;
input PIPERX5ELECIDLE;
input PIPERX5PHYSTATUS;
input PIPERX5VALID;
input PIPERX6CHANISALIGNED;
input PIPERX6ELECIDLE;
input PIPERX6PHYSTATUS;
input PIPERX6VALID;
input PIPERX7CHANISALIGNED;
input PIPERX7ELECIDLE;
input PIPERX7PHYSTATUS;
input PIPERX7VALID;
input PLDIRECTEDLINKAUTON;
input PLDIRECTEDLINKSPEED;
input PLDIRECTEDLTSSMNEWVLD;
input PLDIRECTEDLTSSMSTALL;
input PLDOWNSTREAMDEEMPHSOURCE;
input PLRSTN;
input PLTRANSMITHOTRST;
input PLUPSTREAMPREFERDEEMPH;
input SYSRSTN;
input TL2ASPMSUSPENDCREDITCHECK;
input TL2PPMSUSPENDREQ;
input TLRSTN;
input TRNRDSTRDY;
input TRNRFCPRET;
input TRNRNPOK;
input TRNRNPREQ;
input TRNTCFGGNT;
input TRNTDLLPSRCRDY;
input TRNTECRCGEN;
input TRNTEOF;
input TRNTERRFWD;
input TRNTSOF;
input TRNTSRCDSC;
input TRNTSRCRDY;
input TRNTSTR;
input USERCLK2;
input USERCLK;
input [127:0] CFGERRAERHEADERLOG;
input [127:0] TRNTD;
input [15:0] CFGDEVID;
input [15:0] CFGSUBSYSID;
input [15:0] CFGSUBSYSVENDID;
input [15:0] CFGVENDID;
input [15:0] DRPDI;
input [15:0] PIPERX0DATA;
input [15:0] PIPERX1DATA;
input [15:0] PIPERX2DATA;
input [15:0] PIPERX3DATA;
input [15:0] PIPERX4DATA;
input [15:0] PIPERX5DATA;
input [15:0] PIPERX6DATA;
input [15:0] PIPERX7DATA;
input [1:0] CFGPMFORCESTATE;
input [1:0] DBGMODE;
input [1:0] PIPERX0CHARISK;
input [1:0] PIPERX1CHARISK;
input [1:0] PIPERX2CHARISK;
input [1:0] PIPERX3CHARISK;
input [1:0] PIPERX4CHARISK;
input [1:0] PIPERX5CHARISK;
input [1:0] PIPERX6CHARISK;
input [1:0] PIPERX7CHARISK;
input [1:0] PLDIRECTEDLINKCHANGE;
input [1:0] PLDIRECTEDLINKWIDTH;
input [1:0] TRNTREM;
input [2:0] CFGDSFUNCTIONNUMBER;
input [2:0] CFGFORCEMPS;
input [2:0] PIPERX0STATUS;
input [2:0] PIPERX1STATUS;
input [2:0] PIPERX2STATUS;
input [2:0] PIPERX3STATUS;
input [2:0] PIPERX4STATUS;
input [2:0] PIPERX5STATUS;
input [2:0] PIPERX6STATUS;
input [2:0] PIPERX7STATUS;
input [2:0] PLDBGMODE;
input [2:0] TRNFCSEL;
input [31:0] CFGMGMTDI;
input [31:0] TRNTDLLPDATA;
input [3:0] CFGMGMTBYTEENN;
input [47:0] CFGERRTLPCPLHEADER;
input [4:0] CFGAERINTERRUPTMSGNUM;
input [4:0] CFGDSDEVICENUMBER;
input [4:0] CFGPCIECAPINTERRUPTMSGNUM;
input [4:0] PL2DIRECTEDLSTATE;
input [5:0] PLDIRECTEDLTSSMNEW;
input [63:0] CFGDSN;
input [67:0] MIMRXRDATA;
input [68:0] MIMTXRDATA;
input [7:0] CFGDSBUSNUMBER;
input [7:0] CFGINTERRUPTDI;
input [7:0] CFGPORTNUMBER;
input [7:0] CFGREVID;
input [8:0] DRPADDR;
input [9:0] CFGMGMTDWADDR;
reg SIM_VERSION_BINARY;
reg [0:0] AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] AER_CAP_MULTIHEADER_BINARY;
reg [0:0] AER_CAP_ON_BINARY;
reg [0:0] AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY;
reg [0:0] ALLOW_X8_GEN2_BINARY;
reg [0:0] CMD_INTX_IMPLEMENTED_BINARY;
reg [0:0] CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY;
reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY;
reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY;
reg [0:0] DEV_CAP_EXT_TAG_SUPPORTED_BINARY;
reg [0:0] DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY;
reg [0:0] DEV_CAP_ROLE_BASED_ERROR_BINARY;
reg [0:0] DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY;
reg [0:0] DEV_CONTROL_EXT_TAG_DEFAULT_BINARY;
reg [0:0] DISABLE_ASPM_L1_TIMER_BINARY;
reg [0:0] DISABLE_BAR_FILTERING_BINARY;
reg [0:0] DISABLE_ERR_MSG_BINARY;
reg [0:0] DISABLE_ID_CHECK_BINARY;
reg [0:0] DISABLE_LANE_REVERSAL_BINARY;
reg [0:0] DISABLE_LOCKED_FILTER_BINARY;
reg [0:0] DISABLE_PPM_FILTER_BINARY;
reg [0:0] DISABLE_RX_POISONED_RESP_BINARY;
reg [0:0] DISABLE_RX_TC_FILTER_BINARY;
reg [0:0] DISABLE_SCRAMBLING_BINARY;
reg [0:0] DSN_CAP_ON_BINARY;
reg [0:0] ENABLE_RX_TD_ECRC_TRIM_BINARY;
reg [0:0] ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY;
reg [0:0] ENTER_RVRY_EI_L0_BINARY;
reg [0:0] EXIT_LOOPBACK_ON_EI_BINARY;
reg [0:0] INTERRUPT_STAT_AUTO_BINARY;
reg [0:0] IS_SWITCH_BINARY;
reg [0:0] LINK_CAP_ASPM_OPTIONALITY_BINARY;
reg [0:0] LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY;
reg [0:0] LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY;
reg [0:0] LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY;
reg [0:0] LINK_CAP_RSVD_23_BINARY;
reg [0:0] LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY;
reg [0:0] LINK_CONTROL_RCB_BINARY;
reg [0:0] LINK_CTRL2_DEEMPHASIS_BINARY;
reg [0:0] LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY;
reg [0:0] LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY;
reg [0:0] LL_ACK_TIMEOUT_EN_BINARY;
reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY;
reg [0:0] MPS_FORCE_BINARY;
reg [0:0] MSIX_CAP_ON_BINARY;
reg [0:0] MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY;
reg [0:0] MSI_CAP_MULTIMSG_EXTENSION_BINARY;
reg [0:0] MSI_CAP_ON_BINARY;
reg [0:0] MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY;
reg [0:0] PCIE_CAP_ON_BINARY;
reg [0:0] PCIE_CAP_SLOT_IMPLEMENTED_BINARY;
reg [0:0] PL_FAST_TRAIN_BINARY;
reg [0:0] PM_ASPML0S_TIMEOUT_EN_BINARY;
reg [0:0] PM_ASPM_FASTEXIT_BINARY;
reg [0:0] PM_CAP_D1SUPPORT_BINARY;
reg [0:0] PM_CAP_D2SUPPORT_BINARY;
reg [0:0] PM_CAP_DSI_BINARY;
reg [0:0] PM_CAP_ON_BINARY;
reg [0:0] PM_CAP_PME_CLOCK_BINARY;
reg [0:0] PM_CAP_RSVD_04_BINARY;
reg [0:0] PM_CSR_B2B3_BINARY;
reg [0:0] PM_CSR_BPCCEN_BINARY;
reg [0:0] PM_CSR_NOSOFTRST_BINARY;
reg [0:0] PM_MF_BINARY;
reg [0:0] RBAR_CAP_ON_BINARY;
reg [0:0] RECRC_CHK_TRIM_BINARY;
reg [0:0] ROOT_CAP_CRS_SW_VISIBILITY_BINARY;
reg [0:0] SELECT_DLL_IF_BINARY;
reg [0:0] SLOT_CAP_ATT_BUTTON_PRESENT_BINARY;
reg [0:0] SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY;
reg [0:0] SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY;
reg [0:0] SLOT_CAP_HOTPLUG_CAPABLE_BINARY;
reg [0:0] SLOT_CAP_HOTPLUG_SURPRISE_BINARY;
reg [0:0] SLOT_CAP_MRL_SENSOR_PRESENT_BINARY;
reg [0:0] SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY;
reg [0:0] SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY;
reg [0:0] SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY;
reg [0:0] SPARE_BIT0_BINARY;
reg [0:0] SPARE_BIT1_BINARY;
reg [0:0] SPARE_BIT2_BINARY;
reg [0:0] SPARE_BIT3_BINARY;
reg [0:0] SPARE_BIT4_BINARY;
reg [0:0] SPARE_BIT5_BINARY;
reg [0:0] SPARE_BIT6_BINARY;
reg [0:0] SPARE_BIT7_BINARY;
reg [0:0] SPARE_BIT8_BINARY;
reg [0:0] SSL_MESSAGE_AUTO_BINARY;
reg [0:0] TECRC_EP_INV_BINARY;
reg [0:0] TL_RBYPASS_BINARY;
reg [0:0] TL_RX_RAM_RADDR_LATENCY_BINARY;
reg [0:0] TL_RX_RAM_WRITE_LATENCY_BINARY;
reg [0:0] TL_TFC_DISABLE_BINARY;
reg [0:0] TL_TX_CHECKS_DISABLE_BINARY;
reg [0:0] TL_TX_RAM_RADDR_LATENCY_BINARY;
reg [0:0] TL_TX_RAM_WRITE_LATENCY_BINARY;
reg [0:0] TRN_DW_BINARY;
reg [0:0] TRN_NP_FC_BINARY;
reg [0:0] UPCONFIG_CAPABLE_BINARY;
reg [0:0] UPSTREAM_FACING_BINARY;
reg [0:0] UR_ATOMIC_BINARY;
reg [0:0] UR_CFG1_BINARY;
reg [0:0] UR_INV_REQ_BINARY;
reg [0:0] UR_PRS_RESPONSE_BINARY;
reg [0:0] USER_CLK2_DIV2_BINARY;
reg [0:0] USE_RID_PINS_BINARY;
reg [0:0] VC0_CPL_INFINITE_BINARY;
reg [0:0] VC_CAP_ON_BINARY;
reg [0:0] VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY;
reg [0:0] VSEC_CAP_IS_LINK_VISIBLE_BINARY;
reg [0:0] VSEC_CAP_ON_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_CD_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_NPD_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_PD_BINARY;
reg [1:0] CFG_ECRC_ERR_CPLSTAT_BINARY;
reg [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY;
reg [1:0] DEV_CAP_RSVD_17_16_BINARY;
reg [1:0] LINK_CAP_ASPM_SUPPORT_BINARY;
reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY;
reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY;
reg [1:0] PCIE_CAP_RSVD_15_14_BINARY;
reg [1:0] PM_ASPML0S_TIMEOUT_FUNC_BINARY;
reg [1:0] RECRC_CHK_BINARY;
reg [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY;
reg [1:0] TL_RX_RAM_RDATA_LATENCY_BINARY;
reg [1:0] TL_TX_RAM_RDATA_LATENCY_BINARY;
reg [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY;
reg [2:0] DEV_CAP_ENDPOINT_L1_LATENCY_BINARY;
reg [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY;
reg [2:0] DEV_CAP_RSVD_14_12_BINARY;
reg [2:0] DEV_CAP_RSVD_31_29_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] PL_AUTO_CONFIG_BINARY;
reg [2:0] PM_CAP_AUXCURRENT_BINARY;
reg [2:0] PM_CAP_VERSION_BINARY;
reg [2:0] USER_CLK_FREQ_BINARY;
reg [3:0] PCIE_REVISION_BINARY;
reg [4:0] VC0_TX_LASTPACKET_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_CH_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_NPH_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_PH_BINARY;
reg [7:0] N_FTS_COMCLK_GEN1_BINARY;
reg [7:0] N_FTS_COMCLK_GEN2_BINARY;
reg [7:0] N_FTS_GEN1_BINARY;
reg [7:0] N_FTS_GEN2_BINARY;
// tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_CHECK_CAPABLE);
$finish;
end
endcase
case (AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_GEN_CAPABLE);
$finish;
end
endcase
case (AER_CAP_MULTIHEADER)
"FALSE" : AER_CAP_MULTIHEADER_BINARY = 1'b0;
"TRUE" : AER_CAP_MULTIHEADER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_MULTIHEADER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_MULTIHEADER);
$finish;
end
endcase
case (AER_CAP_ON)
"FALSE" : AER_CAP_ON_BINARY = 1'b0;
"TRUE" : AER_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ON);
$finish;
end
endcase
case (AER_CAP_PERMIT_ROOTERR_UPDATE)
"TRUE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b1;
"FALSE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_PERMIT_ROOTERR_UPDATE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AER_CAP_PERMIT_ROOTERR_UPDATE);
$finish;
end
endcase
case (ALLOW_X8_GEN2)
"FALSE" : ALLOW_X8_GEN2_BINARY = 1'b0;
"TRUE" : ALLOW_X8_GEN2_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALLOW_X8_GEN2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALLOW_X8_GEN2);
$finish;
end
endcase
case (CMD_INTX_IMPLEMENTED)
"TRUE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b1;
"FALSE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CMD_INTX_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CMD_INTX_IMPLEMENTED);
$finish;
end
endcase
case (CPL_TIMEOUT_DISABLE_SUPPORTED)
"FALSE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b0;
"TRUE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CPL_TIMEOUT_DISABLE_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CPL_TIMEOUT_DISABLE_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_ARI_FORWARDING_SUPPORTED)
"FALSE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ARI_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ARI_FORWARDING_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_CAS128_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_CAS128_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_CAS128_COMPLETER_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED)
"FALSE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED)
"FALSE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_LTR_MECHANISM_SUPPORTED)
"FALSE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_LTR_MECHANISM_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_LTR_MECHANISM_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING)
"FALSE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b0;
"TRUE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING);
$finish;
end
endcase
case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE)
"TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b1;
"FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE);
$finish;
end
endcase
case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE)
"TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b1;
"FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE);
$finish;
end
endcase
case (DEV_CAP_EXT_TAG_SUPPORTED)
"TRUE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1;
"FALSE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_EXT_TAG_SUPPORTED);
$finish;
end
endcase
case (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE)
"FALSE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0;
"TRUE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE);
$finish;
end
endcase
case (DEV_CAP_ROLE_BASED_ERROR)
"TRUE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b1;
"FALSE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ROLE_BASED_ERROR on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ROLE_BASED_ERROR);
$finish;
end
endcase
case (DEV_CONTROL_AUX_POWER_SUPPORTED)
"FALSE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CONTROL_AUX_POWER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_AUX_POWER_SUPPORTED);
$finish;
end
endcase
case (DEV_CONTROL_EXT_TAG_DEFAULT)
"FALSE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b0;
"TRUE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CONTROL_EXT_TAG_DEFAULT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_EXT_TAG_DEFAULT);
$finish;
end
endcase
case (DISABLE_ASPM_L1_TIMER)
"FALSE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b0;
"TRUE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ASPM_L1_TIMER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ASPM_L1_TIMER);
$finish;
end
endcase
case (DISABLE_BAR_FILTERING)
"FALSE" : DISABLE_BAR_FILTERING_BINARY = 1'b0;
"TRUE" : DISABLE_BAR_FILTERING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_BAR_FILTERING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_BAR_FILTERING);
$finish;
end
endcase
case (DISABLE_ERR_MSG)
"FALSE" : DISABLE_ERR_MSG_BINARY = 1'b0;
"TRUE" : DISABLE_ERR_MSG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ERR_MSG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ERR_MSG);
$finish;
end
endcase
case (DISABLE_ID_CHECK)
"FALSE" : DISABLE_ID_CHECK_BINARY = 1'b0;
"TRUE" : DISABLE_ID_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ID_CHECK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ID_CHECK);
$finish;
end
endcase
case (DISABLE_LANE_REVERSAL)
"FALSE" : DISABLE_LANE_REVERSAL_BINARY = 1'b0;
"TRUE" : DISABLE_LANE_REVERSAL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_LANE_REVERSAL on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LANE_REVERSAL);
$finish;
end
endcase
case (DISABLE_LOCKED_FILTER)
"FALSE" : DISABLE_LOCKED_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_LOCKED_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_LOCKED_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LOCKED_FILTER);
$finish;
end
endcase
case (DISABLE_PPM_FILTER)
"FALSE" : DISABLE_PPM_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_PPM_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_PPM_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_PPM_FILTER);
$finish;
end
endcase
case (DISABLE_RX_POISONED_RESP)
"FALSE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b0;
"TRUE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_RX_POISONED_RESP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_POISONED_RESP);
$finish;
end
endcase
case (DISABLE_RX_TC_FILTER)
"FALSE" : DISABLE_RX_TC_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_RX_TC_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_RX_TC_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_TC_FILTER);
$finish;
end
endcase
case (DISABLE_SCRAMBLING)
"FALSE" : DISABLE_SCRAMBLING_BINARY = 1'b0;
"TRUE" : DISABLE_SCRAMBLING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_SCRAMBLING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_SCRAMBLING);
$finish;
end
endcase
case (DSN_CAP_ON)
"TRUE" : DSN_CAP_ON_BINARY = 1'b1;
"FALSE" : DSN_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DSN_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DSN_CAP_ON);
$finish;
end
endcase
case (ENABLE_RX_TD_ECRC_TRIM)
"FALSE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b0;
"TRUE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ENABLE_RX_TD_ECRC_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENABLE_RX_TD_ECRC_TRIM);
$finish;
end
endcase
case (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED)
"FALSE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b0;
"TRUE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED);
$finish;
end
endcase
case (ENTER_RVRY_EI_L0)
"TRUE" : ENTER_RVRY_EI_L0_BINARY = 1'b1;
"FALSE" : ENTER_RVRY_EI_L0_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ENTER_RVRY_EI_L0 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ENTER_RVRY_EI_L0);
$finish;
end
endcase
case (EXIT_LOOPBACK_ON_EI)
"TRUE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b1;
"FALSE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute EXIT_LOOPBACK_ON_EI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", EXIT_LOOPBACK_ON_EI);
$finish;
end
endcase
case (INTERRUPT_STAT_AUTO)
"TRUE" : INTERRUPT_STAT_AUTO_BINARY = 1'b1;
"FALSE" : INTERRUPT_STAT_AUTO_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute INTERRUPT_STAT_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", INTERRUPT_STAT_AUTO);
$finish;
end
endcase
case (IS_SWITCH)
"FALSE" : IS_SWITCH_BINARY = 1'b0;
"TRUE" : IS_SWITCH_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute IS_SWITCH on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", IS_SWITCH);
$finish;
end
endcase
case (LINK_CAP_ASPM_OPTIONALITY)
"TRUE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b1;
"FALSE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_OPTIONALITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_CAP_ASPM_OPTIONALITY);
$finish;
end
endcase
case (LINK_CAP_CLOCK_POWER_MANAGEMENT)
"FALSE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b0;
"TRUE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_CLOCK_POWER_MANAGEMENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_CLOCK_POWER_MANAGEMENT);
$finish;
end
endcase
case (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP)
"FALSE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b0;
"TRUE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP);
$finish;
end
endcase
case (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP)
"FALSE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b0;
"TRUE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP);
$finish;
end
endcase
case (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE)
"FALSE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b0;
"TRUE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE);
$finish;
end
endcase
case (LINK_CTRL2_DEEMPHASIS)
"FALSE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b0;
"TRUE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CTRL2_DEEMPHASIS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_DEEMPHASIS);
$finish;
end
endcase
case (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE)
"FALSE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b0;
"TRUE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE);
$finish;
end
endcase
case (LINK_STATUS_SLOT_CLOCK_CONFIG)
"TRUE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1;
"FALSE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_STATUS_SLOT_CLOCK_CONFIG);
$finish;
end
endcase
case (LL_ACK_TIMEOUT_EN)
"FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN);
$finish;
end
endcase
case (LL_REPLAY_TIMEOUT_EN)
"FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN);
$finish;
end
endcase
case (MPS_FORCE)
"FALSE" : MPS_FORCE_BINARY = 1'b0;
"TRUE" : MPS_FORCE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MPS_FORCE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MPS_FORCE);
$finish;
end
endcase
case (MSIX_CAP_ON)
"FALSE" : MSIX_CAP_ON_BINARY = 1'b0;
"TRUE" : MSIX_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSIX_CAP_ON);
$finish;
end
endcase
case (MSI_CAP_64_BIT_ADDR_CAPABLE)
"TRUE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b1;
"FALSE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_64_BIT_ADDR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_64_BIT_ADDR_CAPABLE);
$finish;
end
endcase
case (MSI_CAP_ON)
"FALSE" : MSI_CAP_ON_BINARY = 1'b0;
"TRUE" : MSI_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSI_CAP_ON);
$finish;
end
endcase
case (MSI_CAP_PER_VECTOR_MASKING_CAPABLE)
"TRUE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b1;
"FALSE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_PER_VECTOR_MASKING_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_PER_VECTOR_MASKING_CAPABLE);
$finish;
end
endcase
case (PCIE_CAP_ON)
"TRUE" : PCIE_CAP_ON_BINARY = 1'b1;
"FALSE" : PCIE_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PCIE_CAP_ON);
$finish;
end
endcase
case (PCIE_CAP_SLOT_IMPLEMENTED)
"FALSE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b0;
"TRUE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_SLOT_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCIE_CAP_SLOT_IMPLEMENTED);
$finish;
end
endcase
case (PL_FAST_TRAIN)
"FALSE" : PL_FAST_TRAIN_BINARY = 1'b0;
"TRUE" : PL_FAST_TRAIN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_FAST_TRAIN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_FAST_TRAIN);
$finish;
end
endcase
case (PM_ASPML0S_TIMEOUT_EN)
"FALSE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPML0S_TIMEOUT_EN);
$finish;
end
endcase
case (PM_ASPM_FASTEXIT)
"FALSE" : PM_ASPM_FASTEXIT_BINARY = 1'b0;
"TRUE" : PM_ASPM_FASTEXIT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ASPM_FASTEXIT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPM_FASTEXIT);
$finish;
end
endcase
case (PM_CAP_D1SUPPORT)
"TRUE" : PM_CAP_D1SUPPORT_BINARY = 1'b1;
"FALSE" : PM_CAP_D1SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_D1SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D1SUPPORT);
$finish;
end
endcase
case (PM_CAP_D2SUPPORT)
"TRUE" : PM_CAP_D2SUPPORT_BINARY = 1'b1;
"FALSE" : PM_CAP_D2SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_D2SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D2SUPPORT);
$finish;
end
endcase
case (PM_CAP_DSI)
"FALSE" : PM_CAP_DSI_BINARY = 1'b0;
"TRUE" : PM_CAP_DSI_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_DSI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_DSI);
$finish;
end
endcase
case (PM_CAP_ON)
"TRUE" : PM_CAP_ON_BINARY = 1'b1;
"FALSE" : PM_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_ON);
$finish;
end
endcase
case (PM_CAP_PME_CLOCK)
"FALSE" : PM_CAP_PME_CLOCK_BINARY = 1'b0;
"TRUE" : PM_CAP_PME_CLOCK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_PME_CLOCK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_PME_CLOCK);
$finish;
end
endcase
case (PM_CSR_B2B3)
"FALSE" : PM_CSR_B2B3_BINARY = 1'b0;
"TRUE" : PM_CSR_B2B3_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_B2B3 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_B2B3);
$finish;
end
endcase
case (PM_CSR_BPCCEN)
"FALSE" : PM_CSR_BPCCEN_BINARY = 1'b0;
"TRUE" : PM_CSR_BPCCEN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_BPCCEN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_BPCCEN);
$finish;
end
endcase
case (PM_CSR_NOSOFTRST)
"TRUE" : PM_CSR_NOSOFTRST_BINARY = 1'b1;
"FALSE" : PM_CSR_NOSOFTRST_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_NOSOFTRST on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CSR_NOSOFTRST);
$finish;
end
endcase
case (PM_MF)
"FALSE" : PM_MF_BINARY = 1'b0;
"TRUE" : PM_MF_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_MF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_MF);
$finish;
end
endcase
case (RBAR_CAP_ON)
"FALSE" : RBAR_CAP_ON_BINARY = 1'b0;
"TRUE" : RBAR_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RBAR_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RBAR_CAP_ON);
$finish;
end
endcase
case (RECRC_CHK_TRIM)
"FALSE" : RECRC_CHK_TRIM_BINARY = 1'b0;
"TRUE" : RECRC_CHK_TRIM_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RECRC_CHK_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RECRC_CHK_TRIM);
$finish;
end
endcase
case (ROOT_CAP_CRS_SW_VISIBILITY)
"FALSE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b0;
"TRUE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ROOT_CAP_CRS_SW_VISIBILITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ROOT_CAP_CRS_SW_VISIBILITY);
$finish;
end
endcase
case (SELECT_DLL_IF)
"FALSE" : SELECT_DLL_IF_BINARY = 1'b0;
"TRUE" : SELECT_DLL_IF_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SELECT_DLL_IF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SELECT_DLL_IF);
$finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"1.2" : SIM_VERSION_BINARY = 0;
"1.3" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION);
$finish;
end
endcase
case (SLOT_CAP_ATT_BUTTON_PRESENT)
"FALSE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_BUTTON_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_BUTTON_PRESENT);
$finish;
end
endcase
case (SLOT_CAP_ATT_INDICATOR_PRESENT)
"FALSE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_INDICATOR_PRESENT);
$finish;
end
endcase
case (SLOT_CAP_ELEC_INTERLOCK_PRESENT)
"FALSE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ELEC_INTERLOCK_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ELEC_INTERLOCK_PRESENT);
$finish;
end
endcase
case (SLOT_CAP_HOTPLUG_CAPABLE)
"FALSE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b0;
"TRUE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_CAPABLE);
$finish;
end
endcase
case (SLOT_CAP_HOTPLUG_SURPRISE)
"FALSE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b0;
"TRUE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_SURPRISE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_SURPRISE);
$finish;
end
endcase
case (SLOT_CAP_MRL_SENSOR_PRESENT)
"FALSE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_MRL_SENSOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_MRL_SENSOR_PRESENT);
$finish;
end
endcase
case (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT)
"FALSE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_NO_CMD_COMPLETED_SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_NO_CMD_COMPLETED_SUPPORT);
$finish;
end
endcase
case (SLOT_CAP_POWER_CONTROLLER_PRESENT)
"FALSE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_CONTROLLER_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_CONTROLLER_PRESENT);
$finish;
end
endcase
case (SLOT_CAP_POWER_INDICATOR_PRESENT)
"FALSE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_INDICATOR_PRESENT);
$finish;
end
endcase
case (SSL_MESSAGE_AUTO)
"FALSE" : SSL_MESSAGE_AUTO_BINARY = 1'b0;
"TRUE" : SSL_MESSAGE_AUTO_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SSL_MESSAGE_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SSL_MESSAGE_AUTO);
$finish;
end
endcase
case (TECRC_EP_INV)
"FALSE" : TECRC_EP_INV_BINARY = 1'b0;
"TRUE" : TECRC_EP_INV_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TECRC_EP_INV on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TECRC_EP_INV);
$finish;
end
endcase
case (TL_RBYPASS)
"FALSE" : TL_RBYPASS_BINARY = 1'b0;
"TRUE" : TL_RBYPASS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_RBYPASS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_RBYPASS);
$finish;
end
endcase
case (TL_TFC_DISABLE)
"FALSE" : TL_TFC_DISABLE_BINARY = 1'b0;
"TRUE" : TL_TFC_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TFC_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TFC_DISABLE);
$finish;
end
endcase
case (TL_TX_CHECKS_DISABLE)
"FALSE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b0;
"TRUE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TX_CHECKS_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TX_CHECKS_DISABLE);
$finish;
end
endcase
case (TRN_DW)
"FALSE" : TRN_DW_BINARY = 1'b0;
"TRUE" : TRN_DW_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TRN_DW on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_DW);
$finish;
end
endcase
case (TRN_NP_FC)
"FALSE" : TRN_NP_FC_BINARY = 1'b0;
"TRUE" : TRN_NP_FC_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TRN_NP_FC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_NP_FC);
$finish;
end
endcase
case (UPCONFIG_CAPABLE)
"TRUE" : UPCONFIG_CAPABLE_BINARY = 1'b1;
"FALSE" : UPCONFIG_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UPCONFIG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPCONFIG_CAPABLE);
$finish;
end
endcase
case (UPSTREAM_FACING)
"TRUE" : UPSTREAM_FACING_BINARY = 1'b1;
"FALSE" : UPSTREAM_FACING_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UPSTREAM_FACING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPSTREAM_FACING);
$finish;
end
endcase
case (UR_ATOMIC)
"TRUE" : UR_ATOMIC_BINARY = 1'b1;
"FALSE" : UR_ATOMIC_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_ATOMIC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_ATOMIC);
$finish;
end
endcase
case (UR_CFG1)
"TRUE" : UR_CFG1_BINARY = 1'b1;
"FALSE" : UR_CFG1_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_CFG1 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_CFG1);
$finish;
end
endcase
case (UR_INV_REQ)
"TRUE" : UR_INV_REQ_BINARY = 1'b1;
"FALSE" : UR_INV_REQ_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_INV_REQ on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_INV_REQ);
$finish;
end
endcase
case (UR_PRS_RESPONSE)
"TRUE" : UR_PRS_RESPONSE_BINARY = 1'b1;
"FALSE" : UR_PRS_RESPONSE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_PRS_RESPONSE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_PRS_RESPONSE);
$finish;
end
endcase
case (USER_CLK2_DIV2)
"FALSE" : USER_CLK2_DIV2_BINARY = 1'b0;
"TRUE" : USER_CLK2_DIV2_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute USER_CLK2_DIV2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USER_CLK2_DIV2);
$finish;
end
endcase
case (USE_RID_PINS)
"FALSE" : USE_RID_PINS_BINARY = 1'b0;
"TRUE" : USE_RID_PINS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute USE_RID_PINS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USE_RID_PINS);
$finish;
end
endcase
case (VC0_CPL_INFINITE)
"TRUE" : VC0_CPL_INFINITE_BINARY = 1'b1;
"FALSE" : VC0_CPL_INFINITE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VC0_CPL_INFINITE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VC0_CPL_INFINITE);
$finish;
end
endcase
case (VC_CAP_ON)
"FALSE" : VC_CAP_ON_BINARY = 1'b0;
"TRUE" : VC_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_ON);
$finish;
end
endcase
case (VC_CAP_REJECT_SNOOP_TRANSACTIONS)
"FALSE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b0;
"TRUE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VC_CAP_REJECT_SNOOP_TRANSACTIONS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_REJECT_SNOOP_TRANSACTIONS);
$finish;
end
endcase
case (VSEC_CAP_IS_LINK_VISIBLE)
"TRUE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b1;
"FALSE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VSEC_CAP_IS_LINK_VISIBLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VSEC_CAP_IS_LINK_VISIBLE);
$finish;
end
endcase
case (VSEC_CAP_ON)
"FALSE" : VSEC_CAP_ON_BINARY = 1'b0;
"TRUE" : VSEC_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VSEC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VSEC_CAP_ON);
$finish;
end
endcase
if ((CFG_ECRC_ERR_CPLSTAT >= 0) && (CFG_ECRC_ERR_CPLSTAT <= 3))
CFG_ECRC_ERR_CPLSTAT_BINARY = CFG_ECRC_ERR_CPLSTAT;
else begin
$display("Attribute Syntax Error : The Attribute CFG_ECRC_ERR_CPLSTAT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", CFG_ECRC_ERR_CPLSTAT);
$finish;
end
if ((DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L0S_LATENCY <= 7))
DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = DEV_CAP_ENDPOINT_L0S_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L0S_LATENCY);
$finish;
end
if ((DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L1_LATENCY <= 7))
DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = DEV_CAP_ENDPOINT_L1_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L1_LATENCY);
$finish;
end
if ((DEV_CAP_MAX_PAYLOAD_SUPPORTED >= 0) && (DEV_CAP_MAX_PAYLOAD_SUPPORTED <= 7))
DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY = DEV_CAP_MAX_PAYLOAD_SUPPORTED;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_MAX_PAYLOAD_SUPPORTED on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_MAX_PAYLOAD_SUPPORTED);
$finish;
end
if ((DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT >= 0) && (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT <= 3))
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY = DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT);
$finish;
end
if ((DEV_CAP_RSVD_14_12 >= 0) && (DEV_CAP_RSVD_14_12 <= 7))
DEV_CAP_RSVD_14_12_BINARY = DEV_CAP_RSVD_14_12;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_14_12 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_14_12);
$finish;
end
if ((DEV_CAP_RSVD_17_16 >= 0) && (DEV_CAP_RSVD_17_16 <= 3))
DEV_CAP_RSVD_17_16_BINARY = DEV_CAP_RSVD_17_16;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_17_16 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_RSVD_17_16);
$finish;
end
if ((DEV_CAP_RSVD_31_29 >= 0) && (DEV_CAP_RSVD_31_29 <= 7))
DEV_CAP_RSVD_31_29_BINARY = DEV_CAP_RSVD_31_29;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_31_29 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_31_29);
$finish;
end
if ((LINK_CAP_ASPM_SUPPORT >= 0) && (LINK_CAP_ASPM_SUPPORT <= 3))
LINK_CAP_ASPM_SUPPORT_BINARY = LINK_CAP_ASPM_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LINK_CAP_ASPM_SUPPORT);
$finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1);
$finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2);
$finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN1);
$finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN2);
$finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7))
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1);
$finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7))
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2);
$finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7))
LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN1);
$finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7))
LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN2);
$finish;
end
if ((LINK_CAP_RSVD_23 >= 0) && (LINK_CAP_RSVD_23 <= 1))
LINK_CAP_RSVD_23_BINARY = LINK_CAP_RSVD_23;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_RSVD_23 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CAP_RSVD_23);
$finish;
end
if ((LINK_CONTROL_RCB >= 0) && (LINK_CONTROL_RCB <= 1))
LINK_CONTROL_RCB_BINARY = LINK_CONTROL_RCB;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CONTROL_RCB on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CONTROL_RCB);
$finish;
end
if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3))
LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC);
$finish;
end
if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3))
LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC);
$finish;
end
if ((MSIX_CAP_PBA_BIR >= 0) && (MSIX_CAP_PBA_BIR <= 7))
MSIX_CAP_PBA_BIR_BINARY = MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_PBA_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_PBA_BIR);
$finish;
end
if ((MSIX_CAP_TABLE_BIR >= 0) && (MSIX_CAP_TABLE_BIR <= 7))
MSIX_CAP_TABLE_BIR_BINARY = MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_TABLE_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_TABLE_BIR);
$finish;
end
if ((MSI_CAP_MULTIMSGCAP >= 0) && (MSI_CAP_MULTIMSGCAP <= 7))
MSI_CAP_MULTIMSGCAP_BINARY = MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSGCAP on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((MSI_CAP_MULTIMSG_EXTENSION >= 0) && (MSI_CAP_MULTIMSG_EXTENSION <= 1))
MSI_CAP_MULTIMSG_EXTENSION_BINARY = MSI_CAP_MULTIMSG_EXTENSION;
else begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSG_EXTENSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", MSI_CAP_MULTIMSG_EXTENSION);
$finish;
end
if ((N_FTS_COMCLK_GEN1 >= 0) && (N_FTS_COMCLK_GEN1 <= 255))
N_FTS_COMCLK_GEN1_BINARY = N_FTS_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN1);
$finish;
end
if ((N_FTS_COMCLK_GEN2 >= 0) && (N_FTS_COMCLK_GEN2 <= 255))
N_FTS_COMCLK_GEN2_BINARY = N_FTS_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN2);
$finish;
end
if ((N_FTS_GEN1 >= 0) && (N_FTS_GEN1 <= 255))
N_FTS_GEN1_BINARY = N_FTS_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN1);
$finish;
end
if ((N_FTS_GEN2 >= 0) && (N_FTS_GEN2 <= 255))
N_FTS_GEN2_BINARY = N_FTS_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN2);
$finish;
end
if ((PCIE_CAP_RSVD_15_14 >= 0) && (PCIE_CAP_RSVD_15_14 <= 3))
PCIE_CAP_RSVD_15_14_BINARY = PCIE_CAP_RSVD_15_14;
else begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_RSVD_15_14 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PCIE_CAP_RSVD_15_14);
$finish;
end
if ((PCIE_REVISION >= 0) && (PCIE_REVISION <= 15))
PCIE_REVISION_BINARY = PCIE_REVISION;
else begin
$display("Attribute Syntax Error : The Attribute PCIE_REVISION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", PCIE_REVISION);
$finish;
end
if ((PL_AUTO_CONFIG >= 0) && (PL_AUTO_CONFIG <= 7))
PL_AUTO_CONFIG_BINARY = PL_AUTO_CONFIG;
else begin
$display("Attribute Syntax Error : The Attribute PL_AUTO_CONFIG on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PL_AUTO_CONFIG);
$finish;
end
if ((PM_ASPML0S_TIMEOUT_FUNC >= 0) && (PM_ASPML0S_TIMEOUT_FUNC <= 3))
PM_ASPML0S_TIMEOUT_FUNC_BINARY = PM_ASPML0S_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PM_ASPML0S_TIMEOUT_FUNC);
$finish;
end
if ((PM_CAP_AUXCURRENT >= 0) && (PM_CAP_AUXCURRENT <= 7))
PM_CAP_AUXCURRENT_BINARY = PM_CAP_AUXCURRENT;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_AUXCURRENT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_AUXCURRENT);
$finish;
end
if ((PM_CAP_RSVD_04 >= 0) && (PM_CAP_RSVD_04 <= 1))
PM_CAP_RSVD_04_BINARY = PM_CAP_RSVD_04;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_RSVD_04 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", PM_CAP_RSVD_04);
$finish;
end
if ((PM_CAP_VERSION >= 0) && (PM_CAP_VERSION <= 7))
PM_CAP_VERSION_BINARY = PM_CAP_VERSION;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_VERSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_VERSION);
$finish;
end
if ((RECRC_CHK >= 0) && (RECRC_CHK <= 3))
RECRC_CHK_BINARY = RECRC_CHK;
else begin
$display("Attribute Syntax Error : The Attribute RECRC_CHK on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", RECRC_CHK);
$finish;
end
if ((SLOT_CAP_SLOT_POWER_LIMIT_SCALE >= 0) && (SLOT_CAP_SLOT_POWER_LIMIT_SCALE <= 3))
SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY = SLOT_CAP_SLOT_POWER_LIMIT_SCALE;
else begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_SLOT_POWER_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", SLOT_CAP_SLOT_POWER_LIMIT_SCALE);
$finish;
end
if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1))
SPARE_BIT0_BINARY = SPARE_BIT0;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0);
$finish;
end
if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1))
SPARE_BIT1_BINARY = SPARE_BIT1;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1);
$finish;
end
if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1))
SPARE_BIT2_BINARY = SPARE_BIT2;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2);
$finish;
end
if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1))
SPARE_BIT3_BINARY = SPARE_BIT3;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3);
$finish;
end
if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1))
SPARE_BIT4_BINARY = SPARE_BIT4;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4);
$finish;
end
if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1))
SPARE_BIT5_BINARY = SPARE_BIT5;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5);
$finish;
end
if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1))
SPARE_BIT6_BINARY = SPARE_BIT6;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6);
$finish;
end
if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1))
SPARE_BIT7_BINARY = SPARE_BIT7;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7);
$finish;
end
if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1))
SPARE_BIT8_BINARY = SPARE_BIT8;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8);
$finish;
end
if ((TL_RX_RAM_RADDR_LATENCY >= 0) && (TL_RX_RAM_RADDR_LATENCY <= 1))
TL_RX_RAM_RADDR_LATENCY_BINARY = TL_RX_RAM_RADDR_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_RADDR_LATENCY);
$finish;
end
if ((TL_RX_RAM_RDATA_LATENCY >= 0) && (TL_RX_RAM_RDATA_LATENCY <= 3))
TL_RX_RAM_RDATA_LATENCY_BINARY = TL_RX_RAM_RDATA_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_RX_RAM_RDATA_LATENCY);
$finish;
end
if ((TL_RX_RAM_WRITE_LATENCY >= 0) && (TL_RX_RAM_WRITE_LATENCY <= 1))
TL_RX_RAM_WRITE_LATENCY_BINARY = TL_RX_RAM_WRITE_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_WRITE_LATENCY);
$finish;
end
if ((TL_TX_RAM_RADDR_LATENCY >= 0) && (TL_TX_RAM_RADDR_LATENCY <= 1))
TL_TX_RAM_RADDR_LATENCY_BINARY = TL_TX_RAM_RADDR_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_RADDR_LATENCY);
$finish;
end
if ((TL_TX_RAM_RDATA_LATENCY >= 0) && (TL_TX_RAM_RDATA_LATENCY <= 3))
TL_TX_RAM_RDATA_LATENCY_BINARY = TL_TX_RAM_RDATA_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_TX_RAM_RDATA_LATENCY);
$finish;
end
if ((TL_TX_RAM_WRITE_LATENCY >= 0) && (TL_TX_RAM_WRITE_LATENCY <= 1))
TL_TX_RAM_WRITE_LATENCY_BINARY = TL_TX_RAM_WRITE_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_WRITE_LATENCY);
$finish;
end
if ((USER_CLK_FREQ >= 0) && (USER_CLK_FREQ <= 7))
USER_CLK_FREQ_BINARY = USER_CLK_FREQ;
else begin
$display("Attribute Syntax Error : The Attribute USER_CLK_FREQ on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", USER_CLK_FREQ);
$finish;
end
if ((VC0_TOTAL_CREDITS_CD >= 0) && (VC0_TOTAL_CREDITS_CD <= 2047))
VC0_TOTAL_CREDITS_CD_BINARY = VC0_TOTAL_CREDITS_CD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_CD);
$finish;
end
if ((VC0_TOTAL_CREDITS_CH >= 0) && (VC0_TOTAL_CREDITS_CH <= 127))
VC0_TOTAL_CREDITS_CH_BINARY = VC0_TOTAL_CREDITS_CH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_CH);
$finish;
end
if ((VC0_TOTAL_CREDITS_NPD >= 0) && (VC0_TOTAL_CREDITS_NPD <= 2047))
VC0_TOTAL_CREDITS_NPD_BINARY = VC0_TOTAL_CREDITS_NPD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_NPD);
$finish;
end
if ((VC0_TOTAL_CREDITS_NPH >= 0) && (VC0_TOTAL_CREDITS_NPH <= 127))
VC0_TOTAL_CREDITS_NPH_BINARY = VC0_TOTAL_CREDITS_NPH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_NPH);
$finish;
end
if ((VC0_TOTAL_CREDITS_PD >= 0) && (VC0_TOTAL_CREDITS_PD <= 2047))
VC0_TOTAL_CREDITS_PD_BINARY = VC0_TOTAL_CREDITS_PD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_PD);
$finish;
end
if ((VC0_TOTAL_CREDITS_PH >= 0) && (VC0_TOTAL_CREDITS_PH <= 127))
VC0_TOTAL_CREDITS_PH_BINARY = VC0_TOTAL_CREDITS_PH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_PH);
$finish;
end
if ((VC0_TX_LASTPACKET >= 0) && (VC0_TX_LASTPACKET <= 31))
VC0_TX_LASTPACKET_BINARY = VC0_TX_LASTPACKET;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TX_LASTPACKET on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", VC0_TX_LASTPACKET);
$finish;
end
end
wire [11:0] delay_DBGVECC;
wire [11:0] delay_PLDBGVEC;
wire [11:0] delay_TRNFCCPLD;
wire [11:0] delay_TRNFCNPD;
wire [11:0] delay_TRNFCPD;
wire [127:0] delay_TRNRD;
wire [12:0] delay_MIMRXRADDR;
wire [12:0] delay_MIMRXWADDR;
wire [12:0] delay_MIMTXRADDR;
wire [12:0] delay_MIMTXWADDR;
wire [15:0] delay_CFGMSGDATA;
wire [15:0] delay_DRPDO;
wire [15:0] delay_PIPETX0DATA;
wire [15:0] delay_PIPETX1DATA;
wire [15:0] delay_PIPETX2DATA;
wire [15:0] delay_PIPETX3DATA;
wire [15:0] delay_PIPETX4DATA;
wire [15:0] delay_PIPETX5DATA;
wire [15:0] delay_PIPETX6DATA;
wire [15:0] delay_PIPETX7DATA;
wire [1:0] delay_CFGLINKCONTROLASPMCONTROL;
wire [1:0] delay_CFGLINKSTATUSCURRENTSPEED;
wire [1:0] delay_CFGPMCSRPOWERSTATE;
wire [1:0] delay_PIPETX0CHARISK;
wire [1:0] delay_PIPETX0POWERDOWN;
wire [1:0] delay_PIPETX1CHARISK;
wire [1:0] delay_PIPETX1POWERDOWN;
wire [1:0] delay_PIPETX2CHARISK;
wire [1:0] delay_PIPETX2POWERDOWN;
wire [1:0] delay_PIPETX3CHARISK;
wire [1:0] delay_PIPETX3POWERDOWN;
wire [1:0] delay_PIPETX4CHARISK;
wire [1:0] delay_PIPETX4POWERDOWN;
wire [1:0] delay_PIPETX5CHARISK;
wire [1:0] delay_PIPETX5POWERDOWN;
wire [1:0] delay_PIPETX6CHARISK;
wire [1:0] delay_PIPETX6POWERDOWN;
wire [1:0] delay_PIPETX7CHARISK;
wire [1:0] delay_PIPETX7POWERDOWN;
wire [1:0] delay_PL2RXPMSTATE;
wire [1:0] delay_PLLANEREVERSALMODE;
wire [1:0] delay_PLRXPMSTATE;
wire [1:0] delay_PLSELLNKWIDTH;
wire [1:0] delay_TRNRDLLPSRCRDY;
wire [1:0] delay_TRNRREM;
wire [2:0] delay_CFGDEVCONTROLMAXPAYLOAD;
wire [2:0] delay_CFGDEVCONTROLMAXREADREQ;
wire [2:0] delay_CFGINTERRUPTMMENABLE;
wire [2:0] delay_CFGPCIELINKSTATE;
wire [2:0] delay_PIPETXMARGIN;
wire [2:0] delay_PLINITIALLINKWIDTH;
wire [2:0] delay_PLTXPMSTATE;
wire [31:0] delay_CFGMGMTDO;
wire [3:0] delay_CFGDEVCONTROL2CPLTIMEOUTVAL;
wire [3:0] delay_CFGLINKSTATUSNEGOTIATEDWIDTH;
wire [3:0] delay_TRNTDSTRDY;
wire [4:0] delay_LL2LINKSTATUS;
wire [5:0] delay_PLLTSSMSTATE;
wire [5:0] delay_TRNTBUFAV;
wire [63:0] delay_DBGVECA;
wire [63:0] delay_DBGVECB;
wire [63:0] delay_TL2ERRHDR;
wire [63:0] delay_TRNRDLLPDATA;
wire [67:0] delay_MIMRXWDATA;
wire [68:0] delay_MIMTXWDATA;
wire [6:0] delay_CFGTRANSACTIONADDR;
wire [6:0] delay_CFGVCTCVCMAP;
wire [7:0] delay_CFGINTERRUPTDO;
wire [7:0] delay_TRNFCCPLH;
wire [7:0] delay_TRNFCNPH;
wire [7:0] delay_TRNFCPH;
wire [7:0] delay_TRNRBARHIT;
wire delay_CFGAERECRCCHECKEN;
wire delay_CFGAERECRCGENEN;
wire delay_CFGAERROOTERRCORRERRRECEIVED;
wire delay_CFGAERROOTERRCORRERRREPORTINGEN;
wire delay_CFGAERROOTERRFATALERRRECEIVED;
wire delay_CFGAERROOTERRFATALERRREPORTINGEN;
wire delay_CFGAERROOTERRNONFATALERRRECEIVED;
wire delay_CFGAERROOTERRNONFATALERRREPORTINGEN;
wire delay_CFGBRIDGESERREN;
wire delay_CFGCOMMANDBUSMASTERENABLE;
wire delay_CFGCOMMANDINTERRUPTDISABLE;
wire delay_CFGCOMMANDIOENABLE;
wire delay_CFGCOMMANDMEMENABLE;
wire delay_CFGCOMMANDSERREN;
wire delay_CFGDEVCONTROL2ARIFORWARDEN;
wire delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK;
wire delay_CFGDEVCONTROL2ATOMICREQUESTEREN;
wire delay_CFGDEVCONTROL2CPLTIMEOUTDIS;
wire delay_CFGDEVCONTROL2IDOCPLEN;
wire delay_CFGDEVCONTROL2IDOREQEN;
wire delay_CFGDEVCONTROL2LTREN;
wire delay_CFGDEVCONTROL2TLPPREFIXBLOCK;
wire delay_CFGDEVCONTROLAUXPOWEREN;
wire delay_CFGDEVCONTROLCORRERRREPORTINGEN;
wire delay_CFGDEVCONTROLENABLERO;
wire delay_CFGDEVCONTROLEXTTAGEN;
wire delay_CFGDEVCONTROLFATALERRREPORTINGEN;
wire delay_CFGDEVCONTROLNONFATALREPORTINGEN;
wire delay_CFGDEVCONTROLNOSNOOPEN;
wire delay_CFGDEVCONTROLPHANTOMEN;
wire delay_CFGDEVCONTROLURERRREPORTINGEN;
wire delay_CFGDEVSTATUSCORRERRDETECTED;
wire delay_CFGDEVSTATUSFATALERRDETECTED;
wire delay_CFGDEVSTATUSNONFATALERRDETECTED;
wire delay_CFGDEVSTATUSURDETECTED;
wire delay_CFGERRAERHEADERLOGSETN;
wire delay_CFGERRCPLRDYN;
wire delay_CFGINTERRUPTMSIENABLE;
wire delay_CFGINTERRUPTMSIXENABLE;
wire delay_CFGINTERRUPTMSIXFM;
wire delay_CFGINTERRUPTRDYN;
wire delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN;
wire delay_CFGLINKCONTROLBANDWIDTHINTEN;
wire delay_CFGLINKCONTROLCLOCKPMEN;
wire delay_CFGLINKCONTROLCOMMONCLOCK;
wire delay_CFGLINKCONTROLEXTENDEDSYNC;
wire delay_CFGLINKCONTROLHWAUTOWIDTHDIS;
wire delay_CFGLINKCONTROLLINKDISABLE;
wire delay_CFGLINKCONTROLRCB;
wire delay_CFGLINKCONTROLRETRAINLINK;
wire delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
wire delay_CFGLINKSTATUSBANDWIDTHSTATUS;
wire delay_CFGLINKSTATUSDLLACTIVE;
wire delay_CFGLINKSTATUSLINKTRAINING;
wire delay_CFGMGMTRDWRDONEN;
wire delay_CFGMSGRECEIVED;
wire delay_CFGMSGRECEIVEDASSERTINTA;
wire delay_CFGMSGRECEIVEDASSERTINTB;
wire delay_CFGMSGRECEIVEDASSERTINTC;
wire delay_CFGMSGRECEIVEDASSERTINTD;
wire delay_CFGMSGRECEIVEDDEASSERTINTA;
wire delay_CFGMSGRECEIVEDDEASSERTINTB;
wire delay_CFGMSGRECEIVEDDEASSERTINTC;
wire delay_CFGMSGRECEIVEDDEASSERTINTD;
wire delay_CFGMSGRECEIVEDERRCOR;
wire delay_CFGMSGRECEIVEDERRFATAL;
wire delay_CFGMSGRECEIVEDERRNONFATAL;
wire delay_CFGMSGRECEIVEDPMASNAK;
wire delay_CFGMSGRECEIVEDPMETO;
wire delay_CFGMSGRECEIVEDPMETOACK;
wire delay_CFGMSGRECEIVEDPMPME;
wire delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
wire delay_CFGMSGRECEIVEDUNLOCK;
wire delay_CFGPMCSRPMEEN;
wire delay_CFGPMCSRPMESTATUS;
wire delay_CFGPMRCVASREQL1N;
wire delay_CFGPMRCVENTERL1N;
wire delay_CFGPMRCVENTERL23N;
wire delay_CFGPMRCVREQACKN;
wire delay_CFGROOTCONTROLPMEINTEN;
wire delay_CFGROOTCONTROLSYSERRCORRERREN;
wire delay_CFGROOTCONTROLSYSERRFATALERREN;
wire delay_CFGROOTCONTROLSYSERRNONFATALERREN;
wire delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE;
wire delay_CFGTRANSACTION;
wire delay_CFGTRANSACTIONTYPE;
wire delay_DBGSCLRA;
wire delay_DBGSCLRB;
wire delay_DBGSCLRC;
wire delay_DBGSCLRD;
wire delay_DBGSCLRE;
wire delay_DBGSCLRF;
wire delay_DBGSCLRG;
wire delay_DBGSCLRH;
wire delay_DBGSCLRI;
wire delay_DBGSCLRJ;
wire delay_DBGSCLRK;
wire delay_DRPRDY;
wire delay_LL2BADDLLPERR;
wire delay_LL2BADTLPERR;
wire delay_LL2PROTOCOLERR;
wire delay_LL2RECEIVERERR;
wire delay_LL2REPLAYROERR;
wire delay_LL2REPLAYTOERR;
wire delay_LL2SUSPENDOK;
wire delay_LL2TFCINIT1SEQ;
wire delay_LL2TFCINIT2SEQ;
wire delay_LL2TXIDLE;
wire delay_LNKCLKEN;
wire delay_MIMRXREN;
wire delay_MIMRXWEN;
wire delay_MIMTXREN;
wire delay_MIMTXWEN;
wire delay_PIPERX0POLARITY;
wire delay_PIPERX1POLARITY;
wire delay_PIPERX2POLARITY;
wire delay_PIPERX3POLARITY;
wire delay_PIPERX4POLARITY;
wire delay_PIPERX5POLARITY;
wire delay_PIPERX6POLARITY;
wire delay_PIPERX7POLARITY;
wire delay_PIPETX0COMPLIANCE;
wire delay_PIPETX0ELECIDLE;
wire delay_PIPETX1COMPLIANCE;
wire delay_PIPETX1ELECIDLE;
wire delay_PIPETX2COMPLIANCE;
wire delay_PIPETX2ELECIDLE;
wire delay_PIPETX3COMPLIANCE;
wire delay_PIPETX3ELECIDLE;
wire delay_PIPETX4COMPLIANCE;
wire delay_PIPETX4ELECIDLE;
wire delay_PIPETX5COMPLIANCE;
wire delay_PIPETX5ELECIDLE;
wire delay_PIPETX6COMPLIANCE;
wire delay_PIPETX6ELECIDLE;
wire delay_PIPETX7COMPLIANCE;
wire delay_PIPETX7ELECIDLE;
wire delay_PIPETXDEEMPH;
wire delay_PIPETXRATE;
wire delay_PIPETXRCVRDET;
wire delay_PIPETXRESET;
wire delay_PL2L0REQ;
wire delay_PL2LINKUP;
wire delay_PL2RECEIVERERR;
wire delay_PL2RECOVERY;
wire delay_PL2RXELECIDLE;
wire delay_PL2SUSPENDOK;
wire delay_PLDIRECTEDCHANGEDONE;
wire delay_PLLINKGEN2CAP;
wire delay_PLLINKPARTNERGEN2SUPPORTED;
wire delay_PLLINKUPCFGCAP;
wire delay_PLPHYLNKUPN;
wire delay_PLRECEIVEDHOTRST;
wire delay_PLSELLNKRATE;
wire delay_RECEIVEDFUNCLVLRSTN;
wire delay_TL2ASPMSUSPENDCREDITCHECKOK;
wire delay_TL2ASPMSUSPENDREQ;
wire delay_TL2ERRFCPE;
wire delay_TL2ERRMALFORMED;
wire delay_TL2ERRRXOVERFLOW;
wire delay_TL2PPMSUSPENDOK;
wire delay_TRNLNKUP;
wire delay_TRNRECRCERR;
wire delay_TRNREOF;
wire delay_TRNRERRFWD;
wire delay_TRNRSOF;
wire delay_TRNRSRCDSC;
wire delay_TRNRSRCRDY;
wire delay_TRNTCFGREQ;
wire delay_TRNTDLLPDSTRDY;
wire delay_TRNTERRDROP;
wire delay_USERRSTN;
wire [127:0] delay_CFGERRAERHEADERLOG;
wire [127:0] delay_TRNTD;
wire [15:0] delay_CFGDEVID;
wire [15:0] delay_CFGSUBSYSID;
wire [15:0] delay_CFGSUBSYSVENDID;
wire [15:0] delay_CFGVENDID;
wire [15:0] delay_DRPDI;
wire [15:0] delay_PIPERX0DATA;
wire [15:0] delay_PIPERX1DATA;
wire [15:0] delay_PIPERX2DATA;
wire [15:0] delay_PIPERX3DATA;
wire [15:0] delay_PIPERX4DATA;
wire [15:0] delay_PIPERX5DATA;
wire [15:0] delay_PIPERX6DATA;
wire [15:0] delay_PIPERX7DATA;
wire [1:0] delay_CFGPMFORCESTATE;
wire [1:0] delay_DBGMODE;
wire [1:0] delay_PIPERX0CHARISK;
wire [1:0] delay_PIPERX1CHARISK;
wire [1:0] delay_PIPERX2CHARISK;
wire [1:0] delay_PIPERX3CHARISK;
wire [1:0] delay_PIPERX4CHARISK;
wire [1:0] delay_PIPERX5CHARISK;
wire [1:0] delay_PIPERX6CHARISK;
wire [1:0] delay_PIPERX7CHARISK;
wire [1:0] delay_PLDIRECTEDLINKCHANGE;
wire [1:0] delay_PLDIRECTEDLINKWIDTH;
wire [1:0] delay_TRNTREM;
wire [2:0] delay_CFGDSFUNCTIONNUMBER;
wire [2:0] delay_CFGFORCEMPS;
wire [2:0] delay_PIPERX0STATUS;
wire [2:0] delay_PIPERX1STATUS;
wire [2:0] delay_PIPERX2STATUS;
wire [2:0] delay_PIPERX3STATUS;
wire [2:0] delay_PIPERX4STATUS;
wire [2:0] delay_PIPERX5STATUS;
wire [2:0] delay_PIPERX6STATUS;
wire [2:0] delay_PIPERX7STATUS;
wire [2:0] delay_PLDBGMODE;
wire [2:0] delay_TRNFCSEL;
wire [31:0] delay_CFGMGMTDI;
wire [31:0] delay_TRNTDLLPDATA;
wire [3:0] delay_CFGMGMTBYTEENN;
wire [47:0] delay_CFGERRTLPCPLHEADER;
wire [4:0] delay_CFGAERINTERRUPTMSGNUM;
wire [4:0] delay_CFGDSDEVICENUMBER;
wire [4:0] delay_CFGPCIECAPINTERRUPTMSGNUM;
wire [4:0] delay_PL2DIRECTEDLSTATE;
wire [5:0] delay_PLDIRECTEDLTSSMNEW;
wire [63:0] delay_CFGDSN;
wire [67:0] delay_MIMRXRDATA;
wire [68:0] delay_MIMTXRDATA;
wire [7:0] delay_CFGDSBUSNUMBER;
wire [7:0] delay_CFGINTERRUPTDI;
wire [7:0] delay_CFGPORTNUMBER;
wire [7:0] delay_CFGREVID;
wire [8:0] delay_DRPADDR;
wire [9:0] delay_CFGMGMTDWADDR;
wire delay_CFGERRACSN;
wire delay_CFGERRATOMICEGRESSBLOCKEDN;
wire delay_CFGERRCORN;
wire delay_CFGERRCPLABORTN;
wire delay_CFGERRCPLTIMEOUTN;
wire delay_CFGERRCPLUNEXPECTN;
wire delay_CFGERRECRCN;
wire delay_CFGERRINTERNALCORN;
wire delay_CFGERRINTERNALUNCORN;
wire delay_CFGERRLOCKEDN;
wire delay_CFGERRMALFORMEDN;
wire delay_CFGERRMCBLOCKEDN;
wire delay_CFGERRNORECOVERYN;
wire delay_CFGERRPOISONEDN;
wire delay_CFGERRPOSTEDN;
wire delay_CFGERRURN;
wire delay_CFGFORCECOMMONCLOCKOFF;
wire delay_CFGFORCEEXTENDEDSYNCON;
wire delay_CFGINTERRUPTASSERTN;
wire delay_CFGINTERRUPTN;
wire delay_CFGINTERRUPTSTATN;
wire delay_CFGMGMTRDENN;
wire delay_CFGMGMTWRENN;
wire delay_CFGMGMTWRREADONLYN;
wire delay_CFGMGMTWRRW1CASRWN;
wire delay_CFGPMFORCESTATEENN;
wire delay_CFGPMHALTASPML0SN;
wire delay_CFGPMHALTASPML1N;
wire delay_CFGPMSENDPMETON;
wire delay_CFGPMTURNOFFOKN;
wire delay_CFGPMWAKEN;
wire delay_CFGTRNPENDINGN;
wire delay_CMRSTN;
wire delay_CMSTICKYRSTN;
wire delay_DBGSUBMODE;
wire delay_DLRSTN;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_FUNCLVLRSTN;
wire delay_LL2SENDASREQL1;
wire delay_LL2SENDENTERL1;
wire delay_LL2SENDENTERL23;
wire delay_LL2SENDPMACK;
wire delay_LL2SUSPENDNOW;
wire delay_LL2TLPRCV;
wire delay_PIPECLK;
wire delay_PIPERX0CHANISALIGNED;
wire delay_PIPERX0ELECIDLE;
wire delay_PIPERX0PHYSTATUS;
wire delay_PIPERX0VALID;
wire delay_PIPERX1CHANISALIGNED;
wire delay_PIPERX1ELECIDLE;
wire delay_PIPERX1PHYSTATUS;
wire delay_PIPERX1VALID;
wire delay_PIPERX2CHANISALIGNED;
wire delay_PIPERX2ELECIDLE;
wire delay_PIPERX2PHYSTATUS;
wire delay_PIPERX2VALID;
wire delay_PIPERX3CHANISALIGNED;
wire delay_PIPERX3ELECIDLE;
wire delay_PIPERX3PHYSTATUS;
wire delay_PIPERX3VALID;
wire delay_PIPERX4CHANISALIGNED;
wire delay_PIPERX4ELECIDLE;
wire delay_PIPERX4PHYSTATUS;
wire delay_PIPERX4VALID;
wire delay_PIPERX5CHANISALIGNED;
wire delay_PIPERX5ELECIDLE;
wire delay_PIPERX5PHYSTATUS;
wire delay_PIPERX5VALID;
wire delay_PIPERX6CHANISALIGNED;
wire delay_PIPERX6ELECIDLE;
wire delay_PIPERX6PHYSTATUS;
wire delay_PIPERX6VALID;
wire delay_PIPERX7CHANISALIGNED;
wire delay_PIPERX7ELECIDLE;
wire delay_PIPERX7PHYSTATUS;
wire delay_PIPERX7VALID;
wire delay_PLDIRECTEDLINKAUTON;
wire delay_PLDIRECTEDLINKSPEED;
wire delay_PLDIRECTEDLTSSMNEWVLD;
wire delay_PLDIRECTEDLTSSMSTALL;
wire delay_PLDOWNSTREAMDEEMPHSOURCE;
wire delay_PLRSTN;
wire delay_PLTRANSMITHOTRST;
wire delay_PLUPSTREAMPREFERDEEMPH;
wire delay_SYSRSTN;
wire delay_TL2ASPMSUSPENDCREDITCHECK;
wire delay_TL2PPMSUSPENDREQ;
wire delay_TLRSTN;
wire delay_TRNRDSTRDY;
wire delay_TRNRFCPRET;
wire delay_TRNRNPOK;
wire delay_TRNRNPREQ;
wire delay_TRNTCFGGNT;
wire delay_TRNTDLLPSRCRDY;
wire delay_TRNTECRCGEN;
wire delay_TRNTEOF;
wire delay_TRNTERRFWD;
wire delay_TRNTSOF;
wire delay_TRNTSRCDSC;
wire delay_TRNTSRCRDY;
wire delay_TRNTSTR;
wire delay_USERCLK2;
wire delay_USERCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
assign #(out_delay) CFGAERECRCCHECKEN = delay_CFGAERECRCCHECKEN;
assign #(out_delay) CFGAERECRCGENEN = delay_CFGAERECRCGENEN;
assign #(out_delay) CFGAERROOTERRCORRERRRECEIVED = delay_CFGAERROOTERRCORRERRRECEIVED;
assign #(out_delay) CFGAERROOTERRCORRERRREPORTINGEN = delay_CFGAERROOTERRCORRERRREPORTINGEN;
assign #(out_delay) CFGAERROOTERRFATALERRRECEIVED = delay_CFGAERROOTERRFATALERRRECEIVED;
assign #(out_delay) CFGAERROOTERRFATALERRREPORTINGEN = delay_CFGAERROOTERRFATALERRREPORTINGEN;
assign #(out_delay) CFGAERROOTERRNONFATALERRRECEIVED = delay_CFGAERROOTERRNONFATALERRRECEIVED;
assign #(out_delay) CFGAERROOTERRNONFATALERRREPORTINGEN = delay_CFGAERROOTERRNONFATALERRREPORTINGEN;
assign #(out_delay) CFGBRIDGESERREN = delay_CFGBRIDGESERREN;
assign #(out_delay) CFGCOMMANDBUSMASTERENABLE = delay_CFGCOMMANDBUSMASTERENABLE;
assign #(out_delay) CFGCOMMANDINTERRUPTDISABLE = delay_CFGCOMMANDINTERRUPTDISABLE;
assign #(out_delay) CFGCOMMANDIOENABLE = delay_CFGCOMMANDIOENABLE;
assign #(out_delay) CFGCOMMANDMEMENABLE = delay_CFGCOMMANDMEMENABLE;
assign #(out_delay) CFGCOMMANDSERREN = delay_CFGCOMMANDSERREN;
assign #(out_delay) CFGDEVCONTROL2ARIFORWARDEN = delay_CFGDEVCONTROL2ARIFORWARDEN;
assign #(out_delay) CFGDEVCONTROL2ATOMICEGRESSBLOCK = delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK;
assign #(out_delay) CFGDEVCONTROL2ATOMICREQUESTEREN = delay_CFGDEVCONTROL2ATOMICREQUESTEREN;
assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTDIS = delay_CFGDEVCONTROL2CPLTIMEOUTDIS;
assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTVAL = delay_CFGDEVCONTROL2CPLTIMEOUTVAL;
assign #(out_delay) CFGDEVCONTROL2IDOCPLEN = delay_CFGDEVCONTROL2IDOCPLEN;
assign #(out_delay) CFGDEVCONTROL2IDOREQEN = delay_CFGDEVCONTROL2IDOREQEN;
assign #(out_delay) CFGDEVCONTROL2LTREN = delay_CFGDEVCONTROL2LTREN;
assign #(out_delay) CFGDEVCONTROL2TLPPREFIXBLOCK = delay_CFGDEVCONTROL2TLPPREFIXBLOCK;
assign #(out_delay) CFGDEVCONTROLAUXPOWEREN = delay_CFGDEVCONTROLAUXPOWEREN;
assign #(out_delay) CFGDEVCONTROLCORRERRREPORTINGEN = delay_CFGDEVCONTROLCORRERRREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLENABLERO = delay_CFGDEVCONTROLENABLERO;
assign #(out_delay) CFGDEVCONTROLEXTTAGEN = delay_CFGDEVCONTROLEXTTAGEN;
assign #(out_delay) CFGDEVCONTROLFATALERRREPORTINGEN = delay_CFGDEVCONTROLFATALERRREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLMAXPAYLOAD = delay_CFGDEVCONTROLMAXPAYLOAD;
assign #(out_delay) CFGDEVCONTROLMAXREADREQ = delay_CFGDEVCONTROLMAXREADREQ;
assign #(out_delay) CFGDEVCONTROLNONFATALREPORTINGEN = delay_CFGDEVCONTROLNONFATALREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLNOSNOOPEN = delay_CFGDEVCONTROLNOSNOOPEN;
assign #(out_delay) CFGDEVCONTROLPHANTOMEN = delay_CFGDEVCONTROLPHANTOMEN;
assign #(out_delay) CFGDEVCONTROLURERRREPORTINGEN = delay_CFGDEVCONTROLURERRREPORTINGEN;
assign #(out_delay) CFGDEVSTATUSCORRERRDETECTED = delay_CFGDEVSTATUSCORRERRDETECTED;
assign #(out_delay) CFGDEVSTATUSFATALERRDETECTED = delay_CFGDEVSTATUSFATALERRDETECTED;
assign #(out_delay) CFGDEVSTATUSNONFATALERRDETECTED = delay_CFGDEVSTATUSNONFATALERRDETECTED;
assign #(out_delay) CFGDEVSTATUSURDETECTED = delay_CFGDEVSTATUSURDETECTED;
assign #(out_delay) CFGERRAERHEADERLOGSETN = delay_CFGERRAERHEADERLOGSETN;
assign #(out_delay) CFGERRCPLRDYN = delay_CFGERRCPLRDYN;
assign #(out_delay) CFGINTERRUPTDO = delay_CFGINTERRUPTDO;
assign #(out_delay) CFGINTERRUPTMMENABLE = delay_CFGINTERRUPTMMENABLE;
assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE;
assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE;
assign #(out_delay) CFGINTERRUPTMSIXFM = delay_CFGINTERRUPTMSIXFM;
assign #(out_delay) CFGINTERRUPTRDYN = delay_CFGINTERRUPTRDYN;
assign #(out_delay) CFGLINKCONTROLASPMCONTROL = delay_CFGLINKCONTROLASPMCONTROL;
assign #(out_delay) CFGLINKCONTROLAUTOBANDWIDTHINTEN = delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN;
assign #(out_delay) CFGLINKCONTROLBANDWIDTHINTEN = delay_CFGLINKCONTROLBANDWIDTHINTEN;
assign #(out_delay) CFGLINKCONTROLCLOCKPMEN = delay_CFGLINKCONTROLCLOCKPMEN;
assign #(out_delay) CFGLINKCONTROLCOMMONCLOCK = delay_CFGLINKCONTROLCOMMONCLOCK;
assign #(out_delay) CFGLINKCONTROLEXTENDEDSYNC = delay_CFGLINKCONTROLEXTENDEDSYNC;
assign #(out_delay) CFGLINKCONTROLHWAUTOWIDTHDIS = delay_CFGLINKCONTROLHWAUTOWIDTHDIS;
assign #(out_delay) CFGLINKCONTROLLINKDISABLE = delay_CFGLINKCONTROLLINKDISABLE;
assign #(out_delay) CFGLINKCONTROLRCB = delay_CFGLINKCONTROLRCB;
assign #(out_delay) CFGLINKCONTROLRETRAINLINK = delay_CFGLINKCONTROLRETRAINLINK;
assign #(out_delay) CFGLINKSTATUSAUTOBANDWIDTHSTATUS = delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
assign #(out_delay) CFGLINKSTATUSBANDWIDTHSTATUS = delay_CFGLINKSTATUSBANDWIDTHSTATUS;
assign #(out_delay) CFGLINKSTATUSCURRENTSPEED = delay_CFGLINKSTATUSCURRENTSPEED;
assign #(out_delay) CFGLINKSTATUSDLLACTIVE = delay_CFGLINKSTATUSDLLACTIVE;
assign #(out_delay) CFGLINKSTATUSLINKTRAINING = delay_CFGLINKSTATUSLINKTRAINING;
assign #(out_delay) CFGLINKSTATUSNEGOTIATEDWIDTH = delay_CFGLINKSTATUSNEGOTIATEDWIDTH;
assign #(out_delay) CFGMGMTDO = delay_CFGMGMTDO;
assign #(out_delay) CFGMGMTRDWRDONEN = delay_CFGMGMTRDWRDONEN;
assign #(out_delay) CFGMSGDATA = delay_CFGMSGDATA;
assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTA = delay_CFGMSGRECEIVEDASSERTINTA;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTB = delay_CFGMSGRECEIVEDASSERTINTB;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTC = delay_CFGMSGRECEIVEDASSERTINTC;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTD = delay_CFGMSGRECEIVEDASSERTINTD;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTA = delay_CFGMSGRECEIVEDDEASSERTINTA;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTB = delay_CFGMSGRECEIVEDDEASSERTINTB;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTC = delay_CFGMSGRECEIVEDDEASSERTINTC;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTD = delay_CFGMSGRECEIVEDDEASSERTINTD;
assign #(out_delay) CFGMSGRECEIVEDERRCOR = delay_CFGMSGRECEIVEDERRCOR;
assign #(out_delay) CFGMSGRECEIVEDERRFATAL = delay_CFGMSGRECEIVEDERRFATAL;
assign #(out_delay) CFGMSGRECEIVEDERRNONFATAL = delay_CFGMSGRECEIVEDERRNONFATAL;
assign #(out_delay) CFGMSGRECEIVEDPMASNAK = delay_CFGMSGRECEIVEDPMASNAK;
assign #(out_delay) CFGMSGRECEIVEDPMETO = delay_CFGMSGRECEIVEDPMETO;
assign #(out_delay) CFGMSGRECEIVEDPMETOACK = delay_CFGMSGRECEIVEDPMETOACK;
assign #(out_delay) CFGMSGRECEIVEDPMPME = delay_CFGMSGRECEIVEDPMPME;
assign #(out_delay) CFGMSGRECEIVEDSETSLOTPOWERLIMIT = delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
assign #(out_delay) CFGMSGRECEIVEDUNLOCK = delay_CFGMSGRECEIVEDUNLOCK;
assign #(out_delay) CFGPCIELINKSTATE = delay_CFGPCIELINKSTATE;
assign #(out_delay) CFGPMCSRPMEEN = delay_CFGPMCSRPMEEN;
assign #(out_delay) CFGPMCSRPMESTATUS = delay_CFGPMCSRPMESTATUS;
assign #(out_delay) CFGPMCSRPOWERSTATE = delay_CFGPMCSRPOWERSTATE;
assign #(out_delay) CFGPMRCVASREQL1N = delay_CFGPMRCVASREQL1N;
assign #(out_delay) CFGPMRCVENTERL1N = delay_CFGPMRCVENTERL1N;
assign #(out_delay) CFGPMRCVENTERL23N = delay_CFGPMRCVENTERL23N;
assign #(out_delay) CFGPMRCVREQACKN = delay_CFGPMRCVREQACKN;
assign #(out_delay) CFGROOTCONTROLPMEINTEN = delay_CFGROOTCONTROLPMEINTEN;
assign #(out_delay) CFGROOTCONTROLSYSERRCORRERREN = delay_CFGROOTCONTROLSYSERRCORRERREN;
assign #(out_delay) CFGROOTCONTROLSYSERRFATALERREN = delay_CFGROOTCONTROLSYSERRFATALERREN;
assign #(out_delay) CFGROOTCONTROLSYSERRNONFATALERREN = delay_CFGROOTCONTROLSYSERRNONFATALERREN;
assign #(out_delay) CFGSLOTCONTROLELECTROMECHILCTLPULSE = delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE;
assign #(out_delay) CFGTRANSACTION = delay_CFGTRANSACTION;
assign #(out_delay) CFGTRANSACTIONADDR = delay_CFGTRANSACTIONADDR;
assign #(out_delay) CFGTRANSACTIONTYPE = delay_CFGTRANSACTIONTYPE;
assign #(out_delay) CFGVCTCVCMAP = delay_CFGVCTCVCMAP;
assign #(out_delay) DBGSCLRA = delay_DBGSCLRA;
assign #(out_delay) DBGSCLRB = delay_DBGSCLRB;
assign #(out_delay) DBGSCLRC = delay_DBGSCLRC;
assign #(out_delay) DBGSCLRD = delay_DBGSCLRD;
assign #(out_delay) DBGSCLRE = delay_DBGSCLRE;
assign #(out_delay) DBGSCLRF = delay_DBGSCLRF;
assign #(out_delay) DBGSCLRG = delay_DBGSCLRG;
assign #(out_delay) DBGSCLRH = delay_DBGSCLRH;
assign #(out_delay) DBGSCLRI = delay_DBGSCLRI;
assign #(out_delay) DBGSCLRJ = delay_DBGSCLRJ;
assign #(out_delay) DBGSCLRK = delay_DBGSCLRK;
assign #(out_delay) DBGVECA = delay_DBGVECA;
assign #(out_delay) DBGVECB = delay_DBGVECB;
assign #(out_delay) DBGVECC = delay_DBGVECC;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) LL2BADDLLPERR = delay_LL2BADDLLPERR;
assign #(out_delay) LL2BADTLPERR = delay_LL2BADTLPERR;
assign #(out_delay) LL2LINKSTATUS = delay_LL2LINKSTATUS;
assign #(out_delay) LL2PROTOCOLERR = delay_LL2PROTOCOLERR;
assign #(out_delay) LL2RECEIVERERR = delay_LL2RECEIVERERR;
assign #(out_delay) LL2REPLAYROERR = delay_LL2REPLAYROERR;
assign #(out_delay) LL2REPLAYTOERR = delay_LL2REPLAYTOERR;
assign #(out_delay) LL2SUSPENDOK = delay_LL2SUSPENDOK;
assign #(out_delay) LL2TFCINIT1SEQ = delay_LL2TFCINIT1SEQ;
assign #(out_delay) LL2TFCINIT2SEQ = delay_LL2TFCINIT2SEQ;
assign #(out_delay) LL2TXIDLE = delay_LL2TXIDLE;
assign #(out_delay) LNKCLKEN = delay_LNKCLKEN;
assign #(out_delay) MIMRXRADDR = delay_MIMRXRADDR;
assign #(out_delay) MIMRXREN = delay_MIMRXREN;
assign #(out_delay) MIMRXWADDR = delay_MIMRXWADDR;
assign #(out_delay) MIMRXWDATA = delay_MIMRXWDATA;
assign #(out_delay) MIMRXWEN = delay_MIMRXWEN;
assign #(out_delay) MIMTXRADDR = delay_MIMTXRADDR;
assign #(out_delay) MIMTXREN = delay_MIMTXREN;
assign #(out_delay) MIMTXWADDR = delay_MIMTXWADDR;
assign #(out_delay) MIMTXWDATA = delay_MIMTXWDATA;
assign #(out_delay) MIMTXWEN = delay_MIMTXWEN;
assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY;
assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY;
assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY;
assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY;
assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY;
assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY;
assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY;
assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY;
assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK;
assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE;
assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA;
assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE;
assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN;
assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK;
assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE;
assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA;
assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE;
assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN;
assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK;
assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE;
assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA;
assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE;
assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN;
assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK;
assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE;
assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA;
assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE;
assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN;
assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK;
assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE;
assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA;
assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE;
assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN;
assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK;
assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE;
assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA;
assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE;
assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN;
assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK;
assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE;
assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA;
assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE;
assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN;
assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK;
assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE;
assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA;
assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE;
assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN;
assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH;
assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN;
assign #(out_delay) PIPETXRATE = delay_PIPETXRATE;
assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET;
assign #(out_delay) PIPETXRESET = delay_PIPETXRESET;
assign #(out_delay) PL2L0REQ = delay_PL2L0REQ;
assign #(out_delay) PL2LINKUP = delay_PL2LINKUP;
assign #(out_delay) PL2RECEIVERERR = delay_PL2RECEIVERERR;
assign #(out_delay) PL2RECOVERY = delay_PL2RECOVERY;
assign #(out_delay) PL2RXELECIDLE = delay_PL2RXELECIDLE;
assign #(out_delay) PL2RXPMSTATE = delay_PL2RXPMSTATE;
assign #(out_delay) PL2SUSPENDOK = delay_PL2SUSPENDOK;
assign #(out_delay) PLDBGVEC = delay_PLDBGVEC;
assign #(out_delay) PLDIRECTEDCHANGEDONE = delay_PLDIRECTEDCHANGEDONE;
assign #(out_delay) PLINITIALLINKWIDTH = delay_PLINITIALLINKWIDTH;
assign #(out_delay) PLLANEREVERSALMODE = delay_PLLANEREVERSALMODE;
assign #(out_delay) PLLINKGEN2CAP = delay_PLLINKGEN2CAP;
assign #(out_delay) PLLINKPARTNERGEN2SUPPORTED = delay_PLLINKPARTNERGEN2SUPPORTED;
assign #(out_delay) PLLINKUPCFGCAP = delay_PLLINKUPCFGCAP;
assign #(out_delay) PLLTSSMSTATE = delay_PLLTSSMSTATE;
assign #(out_delay) PLPHYLNKUPN = delay_PLPHYLNKUPN;
assign #(out_delay) PLRECEIVEDHOTRST = delay_PLRECEIVEDHOTRST;
assign #(out_delay) PLRXPMSTATE = delay_PLRXPMSTATE;
assign #(out_delay) PLSELLNKRATE = delay_PLSELLNKRATE;
assign #(out_delay) PLSELLNKWIDTH = delay_PLSELLNKWIDTH;
assign #(out_delay) PLTXPMSTATE = delay_PLTXPMSTATE;
assign #(out_delay) RECEIVEDFUNCLVLRSTN = delay_RECEIVEDFUNCLVLRSTN;
assign #(out_delay) TL2ASPMSUSPENDCREDITCHECKOK = delay_TL2ASPMSUSPENDCREDITCHECKOK;
assign #(out_delay) TL2ASPMSUSPENDREQ = delay_TL2ASPMSUSPENDREQ;
assign #(out_delay) TL2ERRFCPE = delay_TL2ERRFCPE;
assign #(out_delay) TL2ERRHDR = delay_TL2ERRHDR;
assign #(out_delay) TL2ERRMALFORMED = delay_TL2ERRMALFORMED;
assign #(out_delay) TL2ERRRXOVERFLOW = delay_TL2ERRRXOVERFLOW;
assign #(out_delay) TL2PPMSUSPENDOK = delay_TL2PPMSUSPENDOK;
assign #(out_delay) TRNFCCPLD = delay_TRNFCCPLD;
assign #(out_delay) TRNFCCPLH = delay_TRNFCCPLH;
assign #(out_delay) TRNFCNPD = delay_TRNFCNPD;
assign #(out_delay) TRNFCNPH = delay_TRNFCNPH;
assign #(out_delay) TRNFCPD = delay_TRNFCPD;
assign #(out_delay) TRNFCPH = delay_TRNFCPH;
assign #(out_delay) TRNLNKUP = delay_TRNLNKUP;
assign #(out_delay) TRNRBARHIT = delay_TRNRBARHIT;
assign #(out_delay) TRNRD = delay_TRNRD;
assign #(out_delay) TRNRDLLPDATA = delay_TRNRDLLPDATA;
assign #(out_delay) TRNRDLLPSRCRDY = delay_TRNRDLLPSRCRDY;
assign #(out_delay) TRNRECRCERR = delay_TRNRECRCERR;
assign #(out_delay) TRNREOF = delay_TRNREOF;
assign #(out_delay) TRNRERRFWD = delay_TRNRERRFWD;
assign #(out_delay) TRNRREM = delay_TRNRREM;
assign #(out_delay) TRNRSOF = delay_TRNRSOF;
assign #(out_delay) TRNRSRCDSC = delay_TRNRSRCDSC;
assign #(out_delay) TRNRSRCRDY = delay_TRNRSRCRDY;
assign #(out_delay) TRNTBUFAV = delay_TRNTBUFAV;
assign #(out_delay) TRNTCFGREQ = delay_TRNTCFGREQ;
assign #(out_delay) TRNTDLLPDSTRDY = delay_TRNTDLLPDSTRDY;
assign #(out_delay) TRNTDSTRDY = delay_TRNTDSTRDY;
assign #(out_delay) TRNTERRDROP = delay_TRNTERRDROP;
assign #(out_delay) USERRSTN = delay_USERRSTN;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK;
assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK;
assign #(INCLK_DELAY) delay_USERCLK = USERCLK;
assign #(INCLK_DELAY) delay_USERCLK2 = USERCLK2;
assign #(in_delay) delay_CFGAERINTERRUPTMSGNUM = CFGAERINTERRUPTMSGNUM;
assign #(in_delay) delay_CFGDEVID = CFGDEVID;
assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER;
assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER;
assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER;
assign #(in_delay) delay_CFGDSN = CFGDSN;
assign #(in_delay) delay_CFGERRACSN = CFGERRACSN;
assign #(in_delay) delay_CFGERRAERHEADERLOG = CFGERRAERHEADERLOG;
assign #(in_delay) delay_CFGERRATOMICEGRESSBLOCKEDN = CFGERRATOMICEGRESSBLOCKEDN;
assign #(in_delay) delay_CFGERRCORN = CFGERRCORN;
assign #(in_delay) delay_CFGERRCPLABORTN = CFGERRCPLABORTN;
assign #(in_delay) delay_CFGERRCPLTIMEOUTN = CFGERRCPLTIMEOUTN;
assign #(in_delay) delay_CFGERRCPLUNEXPECTN = CFGERRCPLUNEXPECTN;
assign #(in_delay) delay_CFGERRECRCN = CFGERRECRCN;
assign #(in_delay) delay_CFGERRINTERNALCORN = CFGERRINTERNALCORN;
assign #(in_delay) delay_CFGERRINTERNALUNCORN = CFGERRINTERNALUNCORN;
assign #(in_delay) delay_CFGERRLOCKEDN = CFGERRLOCKEDN;
assign #(in_delay) delay_CFGERRMALFORMEDN = CFGERRMALFORMEDN;
assign #(in_delay) delay_CFGERRMCBLOCKEDN = CFGERRMCBLOCKEDN;
assign #(in_delay) delay_CFGERRNORECOVERYN = CFGERRNORECOVERYN;
assign #(in_delay) delay_CFGERRPOISONEDN = CFGERRPOISONEDN;
assign #(in_delay) delay_CFGERRPOSTEDN = CFGERRPOSTEDN;
assign #(in_delay) delay_CFGERRTLPCPLHEADER = CFGERRTLPCPLHEADER;
assign #(in_delay) delay_CFGERRURN = CFGERRURN;
assign #(in_delay) delay_CFGFORCECOMMONCLOCKOFF = CFGFORCECOMMONCLOCKOFF;
assign #(in_delay) delay_CFGFORCEEXTENDEDSYNCON = CFGFORCEEXTENDEDSYNCON;
assign #(in_delay) delay_CFGFORCEMPS = CFGFORCEMPS;
assign #(in_delay) delay_CFGINTERRUPTASSERTN = CFGINTERRUPTASSERTN;
assign #(in_delay) delay_CFGINTERRUPTDI = CFGINTERRUPTDI;
assign #(in_delay) delay_CFGINTERRUPTN = CFGINTERRUPTN;
assign #(in_delay) delay_CFGINTERRUPTSTATN = CFGINTERRUPTSTATN;
assign #(in_delay) delay_CFGMGMTBYTEENN = CFGMGMTBYTEENN;
assign #(in_delay) delay_CFGMGMTDI = CFGMGMTDI;
assign #(in_delay) delay_CFGMGMTDWADDR = CFGMGMTDWADDR;
assign #(in_delay) delay_CFGMGMTRDENN = CFGMGMTRDENN;
assign #(in_delay) delay_CFGMGMTWRENN = CFGMGMTWRENN;
assign #(in_delay) delay_CFGMGMTWRREADONLYN = CFGMGMTWRREADONLYN;
assign #(in_delay) delay_CFGMGMTWRRW1CASRWN = CFGMGMTWRRW1CASRWN;
assign #(in_delay) delay_CFGPCIECAPINTERRUPTMSGNUM = CFGPCIECAPINTERRUPTMSGNUM;
assign #(in_delay) delay_CFGPMFORCESTATE = CFGPMFORCESTATE;
assign #(in_delay) delay_CFGPMFORCESTATEENN = CFGPMFORCESTATEENN;
assign #(in_delay) delay_CFGPMHALTASPML0SN = CFGPMHALTASPML0SN;
assign #(in_delay) delay_CFGPMHALTASPML1N = CFGPMHALTASPML1N;
assign #(in_delay) delay_CFGPMSENDPMETON = CFGPMSENDPMETON;
assign #(in_delay) delay_CFGPMTURNOFFOKN = CFGPMTURNOFFOKN;
assign #(in_delay) delay_CFGPMWAKEN = CFGPMWAKEN;
assign #(in_delay) delay_CFGPORTNUMBER = CFGPORTNUMBER;
assign #(in_delay) delay_CFGREVID = CFGREVID;
assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID;
assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID;
assign #(in_delay) delay_CFGTRNPENDINGN = CFGTRNPENDINGN;
assign #(in_delay) delay_CFGVENDID = CFGVENDID;
assign #(in_delay) delay_CMRSTN = CMRSTN;
assign #(in_delay) delay_CMSTICKYRSTN = CMSTICKYRSTN;
assign #(in_delay) delay_DBGMODE = DBGMODE;
assign #(in_delay) delay_DBGSUBMODE = DBGSUBMODE;
assign #(in_delay) delay_DLRSTN = DLRSTN;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_FUNCLVLRSTN = FUNCLVLRSTN;
assign #(in_delay) delay_LL2SENDASREQL1 = LL2SENDASREQL1;
assign #(in_delay) delay_LL2SENDENTERL1 = LL2SENDENTERL1;
assign #(in_delay) delay_LL2SENDENTERL23 = LL2SENDENTERL23;
assign #(in_delay) delay_LL2SENDPMACK = LL2SENDPMACK;
assign #(in_delay) delay_LL2SUSPENDNOW = LL2SUSPENDNOW;
assign #(in_delay) delay_LL2TLPRCV = LL2TLPRCV;
assign #(in_delay) delay_MIMRXRDATA = MIMRXRDATA;
assign #(in_delay) delay_MIMTXRDATA = MIMTXRDATA;
assign #(in_delay) delay_PIPERX0CHANISALIGNED = PIPERX0CHANISALIGNED;
assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK;
assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA;
assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE;
assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS;
assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS;
assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID;
assign #(in_delay) delay_PIPERX1CHANISALIGNED = PIPERX1CHANISALIGNED;
assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK;
assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA;
assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE;
assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS;
assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS;
assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID;
assign #(in_delay) delay_PIPERX2CHANISALIGNED = PIPERX2CHANISALIGNED;
assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK;
assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA;
assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE;
assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS;
assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS;
assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID;
assign #(in_delay) delay_PIPERX3CHANISALIGNED = PIPERX3CHANISALIGNED;
assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK;
assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA;
assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE;
assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS;
assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS;
assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID;
assign #(in_delay) delay_PIPERX4CHANISALIGNED = PIPERX4CHANISALIGNED;
assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK;
assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA;
assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE;
assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS;
assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS;
assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID;
assign #(in_delay) delay_PIPERX5CHANISALIGNED = PIPERX5CHANISALIGNED;
assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK;
assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA;
assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE;
assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS;
assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS;
assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID;
assign #(in_delay) delay_PIPERX6CHANISALIGNED = PIPERX6CHANISALIGNED;
assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK;
assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA;
assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE;
assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS;
assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS;
assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID;
assign #(in_delay) delay_PIPERX7CHANISALIGNED = PIPERX7CHANISALIGNED;
assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK;
assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA;
assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE;
assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS;
assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS;
assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID;
assign #(in_delay) delay_PL2DIRECTEDLSTATE = PL2DIRECTEDLSTATE;
assign #(in_delay) delay_PLDBGMODE = PLDBGMODE;
assign #(in_delay) delay_PLDIRECTEDLINKAUTON = PLDIRECTEDLINKAUTON;
assign #(in_delay) delay_PLDIRECTEDLINKCHANGE = PLDIRECTEDLINKCHANGE;
assign #(in_delay) delay_PLDIRECTEDLINKSPEED = PLDIRECTEDLINKSPEED;
assign #(in_delay) delay_PLDIRECTEDLINKWIDTH = PLDIRECTEDLINKWIDTH;
assign #(in_delay) delay_PLDIRECTEDLTSSMNEW = PLDIRECTEDLTSSMNEW;
assign #(in_delay) delay_PLDIRECTEDLTSSMNEWVLD = PLDIRECTEDLTSSMNEWVLD;
assign #(in_delay) delay_PLDIRECTEDLTSSMSTALL = PLDIRECTEDLTSSMSTALL;
assign #(in_delay) delay_PLDOWNSTREAMDEEMPHSOURCE = PLDOWNSTREAMDEEMPHSOURCE;
assign #(in_delay) delay_PLRSTN = PLRSTN;
assign #(in_delay) delay_PLTRANSMITHOTRST = PLTRANSMITHOTRST;
assign #(in_delay) delay_PLUPSTREAMPREFERDEEMPH = PLUPSTREAMPREFERDEEMPH;
assign #(in_delay) delay_SYSRSTN = SYSRSTN;
assign #(in_delay) delay_TL2ASPMSUSPENDCREDITCHECK = TL2ASPMSUSPENDCREDITCHECK;
assign #(in_delay) delay_TL2PPMSUSPENDREQ = TL2PPMSUSPENDREQ;
assign #(in_delay) delay_TLRSTN = TLRSTN;
assign #(in_delay) delay_TRNFCSEL = TRNFCSEL;
assign #(in_delay) delay_TRNRDSTRDY = TRNRDSTRDY;
assign #(in_delay) delay_TRNRFCPRET = TRNRFCPRET;
assign #(in_delay) delay_TRNRNPOK = TRNRNPOK;
assign #(in_delay) delay_TRNRNPREQ = TRNRNPREQ;
assign #(in_delay) delay_TRNTCFGGNT = TRNTCFGGNT;
assign #(in_delay) delay_TRNTD = TRNTD;
assign #(in_delay) delay_TRNTDLLPDATA = TRNTDLLPDATA;
assign #(in_delay) delay_TRNTDLLPSRCRDY = TRNTDLLPSRCRDY;
assign #(in_delay) delay_TRNTECRCGEN = TRNTECRCGEN;
assign #(in_delay) delay_TRNTEOF = TRNTEOF;
assign #(in_delay) delay_TRNTERRFWD = TRNTERRFWD;
assign #(in_delay) delay_TRNTREM = TRNTREM;
assign #(in_delay) delay_TRNTSOF = TRNTSOF;
assign #(in_delay) delay_TRNTSRCDSC = TRNTSRCDSC;
assign #(in_delay) delay_TRNTSRCRDY = TRNTSRCRDY;
assign #(in_delay) delay_TRNTSTR = TRNTSTR;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_SYSRSTN = SYSRSTN;
`endif
B_PCIE_2_1 #(
.AER_BASE_PTR (AER_BASE_PTR),
.AER_CAP_ECRC_CHECK_CAPABLE (AER_CAP_ECRC_CHECK_CAPABLE),
.AER_CAP_ECRC_GEN_CAPABLE (AER_CAP_ECRC_GEN_CAPABLE),
.AER_CAP_ID (AER_CAP_ID),
.AER_CAP_MULTIHEADER (AER_CAP_MULTIHEADER),
.AER_CAP_NEXTPTR (AER_CAP_NEXTPTR),
.AER_CAP_ON (AER_CAP_ON),
.AER_CAP_OPTIONAL_ERR_SUPPORT (AER_CAP_OPTIONAL_ERR_SUPPORT),
.AER_CAP_PERMIT_ROOTERR_UPDATE (AER_CAP_PERMIT_ROOTERR_UPDATE),
.AER_CAP_VERSION (AER_CAP_VERSION),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 (BAR0),
.BAR1 (BAR1),
.BAR2 (BAR2),
.BAR3 (BAR3),
.BAR4 (BAR4),
.BAR5 (BAR5),
.CAPABILITIES_PTR (CAPABILITIES_PTR),
.CARDBUS_CIS_POINTER (CARDBUS_CIS_POINTER),
.CFG_ECRC_ERR_CPLSTAT (CFG_ECRC_ERR_CPLSTAT),
.CLASS_CODE (CLASS_CODE),
.CMD_INTX_IMPLEMENTED (CMD_INTX_IMPLEMENTED),
.CPL_TIMEOUT_DISABLE_SUPPORTED (CPL_TIMEOUT_DISABLE_SUPPORTED),
.CPL_TIMEOUT_RANGES_SUPPORTED (CPL_TIMEOUT_RANGES_SUPPORTED),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED (DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE),
.DEV_CAP_ENDPOINT_L0S_LATENCY (DEV_CAP_ENDPOINT_L0S_LATENCY),
.DEV_CAP_ENDPOINT_L1_LATENCY (DEV_CAP_ENDPOINT_L1_LATENCY),
.DEV_CAP_EXT_TAG_SUPPORTED (DEV_CAP_EXT_TAG_SUPPORTED),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED (DEV_CAP_MAX_PAYLOAD_SUPPORTED),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT),
.DEV_CAP_ROLE_BASED_ERROR (DEV_CAP_ROLE_BASED_ERROR),
.DEV_CAP_RSVD_14_12 (DEV_CAP_RSVD_14_12),
.DEV_CAP_RSVD_17_16 (DEV_CAP_RSVD_17_16),
.DEV_CAP_RSVD_31_29 (DEV_CAP_RSVD_31_29),
.DEV_CONTROL_AUX_POWER_SUPPORTED (DEV_CONTROL_AUX_POWER_SUPPORTED),
.DEV_CONTROL_EXT_TAG_DEFAULT (DEV_CONTROL_EXT_TAG_DEFAULT),
.DISABLE_ASPM_L1_TIMER (DISABLE_ASPM_L1_TIMER),
.DISABLE_BAR_FILTERING (DISABLE_BAR_FILTERING),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_ID_CHECK (DISABLE_ID_CHECK),
.DISABLE_LANE_REVERSAL (DISABLE_LANE_REVERSAL),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER (DISABLE_RX_TC_FILTER),
.DISABLE_SCRAMBLING (DISABLE_SCRAMBLING),
.DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
.DSN_BASE_PTR (DSN_BASE_PTR),
.DSN_CAP_ID (DSN_CAP_ID),
.DSN_CAP_NEXTPTR (DSN_CAP_NEXTPTR),
.DSN_CAP_ON (DSN_CAP_ON),
.DSN_CAP_VERSION (DSN_CAP_VERSION),
.ENABLE_MSG_ROUTE (ENABLE_MSG_ROUTE),
.ENABLE_RX_TD_ECRC_TRIM (ENABLE_RX_TD_ECRC_TRIM),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENTER_RVRY_EI_L0 (ENTER_RVRY_EI_L0),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM (EXPANSION_ROM),
.EXT_CFG_CAP_PTR (EXT_CFG_CAP_PTR),
.EXT_CFG_XP_CAP_PTR (EXT_CFG_XP_CAP_PTR),
.HEADER_TYPE (HEADER_TYPE),
.INFER_EI (INFER_EI),
.INTERRUPT_PIN (INTERRUPT_PIN),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH (IS_SWITCH),
.LAST_CONFIG_DWORD (LAST_CONFIG_DWORD),
.LINK_CAP_ASPM_OPTIONALITY (LINK_CAP_ASPM_OPTIONALITY),
.LINK_CAP_ASPM_SUPPORT (LINK_CAP_ASPM_SUPPORT),
.LINK_CAP_CLOCK_POWER_MANAGEMENT (LINK_CAP_CLOCK_POWER_MANAGEMENT),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 (LINK_CAP_L1_EXIT_LATENCY_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 (LINK_CAP_L1_EXIT_LATENCY_GEN2),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED (LINK_CAP_MAX_LINK_SPEED),
.LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_RSVD_23 (LINK_CAP_RSVD_23),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE),
.LINK_CONTROL_RCB (LINK_CONTROL_RCB),
.LINK_CTRL2_DEEMPHASIS (LINK_CTRL2_DEEMPHASIS),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE),
.LINK_CTRL2_TARGET_LINK_SPEED (LINK_CTRL2_TARGET_LINK_SPEED),
.LINK_STATUS_SLOT_CLOCK_CONFIG (LINK_STATUS_SLOT_CLOCK_CONFIG),
.LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
.LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
.LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
.LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
.LTSSM_MAX_LINK_WIDTH (LTSSM_MAX_LINK_WIDTH),
.MPS_FORCE (MPS_FORCE),
.MSIX_BASE_PTR (MSIX_BASE_PTR),
.MSIX_CAP_ID (MSIX_CAP_ID),
.MSIX_CAP_NEXTPTR (MSIX_CAP_NEXTPTR),
.MSIX_CAP_ON (MSIX_CAP_ON),
.MSIX_CAP_PBA_BIR (MSIX_CAP_PBA_BIR),
.MSIX_CAP_PBA_OFFSET (MSIX_CAP_PBA_OFFSET),
.MSIX_CAP_TABLE_BIR (MSIX_CAP_TABLE_BIR),
.MSIX_CAP_TABLE_OFFSET (MSIX_CAP_TABLE_OFFSET),
.MSIX_CAP_TABLE_SIZE (MSIX_CAP_TABLE_SIZE),
.MSI_BASE_PTR (MSI_BASE_PTR),
.MSI_CAP_64_BIT_ADDR_CAPABLE (MSI_CAP_64_BIT_ADDR_CAPABLE),
.MSI_CAP_ID (MSI_CAP_ID),
.MSI_CAP_MULTIMSGCAP (MSI_CAP_MULTIMSGCAP),
.MSI_CAP_MULTIMSG_EXTENSION (MSI_CAP_MULTIMSG_EXTENSION),
.MSI_CAP_NEXTPTR (MSI_CAP_NEXTPTR),
.MSI_CAP_ON (MSI_CAP_ON),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE (MSI_CAP_PER_VECTOR_MASKING_CAPABLE),
.N_FTS_COMCLK_GEN1 (N_FTS_COMCLK_GEN1),
.N_FTS_COMCLK_GEN2 (N_FTS_COMCLK_GEN2),
.N_FTS_GEN1 (N_FTS_GEN1),
.N_FTS_GEN2 (N_FTS_GEN2),
.PCIE_BASE_PTR (PCIE_BASE_PTR),
.PCIE_CAP_CAPABILITY_ID (PCIE_CAP_CAPABILITY_ID),
.PCIE_CAP_CAPABILITY_VERSION (PCIE_CAP_CAPABILITY_VERSION),
.PCIE_CAP_DEVICE_PORT_TYPE (PCIE_CAP_DEVICE_PORT_TYPE),
.PCIE_CAP_NEXTPTR (PCIE_CAP_NEXTPTR),
.PCIE_CAP_ON (PCIE_CAP_ON),
.PCIE_CAP_RSVD_15_14 (PCIE_CAP_RSVD_15_14),
.PCIE_CAP_SLOT_IMPLEMENTED (PCIE_CAP_SLOT_IMPLEMENTED),
.PCIE_REVISION (PCIE_REVISION),
.PL_AUTO_CONFIG (PL_AUTO_CONFIG),
.PL_FAST_TRAIN (PL_FAST_TRAIN),
.PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
.PM_ASPML0S_TIMEOUT_EN (PM_ASPML0S_TIMEOUT_EN),
.PM_ASPML0S_TIMEOUT_FUNC (PM_ASPML0S_TIMEOUT_FUNC),
.PM_ASPM_FASTEXIT (PM_ASPM_FASTEXIT),
.PM_BASE_PTR (PM_BASE_PTR),
.PM_CAP_AUXCURRENT (PM_CAP_AUXCURRENT),
.PM_CAP_D1SUPPORT (PM_CAP_D1SUPPORT),
.PM_CAP_D2SUPPORT (PM_CAP_D2SUPPORT),
.PM_CAP_DSI (PM_CAP_DSI),
.PM_CAP_ID (PM_CAP_ID),
.PM_CAP_NEXTPTR (PM_CAP_NEXTPTR),
.PM_CAP_ON (PM_CAP_ON),
.PM_CAP_PMESUPPORT (PM_CAP_PMESUPPORT),
.PM_CAP_PME_CLOCK (PM_CAP_PME_CLOCK),
.PM_CAP_RSVD_04 (PM_CAP_RSVD_04),
.PM_CAP_VERSION (PM_CAP_VERSION),
.PM_CSR_B2B3 (PM_CSR_B2B3),
.PM_CSR_BPCCEN (PM_CSR_BPCCEN),
.PM_CSR_NOSOFTRST (PM_CSR_NOSOFTRST),
.PM_DATA0 (PM_DATA0),
.PM_DATA1 (PM_DATA1),
.PM_DATA2 (PM_DATA2),
.PM_DATA3 (PM_DATA3),
.PM_DATA4 (PM_DATA4),
.PM_DATA5 (PM_DATA5),
.PM_DATA6 (PM_DATA6),
.PM_DATA7 (PM_DATA7),
.PM_DATA_SCALE0 (PM_DATA_SCALE0),
.PM_DATA_SCALE1 (PM_DATA_SCALE1),
.PM_DATA_SCALE2 (PM_DATA_SCALE2),
.PM_DATA_SCALE3 (PM_DATA_SCALE3),
.PM_DATA_SCALE4 (PM_DATA_SCALE4),
.PM_DATA_SCALE5 (PM_DATA_SCALE5),
.PM_DATA_SCALE6 (PM_DATA_SCALE6),
.PM_DATA_SCALE7 (PM_DATA_SCALE7),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY (ROOT_CAP_CRS_SW_VISIBILITY),
.RP_AUTO_SPD (RP_AUTO_SPD),
.RP_AUTO_SPD_LOOPCNT (RP_AUTO_SPD_LOOPCNT),
.SELECT_DLL_IF (SELECT_DLL_IF),
.SIM_VERSION (SIM_VERSION),
.SLOT_CAP_ATT_BUTTON_PRESENT (SLOT_CAP_ATT_BUTTON_PRESENT),
.SLOT_CAP_ATT_INDICATOR_PRESENT (SLOT_CAP_ATT_INDICATOR_PRESENT),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT (SLOT_CAP_ELEC_INTERLOCK_PRESENT),
.SLOT_CAP_HOTPLUG_CAPABLE (SLOT_CAP_HOTPLUG_CAPABLE),
.SLOT_CAP_HOTPLUG_SURPRISE (SLOT_CAP_HOTPLUG_SURPRISE),
.SLOT_CAP_MRL_SENSOR_PRESENT (SLOT_CAP_MRL_SENSOR_PRESENT),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT),
.SLOT_CAP_PHYSICAL_SLOT_NUM (SLOT_CAP_PHYSICAL_SLOT_NUM),
.SLOT_CAP_POWER_CONTROLLER_PRESENT (SLOT_CAP_POWER_CONTROLLER_PRESENT),
.SLOT_CAP_POWER_INDICATOR_PRESENT (SLOT_CAP_POWER_INDICATOR_PRESENT),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE (SLOT_CAP_SLOT_POWER_LIMIT_SCALE),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE (SLOT_CAP_SLOT_POWER_LIMIT_VALUE),
.SPARE_BIT0 (SPARE_BIT0),
.SPARE_BIT1 (SPARE_BIT1),
.SPARE_BIT2 (SPARE_BIT2),
.SPARE_BIT3 (SPARE_BIT3),
.SPARE_BIT4 (SPARE_BIT4),
.SPARE_BIT5 (SPARE_BIT5),
.SPARE_BIT6 (SPARE_BIT6),
.SPARE_BIT7 (SPARE_BIT7),
.SPARE_BIT8 (SPARE_BIT8),
.SPARE_BYTE0 (SPARE_BYTE0),
.SPARE_BYTE1 (SPARE_BYTE1),
.SPARE_BYTE2 (SPARE_BYTE2),
.SPARE_BYTE3 (SPARE_BYTE3),
.SPARE_WORD0 (SPARE_WORD0),
.SPARE_WORD1 (SPARE_WORD1),
.SPARE_WORD2 (SPARE_WORD2),
.SPARE_WORD3 (SPARE_WORD3),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV (TECRC_EP_INV),
.TL_RBYPASS (TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY (TL_RX_RAM_RADDR_LATENCY),
.TL_RX_RAM_RDATA_LATENCY (TL_RX_RAM_RDATA_LATENCY),
.TL_RX_RAM_WRITE_LATENCY (TL_RX_RAM_WRITE_LATENCY),
.TL_TFC_DISABLE (TL_TFC_DISABLE),
.TL_TX_CHECKS_DISABLE (TL_TX_CHECKS_DISABLE),
.TL_TX_RAM_RADDR_LATENCY (TL_TX_RAM_RADDR_LATENCY),
.TL_TX_RAM_RDATA_LATENCY (TL_TX_RAM_RDATA_LATENCY),
.TL_TX_RAM_WRITE_LATENCY (TL_TX_RAM_WRITE_LATENCY),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE (UPCONFIG_CAPABLE),
.UPSTREAM_FACING (UPSTREAM_FACING),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ (UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ (USER_CLK_FREQ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE (VC0_CPL_INFINITE),
.VC0_RX_RAM_LIMIT (VC0_RX_RAM_LIMIT),
.VC0_TOTAL_CREDITS_CD (VC0_TOTAL_CREDITS_CD),
.VC0_TOTAL_CREDITS_CH (VC0_TOTAL_CREDITS_CH),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH (VC0_TOTAL_CREDITS_NPH),
.VC0_TOTAL_CREDITS_PD (VC0_TOTAL_CREDITS_PD),
.VC0_TOTAL_CREDITS_PH (VC0_TOTAL_CREDITS_PH),
.VC0_TX_LASTPACKET (VC0_TX_LASTPACKET),
.VC_BASE_PTR (VC_BASE_PTR),
.VC_CAP_ID (VC_CAP_ID),
.VC_CAP_NEXTPTR (VC_CAP_NEXTPTR),
.VC_CAP_ON (VC_CAP_ON),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS (VC_CAP_REJECT_SNOOP_TRANSACTIONS),
.VC_CAP_VERSION (VC_CAP_VERSION),
.VSEC_BASE_PTR (VSEC_BASE_PTR),
.VSEC_CAP_HDR_ID (VSEC_CAP_HDR_ID),
.VSEC_CAP_HDR_LENGTH (VSEC_CAP_HDR_LENGTH),
.VSEC_CAP_HDR_REVISION (VSEC_CAP_HDR_REVISION),
.VSEC_CAP_ID (VSEC_CAP_ID),
.VSEC_CAP_IS_LINK_VISIBLE (VSEC_CAP_IS_LINK_VISIBLE),
.VSEC_CAP_NEXTPTR (VSEC_CAP_NEXTPTR),
.VSEC_CAP_ON (VSEC_CAP_ON),
.VSEC_CAP_VERSION (VSEC_CAP_VERSION))
B_PCIE_2_1_INST (
.CFGAERECRCCHECKEN (delay_CFGAERECRCCHECKEN),
.CFGAERECRCGENEN (delay_CFGAERECRCGENEN),
.CFGAERROOTERRCORRERRRECEIVED (delay_CFGAERROOTERRCORRERRRECEIVED),
.CFGAERROOTERRCORRERRREPORTINGEN (delay_CFGAERROOTERRCORRERRREPORTINGEN),
.CFGAERROOTERRFATALERRRECEIVED (delay_CFGAERROOTERRFATALERRRECEIVED),
.CFGAERROOTERRFATALERRREPORTINGEN (delay_CFGAERROOTERRFATALERRREPORTINGEN),
.CFGAERROOTERRNONFATALERRRECEIVED (delay_CFGAERROOTERRNONFATALERRRECEIVED),
.CFGAERROOTERRNONFATALERRREPORTINGEN (delay_CFGAERROOTERRNONFATALERRREPORTINGEN),
.CFGBRIDGESERREN (delay_CFGBRIDGESERREN),
.CFGCOMMANDBUSMASTERENABLE (delay_CFGCOMMANDBUSMASTERENABLE),
.CFGCOMMANDINTERRUPTDISABLE (delay_CFGCOMMANDINTERRUPTDISABLE),
.CFGCOMMANDIOENABLE (delay_CFGCOMMANDIOENABLE),
.CFGCOMMANDMEMENABLE (delay_CFGCOMMANDMEMENABLE),
.CFGCOMMANDSERREN (delay_CFGCOMMANDSERREN),
.CFGDEVCONTROL2ARIFORWARDEN (delay_CFGDEVCONTROL2ARIFORWARDEN),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK (delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK),
.CFGDEVCONTROL2ATOMICREQUESTEREN (delay_CFGDEVCONTROL2ATOMICREQUESTEREN),
.CFGDEVCONTROL2CPLTIMEOUTDIS (delay_CFGDEVCONTROL2CPLTIMEOUTDIS),
.CFGDEVCONTROL2CPLTIMEOUTVAL (delay_CFGDEVCONTROL2CPLTIMEOUTVAL),
.CFGDEVCONTROL2IDOCPLEN (delay_CFGDEVCONTROL2IDOCPLEN),
.CFGDEVCONTROL2IDOREQEN (delay_CFGDEVCONTROL2IDOREQEN),
.CFGDEVCONTROL2LTREN (delay_CFGDEVCONTROL2LTREN),
.CFGDEVCONTROL2TLPPREFIXBLOCK (delay_CFGDEVCONTROL2TLPPREFIXBLOCK),
.CFGDEVCONTROLAUXPOWEREN (delay_CFGDEVCONTROLAUXPOWEREN),
.CFGDEVCONTROLCORRERRREPORTINGEN (delay_CFGDEVCONTROLCORRERRREPORTINGEN),
.CFGDEVCONTROLENABLERO (delay_CFGDEVCONTROLENABLERO),
.CFGDEVCONTROLEXTTAGEN (delay_CFGDEVCONTROLEXTTAGEN),
.CFGDEVCONTROLFATALERRREPORTINGEN (delay_CFGDEVCONTROLFATALERRREPORTINGEN),
.CFGDEVCONTROLMAXPAYLOAD (delay_CFGDEVCONTROLMAXPAYLOAD),
.CFGDEVCONTROLMAXREADREQ (delay_CFGDEVCONTROLMAXREADREQ),
.CFGDEVCONTROLNONFATALREPORTINGEN (delay_CFGDEVCONTROLNONFATALREPORTINGEN),
.CFGDEVCONTROLNOSNOOPEN (delay_CFGDEVCONTROLNOSNOOPEN),
.CFGDEVCONTROLPHANTOMEN (delay_CFGDEVCONTROLPHANTOMEN),
.CFGDEVCONTROLURERRREPORTINGEN (delay_CFGDEVCONTROLURERRREPORTINGEN),
.CFGDEVSTATUSCORRERRDETECTED (delay_CFGDEVSTATUSCORRERRDETECTED),
.CFGDEVSTATUSFATALERRDETECTED (delay_CFGDEVSTATUSFATALERRDETECTED),
.CFGDEVSTATUSNONFATALERRDETECTED (delay_CFGDEVSTATUSNONFATALERRDETECTED),
.CFGDEVSTATUSURDETECTED (delay_CFGDEVSTATUSURDETECTED),
.CFGERRAERHEADERLOGSETN (delay_CFGERRAERHEADERLOGSETN),
.CFGERRCPLRDYN (delay_CFGERRCPLRDYN),
.CFGINTERRUPTDO (delay_CFGINTERRUPTDO),
.CFGINTERRUPTMMENABLE (delay_CFGINTERRUPTMMENABLE),
.CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFM (delay_CFGINTERRUPTMSIXFM),
.CFGINTERRUPTRDYN (delay_CFGINTERRUPTRDYN),
.CFGLINKCONTROLASPMCONTROL (delay_CFGLINKCONTROLASPMCONTROL),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN (delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN),
.CFGLINKCONTROLBANDWIDTHINTEN (delay_CFGLINKCONTROLBANDWIDTHINTEN),
.CFGLINKCONTROLCLOCKPMEN (delay_CFGLINKCONTROLCLOCKPMEN),
.CFGLINKCONTROLCOMMONCLOCK (delay_CFGLINKCONTROLCOMMONCLOCK),
.CFGLINKCONTROLEXTENDEDSYNC (delay_CFGLINKCONTROLEXTENDEDSYNC),
.CFGLINKCONTROLHWAUTOWIDTHDIS (delay_CFGLINKCONTROLHWAUTOWIDTHDIS),
.CFGLINKCONTROLLINKDISABLE (delay_CFGLINKCONTROLLINKDISABLE),
.CFGLINKCONTROLRCB (delay_CFGLINKCONTROLRCB),
.CFGLINKCONTROLRETRAINLINK (delay_CFGLINKCONTROLRETRAINLINK),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS (delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS),
.CFGLINKSTATUSBANDWIDTHSTATUS (delay_CFGLINKSTATUSBANDWIDTHSTATUS),
.CFGLINKSTATUSCURRENTSPEED (delay_CFGLINKSTATUSCURRENTSPEED),
.CFGLINKSTATUSDLLACTIVE (delay_CFGLINKSTATUSDLLACTIVE),
.CFGLINKSTATUSLINKTRAINING (delay_CFGLINKSTATUSLINKTRAINING),
.CFGLINKSTATUSNEGOTIATEDWIDTH (delay_CFGLINKSTATUSNEGOTIATEDWIDTH),
.CFGMGMTDO (delay_CFGMGMTDO),
.CFGMGMTRDWRDONEN (delay_CFGMGMTRDWRDONEN),
.CFGMSGDATA (delay_CFGMSGDATA),
.CFGMSGRECEIVED (delay_CFGMSGRECEIVED),
.CFGMSGRECEIVEDASSERTINTA (delay_CFGMSGRECEIVEDASSERTINTA),
.CFGMSGRECEIVEDASSERTINTB (delay_CFGMSGRECEIVEDASSERTINTB),
.CFGMSGRECEIVEDASSERTINTC (delay_CFGMSGRECEIVEDASSERTINTC),
.CFGMSGRECEIVEDASSERTINTD (delay_CFGMSGRECEIVEDASSERTINTD),
.CFGMSGRECEIVEDDEASSERTINTA (delay_CFGMSGRECEIVEDDEASSERTINTA),
.CFGMSGRECEIVEDDEASSERTINTB (delay_CFGMSGRECEIVEDDEASSERTINTB),
.CFGMSGRECEIVEDDEASSERTINTC (delay_CFGMSGRECEIVEDDEASSERTINTC),
.CFGMSGRECEIVEDDEASSERTINTD (delay_CFGMSGRECEIVEDDEASSERTINTD),
.CFGMSGRECEIVEDERRCOR (delay_CFGMSGRECEIVEDERRCOR),
.CFGMSGRECEIVEDERRFATAL (delay_CFGMSGRECEIVEDERRFATAL),
.CFGMSGRECEIVEDERRNONFATAL (delay_CFGMSGRECEIVEDERRNONFATAL),
.CFGMSGRECEIVEDPMASNAK (delay_CFGMSGRECEIVEDPMASNAK),
.CFGMSGRECEIVEDPMETO (delay_CFGMSGRECEIVEDPMETO),
.CFGMSGRECEIVEDPMETOACK (delay_CFGMSGRECEIVEDPMETOACK),
.CFGMSGRECEIVEDPMPME (delay_CFGMSGRECEIVEDPMPME),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT (delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT),
.CFGMSGRECEIVEDUNLOCK (delay_CFGMSGRECEIVEDUNLOCK),
.CFGPCIELINKSTATE (delay_CFGPCIELINKSTATE),
.CFGPMCSRPMEEN (delay_CFGPMCSRPMEEN),
.CFGPMCSRPMESTATUS (delay_CFGPMCSRPMESTATUS),
.CFGPMCSRPOWERSTATE (delay_CFGPMCSRPOWERSTATE),
.CFGPMRCVASREQL1N (delay_CFGPMRCVASREQL1N),
.CFGPMRCVENTERL1N (delay_CFGPMRCVENTERL1N),
.CFGPMRCVENTERL23N (delay_CFGPMRCVENTERL23N),
.CFGPMRCVREQACKN (delay_CFGPMRCVREQACKN),
.CFGROOTCONTROLPMEINTEN (delay_CFGROOTCONTROLPMEINTEN),
.CFGROOTCONTROLSYSERRCORRERREN (delay_CFGROOTCONTROLSYSERRCORRERREN),
.CFGROOTCONTROLSYSERRFATALERREN (delay_CFGROOTCONTROLSYSERRFATALERREN),
.CFGROOTCONTROLSYSERRNONFATALERREN (delay_CFGROOTCONTROLSYSERRNONFATALERREN),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE (delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE),
.CFGTRANSACTION (delay_CFGTRANSACTION),
.CFGTRANSACTIONADDR (delay_CFGTRANSACTIONADDR),
.CFGTRANSACTIONTYPE (delay_CFGTRANSACTIONTYPE),
.CFGVCTCVCMAP (delay_CFGVCTCVCMAP),
.DBGSCLRA (delay_DBGSCLRA),
.DBGSCLRB (delay_DBGSCLRB),
.DBGSCLRC (delay_DBGSCLRC),
.DBGSCLRD (delay_DBGSCLRD),
.DBGSCLRE (delay_DBGSCLRE),
.DBGSCLRF (delay_DBGSCLRF),
.DBGSCLRG (delay_DBGSCLRG),
.DBGSCLRH (delay_DBGSCLRH),
.DBGSCLRI (delay_DBGSCLRI),
.DBGSCLRJ (delay_DBGSCLRJ),
.DBGSCLRK (delay_DBGSCLRK),
.DBGVECA (delay_DBGVECA),
.DBGVECB (delay_DBGVECB),
.DBGVECC (delay_DBGVECC),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.LL2BADDLLPERR (delay_LL2BADDLLPERR),
.LL2BADTLPERR (delay_LL2BADTLPERR),
.LL2LINKSTATUS (delay_LL2LINKSTATUS),
.LL2PROTOCOLERR (delay_LL2PROTOCOLERR),
.LL2RECEIVERERR (delay_LL2RECEIVERERR),
.LL2REPLAYROERR (delay_LL2REPLAYROERR),
.LL2REPLAYTOERR (delay_LL2REPLAYTOERR),
.LL2SUSPENDOK (delay_LL2SUSPENDOK),
.LL2TFCINIT1SEQ (delay_LL2TFCINIT1SEQ),
.LL2TFCINIT2SEQ (delay_LL2TFCINIT2SEQ),
.LL2TXIDLE (delay_LL2TXIDLE),
.LNKCLKEN (delay_LNKCLKEN),
.MIMRXRADDR (delay_MIMRXRADDR),
.MIMRXREN (delay_MIMRXREN),
.MIMRXWADDR (delay_MIMRXWADDR),
.MIMRXWDATA (delay_MIMRXWDATA),
.MIMRXWEN (delay_MIMRXWEN),
.MIMTXRADDR (delay_MIMTXRADDR),
.MIMTXREN (delay_MIMTXREN),
.MIMTXWADDR (delay_MIMTXWADDR),
.MIMTXWDATA (delay_MIMTXWDATA),
.MIMTXWEN (delay_MIMTXWEN),
.PIPERX0POLARITY (delay_PIPERX0POLARITY),
.PIPERX1POLARITY (delay_PIPERX1POLARITY),
.PIPERX2POLARITY (delay_PIPERX2POLARITY),
.PIPERX3POLARITY (delay_PIPERX3POLARITY),
.PIPERX4POLARITY (delay_PIPERX4POLARITY),
.PIPERX5POLARITY (delay_PIPERX5POLARITY),
.PIPERX6POLARITY (delay_PIPERX6POLARITY),
.PIPERX7POLARITY (delay_PIPERX7POLARITY),
.PIPETX0CHARISK (delay_PIPETX0CHARISK),
.PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE),
.PIPETX0DATA (delay_PIPETX0DATA),
.PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE),
.PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN),
.PIPETX1CHARISK (delay_PIPETX1CHARISK),
.PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE),
.PIPETX1DATA (delay_PIPETX1DATA),
.PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE),
.PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN),
.PIPETX2CHARISK (delay_PIPETX2CHARISK),
.PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE),
.PIPETX2DATA (delay_PIPETX2DATA),
.PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE),
.PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN),
.PIPETX3CHARISK (delay_PIPETX3CHARISK),
.PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE),
.PIPETX3DATA (delay_PIPETX3DATA),
.PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE),
.PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN),
.PIPETX4CHARISK (delay_PIPETX4CHARISK),
.PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE),
.PIPETX4DATA (delay_PIPETX4DATA),
.PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE),
.PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN),
.PIPETX5CHARISK (delay_PIPETX5CHARISK),
.PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE),
.PIPETX5DATA (delay_PIPETX5DATA),
.PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE),
.PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN),
.PIPETX6CHARISK (delay_PIPETX6CHARISK),
.PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE),
.PIPETX6DATA (delay_PIPETX6DATA),
.PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE),
.PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN),
.PIPETX7CHARISK (delay_PIPETX7CHARISK),
.PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE),
.PIPETX7DATA (delay_PIPETX7DATA),
.PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE),
.PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN),
.PIPETXDEEMPH (delay_PIPETXDEEMPH),
.PIPETXMARGIN (delay_PIPETXMARGIN),
.PIPETXRATE (delay_PIPETXRATE),
.PIPETXRCVRDET (delay_PIPETXRCVRDET),
.PIPETXRESET (delay_PIPETXRESET),
.PL2L0REQ (delay_PL2L0REQ),
.PL2LINKUP (delay_PL2LINKUP),
.PL2RECEIVERERR (delay_PL2RECEIVERERR),
.PL2RECOVERY (delay_PL2RECOVERY),
.PL2RXELECIDLE (delay_PL2RXELECIDLE),
.PL2RXPMSTATE (delay_PL2RXPMSTATE),
.PL2SUSPENDOK (delay_PL2SUSPENDOK),
.PLDBGVEC (delay_PLDBGVEC),
.PLDIRECTEDCHANGEDONE (delay_PLDIRECTEDCHANGEDONE),
.PLINITIALLINKWIDTH (delay_PLINITIALLINKWIDTH),
.PLLANEREVERSALMODE (delay_PLLANEREVERSALMODE),
.PLLINKGEN2CAP (delay_PLLINKGEN2CAP),
.PLLINKPARTNERGEN2SUPPORTED (delay_PLLINKPARTNERGEN2SUPPORTED),
.PLLINKUPCFGCAP (delay_PLLINKUPCFGCAP),
.PLLTSSMSTATE (delay_PLLTSSMSTATE),
.PLPHYLNKUPN (delay_PLPHYLNKUPN),
.PLRECEIVEDHOTRST (delay_PLRECEIVEDHOTRST),
.PLRXPMSTATE (delay_PLRXPMSTATE),
.PLSELLNKRATE (delay_PLSELLNKRATE),
.PLSELLNKWIDTH (delay_PLSELLNKWIDTH),
.PLTXPMSTATE (delay_PLTXPMSTATE),
.RECEIVEDFUNCLVLRSTN (delay_RECEIVEDFUNCLVLRSTN),
.TL2ASPMSUSPENDCREDITCHECKOK (delay_TL2ASPMSUSPENDCREDITCHECKOK),
.TL2ASPMSUSPENDREQ (delay_TL2ASPMSUSPENDREQ),
.TL2ERRFCPE (delay_TL2ERRFCPE),
.TL2ERRHDR (delay_TL2ERRHDR),
.TL2ERRMALFORMED (delay_TL2ERRMALFORMED),
.TL2ERRRXOVERFLOW (delay_TL2ERRRXOVERFLOW),
.TL2PPMSUSPENDOK (delay_TL2PPMSUSPENDOK),
.TRNFCCPLD (delay_TRNFCCPLD),
.TRNFCCPLH (delay_TRNFCCPLH),
.TRNFCNPD (delay_TRNFCNPD),
.TRNFCNPH (delay_TRNFCNPH),
.TRNFCPD (delay_TRNFCPD),
.TRNFCPH (delay_TRNFCPH),
.TRNLNKUP (delay_TRNLNKUP),
.TRNRBARHIT (delay_TRNRBARHIT),
.TRNRD (delay_TRNRD),
.TRNRDLLPDATA (delay_TRNRDLLPDATA),
.TRNRDLLPSRCRDY (delay_TRNRDLLPSRCRDY),
.TRNRECRCERR (delay_TRNRECRCERR),
.TRNREOF (delay_TRNREOF),
.TRNRERRFWD (delay_TRNRERRFWD),
.TRNRREM (delay_TRNRREM),
.TRNRSOF (delay_TRNRSOF),
.TRNRSRCDSC (delay_TRNRSRCDSC),
.TRNRSRCRDY (delay_TRNRSRCRDY),
.TRNTBUFAV (delay_TRNTBUFAV),
.TRNTCFGREQ (delay_TRNTCFGREQ),
.TRNTDLLPDSTRDY (delay_TRNTDLLPDSTRDY),
.TRNTDSTRDY (delay_TRNTDSTRDY),
.TRNTERRDROP (delay_TRNTERRDROP),
.USERRSTN (delay_USERRSTN),
.CFGAERINTERRUPTMSGNUM (delay_CFGAERINTERRUPTMSGNUM),
.CFGDEVID (delay_CFGDEVID),
.CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER),
.CFGDSN (delay_CFGDSN),
.CFGERRACSN (delay_CFGERRACSN),
.CFGERRAERHEADERLOG (delay_CFGERRAERHEADERLOG),
.CFGERRATOMICEGRESSBLOCKEDN (delay_CFGERRATOMICEGRESSBLOCKEDN),
.CFGERRCORN (delay_CFGERRCORN),
.CFGERRCPLABORTN (delay_CFGERRCPLABORTN),
.CFGERRCPLTIMEOUTN (delay_CFGERRCPLTIMEOUTN),
.CFGERRCPLUNEXPECTN (delay_CFGERRCPLUNEXPECTN),
.CFGERRECRCN (delay_CFGERRECRCN),
.CFGERRINTERNALCORN (delay_CFGERRINTERNALCORN),
.CFGERRINTERNALUNCORN (delay_CFGERRINTERNALUNCORN),
.CFGERRLOCKEDN (delay_CFGERRLOCKEDN),
.CFGERRMALFORMEDN (delay_CFGERRMALFORMEDN),
.CFGERRMCBLOCKEDN (delay_CFGERRMCBLOCKEDN),
.CFGERRNORECOVERYN (delay_CFGERRNORECOVERYN),
.CFGERRPOISONEDN (delay_CFGERRPOISONEDN),
.CFGERRPOSTEDN (delay_CFGERRPOSTEDN),
.CFGERRTLPCPLHEADER (delay_CFGERRTLPCPLHEADER),
.CFGERRURN (delay_CFGERRURN),
.CFGFORCECOMMONCLOCKOFF (delay_CFGFORCECOMMONCLOCKOFF),
.CFGFORCEEXTENDEDSYNCON (delay_CFGFORCEEXTENDEDSYNCON),
.CFGFORCEMPS (delay_CFGFORCEMPS),
.CFGINTERRUPTASSERTN (delay_CFGINTERRUPTASSERTN),
.CFGINTERRUPTDI (delay_CFGINTERRUPTDI),
.CFGINTERRUPTN (delay_CFGINTERRUPTN),
.CFGINTERRUPTSTATN (delay_CFGINTERRUPTSTATN),
.CFGMGMTBYTEENN (delay_CFGMGMTBYTEENN),
.CFGMGMTDI (delay_CFGMGMTDI),
.CFGMGMTDWADDR (delay_CFGMGMTDWADDR),
.CFGMGMTRDENN (delay_CFGMGMTRDENN),
.CFGMGMTWRENN (delay_CFGMGMTWRENN),
.CFGMGMTWRREADONLYN (delay_CFGMGMTWRREADONLYN),
.CFGMGMTWRRW1CASRWN (delay_CFGMGMTWRRW1CASRWN),
.CFGPCIECAPINTERRUPTMSGNUM (delay_CFGPCIECAPINTERRUPTMSGNUM),
.CFGPMFORCESTATE (delay_CFGPMFORCESTATE),
.CFGPMFORCESTATEENN (delay_CFGPMFORCESTATEENN),
.CFGPMHALTASPML0SN (delay_CFGPMHALTASPML0SN),
.CFGPMHALTASPML1N (delay_CFGPMHALTASPML1N),
.CFGPMSENDPMETON (delay_CFGPMSENDPMETON),
.CFGPMTURNOFFOKN (delay_CFGPMTURNOFFOKN),
.CFGPMWAKEN (delay_CFGPMWAKEN),
.CFGPORTNUMBER (delay_CFGPORTNUMBER),
.CFGREVID (delay_CFGREVID),
.CFGSUBSYSID (delay_CFGSUBSYSID),
.CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID),
.CFGTRNPENDINGN (delay_CFGTRNPENDINGN),
.CFGVENDID (delay_CFGVENDID),
.CMRSTN (delay_CMRSTN),
.CMSTICKYRSTN (delay_CMSTICKYRSTN),
.DBGMODE (delay_DBGMODE),
.DBGSUBMODE (delay_DBGSUBMODE),
.DLRSTN (delay_DLRSTN),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.FUNCLVLRSTN (delay_FUNCLVLRSTN),
.LL2SENDASREQL1 (delay_LL2SENDASREQL1),
.LL2SENDENTERL1 (delay_LL2SENDENTERL1),
.LL2SENDENTERL23 (delay_LL2SENDENTERL23),
.LL2SENDPMACK (delay_LL2SENDPMACK),
.LL2SUSPENDNOW (delay_LL2SUSPENDNOW),
.LL2TLPRCV (delay_LL2TLPRCV),
.MIMRXRDATA (delay_MIMRXRDATA),
.MIMTXRDATA (delay_MIMTXRDATA),
.PIPECLK (delay_PIPECLK),
.PIPERX0CHANISALIGNED (delay_PIPERX0CHANISALIGNED),
.PIPERX0CHARISK (delay_PIPERX0CHARISK),
.PIPERX0DATA (delay_PIPERX0DATA),
.PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE),
.PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS),
.PIPERX0STATUS (delay_PIPERX0STATUS),
.PIPERX0VALID (delay_PIPERX0VALID),
.PIPERX1CHANISALIGNED (delay_PIPERX1CHANISALIGNED),
.PIPERX1CHARISK (delay_PIPERX1CHARISK),
.PIPERX1DATA (delay_PIPERX1DATA),
.PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE),
.PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS),
.PIPERX1STATUS (delay_PIPERX1STATUS),
.PIPERX1VALID (delay_PIPERX1VALID),
.PIPERX2CHANISALIGNED (delay_PIPERX2CHANISALIGNED),
.PIPERX2CHARISK (delay_PIPERX2CHARISK),
.PIPERX2DATA (delay_PIPERX2DATA),
.PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE),
.PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS),
.PIPERX2STATUS (delay_PIPERX2STATUS),
.PIPERX2VALID (delay_PIPERX2VALID),
.PIPERX3CHANISALIGNED (delay_PIPERX3CHANISALIGNED),
.PIPERX3CHARISK (delay_PIPERX3CHARISK),
.PIPERX3DATA (delay_PIPERX3DATA),
.PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE),
.PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS),
.PIPERX3STATUS (delay_PIPERX3STATUS),
.PIPERX3VALID (delay_PIPERX3VALID),
.PIPERX4CHANISALIGNED (delay_PIPERX4CHANISALIGNED),
.PIPERX4CHARISK (delay_PIPERX4CHARISK),
.PIPERX4DATA (delay_PIPERX4DATA),
.PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE),
.PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS),
.PIPERX4STATUS (delay_PIPERX4STATUS),
.PIPERX4VALID (delay_PIPERX4VALID),
.PIPERX5CHANISALIGNED (delay_PIPERX5CHANISALIGNED),
.PIPERX5CHARISK (delay_PIPERX5CHARISK),
.PIPERX5DATA (delay_PIPERX5DATA),
.PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE),
.PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS),
.PIPERX5STATUS (delay_PIPERX5STATUS),
.PIPERX5VALID (delay_PIPERX5VALID),
.PIPERX6CHANISALIGNED (delay_PIPERX6CHANISALIGNED),
.PIPERX6CHARISK (delay_PIPERX6CHARISK),
.PIPERX6DATA (delay_PIPERX6DATA),
.PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE),
.PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS),
.PIPERX6STATUS (delay_PIPERX6STATUS),
.PIPERX6VALID (delay_PIPERX6VALID),
.PIPERX7CHANISALIGNED (delay_PIPERX7CHANISALIGNED),
.PIPERX7CHARISK (delay_PIPERX7CHARISK),
.PIPERX7DATA (delay_PIPERX7DATA),
.PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE),
.PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS),
.PIPERX7STATUS (delay_PIPERX7STATUS),
.PIPERX7VALID (delay_PIPERX7VALID),
.PL2DIRECTEDLSTATE (delay_PL2DIRECTEDLSTATE),
.PLDBGMODE (delay_PLDBGMODE),
.PLDIRECTEDLINKAUTON (delay_PLDIRECTEDLINKAUTON),
.PLDIRECTEDLINKCHANGE (delay_PLDIRECTEDLINKCHANGE),
.PLDIRECTEDLINKSPEED (delay_PLDIRECTEDLINKSPEED),
.PLDIRECTEDLINKWIDTH (delay_PLDIRECTEDLINKWIDTH),
.PLDIRECTEDLTSSMNEW (delay_PLDIRECTEDLTSSMNEW),
.PLDIRECTEDLTSSMNEWVLD (delay_PLDIRECTEDLTSSMNEWVLD),
.PLDIRECTEDLTSSMSTALL (delay_PLDIRECTEDLTSSMSTALL),
.PLDOWNSTREAMDEEMPHSOURCE (delay_PLDOWNSTREAMDEEMPHSOURCE),
.PLRSTN (delay_PLRSTN),
.PLTRANSMITHOTRST (delay_PLTRANSMITHOTRST),
.PLUPSTREAMPREFERDEEMPH (delay_PLUPSTREAMPREFERDEEMPH),
.SYSRSTN (delay_SYSRSTN),
.TL2ASPMSUSPENDCREDITCHECK (delay_TL2ASPMSUSPENDCREDITCHECK),
.TL2PPMSUSPENDREQ (delay_TL2PPMSUSPENDREQ),
.TLRSTN (delay_TLRSTN),
.TRNFCSEL (delay_TRNFCSEL),
.TRNRDSTRDY (delay_TRNRDSTRDY),
.TRNRFCPRET (delay_TRNRFCPRET),
.TRNRNPOK (delay_TRNRNPOK),
.TRNRNPREQ (delay_TRNRNPREQ),
.TRNTCFGGNT (delay_TRNTCFGGNT),
.TRNTD (delay_TRNTD),
.TRNTDLLPDATA (delay_TRNTDLLPDATA),
.TRNTDLLPSRCRDY (delay_TRNTDLLPSRCRDY),
.TRNTECRCGEN (delay_TRNTECRCGEN),
.TRNTEOF (delay_TRNTEOF),
.TRNTERRFWD (delay_TRNTERRFWD),
.TRNTREM (delay_TRNTREM),
.TRNTSOF (delay_TRNTSOF),
.TRNTSRCDSC (delay_TRNTSRCDSC),
.TRNTSRCRDY (delay_TRNTSRCRDY),
.TRNTSTR (delay_TRNTSTR),
.USERCLK (delay_USERCLK),
.USERCLK2 (delay_USERCLK2)
// .GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge PIPECLK, 0:0:0, notifier);
$period (posedge USERCLK, 0:0:0, notifier);
$period (posedge USERCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge PIPECLK, negedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID);
$setuphold (posedge PIPECLK, negedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID);
$setuphold (posedge PIPECLK, negedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID);
$setuphold (posedge PIPECLK, negedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID);
$setuphold (posedge PIPECLK, negedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID);
$setuphold (posedge PIPECLK, negedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID);
$setuphold (posedge PIPECLK, negedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID);
$setuphold (posedge PIPECLK, negedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL);
$setuphold (posedge PIPECLK, negedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE);
$setuphold (posedge PIPECLK, negedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN);
$setuphold (posedge PIPECLK, negedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST);
$setuphold (posedge PIPECLK, negedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH);
$setuphold (posedge PIPECLK, posedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID);
$setuphold (posedge PIPECLK, posedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID);
$setuphold (posedge PIPECLK, posedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID);
$setuphold (posedge PIPECLK, posedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID);
$setuphold (posedge PIPECLK, posedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID);
$setuphold (posedge PIPECLK, posedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID);
$setuphold (posedge PIPECLK, posedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID);
$setuphold (posedge PIPECLK, posedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL);
$setuphold (posedge PIPECLK, posedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE);
$setuphold (posedge PIPECLK, posedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN);
$setuphold (posedge PIPECLK, posedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST);
$setuphold (posedge PIPECLK, posedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]);
$setuphold (posedge USERCLK2, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]);
$setuphold (posedge USERCLK2, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]);
$setuphold (posedge USERCLK2, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]);
$setuphold (posedge USERCLK2, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]);
$setuphold (posedge USERCLK2, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]);
$setuphold (posedge USERCLK2, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]);
$setuphold (posedge USERCLK2, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]);
$setuphold (posedge USERCLK2, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]);
$setuphold (posedge USERCLK2, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]);
$setuphold (posedge USERCLK2, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]);
$setuphold (posedge USERCLK2, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]);
$setuphold (posedge USERCLK2, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]);
$setuphold (posedge USERCLK2, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]);
$setuphold (posedge USERCLK2, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]);
$setuphold (posedge USERCLK2, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]);
$setuphold (posedge USERCLK2, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]);
$setuphold (posedge USERCLK2, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]);
$setuphold (posedge USERCLK2, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]);
$setuphold (posedge USERCLK2, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]);
$setuphold (posedge USERCLK2, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]);
$setuphold (posedge USERCLK2, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]);
$setuphold (posedge USERCLK2, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]);
$setuphold (posedge USERCLK2, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]);
$setuphold (posedge USERCLK2, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]);
$setuphold (posedge USERCLK2, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]);
$setuphold (posedge USERCLK2, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]);
$setuphold (posedge USERCLK2, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]);
$setuphold (posedge USERCLK2, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]);
$setuphold (posedge USERCLK2, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]);
$setuphold (posedge USERCLK2, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]);
$setuphold (posedge USERCLK2, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]);
$setuphold (posedge USERCLK2, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]);
$setuphold (posedge USERCLK2, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]);
$setuphold (posedge USERCLK2, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]);
$setuphold (posedge USERCLK2, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]);
$setuphold (posedge USERCLK2, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]);
$setuphold (posedge USERCLK2, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]);
$setuphold (posedge USERCLK2, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]);
$setuphold (posedge USERCLK2, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]);
$setuphold (posedge USERCLK2, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]);
$setuphold (posedge USERCLK2, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]);
$setuphold (posedge USERCLK2, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]);
$setuphold (posedge USERCLK2, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]);
$setuphold (posedge USERCLK2, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]);
$setuphold (posedge USERCLK2, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]);
$setuphold (posedge USERCLK2, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]);
$setuphold (posedge USERCLK2, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]);
$setuphold (posedge USERCLK2, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]);
$setuphold (posedge USERCLK2, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]);
$setuphold (posedge USERCLK2, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]);
$setuphold (posedge USERCLK2, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]);
$setuphold (posedge USERCLK2, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]);
$setuphold (posedge USERCLK2, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]);
$setuphold (posedge USERCLK2, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]);
$setuphold (posedge USERCLK2, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]);
$setuphold (posedge USERCLK2, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]);
$setuphold (posedge USERCLK2, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]);
$setuphold (posedge USERCLK2, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]);
$setuphold (posedge USERCLK2, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]);
$setuphold (posedge USERCLK2, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]);
$setuphold (posedge USERCLK2, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]);
$setuphold (posedge USERCLK2, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]);
$setuphold (posedge USERCLK2, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]);
$setuphold (posedge USERCLK2, negedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]);
$setuphold (posedge USERCLK2, negedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN);
$setuphold (posedge USERCLK2, negedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN);
$setuphold (posedge USERCLK2, negedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN);
$setuphold (posedge USERCLK2, negedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN);
$setuphold (posedge USERCLK2, negedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN);
$setuphold (posedge USERCLK2, negedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN);
$setuphold (posedge USERCLK2, negedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN);
$setuphold (posedge USERCLK2, negedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]);
$setuphold (posedge USERCLK2, negedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN);
$setuphold (posedge USERCLK2, negedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF);
$setuphold (posedge USERCLK2, negedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]);
$setuphold (posedge USERCLK2, negedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]);
$setuphold (posedge USERCLK2, negedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN);
$setuphold (posedge USERCLK2, negedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N);
$setuphold (posedge USERCLK2, negedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON);
$setuphold (posedge USERCLK2, negedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN);
$setuphold (posedge USERCLK2, negedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]);
$setuphold (posedge USERCLK2, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]);
$setuphold (posedge USERCLK2, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]);
$setuphold (posedge USERCLK2, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]);
$setuphold (posedge USERCLK2, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]);
$setuphold (posedge USERCLK2, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]);
$setuphold (posedge USERCLK2, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]);
$setuphold (posedge USERCLK2, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]);
$setuphold (posedge USERCLK2, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK2, negedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN);
$setuphold (posedge USERCLK2, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK2, negedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN);
$setuphold (posedge USERCLK2, negedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN);
$setuphold (posedge USERCLK2, negedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]);
$setuphold (posedge USERCLK2, negedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]);
$setuphold (posedge USERCLK2, negedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE);
$setuphold (posedge USERCLK2, negedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN);
$setuphold (posedge USERCLK2, negedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN);
$setuphold (posedge USERCLK2, negedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1);
$setuphold (posedge USERCLK2, negedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1);
$setuphold (posedge USERCLK2, negedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23);
$setuphold (posedge USERCLK2, negedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK);
$setuphold (posedge USERCLK2, negedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW);
$setuphold (posedge USERCLK2, negedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]);
$setuphold (posedge USERCLK2, negedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK);
$setuphold (posedge USERCLK2, negedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ);
$setuphold (posedge USERCLK2, negedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]);
$setuphold (posedge USERCLK2, negedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY);
$setuphold (posedge USERCLK2, negedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET);
$setuphold (posedge USERCLK2, negedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK);
$setuphold (posedge USERCLK2, negedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ);
$setuphold (posedge USERCLK2, negedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY);
$setuphold (posedge USERCLK2, negedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]);
$setuphold (posedge USERCLK2, negedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]);
$setuphold (posedge USERCLK2, negedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]);
$setuphold (posedge USERCLK2, negedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]);
$setuphold (posedge USERCLK2, negedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]);
$setuphold (posedge USERCLK2, negedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]);
$setuphold (posedge USERCLK2, negedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]);
$setuphold (posedge USERCLK2, negedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]);
$setuphold (posedge USERCLK2, negedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]);
$setuphold (posedge USERCLK2, negedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]);
$setuphold (posedge USERCLK2, negedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]);
$setuphold (posedge USERCLK2, negedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]);
$setuphold (posedge USERCLK2, negedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]);
$setuphold (posedge USERCLK2, negedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]);
$setuphold (posedge USERCLK2, negedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]);
$setuphold (posedge USERCLK2, negedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]);
$setuphold (posedge USERCLK2, negedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]);
$setuphold (posedge USERCLK2, negedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]);
$setuphold (posedge USERCLK2, negedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]);
$setuphold (posedge USERCLK2, negedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]);
$setuphold (posedge USERCLK2, negedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]);
$setuphold (posedge USERCLK2, negedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]);
$setuphold (posedge USERCLK2, negedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]);
$setuphold (posedge USERCLK2, negedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]);
$setuphold (posedge USERCLK2, negedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]);
$setuphold (posedge USERCLK2, negedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]);
$setuphold (posedge USERCLK2, negedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]);
$setuphold (posedge USERCLK2, negedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]);
$setuphold (posedge USERCLK2, negedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]);
$setuphold (posedge USERCLK2, negedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]);
$setuphold (posedge USERCLK2, negedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]);
$setuphold (posedge USERCLK2, negedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]);
$setuphold (posedge USERCLK2, negedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]);
$setuphold (posedge USERCLK2, negedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]);
$setuphold (posedge USERCLK2, negedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]);
$setuphold (posedge USERCLK2, negedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]);
$setuphold (posedge USERCLK2, negedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]);
$setuphold (posedge USERCLK2, negedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]);
$setuphold (posedge USERCLK2, negedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]);
$setuphold (posedge USERCLK2, negedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]);
$setuphold (posedge USERCLK2, negedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]);
$setuphold (posedge USERCLK2, negedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]);
$setuphold (posedge USERCLK2, negedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]);
$setuphold (posedge USERCLK2, negedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]);
$setuphold (posedge USERCLK2, negedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]);
$setuphold (posedge USERCLK2, negedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]);
$setuphold (posedge USERCLK2, negedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]);
$setuphold (posedge USERCLK2, negedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]);
$setuphold (posedge USERCLK2, negedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]);
$setuphold (posedge USERCLK2, negedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]);
$setuphold (posedge USERCLK2, negedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]);
$setuphold (posedge USERCLK2, negedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]);
$setuphold (posedge USERCLK2, negedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]);
$setuphold (posedge USERCLK2, negedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]);
$setuphold (posedge USERCLK2, negedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]);
$setuphold (posedge USERCLK2, negedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]);
$setuphold (posedge USERCLK2, negedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]);
$setuphold (posedge USERCLK2, negedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]);
$setuphold (posedge USERCLK2, negedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]);
$setuphold (posedge USERCLK2, negedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]);
$setuphold (posedge USERCLK2, negedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]);
$setuphold (posedge USERCLK2, negedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]);
$setuphold (posedge USERCLK2, negedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]);
$setuphold (posedge USERCLK2, negedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]);
$setuphold (posedge USERCLK2, negedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]);
$setuphold (posedge USERCLK2, negedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]);
$setuphold (posedge USERCLK2, negedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]);
$setuphold (posedge USERCLK2, negedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]);
$setuphold (posedge USERCLK2, negedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]);
$setuphold (posedge USERCLK2, negedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]);
$setuphold (posedge USERCLK2, negedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]);
$setuphold (posedge USERCLK2, negedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]);
$setuphold (posedge USERCLK2, negedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]);
$setuphold (posedge USERCLK2, negedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]);
$setuphold (posedge USERCLK2, negedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]);
$setuphold (posedge USERCLK2, negedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]);
$setuphold (posedge USERCLK2, negedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]);
$setuphold (posedge USERCLK2, negedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]);
$setuphold (posedge USERCLK2, negedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]);
$setuphold (posedge USERCLK2, negedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]);
$setuphold (posedge USERCLK2, negedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]);
$setuphold (posedge USERCLK2, negedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]);
$setuphold (posedge USERCLK2, negedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]);
$setuphold (posedge USERCLK2, negedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]);
$setuphold (posedge USERCLK2, negedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]);
$setuphold (posedge USERCLK2, negedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]);
$setuphold (posedge USERCLK2, negedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]);
$setuphold (posedge USERCLK2, negedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]);
$setuphold (posedge USERCLK2, negedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]);
$setuphold (posedge USERCLK2, negedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]);
$setuphold (posedge USERCLK2, negedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]);
$setuphold (posedge USERCLK2, negedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]);
$setuphold (posedge USERCLK2, negedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]);
$setuphold (posedge USERCLK2, negedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]);
$setuphold (posedge USERCLK2, negedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]);
$setuphold (posedge USERCLK2, negedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]);
$setuphold (posedge USERCLK2, negedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]);
$setuphold (posedge USERCLK2, negedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]);
$setuphold (posedge USERCLK2, negedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]);
$setuphold (posedge USERCLK2, negedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]);
$setuphold (posedge USERCLK2, negedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]);
$setuphold (posedge USERCLK2, negedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]);
$setuphold (posedge USERCLK2, negedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]);
$setuphold (posedge USERCLK2, negedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]);
$setuphold (posedge USERCLK2, negedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]);
$setuphold (posedge USERCLK2, negedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]);
$setuphold (posedge USERCLK2, negedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]);
$setuphold (posedge USERCLK2, negedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]);
$setuphold (posedge USERCLK2, negedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]);
$setuphold (posedge USERCLK2, negedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]);
$setuphold (posedge USERCLK2, negedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]);
$setuphold (posedge USERCLK2, negedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]);
$setuphold (posedge USERCLK2, negedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]);
$setuphold (posedge USERCLK2, negedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]);
$setuphold (posedge USERCLK2, negedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]);
$setuphold (posedge USERCLK2, negedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]);
$setuphold (posedge USERCLK2, negedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]);
$setuphold (posedge USERCLK2, negedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]);
$setuphold (posedge USERCLK2, negedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]);
$setuphold (posedge USERCLK2, negedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]);
$setuphold (posedge USERCLK2, negedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]);
$setuphold (posedge USERCLK2, negedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]);
$setuphold (posedge USERCLK2, negedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]);
$setuphold (posedge USERCLK2, negedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]);
$setuphold (posedge USERCLK2, negedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]);
$setuphold (posedge USERCLK2, negedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]);
$setuphold (posedge USERCLK2, negedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]);
$setuphold (posedge USERCLK2, negedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]);
$setuphold (posedge USERCLK2, negedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN);
$setuphold (posedge USERCLK2, negedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF);
$setuphold (posedge USERCLK2, negedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD);
$setuphold (posedge USERCLK2, negedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]);
$setuphold (posedge USERCLK2, negedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]);
$setuphold (posedge USERCLK2, negedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF);
$setuphold (posedge USERCLK2, negedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC);
$setuphold (posedge USERCLK2, negedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY);
$setuphold (posedge USERCLK2, negedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]);
$setuphold (posedge USERCLK2, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]);
$setuphold (posedge USERCLK2, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]);
$setuphold (posedge USERCLK2, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]);
$setuphold (posedge USERCLK2, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]);
$setuphold (posedge USERCLK2, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]);
$setuphold (posedge USERCLK2, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]);
$setuphold (posedge USERCLK2, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]);
$setuphold (posedge USERCLK2, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]);
$setuphold (posedge USERCLK2, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]);
$setuphold (posedge USERCLK2, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]);
$setuphold (posedge USERCLK2, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]);
$setuphold (posedge USERCLK2, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]);
$setuphold (posedge USERCLK2, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]);
$setuphold (posedge USERCLK2, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]);
$setuphold (posedge USERCLK2, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]);
$setuphold (posedge USERCLK2, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]);
$setuphold (posedge USERCLK2, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]);
$setuphold (posedge USERCLK2, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]);
$setuphold (posedge USERCLK2, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]);
$setuphold (posedge USERCLK2, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]);
$setuphold (posedge USERCLK2, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]);
$setuphold (posedge USERCLK2, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]);
$setuphold (posedge USERCLK2, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]);
$setuphold (posedge USERCLK2, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]);
$setuphold (posedge USERCLK2, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]);
$setuphold (posedge USERCLK2, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]);
$setuphold (posedge USERCLK2, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]);
$setuphold (posedge USERCLK2, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]);
$setuphold (posedge USERCLK2, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]);
$setuphold (posedge USERCLK2, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]);
$setuphold (posedge USERCLK2, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]);
$setuphold (posedge USERCLK2, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]);
$setuphold (posedge USERCLK2, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]);
$setuphold (posedge USERCLK2, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]);
$setuphold (posedge USERCLK2, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]);
$setuphold (posedge USERCLK2, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]);
$setuphold (posedge USERCLK2, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]);
$setuphold (posedge USERCLK2, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]);
$setuphold (posedge USERCLK2, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]);
$setuphold (posedge USERCLK2, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]);
$setuphold (posedge USERCLK2, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]);
$setuphold (posedge USERCLK2, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]);
$setuphold (posedge USERCLK2, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]);
$setuphold (posedge USERCLK2, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]);
$setuphold (posedge USERCLK2, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]);
$setuphold (posedge USERCLK2, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]);
$setuphold (posedge USERCLK2, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]);
$setuphold (posedge USERCLK2, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]);
$setuphold (posedge USERCLK2, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]);
$setuphold (posedge USERCLK2, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]);
$setuphold (posedge USERCLK2, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]);
$setuphold (posedge USERCLK2, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]);
$setuphold (posedge USERCLK2, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]);
$setuphold (posedge USERCLK2, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]);
$setuphold (posedge USERCLK2, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]);
$setuphold (posedge USERCLK2, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]);
$setuphold (posedge USERCLK2, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]);
$setuphold (posedge USERCLK2, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]);
$setuphold (posedge USERCLK2, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]);
$setuphold (posedge USERCLK2, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]);
$setuphold (posedge USERCLK2, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]);
$setuphold (posedge USERCLK2, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]);
$setuphold (posedge USERCLK2, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]);
$setuphold (posedge USERCLK2, posedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]);
$setuphold (posedge USERCLK2, posedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN);
$setuphold (posedge USERCLK2, posedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN);
$setuphold (posedge USERCLK2, posedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN);
$setuphold (posedge USERCLK2, posedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN);
$setuphold (posedge USERCLK2, posedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN);
$setuphold (posedge USERCLK2, posedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN);
$setuphold (posedge USERCLK2, posedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN);
$setuphold (posedge USERCLK2, posedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]);
$setuphold (posedge USERCLK2, posedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN);
$setuphold (posedge USERCLK2, posedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF);
$setuphold (posedge USERCLK2, posedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]);
$setuphold (posedge USERCLK2, posedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]);
$setuphold (posedge USERCLK2, posedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN);
$setuphold (posedge USERCLK2, posedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N);
$setuphold (posedge USERCLK2, posedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON);
$setuphold (posedge USERCLK2, posedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN);
$setuphold (posedge USERCLK2, posedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]);
$setuphold (posedge USERCLK2, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]);
$setuphold (posedge USERCLK2, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]);
$setuphold (posedge USERCLK2, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]);
$setuphold (posedge USERCLK2, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]);
$setuphold (posedge USERCLK2, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]);
$setuphold (posedge USERCLK2, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]);
$setuphold (posedge USERCLK2, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]);
$setuphold (posedge USERCLK2, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK2, posedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN);
$setuphold (posedge USERCLK2, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK2, posedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN);
$setuphold (posedge USERCLK2, posedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN);
$setuphold (posedge USERCLK2, posedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]);
$setuphold (posedge USERCLK2, posedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]);
$setuphold (posedge USERCLK2, posedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE);
$setuphold (posedge USERCLK2, posedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN);
$setuphold (posedge USERCLK2, posedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN);
$setuphold (posedge USERCLK2, posedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1);
$setuphold (posedge USERCLK2, posedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1);
$setuphold (posedge USERCLK2, posedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23);
$setuphold (posedge USERCLK2, posedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK);
$setuphold (posedge USERCLK2, posedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW);
$setuphold (posedge USERCLK2, posedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]);
$setuphold (posedge USERCLK2, posedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK);
$setuphold (posedge USERCLK2, posedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ);
$setuphold (posedge USERCLK2, posedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]);
$setuphold (posedge USERCLK2, posedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY);
$setuphold (posedge USERCLK2, posedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET);
$setuphold (posedge USERCLK2, posedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK);
$setuphold (posedge USERCLK2, posedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ);
$setuphold (posedge USERCLK2, posedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY);
$setuphold (posedge USERCLK2, posedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]);
$setuphold (posedge USERCLK2, posedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]);
$setuphold (posedge USERCLK2, posedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]);
$setuphold (posedge USERCLK2, posedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]);
$setuphold (posedge USERCLK2, posedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]);
$setuphold (posedge USERCLK2, posedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]);
$setuphold (posedge USERCLK2, posedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]);
$setuphold (posedge USERCLK2, posedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]);
$setuphold (posedge USERCLK2, posedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]);
$setuphold (posedge USERCLK2, posedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]);
$setuphold (posedge USERCLK2, posedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]);
$setuphold (posedge USERCLK2, posedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]);
$setuphold (posedge USERCLK2, posedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]);
$setuphold (posedge USERCLK2, posedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]);
$setuphold (posedge USERCLK2, posedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]);
$setuphold (posedge USERCLK2, posedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]);
$setuphold (posedge USERCLK2, posedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]);
$setuphold (posedge USERCLK2, posedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]);
$setuphold (posedge USERCLK2, posedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]);
$setuphold (posedge USERCLK2, posedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]);
$setuphold (posedge USERCLK2, posedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]);
$setuphold (posedge USERCLK2, posedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]);
$setuphold (posedge USERCLK2, posedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]);
$setuphold (posedge USERCLK2, posedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]);
$setuphold (posedge USERCLK2, posedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]);
$setuphold (posedge USERCLK2, posedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]);
$setuphold (posedge USERCLK2, posedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]);
$setuphold (posedge USERCLK2, posedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]);
$setuphold (posedge USERCLK2, posedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]);
$setuphold (posedge USERCLK2, posedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]);
$setuphold (posedge USERCLK2, posedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]);
$setuphold (posedge USERCLK2, posedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]);
$setuphold (posedge USERCLK2, posedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]);
$setuphold (posedge USERCLK2, posedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]);
$setuphold (posedge USERCLK2, posedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]);
$setuphold (posedge USERCLK2, posedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]);
$setuphold (posedge USERCLK2, posedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]);
$setuphold (posedge USERCLK2, posedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]);
$setuphold (posedge USERCLK2, posedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]);
$setuphold (posedge USERCLK2, posedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]);
$setuphold (posedge USERCLK2, posedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]);
$setuphold (posedge USERCLK2, posedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]);
$setuphold (posedge USERCLK2, posedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]);
$setuphold (posedge USERCLK2, posedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]);
$setuphold (posedge USERCLK2, posedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]);
$setuphold (posedge USERCLK2, posedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]);
$setuphold (posedge USERCLK2, posedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]);
$setuphold (posedge USERCLK2, posedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]);
$setuphold (posedge USERCLK2, posedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]);
$setuphold (posedge USERCLK2, posedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]);
$setuphold (posedge USERCLK2, posedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]);
$setuphold (posedge USERCLK2, posedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]);
$setuphold (posedge USERCLK2, posedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]);
$setuphold (posedge USERCLK2, posedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]);
$setuphold (posedge USERCLK2, posedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]);
$setuphold (posedge USERCLK2, posedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]);
$setuphold (posedge USERCLK2, posedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]);
$setuphold (posedge USERCLK2, posedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]);
$setuphold (posedge USERCLK2, posedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]);
$setuphold (posedge USERCLK2, posedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]);
$setuphold (posedge USERCLK2, posedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]);
$setuphold (posedge USERCLK2, posedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]);
$setuphold (posedge USERCLK2, posedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]);
$setuphold (posedge USERCLK2, posedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]);
$setuphold (posedge USERCLK2, posedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]);
$setuphold (posedge USERCLK2, posedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]);
$setuphold (posedge USERCLK2, posedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]);
$setuphold (posedge USERCLK2, posedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]);
$setuphold (posedge USERCLK2, posedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]);
$setuphold (posedge USERCLK2, posedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]);
$setuphold (posedge USERCLK2, posedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]);
$setuphold (posedge USERCLK2, posedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]);
$setuphold (posedge USERCLK2, posedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]);
$setuphold (posedge USERCLK2, posedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]);
$setuphold (posedge USERCLK2, posedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]);
$setuphold (posedge USERCLK2, posedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]);
$setuphold (posedge USERCLK2, posedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]);
$setuphold (posedge USERCLK2, posedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]);
$setuphold (posedge USERCLK2, posedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]);
$setuphold (posedge USERCLK2, posedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]);
$setuphold (posedge USERCLK2, posedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]);
$setuphold (posedge USERCLK2, posedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]);
$setuphold (posedge USERCLK2, posedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]);
$setuphold (posedge USERCLK2, posedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]);
$setuphold (posedge USERCLK2, posedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]);
$setuphold (posedge USERCLK2, posedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]);
$setuphold (posedge USERCLK2, posedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]);
$setuphold (posedge USERCLK2, posedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]);
$setuphold (posedge USERCLK2, posedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]);
$setuphold (posedge USERCLK2, posedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]);
$setuphold (posedge USERCLK2, posedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]);
$setuphold (posedge USERCLK2, posedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]);
$setuphold (posedge USERCLK2, posedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]);
$setuphold (posedge USERCLK2, posedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]);
$setuphold (posedge USERCLK2, posedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]);
$setuphold (posedge USERCLK2, posedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]);
$setuphold (posedge USERCLK2, posedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]);
$setuphold (posedge USERCLK2, posedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]);
$setuphold (posedge USERCLK2, posedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]);
$setuphold (posedge USERCLK2, posedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]);
$setuphold (posedge USERCLK2, posedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]);
$setuphold (posedge USERCLK2, posedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]);
$setuphold (posedge USERCLK2, posedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]);
$setuphold (posedge USERCLK2, posedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]);
$setuphold (posedge USERCLK2, posedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]);
$setuphold (posedge USERCLK2, posedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]);
$setuphold (posedge USERCLK2, posedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]);
$setuphold (posedge USERCLK2, posedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]);
$setuphold (posedge USERCLK2, posedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]);
$setuphold (posedge USERCLK2, posedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]);
$setuphold (posedge USERCLK2, posedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]);
$setuphold (posedge USERCLK2, posedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]);
$setuphold (posedge USERCLK2, posedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]);
$setuphold (posedge USERCLK2, posedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]);
$setuphold (posedge USERCLK2, posedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]);
$setuphold (posedge USERCLK2, posedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]);
$setuphold (posedge USERCLK2, posedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]);
$setuphold (posedge USERCLK2, posedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]);
$setuphold (posedge USERCLK2, posedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]);
$setuphold (posedge USERCLK2, posedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]);
$setuphold (posedge USERCLK2, posedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]);
$setuphold (posedge USERCLK2, posedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]);
$setuphold (posedge USERCLK2, posedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]);
$setuphold (posedge USERCLK2, posedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]);
$setuphold (posedge USERCLK2, posedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]);
$setuphold (posedge USERCLK2, posedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]);
$setuphold (posedge USERCLK2, posedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]);
$setuphold (posedge USERCLK2, posedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]);
$setuphold (posedge USERCLK2, posedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN);
$setuphold (posedge USERCLK2, posedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF);
$setuphold (posedge USERCLK2, posedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD);
$setuphold (posedge USERCLK2, posedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]);
$setuphold (posedge USERCLK2, posedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]);
$setuphold (posedge USERCLK2, posedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF);
$setuphold (posedge USERCLK2, posedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC);
$setuphold (posedge USERCLK2, posedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY);
$setuphold (posedge USERCLK2, posedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR);
`endif
( DRPCLK *> DRPDO[0]) = (0, 0);
( DRPCLK *> DRPDO[10]) = (0, 0);
( DRPCLK *> DRPDO[11]) = (0, 0);
( DRPCLK *> DRPDO[12]) = (0, 0);
( DRPCLK *> DRPDO[13]) = (0, 0);
( DRPCLK *> DRPDO[14]) = (0, 0);
( DRPCLK *> DRPDO[15]) = (0, 0);
( DRPCLK *> DRPDO[1]) = (0, 0);
( DRPCLK *> DRPDO[2]) = (0, 0);
( DRPCLK *> DRPDO[3]) = (0, 0);
( DRPCLK *> DRPDO[4]) = (0, 0);
( DRPCLK *> DRPDO[5]) = (0, 0);
( DRPCLK *> DRPDO[6]) = (0, 0);
( DRPCLK *> DRPDO[7]) = (0, 0);
( DRPCLK *> DRPDO[8]) = (0, 0);
( DRPCLK *> DRPDO[9]) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( PIPECLK *> PIPERX0POLARITY) = (0, 0);
( PIPECLK *> PIPERX1POLARITY) = (0, 0);
( PIPECLK *> PIPERX2POLARITY) = (0, 0);
( PIPECLK *> PIPERX3POLARITY) = (0, 0);
( PIPECLK *> PIPERX4POLARITY) = (0, 0);
( PIPECLK *> PIPERX5POLARITY) = (0, 0);
( PIPECLK *> PIPERX6POLARITY) = (0, 0);
( PIPECLK *> PIPERX7POLARITY) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX0DATA[0]) = (0, 0);
( PIPECLK *> PIPETX0DATA[10]) = (0, 0);
( PIPECLK *> PIPETX0DATA[11]) = (0, 0);
( PIPECLK *> PIPETX0DATA[12]) = (0, 0);
( PIPECLK *> PIPETX0DATA[13]) = (0, 0);
( PIPECLK *> PIPETX0DATA[14]) = (0, 0);
( PIPECLK *> PIPETX0DATA[15]) = (0, 0);
( PIPECLK *> PIPETX0DATA[1]) = (0, 0);
( PIPECLK *> PIPETX0DATA[2]) = (0, 0);
( PIPECLK *> PIPETX0DATA[3]) = (0, 0);
( PIPECLK *> PIPETX0DATA[4]) = (0, 0);
( PIPECLK *> PIPETX0DATA[5]) = (0, 0);
( PIPECLK *> PIPETX0DATA[6]) = (0, 0);
( PIPECLK *> PIPETX0DATA[7]) = (0, 0);
( PIPECLK *> PIPETX0DATA[8]) = (0, 0);
( PIPECLK *> PIPETX0DATA[9]) = (0, 0);
( PIPECLK *> PIPETX0ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX1DATA[0]) = (0, 0);
( PIPECLK *> PIPETX1DATA[10]) = (0, 0);
( PIPECLK *> PIPETX1DATA[11]) = (0, 0);
( PIPECLK *> PIPETX1DATA[12]) = (0, 0);
( PIPECLK *> PIPETX1DATA[13]) = (0, 0);
( PIPECLK *> PIPETX1DATA[14]) = (0, 0);
( PIPECLK *> PIPETX1DATA[15]) = (0, 0);
( PIPECLK *> PIPETX1DATA[1]) = (0, 0);
( PIPECLK *> PIPETX1DATA[2]) = (0, 0);
( PIPECLK *> PIPETX1DATA[3]) = (0, 0);
( PIPECLK *> PIPETX1DATA[4]) = (0, 0);
( PIPECLK *> PIPETX1DATA[5]) = (0, 0);
( PIPECLK *> PIPETX1DATA[6]) = (0, 0);
( PIPECLK *> PIPETX1DATA[7]) = (0, 0);
( PIPECLK *> PIPETX1DATA[8]) = (0, 0);
( PIPECLK *> PIPETX1DATA[9]) = (0, 0);
( PIPECLK *> PIPETX1ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX2DATA[0]) = (0, 0);
( PIPECLK *> PIPETX2DATA[10]) = (0, 0);
( PIPECLK *> PIPETX2DATA[11]) = (0, 0);
( PIPECLK *> PIPETX2DATA[12]) = (0, 0);
( PIPECLK *> PIPETX2DATA[13]) = (0, 0);
( PIPECLK *> PIPETX2DATA[14]) = (0, 0);
( PIPECLK *> PIPETX2DATA[15]) = (0, 0);
( PIPECLK *> PIPETX2DATA[1]) = (0, 0);
( PIPECLK *> PIPETX2DATA[2]) = (0, 0);
( PIPECLK *> PIPETX2DATA[3]) = (0, 0);
( PIPECLK *> PIPETX2DATA[4]) = (0, 0);
( PIPECLK *> PIPETX2DATA[5]) = (0, 0);
( PIPECLK *> PIPETX2DATA[6]) = (0, 0);
( PIPECLK *> PIPETX2DATA[7]) = (0, 0);
( PIPECLK *> PIPETX2DATA[8]) = (0, 0);
( PIPECLK *> PIPETX2DATA[9]) = (0, 0);
( PIPECLK *> PIPETX2ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX3DATA[0]) = (0, 0);
( PIPECLK *> PIPETX3DATA[10]) = (0, 0);
( PIPECLK *> PIPETX3DATA[11]) = (0, 0);
( PIPECLK *> PIPETX3DATA[12]) = (0, 0);
( PIPECLK *> PIPETX3DATA[13]) = (0, 0);
( PIPECLK *> PIPETX3DATA[14]) = (0, 0);
( PIPECLK *> PIPETX3DATA[15]) = (0, 0);
( PIPECLK *> PIPETX3DATA[1]) = (0, 0);
( PIPECLK *> PIPETX3DATA[2]) = (0, 0);
( PIPECLK *> PIPETX3DATA[3]) = (0, 0);
( PIPECLK *> PIPETX3DATA[4]) = (0, 0);
( PIPECLK *> PIPETX3DATA[5]) = (0, 0);
( PIPECLK *> PIPETX3DATA[6]) = (0, 0);
( PIPECLK *> PIPETX3DATA[7]) = (0, 0);
( PIPECLK *> PIPETX3DATA[8]) = (0, 0);
( PIPECLK *> PIPETX3DATA[9]) = (0, 0);
( PIPECLK *> PIPETX3ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX4DATA[0]) = (0, 0);
( PIPECLK *> PIPETX4DATA[10]) = (0, 0);
( PIPECLK *> PIPETX4DATA[11]) = (0, 0);
( PIPECLK *> PIPETX4DATA[12]) = (0, 0);
( PIPECLK *> PIPETX4DATA[13]) = (0, 0);
( PIPECLK *> PIPETX4DATA[14]) = (0, 0);
( PIPECLK *> PIPETX4DATA[15]) = (0, 0);
( PIPECLK *> PIPETX4DATA[1]) = (0, 0);
( PIPECLK *> PIPETX4DATA[2]) = (0, 0);
( PIPECLK *> PIPETX4DATA[3]) = (0, 0);
( PIPECLK *> PIPETX4DATA[4]) = (0, 0);
( PIPECLK *> PIPETX4DATA[5]) = (0, 0);
( PIPECLK *> PIPETX4DATA[6]) = (0, 0);
( PIPECLK *> PIPETX4DATA[7]) = (0, 0);
( PIPECLK *> PIPETX4DATA[8]) = (0, 0);
( PIPECLK *> PIPETX4DATA[9]) = (0, 0);
( PIPECLK *> PIPETX4ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX5DATA[0]) = (0, 0);
( PIPECLK *> PIPETX5DATA[10]) = (0, 0);
( PIPECLK *> PIPETX5DATA[11]) = (0, 0);
( PIPECLK *> PIPETX5DATA[12]) = (0, 0);
( PIPECLK *> PIPETX5DATA[13]) = (0, 0);
( PIPECLK *> PIPETX5DATA[14]) = (0, 0);
( PIPECLK *> PIPETX5DATA[15]) = (0, 0);
( PIPECLK *> PIPETX5DATA[1]) = (0, 0);
( PIPECLK *> PIPETX5DATA[2]) = (0, 0);
( PIPECLK *> PIPETX5DATA[3]) = (0, 0);
( PIPECLK *> PIPETX5DATA[4]) = (0, 0);
( PIPECLK *> PIPETX5DATA[5]) = (0, 0);
( PIPECLK *> PIPETX5DATA[6]) = (0, 0);
( PIPECLK *> PIPETX5DATA[7]) = (0, 0);
( PIPECLK *> PIPETX5DATA[8]) = (0, 0);
( PIPECLK *> PIPETX5DATA[9]) = (0, 0);
( PIPECLK *> PIPETX5ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX6DATA[0]) = (0, 0);
( PIPECLK *> PIPETX6DATA[10]) = (0, 0);
( PIPECLK *> PIPETX6DATA[11]) = (0, 0);
( PIPECLK *> PIPETX6DATA[12]) = (0, 0);
( PIPECLK *> PIPETX6DATA[13]) = (0, 0);
( PIPECLK *> PIPETX6DATA[14]) = (0, 0);
( PIPECLK *> PIPETX6DATA[15]) = (0, 0);
( PIPECLK *> PIPETX6DATA[1]) = (0, 0);
( PIPECLK *> PIPETX6DATA[2]) = (0, 0);
( PIPECLK *> PIPETX6DATA[3]) = (0, 0);
( PIPECLK *> PIPETX6DATA[4]) = (0, 0);
( PIPECLK *> PIPETX6DATA[5]) = (0, 0);
( PIPECLK *> PIPETX6DATA[6]) = (0, 0);
( PIPECLK *> PIPETX6DATA[7]) = (0, 0);
( PIPECLK *> PIPETX6DATA[8]) = (0, 0);
( PIPECLK *> PIPETX6DATA[9]) = (0, 0);
( PIPECLK *> PIPETX6ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX7DATA[0]) = (0, 0);
( PIPECLK *> PIPETX7DATA[10]) = (0, 0);
( PIPECLK *> PIPETX7DATA[11]) = (0, 0);
( PIPECLK *> PIPETX7DATA[12]) = (0, 0);
( PIPECLK *> PIPETX7DATA[13]) = (0, 0);
( PIPECLK *> PIPETX7DATA[14]) = (0, 0);
( PIPECLK *> PIPETX7DATA[15]) = (0, 0);
( PIPECLK *> PIPETX7DATA[1]) = (0, 0);
( PIPECLK *> PIPETX7DATA[2]) = (0, 0);
( PIPECLK *> PIPETX7DATA[3]) = (0, 0);
( PIPECLK *> PIPETX7DATA[4]) = (0, 0);
( PIPECLK *> PIPETX7DATA[5]) = (0, 0);
( PIPECLK *> PIPETX7DATA[6]) = (0, 0);
( PIPECLK *> PIPETX7DATA[7]) = (0, 0);
( PIPECLK *> PIPETX7DATA[8]) = (0, 0);
( PIPECLK *> PIPETX7DATA[9]) = (0, 0);
( PIPECLK *> PIPETX7ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETXDEEMPH) = (0, 0);
( PIPECLK *> PIPETXMARGIN[0]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[1]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[2]) = (0, 0);
( PIPECLK *> PIPETXRATE) = (0, 0);
( PIPECLK *> PIPETXRCVRDET) = (0, 0);
( PIPECLK *> PIPETXRESET) = (0, 0);
( PIPECLK *> PLDBGVEC[0]) = (0, 0);
( PIPECLK *> PLDBGVEC[10]) = (0, 0);
( PIPECLK *> PLDBGVEC[11]) = (0, 0);
( PIPECLK *> PLDBGVEC[1]) = (0, 0);
( PIPECLK *> PLDBGVEC[2]) = (0, 0);
( PIPECLK *> PLDBGVEC[3]) = (0, 0);
( PIPECLK *> PLDBGVEC[4]) = (0, 0);
( PIPECLK *> PLDBGVEC[5]) = (0, 0);
( PIPECLK *> PLDBGVEC[6]) = (0, 0);
( PIPECLK *> PLDBGVEC[7]) = (0, 0);
( PIPECLK *> PLDBGVEC[8]) = (0, 0);
( PIPECLK *> PLDBGVEC[9]) = (0, 0);
( PIPECLK *> PLDIRECTEDCHANGEDONE) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[0]) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[1]) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[2]) = (0, 0);
( PIPECLK *> PLLANEREVERSALMODE[0]) = (0, 0);
( PIPECLK *> PLLANEREVERSALMODE[1]) = (0, 0);
( PIPECLK *> PLLINKGEN2CAP) = (0, 0);
( PIPECLK *> PLLINKPARTNERGEN2SUPPORTED) = (0, 0);
( PIPECLK *> PLLINKUPCFGCAP) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[0]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[1]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[2]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[3]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[4]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[5]) = (0, 0);
( PIPECLK *> PLPHYLNKUPN) = (0, 0);
( PIPECLK *> PLRECEIVEDHOTRST) = (0, 0);
( PIPECLK *> PLRXPMSTATE[0]) = (0, 0);
( PIPECLK *> PLRXPMSTATE[1]) = (0, 0);
( PIPECLK *> PLSELLNKRATE) = (0, 0);
( PIPECLK *> PLSELLNKWIDTH[0]) = (0, 0);
( PIPECLK *> PLSELLNKWIDTH[1]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[0]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[1]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[2]) = (0, 0);
( USERCLK *> LNKCLKEN) = (0, 0);
( USERCLK *> MIMRXRADDR[0]) = (0, 0);
( USERCLK *> MIMRXRADDR[10]) = (0, 0);
( USERCLK *> MIMRXRADDR[11]) = (0, 0);
( USERCLK *> MIMRXRADDR[12]) = (0, 0);
( USERCLK *> MIMRXRADDR[1]) = (0, 0);
( USERCLK *> MIMRXRADDR[2]) = (0, 0);
( USERCLK *> MIMRXRADDR[3]) = (0, 0);
( USERCLK *> MIMRXRADDR[4]) = (0, 0);
( USERCLK *> MIMRXRADDR[5]) = (0, 0);
( USERCLK *> MIMRXRADDR[6]) = (0, 0);
( USERCLK *> MIMRXRADDR[7]) = (0, 0);
( USERCLK *> MIMRXRADDR[8]) = (0, 0);
( USERCLK *> MIMRXRADDR[9]) = (0, 0);
( USERCLK *> MIMRXREN) = (0, 0);
( USERCLK *> MIMRXWADDR[0]) = (0, 0);
( USERCLK *> MIMRXWADDR[10]) = (0, 0);
( USERCLK *> MIMRXWADDR[11]) = (0, 0);
( USERCLK *> MIMRXWADDR[12]) = (0, 0);
( USERCLK *> MIMRXWADDR[1]) = (0, 0);
( USERCLK *> MIMRXWADDR[2]) = (0, 0);
( USERCLK *> MIMRXWADDR[3]) = (0, 0);
( USERCLK *> MIMRXWADDR[4]) = (0, 0);
( USERCLK *> MIMRXWADDR[5]) = (0, 0);
( USERCLK *> MIMRXWADDR[6]) = (0, 0);
( USERCLK *> MIMRXWADDR[7]) = (0, 0);
( USERCLK *> MIMRXWADDR[8]) = (0, 0);
( USERCLK *> MIMRXWADDR[9]) = (0, 0);
( USERCLK *> MIMRXWDATA[0]) = (0, 0);
( USERCLK *> MIMRXWDATA[10]) = (0, 0);
( USERCLK *> MIMRXWDATA[11]) = (0, 0);
( USERCLK *> MIMRXWDATA[12]) = (0, 0);
( USERCLK *> MIMRXWDATA[13]) = (0, 0);
( USERCLK *> MIMRXWDATA[14]) = (0, 0);
( USERCLK *> MIMRXWDATA[15]) = (0, 0);
( USERCLK *> MIMRXWDATA[16]) = (0, 0);
( USERCLK *> MIMRXWDATA[17]) = (0, 0);
( USERCLK *> MIMRXWDATA[18]) = (0, 0);
( USERCLK *> MIMRXWDATA[19]) = (0, 0);
( USERCLK *> MIMRXWDATA[1]) = (0, 0);
( USERCLK *> MIMRXWDATA[20]) = (0, 0);
( USERCLK *> MIMRXWDATA[21]) = (0, 0);
( USERCLK *> MIMRXWDATA[22]) = (0, 0);
( USERCLK *> MIMRXWDATA[23]) = (0, 0);
( USERCLK *> MIMRXWDATA[24]) = (0, 0);
( USERCLK *> MIMRXWDATA[25]) = (0, 0);
( USERCLK *> MIMRXWDATA[26]) = (0, 0);
( USERCLK *> MIMRXWDATA[27]) = (0, 0);
( USERCLK *> MIMRXWDATA[28]) = (0, 0);
( USERCLK *> MIMRXWDATA[29]) = (0, 0);
( USERCLK *> MIMRXWDATA[2]) = (0, 0);
( USERCLK *> MIMRXWDATA[30]) = (0, 0);
( USERCLK *> MIMRXWDATA[31]) = (0, 0);
( USERCLK *> MIMRXWDATA[32]) = (0, 0);
( USERCLK *> MIMRXWDATA[33]) = (0, 0);
( USERCLK *> MIMRXWDATA[34]) = (0, 0);
( USERCLK *> MIMRXWDATA[35]) = (0, 0);
( USERCLK *> MIMRXWDATA[36]) = (0, 0);
( USERCLK *> MIMRXWDATA[37]) = (0, 0);
( USERCLK *> MIMRXWDATA[38]) = (0, 0);
( USERCLK *> MIMRXWDATA[39]) = (0, 0);
( USERCLK *> MIMRXWDATA[3]) = (0, 0);
( USERCLK *> MIMRXWDATA[40]) = (0, 0);
( USERCLK *> MIMRXWDATA[41]) = (0, 0);
( USERCLK *> MIMRXWDATA[42]) = (0, 0);
( USERCLK *> MIMRXWDATA[43]) = (0, 0);
( USERCLK *> MIMRXWDATA[44]) = (0, 0);
( USERCLK *> MIMRXWDATA[45]) = (0, 0);
( USERCLK *> MIMRXWDATA[46]) = (0, 0);
( USERCLK *> MIMRXWDATA[47]) = (0, 0);
( USERCLK *> MIMRXWDATA[48]) = (0, 0);
( USERCLK *> MIMRXWDATA[49]) = (0, 0);
( USERCLK *> MIMRXWDATA[4]) = (0, 0);
( USERCLK *> MIMRXWDATA[50]) = (0, 0);
( USERCLK *> MIMRXWDATA[51]) = (0, 0);
( USERCLK *> MIMRXWDATA[52]) = (0, 0);
( USERCLK *> MIMRXWDATA[53]) = (0, 0);
( USERCLK *> MIMRXWDATA[54]) = (0, 0);
( USERCLK *> MIMRXWDATA[55]) = (0, 0);
( USERCLK *> MIMRXWDATA[56]) = (0, 0);
( USERCLK *> MIMRXWDATA[57]) = (0, 0);
( USERCLK *> MIMRXWDATA[58]) = (0, 0);
( USERCLK *> MIMRXWDATA[59]) = (0, 0);
( USERCLK *> MIMRXWDATA[5]) = (0, 0);
( USERCLK *> MIMRXWDATA[60]) = (0, 0);
( USERCLK *> MIMRXWDATA[61]) = (0, 0);
( USERCLK *> MIMRXWDATA[62]) = (0, 0);
( USERCLK *> MIMRXWDATA[63]) = (0, 0);
( USERCLK *> MIMRXWDATA[64]) = (0, 0);
( USERCLK *> MIMRXWDATA[65]) = (0, 0);
( USERCLK *> MIMRXWDATA[66]) = (0, 0);
( USERCLK *> MIMRXWDATA[67]) = (0, 0);
( USERCLK *> MIMRXWDATA[6]) = (0, 0);
( USERCLK *> MIMRXWDATA[7]) = (0, 0);
( USERCLK *> MIMRXWDATA[8]) = (0, 0);
( USERCLK *> MIMRXWDATA[9]) = (0, 0);
( USERCLK *> MIMRXWEN) = (0, 0);
( USERCLK *> MIMTXRADDR[0]) = (0, 0);
( USERCLK *> MIMTXRADDR[10]) = (0, 0);
( USERCLK *> MIMTXRADDR[11]) = (0, 0);
( USERCLK *> MIMTXRADDR[12]) = (0, 0);
( USERCLK *> MIMTXRADDR[1]) = (0, 0);
( USERCLK *> MIMTXRADDR[2]) = (0, 0);
( USERCLK *> MIMTXRADDR[3]) = (0, 0);
( USERCLK *> MIMTXRADDR[4]) = (0, 0);
( USERCLK *> MIMTXRADDR[5]) = (0, 0);
( USERCLK *> MIMTXRADDR[6]) = (0, 0);
( USERCLK *> MIMTXRADDR[7]) = (0, 0);
( USERCLK *> MIMTXRADDR[8]) = (0, 0);
( USERCLK *> MIMTXRADDR[9]) = (0, 0);
( USERCLK *> MIMTXREN) = (0, 0);
( USERCLK *> MIMTXWADDR[0]) = (0, 0);
( USERCLK *> MIMTXWADDR[10]) = (0, 0);
( USERCLK *> MIMTXWADDR[11]) = (0, 0);
( USERCLK *> MIMTXWADDR[12]) = (0, 0);
( USERCLK *> MIMTXWADDR[1]) = (0, 0);
( USERCLK *> MIMTXWADDR[2]) = (0, 0);
( USERCLK *> MIMTXWADDR[3]) = (0, 0);
( USERCLK *> MIMTXWADDR[4]) = (0, 0);
( USERCLK *> MIMTXWADDR[5]) = (0, 0);
( USERCLK *> MIMTXWADDR[6]) = (0, 0);
( USERCLK *> MIMTXWADDR[7]) = (0, 0);
( USERCLK *> MIMTXWADDR[8]) = (0, 0);
( USERCLK *> MIMTXWADDR[9]) = (0, 0);
( USERCLK *> MIMTXWDATA[0]) = (0, 0);
( USERCLK *> MIMTXWDATA[10]) = (0, 0);
( USERCLK *> MIMTXWDATA[11]) = (0, 0);
( USERCLK *> MIMTXWDATA[12]) = (0, 0);
( USERCLK *> MIMTXWDATA[13]) = (0, 0);
( USERCLK *> MIMTXWDATA[14]) = (0, 0);
( USERCLK *> MIMTXWDATA[15]) = (0, 0);
( USERCLK *> MIMTXWDATA[16]) = (0, 0);
( USERCLK *> MIMTXWDATA[17]) = (0, 0);
( USERCLK *> MIMTXWDATA[18]) = (0, 0);
( USERCLK *> MIMTXWDATA[19]) = (0, 0);
( USERCLK *> MIMTXWDATA[1]) = (0, 0);
( USERCLK *> MIMTXWDATA[20]) = (0, 0);
( USERCLK *> MIMTXWDATA[21]) = (0, 0);
( USERCLK *> MIMTXWDATA[22]) = (0, 0);
( USERCLK *> MIMTXWDATA[23]) = (0, 0);
( USERCLK *> MIMTXWDATA[24]) = (0, 0);
( USERCLK *> MIMTXWDATA[25]) = (0, 0);
( USERCLK *> MIMTXWDATA[26]) = (0, 0);
( USERCLK *> MIMTXWDATA[27]) = (0, 0);
( USERCLK *> MIMTXWDATA[28]) = (0, 0);
( USERCLK *> MIMTXWDATA[29]) = (0, 0);
( USERCLK *> MIMTXWDATA[2]) = (0, 0);
( USERCLK *> MIMTXWDATA[30]) = (0, 0);
( USERCLK *> MIMTXWDATA[31]) = (0, 0);
( USERCLK *> MIMTXWDATA[32]) = (0, 0);
( USERCLK *> MIMTXWDATA[33]) = (0, 0);
( USERCLK *> MIMTXWDATA[34]) = (0, 0);
( USERCLK *> MIMTXWDATA[35]) = (0, 0);
( USERCLK *> MIMTXWDATA[36]) = (0, 0);
( USERCLK *> MIMTXWDATA[37]) = (0, 0);
( USERCLK *> MIMTXWDATA[38]) = (0, 0);
( USERCLK *> MIMTXWDATA[39]) = (0, 0);
( USERCLK *> MIMTXWDATA[3]) = (0, 0);
( USERCLK *> MIMTXWDATA[40]) = (0, 0);
( USERCLK *> MIMTXWDATA[41]) = (0, 0);
( USERCLK *> MIMTXWDATA[42]) = (0, 0);
( USERCLK *> MIMTXWDATA[43]) = (0, 0);
( USERCLK *> MIMTXWDATA[44]) = (0, 0);
( USERCLK *> MIMTXWDATA[45]) = (0, 0);
( USERCLK *> MIMTXWDATA[46]) = (0, 0);
( USERCLK *> MIMTXWDATA[47]) = (0, 0);
( USERCLK *> MIMTXWDATA[48]) = (0, 0);
( USERCLK *> MIMTXWDATA[49]) = (0, 0);
( USERCLK *> MIMTXWDATA[4]) = (0, 0);
( USERCLK *> MIMTXWDATA[50]) = (0, 0);
( USERCLK *> MIMTXWDATA[51]) = (0, 0);
( USERCLK *> MIMTXWDATA[52]) = (0, 0);
( USERCLK *> MIMTXWDATA[53]) = (0, 0);
( USERCLK *> MIMTXWDATA[54]) = (0, 0);
( USERCLK *> MIMTXWDATA[55]) = (0, 0);
( USERCLK *> MIMTXWDATA[56]) = (0, 0);
( USERCLK *> MIMTXWDATA[57]) = (0, 0);
( USERCLK *> MIMTXWDATA[58]) = (0, 0);
( USERCLK *> MIMTXWDATA[59]) = (0, 0);
( USERCLK *> MIMTXWDATA[5]) = (0, 0);
( USERCLK *> MIMTXWDATA[60]) = (0, 0);
( USERCLK *> MIMTXWDATA[61]) = (0, 0);
( USERCLK *> MIMTXWDATA[62]) = (0, 0);
( USERCLK *> MIMTXWDATA[63]) = (0, 0);
( USERCLK *> MIMTXWDATA[64]) = (0, 0);
( USERCLK *> MIMTXWDATA[65]) = (0, 0);
( USERCLK *> MIMTXWDATA[66]) = (0, 0);
( USERCLK *> MIMTXWDATA[67]) = (0, 0);
( USERCLK *> MIMTXWDATA[68]) = (0, 0);
( USERCLK *> MIMTXWDATA[6]) = (0, 0);
( USERCLK *> MIMTXWDATA[7]) = (0, 0);
( USERCLK *> MIMTXWDATA[8]) = (0, 0);
( USERCLK *> MIMTXWDATA[9]) = (0, 0);
( USERCLK *> MIMTXWEN) = (0, 0);
( USERCLK2 *> CFGAERECRCCHECKEN) = (0, 0);
( USERCLK2 *> CFGAERECRCGENEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRCORRERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRCORRERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRFATALERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRNONFATALERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRNONFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGBRIDGESERREN) = (0, 0);
( USERCLK2 *> CFGCOMMANDBUSMASTERENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDINTERRUPTDISABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDIOENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDMEMENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDSERREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ARIFORWARDEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ATOMICEGRESSBLOCK) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ATOMICREQUESTEREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTDIS) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[3]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2IDOCPLEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2IDOREQEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2LTREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2TLPPREFIXBLOCK) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLAUXPOWEREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLCORRERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLENABLERO) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLEXTTAGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLNONFATALREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLNOSNOOPEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLPHANTOMEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLURERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSCORRERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSFATALERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSNONFATALERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSURDETECTED) = (0, 0);
( USERCLK2 *> CFGERRAERHEADERLOGSETN) = (0, 0);
( USERCLK2 *> CFGERRCPLRDYN) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[0]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[1]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[2]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[3]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[4]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[5]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[6]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[7]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[0]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[1]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[2]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIENABLE) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIXENABLE) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIXFM) = (0, 0);
( USERCLK2 *> CFGINTERRUPTRDYN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[0]) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[1]) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLAUTOBANDWIDTHINTEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLBANDWIDTHINTEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLCLOCKPMEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLCOMMONCLOCK) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLEXTENDEDSYNC) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLHWAUTOWIDTHDIS) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLLINKDISABLE) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLRCB) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLRETRAINLINK) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSAUTOBANDWIDTHSTATUS) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSBANDWIDTHSTATUS) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[0]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[1]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSDLLACTIVE) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSLINKTRAINING) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[0]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[1]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[2]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[3]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[0]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[10]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[11]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[12]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[13]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[14]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[15]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[16]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[17]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[18]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[19]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[1]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[20]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[21]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[22]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[23]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[24]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[25]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[26]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[27]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[28]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[29]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[2]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[30]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[31]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[3]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[4]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[5]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[6]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[7]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[8]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[9]) = (0, 0);
( USERCLK2 *> CFGMGMTRDWRDONEN) = (0, 0);
( USERCLK2 *> CFGMSGDATA[0]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[10]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[11]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[12]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[13]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[14]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[15]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[1]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[2]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[3]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[4]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[5]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[6]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[7]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[8]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[9]) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVED) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTA) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTB) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTC) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTD) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTA) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTB) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTC) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTD) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRCOR) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRFATAL) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRNONFATAL) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMASNAK) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMETO) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMETOACK) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMPME) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDSETSLOTPOWERLIMIT) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDUNLOCK) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[0]) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[1]) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[2]) = (0, 0);
( USERCLK2 *> CFGPMCSRPMEEN) = (0, 0);
( USERCLK2 *> CFGPMCSRPMESTATUS) = (0, 0);
( USERCLK2 *> CFGPMCSRPOWERSTATE[0]) = (0, 0);
( USERCLK2 *> CFGPMCSRPOWERSTATE[1]) = (0, 0);
( USERCLK2 *> CFGPMRCVASREQL1N) = (0, 0);
( USERCLK2 *> CFGPMRCVENTERL1N) = (0, 0);
( USERCLK2 *> CFGPMRCVENTERL23N) = (0, 0);
( USERCLK2 *> CFGPMRCVREQACKN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLPMEINTEN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRCORRERREN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRFATALERREN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRNONFATALERREN) = (0, 0);
( USERCLK2 *> CFGSLOTCONTROLELECTROMECHILCTLPULSE) = (0, 0);
( USERCLK2 *> CFGTRANSACTION) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[0]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[1]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[2]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[3]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[4]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[5]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[6]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONTYPE) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[0]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[1]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[2]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[3]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[4]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[5]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[6]) = (0, 0);
( USERCLK2 *> DBGSCLRA) = (0, 0);
( USERCLK2 *> DBGSCLRB) = (0, 0);
( USERCLK2 *> DBGSCLRC) = (0, 0);
( USERCLK2 *> DBGSCLRD) = (0, 0);
( USERCLK2 *> DBGSCLRE) = (0, 0);
( USERCLK2 *> DBGSCLRF) = (0, 0);
( USERCLK2 *> DBGSCLRG) = (0, 0);
( USERCLK2 *> DBGSCLRH) = (0, 0);
( USERCLK2 *> DBGSCLRI) = (0, 0);
( USERCLK2 *> DBGSCLRJ) = (0, 0);
( USERCLK2 *> DBGSCLRK) = (0, 0);
( USERCLK2 *> DBGVECA[0]) = (0, 0);
( USERCLK2 *> DBGVECA[10]) = (0, 0);
( USERCLK2 *> DBGVECA[11]) = (0, 0);
( USERCLK2 *> DBGVECA[12]) = (0, 0);
( USERCLK2 *> DBGVECA[13]) = (0, 0);
( USERCLK2 *> DBGVECA[14]) = (0, 0);
( USERCLK2 *> DBGVECA[15]) = (0, 0);
( USERCLK2 *> DBGVECA[16]) = (0, 0);
( USERCLK2 *> DBGVECA[17]) = (0, 0);
( USERCLK2 *> DBGVECA[18]) = (0, 0);
( USERCLK2 *> DBGVECA[19]) = (0, 0);
( USERCLK2 *> DBGVECA[1]) = (0, 0);
( USERCLK2 *> DBGVECA[20]) = (0, 0);
( USERCLK2 *> DBGVECA[21]) = (0, 0);
( USERCLK2 *> DBGVECA[22]) = (0, 0);
( USERCLK2 *> DBGVECA[23]) = (0, 0);
( USERCLK2 *> DBGVECA[24]) = (0, 0);
( USERCLK2 *> DBGVECA[25]) = (0, 0);
( USERCLK2 *> DBGVECA[26]) = (0, 0);
( USERCLK2 *> DBGVECA[27]) = (0, 0);
( USERCLK2 *> DBGVECA[28]) = (0, 0);
( USERCLK2 *> DBGVECA[29]) = (0, 0);
( USERCLK2 *> DBGVECA[2]) = (0, 0);
( USERCLK2 *> DBGVECA[30]) = (0, 0);
( USERCLK2 *> DBGVECA[31]) = (0, 0);
( USERCLK2 *> DBGVECA[32]) = (0, 0);
( USERCLK2 *> DBGVECA[33]) = (0, 0);
( USERCLK2 *> DBGVECA[34]) = (0, 0);
( USERCLK2 *> DBGVECA[35]) = (0, 0);
( USERCLK2 *> DBGVECA[36]) = (0, 0);
( USERCLK2 *> DBGVECA[37]) = (0, 0);
( USERCLK2 *> DBGVECA[38]) = (0, 0);
( USERCLK2 *> DBGVECA[39]) = (0, 0);
( USERCLK2 *> DBGVECA[3]) = (0, 0);
( USERCLK2 *> DBGVECA[40]) = (0, 0);
( USERCLK2 *> DBGVECA[41]) = (0, 0);
( USERCLK2 *> DBGVECA[42]) = (0, 0);
( USERCLK2 *> DBGVECA[43]) = (0, 0);
( USERCLK2 *> DBGVECA[44]) = (0, 0);
( USERCLK2 *> DBGVECA[45]) = (0, 0);
( USERCLK2 *> DBGVECA[46]) = (0, 0);
( USERCLK2 *> DBGVECA[47]) = (0, 0);
( USERCLK2 *> DBGVECA[48]) = (0, 0);
( USERCLK2 *> DBGVECA[49]) = (0, 0);
( USERCLK2 *> DBGVECA[4]) = (0, 0);
( USERCLK2 *> DBGVECA[50]) = (0, 0);
( USERCLK2 *> DBGVECA[51]) = (0, 0);
( USERCLK2 *> DBGVECA[52]) = (0, 0);
( USERCLK2 *> DBGVECA[53]) = (0, 0);
( USERCLK2 *> DBGVECA[54]) = (0, 0);
( USERCLK2 *> DBGVECA[55]) = (0, 0);
( USERCLK2 *> DBGVECA[56]) = (0, 0);
( USERCLK2 *> DBGVECA[57]) = (0, 0);
( USERCLK2 *> DBGVECA[58]) = (0, 0);
( USERCLK2 *> DBGVECA[59]) = (0, 0);
( USERCLK2 *> DBGVECA[5]) = (0, 0);
( USERCLK2 *> DBGVECA[60]) = (0, 0);
( USERCLK2 *> DBGVECA[61]) = (0, 0);
( USERCLK2 *> DBGVECA[62]) = (0, 0);
( USERCLK2 *> DBGVECA[63]) = (0, 0);
( USERCLK2 *> DBGVECA[6]) = (0, 0);
( USERCLK2 *> DBGVECA[7]) = (0, 0);
( USERCLK2 *> DBGVECA[8]) = (0, 0);
( USERCLK2 *> DBGVECA[9]) = (0, 0);
( USERCLK2 *> DBGVECB[0]) = (0, 0);
( USERCLK2 *> DBGVECB[10]) = (0, 0);
( USERCLK2 *> DBGVECB[11]) = (0, 0);
( USERCLK2 *> DBGVECB[12]) = (0, 0);
( USERCLK2 *> DBGVECB[13]) = (0, 0);
( USERCLK2 *> DBGVECB[14]) = (0, 0);
( USERCLK2 *> DBGVECB[15]) = (0, 0);
( USERCLK2 *> DBGVECB[16]) = (0, 0);
( USERCLK2 *> DBGVECB[17]) = (0, 0);
( USERCLK2 *> DBGVECB[18]) = (0, 0);
( USERCLK2 *> DBGVECB[19]) = (0, 0);
( USERCLK2 *> DBGVECB[1]) = (0, 0);
( USERCLK2 *> DBGVECB[20]) = (0, 0);
( USERCLK2 *> DBGVECB[21]) = (0, 0);
( USERCLK2 *> DBGVECB[22]) = (0, 0);
( USERCLK2 *> DBGVECB[23]) = (0, 0);
( USERCLK2 *> DBGVECB[24]) = (0, 0);
( USERCLK2 *> DBGVECB[25]) = (0, 0);
( USERCLK2 *> DBGVECB[26]) = (0, 0);
( USERCLK2 *> DBGVECB[27]) = (0, 0);
( USERCLK2 *> DBGVECB[28]) = (0, 0);
( USERCLK2 *> DBGVECB[29]) = (0, 0);
( USERCLK2 *> DBGVECB[2]) = (0, 0);
( USERCLK2 *> DBGVECB[30]) = (0, 0);
( USERCLK2 *> DBGVECB[31]) = (0, 0);
( USERCLK2 *> DBGVECB[32]) = (0, 0);
( USERCLK2 *> DBGVECB[33]) = (0, 0);
( USERCLK2 *> DBGVECB[34]) = (0, 0);
( USERCLK2 *> DBGVECB[35]) = (0, 0);
( USERCLK2 *> DBGVECB[36]) = (0, 0);
( USERCLK2 *> DBGVECB[37]) = (0, 0);
( USERCLK2 *> DBGVECB[38]) = (0, 0);
( USERCLK2 *> DBGVECB[39]) = (0, 0);
( USERCLK2 *> DBGVECB[3]) = (0, 0);
( USERCLK2 *> DBGVECB[40]) = (0, 0);
( USERCLK2 *> DBGVECB[41]) = (0, 0);
( USERCLK2 *> DBGVECB[42]) = (0, 0);
( USERCLK2 *> DBGVECB[43]) = (0, 0);
( USERCLK2 *> DBGVECB[44]) = (0, 0);
( USERCLK2 *> DBGVECB[45]) = (0, 0);
( USERCLK2 *> DBGVECB[46]) = (0, 0);
( USERCLK2 *> DBGVECB[47]) = (0, 0);
( USERCLK2 *> DBGVECB[48]) = (0, 0);
( USERCLK2 *> DBGVECB[49]) = (0, 0);
( USERCLK2 *> DBGVECB[4]) = (0, 0);
( USERCLK2 *> DBGVECB[50]) = (0, 0);
( USERCLK2 *> DBGVECB[51]) = (0, 0);
( USERCLK2 *> DBGVECB[52]) = (0, 0);
( USERCLK2 *> DBGVECB[53]) = (0, 0);
( USERCLK2 *> DBGVECB[54]) = (0, 0);
( USERCLK2 *> DBGVECB[55]) = (0, 0);
( USERCLK2 *> DBGVECB[56]) = (0, 0);
( USERCLK2 *> DBGVECB[57]) = (0, 0);
( USERCLK2 *> DBGVECB[58]) = (0, 0);
( USERCLK2 *> DBGVECB[59]) = (0, 0);
( USERCLK2 *> DBGVECB[5]) = (0, 0);
( USERCLK2 *> DBGVECB[60]) = (0, 0);
( USERCLK2 *> DBGVECB[61]) = (0, 0);
( USERCLK2 *> DBGVECB[62]) = (0, 0);
( USERCLK2 *> DBGVECB[63]) = (0, 0);
( USERCLK2 *> DBGVECB[6]) = (0, 0);
( USERCLK2 *> DBGVECB[7]) = (0, 0);
( USERCLK2 *> DBGVECB[8]) = (0, 0);
( USERCLK2 *> DBGVECB[9]) = (0, 0);
( USERCLK2 *> DBGVECC[0]) = (0, 0);
( USERCLK2 *> DBGVECC[10]) = (0, 0);
( USERCLK2 *> DBGVECC[11]) = (0, 0);
( USERCLK2 *> DBGVECC[1]) = (0, 0);
( USERCLK2 *> DBGVECC[2]) = (0, 0);
( USERCLK2 *> DBGVECC[3]) = (0, 0);
( USERCLK2 *> DBGVECC[4]) = (0, 0);
( USERCLK2 *> DBGVECC[5]) = (0, 0);
( USERCLK2 *> DBGVECC[6]) = (0, 0);
( USERCLK2 *> DBGVECC[7]) = (0, 0);
( USERCLK2 *> DBGVECC[8]) = (0, 0);
( USERCLK2 *> DBGVECC[9]) = (0, 0);
( USERCLK2 *> LL2BADDLLPERR) = (0, 0);
( USERCLK2 *> LL2BADTLPERR) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[0]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[1]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[2]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[3]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[4]) = (0, 0);
( USERCLK2 *> LL2PROTOCOLERR) = (0, 0);
( USERCLK2 *> LL2RECEIVERERR) = (0, 0);
( USERCLK2 *> LL2REPLAYROERR) = (0, 0);
( USERCLK2 *> LL2REPLAYTOERR) = (0, 0);
( USERCLK2 *> LL2SUSPENDOK) = (0, 0);
( USERCLK2 *> LL2TFCINIT1SEQ) = (0, 0);
( USERCLK2 *> LL2TFCINIT2SEQ) = (0, 0);
( USERCLK2 *> LL2TXIDLE) = (0, 0);
( USERCLK2 *> PL2L0REQ) = (0, 0);
( USERCLK2 *> PL2LINKUP) = (0, 0);
( USERCLK2 *> PL2RECEIVERERR) = (0, 0);
( USERCLK2 *> PL2RECOVERY) = (0, 0);
( USERCLK2 *> PL2RXELECIDLE) = (0, 0);
( USERCLK2 *> PL2RXPMSTATE[0]) = (0, 0);
( USERCLK2 *> PL2RXPMSTATE[1]) = (0, 0);
( USERCLK2 *> PL2SUSPENDOK) = (0, 0);
( USERCLK2 *> RECEIVEDFUNCLVLRSTN) = (0, 0);
( USERCLK2 *> TL2ASPMSUSPENDCREDITCHECKOK) = (0, 0);
( USERCLK2 *> TL2ASPMSUSPENDREQ) = (0, 0);
( USERCLK2 *> TL2ERRFCPE) = (0, 0);
( USERCLK2 *> TL2ERRHDR[0]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[10]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[11]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[12]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[13]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[14]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[15]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[16]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[17]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[18]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[19]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[1]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[20]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[21]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[22]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[23]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[24]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[25]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[26]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[27]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[28]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[29]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[2]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[30]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[31]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[32]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[33]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[34]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[35]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[36]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[37]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[38]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[39]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[3]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[40]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[41]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[42]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[43]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[44]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[45]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[46]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[47]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[48]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[49]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[4]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[50]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[51]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[52]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[53]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[54]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[55]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[56]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[57]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[58]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[59]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[5]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[60]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[61]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[62]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[63]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[6]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[7]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[8]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[9]) = (0, 0);
( USERCLK2 *> TL2ERRMALFORMED) = (0, 0);
( USERCLK2 *> TL2ERRRXOVERFLOW) = (0, 0);
( USERCLK2 *> TL2PPMSUSPENDOK) = (0, 0);
( USERCLK2 *> TRNFCCPLD[0]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[10]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[11]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[1]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[2]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[3]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[4]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[5]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[6]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[7]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[8]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[9]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[0]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[1]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[2]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[3]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[4]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[5]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[6]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[7]) = (0, 0);
( USERCLK2 *> TRNFCNPD[0]) = (0, 0);
( USERCLK2 *> TRNFCNPD[10]) = (0, 0);
( USERCLK2 *> TRNFCNPD[11]) = (0, 0);
( USERCLK2 *> TRNFCNPD[1]) = (0, 0);
( USERCLK2 *> TRNFCNPD[2]) = (0, 0);
( USERCLK2 *> TRNFCNPD[3]) = (0, 0);
( USERCLK2 *> TRNFCNPD[4]) = (0, 0);
( USERCLK2 *> TRNFCNPD[5]) = (0, 0);
( USERCLK2 *> TRNFCNPD[6]) = (0, 0);
( USERCLK2 *> TRNFCNPD[7]) = (0, 0);
( USERCLK2 *> TRNFCNPD[8]) = (0, 0);
( USERCLK2 *> TRNFCNPD[9]) = (0, 0);
( USERCLK2 *> TRNFCNPH[0]) = (0, 0);
( USERCLK2 *> TRNFCNPH[1]) = (0, 0);
( USERCLK2 *> TRNFCNPH[2]) = (0, 0);
( USERCLK2 *> TRNFCNPH[3]) = (0, 0);
( USERCLK2 *> TRNFCNPH[4]) = (0, 0);
( USERCLK2 *> TRNFCNPH[5]) = (0, 0);
( USERCLK2 *> TRNFCNPH[6]) = (0, 0);
( USERCLK2 *> TRNFCNPH[7]) = (0, 0);
( USERCLK2 *> TRNFCPD[0]) = (0, 0);
( USERCLK2 *> TRNFCPD[10]) = (0, 0);
( USERCLK2 *> TRNFCPD[11]) = (0, 0);
( USERCLK2 *> TRNFCPD[1]) = (0, 0);
( USERCLK2 *> TRNFCPD[2]) = (0, 0);
( USERCLK2 *> TRNFCPD[3]) = (0, 0);
( USERCLK2 *> TRNFCPD[4]) = (0, 0);
( USERCLK2 *> TRNFCPD[5]) = (0, 0);
( USERCLK2 *> TRNFCPD[6]) = (0, 0);
( USERCLK2 *> TRNFCPD[7]) = (0, 0);
( USERCLK2 *> TRNFCPD[8]) = (0, 0);
( USERCLK2 *> TRNFCPD[9]) = (0, 0);
( USERCLK2 *> TRNFCPH[0]) = (0, 0);
( USERCLK2 *> TRNFCPH[1]) = (0, 0);
( USERCLK2 *> TRNFCPH[2]) = (0, 0);
( USERCLK2 *> TRNFCPH[3]) = (0, 0);
( USERCLK2 *> TRNFCPH[4]) = (0, 0);
( USERCLK2 *> TRNFCPH[5]) = (0, 0);
( USERCLK2 *> TRNFCPH[6]) = (0, 0);
( USERCLK2 *> TRNFCPH[7]) = (0, 0);
( USERCLK2 *> TRNLNKUP) = (0, 0);
( USERCLK2 *> TRNRBARHIT[0]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[1]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[2]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[3]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[4]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[5]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[6]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[7]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[0]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[10]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[11]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[12]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[13]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[14]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[15]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[16]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[17]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[18]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[19]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[1]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[20]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[21]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[22]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[23]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[24]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[25]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[26]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[27]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[28]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[29]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[2]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[30]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[31]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[32]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[33]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[34]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[35]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[36]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[37]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[38]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[39]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[3]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[40]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[41]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[42]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[43]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[44]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[45]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[46]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[47]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[48]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[49]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[4]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[50]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[51]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[52]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[53]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[54]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[55]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[56]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[57]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[58]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[59]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[5]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[60]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[61]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[62]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[63]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[6]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[7]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[8]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[9]) = (0, 0);
( USERCLK2 *> TRNRDLLPSRCRDY[0]) = (0, 0);
( USERCLK2 *> TRNRDLLPSRCRDY[1]) = (0, 0);
( USERCLK2 *> TRNRD[0]) = (0, 0);
( USERCLK2 *> TRNRD[100]) = (0, 0);
( USERCLK2 *> TRNRD[101]) = (0, 0);
( USERCLK2 *> TRNRD[102]) = (0, 0);
( USERCLK2 *> TRNRD[103]) = (0, 0);
( USERCLK2 *> TRNRD[104]) = (0, 0);
( USERCLK2 *> TRNRD[105]) = (0, 0);
( USERCLK2 *> TRNRD[106]) = (0, 0);
( USERCLK2 *> TRNRD[107]) = (0, 0);
( USERCLK2 *> TRNRD[108]) = (0, 0);
( USERCLK2 *> TRNRD[109]) = (0, 0);
( USERCLK2 *> TRNRD[10]) = (0, 0);
( USERCLK2 *> TRNRD[110]) = (0, 0);
( USERCLK2 *> TRNRD[111]) = (0, 0);
( USERCLK2 *> TRNRD[112]) = (0, 0);
( USERCLK2 *> TRNRD[113]) = (0, 0);
( USERCLK2 *> TRNRD[114]) = (0, 0);
( USERCLK2 *> TRNRD[115]) = (0, 0);
( USERCLK2 *> TRNRD[116]) = (0, 0);
( USERCLK2 *> TRNRD[117]) = (0, 0);
( USERCLK2 *> TRNRD[118]) = (0, 0);
( USERCLK2 *> TRNRD[119]) = (0, 0);
( USERCLK2 *> TRNRD[11]) = (0, 0);
( USERCLK2 *> TRNRD[120]) = (0, 0);
( USERCLK2 *> TRNRD[121]) = (0, 0);
( USERCLK2 *> TRNRD[122]) = (0, 0);
( USERCLK2 *> TRNRD[123]) = (0, 0);
( USERCLK2 *> TRNRD[124]) = (0, 0);
( USERCLK2 *> TRNRD[125]) = (0, 0);
( USERCLK2 *> TRNRD[126]) = (0, 0);
( USERCLK2 *> TRNRD[127]) = (0, 0);
( USERCLK2 *> TRNRD[12]) = (0, 0);
( USERCLK2 *> TRNRD[13]) = (0, 0);
( USERCLK2 *> TRNRD[14]) = (0, 0);
( USERCLK2 *> TRNRD[15]) = (0, 0);
( USERCLK2 *> TRNRD[16]) = (0, 0);
( USERCLK2 *> TRNRD[17]) = (0, 0);
( USERCLK2 *> TRNRD[18]) = (0, 0);
( USERCLK2 *> TRNRD[19]) = (0, 0);
( USERCLK2 *> TRNRD[1]) = (0, 0);
( USERCLK2 *> TRNRD[20]) = (0, 0);
( USERCLK2 *> TRNRD[21]) = (0, 0);
( USERCLK2 *> TRNRD[22]) = (0, 0);
( USERCLK2 *> TRNRD[23]) = (0, 0);
( USERCLK2 *> TRNRD[24]) = (0, 0);
( USERCLK2 *> TRNRD[25]) = (0, 0);
( USERCLK2 *> TRNRD[26]) = (0, 0);
( USERCLK2 *> TRNRD[27]) = (0, 0);
( USERCLK2 *> TRNRD[28]) = (0, 0);
( USERCLK2 *> TRNRD[29]) = (0, 0);
( USERCLK2 *> TRNRD[2]) = (0, 0);
( USERCLK2 *> TRNRD[30]) = (0, 0);
( USERCLK2 *> TRNRD[31]) = (0, 0);
( USERCLK2 *> TRNRD[32]) = (0, 0);
( USERCLK2 *> TRNRD[33]) = (0, 0);
( USERCLK2 *> TRNRD[34]) = (0, 0);
( USERCLK2 *> TRNRD[35]) = (0, 0);
( USERCLK2 *> TRNRD[36]) = (0, 0);
( USERCLK2 *> TRNRD[37]) = (0, 0);
( USERCLK2 *> TRNRD[38]) = (0, 0);
( USERCLK2 *> TRNRD[39]) = (0, 0);
( USERCLK2 *> TRNRD[3]) = (0, 0);
( USERCLK2 *> TRNRD[40]) = (0, 0);
( USERCLK2 *> TRNRD[41]) = (0, 0);
( USERCLK2 *> TRNRD[42]) = (0, 0);
( USERCLK2 *> TRNRD[43]) = (0, 0);
( USERCLK2 *> TRNRD[44]) = (0, 0);
( USERCLK2 *> TRNRD[45]) = (0, 0);
( USERCLK2 *> TRNRD[46]) = (0, 0);
( USERCLK2 *> TRNRD[47]) = (0, 0);
( USERCLK2 *> TRNRD[48]) = (0, 0);
( USERCLK2 *> TRNRD[49]) = (0, 0);
( USERCLK2 *> TRNRD[4]) = (0, 0);
( USERCLK2 *> TRNRD[50]) = (0, 0);
( USERCLK2 *> TRNRD[51]) = (0, 0);
( USERCLK2 *> TRNRD[52]) = (0, 0);
( USERCLK2 *> TRNRD[53]) = (0, 0);
( USERCLK2 *> TRNRD[54]) = (0, 0);
( USERCLK2 *> TRNRD[55]) = (0, 0);
( USERCLK2 *> TRNRD[56]) = (0, 0);
( USERCLK2 *> TRNRD[57]) = (0, 0);
( USERCLK2 *> TRNRD[58]) = (0, 0);
( USERCLK2 *> TRNRD[59]) = (0, 0);
( USERCLK2 *> TRNRD[5]) = (0, 0);
( USERCLK2 *> TRNRD[60]) = (0, 0);
( USERCLK2 *> TRNRD[61]) = (0, 0);
( USERCLK2 *> TRNRD[62]) = (0, 0);
( USERCLK2 *> TRNRD[63]) = (0, 0);
( USERCLK2 *> TRNRD[64]) = (0, 0);
( USERCLK2 *> TRNRD[65]) = (0, 0);
( USERCLK2 *> TRNRD[66]) = (0, 0);
( USERCLK2 *> TRNRD[67]) = (0, 0);
( USERCLK2 *> TRNRD[68]) = (0, 0);
( USERCLK2 *> TRNRD[69]) = (0, 0);
( USERCLK2 *> TRNRD[6]) = (0, 0);
( USERCLK2 *> TRNRD[70]) = (0, 0);
( USERCLK2 *> TRNRD[71]) = (0, 0);
( USERCLK2 *> TRNRD[72]) = (0, 0);
( USERCLK2 *> TRNRD[73]) = (0, 0);
( USERCLK2 *> TRNRD[74]) = (0, 0);
( USERCLK2 *> TRNRD[75]) = (0, 0);
( USERCLK2 *> TRNRD[76]) = (0, 0);
( USERCLK2 *> TRNRD[77]) = (0, 0);
( USERCLK2 *> TRNRD[78]) = (0, 0);
( USERCLK2 *> TRNRD[79]) = (0, 0);
( USERCLK2 *> TRNRD[7]) = (0, 0);
( USERCLK2 *> TRNRD[80]) = (0, 0);
( USERCLK2 *> TRNRD[81]) = (0, 0);
( USERCLK2 *> TRNRD[82]) = (0, 0);
( USERCLK2 *> TRNRD[83]) = (0, 0);
( USERCLK2 *> TRNRD[84]) = (0, 0);
( USERCLK2 *> TRNRD[85]) = (0, 0);
( USERCLK2 *> TRNRD[86]) = (0, 0);
( USERCLK2 *> TRNRD[87]) = (0, 0);
( USERCLK2 *> TRNRD[88]) = (0, 0);
( USERCLK2 *> TRNRD[89]) = (0, 0);
( USERCLK2 *> TRNRD[8]) = (0, 0);
( USERCLK2 *> TRNRD[90]) = (0, 0);
( USERCLK2 *> TRNRD[91]) = (0, 0);
( USERCLK2 *> TRNRD[92]) = (0, 0);
( USERCLK2 *> TRNRD[93]) = (0, 0);
( USERCLK2 *> TRNRD[94]) = (0, 0);
( USERCLK2 *> TRNRD[95]) = (0, 0);
( USERCLK2 *> TRNRD[96]) = (0, 0);
( USERCLK2 *> TRNRD[97]) = (0, 0);
( USERCLK2 *> TRNRD[98]) = (0, 0);
( USERCLK2 *> TRNRD[99]) = (0, 0);
( USERCLK2 *> TRNRD[9]) = (0, 0);
( USERCLK2 *> TRNRECRCERR) = (0, 0);
( USERCLK2 *> TRNREOF) = (0, 0);
( USERCLK2 *> TRNRERRFWD) = (0, 0);
( USERCLK2 *> TRNRREM[0]) = (0, 0);
( USERCLK2 *> TRNRREM[1]) = (0, 0);
( USERCLK2 *> TRNRSOF) = (0, 0);
( USERCLK2 *> TRNRSRCDSC) = (0, 0);
( USERCLK2 *> TRNRSRCRDY) = (0, 0);
( USERCLK2 *> TRNTBUFAV[0]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[1]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[2]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[3]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[4]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[5]) = (0, 0);
( USERCLK2 *> TRNTCFGREQ) = (0, 0);
( USERCLK2 *> TRNTDLLPDSTRDY) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[0]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[1]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[2]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[3]) = (0, 0);
( USERCLK2 *> TRNTERRDROP) = (0, 0);
( USERCLK2 *> USERRSTN) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PCIE_3_0.v 0000664 0000000 0000000 00003526234 12327044266 0022622 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : PCIE_3_0.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PCIE_3_0 (
CFGCURRENTSPEED,
CFGDPASUBSTATECHANGE,
CFGERRCOROUT,
CFGERRFATALOUT,
CFGERRNONFATALOUT,
CFGEXTFUNCTIONNUMBER,
CFGEXTREADRECEIVED,
CFGEXTREGISTERNUMBER,
CFGEXTWRITEBYTEENABLE,
CFGEXTWRITEDATA,
CFGEXTWRITERECEIVED,
CFGFCCPLD,
CFGFCCPLH,
CFGFCNPD,
CFGFCNPH,
CFGFCPD,
CFGFCPH,
CFGFLRINPROCESS,
CFGFUNCTIONPOWERSTATE,
CFGFUNCTIONSTATUS,
CFGHOTRESETOUT,
CFGINPUTUPDATEDONE,
CFGINTERRUPTAOUTPUT,
CFGINTERRUPTBOUTPUT,
CFGINTERRUPTCOUTPUT,
CFGINTERRUPTDOUTPUT,
CFGINTERRUPTMSIDATA,
CFGINTERRUPTMSIENABLE,
CFGINTERRUPTMSIFAIL,
CFGINTERRUPTMSIMASKUPDATE,
CFGINTERRUPTMSIMMENABLE,
CFGINTERRUPTMSISENT,
CFGINTERRUPTMSIVFENABLE,
CFGINTERRUPTMSIXENABLE,
CFGINTERRUPTMSIXFAIL,
CFGINTERRUPTMSIXMASK,
CFGINTERRUPTMSIXSENT,
CFGINTERRUPTMSIXVFENABLE,
CFGINTERRUPTMSIXVFMASK,
CFGINTERRUPTSENT,
CFGLINKPOWERSTATE,
CFGLOCALERROR,
CFGLTRENABLE,
CFGLTSSMSTATE,
CFGMAXPAYLOAD,
CFGMAXREADREQ,
CFGMCUPDATEDONE,
CFGMGMTREADDATA,
CFGMGMTREADWRITEDONE,
CFGMSGRECEIVED,
CFGMSGRECEIVEDDATA,
CFGMSGRECEIVEDTYPE,
CFGMSGTRANSMITDONE,
CFGNEGOTIATEDWIDTH,
CFGOBFFENABLE,
CFGPERFUNCSTATUSDATA,
CFGPERFUNCTIONUPDATEDONE,
CFGPHYLINKDOWN,
CFGPHYLINKSTATUS,
CFGPLSTATUSCHANGE,
CFGPOWERSTATECHANGEINTERRUPT,
CFGRCBSTATUS,
CFGTPHFUNCTIONNUM,
CFGTPHREQUESTERENABLE,
CFGTPHSTMODE,
CFGTPHSTTADDRESS,
CFGTPHSTTREADENABLE,
CFGTPHSTTWRITEBYTEVALID,
CFGTPHSTTWRITEDATA,
CFGTPHSTTWRITEENABLE,
CFGVFFLRINPROCESS,
CFGVFPOWERSTATE,
CFGVFSTATUS,
CFGVFTPHREQUESTERENABLE,
CFGVFTPHSTMODE,
DBGDATAOUT,
DRPDO,
DRPRDY,
MAXISCQTDATA,
MAXISCQTKEEP,
MAXISCQTLAST,
MAXISCQTUSER,
MAXISCQTVALID,
MAXISRCTDATA,
MAXISRCTKEEP,
MAXISRCTLAST,
MAXISRCTUSER,
MAXISRCTVALID,
MICOMPLETIONRAMREADADDRESSAL,
MICOMPLETIONRAMREADADDRESSAU,
MICOMPLETIONRAMREADADDRESSBL,
MICOMPLETIONRAMREADADDRESSBU,
MICOMPLETIONRAMREADENABLEL,
MICOMPLETIONRAMREADENABLEU,
MICOMPLETIONRAMWRITEADDRESSAL,
MICOMPLETIONRAMWRITEADDRESSAU,
MICOMPLETIONRAMWRITEADDRESSBL,
MICOMPLETIONRAMWRITEADDRESSBU,
MICOMPLETIONRAMWRITEDATAL,
MICOMPLETIONRAMWRITEDATAU,
MICOMPLETIONRAMWRITEENABLEL,
MICOMPLETIONRAMWRITEENABLEU,
MIREPLAYRAMADDRESS,
MIREPLAYRAMREADENABLE,
MIREPLAYRAMWRITEDATA,
MIREPLAYRAMWRITEENABLE,
MIREQUESTRAMREADADDRESSA,
MIREQUESTRAMREADADDRESSB,
MIREQUESTRAMREADENABLE,
MIREQUESTRAMWRITEADDRESSA,
MIREQUESTRAMWRITEADDRESSB,
MIREQUESTRAMWRITEDATA,
MIREQUESTRAMWRITEENABLE,
PCIECQNPREQCOUNT,
PCIERQSEQNUM,
PCIERQSEQNUMVLD,
PCIERQTAG,
PCIERQTAGAV,
PCIERQTAGVLD,
PCIETFCNPDAV,
PCIETFCNPHAV,
PIPERX0EQCONTROL,
PIPERX0EQLPLFFS,
PIPERX0EQLPTXPRESET,
PIPERX0EQPRESET,
PIPERX0POLARITY,
PIPERX1EQCONTROL,
PIPERX1EQLPLFFS,
PIPERX1EQLPTXPRESET,
PIPERX1EQPRESET,
PIPERX1POLARITY,
PIPERX2EQCONTROL,
PIPERX2EQLPLFFS,
PIPERX2EQLPTXPRESET,
PIPERX2EQPRESET,
PIPERX2POLARITY,
PIPERX3EQCONTROL,
PIPERX3EQLPLFFS,
PIPERX3EQLPTXPRESET,
PIPERX3EQPRESET,
PIPERX3POLARITY,
PIPERX4EQCONTROL,
PIPERX4EQLPLFFS,
PIPERX4EQLPTXPRESET,
PIPERX4EQPRESET,
PIPERX4POLARITY,
PIPERX5EQCONTROL,
PIPERX5EQLPLFFS,
PIPERX5EQLPTXPRESET,
PIPERX5EQPRESET,
PIPERX5POLARITY,
PIPERX6EQCONTROL,
PIPERX6EQLPLFFS,
PIPERX6EQLPTXPRESET,
PIPERX6EQPRESET,
PIPERX6POLARITY,
PIPERX7EQCONTROL,
PIPERX7EQLPLFFS,
PIPERX7EQLPTXPRESET,
PIPERX7EQPRESET,
PIPERX7POLARITY,
PIPETX0CHARISK,
PIPETX0COMPLIANCE,
PIPETX0DATA,
PIPETX0DATAVALID,
PIPETX0ELECIDLE,
PIPETX0EQCONTROL,
PIPETX0EQDEEMPH,
PIPETX0EQPRESET,
PIPETX0POWERDOWN,
PIPETX0STARTBLOCK,
PIPETX0SYNCHEADER,
PIPETX1CHARISK,
PIPETX1COMPLIANCE,
PIPETX1DATA,
PIPETX1DATAVALID,
PIPETX1ELECIDLE,
PIPETX1EQCONTROL,
PIPETX1EQDEEMPH,
PIPETX1EQPRESET,
PIPETX1POWERDOWN,
PIPETX1STARTBLOCK,
PIPETX1SYNCHEADER,
PIPETX2CHARISK,
PIPETX2COMPLIANCE,
PIPETX2DATA,
PIPETX2DATAVALID,
PIPETX2ELECIDLE,
PIPETX2EQCONTROL,
PIPETX2EQDEEMPH,
PIPETX2EQPRESET,
PIPETX2POWERDOWN,
PIPETX2STARTBLOCK,
PIPETX2SYNCHEADER,
PIPETX3CHARISK,
PIPETX3COMPLIANCE,
PIPETX3DATA,
PIPETX3DATAVALID,
PIPETX3ELECIDLE,
PIPETX3EQCONTROL,
PIPETX3EQDEEMPH,
PIPETX3EQPRESET,
PIPETX3POWERDOWN,
PIPETX3STARTBLOCK,
PIPETX3SYNCHEADER,
PIPETX4CHARISK,
PIPETX4COMPLIANCE,
PIPETX4DATA,
PIPETX4DATAVALID,
PIPETX4ELECIDLE,
PIPETX4EQCONTROL,
PIPETX4EQDEEMPH,
PIPETX4EQPRESET,
PIPETX4POWERDOWN,
PIPETX4STARTBLOCK,
PIPETX4SYNCHEADER,
PIPETX5CHARISK,
PIPETX5COMPLIANCE,
PIPETX5DATA,
PIPETX5DATAVALID,
PIPETX5ELECIDLE,
PIPETX5EQCONTROL,
PIPETX5EQDEEMPH,
PIPETX5EQPRESET,
PIPETX5POWERDOWN,
PIPETX5STARTBLOCK,
PIPETX5SYNCHEADER,
PIPETX6CHARISK,
PIPETX6COMPLIANCE,
PIPETX6DATA,
PIPETX6DATAVALID,
PIPETX6ELECIDLE,
PIPETX6EQCONTROL,
PIPETX6EQDEEMPH,
PIPETX6EQPRESET,
PIPETX6POWERDOWN,
PIPETX6STARTBLOCK,
PIPETX6SYNCHEADER,
PIPETX7CHARISK,
PIPETX7COMPLIANCE,
PIPETX7DATA,
PIPETX7DATAVALID,
PIPETX7ELECIDLE,
PIPETX7EQCONTROL,
PIPETX7EQDEEMPH,
PIPETX7EQPRESET,
PIPETX7POWERDOWN,
PIPETX7STARTBLOCK,
PIPETX7SYNCHEADER,
PIPETXDEEMPH,
PIPETXMARGIN,
PIPETXRATE,
PIPETXRCVRDET,
PIPETXRESET,
PIPETXSWING,
PLEQINPROGRESS,
PLEQPHASE,
PLGEN3PCSRXSLIDE,
SAXISCCTREADY,
SAXISRQTREADY,
CFGCONFIGSPACEENABLE,
CFGDEVID,
CFGDSBUSNUMBER,
CFGDSDEVICENUMBER,
CFGDSFUNCTIONNUMBER,
CFGDSN,
CFGDSPORTNUMBER,
CFGERRCORIN,
CFGERRUNCORIN,
CFGEXTREADDATA,
CFGEXTREADDATAVALID,
CFGFCSEL,
CFGFLRDONE,
CFGHOTRESETIN,
CFGINPUTUPDATEREQUEST,
CFGINTERRUPTINT,
CFGINTERRUPTMSIATTR,
CFGINTERRUPTMSIFUNCTIONNUMBER,
CFGINTERRUPTMSIINT,
CFGINTERRUPTMSIPENDINGSTATUS,
CFGINTERRUPTMSISELECT,
CFGINTERRUPTMSITPHPRESENT,
CFGINTERRUPTMSITPHSTTAG,
CFGINTERRUPTMSITPHTYPE,
CFGINTERRUPTMSIXADDRESS,
CFGINTERRUPTMSIXDATA,
CFGINTERRUPTMSIXINT,
CFGINTERRUPTPENDING,
CFGLINKTRAININGENABLE,
CFGMCUPDATEREQUEST,
CFGMGMTADDR,
CFGMGMTBYTEENABLE,
CFGMGMTREAD,
CFGMGMTTYPE1CFGREGACCESS,
CFGMGMTWRITE,
CFGMGMTWRITEDATA,
CFGMSGTRANSMIT,
CFGMSGTRANSMITDATA,
CFGMSGTRANSMITTYPE,
CFGPERFUNCSTATUSCONTROL,
CFGPERFUNCTIONNUMBER,
CFGPERFUNCTIONOUTPUTREQUEST,
CFGPOWERSTATECHANGEACK,
CFGREQPMTRANSITIONL23READY,
CFGREVID,
CFGSUBSYSID,
CFGSUBSYSVENDID,
CFGTPHSTTREADDATA,
CFGTPHSTTREADDATAVALID,
CFGVENDID,
CFGVFFLRDONE,
CORECLK,
CORECLKMICOMPLETIONRAML,
CORECLKMICOMPLETIONRAMU,
CORECLKMIREPLAYRAM,
CORECLKMIREQUESTRAM,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
MAXISCQTREADY,
MAXISRCTREADY,
MGMTRESETN,
MGMTSTICKYRESETN,
MICOMPLETIONRAMREADDATA,
MIREPLAYRAMREADDATA,
MIREQUESTRAMREADDATA,
PCIECQNPREQ,
PIPECLK,
PIPEEQFS,
PIPEEQLF,
PIPERESETN,
PIPERX0CHARISK,
PIPERX0DATA,
PIPERX0DATAVALID,
PIPERX0ELECIDLE,
PIPERX0EQDONE,
PIPERX0EQLPADAPTDONE,
PIPERX0EQLPLFFSSEL,
PIPERX0EQLPNEWTXCOEFFORPRESET,
PIPERX0PHYSTATUS,
PIPERX0STARTBLOCK,
PIPERX0STATUS,
PIPERX0SYNCHEADER,
PIPERX0VALID,
PIPERX1CHARISK,
PIPERX1DATA,
PIPERX1DATAVALID,
PIPERX1ELECIDLE,
PIPERX1EQDONE,
PIPERX1EQLPADAPTDONE,
PIPERX1EQLPLFFSSEL,
PIPERX1EQLPNEWTXCOEFFORPRESET,
PIPERX1PHYSTATUS,
PIPERX1STARTBLOCK,
PIPERX1STATUS,
PIPERX1SYNCHEADER,
PIPERX1VALID,
PIPERX2CHARISK,
PIPERX2DATA,
PIPERX2DATAVALID,
PIPERX2ELECIDLE,
PIPERX2EQDONE,
PIPERX2EQLPADAPTDONE,
PIPERX2EQLPLFFSSEL,
PIPERX2EQLPNEWTXCOEFFORPRESET,
PIPERX2PHYSTATUS,
PIPERX2STARTBLOCK,
PIPERX2STATUS,
PIPERX2SYNCHEADER,
PIPERX2VALID,
PIPERX3CHARISK,
PIPERX3DATA,
PIPERX3DATAVALID,
PIPERX3ELECIDLE,
PIPERX3EQDONE,
PIPERX3EQLPADAPTDONE,
PIPERX3EQLPLFFSSEL,
PIPERX3EQLPNEWTXCOEFFORPRESET,
PIPERX3PHYSTATUS,
PIPERX3STARTBLOCK,
PIPERX3STATUS,
PIPERX3SYNCHEADER,
PIPERX3VALID,
PIPERX4CHARISK,
PIPERX4DATA,
PIPERX4DATAVALID,
PIPERX4ELECIDLE,
PIPERX4EQDONE,
PIPERX4EQLPADAPTDONE,
PIPERX4EQLPLFFSSEL,
PIPERX4EQLPNEWTXCOEFFORPRESET,
PIPERX4PHYSTATUS,
PIPERX4STARTBLOCK,
PIPERX4STATUS,
PIPERX4SYNCHEADER,
PIPERX4VALID,
PIPERX5CHARISK,
PIPERX5DATA,
PIPERX5DATAVALID,
PIPERX5ELECIDLE,
PIPERX5EQDONE,
PIPERX5EQLPADAPTDONE,
PIPERX5EQLPLFFSSEL,
PIPERX5EQLPNEWTXCOEFFORPRESET,
PIPERX5PHYSTATUS,
PIPERX5STARTBLOCK,
PIPERX5STATUS,
PIPERX5SYNCHEADER,
PIPERX5VALID,
PIPERX6CHARISK,
PIPERX6DATA,
PIPERX6DATAVALID,
PIPERX6ELECIDLE,
PIPERX6EQDONE,
PIPERX6EQLPADAPTDONE,
PIPERX6EQLPLFFSSEL,
PIPERX6EQLPNEWTXCOEFFORPRESET,
PIPERX6PHYSTATUS,
PIPERX6STARTBLOCK,
PIPERX6STATUS,
PIPERX6SYNCHEADER,
PIPERX6VALID,
PIPERX7CHARISK,
PIPERX7DATA,
PIPERX7DATAVALID,
PIPERX7ELECIDLE,
PIPERX7EQDONE,
PIPERX7EQLPADAPTDONE,
PIPERX7EQLPLFFSSEL,
PIPERX7EQLPNEWTXCOEFFORPRESET,
PIPERX7PHYSTATUS,
PIPERX7STARTBLOCK,
PIPERX7STATUS,
PIPERX7SYNCHEADER,
PIPERX7VALID,
PIPETX0EQCOEFF,
PIPETX0EQDONE,
PIPETX1EQCOEFF,
PIPETX1EQDONE,
PIPETX2EQCOEFF,
PIPETX2EQDONE,
PIPETX3EQCOEFF,
PIPETX3EQDONE,
PIPETX4EQCOEFF,
PIPETX4EQDONE,
PIPETX5EQCOEFF,
PIPETX5EQDONE,
PIPETX6EQCOEFF,
PIPETX6EQDONE,
PIPETX7EQCOEFF,
PIPETX7EQDONE,
PLDISABLESCRAMBLER,
PLEQRESETEIEOSCOUNT,
PLGEN3PCSDISABLE,
PLGEN3PCSRXSYNCDONE,
RECCLK,
RESETN,
SAXISCCTDATA,
SAXISCCTKEEP,
SAXISCCTLAST,
SAXISCCTUSER,
SAXISCCTVALID,
SAXISRQTDATA,
SAXISRQTKEEP,
SAXISRQTLAST,
SAXISRQTUSER,
SAXISRQTVALID,
USERCLK
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter ARI_CAP_ENABLE = "FALSE";
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1;
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE";
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
parameter [7:0] PF0_BIST_REGISTER = 8'h00;
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
parameter [15:0] PF0_DEVICE_ID = 16'h0000;
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
parameter [3:0] PF0_PB_CAP_VER = 4'h1;
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
parameter PF0_RBAR_CAP_ENABLE = "FALSE";
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0;
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
parameter [2:0] PF0_RBAR_NUM = 3'h1;
parameter [7:0] PF0_REVISION_ID = 8'h00;
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
parameter [7:0] PF1_BIST_REGISTER = 8'h00;
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
parameter [15:0] PF1_DEVICE_ID = 16'h0000;
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
parameter [3:0] PF1_PB_CAP_VER = 4'h1;
parameter [7:0] PF1_PM_CAP_ID = 8'h01;
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
parameter PF1_RBAR_CAP_ENABLE = "FALSE";
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0;
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
parameter [2:0] PF1_RBAR_NUM = 3'h1;
parameter [7:0] PF1_REVISION_ID = 8'h00;
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter PF1_TPHR_CAP_ENABLE = "FALSE";
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
parameter PL_DISABLE_SCRAMBLING = "FALSE";
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
parameter integer PL_N_FTS_GEN1 = 255;
parameter integer PL_N_FTS_GEN2 = 255;
parameter integer PL_N_FTS_GEN3 = 255;
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
parameter PL_UPSTREAM_FACING = "TRUE";
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
parameter SIM_VERSION = "1.0";
parameter integer SPARE_BIT0 = 0;
parameter integer SPARE_BIT1 = 0;
parameter integer SPARE_BIT2 = 0;
parameter integer SPARE_BIT3 = 0;
parameter integer SPARE_BIT4 = 0;
parameter integer SPARE_BIT5 = 0;
parameter integer SPARE_BIT6 = 0;
parameter integer SPARE_BIT7 = 0;
parameter integer SPARE_BIT8 = 0;
parameter [7:0] SPARE_BYTE0 = 8'h00;
parameter [7:0] SPARE_BYTE1 = 8'h00;
parameter [7:0] SPARE_BYTE2 = 8'h00;
parameter [7:0] SPARE_BYTE3 = 8'h00;
parameter [31:0] SPARE_WORD0 = 32'h00000000;
parameter [31:0] SPARE_WORD1 = 32'h00000000;
parameter [31:0] SPARE_WORD2 = 32'h00000000;
parameter [31:0] SPARE_WORD3 = 32'h00000000;
parameter SRIOV_CAP_ENABLE = "FALSE";
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000;
parameter [11:0] TL_CREDITS_CD = 12'h3E0;
parameter [7:0] TL_CREDITS_CH = 8'h20;
parameter [11:0] TL_CREDITS_NPD = 12'h028;
parameter [7:0] TL_CREDITS_NPH = 8'h20;
parameter [11:0] TL_CREDITS_PD = 12'h198;
parameter [7:0] TL_CREDITS_PH = 8'h20;
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
parameter TL_LEGACY_MODE_ENABLE = "FALSE";
parameter TL_PF_ENABLE_REG = "FALSE";
parameter TL_TAG_MGMT_ENABLE = "TRUE";
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF0_PM_CAP_ID = 8'h01;
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF0_TPHR_CAP_ENABLE = "FALSE";
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF1_PM_CAP_ID = 8'h01;
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF1_TPHR_CAP_ENABLE = "FALSE";
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF2_PM_CAP_ID = 8'h01;
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF2_TPHR_CAP_ENABLE = "FALSE";
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF3_PM_CAP_ID = 8'h01;
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF3_TPHR_CAP_ENABLE = "FALSE";
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF4_PM_CAP_ID = 8'h01;
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF4_TPHR_CAP_ENABLE = "FALSE";
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF5_PM_CAP_ID = 8'h01;
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF5_TPHR_CAP_ENABLE = "FALSE";
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CFGERRCOROUT;
output CFGERRFATALOUT;
output CFGERRNONFATALOUT;
output CFGEXTREADRECEIVED;
output CFGEXTWRITERECEIVED;
output CFGHOTRESETOUT;
output CFGINPUTUPDATEDONE;
output CFGINTERRUPTAOUTPUT;
output CFGINTERRUPTBOUTPUT;
output CFGINTERRUPTCOUTPUT;
output CFGINTERRUPTDOUTPUT;
output CFGINTERRUPTMSIFAIL;
output CFGINTERRUPTMSIMASKUPDATE;
output CFGINTERRUPTMSISENT;
output CFGINTERRUPTMSIXFAIL;
output CFGINTERRUPTMSIXSENT;
output CFGINTERRUPTSENT;
output CFGLOCALERROR;
output CFGLTRENABLE;
output CFGMCUPDATEDONE;
output CFGMGMTREADWRITEDONE;
output CFGMSGRECEIVED;
output CFGMSGTRANSMITDONE;
output CFGPERFUNCTIONUPDATEDONE;
output CFGPHYLINKDOWN;
output CFGPLSTATUSCHANGE;
output CFGPOWERSTATECHANGEINTERRUPT;
output CFGTPHSTTREADENABLE;
output CFGTPHSTTWRITEENABLE;
output DRPRDY;
output MAXISCQTLAST;
output MAXISCQTVALID;
output MAXISRCTLAST;
output MAXISRCTVALID;
output PCIERQSEQNUMVLD;
output PCIERQTAGVLD;
output PIPERX0POLARITY;
output PIPERX1POLARITY;
output PIPERX2POLARITY;
output PIPERX3POLARITY;
output PIPERX4POLARITY;
output PIPERX5POLARITY;
output PIPERX6POLARITY;
output PIPERX7POLARITY;
output PIPETX0COMPLIANCE;
output PIPETX0DATAVALID;
output PIPETX0ELECIDLE;
output PIPETX0STARTBLOCK;
output PIPETX1COMPLIANCE;
output PIPETX1DATAVALID;
output PIPETX1ELECIDLE;
output PIPETX1STARTBLOCK;
output PIPETX2COMPLIANCE;
output PIPETX2DATAVALID;
output PIPETX2ELECIDLE;
output PIPETX2STARTBLOCK;
output PIPETX3COMPLIANCE;
output PIPETX3DATAVALID;
output PIPETX3ELECIDLE;
output PIPETX3STARTBLOCK;
output PIPETX4COMPLIANCE;
output PIPETX4DATAVALID;
output PIPETX4ELECIDLE;
output PIPETX4STARTBLOCK;
output PIPETX5COMPLIANCE;
output PIPETX5DATAVALID;
output PIPETX5ELECIDLE;
output PIPETX5STARTBLOCK;
output PIPETX6COMPLIANCE;
output PIPETX6DATAVALID;
output PIPETX6ELECIDLE;
output PIPETX6STARTBLOCK;
output PIPETX7COMPLIANCE;
output PIPETX7DATAVALID;
output PIPETX7ELECIDLE;
output PIPETX7STARTBLOCK;
output PIPETXDEEMPH;
output PIPETXRCVRDET;
output PIPETXRESET;
output PIPETXSWING;
output PLEQINPROGRESS;
output [11:0] CFGFCCPLD;
output [11:0] CFGFCNPD;
output [11:0] CFGFCPD;
output [11:0] CFGVFSTATUS;
output [143:0] MIREPLAYRAMWRITEDATA;
output [143:0] MIREQUESTRAMWRITEDATA;
output [15:0] CFGPERFUNCSTATUSDATA;
output [15:0] DBGDATAOUT;
output [15:0] DRPDO;
output [17:0] CFGVFPOWERSTATE;
output [17:0] CFGVFTPHSTMODE;
output [1:0] CFGDPASUBSTATECHANGE;
output [1:0] CFGFLRINPROCESS;
output [1:0] CFGINTERRUPTMSIENABLE;
output [1:0] CFGINTERRUPTMSIXENABLE;
output [1:0] CFGINTERRUPTMSIXMASK;
output [1:0] CFGLINKPOWERSTATE;
output [1:0] CFGOBFFENABLE;
output [1:0] CFGPHYLINKSTATUS;
output [1:0] CFGRCBSTATUS;
output [1:0] CFGTPHREQUESTERENABLE;
output [1:0] MIREPLAYRAMREADENABLE;
output [1:0] MIREPLAYRAMWRITEENABLE;
output [1:0] PCIERQTAGAV;
output [1:0] PCIETFCNPDAV;
output [1:0] PCIETFCNPHAV;
output [1:0] PIPERX0EQCONTROL;
output [1:0] PIPERX1EQCONTROL;
output [1:0] PIPERX2EQCONTROL;
output [1:0] PIPERX3EQCONTROL;
output [1:0] PIPERX4EQCONTROL;
output [1:0] PIPERX5EQCONTROL;
output [1:0] PIPERX6EQCONTROL;
output [1:0] PIPERX7EQCONTROL;
output [1:0] PIPETX0CHARISK;
output [1:0] PIPETX0EQCONTROL;
output [1:0] PIPETX0POWERDOWN;
output [1:0] PIPETX0SYNCHEADER;
output [1:0] PIPETX1CHARISK;
output [1:0] PIPETX1EQCONTROL;
output [1:0] PIPETX1POWERDOWN;
output [1:0] PIPETX1SYNCHEADER;
output [1:0] PIPETX2CHARISK;
output [1:0] PIPETX2EQCONTROL;
output [1:0] PIPETX2POWERDOWN;
output [1:0] PIPETX2SYNCHEADER;
output [1:0] PIPETX3CHARISK;
output [1:0] PIPETX3EQCONTROL;
output [1:0] PIPETX3POWERDOWN;
output [1:0] PIPETX3SYNCHEADER;
output [1:0] PIPETX4CHARISK;
output [1:0] PIPETX4EQCONTROL;
output [1:0] PIPETX4POWERDOWN;
output [1:0] PIPETX4SYNCHEADER;
output [1:0] PIPETX5CHARISK;
output [1:0] PIPETX5EQCONTROL;
output [1:0] PIPETX5POWERDOWN;
output [1:0] PIPETX5SYNCHEADER;
output [1:0] PIPETX6CHARISK;
output [1:0] PIPETX6EQCONTROL;
output [1:0] PIPETX6POWERDOWN;
output [1:0] PIPETX6SYNCHEADER;
output [1:0] PIPETX7CHARISK;
output [1:0] PIPETX7EQCONTROL;
output [1:0] PIPETX7POWERDOWN;
output [1:0] PIPETX7SYNCHEADER;
output [1:0] PIPETXRATE;
output [1:0] PLEQPHASE;
output [255:0] MAXISCQTDATA;
output [255:0] MAXISRCTDATA;
output [2:0] CFGCURRENTSPEED;
output [2:0] CFGMAXPAYLOAD;
output [2:0] CFGMAXREADREQ;
output [2:0] CFGTPHFUNCTIONNUM;
output [2:0] PIPERX0EQPRESET;
output [2:0] PIPERX1EQPRESET;
output [2:0] PIPERX2EQPRESET;
output [2:0] PIPERX3EQPRESET;
output [2:0] PIPERX4EQPRESET;
output [2:0] PIPERX5EQPRESET;
output [2:0] PIPERX6EQPRESET;
output [2:0] PIPERX7EQPRESET;
output [2:0] PIPETXMARGIN;
output [31:0] CFGEXTWRITEDATA;
output [31:0] CFGINTERRUPTMSIDATA;
output [31:0] CFGMGMTREADDATA;
output [31:0] CFGTPHSTTWRITEDATA;
output [31:0] PIPETX0DATA;
output [31:0] PIPETX1DATA;
output [31:0] PIPETX2DATA;
output [31:0] PIPETX3DATA;
output [31:0] PIPETX4DATA;
output [31:0] PIPETX5DATA;
output [31:0] PIPETX6DATA;
output [31:0] PIPETX7DATA;
output [3:0] CFGEXTWRITEBYTEENABLE;
output [3:0] CFGNEGOTIATEDWIDTH;
output [3:0] CFGTPHSTTWRITEBYTEVALID;
output [3:0] MICOMPLETIONRAMREADENABLEL;
output [3:0] MICOMPLETIONRAMREADENABLEU;
output [3:0] MICOMPLETIONRAMWRITEENABLEL;
output [3:0] MICOMPLETIONRAMWRITEENABLEU;
output [3:0] MIREQUESTRAMREADENABLE;
output [3:0] MIREQUESTRAMWRITEENABLE;
output [3:0] PCIERQSEQNUM;
output [3:0] PIPERX0EQLPTXPRESET;
output [3:0] PIPERX1EQLPTXPRESET;
output [3:0] PIPERX2EQLPTXPRESET;
output [3:0] PIPERX3EQLPTXPRESET;
output [3:0] PIPERX4EQLPTXPRESET;
output [3:0] PIPERX5EQLPTXPRESET;
output [3:0] PIPERX6EQLPTXPRESET;
output [3:0] PIPERX7EQLPTXPRESET;
output [3:0] PIPETX0EQPRESET;
output [3:0] PIPETX1EQPRESET;
output [3:0] PIPETX2EQPRESET;
output [3:0] PIPETX3EQPRESET;
output [3:0] PIPETX4EQPRESET;
output [3:0] PIPETX5EQPRESET;
output [3:0] PIPETX6EQPRESET;
output [3:0] PIPETX7EQPRESET;
output [3:0] SAXISCCTREADY;
output [3:0] SAXISRQTREADY;
output [4:0] CFGMSGRECEIVEDTYPE;
output [4:0] CFGTPHSTTADDRESS;
output [5:0] CFGFUNCTIONPOWERSTATE;
output [5:0] CFGINTERRUPTMSIMMENABLE;
output [5:0] CFGINTERRUPTMSIVFENABLE;
output [5:0] CFGINTERRUPTMSIXVFENABLE;
output [5:0] CFGINTERRUPTMSIXVFMASK;
output [5:0] CFGLTSSMSTATE;
output [5:0] CFGTPHSTMODE;
output [5:0] CFGVFFLRINPROCESS;
output [5:0] CFGVFTPHREQUESTERENABLE;
output [5:0] PCIECQNPREQCOUNT;
output [5:0] PCIERQTAG;
output [5:0] PIPERX0EQLPLFFS;
output [5:0] PIPERX1EQLPLFFS;
output [5:0] PIPERX2EQLPLFFS;
output [5:0] PIPERX3EQLPLFFS;
output [5:0] PIPERX4EQLPLFFS;
output [5:0] PIPERX5EQLPLFFS;
output [5:0] PIPERX6EQLPLFFS;
output [5:0] PIPERX7EQLPLFFS;
output [5:0] PIPETX0EQDEEMPH;
output [5:0] PIPETX1EQDEEMPH;
output [5:0] PIPETX2EQDEEMPH;
output [5:0] PIPETX3EQDEEMPH;
output [5:0] PIPETX4EQDEEMPH;
output [5:0] PIPETX5EQDEEMPH;
output [5:0] PIPETX6EQDEEMPH;
output [5:0] PIPETX7EQDEEMPH;
output [71:0] MICOMPLETIONRAMWRITEDATAL;
output [71:0] MICOMPLETIONRAMWRITEDATAU;
output [74:0] MAXISRCTUSER;
output [7:0] CFGEXTFUNCTIONNUMBER;
output [7:0] CFGFCCPLH;
output [7:0] CFGFCNPH;
output [7:0] CFGFCPH;
output [7:0] CFGFUNCTIONSTATUS;
output [7:0] CFGMSGRECEIVEDDATA;
output [7:0] MAXISCQTKEEP;
output [7:0] MAXISRCTKEEP;
output [7:0] PLGEN3PCSRXSLIDE;
output [84:0] MAXISCQTUSER;
output [8:0] MIREPLAYRAMADDRESS;
output [8:0] MIREQUESTRAMREADADDRESSA;
output [8:0] MIREQUESTRAMREADADDRESSB;
output [8:0] MIREQUESTRAMWRITEADDRESSA;
output [8:0] MIREQUESTRAMWRITEADDRESSB;
output [9:0] CFGEXTREGISTERNUMBER;
output [9:0] MICOMPLETIONRAMREADADDRESSAL;
output [9:0] MICOMPLETIONRAMREADADDRESSAU;
output [9:0] MICOMPLETIONRAMREADADDRESSBL;
output [9:0] MICOMPLETIONRAMREADADDRESSBU;
output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
input CFGCONFIGSPACEENABLE;
input CFGERRCORIN;
input CFGERRUNCORIN;
input CFGEXTREADDATAVALID;
input CFGHOTRESETIN;
input CFGINPUTUPDATEREQUEST;
input CFGINTERRUPTMSITPHPRESENT;
input CFGINTERRUPTMSIXINT;
input CFGLINKTRAININGENABLE;
input CFGMCUPDATEREQUEST;
input CFGMGMTREAD;
input CFGMGMTTYPE1CFGREGACCESS;
input CFGMGMTWRITE;
input CFGMSGTRANSMIT;
input CFGPERFUNCTIONOUTPUTREQUEST;
input CFGPOWERSTATECHANGEACK;
input CFGREQPMTRANSITIONL23READY;
input CFGTPHSTTREADDATAVALID;
input CORECLK;
input CORECLKMICOMPLETIONRAML;
input CORECLKMICOMPLETIONRAMU;
input CORECLKMIREPLAYRAM;
input CORECLKMIREQUESTRAM;
input DRPCLK;
input DRPEN;
input DRPWE;
input MGMTRESETN;
input MGMTSTICKYRESETN;
input PCIECQNPREQ;
input PIPECLK;
input PIPERESETN;
input PIPERX0DATAVALID;
input PIPERX0ELECIDLE;
input PIPERX0EQDONE;
input PIPERX0EQLPADAPTDONE;
input PIPERX0EQLPLFFSSEL;
input PIPERX0PHYSTATUS;
input PIPERX0STARTBLOCK;
input PIPERX0VALID;
input PIPERX1DATAVALID;
input PIPERX1ELECIDLE;
input PIPERX1EQDONE;
input PIPERX1EQLPADAPTDONE;
input PIPERX1EQLPLFFSSEL;
input PIPERX1PHYSTATUS;
input PIPERX1STARTBLOCK;
input PIPERX1VALID;
input PIPERX2DATAVALID;
input PIPERX2ELECIDLE;
input PIPERX2EQDONE;
input PIPERX2EQLPADAPTDONE;
input PIPERX2EQLPLFFSSEL;
input PIPERX2PHYSTATUS;
input PIPERX2STARTBLOCK;
input PIPERX2VALID;
input PIPERX3DATAVALID;
input PIPERX3ELECIDLE;
input PIPERX3EQDONE;
input PIPERX3EQLPADAPTDONE;
input PIPERX3EQLPLFFSSEL;
input PIPERX3PHYSTATUS;
input PIPERX3STARTBLOCK;
input PIPERX3VALID;
input PIPERX4DATAVALID;
input PIPERX4ELECIDLE;
input PIPERX4EQDONE;
input PIPERX4EQLPADAPTDONE;
input PIPERX4EQLPLFFSSEL;
input PIPERX4PHYSTATUS;
input PIPERX4STARTBLOCK;
input PIPERX4VALID;
input PIPERX5DATAVALID;
input PIPERX5ELECIDLE;
input PIPERX5EQDONE;
input PIPERX5EQLPADAPTDONE;
input PIPERX5EQLPLFFSSEL;
input PIPERX5PHYSTATUS;
input PIPERX5STARTBLOCK;
input PIPERX5VALID;
input PIPERX6DATAVALID;
input PIPERX6ELECIDLE;
input PIPERX6EQDONE;
input PIPERX6EQLPADAPTDONE;
input PIPERX6EQLPLFFSSEL;
input PIPERX6PHYSTATUS;
input PIPERX6STARTBLOCK;
input PIPERX6VALID;
input PIPERX7DATAVALID;
input PIPERX7ELECIDLE;
input PIPERX7EQDONE;
input PIPERX7EQLPADAPTDONE;
input PIPERX7EQLPLFFSSEL;
input PIPERX7PHYSTATUS;
input PIPERX7STARTBLOCK;
input PIPERX7VALID;
input PIPETX0EQDONE;
input PIPETX1EQDONE;
input PIPETX2EQDONE;
input PIPETX3EQDONE;
input PIPETX4EQDONE;
input PIPETX5EQDONE;
input PIPETX6EQDONE;
input PIPETX7EQDONE;
input PLDISABLESCRAMBLER;
input PLEQRESETEIEOSCOUNT;
input PLGEN3PCSDISABLE;
input RECCLK;
input RESETN;
input SAXISCCTLAST;
input SAXISCCTVALID;
input SAXISRQTLAST;
input SAXISRQTVALID;
input USERCLK;
input [10:0] DRPADDR;
input [143:0] MICOMPLETIONRAMREADDATA;
input [143:0] MIREPLAYRAMREADDATA;
input [143:0] MIREQUESTRAMREADDATA;
input [15:0] CFGDEVID;
input [15:0] CFGSUBSYSID;
input [15:0] CFGSUBSYSVENDID;
input [15:0] CFGVENDID;
input [15:0] DRPDI;
input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPETX0EQCOEFF;
input [17:0] PIPETX1EQCOEFF;
input [17:0] PIPETX2EQCOEFF;
input [17:0] PIPETX3EQCOEFF;
input [17:0] PIPETX4EQCOEFF;
input [17:0] PIPETX5EQCOEFF;
input [17:0] PIPETX6EQCOEFF;
input [17:0] PIPETX7EQCOEFF;
input [18:0] CFGMGMTADDR;
input [1:0] CFGFLRDONE;
input [1:0] CFGINTERRUPTMSITPHTYPE;
input [1:0] CFGINTERRUPTPENDING;
input [1:0] PIPERX0CHARISK;
input [1:0] PIPERX0SYNCHEADER;
input [1:0] PIPERX1CHARISK;
input [1:0] PIPERX1SYNCHEADER;
input [1:0] PIPERX2CHARISK;
input [1:0] PIPERX2SYNCHEADER;
input [1:0] PIPERX3CHARISK;
input [1:0] PIPERX3SYNCHEADER;
input [1:0] PIPERX4CHARISK;
input [1:0] PIPERX4SYNCHEADER;
input [1:0] PIPERX5CHARISK;
input [1:0] PIPERX5SYNCHEADER;
input [1:0] PIPERX6CHARISK;
input [1:0] PIPERX6SYNCHEADER;
input [1:0] PIPERX7CHARISK;
input [1:0] PIPERX7SYNCHEADER;
input [21:0] MAXISCQTREADY;
input [21:0] MAXISRCTREADY;
input [255:0] SAXISCCTDATA;
input [255:0] SAXISRQTDATA;
input [2:0] CFGDSFUNCTIONNUMBER;
input [2:0] CFGFCSEL;
input [2:0] CFGINTERRUPTMSIATTR;
input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
input [2:0] CFGMSGTRANSMITTYPE;
input [2:0] CFGPERFUNCSTATUSCONTROL;
input [2:0] CFGPERFUNCTIONNUMBER;
input [2:0] PIPERX0STATUS;
input [2:0] PIPERX1STATUS;
input [2:0] PIPERX2STATUS;
input [2:0] PIPERX3STATUS;
input [2:0] PIPERX4STATUS;
input [2:0] PIPERX5STATUS;
input [2:0] PIPERX6STATUS;
input [2:0] PIPERX7STATUS;
input [31:0] CFGEXTREADDATA;
input [31:0] CFGINTERRUPTMSIINT;
input [31:0] CFGINTERRUPTMSIXDATA;
input [31:0] CFGMGMTWRITEDATA;
input [31:0] CFGMSGTRANSMITDATA;
input [31:0] CFGTPHSTTREADDATA;
input [31:0] PIPERX0DATA;
input [31:0] PIPERX1DATA;
input [31:0] PIPERX2DATA;
input [31:0] PIPERX3DATA;
input [31:0] PIPERX4DATA;
input [31:0] PIPERX5DATA;
input [31:0] PIPERX6DATA;
input [31:0] PIPERX7DATA;
input [32:0] SAXISCCTUSER;
input [3:0] CFGINTERRUPTINT;
input [3:0] CFGINTERRUPTMSISELECT;
input [3:0] CFGMGMTBYTEENABLE;
input [4:0] CFGDSDEVICENUMBER;
input [59:0] SAXISRQTUSER;
input [5:0] CFGVFFLRDONE;
input [5:0] PIPEEQFS;
input [5:0] PIPEEQLF;
input [63:0] CFGDSN;
input [63:0] CFGINTERRUPTMSIPENDINGSTATUS;
input [63:0] CFGINTERRUPTMSIXADDRESS;
input [7:0] CFGDSBUSNUMBER;
input [7:0] CFGDSPORTNUMBER;
input [7:0] CFGREVID;
input [7:0] PLGEN3PCSRXSYNCDONE;
input [7:0] SAXISCCTKEEP;
input [7:0] SAXISRQTKEEP;
input [8:0] CFGINTERRUPTMSITPHSTTAG;
reg SIM_VERSION_BINARY;
reg [0:0] ARI_CAP_ENABLE_BINARY;
reg [0:0] AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_CC_PARITY_CHK_BINARY;
reg [0:0] AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY;
reg [0:0] AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY;
reg [0:0] AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_RC_STRADDLE_BINARY;
reg [0:0] AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_RQ_PARITY_CHK_BINARY;
reg [0:0] CRM_CORE_CLK_FREQ_500_BINARY;
reg [0:0] GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY;
reg [0:0] LL_ACK_TIMEOUT_EN_BINARY;
reg [0:0] LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY;
reg [0:0] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY;
reg [0:0] LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY;
reg [0:0] PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY;
reg [0:0] PF0_DEV_CAP2_LTR_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY;
reg [0:0] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY;
reg [0:0] PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY;
reg [0:0] PF0_EXPANSION_ROM_ENABLE_BINARY;
reg [0:0] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY;
reg [0:0] PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D0_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D1_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY;
reg [0:0] PF0_PM_CAP_SUPP_D1_STATE_BINARY;
reg [0:0] PF0_PM_CSR_NOSOFTRESET_BINARY;
reg [0:0] PF0_RBAR_CAP_ENABLE_BINARY;
reg [0:0] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] PF0_TPHR_CAP_ENABLE_BINARY;
reg [0:0] PF0_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY;
reg [0:0] PF1_EXPANSION_ROM_ENABLE_BINARY;
reg [0:0] PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY;
reg [0:0] PF1_RBAR_CAP_ENABLE_BINARY;
reg [0:0] PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] PF1_TPHR_CAP_ENABLE_BINARY;
reg [0:0] PF1_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] PL_DISABLE_EI_INFER_IN_L0_BINARY;
reg [0:0] PL_DISABLE_GEN3_DC_BALANCE_BINARY;
reg [0:0] PL_DISABLE_SCRAMBLING_BINARY;
reg [0:0] PL_DISABLE_UPCONFIG_CAPABLE_BINARY;
reg [0:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY;
reg [0:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY;
reg [0:0] PL_EQ_BYPASS_PHASE23_BINARY;
reg [0:0] PL_EQ_SHORT_ADAPT_PHASE_BINARY;
reg [0:0] PL_SIM_FAST_LINK_TRAINING_BINARY;
reg [0:0] PL_UPSTREAM_FACING_BINARY;
reg [0:0] PM_ENABLE_SLOT_POWER_CAPTURE_BINARY;
reg [0:0] SPARE_BIT0_BINARY;
reg [0:0] SPARE_BIT1_BINARY;
reg [0:0] SPARE_BIT2_BINARY;
reg [0:0] SPARE_BIT3_BINARY;
reg [0:0] SPARE_BIT4_BINARY;
reg [0:0] SPARE_BIT5_BINARY;
reg [0:0] SPARE_BIT6_BINARY;
reg [0:0] SPARE_BIT7_BINARY;
reg [0:0] SPARE_BIT8_BINARY;
reg [0:0] SRIOV_CAP_ENABLE_BINARY;
reg [0:0] TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY;
reg [0:0] TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY;
reg [0:0] TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY;
reg [0:0] TL_LEGACY_MODE_ENABLE_BINARY;
reg [0:0] TL_PF_ENABLE_REG_BINARY;
reg [0:0] TL_TAG_MGMT_ENABLE_BINARY;
reg [0:0] VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF0_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF0_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF1_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF1_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF2_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF2_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF3_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF3_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF4_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF4_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF5_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF5_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY;
reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY;
reg [1:0] PF0_LINK_CAP_ASPM_SUPPORT_BINARY;
reg [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY;
reg [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY;
reg [2:0] PF0_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] PF0_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] PF0_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] PF1_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] PF1_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] PF1_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF0_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF0_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF0_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF1_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF1_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF1_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF2_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF2_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF2_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF3_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF3_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF3_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF4_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF4_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF4_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF5_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF5_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF5_MSI_CAP_MULTIMSGCAP_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN1_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN2_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN3_BINARY;
reg [7:0] PL_N_FTS_GEN1_BINARY;
reg [7:0] PL_N_FTS_GEN2_BINARY;
reg [7:0] PL_N_FTS_GEN3_BINARY;
reg notifier;
initial begin
case (ARI_CAP_ENABLE)
"FALSE" : ARI_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : ARI_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ARI_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ARI_CAP_ENABLE);
$finish;
end
endcase
case (AXISTEN_IF_CC_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CC_ALIGNMENT_MODE);
$finish;
end
endcase
case (AXISTEN_IF_CC_PARITY_CHK)
"TRUE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b1;
"FALSE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_CC_PARITY_CHK);
$finish;
end
endcase
case (AXISTEN_IF_CQ_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CQ_ALIGNMENT_MODE);
$finish;
end
endcase
case (AXISTEN_IF_ENABLE_CLIENT_TAG)
"FALSE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_CLIENT_TAG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_CLIENT_TAG);
$finish;
end
endcase
case (AXISTEN_IF_ENABLE_RX_MSG_INTFC)
"FALSE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_RX_MSG_INTFC on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_RX_MSG_INTFC);
$finish;
end
endcase
case (AXISTEN_IF_RC_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_ALIGNMENT_MODE);
$finish;
end
endcase
case (AXISTEN_IF_RC_STRADDLE)
"FALSE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_STRADDLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_STRADDLE);
$finish;
end
endcase
case (AXISTEN_IF_RQ_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RQ_ALIGNMENT_MODE);
$finish;
end
endcase
case (AXISTEN_IF_RQ_PARITY_CHK)
"TRUE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b1;
"FALSE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_RQ_PARITY_CHK);
$finish;
end
endcase
case (CRM_CORE_CLK_FREQ_500)
"TRUE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b1;
"FALSE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CRM_CORE_CLK_FREQ_500 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CRM_CORE_CLK_FREQ_500);
$finish;
end
endcase
case (GEN3_PCS_RX_ELECIDLE_INTERNAL)
"TRUE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b1;
"FALSE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute GEN3_PCS_RX_ELECIDLE_INTERNAL on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", GEN3_PCS_RX_ELECIDLE_INTERNAL);
$finish;
end
endcase
case (LL_ACK_TIMEOUT_EN)
"FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN);
$finish;
end
endcase
case (LL_CPL_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_CPL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_CPL_FC_UPDATE_TIMER_OVERRIDE);
$finish;
end
endcase
case (LL_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_FC_UPDATE_TIMER_OVERRIDE);
$finish;
end
endcase
case (LL_NP_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_NP_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_NP_FC_UPDATE_TIMER_OVERRIDE);
$finish;
end
endcase
case (LL_P_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_P_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_P_FC_UPDATE_TIMER_OVERRIDE);
$finish;
end
endcase
case (LL_REPLAY_TIMEOUT_EN)
"FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN);
$finish;
end
endcase
case (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE)
"FALSE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b0;
"TRUE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE);
$finish;
end
endcase
case (LTR_TX_MESSAGE_ON_LTR_ENABLE)
"FALSE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b0;
"TRUE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_LTR_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_LTR_ENABLE);
$finish;
end
endcase
case (PF0_AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_CHECK_CAPABLE);
$finish;
end
endcase
case (PF0_AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_GEN_CAPABLE);
$finish;
end
endcase
case (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT);
$finish;
end
endcase
case (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT);
$finish;
end
endcase
case (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT);
$finish;
end
endcase
case (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE)
"TRUE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE);
$finish;
end
endcase
case (PF0_DEV_CAP2_LTR_SUPPORT)
"TRUE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_LTR_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_LTR_SUPPORT);
$finish;
end
endcase
case (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT)
"FALSE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b0;
"TRUE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT);
$finish;
end
endcase
case (PF0_DEV_CAP_EXT_TAG_SUPPORTED)
"TRUE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_EXT_TAG_SUPPORTED);
$finish;
end
endcase
case (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE)
"TRUE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE);
$finish;
end
endcase
case (PF0_DPA_CAP_SUB_STATE_CONTROL_EN)
"TRUE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1;
"FALSE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DPA_CAP_SUB_STATE_CONTROL_EN);
$finish;
end
endcase
case (PF0_EXPANSION_ROM_ENABLE)
"FALSE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_EXPANSION_ROM_ENABLE);
$finish;
end
endcase
case (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG)
"TRUE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1;
"FALSE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_LINK_STATUS_SLOT_CLOCK_CONFIG);
$finish;
end
endcase
case (PF0_PB_CAP_SYSTEM_ALLOCATED)
"FALSE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0;
"TRUE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_PB_CAP_SYSTEM_ALLOCATED);
$finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D0)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D0);
$finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D1)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D1 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D1);
$finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D3HOT)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D3HOT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D3HOT);
$finish;
end
endcase
case (PF0_PM_CAP_SUPP_D1_STATE)
"TRUE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_SUPP_D1_STATE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_SUPP_D1_STATE);
$finish;
end
endcase
case (PF0_PM_CSR_NOSOFTRESET)
"TRUE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b1;
"FALSE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CSR_NOSOFTRESET on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CSR_NOSOFTRESET);
$finish;
end
endcase
case (PF0_RBAR_CAP_ENABLE)
"FALSE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_RBAR_CAP_ENABLE);
$finish;
end
endcase
case (PF0_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (PF0_TPHR_CAP_ENABLE)
"FALSE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (PF0_TPHR_CAP_INT_VEC_MODE)
"TRUE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (PF1_AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_CHECK_CAPABLE);
$finish;
end
endcase
case (PF1_AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_GEN_CAPABLE);
$finish;
end
endcase
case (PF1_DPA_CAP_SUB_STATE_CONTROL_EN)
"TRUE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1;
"FALSE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_DPA_CAP_SUB_STATE_CONTROL_EN);
$finish;
end
endcase
case (PF1_EXPANSION_ROM_ENABLE)
"FALSE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_EXPANSION_ROM_ENABLE);
$finish;
end
endcase
case (PF1_PB_CAP_SYSTEM_ALLOCATED)
"FALSE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0;
"TRUE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_PB_CAP_SYSTEM_ALLOCATED);
$finish;
end
endcase
case (PF1_RBAR_CAP_ENABLE)
"FALSE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_RBAR_CAP_ENABLE);
$finish;
end
endcase
case (PF1_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (PF1_TPHR_CAP_ENABLE)
"FALSE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (PF1_TPHR_CAP_INT_VEC_MODE)
"TRUE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (PL_DISABLE_EI_INFER_IN_L0)
"FALSE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b0;
"TRUE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_EI_INFER_IN_L0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_EI_INFER_IN_L0);
$finish;
end
endcase
case (PL_DISABLE_GEN3_DC_BALANCE)
"FALSE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b0;
"TRUE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_GEN3_DC_BALANCE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_GEN3_DC_BALANCE);
$finish;
end
endcase
case (PL_DISABLE_SCRAMBLING)
"FALSE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b0;
"TRUE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_SCRAMBLING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_SCRAMBLING);
$finish;
end
endcase
case (PL_DISABLE_UPCONFIG_CAPABLE)
"FALSE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b0;
"TRUE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_UPCONFIG_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_UPCONFIG_CAPABLE);
$finish;
end
endcase
case (PL_EQ_ADAPT_DISABLE_COEFF_CHECK)
"FALSE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b0;
"TRUE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_COEFF_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_COEFF_CHECK);
$finish;
end
endcase
case (PL_EQ_ADAPT_DISABLE_PRESET_CHECK)
"FALSE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b0;
"TRUE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_PRESET_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_PRESET_CHECK);
$finish;
end
endcase
case (PL_EQ_BYPASS_PHASE23)
"FALSE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b0;
"TRUE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_BYPASS_PHASE23 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_BYPASS_PHASE23);
$finish;
end
endcase
case (PL_EQ_SHORT_ADAPT_PHASE)
"FALSE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b0;
"TRUE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_SHORT_ADAPT_PHASE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_SHORT_ADAPT_PHASE);
$finish;
end
endcase
case (PL_SIM_FAST_LINK_TRAINING)
"FALSE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b0;
"TRUE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_SIM_FAST_LINK_TRAINING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_SIM_FAST_LINK_TRAINING);
$finish;
end
endcase
case (PL_UPSTREAM_FACING)
"TRUE" : PL_UPSTREAM_FACING_BINARY = 1'b1;
"FALSE" : PL_UPSTREAM_FACING_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PL_UPSTREAM_FACING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PL_UPSTREAM_FACING);
$finish;
end
endcase
case (PM_ENABLE_SLOT_POWER_CAPTURE)
"TRUE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b1;
"FALSE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ENABLE_SLOT_POWER_CAPTURE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_ENABLE_SLOT_POWER_CAPTURE);
$finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"1.2" : SIM_VERSION_BINARY = 0;
"1.3" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION);
$finish;
end
endcase
case (SRIOV_CAP_ENABLE)
"FALSE" : SRIOV_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : SRIOV_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SRIOV_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SRIOV_CAP_ENABLE);
$finish;
end
endcase
case (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE)
"TRUE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b1;
"FALSE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TL_ENABLE_MESSAGE_RID_CHECK_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_ENABLE_MESSAGE_RID_CHECK_ENABLE);
$finish;
end
endcase
case (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE)
"FALSE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE);
$finish;
end
endcase
case (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE)
"FALSE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE);
$finish;
end
endcase
case (TL_LEGACY_MODE_ENABLE)
"FALSE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_LEGACY_MODE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_MODE_ENABLE);
$finish;
end
endcase
case (TL_PF_ENABLE_REG)
"FALSE" : TL_PF_ENABLE_REG_BINARY = 1'b0;
"TRUE" : TL_PF_ENABLE_REG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_PF_ENABLE_REG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_PF_ENABLE_REG);
$finish;
end
endcase
case (TL_TAG_MGMT_ENABLE)
"TRUE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b1;
"FALSE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TAG_MGMT_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_TAG_MGMT_ENABLE);
$finish;
end
endcase
case (VF0_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF0_TPHR_CAP_ENABLE)
"FALSE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF0_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF0_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (VF1_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF1_TPHR_CAP_ENABLE)
"FALSE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF1_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF1_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (VF2_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF2_TPHR_CAP_ENABLE)
"FALSE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF2_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF2_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (VF3_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF3_TPHR_CAP_ENABLE)
"FALSE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF3_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF3_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (VF4_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF4_TPHR_CAP_ENABLE)
"FALSE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF4_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF4_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
case (VF5_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_DEV_SPECIFIC_MODE);
$finish;
end
endcase
case (VF5_TPHR_CAP_ENABLE)
"FALSE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF5_TPHR_CAP_ENABLE);
$finish;
end
endcase
case (VF5_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_INT_VEC_MODE);
$finish;
end
endcase
if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3))
LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC);
$finish;
end
if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3))
LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC);
$finish;
end
if ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY <= 7))
PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L0S_LATENCY);
$finish;
end
if ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L1_LATENCY <= 7))
PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L1_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L1_LATENCY);
$finish;
end
if ((PF0_LINK_CAP_ASPM_SUPPORT >= 0) && (PF0_LINK_CAP_ASPM_SUPPORT <= 3))
PF0_LINK_CAP_ASPM_SUPPORT_BINARY = PF0_LINK_CAP_ASPM_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_ASPM_SUPPORT on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PF0_LINK_CAP_ASPM_SUPPORT);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2);
$finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2);
$finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3);
$finish;
end
if ((PF0_MSIX_CAP_PBA_BIR >= 0) && (PF0_MSIX_CAP_PBA_BIR <= 7))
PF0_MSIX_CAP_PBA_BIR_BINARY = PF0_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_PBA_BIR);
$finish;
end
if ((PF0_MSIX_CAP_TABLE_BIR >= 0) && (PF0_MSIX_CAP_TABLE_BIR <= 7))
PF0_MSIX_CAP_TABLE_BIR_BINARY = PF0_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((PF0_MSI_CAP_MULTIMSGCAP >= 0) && (PF0_MSI_CAP_MULTIMSGCAP <= 7))
PF0_MSI_CAP_MULTIMSGCAP_BINARY = PF0_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((PF1_MSIX_CAP_PBA_BIR >= 0) && (PF1_MSIX_CAP_PBA_BIR <= 7))
PF1_MSIX_CAP_PBA_BIR_BINARY = PF1_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_PBA_BIR);
$finish;
end
if ((PF1_MSIX_CAP_TABLE_BIR >= 0) && (PF1_MSIX_CAP_TABLE_BIR <= 7))
PF1_MSIX_CAP_TABLE_BIR_BINARY = PF1_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((PF1_MSI_CAP_MULTIMSGCAP >= 0) && (PF1_MSI_CAP_MULTIMSGCAP <= 7))
PF1_MSI_CAP_MULTIMSGCAP_BINARY = PF1_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((PL_N_FTS_COMCLK_GEN1 >= 0) && (PL_N_FTS_COMCLK_GEN1 <= 255))
PL_N_FTS_COMCLK_GEN1_BINARY = PL_N_FTS_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN1);
$finish;
end
if ((PL_N_FTS_COMCLK_GEN2 >= 0) && (PL_N_FTS_COMCLK_GEN2 <= 255))
PL_N_FTS_COMCLK_GEN2_BINARY = PL_N_FTS_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN2);
$finish;
end
if ((PL_N_FTS_COMCLK_GEN3 >= 0) && (PL_N_FTS_COMCLK_GEN3 <= 255))
PL_N_FTS_COMCLK_GEN3_BINARY = PL_N_FTS_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN3);
$finish;
end
if ((PL_N_FTS_GEN1 >= 0) && (PL_N_FTS_GEN1 <= 255))
PL_N_FTS_GEN1_BINARY = PL_N_FTS_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN1);
$finish;
end
if ((PL_N_FTS_GEN2 >= 0) && (PL_N_FTS_GEN2 <= 255))
PL_N_FTS_GEN2_BINARY = PL_N_FTS_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN2);
$finish;
end
if ((PL_N_FTS_GEN3 >= 0) && (PL_N_FTS_GEN3 <= 255))
PL_N_FTS_GEN3_BINARY = PL_N_FTS_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN3);
$finish;
end
if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1))
SPARE_BIT0_BINARY = SPARE_BIT0;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0);
$finish;
end
if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1))
SPARE_BIT1_BINARY = SPARE_BIT1;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1);
$finish;
end
if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1))
SPARE_BIT2_BINARY = SPARE_BIT2;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2);
$finish;
end
if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1))
SPARE_BIT3_BINARY = SPARE_BIT3;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3);
$finish;
end
if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1))
SPARE_BIT4_BINARY = SPARE_BIT4;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4);
$finish;
end
if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1))
SPARE_BIT5_BINARY = SPARE_BIT5;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5);
$finish;
end
if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1))
SPARE_BIT6_BINARY = SPARE_BIT6;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6);
$finish;
end
if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1))
SPARE_BIT7_BINARY = SPARE_BIT7;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7);
$finish;
end
if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1))
SPARE_BIT8_BINARY = SPARE_BIT8;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8);
$finish;
end
if ((VF0_MSIX_CAP_PBA_BIR >= 0) && (VF0_MSIX_CAP_PBA_BIR <= 7))
VF0_MSIX_CAP_PBA_BIR_BINARY = VF0_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF0_MSIX_CAP_TABLE_BIR >= 0) && (VF0_MSIX_CAP_TABLE_BIR <= 7))
VF0_MSIX_CAP_TABLE_BIR_BINARY = VF0_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF0_MSI_CAP_MULTIMSGCAP >= 0) && (VF0_MSI_CAP_MULTIMSGCAP <= 7))
VF0_MSI_CAP_MULTIMSGCAP_BINARY = VF0_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((VF1_MSIX_CAP_PBA_BIR >= 0) && (VF1_MSIX_CAP_PBA_BIR <= 7))
VF1_MSIX_CAP_PBA_BIR_BINARY = VF1_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF1_MSIX_CAP_TABLE_BIR >= 0) && (VF1_MSIX_CAP_TABLE_BIR <= 7))
VF1_MSIX_CAP_TABLE_BIR_BINARY = VF1_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF1_MSI_CAP_MULTIMSGCAP >= 0) && (VF1_MSI_CAP_MULTIMSGCAP <= 7))
VF1_MSI_CAP_MULTIMSGCAP_BINARY = VF1_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((VF2_MSIX_CAP_PBA_BIR >= 0) && (VF2_MSIX_CAP_PBA_BIR <= 7))
VF2_MSIX_CAP_PBA_BIR_BINARY = VF2_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF2_MSIX_CAP_TABLE_BIR >= 0) && (VF2_MSIX_CAP_TABLE_BIR <= 7))
VF2_MSIX_CAP_TABLE_BIR_BINARY = VF2_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF2_MSI_CAP_MULTIMSGCAP >= 0) && (VF2_MSI_CAP_MULTIMSGCAP <= 7))
VF2_MSI_CAP_MULTIMSGCAP_BINARY = VF2_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((VF3_MSIX_CAP_PBA_BIR >= 0) && (VF3_MSIX_CAP_PBA_BIR <= 7))
VF3_MSIX_CAP_PBA_BIR_BINARY = VF3_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF3_MSIX_CAP_TABLE_BIR >= 0) && (VF3_MSIX_CAP_TABLE_BIR <= 7))
VF3_MSIX_CAP_TABLE_BIR_BINARY = VF3_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF3_MSI_CAP_MULTIMSGCAP >= 0) && (VF3_MSI_CAP_MULTIMSGCAP <= 7))
VF3_MSI_CAP_MULTIMSGCAP_BINARY = VF3_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((VF4_MSIX_CAP_PBA_BIR >= 0) && (VF4_MSIX_CAP_PBA_BIR <= 7))
VF4_MSIX_CAP_PBA_BIR_BINARY = VF4_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF4_MSIX_CAP_TABLE_BIR >= 0) && (VF4_MSIX_CAP_TABLE_BIR <= 7))
VF4_MSIX_CAP_TABLE_BIR_BINARY = VF4_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF4_MSI_CAP_MULTIMSGCAP >= 0) && (VF4_MSI_CAP_MULTIMSGCAP <= 7))
VF4_MSI_CAP_MULTIMSGCAP_BINARY = VF4_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSI_CAP_MULTIMSGCAP);
$finish;
end
if ((VF5_MSIX_CAP_PBA_BIR >= 0) && (VF5_MSIX_CAP_PBA_BIR <= 7))
VF5_MSIX_CAP_PBA_BIR_BINARY = VF5_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_PBA_BIR);
$finish;
end
if ((VF5_MSIX_CAP_TABLE_BIR >= 0) && (VF5_MSIX_CAP_TABLE_BIR <= 7))
VF5_MSIX_CAP_TABLE_BIR_BINARY = VF5_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_TABLE_BIR);
$finish;
end
if ((VF5_MSI_CAP_MULTIMSGCAP >= 0) && (VF5_MSI_CAP_MULTIMSGCAP <= 7))
VF5_MSI_CAP_MULTIMSGCAP_BINARY = VF5_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSI_CAP_MULTIMSGCAP);
$finish;
end
end
wire [11:0] delay_CFGFCCPLD;
wire [11:0] delay_CFGFCNPD;
wire [11:0] delay_CFGFCPD;
wire [11:0] delay_CFGVFSTATUS;
wire [143:0] delay_MIREPLAYRAMWRITEDATA;
wire [143:0] delay_MIREQUESTRAMWRITEDATA;
wire [15:0] delay_CFGPERFUNCSTATUSDATA;
wire [15:0] delay_DBGDATAOUT;
wire [15:0] delay_DRPDO;
wire [17:0] delay_CFGVFPOWERSTATE;
wire [17:0] delay_CFGVFTPHSTMODE;
wire [1:0] delay_CFGDPASUBSTATECHANGE;
wire [1:0] delay_CFGFLRINPROCESS;
wire [1:0] delay_CFGINTERRUPTMSIENABLE;
wire [1:0] delay_CFGINTERRUPTMSIXENABLE;
wire [1:0] delay_CFGINTERRUPTMSIXMASK;
wire [1:0] delay_CFGLINKPOWERSTATE;
wire [1:0] delay_CFGOBFFENABLE;
wire [1:0] delay_CFGPHYLINKSTATUS;
wire [1:0] delay_CFGRCBSTATUS;
wire [1:0] delay_CFGTPHREQUESTERENABLE;
wire [1:0] delay_MIREPLAYRAMREADENABLE;
wire [1:0] delay_MIREPLAYRAMWRITEENABLE;
wire [1:0] delay_PCIERQTAGAV;
wire [1:0] delay_PCIETFCNPDAV;
wire [1:0] delay_PCIETFCNPHAV;
wire [1:0] delay_PIPERX0EQCONTROL;
wire [1:0] delay_PIPERX1EQCONTROL;
wire [1:0] delay_PIPERX2EQCONTROL;
wire [1:0] delay_PIPERX3EQCONTROL;
wire [1:0] delay_PIPERX4EQCONTROL;
wire [1:0] delay_PIPERX5EQCONTROL;
wire [1:0] delay_PIPERX6EQCONTROL;
wire [1:0] delay_PIPERX7EQCONTROL;
wire [1:0] delay_PIPETX0CHARISK;
wire [1:0] delay_PIPETX0EQCONTROL;
wire [1:0] delay_PIPETX0POWERDOWN;
wire [1:0] delay_PIPETX0SYNCHEADER;
wire [1:0] delay_PIPETX1CHARISK;
wire [1:0] delay_PIPETX1EQCONTROL;
wire [1:0] delay_PIPETX1POWERDOWN;
wire [1:0] delay_PIPETX1SYNCHEADER;
wire [1:0] delay_PIPETX2CHARISK;
wire [1:0] delay_PIPETX2EQCONTROL;
wire [1:0] delay_PIPETX2POWERDOWN;
wire [1:0] delay_PIPETX2SYNCHEADER;
wire [1:0] delay_PIPETX3CHARISK;
wire [1:0] delay_PIPETX3EQCONTROL;
wire [1:0] delay_PIPETX3POWERDOWN;
wire [1:0] delay_PIPETX3SYNCHEADER;
wire [1:0] delay_PIPETX4CHARISK;
wire [1:0] delay_PIPETX4EQCONTROL;
wire [1:0] delay_PIPETX4POWERDOWN;
wire [1:0] delay_PIPETX4SYNCHEADER;
wire [1:0] delay_PIPETX5CHARISK;
wire [1:0] delay_PIPETX5EQCONTROL;
wire [1:0] delay_PIPETX5POWERDOWN;
wire [1:0] delay_PIPETX5SYNCHEADER;
wire [1:0] delay_PIPETX6CHARISK;
wire [1:0] delay_PIPETX6EQCONTROL;
wire [1:0] delay_PIPETX6POWERDOWN;
wire [1:0] delay_PIPETX6SYNCHEADER;
wire [1:0] delay_PIPETX7CHARISK;
wire [1:0] delay_PIPETX7EQCONTROL;
wire [1:0] delay_PIPETX7POWERDOWN;
wire [1:0] delay_PIPETX7SYNCHEADER;
wire [1:0] delay_PIPETXRATE;
wire [1:0] delay_PLEQPHASE;
wire [255:0] delay_MAXISCQTDATA;
wire [255:0] delay_MAXISRCTDATA;
wire [2:0] delay_CFGCURRENTSPEED;
wire [2:0] delay_CFGMAXPAYLOAD;
wire [2:0] delay_CFGMAXREADREQ;
wire [2:0] delay_CFGTPHFUNCTIONNUM;
wire [2:0] delay_PIPERX0EQPRESET;
wire [2:0] delay_PIPERX1EQPRESET;
wire [2:0] delay_PIPERX2EQPRESET;
wire [2:0] delay_PIPERX3EQPRESET;
wire [2:0] delay_PIPERX4EQPRESET;
wire [2:0] delay_PIPERX5EQPRESET;
wire [2:0] delay_PIPERX6EQPRESET;
wire [2:0] delay_PIPERX7EQPRESET;
wire [2:0] delay_PIPETXMARGIN;
wire [31:0] delay_CFGEXTWRITEDATA;
wire [31:0] delay_CFGINTERRUPTMSIDATA;
wire [31:0] delay_CFGMGMTREADDATA;
wire [31:0] delay_CFGTPHSTTWRITEDATA;
wire [31:0] delay_PIPETX0DATA;
wire [31:0] delay_PIPETX1DATA;
wire [31:0] delay_PIPETX2DATA;
wire [31:0] delay_PIPETX3DATA;
wire [31:0] delay_PIPETX4DATA;
wire [31:0] delay_PIPETX5DATA;
wire [31:0] delay_PIPETX6DATA;
wire [31:0] delay_PIPETX7DATA;
wire [3:0] delay_CFGEXTWRITEBYTEENABLE;
wire [3:0] delay_CFGNEGOTIATEDWIDTH;
wire [3:0] delay_CFGTPHSTTWRITEBYTEVALID;
wire [3:0] delay_MICOMPLETIONRAMREADENABLEL;
wire [3:0] delay_MICOMPLETIONRAMREADENABLEU;
wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEL;
wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEU;
wire [3:0] delay_MIREQUESTRAMREADENABLE;
wire [3:0] delay_MIREQUESTRAMWRITEENABLE;
wire [3:0] delay_PCIERQSEQNUM;
wire [3:0] delay_PIPERX0EQLPTXPRESET;
wire [3:0] delay_PIPERX1EQLPTXPRESET;
wire [3:0] delay_PIPERX2EQLPTXPRESET;
wire [3:0] delay_PIPERX3EQLPTXPRESET;
wire [3:0] delay_PIPERX4EQLPTXPRESET;
wire [3:0] delay_PIPERX5EQLPTXPRESET;
wire [3:0] delay_PIPERX6EQLPTXPRESET;
wire [3:0] delay_PIPERX7EQLPTXPRESET;
wire [3:0] delay_PIPETX0EQPRESET;
wire [3:0] delay_PIPETX1EQPRESET;
wire [3:0] delay_PIPETX2EQPRESET;
wire [3:0] delay_PIPETX3EQPRESET;
wire [3:0] delay_PIPETX4EQPRESET;
wire [3:0] delay_PIPETX5EQPRESET;
wire [3:0] delay_PIPETX6EQPRESET;
wire [3:0] delay_PIPETX7EQPRESET;
wire [3:0] delay_SAXISCCTREADY;
wire [3:0] delay_SAXISRQTREADY;
wire [4:0] delay_CFGMSGRECEIVEDTYPE;
wire [4:0] delay_CFGTPHSTTADDRESS;
wire [5:0] delay_CFGFUNCTIONPOWERSTATE;
wire [5:0] delay_CFGINTERRUPTMSIMMENABLE;
wire [5:0] delay_CFGINTERRUPTMSIVFENABLE;
wire [5:0] delay_CFGINTERRUPTMSIXVFENABLE;
wire [5:0] delay_CFGINTERRUPTMSIXVFMASK;
wire [5:0] delay_CFGLTSSMSTATE;
wire [5:0] delay_CFGTPHSTMODE;
wire [5:0] delay_CFGVFFLRINPROCESS;
wire [5:0] delay_CFGVFTPHREQUESTERENABLE;
wire [5:0] delay_PCIECQNPREQCOUNT;
wire [5:0] delay_PCIERQTAG;
wire [5:0] delay_PIPERX0EQLPLFFS;
wire [5:0] delay_PIPERX1EQLPLFFS;
wire [5:0] delay_PIPERX2EQLPLFFS;
wire [5:0] delay_PIPERX3EQLPLFFS;
wire [5:0] delay_PIPERX4EQLPLFFS;
wire [5:0] delay_PIPERX5EQLPLFFS;
wire [5:0] delay_PIPERX6EQLPLFFS;
wire [5:0] delay_PIPERX7EQLPLFFS;
wire [5:0] delay_PIPETX0EQDEEMPH;
wire [5:0] delay_PIPETX1EQDEEMPH;
wire [5:0] delay_PIPETX2EQDEEMPH;
wire [5:0] delay_PIPETX3EQDEEMPH;
wire [5:0] delay_PIPETX4EQDEEMPH;
wire [5:0] delay_PIPETX5EQDEEMPH;
wire [5:0] delay_PIPETX6EQDEEMPH;
wire [5:0] delay_PIPETX7EQDEEMPH;
wire [71:0] delay_MICOMPLETIONRAMWRITEDATAL;
wire [71:0] delay_MICOMPLETIONRAMWRITEDATAU;
wire [74:0] delay_MAXISRCTUSER;
wire [7:0] delay_CFGEXTFUNCTIONNUMBER;
wire [7:0] delay_CFGFCCPLH;
wire [7:0] delay_CFGFCNPH;
wire [7:0] delay_CFGFCPH;
wire [7:0] delay_CFGFUNCTIONSTATUS;
wire [7:0] delay_CFGMSGRECEIVEDDATA;
wire [7:0] delay_MAXISCQTKEEP;
wire [7:0] delay_MAXISRCTKEEP;
wire [7:0] delay_PLGEN3PCSRXSLIDE;
wire [84:0] delay_MAXISCQTUSER;
wire [8:0] delay_MIREPLAYRAMADDRESS;
wire [8:0] delay_MIREQUESTRAMREADADDRESSA;
wire [8:0] delay_MIREQUESTRAMREADADDRESSB;
wire [8:0] delay_MIREQUESTRAMWRITEADDRESSA;
wire [8:0] delay_MIREQUESTRAMWRITEADDRESSB;
wire [9:0] delay_CFGEXTREGISTERNUMBER;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAL;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAU;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBL;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBU;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAL;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAU;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBL;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBU;
wire delay_CFGERRCOROUT;
wire delay_CFGERRFATALOUT;
wire delay_CFGERRNONFATALOUT;
wire delay_CFGEXTREADRECEIVED;
wire delay_CFGEXTWRITERECEIVED;
wire delay_CFGHOTRESETOUT;
wire delay_CFGINPUTUPDATEDONE;
wire delay_CFGINTERRUPTAOUTPUT;
wire delay_CFGINTERRUPTBOUTPUT;
wire delay_CFGINTERRUPTCOUTPUT;
wire delay_CFGINTERRUPTDOUTPUT;
wire delay_CFGINTERRUPTMSIFAIL;
wire delay_CFGINTERRUPTMSIMASKUPDATE;
wire delay_CFGINTERRUPTMSISENT;
wire delay_CFGINTERRUPTMSIXFAIL;
wire delay_CFGINTERRUPTMSIXSENT;
wire delay_CFGINTERRUPTSENT;
wire delay_CFGLOCALERROR;
wire delay_CFGLTRENABLE;
wire delay_CFGMCUPDATEDONE;
wire delay_CFGMGMTREADWRITEDONE;
wire delay_CFGMSGRECEIVED;
wire delay_CFGMSGTRANSMITDONE;
wire delay_CFGPERFUNCTIONUPDATEDONE;
wire delay_CFGPHYLINKDOWN;
wire delay_CFGPLSTATUSCHANGE;
wire delay_CFGPOWERSTATECHANGEINTERRUPT;
wire delay_CFGTPHSTTREADENABLE;
wire delay_CFGTPHSTTWRITEENABLE;
wire delay_DRPRDY;
wire delay_MAXISCQTLAST;
wire delay_MAXISCQTVALID;
wire delay_MAXISRCTLAST;
wire delay_MAXISRCTVALID;
wire delay_PCIERQSEQNUMVLD;
wire delay_PCIERQTAGVLD;
wire delay_PIPERX0POLARITY;
wire delay_PIPERX1POLARITY;
wire delay_PIPERX2POLARITY;
wire delay_PIPERX3POLARITY;
wire delay_PIPERX4POLARITY;
wire delay_PIPERX5POLARITY;
wire delay_PIPERX6POLARITY;
wire delay_PIPERX7POLARITY;
wire delay_PIPETX0COMPLIANCE;
wire delay_PIPETX0DATAVALID;
wire delay_PIPETX0ELECIDLE;
wire delay_PIPETX0STARTBLOCK;
wire delay_PIPETX1COMPLIANCE;
wire delay_PIPETX1DATAVALID;
wire delay_PIPETX1ELECIDLE;
wire delay_PIPETX1STARTBLOCK;
wire delay_PIPETX2COMPLIANCE;
wire delay_PIPETX2DATAVALID;
wire delay_PIPETX2ELECIDLE;
wire delay_PIPETX2STARTBLOCK;
wire delay_PIPETX3COMPLIANCE;
wire delay_PIPETX3DATAVALID;
wire delay_PIPETX3ELECIDLE;
wire delay_PIPETX3STARTBLOCK;
wire delay_PIPETX4COMPLIANCE;
wire delay_PIPETX4DATAVALID;
wire delay_PIPETX4ELECIDLE;
wire delay_PIPETX4STARTBLOCK;
wire delay_PIPETX5COMPLIANCE;
wire delay_PIPETX5DATAVALID;
wire delay_PIPETX5ELECIDLE;
wire delay_PIPETX5STARTBLOCK;
wire delay_PIPETX6COMPLIANCE;
wire delay_PIPETX6DATAVALID;
wire delay_PIPETX6ELECIDLE;
wire delay_PIPETX6STARTBLOCK;
wire delay_PIPETX7COMPLIANCE;
wire delay_PIPETX7DATAVALID;
wire delay_PIPETX7ELECIDLE;
wire delay_PIPETX7STARTBLOCK;
wire delay_PIPETXDEEMPH;
wire delay_PIPETXRCVRDET;
wire delay_PIPETXRESET;
wire delay_PIPETXSWING;
wire delay_PLEQINPROGRESS;
wire [10:0] delay_DRPADDR;
wire [143:0] delay_MICOMPLETIONRAMREADDATA;
wire [143:0] delay_MIREPLAYRAMREADDATA;
wire [143:0] delay_MIREQUESTRAMREADDATA;
wire [15:0] delay_CFGDEVID;
wire [15:0] delay_CFGSUBSYSID;
wire [15:0] delay_CFGSUBSYSVENDID;
wire [15:0] delay_CFGVENDID;
wire [15:0] delay_DRPDI;
wire [17:0] delay_PIPERX0EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX1EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX2EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX3EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX4EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX5EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX6EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX7EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPETX0EQCOEFF;
wire [17:0] delay_PIPETX1EQCOEFF;
wire [17:0] delay_PIPETX2EQCOEFF;
wire [17:0] delay_PIPETX3EQCOEFF;
wire [17:0] delay_PIPETX4EQCOEFF;
wire [17:0] delay_PIPETX5EQCOEFF;
wire [17:0] delay_PIPETX6EQCOEFF;
wire [17:0] delay_PIPETX7EQCOEFF;
wire [18:0] delay_CFGMGMTADDR;
wire [1:0] delay_CFGFLRDONE;
wire [1:0] delay_CFGINTERRUPTMSITPHTYPE;
wire [1:0] delay_CFGINTERRUPTPENDING;
wire [1:0] delay_PIPERX0CHARISK;
wire [1:0] delay_PIPERX0SYNCHEADER;
wire [1:0] delay_PIPERX1CHARISK;
wire [1:0] delay_PIPERX1SYNCHEADER;
wire [1:0] delay_PIPERX2CHARISK;
wire [1:0] delay_PIPERX2SYNCHEADER;
wire [1:0] delay_PIPERX3CHARISK;
wire [1:0] delay_PIPERX3SYNCHEADER;
wire [1:0] delay_PIPERX4CHARISK;
wire [1:0] delay_PIPERX4SYNCHEADER;
wire [1:0] delay_PIPERX5CHARISK;
wire [1:0] delay_PIPERX5SYNCHEADER;
wire [1:0] delay_PIPERX6CHARISK;
wire [1:0] delay_PIPERX6SYNCHEADER;
wire [1:0] delay_PIPERX7CHARISK;
wire [1:0] delay_PIPERX7SYNCHEADER;
wire [21:0] delay_MAXISCQTREADY;
wire [21:0] delay_MAXISRCTREADY;
wire [255:0] delay_SAXISCCTDATA;
wire [255:0] delay_SAXISRQTDATA;
wire [2:0] delay_CFGDSFUNCTIONNUMBER;
wire [2:0] delay_CFGFCSEL;
wire [2:0] delay_CFGINTERRUPTMSIATTR;
wire [2:0] delay_CFGINTERRUPTMSIFUNCTIONNUMBER;
wire [2:0] delay_CFGMSGTRANSMITTYPE;
wire [2:0] delay_CFGPERFUNCSTATUSCONTROL;
wire [2:0] delay_CFGPERFUNCTIONNUMBER;
wire [2:0] delay_PIPERX0STATUS;
wire [2:0] delay_PIPERX1STATUS;
wire [2:0] delay_PIPERX2STATUS;
wire [2:0] delay_PIPERX3STATUS;
wire [2:0] delay_PIPERX4STATUS;
wire [2:0] delay_PIPERX5STATUS;
wire [2:0] delay_PIPERX6STATUS;
wire [2:0] delay_PIPERX7STATUS;
wire [31:0] delay_CFGEXTREADDATA;
wire [31:0] delay_CFGINTERRUPTMSIINT;
wire [31:0] delay_CFGINTERRUPTMSIXDATA;
wire [31:0] delay_CFGMGMTWRITEDATA;
wire [31:0] delay_CFGMSGTRANSMITDATA;
wire [31:0] delay_CFGTPHSTTREADDATA;
wire [31:0] delay_PIPERX0DATA;
wire [31:0] delay_PIPERX1DATA;
wire [31:0] delay_PIPERX2DATA;
wire [31:0] delay_PIPERX3DATA;
wire [31:0] delay_PIPERX4DATA;
wire [31:0] delay_PIPERX5DATA;
wire [31:0] delay_PIPERX6DATA;
wire [31:0] delay_PIPERX7DATA;
wire [32:0] delay_SAXISCCTUSER;
wire [3:0] delay_CFGINTERRUPTINT;
wire [3:0] delay_CFGINTERRUPTMSISELECT;
wire [3:0] delay_CFGMGMTBYTEENABLE;
wire [4:0] delay_CFGDSDEVICENUMBER;
wire [59:0] delay_SAXISRQTUSER;
wire [5:0] delay_CFGVFFLRDONE;
wire [5:0] delay_PIPEEQFS;
wire [5:0] delay_PIPEEQLF;
wire [63:0] delay_CFGDSN;
wire [63:0] delay_CFGINTERRUPTMSIPENDINGSTATUS;
wire [63:0] delay_CFGINTERRUPTMSIXADDRESS;
wire [7:0] delay_CFGDSBUSNUMBER;
wire [7:0] delay_CFGDSPORTNUMBER;
wire [7:0] delay_CFGREVID;
wire [7:0] delay_PLGEN3PCSRXSYNCDONE;
wire [7:0] delay_SAXISCCTKEEP;
wire [7:0] delay_SAXISRQTKEEP;
wire [8:0] delay_CFGINTERRUPTMSITPHSTTAG;
wire delay_CFGCONFIGSPACEENABLE;
wire delay_CFGERRCORIN;
wire delay_CFGERRUNCORIN;
wire delay_CFGEXTREADDATAVALID;
wire delay_CFGHOTRESETIN;
wire delay_CFGINPUTUPDATEREQUEST;
wire delay_CFGINTERRUPTMSITPHPRESENT;
wire delay_CFGINTERRUPTMSIXINT;
wire delay_CFGLINKTRAININGENABLE;
wire delay_CFGMCUPDATEREQUEST;
wire delay_CFGMGMTREAD;
wire delay_CFGMGMTTYPE1CFGREGACCESS;
wire delay_CFGMGMTWRITE;
wire delay_CFGMSGTRANSMIT;
wire delay_CFGPERFUNCTIONOUTPUTREQUEST;
wire delay_CFGPOWERSTATECHANGEACK;
wire delay_CFGREQPMTRANSITIONL23READY;
wire delay_CFGTPHSTTREADDATAVALID;
wire delay_CORECLK;
wire delay_CORECLKMICOMPLETIONRAML;
wire delay_CORECLKMICOMPLETIONRAMU;
wire delay_CORECLKMIREPLAYRAM;
wire delay_CORECLKMIREQUESTRAM;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_MGMTRESETN;
wire delay_MGMTSTICKYRESETN;
wire delay_PCIECQNPREQ;
wire delay_PIPECLK;
wire delay_PIPERESETN;
wire delay_PIPERX0DATAVALID;
wire delay_PIPERX0ELECIDLE;
wire delay_PIPERX0EQDONE;
wire delay_PIPERX0EQLPADAPTDONE;
wire delay_PIPERX0EQLPLFFSSEL;
wire delay_PIPERX0PHYSTATUS;
wire delay_PIPERX0STARTBLOCK;
wire delay_PIPERX0VALID;
wire delay_PIPERX1DATAVALID;
wire delay_PIPERX1ELECIDLE;
wire delay_PIPERX1EQDONE;
wire delay_PIPERX1EQLPADAPTDONE;
wire delay_PIPERX1EQLPLFFSSEL;
wire delay_PIPERX1PHYSTATUS;
wire delay_PIPERX1STARTBLOCK;
wire delay_PIPERX1VALID;
wire delay_PIPERX2DATAVALID;
wire delay_PIPERX2ELECIDLE;
wire delay_PIPERX2EQDONE;
wire delay_PIPERX2EQLPADAPTDONE;
wire delay_PIPERX2EQLPLFFSSEL;
wire delay_PIPERX2PHYSTATUS;
wire delay_PIPERX2STARTBLOCK;
wire delay_PIPERX2VALID;
wire delay_PIPERX3DATAVALID;
wire delay_PIPERX3ELECIDLE;
wire delay_PIPERX3EQDONE;
wire delay_PIPERX3EQLPADAPTDONE;
wire delay_PIPERX3EQLPLFFSSEL;
wire delay_PIPERX3PHYSTATUS;
wire delay_PIPERX3STARTBLOCK;
wire delay_PIPERX3VALID;
wire delay_PIPERX4DATAVALID;
wire delay_PIPERX4ELECIDLE;
wire delay_PIPERX4EQDONE;
wire delay_PIPERX4EQLPADAPTDONE;
wire delay_PIPERX4EQLPLFFSSEL;
wire delay_PIPERX4PHYSTATUS;
wire delay_PIPERX4STARTBLOCK;
wire delay_PIPERX4VALID;
wire delay_PIPERX5DATAVALID;
wire delay_PIPERX5ELECIDLE;
wire delay_PIPERX5EQDONE;
wire delay_PIPERX5EQLPADAPTDONE;
wire delay_PIPERX5EQLPLFFSSEL;
wire delay_PIPERX5PHYSTATUS;
wire delay_PIPERX5STARTBLOCK;
wire delay_PIPERX5VALID;
wire delay_PIPERX6DATAVALID;
wire delay_PIPERX6ELECIDLE;
wire delay_PIPERX6EQDONE;
wire delay_PIPERX6EQLPADAPTDONE;
wire delay_PIPERX6EQLPLFFSSEL;
wire delay_PIPERX6PHYSTATUS;
wire delay_PIPERX6STARTBLOCK;
wire delay_PIPERX6VALID;
wire delay_PIPERX7DATAVALID;
wire delay_PIPERX7ELECIDLE;
wire delay_PIPERX7EQDONE;
wire delay_PIPERX7EQLPADAPTDONE;
wire delay_PIPERX7EQLPLFFSSEL;
wire delay_PIPERX7PHYSTATUS;
wire delay_PIPERX7STARTBLOCK;
wire delay_PIPERX7VALID;
wire delay_PIPETX0EQDONE;
wire delay_PIPETX1EQDONE;
wire delay_PIPETX2EQDONE;
wire delay_PIPETX3EQDONE;
wire delay_PIPETX4EQDONE;
wire delay_PIPETX5EQDONE;
wire delay_PIPETX6EQDONE;
wire delay_PIPETX7EQDONE;
wire delay_PLDISABLESCRAMBLER;
wire delay_PLEQRESETEIEOSCOUNT;
wire delay_PLGEN3PCSDISABLE;
wire delay_RECCLK;
wire delay_RESETN;
wire delay_SAXISCCTLAST;
wire delay_SAXISCCTVALID;
wire delay_SAXISRQTLAST;
wire delay_SAXISRQTVALID;
wire delay_USERCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
assign #(out_delay) CFGCURRENTSPEED = delay_CFGCURRENTSPEED;
assign #(out_delay) CFGDPASUBSTATECHANGE = delay_CFGDPASUBSTATECHANGE;
assign #(out_delay) CFGERRCOROUT = delay_CFGERRCOROUT;
assign #(out_delay) CFGERRFATALOUT = delay_CFGERRFATALOUT;
assign #(out_delay) CFGERRNONFATALOUT = delay_CFGERRNONFATALOUT;
assign #(out_delay) CFGEXTFUNCTIONNUMBER = delay_CFGEXTFUNCTIONNUMBER;
assign #(out_delay) CFGEXTREADRECEIVED = delay_CFGEXTREADRECEIVED;
assign #(out_delay) CFGEXTREGISTERNUMBER = delay_CFGEXTREGISTERNUMBER;
assign #(out_delay) CFGEXTWRITEBYTEENABLE = delay_CFGEXTWRITEBYTEENABLE;
assign #(out_delay) CFGEXTWRITEDATA = delay_CFGEXTWRITEDATA;
assign #(out_delay) CFGEXTWRITERECEIVED = delay_CFGEXTWRITERECEIVED;
assign #(out_delay) CFGFCCPLD = delay_CFGFCCPLD;
assign #(out_delay) CFGFCCPLH = delay_CFGFCCPLH;
assign #(out_delay) CFGFCNPD = delay_CFGFCNPD;
assign #(out_delay) CFGFCNPH = delay_CFGFCNPH;
assign #(out_delay) CFGFCPD = delay_CFGFCPD;
assign #(out_delay) CFGFCPH = delay_CFGFCPH;
assign #(out_delay) CFGFLRINPROCESS = delay_CFGFLRINPROCESS;
assign #(out_delay) CFGFUNCTIONPOWERSTATE = delay_CFGFUNCTIONPOWERSTATE;
assign #(out_delay) CFGFUNCTIONSTATUS = delay_CFGFUNCTIONSTATUS;
assign #(out_delay) CFGHOTRESETOUT = delay_CFGHOTRESETOUT;
assign #(out_delay) CFGINPUTUPDATEDONE = delay_CFGINPUTUPDATEDONE;
assign #(out_delay) CFGINTERRUPTAOUTPUT = delay_CFGINTERRUPTAOUTPUT;
assign #(out_delay) CFGINTERRUPTBOUTPUT = delay_CFGINTERRUPTBOUTPUT;
assign #(out_delay) CFGINTERRUPTCOUTPUT = delay_CFGINTERRUPTCOUTPUT;
assign #(out_delay) CFGINTERRUPTDOUTPUT = delay_CFGINTERRUPTDOUTPUT;
assign #(out_delay) CFGINTERRUPTMSIDATA = delay_CFGINTERRUPTMSIDATA;
assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE;
assign #(out_delay) CFGINTERRUPTMSIFAIL = delay_CFGINTERRUPTMSIFAIL;
assign #(out_delay) CFGINTERRUPTMSIMASKUPDATE = delay_CFGINTERRUPTMSIMASKUPDATE;
assign #(out_delay) CFGINTERRUPTMSIMMENABLE = delay_CFGINTERRUPTMSIMMENABLE;
assign #(out_delay) CFGINTERRUPTMSISENT = delay_CFGINTERRUPTMSISENT;
assign #(out_delay) CFGINTERRUPTMSIVFENABLE = delay_CFGINTERRUPTMSIVFENABLE;
assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE;
assign #(out_delay) CFGINTERRUPTMSIXFAIL = delay_CFGINTERRUPTMSIXFAIL;
assign #(out_delay) CFGINTERRUPTMSIXMASK = delay_CFGINTERRUPTMSIXMASK;
assign #(out_delay) CFGINTERRUPTMSIXSENT = delay_CFGINTERRUPTMSIXSENT;
assign #(out_delay) CFGINTERRUPTMSIXVFENABLE = delay_CFGINTERRUPTMSIXVFENABLE;
assign #(out_delay) CFGINTERRUPTMSIXVFMASK = delay_CFGINTERRUPTMSIXVFMASK;
assign #(out_delay) CFGINTERRUPTSENT = delay_CFGINTERRUPTSENT;
assign #(out_delay) CFGLINKPOWERSTATE = delay_CFGLINKPOWERSTATE;
assign #(out_delay) CFGLOCALERROR = delay_CFGLOCALERROR;
assign #(out_delay) CFGLTRENABLE = delay_CFGLTRENABLE;
assign #(out_delay) CFGLTSSMSTATE = delay_CFGLTSSMSTATE;
assign #(out_delay) CFGMAXPAYLOAD = delay_CFGMAXPAYLOAD;
assign #(out_delay) CFGMAXREADREQ = delay_CFGMAXREADREQ;
assign #(out_delay) CFGMCUPDATEDONE = delay_CFGMCUPDATEDONE;
assign #(out_delay) CFGMGMTREADDATA = delay_CFGMGMTREADDATA;
assign #(out_delay) CFGMGMTREADWRITEDONE = delay_CFGMGMTREADWRITEDONE;
assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED;
assign #(out_delay) CFGMSGRECEIVEDDATA = delay_CFGMSGRECEIVEDDATA;
assign #(out_delay) CFGMSGRECEIVEDTYPE = delay_CFGMSGRECEIVEDTYPE;
assign #(out_delay) CFGMSGTRANSMITDONE = delay_CFGMSGTRANSMITDONE;
assign #(out_delay) CFGNEGOTIATEDWIDTH = delay_CFGNEGOTIATEDWIDTH;
assign #(out_delay) CFGOBFFENABLE = delay_CFGOBFFENABLE;
assign #(out_delay) CFGPERFUNCSTATUSDATA = delay_CFGPERFUNCSTATUSDATA;
assign #(out_delay) CFGPERFUNCTIONUPDATEDONE = delay_CFGPERFUNCTIONUPDATEDONE;
assign #(out_delay) CFGPHYLINKDOWN = delay_CFGPHYLINKDOWN;
assign #(out_delay) CFGPHYLINKSTATUS = delay_CFGPHYLINKSTATUS;
assign #(out_delay) CFGPLSTATUSCHANGE = delay_CFGPLSTATUSCHANGE;
assign #(out_delay) CFGPOWERSTATECHANGEINTERRUPT = delay_CFGPOWERSTATECHANGEINTERRUPT;
assign #(out_delay) CFGRCBSTATUS = delay_CFGRCBSTATUS;
assign #(out_delay) CFGTPHFUNCTIONNUM = delay_CFGTPHFUNCTIONNUM;
assign #(out_delay) CFGTPHREQUESTERENABLE = delay_CFGTPHREQUESTERENABLE;
assign #(out_delay) CFGTPHSTMODE = delay_CFGTPHSTMODE;
assign #(out_delay) CFGTPHSTTADDRESS = delay_CFGTPHSTTADDRESS;
assign #(out_delay) CFGTPHSTTREADENABLE = delay_CFGTPHSTTREADENABLE;
assign #(out_delay) CFGTPHSTTWRITEBYTEVALID = delay_CFGTPHSTTWRITEBYTEVALID;
assign #(out_delay) CFGTPHSTTWRITEDATA = delay_CFGTPHSTTWRITEDATA;
assign #(out_delay) CFGTPHSTTWRITEENABLE = delay_CFGTPHSTTWRITEENABLE;
assign #(out_delay) CFGVFFLRINPROCESS = delay_CFGVFFLRINPROCESS;
assign #(out_delay) CFGVFPOWERSTATE = delay_CFGVFPOWERSTATE;
assign #(out_delay) CFGVFSTATUS = delay_CFGVFSTATUS;
assign #(out_delay) CFGVFTPHREQUESTERENABLE = delay_CFGVFTPHREQUESTERENABLE;
assign #(out_delay) CFGVFTPHSTMODE = delay_CFGVFTPHSTMODE;
assign #(out_delay) DBGDATAOUT = delay_DBGDATAOUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) MAXISCQTDATA = delay_MAXISCQTDATA;
assign #(out_delay) MAXISCQTKEEP = delay_MAXISCQTKEEP;
assign #(out_delay) MAXISCQTLAST = delay_MAXISCQTLAST;
assign #(out_delay) MAXISCQTUSER = delay_MAXISCQTUSER;
assign #(out_delay) MAXISCQTVALID = delay_MAXISCQTVALID;
assign #(out_delay) MAXISRCTDATA = delay_MAXISRCTDATA;
assign #(out_delay) MAXISRCTKEEP = delay_MAXISRCTKEEP;
assign #(out_delay) MAXISRCTLAST = delay_MAXISRCTLAST;
assign #(out_delay) MAXISRCTUSER = delay_MAXISRCTUSER;
assign #(out_delay) MAXISRCTVALID = delay_MAXISRCTVALID;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAL = delay_MICOMPLETIONRAMREADADDRESSAL;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAU = delay_MICOMPLETIONRAMREADADDRESSAU;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBL = delay_MICOMPLETIONRAMREADADDRESSBL;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBU = delay_MICOMPLETIONRAMREADADDRESSBU;
assign #(out_delay) MICOMPLETIONRAMREADENABLEL = delay_MICOMPLETIONRAMREADENABLEL;
assign #(out_delay) MICOMPLETIONRAMREADENABLEU = delay_MICOMPLETIONRAMREADENABLEU;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAL = delay_MICOMPLETIONRAMWRITEADDRESSAL;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAU = delay_MICOMPLETIONRAMWRITEADDRESSAU;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBL = delay_MICOMPLETIONRAMWRITEADDRESSBL;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBU = delay_MICOMPLETIONRAMWRITEADDRESSBU;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAL = delay_MICOMPLETIONRAMWRITEDATAL;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAU = delay_MICOMPLETIONRAMWRITEDATAU;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEL = delay_MICOMPLETIONRAMWRITEENABLEL;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEU = delay_MICOMPLETIONRAMWRITEENABLEU;
assign #(out_delay) MIREPLAYRAMADDRESS = delay_MIREPLAYRAMADDRESS;
assign #(out_delay) MIREPLAYRAMREADENABLE = delay_MIREPLAYRAMREADENABLE;
assign #(out_delay) MIREPLAYRAMWRITEDATA = delay_MIREPLAYRAMWRITEDATA;
assign #(out_delay) MIREPLAYRAMWRITEENABLE = delay_MIREPLAYRAMWRITEENABLE;
assign #(out_delay) MIREQUESTRAMREADADDRESSA = delay_MIREQUESTRAMREADADDRESSA;
assign #(out_delay) MIREQUESTRAMREADADDRESSB = delay_MIREQUESTRAMREADADDRESSB;
assign #(out_delay) MIREQUESTRAMREADENABLE = delay_MIREQUESTRAMREADENABLE;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSA = delay_MIREQUESTRAMWRITEADDRESSA;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSB = delay_MIREQUESTRAMWRITEADDRESSB;
assign #(out_delay) MIREQUESTRAMWRITEDATA = delay_MIREQUESTRAMWRITEDATA;
assign #(out_delay) MIREQUESTRAMWRITEENABLE = delay_MIREQUESTRAMWRITEENABLE;
assign #(out_delay) PCIECQNPREQCOUNT = delay_PCIECQNPREQCOUNT;
assign #(out_delay) PCIERQSEQNUM = delay_PCIERQSEQNUM;
assign #(out_delay) PCIERQSEQNUMVLD = delay_PCIERQSEQNUMVLD;
assign #(out_delay) PCIERQTAG = delay_PCIERQTAG;
assign #(out_delay) PCIERQTAGAV = delay_PCIERQTAGAV;
assign #(out_delay) PCIERQTAGVLD = delay_PCIERQTAGVLD;
assign #(out_delay) PCIETFCNPDAV = delay_PCIETFCNPDAV;
assign #(out_delay) PCIETFCNPHAV = delay_PCIETFCNPHAV;
assign #(out_delay) PIPERX0EQCONTROL = delay_PIPERX0EQCONTROL;
assign #(out_delay) PIPERX0EQLPLFFS = delay_PIPERX0EQLPLFFS;
assign #(out_delay) PIPERX0EQLPTXPRESET = delay_PIPERX0EQLPTXPRESET;
assign #(out_delay) PIPERX0EQPRESET = delay_PIPERX0EQPRESET;
assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY;
assign #(out_delay) PIPERX1EQCONTROL = delay_PIPERX1EQCONTROL;
assign #(out_delay) PIPERX1EQLPLFFS = delay_PIPERX1EQLPLFFS;
assign #(out_delay) PIPERX1EQLPTXPRESET = delay_PIPERX1EQLPTXPRESET;
assign #(out_delay) PIPERX1EQPRESET = delay_PIPERX1EQPRESET;
assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY;
assign #(out_delay) PIPERX2EQCONTROL = delay_PIPERX2EQCONTROL;
assign #(out_delay) PIPERX2EQLPLFFS = delay_PIPERX2EQLPLFFS;
assign #(out_delay) PIPERX2EQLPTXPRESET = delay_PIPERX2EQLPTXPRESET;
assign #(out_delay) PIPERX2EQPRESET = delay_PIPERX2EQPRESET;
assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY;
assign #(out_delay) PIPERX3EQCONTROL = delay_PIPERX3EQCONTROL;
assign #(out_delay) PIPERX3EQLPLFFS = delay_PIPERX3EQLPLFFS;
assign #(out_delay) PIPERX3EQLPTXPRESET = delay_PIPERX3EQLPTXPRESET;
assign #(out_delay) PIPERX3EQPRESET = delay_PIPERX3EQPRESET;
assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY;
assign #(out_delay) PIPERX4EQCONTROL = delay_PIPERX4EQCONTROL;
assign #(out_delay) PIPERX4EQLPLFFS = delay_PIPERX4EQLPLFFS;
assign #(out_delay) PIPERX4EQLPTXPRESET = delay_PIPERX4EQLPTXPRESET;
assign #(out_delay) PIPERX4EQPRESET = delay_PIPERX4EQPRESET;
assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY;
assign #(out_delay) PIPERX5EQCONTROL = delay_PIPERX5EQCONTROL;
assign #(out_delay) PIPERX5EQLPLFFS = delay_PIPERX5EQLPLFFS;
assign #(out_delay) PIPERX5EQLPTXPRESET = delay_PIPERX5EQLPTXPRESET;
assign #(out_delay) PIPERX5EQPRESET = delay_PIPERX5EQPRESET;
assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY;
assign #(out_delay) PIPERX6EQCONTROL = delay_PIPERX6EQCONTROL;
assign #(out_delay) PIPERX6EQLPLFFS = delay_PIPERX6EQLPLFFS;
assign #(out_delay) PIPERX6EQLPTXPRESET = delay_PIPERX6EQLPTXPRESET;
assign #(out_delay) PIPERX6EQPRESET = delay_PIPERX6EQPRESET;
assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY;
assign #(out_delay) PIPERX7EQCONTROL = delay_PIPERX7EQCONTROL;
assign #(out_delay) PIPERX7EQLPLFFS = delay_PIPERX7EQLPLFFS;
assign #(out_delay) PIPERX7EQLPTXPRESET = delay_PIPERX7EQLPTXPRESET;
assign #(out_delay) PIPERX7EQPRESET = delay_PIPERX7EQPRESET;
assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY;
assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK;
assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE;
assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA;
assign #(out_delay) PIPETX0DATAVALID = delay_PIPETX0DATAVALID;
assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE;
assign #(out_delay) PIPETX0EQCONTROL = delay_PIPETX0EQCONTROL;
assign #(out_delay) PIPETX0EQDEEMPH = delay_PIPETX0EQDEEMPH;
assign #(out_delay) PIPETX0EQPRESET = delay_PIPETX0EQPRESET;
assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN;
assign #(out_delay) PIPETX0STARTBLOCK = delay_PIPETX0STARTBLOCK;
assign #(out_delay) PIPETX0SYNCHEADER = delay_PIPETX0SYNCHEADER;
assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK;
assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE;
assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA;
assign #(out_delay) PIPETX1DATAVALID = delay_PIPETX1DATAVALID;
assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE;
assign #(out_delay) PIPETX1EQCONTROL = delay_PIPETX1EQCONTROL;
assign #(out_delay) PIPETX1EQDEEMPH = delay_PIPETX1EQDEEMPH;
assign #(out_delay) PIPETX1EQPRESET = delay_PIPETX1EQPRESET;
assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN;
assign #(out_delay) PIPETX1STARTBLOCK = delay_PIPETX1STARTBLOCK;
assign #(out_delay) PIPETX1SYNCHEADER = delay_PIPETX1SYNCHEADER;
assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK;
assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE;
assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA;
assign #(out_delay) PIPETX2DATAVALID = delay_PIPETX2DATAVALID;
assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE;
assign #(out_delay) PIPETX2EQCONTROL = delay_PIPETX2EQCONTROL;
assign #(out_delay) PIPETX2EQDEEMPH = delay_PIPETX2EQDEEMPH;
assign #(out_delay) PIPETX2EQPRESET = delay_PIPETX2EQPRESET;
assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN;
assign #(out_delay) PIPETX2STARTBLOCK = delay_PIPETX2STARTBLOCK;
assign #(out_delay) PIPETX2SYNCHEADER = delay_PIPETX2SYNCHEADER;
assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK;
assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE;
assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA;
assign #(out_delay) PIPETX3DATAVALID = delay_PIPETX3DATAVALID;
assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE;
assign #(out_delay) PIPETX3EQCONTROL = delay_PIPETX3EQCONTROL;
assign #(out_delay) PIPETX3EQDEEMPH = delay_PIPETX3EQDEEMPH;
assign #(out_delay) PIPETX3EQPRESET = delay_PIPETX3EQPRESET;
assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN;
assign #(out_delay) PIPETX3STARTBLOCK = delay_PIPETX3STARTBLOCK;
assign #(out_delay) PIPETX3SYNCHEADER = delay_PIPETX3SYNCHEADER;
assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK;
assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE;
assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA;
assign #(out_delay) PIPETX4DATAVALID = delay_PIPETX4DATAVALID;
assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE;
assign #(out_delay) PIPETX4EQCONTROL = delay_PIPETX4EQCONTROL;
assign #(out_delay) PIPETX4EQDEEMPH = delay_PIPETX4EQDEEMPH;
assign #(out_delay) PIPETX4EQPRESET = delay_PIPETX4EQPRESET;
assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN;
assign #(out_delay) PIPETX4STARTBLOCK = delay_PIPETX4STARTBLOCK;
assign #(out_delay) PIPETX4SYNCHEADER = delay_PIPETX4SYNCHEADER;
assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK;
assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE;
assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA;
assign #(out_delay) PIPETX5DATAVALID = delay_PIPETX5DATAVALID;
assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE;
assign #(out_delay) PIPETX5EQCONTROL = delay_PIPETX5EQCONTROL;
assign #(out_delay) PIPETX5EQDEEMPH = delay_PIPETX5EQDEEMPH;
assign #(out_delay) PIPETX5EQPRESET = delay_PIPETX5EQPRESET;
assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN;
assign #(out_delay) PIPETX5STARTBLOCK = delay_PIPETX5STARTBLOCK;
assign #(out_delay) PIPETX5SYNCHEADER = delay_PIPETX5SYNCHEADER;
assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK;
assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE;
assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA;
assign #(out_delay) PIPETX6DATAVALID = delay_PIPETX6DATAVALID;
assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE;
assign #(out_delay) PIPETX6EQCONTROL = delay_PIPETX6EQCONTROL;
assign #(out_delay) PIPETX6EQDEEMPH = delay_PIPETX6EQDEEMPH;
assign #(out_delay) PIPETX6EQPRESET = delay_PIPETX6EQPRESET;
assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN;
assign #(out_delay) PIPETX6STARTBLOCK = delay_PIPETX6STARTBLOCK;
assign #(out_delay) PIPETX6SYNCHEADER = delay_PIPETX6SYNCHEADER;
assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK;
assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE;
assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA;
assign #(out_delay) PIPETX7DATAVALID = delay_PIPETX7DATAVALID;
assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE;
assign #(out_delay) PIPETX7EQCONTROL = delay_PIPETX7EQCONTROL;
assign #(out_delay) PIPETX7EQDEEMPH = delay_PIPETX7EQDEEMPH;
assign #(out_delay) PIPETX7EQPRESET = delay_PIPETX7EQPRESET;
assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN;
assign #(out_delay) PIPETX7STARTBLOCK = delay_PIPETX7STARTBLOCK;
assign #(out_delay) PIPETX7SYNCHEADER = delay_PIPETX7SYNCHEADER;
assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH;
assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN;
assign #(out_delay) PIPETXRATE = delay_PIPETXRATE;
assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET;
assign #(out_delay) PIPETXRESET = delay_PIPETXRESET;
assign #(out_delay) PIPETXSWING = delay_PIPETXSWING;
assign #(out_delay) PLEQINPROGRESS = delay_PLEQINPROGRESS;
assign #(out_delay) PLEQPHASE = delay_PLEQPHASE;
assign #(out_delay) PLGEN3PCSRXSLIDE = delay_PLGEN3PCSRXSLIDE;
assign #(out_delay) SAXISCCTREADY = delay_SAXISCCTREADY;
assign #(out_delay) SAXISRQTREADY = delay_SAXISRQTREADY;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CORECLK = CORECLK;
assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML;
assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU;
assign #(INCLK_DELAY) delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM;
assign #(INCLK_DELAY) delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK;
assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK;
assign #(INCLK_DELAY) delay_RECCLK = RECCLK;
assign #(INCLK_DELAY) delay_USERCLK = USERCLK;
assign #(in_delay) delay_CFGCONFIGSPACEENABLE = CFGCONFIGSPACEENABLE;
assign #(in_delay) delay_CFGDEVID = CFGDEVID;
assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER;
assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER;
assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER;
assign #(in_delay) delay_CFGDSN = CFGDSN;
assign #(in_delay) delay_CFGDSPORTNUMBER = CFGDSPORTNUMBER;
assign #(in_delay) delay_CFGERRCORIN = CFGERRCORIN;
assign #(in_delay) delay_CFGERRUNCORIN = CFGERRUNCORIN;
assign #(in_delay) delay_CFGEXTREADDATA = CFGEXTREADDATA;
assign #(in_delay) delay_CFGEXTREADDATAVALID = CFGEXTREADDATAVALID;
assign #(in_delay) delay_CFGFCSEL = CFGFCSEL;
assign #(in_delay) delay_CFGFLRDONE = CFGFLRDONE;
assign #(in_delay) delay_CFGHOTRESETIN = CFGHOTRESETIN;
assign #(in_delay) delay_CFGINPUTUPDATEREQUEST = CFGINPUTUPDATEREQUEST;
assign #(in_delay) delay_CFGINTERRUPTINT = CFGINTERRUPTINT;
assign #(in_delay) delay_CFGINTERRUPTMSIATTR = CFGINTERRUPTMSIATTR;
assign #(in_delay) delay_CFGINTERRUPTMSIFUNCTIONNUMBER = CFGINTERRUPTMSIFUNCTIONNUMBER;
assign #(in_delay) delay_CFGINTERRUPTMSIINT = CFGINTERRUPTMSIINT;
assign #(in_delay) delay_CFGINTERRUPTMSIPENDINGSTATUS = CFGINTERRUPTMSIPENDINGSTATUS;
assign #(in_delay) delay_CFGINTERRUPTMSISELECT = CFGINTERRUPTMSISELECT;
assign #(in_delay) delay_CFGINTERRUPTMSITPHPRESENT = CFGINTERRUPTMSITPHPRESENT;
assign #(in_delay) delay_CFGINTERRUPTMSITPHSTTAG = CFGINTERRUPTMSITPHSTTAG;
assign #(in_delay) delay_CFGINTERRUPTMSITPHTYPE = CFGINTERRUPTMSITPHTYPE;
assign #(in_delay) delay_CFGINTERRUPTMSIXADDRESS = CFGINTERRUPTMSIXADDRESS;
assign #(in_delay) delay_CFGINTERRUPTMSIXDATA = CFGINTERRUPTMSIXDATA;
assign #(in_delay) delay_CFGINTERRUPTMSIXINT = CFGINTERRUPTMSIXINT;
assign #(in_delay) delay_CFGINTERRUPTPENDING = CFGINTERRUPTPENDING;
assign #(in_delay) delay_CFGLINKTRAININGENABLE = CFGLINKTRAININGENABLE;
assign #(in_delay) delay_CFGMCUPDATEREQUEST = CFGMCUPDATEREQUEST;
assign #(in_delay) delay_CFGMGMTADDR = CFGMGMTADDR;
assign #(in_delay) delay_CFGMGMTBYTEENABLE = CFGMGMTBYTEENABLE;
assign #(in_delay) delay_CFGMGMTREAD = CFGMGMTREAD;
assign #(in_delay) delay_CFGMGMTTYPE1CFGREGACCESS = CFGMGMTTYPE1CFGREGACCESS;
assign #(in_delay) delay_CFGMGMTWRITE = CFGMGMTWRITE;
assign #(in_delay) delay_CFGMGMTWRITEDATA = CFGMGMTWRITEDATA;
assign #(in_delay) delay_CFGMSGTRANSMIT = CFGMSGTRANSMIT;
assign #(in_delay) delay_CFGMSGTRANSMITDATA = CFGMSGTRANSMITDATA;
assign #(in_delay) delay_CFGMSGTRANSMITTYPE = CFGMSGTRANSMITTYPE;
assign #(in_delay) delay_CFGPERFUNCSTATUSCONTROL = CFGPERFUNCSTATUSCONTROL;
assign #(in_delay) delay_CFGPERFUNCTIONNUMBER = CFGPERFUNCTIONNUMBER;
assign #(in_delay) delay_CFGPERFUNCTIONOUTPUTREQUEST = CFGPERFUNCTIONOUTPUTREQUEST;
assign #(in_delay) delay_CFGPOWERSTATECHANGEACK = CFGPOWERSTATECHANGEACK;
assign #(in_delay) delay_CFGREQPMTRANSITIONL23READY = CFGREQPMTRANSITIONL23READY;
assign #(in_delay) delay_CFGREVID = CFGREVID;
assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID;
assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID;
assign #(in_delay) delay_CFGTPHSTTREADDATA = CFGTPHSTTREADDATA;
assign #(in_delay) delay_CFGTPHSTTREADDATAVALID = CFGTPHSTTREADDATAVALID;
assign #(in_delay) delay_CFGVENDID = CFGVENDID;
assign #(in_delay) delay_CFGVFFLRDONE = CFGVFFLRDONE;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_MAXISCQTREADY = MAXISCQTREADY;
assign #(in_delay) delay_MAXISRCTREADY = MAXISRCTREADY;
assign #(in_delay) delay_MGMTRESETN = MGMTRESETN;
assign #(in_delay) delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN;
assign #(in_delay) delay_MICOMPLETIONRAMREADDATA = MICOMPLETIONRAMREADDATA;
assign #(in_delay) delay_MIREPLAYRAMREADDATA = MIREPLAYRAMREADDATA;
assign #(in_delay) delay_MIREQUESTRAMREADDATA = MIREQUESTRAMREADDATA;
assign #(in_delay) delay_PCIECQNPREQ = PCIECQNPREQ;
assign #(in_delay) delay_PIPEEQFS = PIPEEQFS;
assign #(in_delay) delay_PIPEEQLF = PIPEEQLF;
assign #(in_delay) delay_PIPERESETN = PIPERESETN;
assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK;
assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA;
assign #(in_delay) delay_PIPERX0DATAVALID = PIPERX0DATAVALID;
assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE;
assign #(in_delay) delay_PIPERX0EQDONE = PIPERX0EQDONE;
assign #(in_delay) delay_PIPERX0EQLPADAPTDONE = PIPERX0EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX0EQLPLFFSSEL = PIPERX0EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX0EQLPNEWTXCOEFFORPRESET = PIPERX0EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS;
assign #(in_delay) delay_PIPERX0STARTBLOCK = PIPERX0STARTBLOCK;
assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS;
assign #(in_delay) delay_PIPERX0SYNCHEADER = PIPERX0SYNCHEADER;
assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID;
assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK;
assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA;
assign #(in_delay) delay_PIPERX1DATAVALID = PIPERX1DATAVALID;
assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE;
assign #(in_delay) delay_PIPERX1EQDONE = PIPERX1EQDONE;
assign #(in_delay) delay_PIPERX1EQLPADAPTDONE = PIPERX1EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX1EQLPLFFSSEL = PIPERX1EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX1EQLPNEWTXCOEFFORPRESET = PIPERX1EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS;
assign #(in_delay) delay_PIPERX1STARTBLOCK = PIPERX1STARTBLOCK;
assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS;
assign #(in_delay) delay_PIPERX1SYNCHEADER = PIPERX1SYNCHEADER;
assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID;
assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK;
assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA;
assign #(in_delay) delay_PIPERX2DATAVALID = PIPERX2DATAVALID;
assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE;
assign #(in_delay) delay_PIPERX2EQDONE = PIPERX2EQDONE;
assign #(in_delay) delay_PIPERX2EQLPADAPTDONE = PIPERX2EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX2EQLPLFFSSEL = PIPERX2EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX2EQLPNEWTXCOEFFORPRESET = PIPERX2EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS;
assign #(in_delay) delay_PIPERX2STARTBLOCK = PIPERX2STARTBLOCK;
assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS;
assign #(in_delay) delay_PIPERX2SYNCHEADER = PIPERX2SYNCHEADER;
assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID;
assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK;
assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA;
assign #(in_delay) delay_PIPERX3DATAVALID = PIPERX3DATAVALID;
assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE;
assign #(in_delay) delay_PIPERX3EQDONE = PIPERX3EQDONE;
assign #(in_delay) delay_PIPERX3EQLPADAPTDONE = PIPERX3EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX3EQLPLFFSSEL = PIPERX3EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX3EQLPNEWTXCOEFFORPRESET = PIPERX3EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS;
assign #(in_delay) delay_PIPERX3STARTBLOCK = PIPERX3STARTBLOCK;
assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS;
assign #(in_delay) delay_PIPERX3SYNCHEADER = PIPERX3SYNCHEADER;
assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID;
assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK;
assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA;
assign #(in_delay) delay_PIPERX4DATAVALID = PIPERX4DATAVALID;
assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE;
assign #(in_delay) delay_PIPERX4EQDONE = PIPERX4EQDONE;
assign #(in_delay) delay_PIPERX4EQLPADAPTDONE = PIPERX4EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX4EQLPLFFSSEL = PIPERX4EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX4EQLPNEWTXCOEFFORPRESET = PIPERX4EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS;
assign #(in_delay) delay_PIPERX4STARTBLOCK = PIPERX4STARTBLOCK;
assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS;
assign #(in_delay) delay_PIPERX4SYNCHEADER = PIPERX4SYNCHEADER;
assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID;
assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK;
assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA;
assign #(in_delay) delay_PIPERX5DATAVALID = PIPERX5DATAVALID;
assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE;
assign #(in_delay) delay_PIPERX5EQDONE = PIPERX5EQDONE;
assign #(in_delay) delay_PIPERX5EQLPADAPTDONE = PIPERX5EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX5EQLPLFFSSEL = PIPERX5EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX5EQLPNEWTXCOEFFORPRESET = PIPERX5EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS;
assign #(in_delay) delay_PIPERX5STARTBLOCK = PIPERX5STARTBLOCK;
assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS;
assign #(in_delay) delay_PIPERX5SYNCHEADER = PIPERX5SYNCHEADER;
assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID;
assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK;
assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA;
assign #(in_delay) delay_PIPERX6DATAVALID = PIPERX6DATAVALID;
assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE;
assign #(in_delay) delay_PIPERX6EQDONE = PIPERX6EQDONE;
assign #(in_delay) delay_PIPERX6EQLPADAPTDONE = PIPERX6EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX6EQLPLFFSSEL = PIPERX6EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX6EQLPNEWTXCOEFFORPRESET = PIPERX6EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS;
assign #(in_delay) delay_PIPERX6STARTBLOCK = PIPERX6STARTBLOCK;
assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS;
assign #(in_delay) delay_PIPERX6SYNCHEADER = PIPERX6SYNCHEADER;
assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID;
assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK;
assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA;
assign #(in_delay) delay_PIPERX7DATAVALID = PIPERX7DATAVALID;
assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE;
assign #(in_delay) delay_PIPERX7EQDONE = PIPERX7EQDONE;
assign #(in_delay) delay_PIPERX7EQLPADAPTDONE = PIPERX7EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX7EQLPLFFSSEL = PIPERX7EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX7EQLPNEWTXCOEFFORPRESET = PIPERX7EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS;
assign #(in_delay) delay_PIPERX7STARTBLOCK = PIPERX7STARTBLOCK;
assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS;
assign #(in_delay) delay_PIPERX7SYNCHEADER = PIPERX7SYNCHEADER;
assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID;
assign #(in_delay) delay_PIPETX0EQCOEFF = PIPETX0EQCOEFF;
assign #(in_delay) delay_PIPETX0EQDONE = PIPETX0EQDONE;
assign #(in_delay) delay_PIPETX1EQCOEFF = PIPETX1EQCOEFF;
assign #(in_delay) delay_PIPETX1EQDONE = PIPETX1EQDONE;
assign #(in_delay) delay_PIPETX2EQCOEFF = PIPETX2EQCOEFF;
assign #(in_delay) delay_PIPETX2EQDONE = PIPETX2EQDONE;
assign #(in_delay) delay_PIPETX3EQCOEFF = PIPETX3EQCOEFF;
assign #(in_delay) delay_PIPETX3EQDONE = PIPETX3EQDONE;
assign #(in_delay) delay_PIPETX4EQCOEFF = PIPETX4EQCOEFF;
assign #(in_delay) delay_PIPETX4EQDONE = PIPETX4EQDONE;
assign #(in_delay) delay_PIPETX5EQCOEFF = PIPETX5EQCOEFF;
assign #(in_delay) delay_PIPETX5EQDONE = PIPETX5EQDONE;
assign #(in_delay) delay_PIPETX6EQCOEFF = PIPETX6EQCOEFF;
assign #(in_delay) delay_PIPETX6EQDONE = PIPETX6EQDONE;
assign #(in_delay) delay_PIPETX7EQCOEFF = PIPETX7EQCOEFF;
assign #(in_delay) delay_PIPETX7EQDONE = PIPETX7EQDONE;
assign #(in_delay) delay_PLDISABLESCRAMBLER = PLDISABLESCRAMBLER;
assign #(in_delay) delay_PLEQRESETEIEOSCOUNT = PLEQRESETEIEOSCOUNT;
assign #(in_delay) delay_PLGEN3PCSDISABLE = PLGEN3PCSDISABLE;
assign #(in_delay) delay_PLGEN3PCSRXSYNCDONE = PLGEN3PCSRXSYNCDONE;
assign #(in_delay) delay_RESETN = RESETN;
assign #(in_delay) delay_SAXISCCTDATA = SAXISCCTDATA;
assign #(in_delay) delay_SAXISCCTKEEP = SAXISCCTKEEP;
assign #(in_delay) delay_SAXISCCTLAST = SAXISCCTLAST;
assign #(in_delay) delay_SAXISCCTUSER = SAXISCCTUSER;
assign #(in_delay) delay_SAXISCCTVALID = SAXISCCTVALID;
assign #(in_delay) delay_SAXISRQTDATA = SAXISRQTDATA;
assign #(in_delay) delay_SAXISRQTKEEP = SAXISRQTKEEP;
assign #(in_delay) delay_SAXISRQTLAST = SAXISRQTLAST;
assign #(in_delay) delay_SAXISRQTUSER = SAXISRQTUSER;
assign #(in_delay) delay_SAXISRQTVALID = SAXISRQTVALID;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML;
assign delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU;
assign delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM;
assign delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM;
assign delay_MGMTRESETN = MGMTRESETN;
assign delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN;
assign delay_PIPERESETN = PIPERESETN;
assign delay_RESETN = RESETN;
`endif
B_PCIE_3_0 #(
.ARI_CAP_ENABLE (ARI_CAP_ENABLE),
.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE),
.AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK),
.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE),
.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG),
.AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC),
.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE),
.AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE),
.AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK),
.AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH),
.CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500),
.CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ),
.DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
.GEN3_PCS_AUTO_REALIGN (GEN3_PCS_AUTO_REALIGN),
.GEN3_PCS_RX_ELECIDLE_INTERNAL (GEN3_PCS_RX_ELECIDLE_INTERNAL),
.LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
.LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
.LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE),
.LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER),
.LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE),
.LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE),
.LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER),
.LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE),
.LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
.LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE),
.LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE),
.PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE),
.PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR),
.PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR),
.PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC),
.PF0_ARI_CAP_VER (PF0_ARI_CAP_VER),
.PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE),
.PF0_BAR0_CONTROL (PF0_BAR0_CONTROL),
.PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE),
.PF0_BAR1_CONTROL (PF0_BAR1_CONTROL),
.PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE),
.PF0_BAR2_CONTROL (PF0_BAR2_CONTROL),
.PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE),
.PF0_BAR3_CONTROL (PF0_BAR3_CONTROL),
.PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE),
.PF0_BAR4_CONTROL (PF0_BAR4_CONTROL),
.PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE),
.PF0_BAR5_CONTROL (PF0_BAR5_CONTROL),
.PF0_BIST_REGISTER (PF0_BIST_REGISTER),
.PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER),
.PF0_CLASS_CODE (PF0_CLASS_CODE),
.PF0_DEVICE_ID (PF0_DEVICE_ID),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE),
.PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT),
.PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE),
.PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR),
.PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
.PF0_DPA_CAP_VER (PF0_DPA_CAP_VER),
.PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR),
.PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE),
.PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE),
.PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE),
.PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN),
.PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT),
.PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT),
.PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR),
.PF0_LTR_CAP_VER (PF0_LTR_CAP_VER),
.PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR),
.PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR),
.PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET),
.PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR),
.PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET),
.PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE),
.PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP),
.PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR),
.PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR),
.PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED),
.PF0_PB_CAP_VER (PF0_PB_CAP_VER),
.PF0_PM_CAP_ID (PF0_PM_CAP_ID),
.PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR),
.PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0),
.PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1),
.PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT),
.PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE),
.PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID),
.PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET),
.PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE),
.PF0_RBAR_CAP_INDEX0 (PF0_RBAR_CAP_INDEX0),
.PF0_RBAR_CAP_INDEX1 (PF0_RBAR_CAP_INDEX1),
.PF0_RBAR_CAP_INDEX2 (PF0_RBAR_CAP_INDEX2),
.PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR),
.PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0),
.PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1),
.PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2),
.PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER),
.PF0_RBAR_NUM (PF0_RBAR_NUM),
.PF0_REVISION_ID (PF0_REVISION_ID),
.PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE),
.PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL),
.PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE),
.PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL),
.PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE),
.PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL),
.PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE),
.PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL),
.PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE),
.PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL),
.PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE),
.PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL),
.PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF),
.PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR),
.PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF),
.PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER),
.PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET),
.PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE),
.PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID),
.PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE),
.PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE),
.PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE),
.PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR),
.PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL),
.PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC),
.PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE),
.PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER),
.PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR),
.PF0_VC_CAP_VER (PF0_VC_CAP_VER),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE),
.PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE),
.PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR),
.PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR),
.PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC),
.PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE),
.PF1_BAR0_CONTROL (PF1_BAR0_CONTROL),
.PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE),
.PF1_BAR1_CONTROL (PF1_BAR1_CONTROL),
.PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE),
.PF1_BAR2_CONTROL (PF1_BAR2_CONTROL),
.PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE),
.PF1_BAR3_CONTROL (PF1_BAR3_CONTROL),
.PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE),
.PF1_BAR4_CONTROL (PF1_BAR4_CONTROL),
.PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE),
.PF1_BAR5_CONTROL (PF1_BAR5_CONTROL),
.PF1_BIST_REGISTER (PF1_BIST_REGISTER),
.PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER),
.PF1_CLASS_CODE (PF1_CLASS_CODE),
.PF1_DEVICE_ID (PF1_DEVICE_ID),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE),
.PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR),
.PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
.PF1_DPA_CAP_VER (PF1_DPA_CAP_VER),
.PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR),
.PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE),
.PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE),
.PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE),
.PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN),
.PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR),
.PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR),
.PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET),
.PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR),
.PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET),
.PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE),
.PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP),
.PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR),
.PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR),
.PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED),
.PF1_PB_CAP_VER (PF1_PB_CAP_VER),
.PF1_PM_CAP_ID (PF1_PM_CAP_ID),
.PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR),
.PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID),
.PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE),
.PF1_RBAR_CAP_INDEX0 (PF1_RBAR_CAP_INDEX0),
.PF1_RBAR_CAP_INDEX1 (PF1_RBAR_CAP_INDEX1),
.PF1_RBAR_CAP_INDEX2 (PF1_RBAR_CAP_INDEX2),
.PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR),
.PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0),
.PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1),
.PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2),
.PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER),
.PF1_RBAR_NUM (PF1_RBAR_NUM),
.PF1_REVISION_ID (PF1_REVISION_ID),
.PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE),
.PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL),
.PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE),
.PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL),
.PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE),
.PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL),
.PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE),
.PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL),
.PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE),
.PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL),
.PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE),
.PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL),
.PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF),
.PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR),
.PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF),
.PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER),
.PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET),
.PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE),
.PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID),
.PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE),
.PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE),
.PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE),
.PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR),
.PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL),
.PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC),
.PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE),
.PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER),
.PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0),
.PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE),
.PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING),
.PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK),
.PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT),
.PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23),
.PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE),
.PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL),
.PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL),
.PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL),
.PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL),
.PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL),
.PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL),
.PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL),
.PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL),
.PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED),
.PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH),
.PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1),
.PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2),
.PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3),
.PL_N_FTS_GEN1 (PL_N_FTS_GEN1),
.PL_N_FTS_GEN2 (PL_N_FTS_GEN2),
.PL_N_FTS_GEN3 (PL_N_FTS_GEN3),
.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING),
.PL_UPSTREAM_FACING (PL_UPSTREAM_FACING),
.PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
.PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY),
.PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE),
.PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY),
.PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY),
.PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY),
.SIM_VERSION (SIM_VERSION),
.SPARE_BIT0 (SPARE_BIT0),
.SPARE_BIT1 (SPARE_BIT1),
.SPARE_BIT2 (SPARE_BIT2),
.SPARE_BIT3 (SPARE_BIT3),
.SPARE_BIT4 (SPARE_BIT4),
.SPARE_BIT5 (SPARE_BIT5),
.SPARE_BIT6 (SPARE_BIT6),
.SPARE_BIT7 (SPARE_BIT7),
.SPARE_BIT8 (SPARE_BIT8),
.SPARE_BYTE0 (SPARE_BYTE0),
.SPARE_BYTE1 (SPARE_BYTE1),
.SPARE_BYTE2 (SPARE_BYTE2),
.SPARE_BYTE3 (SPARE_BYTE3),
.SPARE_WORD0 (SPARE_WORD0),
.SPARE_WORD1 (SPARE_WORD1),
.SPARE_WORD2 (SPARE_WORD2),
.SPARE_WORD3 (SPARE_WORD3),
.SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE),
.TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0),
.TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1),
.TL_CREDITS_CD (TL_CREDITS_CD),
.TL_CREDITS_CH (TL_CREDITS_CH),
.TL_CREDITS_NPD (TL_CREDITS_NPD),
.TL_CREDITS_NPH (TL_CREDITS_NPH),
.TL_CREDITS_PD (TL_CREDITS_PD),
.TL_CREDITS_PH (TL_CREDITS_PH),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE),
.TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE),
.TL_PF_ENABLE_REG (TL_PF_ENABLE_REG),
.TL_TAG_MGMT_ENABLE (TL_TAG_MGMT_ENABLE),
.VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR),
.VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER),
.VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR),
.VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET),
.VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR),
.VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET),
.VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE),
.VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP),
.VF0_PM_CAP_ID (VF0_PM_CAP_ID),
.VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR),
.VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE),
.VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE),
.VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR),
.VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL),
.VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC),
.VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE),
.VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER),
.VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR),
.VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR),
.VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET),
.VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR),
.VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET),
.VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE),
.VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP),
.VF1_PM_CAP_ID (VF1_PM_CAP_ID),
.VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR),
.VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE),
.VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE),
.VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR),
.VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL),
.VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC),
.VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE),
.VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER),
.VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR),
.VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR),
.VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET),
.VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR),
.VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET),
.VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE),
.VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP),
.VF2_PM_CAP_ID (VF2_PM_CAP_ID),
.VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR),
.VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE),
.VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE),
.VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR),
.VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL),
.VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC),
.VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE),
.VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER),
.VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR),
.VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR),
.VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET),
.VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR),
.VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET),
.VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE),
.VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP),
.VF3_PM_CAP_ID (VF3_PM_CAP_ID),
.VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR),
.VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE),
.VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE),
.VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR),
.VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL),
.VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC),
.VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE),
.VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER),
.VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR),
.VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR),
.VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET),
.VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR),
.VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET),
.VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE),
.VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP),
.VF4_PM_CAP_ID (VF4_PM_CAP_ID),
.VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR),
.VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE),
.VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE),
.VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR),
.VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL),
.VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC),
.VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE),
.VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER),
.VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR),
.VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR),
.VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET),
.VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR),
.VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET),
.VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE),
.VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP),
.VF5_PM_CAP_ID (VF5_PM_CAP_ID),
.VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR),
.VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE),
.VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE),
.VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR),
.VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL),
.VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC),
.VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE),
.VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER))
B_PCIE_3_0_INST (
.CFGCURRENTSPEED (delay_CFGCURRENTSPEED),
.CFGDPASUBSTATECHANGE (delay_CFGDPASUBSTATECHANGE),
.CFGERRCOROUT (delay_CFGERRCOROUT),
.CFGERRFATALOUT (delay_CFGERRFATALOUT),
.CFGERRNONFATALOUT (delay_CFGERRNONFATALOUT),
.CFGEXTFUNCTIONNUMBER (delay_CFGEXTFUNCTIONNUMBER),
.CFGEXTREADRECEIVED (delay_CFGEXTREADRECEIVED),
.CFGEXTREGISTERNUMBER (delay_CFGEXTREGISTERNUMBER),
.CFGEXTWRITEBYTEENABLE (delay_CFGEXTWRITEBYTEENABLE),
.CFGEXTWRITEDATA (delay_CFGEXTWRITEDATA),
.CFGEXTWRITERECEIVED (delay_CFGEXTWRITERECEIVED),
.CFGFCCPLD (delay_CFGFCCPLD),
.CFGFCCPLH (delay_CFGFCCPLH),
.CFGFCNPD (delay_CFGFCNPD),
.CFGFCNPH (delay_CFGFCNPH),
.CFGFCPD (delay_CFGFCPD),
.CFGFCPH (delay_CFGFCPH),
.CFGFLRINPROCESS (delay_CFGFLRINPROCESS),
.CFGFUNCTIONPOWERSTATE (delay_CFGFUNCTIONPOWERSTATE),
.CFGFUNCTIONSTATUS (delay_CFGFUNCTIONSTATUS),
.CFGHOTRESETOUT (delay_CFGHOTRESETOUT),
.CFGINPUTUPDATEDONE (delay_CFGINPUTUPDATEDONE),
.CFGINTERRUPTAOUTPUT (delay_CFGINTERRUPTAOUTPUT),
.CFGINTERRUPTBOUTPUT (delay_CFGINTERRUPTBOUTPUT),
.CFGINTERRUPTCOUTPUT (delay_CFGINTERRUPTCOUTPUT),
.CFGINTERRUPTDOUTPUT (delay_CFGINTERRUPTDOUTPUT),
.CFGINTERRUPTMSIDATA (delay_CFGINTERRUPTMSIDATA),
.CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIFAIL (delay_CFGINTERRUPTMSIFAIL),
.CFGINTERRUPTMSIMASKUPDATE (delay_CFGINTERRUPTMSIMASKUPDATE),
.CFGINTERRUPTMSIMMENABLE (delay_CFGINTERRUPTMSIMMENABLE),
.CFGINTERRUPTMSISENT (delay_CFGINTERRUPTMSISENT),
.CFGINTERRUPTMSIVFENABLE (delay_CFGINTERRUPTMSIVFENABLE),
.CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFAIL (delay_CFGINTERRUPTMSIXFAIL),
.CFGINTERRUPTMSIXMASK (delay_CFGINTERRUPTMSIXMASK),
.CFGINTERRUPTMSIXSENT (delay_CFGINTERRUPTMSIXSENT),
.CFGINTERRUPTMSIXVFENABLE (delay_CFGINTERRUPTMSIXVFENABLE),
.CFGINTERRUPTMSIXVFMASK (delay_CFGINTERRUPTMSIXVFMASK),
.CFGINTERRUPTSENT (delay_CFGINTERRUPTSENT),
.CFGLINKPOWERSTATE (delay_CFGLINKPOWERSTATE),
.CFGLOCALERROR (delay_CFGLOCALERROR),
.CFGLTRENABLE (delay_CFGLTRENABLE),
.CFGLTSSMSTATE (delay_CFGLTSSMSTATE),
.CFGMAXPAYLOAD (delay_CFGMAXPAYLOAD),
.CFGMAXREADREQ (delay_CFGMAXREADREQ),
.CFGMCUPDATEDONE (delay_CFGMCUPDATEDONE),
.CFGMGMTREADDATA (delay_CFGMGMTREADDATA),
.CFGMGMTREADWRITEDONE (delay_CFGMGMTREADWRITEDONE),
.CFGMSGRECEIVED (delay_CFGMSGRECEIVED),
.CFGMSGRECEIVEDDATA (delay_CFGMSGRECEIVEDDATA),
.CFGMSGRECEIVEDTYPE (delay_CFGMSGRECEIVEDTYPE),
.CFGMSGTRANSMITDONE (delay_CFGMSGTRANSMITDONE),
.CFGNEGOTIATEDWIDTH (delay_CFGNEGOTIATEDWIDTH),
.CFGOBFFENABLE (delay_CFGOBFFENABLE),
.CFGPERFUNCSTATUSDATA (delay_CFGPERFUNCSTATUSDATA),
.CFGPERFUNCTIONUPDATEDONE (delay_CFGPERFUNCTIONUPDATEDONE),
.CFGPHYLINKDOWN (delay_CFGPHYLINKDOWN),
.CFGPHYLINKSTATUS (delay_CFGPHYLINKSTATUS),
.CFGPLSTATUSCHANGE (delay_CFGPLSTATUSCHANGE),
.CFGPOWERSTATECHANGEINTERRUPT (delay_CFGPOWERSTATECHANGEINTERRUPT),
.CFGRCBSTATUS (delay_CFGRCBSTATUS),
.CFGTPHFUNCTIONNUM (delay_CFGTPHFUNCTIONNUM),
.CFGTPHREQUESTERENABLE (delay_CFGTPHREQUESTERENABLE),
.CFGTPHSTMODE (delay_CFGTPHSTMODE),
.CFGTPHSTTADDRESS (delay_CFGTPHSTTADDRESS),
.CFGTPHSTTREADENABLE (delay_CFGTPHSTTREADENABLE),
.CFGTPHSTTWRITEBYTEVALID (delay_CFGTPHSTTWRITEBYTEVALID),
.CFGTPHSTTWRITEDATA (delay_CFGTPHSTTWRITEDATA),
.CFGTPHSTTWRITEENABLE (delay_CFGTPHSTTWRITEENABLE),
.CFGVFFLRINPROCESS (delay_CFGVFFLRINPROCESS),
.CFGVFPOWERSTATE (delay_CFGVFPOWERSTATE),
.CFGVFSTATUS (delay_CFGVFSTATUS),
.CFGVFTPHREQUESTERENABLE (delay_CFGVFTPHREQUESTERENABLE),
.CFGVFTPHSTMODE (delay_CFGVFTPHSTMODE),
.DBGDATAOUT (delay_DBGDATAOUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.MAXISCQTDATA (delay_MAXISCQTDATA),
.MAXISCQTKEEP (delay_MAXISCQTKEEP),
.MAXISCQTLAST (delay_MAXISCQTLAST),
.MAXISCQTUSER (delay_MAXISCQTUSER),
.MAXISCQTVALID (delay_MAXISCQTVALID),
.MAXISRCTDATA (delay_MAXISRCTDATA),
.MAXISRCTKEEP (delay_MAXISRCTKEEP),
.MAXISRCTLAST (delay_MAXISRCTLAST),
.MAXISRCTUSER (delay_MAXISRCTUSER),
.MAXISRCTVALID (delay_MAXISRCTVALID),
.MICOMPLETIONRAMREADADDRESSAL (delay_MICOMPLETIONRAMREADADDRESSAL),
.MICOMPLETIONRAMREADADDRESSAU (delay_MICOMPLETIONRAMREADADDRESSAU),
.MICOMPLETIONRAMREADADDRESSBL (delay_MICOMPLETIONRAMREADADDRESSBL),
.MICOMPLETIONRAMREADADDRESSBU (delay_MICOMPLETIONRAMREADADDRESSBU),
.MICOMPLETIONRAMREADENABLEL (delay_MICOMPLETIONRAMREADENABLEL),
.MICOMPLETIONRAMREADENABLEU (delay_MICOMPLETIONRAMREADENABLEU),
.MICOMPLETIONRAMWRITEADDRESSAL (delay_MICOMPLETIONRAMWRITEADDRESSAL),
.MICOMPLETIONRAMWRITEADDRESSAU (delay_MICOMPLETIONRAMWRITEADDRESSAU),
.MICOMPLETIONRAMWRITEADDRESSBL (delay_MICOMPLETIONRAMWRITEADDRESSBL),
.MICOMPLETIONRAMWRITEADDRESSBU (delay_MICOMPLETIONRAMWRITEADDRESSBU),
.MICOMPLETIONRAMWRITEDATAL (delay_MICOMPLETIONRAMWRITEDATAL),
.MICOMPLETIONRAMWRITEDATAU (delay_MICOMPLETIONRAMWRITEDATAU),
.MICOMPLETIONRAMWRITEENABLEL (delay_MICOMPLETIONRAMWRITEENABLEL),
.MICOMPLETIONRAMWRITEENABLEU (delay_MICOMPLETIONRAMWRITEENABLEU),
.MIREPLAYRAMADDRESS (delay_MIREPLAYRAMADDRESS),
.MIREPLAYRAMREADENABLE (delay_MIREPLAYRAMREADENABLE),
.MIREPLAYRAMWRITEDATA (delay_MIREPLAYRAMWRITEDATA),
.MIREPLAYRAMWRITEENABLE (delay_MIREPLAYRAMWRITEENABLE),
.MIREQUESTRAMREADADDRESSA (delay_MIREQUESTRAMREADADDRESSA),
.MIREQUESTRAMREADADDRESSB (delay_MIREQUESTRAMREADADDRESSB),
.MIREQUESTRAMREADENABLE (delay_MIREQUESTRAMREADENABLE),
.MIREQUESTRAMWRITEADDRESSA (delay_MIREQUESTRAMWRITEADDRESSA),
.MIREQUESTRAMWRITEADDRESSB (delay_MIREQUESTRAMWRITEADDRESSB),
.MIREQUESTRAMWRITEDATA (delay_MIREQUESTRAMWRITEDATA),
.MIREQUESTRAMWRITEENABLE (delay_MIREQUESTRAMWRITEENABLE),
.PCIECQNPREQCOUNT (delay_PCIECQNPREQCOUNT),
.PCIERQSEQNUM (delay_PCIERQSEQNUM),
.PCIERQSEQNUMVLD (delay_PCIERQSEQNUMVLD),
.PCIERQTAG (delay_PCIERQTAG),
.PCIERQTAGAV (delay_PCIERQTAGAV),
.PCIERQTAGVLD (delay_PCIERQTAGVLD),
.PCIETFCNPDAV (delay_PCIETFCNPDAV),
.PCIETFCNPHAV (delay_PCIETFCNPHAV),
.PIPERX0EQCONTROL (delay_PIPERX0EQCONTROL),
.PIPERX0EQLPLFFS (delay_PIPERX0EQLPLFFS),
.PIPERX0EQLPTXPRESET (delay_PIPERX0EQLPTXPRESET),
.PIPERX0EQPRESET (delay_PIPERX0EQPRESET),
.PIPERX0POLARITY (delay_PIPERX0POLARITY),
.PIPERX1EQCONTROL (delay_PIPERX1EQCONTROL),
.PIPERX1EQLPLFFS (delay_PIPERX1EQLPLFFS),
.PIPERX1EQLPTXPRESET (delay_PIPERX1EQLPTXPRESET),
.PIPERX1EQPRESET (delay_PIPERX1EQPRESET),
.PIPERX1POLARITY (delay_PIPERX1POLARITY),
.PIPERX2EQCONTROL (delay_PIPERX2EQCONTROL),
.PIPERX2EQLPLFFS (delay_PIPERX2EQLPLFFS),
.PIPERX2EQLPTXPRESET (delay_PIPERX2EQLPTXPRESET),
.PIPERX2EQPRESET (delay_PIPERX2EQPRESET),
.PIPERX2POLARITY (delay_PIPERX2POLARITY),
.PIPERX3EQCONTROL (delay_PIPERX3EQCONTROL),
.PIPERX3EQLPLFFS (delay_PIPERX3EQLPLFFS),
.PIPERX3EQLPTXPRESET (delay_PIPERX3EQLPTXPRESET),
.PIPERX3EQPRESET (delay_PIPERX3EQPRESET),
.PIPERX3POLARITY (delay_PIPERX3POLARITY),
.PIPERX4EQCONTROL (delay_PIPERX4EQCONTROL),
.PIPERX4EQLPLFFS (delay_PIPERX4EQLPLFFS),
.PIPERX4EQLPTXPRESET (delay_PIPERX4EQLPTXPRESET),
.PIPERX4EQPRESET (delay_PIPERX4EQPRESET),
.PIPERX4POLARITY (delay_PIPERX4POLARITY),
.PIPERX5EQCONTROL (delay_PIPERX5EQCONTROL),
.PIPERX5EQLPLFFS (delay_PIPERX5EQLPLFFS),
.PIPERX5EQLPTXPRESET (delay_PIPERX5EQLPTXPRESET),
.PIPERX5EQPRESET (delay_PIPERX5EQPRESET),
.PIPERX5POLARITY (delay_PIPERX5POLARITY),
.PIPERX6EQCONTROL (delay_PIPERX6EQCONTROL),
.PIPERX6EQLPLFFS (delay_PIPERX6EQLPLFFS),
.PIPERX6EQLPTXPRESET (delay_PIPERX6EQLPTXPRESET),
.PIPERX6EQPRESET (delay_PIPERX6EQPRESET),
.PIPERX6POLARITY (delay_PIPERX6POLARITY),
.PIPERX7EQCONTROL (delay_PIPERX7EQCONTROL),
.PIPERX7EQLPLFFS (delay_PIPERX7EQLPLFFS),
.PIPERX7EQLPTXPRESET (delay_PIPERX7EQLPTXPRESET),
.PIPERX7EQPRESET (delay_PIPERX7EQPRESET),
.PIPERX7POLARITY (delay_PIPERX7POLARITY),
.PIPETX0CHARISK (delay_PIPETX0CHARISK),
.PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE),
.PIPETX0DATA (delay_PIPETX0DATA),
.PIPETX0DATAVALID (delay_PIPETX0DATAVALID),
.PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE),
.PIPETX0EQCONTROL (delay_PIPETX0EQCONTROL),
.PIPETX0EQDEEMPH (delay_PIPETX0EQDEEMPH),
.PIPETX0EQPRESET (delay_PIPETX0EQPRESET),
.PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN),
.PIPETX0STARTBLOCK (delay_PIPETX0STARTBLOCK),
.PIPETX0SYNCHEADER (delay_PIPETX0SYNCHEADER),
.PIPETX1CHARISK (delay_PIPETX1CHARISK),
.PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE),
.PIPETX1DATA (delay_PIPETX1DATA),
.PIPETX1DATAVALID (delay_PIPETX1DATAVALID),
.PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE),
.PIPETX1EQCONTROL (delay_PIPETX1EQCONTROL),
.PIPETX1EQDEEMPH (delay_PIPETX1EQDEEMPH),
.PIPETX1EQPRESET (delay_PIPETX1EQPRESET),
.PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN),
.PIPETX1STARTBLOCK (delay_PIPETX1STARTBLOCK),
.PIPETX1SYNCHEADER (delay_PIPETX1SYNCHEADER),
.PIPETX2CHARISK (delay_PIPETX2CHARISK),
.PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE),
.PIPETX2DATA (delay_PIPETX2DATA),
.PIPETX2DATAVALID (delay_PIPETX2DATAVALID),
.PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE),
.PIPETX2EQCONTROL (delay_PIPETX2EQCONTROL),
.PIPETX2EQDEEMPH (delay_PIPETX2EQDEEMPH),
.PIPETX2EQPRESET (delay_PIPETX2EQPRESET),
.PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN),
.PIPETX2STARTBLOCK (delay_PIPETX2STARTBLOCK),
.PIPETX2SYNCHEADER (delay_PIPETX2SYNCHEADER),
.PIPETX3CHARISK (delay_PIPETX3CHARISK),
.PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE),
.PIPETX3DATA (delay_PIPETX3DATA),
.PIPETX3DATAVALID (delay_PIPETX3DATAVALID),
.PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE),
.PIPETX3EQCONTROL (delay_PIPETX3EQCONTROL),
.PIPETX3EQDEEMPH (delay_PIPETX3EQDEEMPH),
.PIPETX3EQPRESET (delay_PIPETX3EQPRESET),
.PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN),
.PIPETX3STARTBLOCK (delay_PIPETX3STARTBLOCK),
.PIPETX3SYNCHEADER (delay_PIPETX3SYNCHEADER),
.PIPETX4CHARISK (delay_PIPETX4CHARISK),
.PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE),
.PIPETX4DATA (delay_PIPETX4DATA),
.PIPETX4DATAVALID (delay_PIPETX4DATAVALID),
.PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE),
.PIPETX4EQCONTROL (delay_PIPETX4EQCONTROL),
.PIPETX4EQDEEMPH (delay_PIPETX4EQDEEMPH),
.PIPETX4EQPRESET (delay_PIPETX4EQPRESET),
.PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN),
.PIPETX4STARTBLOCK (delay_PIPETX4STARTBLOCK),
.PIPETX4SYNCHEADER (delay_PIPETX4SYNCHEADER),
.PIPETX5CHARISK (delay_PIPETX5CHARISK),
.PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE),
.PIPETX5DATA (delay_PIPETX5DATA),
.PIPETX5DATAVALID (delay_PIPETX5DATAVALID),
.PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE),
.PIPETX5EQCONTROL (delay_PIPETX5EQCONTROL),
.PIPETX5EQDEEMPH (delay_PIPETX5EQDEEMPH),
.PIPETX5EQPRESET (delay_PIPETX5EQPRESET),
.PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN),
.PIPETX5STARTBLOCK (delay_PIPETX5STARTBLOCK),
.PIPETX5SYNCHEADER (delay_PIPETX5SYNCHEADER),
.PIPETX6CHARISK (delay_PIPETX6CHARISK),
.PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE),
.PIPETX6DATA (delay_PIPETX6DATA),
.PIPETX6DATAVALID (delay_PIPETX6DATAVALID),
.PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE),
.PIPETX6EQCONTROL (delay_PIPETX6EQCONTROL),
.PIPETX6EQDEEMPH (delay_PIPETX6EQDEEMPH),
.PIPETX6EQPRESET (delay_PIPETX6EQPRESET),
.PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN),
.PIPETX6STARTBLOCK (delay_PIPETX6STARTBLOCK),
.PIPETX6SYNCHEADER (delay_PIPETX6SYNCHEADER),
.PIPETX7CHARISK (delay_PIPETX7CHARISK),
.PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE),
.PIPETX7DATA (delay_PIPETX7DATA),
.PIPETX7DATAVALID (delay_PIPETX7DATAVALID),
.PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE),
.PIPETX7EQCONTROL (delay_PIPETX7EQCONTROL),
.PIPETX7EQDEEMPH (delay_PIPETX7EQDEEMPH),
.PIPETX7EQPRESET (delay_PIPETX7EQPRESET),
.PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN),
.PIPETX7STARTBLOCK (delay_PIPETX7STARTBLOCK),
.PIPETX7SYNCHEADER (delay_PIPETX7SYNCHEADER),
.PIPETXDEEMPH (delay_PIPETXDEEMPH),
.PIPETXMARGIN (delay_PIPETXMARGIN),
.PIPETXRATE (delay_PIPETXRATE),
.PIPETXRCVRDET (delay_PIPETXRCVRDET),
.PIPETXRESET (delay_PIPETXRESET),
.PIPETXSWING (delay_PIPETXSWING),
.PLEQINPROGRESS (delay_PLEQINPROGRESS),
.PLEQPHASE (delay_PLEQPHASE),
.PLGEN3PCSRXSLIDE (delay_PLGEN3PCSRXSLIDE),
.SAXISCCTREADY (delay_SAXISCCTREADY),
.SAXISRQTREADY (delay_SAXISRQTREADY),
.CFGCONFIGSPACEENABLE (delay_CFGCONFIGSPACEENABLE),
.CFGDEVID (delay_CFGDEVID),
.CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER),
.CFGDSN (delay_CFGDSN),
.CFGDSPORTNUMBER (delay_CFGDSPORTNUMBER),
.CFGERRCORIN (delay_CFGERRCORIN),
.CFGERRUNCORIN (delay_CFGERRUNCORIN),
.CFGEXTREADDATA (delay_CFGEXTREADDATA),
.CFGEXTREADDATAVALID (delay_CFGEXTREADDATAVALID),
.CFGFCSEL (delay_CFGFCSEL),
.CFGFLRDONE (delay_CFGFLRDONE),
.CFGHOTRESETIN (delay_CFGHOTRESETIN),
.CFGINPUTUPDATEREQUEST (delay_CFGINPUTUPDATEREQUEST),
.CFGINTERRUPTINT (delay_CFGINTERRUPTINT),
.CFGINTERRUPTMSIATTR (delay_CFGINTERRUPTMSIATTR),
.CFGINTERRUPTMSIFUNCTIONNUMBER (delay_CFGINTERRUPTMSIFUNCTIONNUMBER),
.CFGINTERRUPTMSIINT (delay_CFGINTERRUPTMSIINT),
.CFGINTERRUPTMSIPENDINGSTATUS (delay_CFGINTERRUPTMSIPENDINGSTATUS),
.CFGINTERRUPTMSISELECT (delay_CFGINTERRUPTMSISELECT),
.CFGINTERRUPTMSITPHPRESENT (delay_CFGINTERRUPTMSITPHPRESENT),
.CFGINTERRUPTMSITPHSTTAG (delay_CFGINTERRUPTMSITPHSTTAG),
.CFGINTERRUPTMSITPHTYPE (delay_CFGINTERRUPTMSITPHTYPE),
.CFGINTERRUPTMSIXADDRESS (delay_CFGINTERRUPTMSIXADDRESS),
.CFGINTERRUPTMSIXDATA (delay_CFGINTERRUPTMSIXDATA),
.CFGINTERRUPTMSIXINT (delay_CFGINTERRUPTMSIXINT),
.CFGINTERRUPTPENDING (delay_CFGINTERRUPTPENDING),
.CFGLINKTRAININGENABLE (delay_CFGLINKTRAININGENABLE),
.CFGMCUPDATEREQUEST (delay_CFGMCUPDATEREQUEST),
.CFGMGMTADDR (delay_CFGMGMTADDR),
.CFGMGMTBYTEENABLE (delay_CFGMGMTBYTEENABLE),
.CFGMGMTREAD (delay_CFGMGMTREAD),
.CFGMGMTTYPE1CFGREGACCESS (delay_CFGMGMTTYPE1CFGREGACCESS),
.CFGMGMTWRITE (delay_CFGMGMTWRITE),
.CFGMGMTWRITEDATA (delay_CFGMGMTWRITEDATA),
.CFGMSGTRANSMIT (delay_CFGMSGTRANSMIT),
.CFGMSGTRANSMITDATA (delay_CFGMSGTRANSMITDATA),
.CFGMSGTRANSMITTYPE (delay_CFGMSGTRANSMITTYPE),
.CFGPERFUNCSTATUSCONTROL (delay_CFGPERFUNCSTATUSCONTROL),
.CFGPERFUNCTIONNUMBER (delay_CFGPERFUNCTIONNUMBER),
.CFGPERFUNCTIONOUTPUTREQUEST (delay_CFGPERFUNCTIONOUTPUTREQUEST),
.CFGPOWERSTATECHANGEACK (delay_CFGPOWERSTATECHANGEACK),
.CFGREQPMTRANSITIONL23READY (delay_CFGREQPMTRANSITIONL23READY),
.CFGREVID (delay_CFGREVID),
.CFGSUBSYSID (delay_CFGSUBSYSID),
.CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID),
.CFGTPHSTTREADDATA (delay_CFGTPHSTTREADDATA),
.CFGTPHSTTREADDATAVALID (delay_CFGTPHSTTREADDATAVALID),
.CFGVENDID (delay_CFGVENDID),
.CFGVFFLRDONE (delay_CFGVFFLRDONE),
.CORECLK (delay_CORECLK),
.CORECLKMICOMPLETIONRAML (delay_CORECLKMICOMPLETIONRAML),
.CORECLKMICOMPLETIONRAMU (delay_CORECLKMICOMPLETIONRAMU),
.CORECLKMIREPLAYRAM (delay_CORECLKMIREPLAYRAM),
.CORECLKMIREQUESTRAM (delay_CORECLKMIREQUESTRAM),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.MAXISCQTREADY (delay_MAXISCQTREADY),
.MAXISRCTREADY (delay_MAXISRCTREADY),
.MGMTRESETN (delay_MGMTRESETN),
.MGMTSTICKYRESETN (delay_MGMTSTICKYRESETN),
.MICOMPLETIONRAMREADDATA (delay_MICOMPLETIONRAMREADDATA),
.MIREPLAYRAMREADDATA (delay_MIREPLAYRAMREADDATA),
.MIREQUESTRAMREADDATA (delay_MIREQUESTRAMREADDATA),
.PCIECQNPREQ (delay_PCIECQNPREQ),
.PIPECLK (delay_PIPECLK),
.PIPEEQFS (delay_PIPEEQFS),
.PIPEEQLF (delay_PIPEEQLF),
.PIPERESETN (delay_PIPERESETN),
.PIPERX0CHARISK (delay_PIPERX0CHARISK),
.PIPERX0DATA (delay_PIPERX0DATA),
.PIPERX0DATAVALID (delay_PIPERX0DATAVALID),
.PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE),
.PIPERX0EQDONE (delay_PIPERX0EQDONE),
.PIPERX0EQLPADAPTDONE (delay_PIPERX0EQLPADAPTDONE),
.PIPERX0EQLPLFFSSEL (delay_PIPERX0EQLPLFFSSEL),
.PIPERX0EQLPNEWTXCOEFFORPRESET (delay_PIPERX0EQLPNEWTXCOEFFORPRESET),
.PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS),
.PIPERX0STARTBLOCK (delay_PIPERX0STARTBLOCK),
.PIPERX0STATUS (delay_PIPERX0STATUS),
.PIPERX0SYNCHEADER (delay_PIPERX0SYNCHEADER),
.PIPERX0VALID (delay_PIPERX0VALID),
.PIPERX1CHARISK (delay_PIPERX1CHARISK),
.PIPERX1DATA (delay_PIPERX1DATA),
.PIPERX1DATAVALID (delay_PIPERX1DATAVALID),
.PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE),
.PIPERX1EQDONE (delay_PIPERX1EQDONE),
.PIPERX1EQLPADAPTDONE (delay_PIPERX1EQLPADAPTDONE),
.PIPERX1EQLPLFFSSEL (delay_PIPERX1EQLPLFFSSEL),
.PIPERX1EQLPNEWTXCOEFFORPRESET (delay_PIPERX1EQLPNEWTXCOEFFORPRESET),
.PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS),
.PIPERX1STARTBLOCK (delay_PIPERX1STARTBLOCK),
.PIPERX1STATUS (delay_PIPERX1STATUS),
.PIPERX1SYNCHEADER (delay_PIPERX1SYNCHEADER),
.PIPERX1VALID (delay_PIPERX1VALID),
.PIPERX2CHARISK (delay_PIPERX2CHARISK),
.PIPERX2DATA (delay_PIPERX2DATA),
.PIPERX2DATAVALID (delay_PIPERX2DATAVALID),
.PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE),
.PIPERX2EQDONE (delay_PIPERX2EQDONE),
.PIPERX2EQLPADAPTDONE (delay_PIPERX2EQLPADAPTDONE),
.PIPERX2EQLPLFFSSEL (delay_PIPERX2EQLPLFFSSEL),
.PIPERX2EQLPNEWTXCOEFFORPRESET (delay_PIPERX2EQLPNEWTXCOEFFORPRESET),
.PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS),
.PIPERX2STARTBLOCK (delay_PIPERX2STARTBLOCK),
.PIPERX2STATUS (delay_PIPERX2STATUS),
.PIPERX2SYNCHEADER (delay_PIPERX2SYNCHEADER),
.PIPERX2VALID (delay_PIPERX2VALID),
.PIPERX3CHARISK (delay_PIPERX3CHARISK),
.PIPERX3DATA (delay_PIPERX3DATA),
.PIPERX3DATAVALID (delay_PIPERX3DATAVALID),
.PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE),
.PIPERX3EQDONE (delay_PIPERX3EQDONE),
.PIPERX3EQLPADAPTDONE (delay_PIPERX3EQLPADAPTDONE),
.PIPERX3EQLPLFFSSEL (delay_PIPERX3EQLPLFFSSEL),
.PIPERX3EQLPNEWTXCOEFFORPRESET (delay_PIPERX3EQLPNEWTXCOEFFORPRESET),
.PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS),
.PIPERX3STARTBLOCK (delay_PIPERX3STARTBLOCK),
.PIPERX3STATUS (delay_PIPERX3STATUS),
.PIPERX3SYNCHEADER (delay_PIPERX3SYNCHEADER),
.PIPERX3VALID (delay_PIPERX3VALID),
.PIPERX4CHARISK (delay_PIPERX4CHARISK),
.PIPERX4DATA (delay_PIPERX4DATA),
.PIPERX4DATAVALID (delay_PIPERX4DATAVALID),
.PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE),
.PIPERX4EQDONE (delay_PIPERX4EQDONE),
.PIPERX4EQLPADAPTDONE (delay_PIPERX4EQLPADAPTDONE),
.PIPERX4EQLPLFFSSEL (delay_PIPERX4EQLPLFFSSEL),
.PIPERX4EQLPNEWTXCOEFFORPRESET (delay_PIPERX4EQLPNEWTXCOEFFORPRESET),
.PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS),
.PIPERX4STARTBLOCK (delay_PIPERX4STARTBLOCK),
.PIPERX4STATUS (delay_PIPERX4STATUS),
.PIPERX4SYNCHEADER (delay_PIPERX4SYNCHEADER),
.PIPERX4VALID (delay_PIPERX4VALID),
.PIPERX5CHARISK (delay_PIPERX5CHARISK),
.PIPERX5DATA (delay_PIPERX5DATA),
.PIPERX5DATAVALID (delay_PIPERX5DATAVALID),
.PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE),
.PIPERX5EQDONE (delay_PIPERX5EQDONE),
.PIPERX5EQLPADAPTDONE (delay_PIPERX5EQLPADAPTDONE),
.PIPERX5EQLPLFFSSEL (delay_PIPERX5EQLPLFFSSEL),
.PIPERX5EQLPNEWTXCOEFFORPRESET (delay_PIPERX5EQLPNEWTXCOEFFORPRESET),
.PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS),
.PIPERX5STARTBLOCK (delay_PIPERX5STARTBLOCK),
.PIPERX5STATUS (delay_PIPERX5STATUS),
.PIPERX5SYNCHEADER (delay_PIPERX5SYNCHEADER),
.PIPERX5VALID (delay_PIPERX5VALID),
.PIPERX6CHARISK (delay_PIPERX6CHARISK),
.PIPERX6DATA (delay_PIPERX6DATA),
.PIPERX6DATAVALID (delay_PIPERX6DATAVALID),
.PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE),
.PIPERX6EQDONE (delay_PIPERX6EQDONE),
.PIPERX6EQLPADAPTDONE (delay_PIPERX6EQLPADAPTDONE),
.PIPERX6EQLPLFFSSEL (delay_PIPERX6EQLPLFFSSEL),
.PIPERX6EQLPNEWTXCOEFFORPRESET (delay_PIPERX6EQLPNEWTXCOEFFORPRESET),
.PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS),
.PIPERX6STARTBLOCK (delay_PIPERX6STARTBLOCK),
.PIPERX6STATUS (delay_PIPERX6STATUS),
.PIPERX6SYNCHEADER (delay_PIPERX6SYNCHEADER),
.PIPERX6VALID (delay_PIPERX6VALID),
.PIPERX7CHARISK (delay_PIPERX7CHARISK),
.PIPERX7DATA (delay_PIPERX7DATA),
.PIPERX7DATAVALID (delay_PIPERX7DATAVALID),
.PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE),
.PIPERX7EQDONE (delay_PIPERX7EQDONE),
.PIPERX7EQLPADAPTDONE (delay_PIPERX7EQLPADAPTDONE),
.PIPERX7EQLPLFFSSEL (delay_PIPERX7EQLPLFFSSEL),
.PIPERX7EQLPNEWTXCOEFFORPRESET (delay_PIPERX7EQLPNEWTXCOEFFORPRESET),
.PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS),
.PIPERX7STARTBLOCK (delay_PIPERX7STARTBLOCK),
.PIPERX7STATUS (delay_PIPERX7STATUS),
.PIPERX7SYNCHEADER (delay_PIPERX7SYNCHEADER),
.PIPERX7VALID (delay_PIPERX7VALID),
.PIPETX0EQCOEFF (delay_PIPETX0EQCOEFF),
.PIPETX0EQDONE (delay_PIPETX0EQDONE),
.PIPETX1EQCOEFF (delay_PIPETX1EQCOEFF),
.PIPETX1EQDONE (delay_PIPETX1EQDONE),
.PIPETX2EQCOEFF (delay_PIPETX2EQCOEFF),
.PIPETX2EQDONE (delay_PIPETX2EQDONE),
.PIPETX3EQCOEFF (delay_PIPETX3EQCOEFF),
.PIPETX3EQDONE (delay_PIPETX3EQDONE),
.PIPETX4EQCOEFF (delay_PIPETX4EQCOEFF),
.PIPETX4EQDONE (delay_PIPETX4EQDONE),
.PIPETX5EQCOEFF (delay_PIPETX5EQCOEFF),
.PIPETX5EQDONE (delay_PIPETX5EQDONE),
.PIPETX6EQCOEFF (delay_PIPETX6EQCOEFF),
.PIPETX6EQDONE (delay_PIPETX6EQDONE),
.PIPETX7EQCOEFF (delay_PIPETX7EQCOEFF),
.PIPETX7EQDONE (delay_PIPETX7EQDONE),
.PLDISABLESCRAMBLER (delay_PLDISABLESCRAMBLER),
.PLEQRESETEIEOSCOUNT (delay_PLEQRESETEIEOSCOUNT),
.PLGEN3PCSDISABLE (delay_PLGEN3PCSDISABLE),
.PLGEN3PCSRXSYNCDONE (delay_PLGEN3PCSRXSYNCDONE),
.RECCLK (delay_RECCLK),
.RESETN (delay_RESETN),
.SAXISCCTDATA (delay_SAXISCCTDATA),
.SAXISCCTKEEP (delay_SAXISCCTKEEP),
.SAXISCCTLAST (delay_SAXISCCTLAST),
.SAXISCCTUSER (delay_SAXISCCTUSER),
.SAXISCCTVALID (delay_SAXISCCTVALID),
.SAXISRQTDATA (delay_SAXISRQTDATA),
.SAXISRQTKEEP (delay_SAXISRQTKEEP),
.SAXISRQTLAST (delay_SAXISRQTLAST),
.SAXISRQTUSER (delay_SAXISRQTUSER),
.SAXISRQTVALID (delay_SAXISRQTVALID),
.USERCLK (delay_USERCLK)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CORECLK, 0:0:0, notifier);
$period (posedge CORECLKMICOMPLETIONRAML, 0:0:0, notifier);
$period (posedge CORECLKMICOMPLETIONRAMU, 0:0:0, notifier);
$period (posedge CORECLKMIREPLAYRAM, 0:0:0, notifier);
$period (posedge CORECLKMIREQUESTRAM, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge PIPECLK, 0:0:0, notifier);
$period (posedge RECCLK, 0:0:0, notifier);
$period (posedge USERCLK, 0:0:0, notifier);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE);
$setuphold (posedge PIPECLK, negedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER);
$setuphold (posedge PIPECLK, negedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT);
$setuphold (posedge PIPECLK, negedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE);
$setuphold (posedge PIPECLK, posedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER);
$setuphold (posedge PIPECLK, posedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT);
$setuphold (posedge PIPECLK, posedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE);
$setuphold (posedge RECCLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID);
$setuphold (posedge RECCLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID);
$setuphold (posedge RECCLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID);
$setuphold (posedge RECCLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID);
$setuphold (posedge RECCLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID);
$setuphold (posedge RECCLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID);
$setuphold (posedge RECCLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID);
$setuphold (posedge RECCLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]);
$setuphold (posedge RECCLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID);
$setuphold (posedge RECCLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID);
$setuphold (posedge RECCLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID);
$setuphold (posedge RECCLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID);
$setuphold (posedge RECCLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID);
$setuphold (posedge RECCLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID);
$setuphold (posedge RECCLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID);
$setuphold (posedge RECCLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]);
$setuphold (posedge USERCLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE);
$setuphold (posedge USERCLK, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]);
$setuphold (posedge USERCLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]);
$setuphold (posedge USERCLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]);
$setuphold (posedge USERCLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]);
$setuphold (posedge USERCLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]);
$setuphold (posedge USERCLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]);
$setuphold (posedge USERCLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]);
$setuphold (posedge USERCLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]);
$setuphold (posedge USERCLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]);
$setuphold (posedge USERCLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]);
$setuphold (posedge USERCLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]);
$setuphold (posedge USERCLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]);
$setuphold (posedge USERCLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]);
$setuphold (posedge USERCLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]);
$setuphold (posedge USERCLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]);
$setuphold (posedge USERCLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]);
$setuphold (posedge USERCLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]);
$setuphold (posedge USERCLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]);
$setuphold (posedge USERCLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]);
$setuphold (posedge USERCLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]);
$setuphold (posedge USERCLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]);
$setuphold (posedge USERCLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]);
$setuphold (posedge USERCLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]);
$setuphold (posedge USERCLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]);
$setuphold (posedge USERCLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]);
$setuphold (posedge USERCLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]);
$setuphold (posedge USERCLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]);
$setuphold (posedge USERCLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]);
$setuphold (posedge USERCLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]);
$setuphold (posedge USERCLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]);
$setuphold (posedge USERCLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]);
$setuphold (posedge USERCLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]);
$setuphold (posedge USERCLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]);
$setuphold (posedge USERCLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]);
$setuphold (posedge USERCLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]);
$setuphold (posedge USERCLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]);
$setuphold (posedge USERCLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]);
$setuphold (posedge USERCLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]);
$setuphold (posedge USERCLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]);
$setuphold (posedge USERCLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]);
$setuphold (posedge USERCLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]);
$setuphold (posedge USERCLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]);
$setuphold (posedge USERCLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]);
$setuphold (posedge USERCLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]);
$setuphold (posedge USERCLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]);
$setuphold (posedge USERCLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]);
$setuphold (posedge USERCLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]);
$setuphold (posedge USERCLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]);
$setuphold (posedge USERCLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]);
$setuphold (posedge USERCLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]);
$setuphold (posedge USERCLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]);
$setuphold (posedge USERCLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]);
$setuphold (posedge USERCLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]);
$setuphold (posedge USERCLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]);
$setuphold (posedge USERCLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]);
$setuphold (posedge USERCLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]);
$setuphold (posedge USERCLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]);
$setuphold (posedge USERCLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]);
$setuphold (posedge USERCLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]);
$setuphold (posedge USERCLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]);
$setuphold (posedge USERCLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]);
$setuphold (posedge USERCLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]);
$setuphold (posedge USERCLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]);
$setuphold (posedge USERCLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN);
$setuphold (posedge USERCLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]);
$setuphold (posedge USERCLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN);
$setuphold (posedge USERCLK, negedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]);
$setuphold (posedge USERCLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE);
$setuphold (posedge USERCLK, negedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD);
$setuphold (posedge USERCLK, negedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST);
$setuphold (posedge USERCLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK);
$setuphold (posedge USERCLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY);
$setuphold (posedge USERCLK, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]);
$setuphold (posedge USERCLK, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]);
$setuphold (posedge USERCLK, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]);
$setuphold (posedge USERCLK, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]);
$setuphold (posedge USERCLK, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]);
$setuphold (posedge USERCLK, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]);
$setuphold (posedge USERCLK, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]);
$setuphold (posedge USERCLK, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]);
$setuphold (posedge USERCLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]);
$setuphold (posedge USERCLK, negedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID);
$setuphold (posedge USERCLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE);
$setuphold (posedge USERCLK, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]);
$setuphold (posedge USERCLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]);
$setuphold (posedge USERCLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]);
$setuphold (posedge USERCLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]);
$setuphold (posedge USERCLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]);
$setuphold (posedge USERCLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]);
$setuphold (posedge USERCLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]);
$setuphold (posedge USERCLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]);
$setuphold (posedge USERCLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]);
$setuphold (posedge USERCLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]);
$setuphold (posedge USERCLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]);
$setuphold (posedge USERCLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]);
$setuphold (posedge USERCLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]);
$setuphold (posedge USERCLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]);
$setuphold (posedge USERCLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]);
$setuphold (posedge USERCLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]);
$setuphold (posedge USERCLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]);
$setuphold (posedge USERCLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]);
$setuphold (posedge USERCLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]);
$setuphold (posedge USERCLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]);
$setuphold (posedge USERCLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]);
$setuphold (posedge USERCLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]);
$setuphold (posedge USERCLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]);
$setuphold (posedge USERCLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]);
$setuphold (posedge USERCLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]);
$setuphold (posedge USERCLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]);
$setuphold (posedge USERCLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]);
$setuphold (posedge USERCLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]);
$setuphold (posedge USERCLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]);
$setuphold (posedge USERCLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]);
$setuphold (posedge USERCLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]);
$setuphold (posedge USERCLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]);
$setuphold (posedge USERCLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]);
$setuphold (posedge USERCLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]);
$setuphold (posedge USERCLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]);
$setuphold (posedge USERCLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]);
$setuphold (posedge USERCLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]);
$setuphold (posedge USERCLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]);
$setuphold (posedge USERCLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]);
$setuphold (posedge USERCLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]);
$setuphold (posedge USERCLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]);
$setuphold (posedge USERCLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]);
$setuphold (posedge USERCLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]);
$setuphold (posedge USERCLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]);
$setuphold (posedge USERCLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]);
$setuphold (posedge USERCLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]);
$setuphold (posedge USERCLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]);
$setuphold (posedge USERCLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]);
$setuphold (posedge USERCLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]);
$setuphold (posedge USERCLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]);
$setuphold (posedge USERCLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]);
$setuphold (posedge USERCLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]);
$setuphold (posedge USERCLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]);
$setuphold (posedge USERCLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]);
$setuphold (posedge USERCLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]);
$setuphold (posedge USERCLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]);
$setuphold (posedge USERCLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]);
$setuphold (posedge USERCLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]);
$setuphold (posedge USERCLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]);
$setuphold (posedge USERCLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]);
$setuphold (posedge USERCLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]);
$setuphold (posedge USERCLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]);
$setuphold (posedge USERCLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]);
$setuphold (posedge USERCLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN);
$setuphold (posedge USERCLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]);
$setuphold (posedge USERCLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN);
$setuphold (posedge USERCLK, posedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]);
$setuphold (posedge USERCLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE);
$setuphold (posedge USERCLK, posedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD);
$setuphold (posedge USERCLK, posedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST);
$setuphold (posedge USERCLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK);
$setuphold (posedge USERCLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY);
$setuphold (posedge USERCLK, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]);
$setuphold (posedge USERCLK, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]);
$setuphold (posedge USERCLK, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]);
$setuphold (posedge USERCLK, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]);
$setuphold (posedge USERCLK, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]);
$setuphold (posedge USERCLK, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]);
$setuphold (posedge USERCLK, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]);
$setuphold (posedge USERCLK, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]);
$setuphold (posedge USERCLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]);
$setuphold (posedge USERCLK, posedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID);
`endif
( CORECLK *> DBGDATAOUT[0]) = (0, 0);
( CORECLK *> DBGDATAOUT[10]) = (0, 0);
( CORECLK *> DBGDATAOUT[11]) = (0, 0);
( CORECLK *> DBGDATAOUT[12]) = (0, 0);
( CORECLK *> DBGDATAOUT[13]) = (0, 0);
( CORECLK *> DBGDATAOUT[14]) = (0, 0);
( CORECLK *> DBGDATAOUT[15]) = (0, 0);
( CORECLK *> DBGDATAOUT[1]) = (0, 0);
( CORECLK *> DBGDATAOUT[2]) = (0, 0);
( CORECLK *> DBGDATAOUT[3]) = (0, 0);
( CORECLK *> DBGDATAOUT[4]) = (0, 0);
( CORECLK *> DBGDATAOUT[5]) = (0, 0);
( CORECLK *> DBGDATAOUT[6]) = (0, 0);
( CORECLK *> DBGDATAOUT[7]) = (0, 0);
( CORECLK *> DBGDATAOUT[8]) = (0, 0);
( CORECLK *> DBGDATAOUT[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[10]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[11]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[12]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[13]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[14]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[15]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[16]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[17]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[18]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[19]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[20]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[21]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[22]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[23]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[24]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[25]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[26]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[27]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[28]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[29]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[30]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[31]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[32]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[33]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[34]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[35]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[36]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[37]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[38]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[39]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[40]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[41]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[42]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[43]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[44]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[45]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[46]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[47]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[48]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[49]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[50]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[51]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[52]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[53]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[54]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[55]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[56]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[57]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[58]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[59]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[60]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[61]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[62]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[63]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[64]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[65]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[66]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[67]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[68]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[69]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[70]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[71]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[10]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[11]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[12]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[13]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[14]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[15]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[16]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[17]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[18]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[19]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[20]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[21]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[22]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[23]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[24]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[25]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[26]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[27]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[28]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[29]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[30]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[31]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[32]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[33]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[34]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[35]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[36]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[37]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[38]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[39]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[40]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[41]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[42]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[43]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[44]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[45]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[46]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[47]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[48]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[49]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[50]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[51]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[52]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[53]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[54]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[55]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[56]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[57]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[58]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[59]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[60]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[61]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[62]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[63]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[64]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[65]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[66]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[67]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[68]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[69]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[70]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[71]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[2]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[4]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[5]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[6]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[7]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[8]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[100]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[101]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[102]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[103]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[104]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[105]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[106]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[107]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[108]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[109]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[10]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[110]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[111]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[112]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[113]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[114]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[115]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[116]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[117]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[118]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[119]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[11]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[120]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[121]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[122]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[123]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[124]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[125]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[126]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[127]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[128]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[129]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[12]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[130]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[131]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[132]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[133]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[134]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[135]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[136]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[137]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[138]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[139]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[13]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[140]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[141]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[142]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[143]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[14]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[15]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[16]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[17]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[18]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[19]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[20]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[21]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[22]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[23]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[24]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[25]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[26]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[27]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[28]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[29]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[2]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[30]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[31]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[32]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[33]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[34]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[35]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[36]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[37]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[38]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[39]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[40]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[41]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[42]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[43]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[44]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[45]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[46]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[47]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[48]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[49]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[4]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[50]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[51]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[52]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[53]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[54]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[55]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[56]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[57]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[58]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[59]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[5]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[60]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[61]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[62]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[63]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[64]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[65]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[66]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[67]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[68]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[69]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[6]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[70]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[71]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[72]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[73]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[74]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[75]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[76]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[77]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[78]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[79]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[7]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[80]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[81]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[82]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[83]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[84]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[85]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[86]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[87]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[88]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[89]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[8]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[90]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[91]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[92]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[93]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[94]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[95]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[96]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[97]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[98]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[99]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[9]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[100]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[101]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[102]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[103]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[104]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[105]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[106]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[107]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[108]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[109]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[10]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[110]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[111]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[112]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[113]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[114]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[115]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[116]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[117]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[118]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[119]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[11]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[120]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[121]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[122]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[123]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[124]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[125]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[126]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[127]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[128]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[129]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[12]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[130]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[131]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[132]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[133]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[134]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[135]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[136]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[137]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[138]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[139]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[13]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[140]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[141]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[142]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[143]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[14]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[15]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[16]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[17]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[18]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[19]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[20]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[21]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[22]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[23]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[24]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[25]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[26]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[27]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[28]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[29]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[30]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[31]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[32]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[33]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[34]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[35]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[36]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[37]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[38]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[39]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[40]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[41]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[42]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[43]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[44]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[45]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[46]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[47]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[48]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[49]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[50]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[51]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[52]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[53]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[54]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[55]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[56]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[57]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[58]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[59]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[60]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[61]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[62]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[63]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[64]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[65]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[66]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[67]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[68]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[69]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[70]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[71]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[72]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[73]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[74]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[75]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[76]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[77]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[78]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[79]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[80]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[81]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[82]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[83]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[84]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[85]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[86]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[87]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[88]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[89]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[90]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[91]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[92]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[93]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[94]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[95]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[96]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[97]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[98]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[99]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[9]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[3]) = (0, 0);
( DRPCLK *> DRPDO[0]) = (0, 0);
( DRPCLK *> DRPDO[10]) = (0, 0);
( DRPCLK *> DRPDO[11]) = (0, 0);
( DRPCLK *> DRPDO[12]) = (0, 0);
( DRPCLK *> DRPDO[13]) = (0, 0);
( DRPCLK *> DRPDO[14]) = (0, 0);
( DRPCLK *> DRPDO[15]) = (0, 0);
( DRPCLK *> DRPDO[1]) = (0, 0);
( DRPCLK *> DRPDO[2]) = (0, 0);
( DRPCLK *> DRPDO[3]) = (0, 0);
( DRPCLK *> DRPDO[4]) = (0, 0);
( DRPCLK *> DRPDO[5]) = (0, 0);
( DRPCLK *> DRPDO[6]) = (0, 0);
( DRPCLK *> DRPDO[7]) = (0, 0);
( DRPCLK *> DRPDO[8]) = (0, 0);
( DRPCLK *> DRPDO[9]) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( PIPECLK *> PIPERX0EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX0EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX0POLARITY) = (0, 0);
( PIPECLK *> PIPERX1EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX1EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX1POLARITY) = (0, 0);
( PIPECLK *> PIPERX2EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX2EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX2POLARITY) = (0, 0);
( PIPECLK *> PIPERX3EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX3EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX3POLARITY) = (0, 0);
( PIPECLK *> PIPERX4EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX4EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX4POLARITY) = (0, 0);
( PIPECLK *> PIPERX5EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX5EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX5POLARITY) = (0, 0);
( PIPECLK *> PIPERX6EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX6EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX6POLARITY) = (0, 0);
( PIPECLK *> PIPERX7EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX7EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX7POLARITY) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX0DATAVALID) = (0, 0);
( PIPECLK *> PIPETX0DATA[0]) = (0, 0);
( PIPECLK *> PIPETX0DATA[10]) = (0, 0);
( PIPECLK *> PIPETX0DATA[11]) = (0, 0);
( PIPECLK *> PIPETX0DATA[12]) = (0, 0);
( PIPECLK *> PIPETX0DATA[13]) = (0, 0);
( PIPECLK *> PIPETX0DATA[14]) = (0, 0);
( PIPECLK *> PIPETX0DATA[15]) = (0, 0);
( PIPECLK *> PIPETX0DATA[16]) = (0, 0);
( PIPECLK *> PIPETX0DATA[17]) = (0, 0);
( PIPECLK *> PIPETX0DATA[18]) = (0, 0);
( PIPECLK *> PIPETX0DATA[19]) = (0, 0);
( PIPECLK *> PIPETX0DATA[1]) = (0, 0);
( PIPECLK *> PIPETX0DATA[20]) = (0, 0);
( PIPECLK *> PIPETX0DATA[21]) = (0, 0);
( PIPECLK *> PIPETX0DATA[22]) = (0, 0);
( PIPECLK *> PIPETX0DATA[23]) = (0, 0);
( PIPECLK *> PIPETX0DATA[24]) = (0, 0);
( PIPECLK *> PIPETX0DATA[25]) = (0, 0);
( PIPECLK *> PIPETX0DATA[26]) = (0, 0);
( PIPECLK *> PIPETX0DATA[27]) = (0, 0);
( PIPECLK *> PIPETX0DATA[28]) = (0, 0);
( PIPECLK *> PIPETX0DATA[29]) = (0, 0);
( PIPECLK *> PIPETX0DATA[2]) = (0, 0);
( PIPECLK *> PIPETX0DATA[30]) = (0, 0);
( PIPECLK *> PIPETX0DATA[31]) = (0, 0);
( PIPECLK *> PIPETX0DATA[3]) = (0, 0);
( PIPECLK *> PIPETX0DATA[4]) = (0, 0);
( PIPECLK *> PIPETX0DATA[5]) = (0, 0);
( PIPECLK *> PIPETX0DATA[6]) = (0, 0);
( PIPECLK *> PIPETX0DATA[7]) = (0, 0);
( PIPECLK *> PIPETX0DATA[8]) = (0, 0);
( PIPECLK *> PIPETX0DATA[9]) = (0, 0);
( PIPECLK *> PIPETX0ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX0EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX0EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX0STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX0SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX0SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX1DATAVALID) = (0, 0);
( PIPECLK *> PIPETX1DATA[0]) = (0, 0);
( PIPECLK *> PIPETX1DATA[10]) = (0, 0);
( PIPECLK *> PIPETX1DATA[11]) = (0, 0);
( PIPECLK *> PIPETX1DATA[12]) = (0, 0);
( PIPECLK *> PIPETX1DATA[13]) = (0, 0);
( PIPECLK *> PIPETX1DATA[14]) = (0, 0);
( PIPECLK *> PIPETX1DATA[15]) = (0, 0);
( PIPECLK *> PIPETX1DATA[16]) = (0, 0);
( PIPECLK *> PIPETX1DATA[17]) = (0, 0);
( PIPECLK *> PIPETX1DATA[18]) = (0, 0);
( PIPECLK *> PIPETX1DATA[19]) = (0, 0);
( PIPECLK *> PIPETX1DATA[1]) = (0, 0);
( PIPECLK *> PIPETX1DATA[20]) = (0, 0);
( PIPECLK *> PIPETX1DATA[21]) = (0, 0);
( PIPECLK *> PIPETX1DATA[22]) = (0, 0);
( PIPECLK *> PIPETX1DATA[23]) = (0, 0);
( PIPECLK *> PIPETX1DATA[24]) = (0, 0);
( PIPECLK *> PIPETX1DATA[25]) = (0, 0);
( PIPECLK *> PIPETX1DATA[26]) = (0, 0);
( PIPECLK *> PIPETX1DATA[27]) = (0, 0);
( PIPECLK *> PIPETX1DATA[28]) = (0, 0);
( PIPECLK *> PIPETX1DATA[29]) = (0, 0);
( PIPECLK *> PIPETX1DATA[2]) = (0, 0);
( PIPECLK *> PIPETX1DATA[30]) = (0, 0);
( PIPECLK *> PIPETX1DATA[31]) = (0, 0);
( PIPECLK *> PIPETX1DATA[3]) = (0, 0);
( PIPECLK *> PIPETX1DATA[4]) = (0, 0);
( PIPECLK *> PIPETX1DATA[5]) = (0, 0);
( PIPECLK *> PIPETX1DATA[6]) = (0, 0);
( PIPECLK *> PIPETX1DATA[7]) = (0, 0);
( PIPECLK *> PIPETX1DATA[8]) = (0, 0);
( PIPECLK *> PIPETX1DATA[9]) = (0, 0);
( PIPECLK *> PIPETX1ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX1EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX1EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX1STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX1SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX1SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX2DATAVALID) = (0, 0);
( PIPECLK *> PIPETX2DATA[0]) = (0, 0);
( PIPECLK *> PIPETX2DATA[10]) = (0, 0);
( PIPECLK *> PIPETX2DATA[11]) = (0, 0);
( PIPECLK *> PIPETX2DATA[12]) = (0, 0);
( PIPECLK *> PIPETX2DATA[13]) = (0, 0);
( PIPECLK *> PIPETX2DATA[14]) = (0, 0);
( PIPECLK *> PIPETX2DATA[15]) = (0, 0);
( PIPECLK *> PIPETX2DATA[16]) = (0, 0);
( PIPECLK *> PIPETX2DATA[17]) = (0, 0);
( PIPECLK *> PIPETX2DATA[18]) = (0, 0);
( PIPECLK *> PIPETX2DATA[19]) = (0, 0);
( PIPECLK *> PIPETX2DATA[1]) = (0, 0);
( PIPECLK *> PIPETX2DATA[20]) = (0, 0);
( PIPECLK *> PIPETX2DATA[21]) = (0, 0);
( PIPECLK *> PIPETX2DATA[22]) = (0, 0);
( PIPECLK *> PIPETX2DATA[23]) = (0, 0);
( PIPECLK *> PIPETX2DATA[24]) = (0, 0);
( PIPECLK *> PIPETX2DATA[25]) = (0, 0);
( PIPECLK *> PIPETX2DATA[26]) = (0, 0);
( PIPECLK *> PIPETX2DATA[27]) = (0, 0);
( PIPECLK *> PIPETX2DATA[28]) = (0, 0);
( PIPECLK *> PIPETX2DATA[29]) = (0, 0);
( PIPECLK *> PIPETX2DATA[2]) = (0, 0);
( PIPECLK *> PIPETX2DATA[30]) = (0, 0);
( PIPECLK *> PIPETX2DATA[31]) = (0, 0);
( PIPECLK *> PIPETX2DATA[3]) = (0, 0);
( PIPECLK *> PIPETX2DATA[4]) = (0, 0);
( PIPECLK *> PIPETX2DATA[5]) = (0, 0);
( PIPECLK *> PIPETX2DATA[6]) = (0, 0);
( PIPECLK *> PIPETX2DATA[7]) = (0, 0);
( PIPECLK *> PIPETX2DATA[8]) = (0, 0);
( PIPECLK *> PIPETX2DATA[9]) = (0, 0);
( PIPECLK *> PIPETX2ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX2EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX2EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX2STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX2SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX2SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX3DATAVALID) = (0, 0);
( PIPECLK *> PIPETX3DATA[0]) = (0, 0);
( PIPECLK *> PIPETX3DATA[10]) = (0, 0);
( PIPECLK *> PIPETX3DATA[11]) = (0, 0);
( PIPECLK *> PIPETX3DATA[12]) = (0, 0);
( PIPECLK *> PIPETX3DATA[13]) = (0, 0);
( PIPECLK *> PIPETX3DATA[14]) = (0, 0);
( PIPECLK *> PIPETX3DATA[15]) = (0, 0);
( PIPECLK *> PIPETX3DATA[16]) = (0, 0);
( PIPECLK *> PIPETX3DATA[17]) = (0, 0);
( PIPECLK *> PIPETX3DATA[18]) = (0, 0);
( PIPECLK *> PIPETX3DATA[19]) = (0, 0);
( PIPECLK *> PIPETX3DATA[1]) = (0, 0);
( PIPECLK *> PIPETX3DATA[20]) = (0, 0);
( PIPECLK *> PIPETX3DATA[21]) = (0, 0);
( PIPECLK *> PIPETX3DATA[22]) = (0, 0);
( PIPECLK *> PIPETX3DATA[23]) = (0, 0);
( PIPECLK *> PIPETX3DATA[24]) = (0, 0);
( PIPECLK *> PIPETX3DATA[25]) = (0, 0);
( PIPECLK *> PIPETX3DATA[26]) = (0, 0);
( PIPECLK *> PIPETX3DATA[27]) = (0, 0);
( PIPECLK *> PIPETX3DATA[28]) = (0, 0);
( PIPECLK *> PIPETX3DATA[29]) = (0, 0);
( PIPECLK *> PIPETX3DATA[2]) = (0, 0);
( PIPECLK *> PIPETX3DATA[30]) = (0, 0);
( PIPECLK *> PIPETX3DATA[31]) = (0, 0);
( PIPECLK *> PIPETX3DATA[3]) = (0, 0);
( PIPECLK *> PIPETX3DATA[4]) = (0, 0);
( PIPECLK *> PIPETX3DATA[5]) = (0, 0);
( PIPECLK *> PIPETX3DATA[6]) = (0, 0);
( PIPECLK *> PIPETX3DATA[7]) = (0, 0);
( PIPECLK *> PIPETX3DATA[8]) = (0, 0);
( PIPECLK *> PIPETX3DATA[9]) = (0, 0);
( PIPECLK *> PIPETX3ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX3EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX3EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX3STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX3SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX3SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX4DATAVALID) = (0, 0);
( PIPECLK *> PIPETX4DATA[0]) = (0, 0);
( PIPECLK *> PIPETX4DATA[10]) = (0, 0);
( PIPECLK *> PIPETX4DATA[11]) = (0, 0);
( PIPECLK *> PIPETX4DATA[12]) = (0, 0);
( PIPECLK *> PIPETX4DATA[13]) = (0, 0);
( PIPECLK *> PIPETX4DATA[14]) = (0, 0);
( PIPECLK *> PIPETX4DATA[15]) = (0, 0);
( PIPECLK *> PIPETX4DATA[16]) = (0, 0);
( PIPECLK *> PIPETX4DATA[17]) = (0, 0);
( PIPECLK *> PIPETX4DATA[18]) = (0, 0);
( PIPECLK *> PIPETX4DATA[19]) = (0, 0);
( PIPECLK *> PIPETX4DATA[1]) = (0, 0);
( PIPECLK *> PIPETX4DATA[20]) = (0, 0);
( PIPECLK *> PIPETX4DATA[21]) = (0, 0);
( PIPECLK *> PIPETX4DATA[22]) = (0, 0);
( PIPECLK *> PIPETX4DATA[23]) = (0, 0);
( PIPECLK *> PIPETX4DATA[24]) = (0, 0);
( PIPECLK *> PIPETX4DATA[25]) = (0, 0);
( PIPECLK *> PIPETX4DATA[26]) = (0, 0);
( PIPECLK *> PIPETX4DATA[27]) = (0, 0);
( PIPECLK *> PIPETX4DATA[28]) = (0, 0);
( PIPECLK *> PIPETX4DATA[29]) = (0, 0);
( PIPECLK *> PIPETX4DATA[2]) = (0, 0);
( PIPECLK *> PIPETX4DATA[30]) = (0, 0);
( PIPECLK *> PIPETX4DATA[31]) = (0, 0);
( PIPECLK *> PIPETX4DATA[3]) = (0, 0);
( PIPECLK *> PIPETX4DATA[4]) = (0, 0);
( PIPECLK *> PIPETX4DATA[5]) = (0, 0);
( PIPECLK *> PIPETX4DATA[6]) = (0, 0);
( PIPECLK *> PIPETX4DATA[7]) = (0, 0);
( PIPECLK *> PIPETX4DATA[8]) = (0, 0);
( PIPECLK *> PIPETX4DATA[9]) = (0, 0);
( PIPECLK *> PIPETX4ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX4EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX4EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX4STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX4SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX4SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX5DATAVALID) = (0, 0);
( PIPECLK *> PIPETX5DATA[0]) = (0, 0);
( PIPECLK *> PIPETX5DATA[10]) = (0, 0);
( PIPECLK *> PIPETX5DATA[11]) = (0, 0);
( PIPECLK *> PIPETX5DATA[12]) = (0, 0);
( PIPECLK *> PIPETX5DATA[13]) = (0, 0);
( PIPECLK *> PIPETX5DATA[14]) = (0, 0);
( PIPECLK *> PIPETX5DATA[15]) = (0, 0);
( PIPECLK *> PIPETX5DATA[16]) = (0, 0);
( PIPECLK *> PIPETX5DATA[17]) = (0, 0);
( PIPECLK *> PIPETX5DATA[18]) = (0, 0);
( PIPECLK *> PIPETX5DATA[19]) = (0, 0);
( PIPECLK *> PIPETX5DATA[1]) = (0, 0);
( PIPECLK *> PIPETX5DATA[20]) = (0, 0);
( PIPECLK *> PIPETX5DATA[21]) = (0, 0);
( PIPECLK *> PIPETX5DATA[22]) = (0, 0);
( PIPECLK *> PIPETX5DATA[23]) = (0, 0);
( PIPECLK *> PIPETX5DATA[24]) = (0, 0);
( PIPECLK *> PIPETX5DATA[25]) = (0, 0);
( PIPECLK *> PIPETX5DATA[26]) = (0, 0);
( PIPECLK *> PIPETX5DATA[27]) = (0, 0);
( PIPECLK *> PIPETX5DATA[28]) = (0, 0);
( PIPECLK *> PIPETX5DATA[29]) = (0, 0);
( PIPECLK *> PIPETX5DATA[2]) = (0, 0);
( PIPECLK *> PIPETX5DATA[30]) = (0, 0);
( PIPECLK *> PIPETX5DATA[31]) = (0, 0);
( PIPECLK *> PIPETX5DATA[3]) = (0, 0);
( PIPECLK *> PIPETX5DATA[4]) = (0, 0);
( PIPECLK *> PIPETX5DATA[5]) = (0, 0);
( PIPECLK *> PIPETX5DATA[6]) = (0, 0);
( PIPECLK *> PIPETX5DATA[7]) = (0, 0);
( PIPECLK *> PIPETX5DATA[8]) = (0, 0);
( PIPECLK *> PIPETX5DATA[9]) = (0, 0);
( PIPECLK *> PIPETX5ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX5EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX5EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX5STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX5SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX5SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX6DATAVALID) = (0, 0);
( PIPECLK *> PIPETX6DATA[0]) = (0, 0);
( PIPECLK *> PIPETX6DATA[10]) = (0, 0);
( PIPECLK *> PIPETX6DATA[11]) = (0, 0);
( PIPECLK *> PIPETX6DATA[12]) = (0, 0);
( PIPECLK *> PIPETX6DATA[13]) = (0, 0);
( PIPECLK *> PIPETX6DATA[14]) = (0, 0);
( PIPECLK *> PIPETX6DATA[15]) = (0, 0);
( PIPECLK *> PIPETX6DATA[16]) = (0, 0);
( PIPECLK *> PIPETX6DATA[17]) = (0, 0);
( PIPECLK *> PIPETX6DATA[18]) = (0, 0);
( PIPECLK *> PIPETX6DATA[19]) = (0, 0);
( PIPECLK *> PIPETX6DATA[1]) = (0, 0);
( PIPECLK *> PIPETX6DATA[20]) = (0, 0);
( PIPECLK *> PIPETX6DATA[21]) = (0, 0);
( PIPECLK *> PIPETX6DATA[22]) = (0, 0);
( PIPECLK *> PIPETX6DATA[23]) = (0, 0);
( PIPECLK *> PIPETX6DATA[24]) = (0, 0);
( PIPECLK *> PIPETX6DATA[25]) = (0, 0);
( PIPECLK *> PIPETX6DATA[26]) = (0, 0);
( PIPECLK *> PIPETX6DATA[27]) = (0, 0);
( PIPECLK *> PIPETX6DATA[28]) = (0, 0);
( PIPECLK *> PIPETX6DATA[29]) = (0, 0);
( PIPECLK *> PIPETX6DATA[2]) = (0, 0);
( PIPECLK *> PIPETX6DATA[30]) = (0, 0);
( PIPECLK *> PIPETX6DATA[31]) = (0, 0);
( PIPECLK *> PIPETX6DATA[3]) = (0, 0);
( PIPECLK *> PIPETX6DATA[4]) = (0, 0);
( PIPECLK *> PIPETX6DATA[5]) = (0, 0);
( PIPECLK *> PIPETX6DATA[6]) = (0, 0);
( PIPECLK *> PIPETX6DATA[7]) = (0, 0);
( PIPECLK *> PIPETX6DATA[8]) = (0, 0);
( PIPECLK *> PIPETX6DATA[9]) = (0, 0);
( PIPECLK *> PIPETX6ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX6EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX6EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX6STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX6SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX6SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX7DATAVALID) = (0, 0);
( PIPECLK *> PIPETX7DATA[0]) = (0, 0);
( PIPECLK *> PIPETX7DATA[10]) = (0, 0);
( PIPECLK *> PIPETX7DATA[11]) = (0, 0);
( PIPECLK *> PIPETX7DATA[12]) = (0, 0);
( PIPECLK *> PIPETX7DATA[13]) = (0, 0);
( PIPECLK *> PIPETX7DATA[14]) = (0, 0);
( PIPECLK *> PIPETX7DATA[15]) = (0, 0);
( PIPECLK *> PIPETX7DATA[16]) = (0, 0);
( PIPECLK *> PIPETX7DATA[17]) = (0, 0);
( PIPECLK *> PIPETX7DATA[18]) = (0, 0);
( PIPECLK *> PIPETX7DATA[19]) = (0, 0);
( PIPECLK *> PIPETX7DATA[1]) = (0, 0);
( PIPECLK *> PIPETX7DATA[20]) = (0, 0);
( PIPECLK *> PIPETX7DATA[21]) = (0, 0);
( PIPECLK *> PIPETX7DATA[22]) = (0, 0);
( PIPECLK *> PIPETX7DATA[23]) = (0, 0);
( PIPECLK *> PIPETX7DATA[24]) = (0, 0);
( PIPECLK *> PIPETX7DATA[25]) = (0, 0);
( PIPECLK *> PIPETX7DATA[26]) = (0, 0);
( PIPECLK *> PIPETX7DATA[27]) = (0, 0);
( PIPECLK *> PIPETX7DATA[28]) = (0, 0);
( PIPECLK *> PIPETX7DATA[29]) = (0, 0);
( PIPECLK *> PIPETX7DATA[2]) = (0, 0);
( PIPECLK *> PIPETX7DATA[30]) = (0, 0);
( PIPECLK *> PIPETX7DATA[31]) = (0, 0);
( PIPECLK *> PIPETX7DATA[3]) = (0, 0);
( PIPECLK *> PIPETX7DATA[4]) = (0, 0);
( PIPECLK *> PIPETX7DATA[5]) = (0, 0);
( PIPECLK *> PIPETX7DATA[6]) = (0, 0);
( PIPECLK *> PIPETX7DATA[7]) = (0, 0);
( PIPECLK *> PIPETX7DATA[8]) = (0, 0);
( PIPECLK *> PIPETX7DATA[9]) = (0, 0);
( PIPECLK *> PIPETX7ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX7EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX7EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX7STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX7SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX7SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETXDEEMPH) = (0, 0);
( PIPECLK *> PIPETXMARGIN[0]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[1]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[2]) = (0, 0);
( PIPECLK *> PIPETXRATE[0]) = (0, 0);
( PIPECLK *> PIPETXRATE[1]) = (0, 0);
( PIPECLK *> PIPETXRCVRDET) = (0, 0);
( PIPECLK *> PIPETXRESET) = (0, 0);
( PIPECLK *> PIPETXSWING) = (0, 0);
( PIPECLK *> PLEQINPROGRESS) = (0, 0);
( PIPECLK *> PLEQPHASE[0]) = (0, 0);
( PIPECLK *> PLEQPHASE[1]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[0]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[1]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[2]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[3]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[4]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[5]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[6]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[7]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[0]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[1]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[2]) = (0, 0);
( USERCLK *> CFGDPASUBSTATECHANGE[0]) = (0, 0);
( USERCLK *> CFGDPASUBSTATECHANGE[1]) = (0, 0);
( USERCLK *> CFGERRCOROUT) = (0, 0);
( USERCLK *> CFGERRFATALOUT) = (0, 0);
( USERCLK *> CFGERRNONFATALOUT) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[0]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[1]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[2]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[3]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[4]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[5]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[6]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[7]) = (0, 0);
( USERCLK *> CFGEXTREADRECEIVED) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[0]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[1]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[2]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[3]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[4]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[5]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[6]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[7]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[8]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[9]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[0]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[1]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[2]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[3]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[0]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[10]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[11]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[12]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[13]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[14]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[15]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[16]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[17]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[18]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[19]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[1]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[20]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[21]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[22]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[23]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[24]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[25]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[26]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[27]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[28]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[29]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[2]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[30]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[31]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[3]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[4]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[5]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[6]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[7]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[8]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[9]) = (0, 0);
( USERCLK *> CFGEXTWRITERECEIVED) = (0, 0);
( USERCLK *> CFGFCCPLD[0]) = (0, 0);
( USERCLK *> CFGFCCPLD[10]) = (0, 0);
( USERCLK *> CFGFCCPLD[11]) = (0, 0);
( USERCLK *> CFGFCCPLD[1]) = (0, 0);
( USERCLK *> CFGFCCPLD[2]) = (0, 0);
( USERCLK *> CFGFCCPLD[3]) = (0, 0);
( USERCLK *> CFGFCCPLD[4]) = (0, 0);
( USERCLK *> CFGFCCPLD[5]) = (0, 0);
( USERCLK *> CFGFCCPLD[6]) = (0, 0);
( USERCLK *> CFGFCCPLD[7]) = (0, 0);
( USERCLK *> CFGFCCPLD[8]) = (0, 0);
( USERCLK *> CFGFCCPLD[9]) = (0, 0);
( USERCLK *> CFGFCCPLH[0]) = (0, 0);
( USERCLK *> CFGFCCPLH[1]) = (0, 0);
( USERCLK *> CFGFCCPLH[2]) = (0, 0);
( USERCLK *> CFGFCCPLH[3]) = (0, 0);
( USERCLK *> CFGFCCPLH[4]) = (0, 0);
( USERCLK *> CFGFCCPLH[5]) = (0, 0);
( USERCLK *> CFGFCCPLH[6]) = (0, 0);
( USERCLK *> CFGFCCPLH[7]) = (0, 0);
( USERCLK *> CFGFCNPD[0]) = (0, 0);
( USERCLK *> CFGFCNPD[10]) = (0, 0);
( USERCLK *> CFGFCNPD[11]) = (0, 0);
( USERCLK *> CFGFCNPD[1]) = (0, 0);
( USERCLK *> CFGFCNPD[2]) = (0, 0);
( USERCLK *> CFGFCNPD[3]) = (0, 0);
( USERCLK *> CFGFCNPD[4]) = (0, 0);
( USERCLK *> CFGFCNPD[5]) = (0, 0);
( USERCLK *> CFGFCNPD[6]) = (0, 0);
( USERCLK *> CFGFCNPD[7]) = (0, 0);
( USERCLK *> CFGFCNPD[8]) = (0, 0);
( USERCLK *> CFGFCNPD[9]) = (0, 0);
( USERCLK *> CFGFCNPH[0]) = (0, 0);
( USERCLK *> CFGFCNPH[1]) = (0, 0);
( USERCLK *> CFGFCNPH[2]) = (0, 0);
( USERCLK *> CFGFCNPH[3]) = (0, 0);
( USERCLK *> CFGFCNPH[4]) = (0, 0);
( USERCLK *> CFGFCNPH[5]) = (0, 0);
( USERCLK *> CFGFCNPH[6]) = (0, 0);
( USERCLK *> CFGFCNPH[7]) = (0, 0);
( USERCLK *> CFGFCPD[0]) = (0, 0);
( USERCLK *> CFGFCPD[10]) = (0, 0);
( USERCLK *> CFGFCPD[11]) = (0, 0);
( USERCLK *> CFGFCPD[1]) = (0, 0);
( USERCLK *> CFGFCPD[2]) = (0, 0);
( USERCLK *> CFGFCPD[3]) = (0, 0);
( USERCLK *> CFGFCPD[4]) = (0, 0);
( USERCLK *> CFGFCPD[5]) = (0, 0);
( USERCLK *> CFGFCPD[6]) = (0, 0);
( USERCLK *> CFGFCPD[7]) = (0, 0);
( USERCLK *> CFGFCPD[8]) = (0, 0);
( USERCLK *> CFGFCPD[9]) = (0, 0);
( USERCLK *> CFGFCPH[0]) = (0, 0);
( USERCLK *> CFGFCPH[1]) = (0, 0);
( USERCLK *> CFGFCPH[2]) = (0, 0);
( USERCLK *> CFGFCPH[3]) = (0, 0);
( USERCLK *> CFGFCPH[4]) = (0, 0);
( USERCLK *> CFGFCPH[5]) = (0, 0);
( USERCLK *> CFGFCPH[6]) = (0, 0);
( USERCLK *> CFGFCPH[7]) = (0, 0);
( USERCLK *> CFGFLRINPROCESS[0]) = (0, 0);
( USERCLK *> CFGFLRINPROCESS[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[2]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[3]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[4]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[5]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[0]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[2]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[3]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[4]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[5]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[6]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[7]) = (0, 0);
( USERCLK *> CFGHOTRESETOUT) = (0, 0);
( USERCLK *> CFGINPUTUPDATEDONE) = (0, 0);
( USERCLK *> CFGINTERRUPTAOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTBOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTCOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTDOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[10]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[11]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[12]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[13]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[14]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[15]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[16]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[17]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[18]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[19]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[20]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[21]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[22]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[23]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[24]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[25]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[26]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[27]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[28]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[29]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[30]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[31]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[6]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[7]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[8]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[9]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIFAIL) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMASKUPDATE) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSISENT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXFAIL) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXMASK[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXMASK[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXSENT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTSENT) = (0, 0);
( USERCLK *> CFGLINKPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGLINKPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGLOCALERROR) = (0, 0);
( USERCLK *> CFGLTRENABLE) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[0]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[1]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[2]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[3]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[4]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[5]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[0]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[1]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[2]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[0]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[1]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[2]) = (0, 0);
( USERCLK *> CFGMCUPDATEDONE) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[0]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[10]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[11]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[12]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[13]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[14]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[15]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[16]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[17]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[18]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[19]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[1]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[20]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[21]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[22]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[23]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[24]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[25]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[26]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[27]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[28]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[29]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[2]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[30]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[31]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[3]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[4]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[5]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[6]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[7]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[8]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[9]) = (0, 0);
( USERCLK *> CFGMGMTREADWRITEDONE) = (0, 0);
( USERCLK *> CFGMSGRECEIVED) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[0]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[1]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[2]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[3]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[4]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[5]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[6]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[7]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[0]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[1]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[2]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[3]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[4]) = (0, 0);
( USERCLK *> CFGMSGTRANSMITDONE) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[0]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[1]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[2]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[3]) = (0, 0);
( USERCLK *> CFGOBFFENABLE[0]) = (0, 0);
( USERCLK *> CFGOBFFENABLE[1]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[0]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[10]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[11]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[12]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[13]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[14]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[15]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[1]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[2]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[3]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[4]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[5]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[6]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[7]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[8]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[9]) = (0, 0);
( USERCLK *> CFGPERFUNCTIONUPDATEDONE) = (0, 0);
( USERCLK *> CFGPHYLINKDOWN) = (0, 0);
( USERCLK *> CFGPHYLINKSTATUS[0]) = (0, 0);
( USERCLK *> CFGPHYLINKSTATUS[1]) = (0, 0);
( USERCLK *> CFGPLSTATUSCHANGE) = (0, 0);
( USERCLK *> CFGPOWERSTATECHANGEINTERRUPT) = (0, 0);
( USERCLK *> CFGRCBSTATUS[0]) = (0, 0);
( USERCLK *> CFGRCBSTATUS[1]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[0]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[1]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[2]) = (0, 0);
( USERCLK *> CFGTPHREQUESTERENABLE[0]) = (0, 0);
( USERCLK *> CFGTPHREQUESTERENABLE[1]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[0]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[1]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[2]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[3]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[4]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[5]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[0]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[1]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[2]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[3]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[4]) = (0, 0);
( USERCLK *> CFGTPHSTTREADENABLE) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[0]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[1]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[2]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[3]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[0]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[10]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[11]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[12]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[13]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[14]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[15]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[16]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[17]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[18]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[19]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[1]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[20]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[21]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[22]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[23]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[24]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[25]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[26]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[27]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[28]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[29]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[2]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[30]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[31]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[3]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[4]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[5]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[6]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[7]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[8]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[9]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEENABLE) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[0]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[1]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[2]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[3]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[4]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[5]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[10]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[11]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[12]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[13]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[14]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[15]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[16]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[17]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[2]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[3]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[4]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[5]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[6]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[7]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[8]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[9]) = (0, 0);
( USERCLK *> CFGVFSTATUS[0]) = (0, 0);
( USERCLK *> CFGVFSTATUS[10]) = (0, 0);
( USERCLK *> CFGVFSTATUS[11]) = (0, 0);
( USERCLK *> CFGVFSTATUS[1]) = (0, 0);
( USERCLK *> CFGVFSTATUS[2]) = (0, 0);
( USERCLK *> CFGVFSTATUS[3]) = (0, 0);
( USERCLK *> CFGVFSTATUS[4]) = (0, 0);
( USERCLK *> CFGVFSTATUS[5]) = (0, 0);
( USERCLK *> CFGVFSTATUS[6]) = (0, 0);
( USERCLK *> CFGVFSTATUS[7]) = (0, 0);
( USERCLK *> CFGVFSTATUS[8]) = (0, 0);
( USERCLK *> CFGVFSTATUS[9]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[0]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[1]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[2]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[3]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[4]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[5]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[0]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[10]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[11]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[12]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[13]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[14]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[15]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[16]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[17]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[1]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[2]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[3]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[4]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[5]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[6]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[7]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[8]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[9]) = (0, 0);
( USERCLK *> MAXISCQTDATA[0]) = (0, 0);
( USERCLK *> MAXISCQTDATA[100]) = (0, 0);
( USERCLK *> MAXISCQTDATA[101]) = (0, 0);
( USERCLK *> MAXISCQTDATA[102]) = (0, 0);
( USERCLK *> MAXISCQTDATA[103]) = (0, 0);
( USERCLK *> MAXISCQTDATA[104]) = (0, 0);
( USERCLK *> MAXISCQTDATA[105]) = (0, 0);
( USERCLK *> MAXISCQTDATA[106]) = (0, 0);
( USERCLK *> MAXISCQTDATA[107]) = (0, 0);
( USERCLK *> MAXISCQTDATA[108]) = (0, 0);
( USERCLK *> MAXISCQTDATA[109]) = (0, 0);
( USERCLK *> MAXISCQTDATA[10]) = (0, 0);
( USERCLK *> MAXISCQTDATA[110]) = (0, 0);
( USERCLK *> MAXISCQTDATA[111]) = (0, 0);
( USERCLK *> MAXISCQTDATA[112]) = (0, 0);
( USERCLK *> MAXISCQTDATA[113]) = (0, 0);
( USERCLK *> MAXISCQTDATA[114]) = (0, 0);
( USERCLK *> MAXISCQTDATA[115]) = (0, 0);
( USERCLK *> MAXISCQTDATA[116]) = (0, 0);
( USERCLK *> MAXISCQTDATA[117]) = (0, 0);
( USERCLK *> MAXISCQTDATA[118]) = (0, 0);
( USERCLK *> MAXISCQTDATA[119]) = (0, 0);
( USERCLK *> MAXISCQTDATA[11]) = (0, 0);
( USERCLK *> MAXISCQTDATA[120]) = (0, 0);
( USERCLK *> MAXISCQTDATA[121]) = (0, 0);
( USERCLK *> MAXISCQTDATA[122]) = (0, 0);
( USERCLK *> MAXISCQTDATA[123]) = (0, 0);
( USERCLK *> MAXISCQTDATA[124]) = (0, 0);
( USERCLK *> MAXISCQTDATA[125]) = (0, 0);
( USERCLK *> MAXISCQTDATA[126]) = (0, 0);
( USERCLK *> MAXISCQTDATA[127]) = (0, 0);
( USERCLK *> MAXISCQTDATA[128]) = (0, 0);
( USERCLK *> MAXISCQTDATA[129]) = (0, 0);
( USERCLK *> MAXISCQTDATA[12]) = (0, 0);
( USERCLK *> MAXISCQTDATA[130]) = (0, 0);
( USERCLK *> MAXISCQTDATA[131]) = (0, 0);
( USERCLK *> MAXISCQTDATA[132]) = (0, 0);
( USERCLK *> MAXISCQTDATA[133]) = (0, 0);
( USERCLK *> MAXISCQTDATA[134]) = (0, 0);
( USERCLK *> MAXISCQTDATA[135]) = (0, 0);
( USERCLK *> MAXISCQTDATA[136]) = (0, 0);
( USERCLK *> MAXISCQTDATA[137]) = (0, 0);
( USERCLK *> MAXISCQTDATA[138]) = (0, 0);
( USERCLK *> MAXISCQTDATA[139]) = (0, 0);
( USERCLK *> MAXISCQTDATA[13]) = (0, 0);
( USERCLK *> MAXISCQTDATA[140]) = (0, 0);
( USERCLK *> MAXISCQTDATA[141]) = (0, 0);
( USERCLK *> MAXISCQTDATA[142]) = (0, 0);
( USERCLK *> MAXISCQTDATA[143]) = (0, 0);
( USERCLK *> MAXISCQTDATA[144]) = (0, 0);
( USERCLK *> MAXISCQTDATA[145]) = (0, 0);
( USERCLK *> MAXISCQTDATA[146]) = (0, 0);
( USERCLK *> MAXISCQTDATA[147]) = (0, 0);
( USERCLK *> MAXISCQTDATA[148]) = (0, 0);
( USERCLK *> MAXISCQTDATA[149]) = (0, 0);
( USERCLK *> MAXISCQTDATA[14]) = (0, 0);
( USERCLK *> MAXISCQTDATA[150]) = (0, 0);
( USERCLK *> MAXISCQTDATA[151]) = (0, 0);
( USERCLK *> MAXISCQTDATA[152]) = (0, 0);
( USERCLK *> MAXISCQTDATA[153]) = (0, 0);
( USERCLK *> MAXISCQTDATA[154]) = (0, 0);
( USERCLK *> MAXISCQTDATA[155]) = (0, 0);
( USERCLK *> MAXISCQTDATA[156]) = (0, 0);
( USERCLK *> MAXISCQTDATA[157]) = (0, 0);
( USERCLK *> MAXISCQTDATA[158]) = (0, 0);
( USERCLK *> MAXISCQTDATA[159]) = (0, 0);
( USERCLK *> MAXISCQTDATA[15]) = (0, 0);
( USERCLK *> MAXISCQTDATA[160]) = (0, 0);
( USERCLK *> MAXISCQTDATA[161]) = (0, 0);
( USERCLK *> MAXISCQTDATA[162]) = (0, 0);
( USERCLK *> MAXISCQTDATA[163]) = (0, 0);
( USERCLK *> MAXISCQTDATA[164]) = (0, 0);
( USERCLK *> MAXISCQTDATA[165]) = (0, 0);
( USERCLK *> MAXISCQTDATA[166]) = (0, 0);
( USERCLK *> MAXISCQTDATA[167]) = (0, 0);
( USERCLK *> MAXISCQTDATA[168]) = (0, 0);
( USERCLK *> MAXISCQTDATA[169]) = (0, 0);
( USERCLK *> MAXISCQTDATA[16]) = (0, 0);
( USERCLK *> MAXISCQTDATA[170]) = (0, 0);
( USERCLK *> MAXISCQTDATA[171]) = (0, 0);
( USERCLK *> MAXISCQTDATA[172]) = (0, 0);
( USERCLK *> MAXISCQTDATA[173]) = (0, 0);
( USERCLK *> MAXISCQTDATA[174]) = (0, 0);
( USERCLK *> MAXISCQTDATA[175]) = (0, 0);
( USERCLK *> MAXISCQTDATA[176]) = (0, 0);
( USERCLK *> MAXISCQTDATA[177]) = (0, 0);
( USERCLK *> MAXISCQTDATA[178]) = (0, 0);
( USERCLK *> MAXISCQTDATA[179]) = (0, 0);
( USERCLK *> MAXISCQTDATA[17]) = (0, 0);
( USERCLK *> MAXISCQTDATA[180]) = (0, 0);
( USERCLK *> MAXISCQTDATA[181]) = (0, 0);
( USERCLK *> MAXISCQTDATA[182]) = (0, 0);
( USERCLK *> MAXISCQTDATA[183]) = (0, 0);
( USERCLK *> MAXISCQTDATA[184]) = (0, 0);
( USERCLK *> MAXISCQTDATA[185]) = (0, 0);
( USERCLK *> MAXISCQTDATA[186]) = (0, 0);
( USERCLK *> MAXISCQTDATA[187]) = (0, 0);
( USERCLK *> MAXISCQTDATA[188]) = (0, 0);
( USERCLK *> MAXISCQTDATA[189]) = (0, 0);
( USERCLK *> MAXISCQTDATA[18]) = (0, 0);
( USERCLK *> MAXISCQTDATA[190]) = (0, 0);
( USERCLK *> MAXISCQTDATA[191]) = (0, 0);
( USERCLK *> MAXISCQTDATA[192]) = (0, 0);
( USERCLK *> MAXISCQTDATA[193]) = (0, 0);
( USERCLK *> MAXISCQTDATA[194]) = (0, 0);
( USERCLK *> MAXISCQTDATA[195]) = (0, 0);
( USERCLK *> MAXISCQTDATA[196]) = (0, 0);
( USERCLK *> MAXISCQTDATA[197]) = (0, 0);
( USERCLK *> MAXISCQTDATA[198]) = (0, 0);
( USERCLK *> MAXISCQTDATA[199]) = (0, 0);
( USERCLK *> MAXISCQTDATA[19]) = (0, 0);
( USERCLK *> MAXISCQTDATA[1]) = (0, 0);
( USERCLK *> MAXISCQTDATA[200]) = (0, 0);
( USERCLK *> MAXISCQTDATA[201]) = (0, 0);
( USERCLK *> MAXISCQTDATA[202]) = (0, 0);
( USERCLK *> MAXISCQTDATA[203]) = (0, 0);
( USERCLK *> MAXISCQTDATA[204]) = (0, 0);
( USERCLK *> MAXISCQTDATA[205]) = (0, 0);
( USERCLK *> MAXISCQTDATA[206]) = (0, 0);
( USERCLK *> MAXISCQTDATA[207]) = (0, 0);
( USERCLK *> MAXISCQTDATA[208]) = (0, 0);
( USERCLK *> MAXISCQTDATA[209]) = (0, 0);
( USERCLK *> MAXISCQTDATA[20]) = (0, 0);
( USERCLK *> MAXISCQTDATA[210]) = (0, 0);
( USERCLK *> MAXISCQTDATA[211]) = (0, 0);
( USERCLK *> MAXISCQTDATA[212]) = (0, 0);
( USERCLK *> MAXISCQTDATA[213]) = (0, 0);
( USERCLK *> MAXISCQTDATA[214]) = (0, 0);
( USERCLK *> MAXISCQTDATA[215]) = (0, 0);
( USERCLK *> MAXISCQTDATA[216]) = (0, 0);
( USERCLK *> MAXISCQTDATA[217]) = (0, 0);
( USERCLK *> MAXISCQTDATA[218]) = (0, 0);
( USERCLK *> MAXISCQTDATA[219]) = (0, 0);
( USERCLK *> MAXISCQTDATA[21]) = (0, 0);
( USERCLK *> MAXISCQTDATA[220]) = (0, 0);
( USERCLK *> MAXISCQTDATA[221]) = (0, 0);
( USERCLK *> MAXISCQTDATA[222]) = (0, 0);
( USERCLK *> MAXISCQTDATA[223]) = (0, 0);
( USERCLK *> MAXISCQTDATA[224]) = (0, 0);
( USERCLK *> MAXISCQTDATA[225]) = (0, 0);
( USERCLK *> MAXISCQTDATA[226]) = (0, 0);
( USERCLK *> MAXISCQTDATA[227]) = (0, 0);
( USERCLK *> MAXISCQTDATA[228]) = (0, 0);
( USERCLK *> MAXISCQTDATA[229]) = (0, 0);
( USERCLK *> MAXISCQTDATA[22]) = (0, 0);
( USERCLK *> MAXISCQTDATA[230]) = (0, 0);
( USERCLK *> MAXISCQTDATA[231]) = (0, 0);
( USERCLK *> MAXISCQTDATA[232]) = (0, 0);
( USERCLK *> MAXISCQTDATA[233]) = (0, 0);
( USERCLK *> MAXISCQTDATA[234]) = (0, 0);
( USERCLK *> MAXISCQTDATA[235]) = (0, 0);
( USERCLK *> MAXISCQTDATA[236]) = (0, 0);
( USERCLK *> MAXISCQTDATA[237]) = (0, 0);
( USERCLK *> MAXISCQTDATA[238]) = (0, 0);
( USERCLK *> MAXISCQTDATA[239]) = (0, 0);
( USERCLK *> MAXISCQTDATA[23]) = (0, 0);
( USERCLK *> MAXISCQTDATA[240]) = (0, 0);
( USERCLK *> MAXISCQTDATA[241]) = (0, 0);
( USERCLK *> MAXISCQTDATA[242]) = (0, 0);
( USERCLK *> MAXISCQTDATA[243]) = (0, 0);
( USERCLK *> MAXISCQTDATA[244]) = (0, 0);
( USERCLK *> MAXISCQTDATA[245]) = (0, 0);
( USERCLK *> MAXISCQTDATA[246]) = (0, 0);
( USERCLK *> MAXISCQTDATA[247]) = (0, 0);
( USERCLK *> MAXISCQTDATA[248]) = (0, 0);
( USERCLK *> MAXISCQTDATA[249]) = (0, 0);
( USERCLK *> MAXISCQTDATA[24]) = (0, 0);
( USERCLK *> MAXISCQTDATA[250]) = (0, 0);
( USERCLK *> MAXISCQTDATA[251]) = (0, 0);
( USERCLK *> MAXISCQTDATA[252]) = (0, 0);
( USERCLK *> MAXISCQTDATA[253]) = (0, 0);
( USERCLK *> MAXISCQTDATA[254]) = (0, 0);
( USERCLK *> MAXISCQTDATA[255]) = (0, 0);
( USERCLK *> MAXISCQTDATA[25]) = (0, 0);
( USERCLK *> MAXISCQTDATA[26]) = (0, 0);
( USERCLK *> MAXISCQTDATA[27]) = (0, 0);
( USERCLK *> MAXISCQTDATA[28]) = (0, 0);
( USERCLK *> MAXISCQTDATA[29]) = (0, 0);
( USERCLK *> MAXISCQTDATA[2]) = (0, 0);
( USERCLK *> MAXISCQTDATA[30]) = (0, 0);
( USERCLK *> MAXISCQTDATA[31]) = (0, 0);
( USERCLK *> MAXISCQTDATA[32]) = (0, 0);
( USERCLK *> MAXISCQTDATA[33]) = (0, 0);
( USERCLK *> MAXISCQTDATA[34]) = (0, 0);
( USERCLK *> MAXISCQTDATA[35]) = (0, 0);
( USERCLK *> MAXISCQTDATA[36]) = (0, 0);
( USERCLK *> MAXISCQTDATA[37]) = (0, 0);
( USERCLK *> MAXISCQTDATA[38]) = (0, 0);
( USERCLK *> MAXISCQTDATA[39]) = (0, 0);
( USERCLK *> MAXISCQTDATA[3]) = (0, 0);
( USERCLK *> MAXISCQTDATA[40]) = (0, 0);
( USERCLK *> MAXISCQTDATA[41]) = (0, 0);
( USERCLK *> MAXISCQTDATA[42]) = (0, 0);
( USERCLK *> MAXISCQTDATA[43]) = (0, 0);
( USERCLK *> MAXISCQTDATA[44]) = (0, 0);
( USERCLK *> MAXISCQTDATA[45]) = (0, 0);
( USERCLK *> MAXISCQTDATA[46]) = (0, 0);
( USERCLK *> MAXISCQTDATA[47]) = (0, 0);
( USERCLK *> MAXISCQTDATA[48]) = (0, 0);
( USERCLK *> MAXISCQTDATA[49]) = (0, 0);
( USERCLK *> MAXISCQTDATA[4]) = (0, 0);
( USERCLK *> MAXISCQTDATA[50]) = (0, 0);
( USERCLK *> MAXISCQTDATA[51]) = (0, 0);
( USERCLK *> MAXISCQTDATA[52]) = (0, 0);
( USERCLK *> MAXISCQTDATA[53]) = (0, 0);
( USERCLK *> MAXISCQTDATA[54]) = (0, 0);
( USERCLK *> MAXISCQTDATA[55]) = (0, 0);
( USERCLK *> MAXISCQTDATA[56]) = (0, 0);
( USERCLK *> MAXISCQTDATA[57]) = (0, 0);
( USERCLK *> MAXISCQTDATA[58]) = (0, 0);
( USERCLK *> MAXISCQTDATA[59]) = (0, 0);
( USERCLK *> MAXISCQTDATA[5]) = (0, 0);
( USERCLK *> MAXISCQTDATA[60]) = (0, 0);
( USERCLK *> MAXISCQTDATA[61]) = (0, 0);
( USERCLK *> MAXISCQTDATA[62]) = (0, 0);
( USERCLK *> MAXISCQTDATA[63]) = (0, 0);
( USERCLK *> MAXISCQTDATA[64]) = (0, 0);
( USERCLK *> MAXISCQTDATA[65]) = (0, 0);
( USERCLK *> MAXISCQTDATA[66]) = (0, 0);
( USERCLK *> MAXISCQTDATA[67]) = (0, 0);
( USERCLK *> MAXISCQTDATA[68]) = (0, 0);
( USERCLK *> MAXISCQTDATA[69]) = (0, 0);
( USERCLK *> MAXISCQTDATA[6]) = (0, 0);
( USERCLK *> MAXISCQTDATA[70]) = (0, 0);
( USERCLK *> MAXISCQTDATA[71]) = (0, 0);
( USERCLK *> MAXISCQTDATA[72]) = (0, 0);
( USERCLK *> MAXISCQTDATA[73]) = (0, 0);
( USERCLK *> MAXISCQTDATA[74]) = (0, 0);
( USERCLK *> MAXISCQTDATA[75]) = (0, 0);
( USERCLK *> MAXISCQTDATA[76]) = (0, 0);
( USERCLK *> MAXISCQTDATA[77]) = (0, 0);
( USERCLK *> MAXISCQTDATA[78]) = (0, 0);
( USERCLK *> MAXISCQTDATA[79]) = (0, 0);
( USERCLK *> MAXISCQTDATA[7]) = (0, 0);
( USERCLK *> MAXISCQTDATA[80]) = (0, 0);
( USERCLK *> MAXISCQTDATA[81]) = (0, 0);
( USERCLK *> MAXISCQTDATA[82]) = (0, 0);
( USERCLK *> MAXISCQTDATA[83]) = (0, 0);
( USERCLK *> MAXISCQTDATA[84]) = (0, 0);
( USERCLK *> MAXISCQTDATA[85]) = (0, 0);
( USERCLK *> MAXISCQTDATA[86]) = (0, 0);
( USERCLK *> MAXISCQTDATA[87]) = (0, 0);
( USERCLK *> MAXISCQTDATA[88]) = (0, 0);
( USERCLK *> MAXISCQTDATA[89]) = (0, 0);
( USERCLK *> MAXISCQTDATA[8]) = (0, 0);
( USERCLK *> MAXISCQTDATA[90]) = (0, 0);
( USERCLK *> MAXISCQTDATA[91]) = (0, 0);
( USERCLK *> MAXISCQTDATA[92]) = (0, 0);
( USERCLK *> MAXISCQTDATA[93]) = (0, 0);
( USERCLK *> MAXISCQTDATA[94]) = (0, 0);
( USERCLK *> MAXISCQTDATA[95]) = (0, 0);
( USERCLK *> MAXISCQTDATA[96]) = (0, 0);
( USERCLK *> MAXISCQTDATA[97]) = (0, 0);
( USERCLK *> MAXISCQTDATA[98]) = (0, 0);
( USERCLK *> MAXISCQTDATA[99]) = (0, 0);
( USERCLK *> MAXISCQTDATA[9]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[0]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[1]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[2]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[3]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[4]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[5]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[6]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[7]) = (0, 0);
( USERCLK *> MAXISCQTLAST) = (0, 0);
( USERCLK *> MAXISCQTUSER[0]) = (0, 0);
( USERCLK *> MAXISCQTUSER[10]) = (0, 0);
( USERCLK *> MAXISCQTUSER[11]) = (0, 0);
( USERCLK *> MAXISCQTUSER[12]) = (0, 0);
( USERCLK *> MAXISCQTUSER[13]) = (0, 0);
( USERCLK *> MAXISCQTUSER[14]) = (0, 0);
( USERCLK *> MAXISCQTUSER[15]) = (0, 0);
( USERCLK *> MAXISCQTUSER[16]) = (0, 0);
( USERCLK *> MAXISCQTUSER[17]) = (0, 0);
( USERCLK *> MAXISCQTUSER[18]) = (0, 0);
( USERCLK *> MAXISCQTUSER[19]) = (0, 0);
( USERCLK *> MAXISCQTUSER[1]) = (0, 0);
( USERCLK *> MAXISCQTUSER[20]) = (0, 0);
( USERCLK *> MAXISCQTUSER[21]) = (0, 0);
( USERCLK *> MAXISCQTUSER[22]) = (0, 0);
( USERCLK *> MAXISCQTUSER[23]) = (0, 0);
( USERCLK *> MAXISCQTUSER[24]) = (0, 0);
( USERCLK *> MAXISCQTUSER[25]) = (0, 0);
( USERCLK *> MAXISCQTUSER[26]) = (0, 0);
( USERCLK *> MAXISCQTUSER[27]) = (0, 0);
( USERCLK *> MAXISCQTUSER[28]) = (0, 0);
( USERCLK *> MAXISCQTUSER[29]) = (0, 0);
( USERCLK *> MAXISCQTUSER[2]) = (0, 0);
( USERCLK *> MAXISCQTUSER[30]) = (0, 0);
( USERCLK *> MAXISCQTUSER[31]) = (0, 0);
( USERCLK *> MAXISCQTUSER[32]) = (0, 0);
( USERCLK *> MAXISCQTUSER[33]) = (0, 0);
( USERCLK *> MAXISCQTUSER[34]) = (0, 0);
( USERCLK *> MAXISCQTUSER[35]) = (0, 0);
( USERCLK *> MAXISCQTUSER[36]) = (0, 0);
( USERCLK *> MAXISCQTUSER[37]) = (0, 0);
( USERCLK *> MAXISCQTUSER[38]) = (0, 0);
( USERCLK *> MAXISCQTUSER[39]) = (0, 0);
( USERCLK *> MAXISCQTUSER[3]) = (0, 0);
( USERCLK *> MAXISCQTUSER[40]) = (0, 0);
( USERCLK *> MAXISCQTUSER[41]) = (0, 0);
( USERCLK *> MAXISCQTUSER[42]) = (0, 0);
( USERCLK *> MAXISCQTUSER[43]) = (0, 0);
( USERCLK *> MAXISCQTUSER[44]) = (0, 0);
( USERCLK *> MAXISCQTUSER[45]) = (0, 0);
( USERCLK *> MAXISCQTUSER[46]) = (0, 0);
( USERCLK *> MAXISCQTUSER[47]) = (0, 0);
( USERCLK *> MAXISCQTUSER[48]) = (0, 0);
( USERCLK *> MAXISCQTUSER[49]) = (0, 0);
( USERCLK *> MAXISCQTUSER[4]) = (0, 0);
( USERCLK *> MAXISCQTUSER[50]) = (0, 0);
( USERCLK *> MAXISCQTUSER[51]) = (0, 0);
( USERCLK *> MAXISCQTUSER[52]) = (0, 0);
( USERCLK *> MAXISCQTUSER[53]) = (0, 0);
( USERCLK *> MAXISCQTUSER[54]) = (0, 0);
( USERCLK *> MAXISCQTUSER[55]) = (0, 0);
( USERCLK *> MAXISCQTUSER[56]) = (0, 0);
( USERCLK *> MAXISCQTUSER[57]) = (0, 0);
( USERCLK *> MAXISCQTUSER[58]) = (0, 0);
( USERCLK *> MAXISCQTUSER[59]) = (0, 0);
( USERCLK *> MAXISCQTUSER[5]) = (0, 0);
( USERCLK *> MAXISCQTUSER[60]) = (0, 0);
( USERCLK *> MAXISCQTUSER[61]) = (0, 0);
( USERCLK *> MAXISCQTUSER[62]) = (0, 0);
( USERCLK *> MAXISCQTUSER[63]) = (0, 0);
( USERCLK *> MAXISCQTUSER[64]) = (0, 0);
( USERCLK *> MAXISCQTUSER[65]) = (0, 0);
( USERCLK *> MAXISCQTUSER[66]) = (0, 0);
( USERCLK *> MAXISCQTUSER[67]) = (0, 0);
( USERCLK *> MAXISCQTUSER[68]) = (0, 0);
( USERCLK *> MAXISCQTUSER[69]) = (0, 0);
( USERCLK *> MAXISCQTUSER[6]) = (0, 0);
( USERCLK *> MAXISCQTUSER[70]) = (0, 0);
( USERCLK *> MAXISCQTUSER[71]) = (0, 0);
( USERCLK *> MAXISCQTUSER[72]) = (0, 0);
( USERCLK *> MAXISCQTUSER[73]) = (0, 0);
( USERCLK *> MAXISCQTUSER[74]) = (0, 0);
( USERCLK *> MAXISCQTUSER[75]) = (0, 0);
( USERCLK *> MAXISCQTUSER[76]) = (0, 0);
( USERCLK *> MAXISCQTUSER[77]) = (0, 0);
( USERCLK *> MAXISCQTUSER[78]) = (0, 0);
( USERCLK *> MAXISCQTUSER[79]) = (0, 0);
( USERCLK *> MAXISCQTUSER[7]) = (0, 0);
( USERCLK *> MAXISCQTUSER[80]) = (0, 0);
( USERCLK *> MAXISCQTUSER[81]) = (0, 0);
( USERCLK *> MAXISCQTUSER[82]) = (0, 0);
( USERCLK *> MAXISCQTUSER[83]) = (0, 0);
( USERCLK *> MAXISCQTUSER[84]) = (0, 0);
( USERCLK *> MAXISCQTUSER[8]) = (0, 0);
( USERCLK *> MAXISCQTUSER[9]) = (0, 0);
( USERCLK *> MAXISCQTVALID) = (0, 0);
( USERCLK *> MAXISRCTDATA[0]) = (0, 0);
( USERCLK *> MAXISRCTDATA[100]) = (0, 0);
( USERCLK *> MAXISRCTDATA[101]) = (0, 0);
( USERCLK *> MAXISRCTDATA[102]) = (0, 0);
( USERCLK *> MAXISRCTDATA[103]) = (0, 0);
( USERCLK *> MAXISRCTDATA[104]) = (0, 0);
( USERCLK *> MAXISRCTDATA[105]) = (0, 0);
( USERCLK *> MAXISRCTDATA[106]) = (0, 0);
( USERCLK *> MAXISRCTDATA[107]) = (0, 0);
( USERCLK *> MAXISRCTDATA[108]) = (0, 0);
( USERCLK *> MAXISRCTDATA[109]) = (0, 0);
( USERCLK *> MAXISRCTDATA[10]) = (0, 0);
( USERCLK *> MAXISRCTDATA[110]) = (0, 0);
( USERCLK *> MAXISRCTDATA[111]) = (0, 0);
( USERCLK *> MAXISRCTDATA[112]) = (0, 0);
( USERCLK *> MAXISRCTDATA[113]) = (0, 0);
( USERCLK *> MAXISRCTDATA[114]) = (0, 0);
( USERCLK *> MAXISRCTDATA[115]) = (0, 0);
( USERCLK *> MAXISRCTDATA[116]) = (0, 0);
( USERCLK *> MAXISRCTDATA[117]) = (0, 0);
( USERCLK *> MAXISRCTDATA[118]) = (0, 0);
( USERCLK *> MAXISRCTDATA[119]) = (0, 0);
( USERCLK *> MAXISRCTDATA[11]) = (0, 0);
( USERCLK *> MAXISRCTDATA[120]) = (0, 0);
( USERCLK *> MAXISRCTDATA[121]) = (0, 0);
( USERCLK *> MAXISRCTDATA[122]) = (0, 0);
( USERCLK *> MAXISRCTDATA[123]) = (0, 0);
( USERCLK *> MAXISRCTDATA[124]) = (0, 0);
( USERCLK *> MAXISRCTDATA[125]) = (0, 0);
( USERCLK *> MAXISRCTDATA[126]) = (0, 0);
( USERCLK *> MAXISRCTDATA[127]) = (0, 0);
( USERCLK *> MAXISRCTDATA[128]) = (0, 0);
( USERCLK *> MAXISRCTDATA[129]) = (0, 0);
( USERCLK *> MAXISRCTDATA[12]) = (0, 0);
( USERCLK *> MAXISRCTDATA[130]) = (0, 0);
( USERCLK *> MAXISRCTDATA[131]) = (0, 0);
( USERCLK *> MAXISRCTDATA[132]) = (0, 0);
( USERCLK *> MAXISRCTDATA[133]) = (0, 0);
( USERCLK *> MAXISRCTDATA[134]) = (0, 0);
( USERCLK *> MAXISRCTDATA[135]) = (0, 0);
( USERCLK *> MAXISRCTDATA[136]) = (0, 0);
( USERCLK *> MAXISRCTDATA[137]) = (0, 0);
( USERCLK *> MAXISRCTDATA[138]) = (0, 0);
( USERCLK *> MAXISRCTDATA[139]) = (0, 0);
( USERCLK *> MAXISRCTDATA[13]) = (0, 0);
( USERCLK *> MAXISRCTDATA[140]) = (0, 0);
( USERCLK *> MAXISRCTDATA[141]) = (0, 0);
( USERCLK *> MAXISRCTDATA[142]) = (0, 0);
( USERCLK *> MAXISRCTDATA[143]) = (0, 0);
( USERCLK *> MAXISRCTDATA[144]) = (0, 0);
( USERCLK *> MAXISRCTDATA[145]) = (0, 0);
( USERCLK *> MAXISRCTDATA[146]) = (0, 0);
( USERCLK *> MAXISRCTDATA[147]) = (0, 0);
( USERCLK *> MAXISRCTDATA[148]) = (0, 0);
( USERCLK *> MAXISRCTDATA[149]) = (0, 0);
( USERCLK *> MAXISRCTDATA[14]) = (0, 0);
( USERCLK *> MAXISRCTDATA[150]) = (0, 0);
( USERCLK *> MAXISRCTDATA[151]) = (0, 0);
( USERCLK *> MAXISRCTDATA[152]) = (0, 0);
( USERCLK *> MAXISRCTDATA[153]) = (0, 0);
( USERCLK *> MAXISRCTDATA[154]) = (0, 0);
( USERCLK *> MAXISRCTDATA[155]) = (0, 0);
( USERCLK *> MAXISRCTDATA[156]) = (0, 0);
( USERCLK *> MAXISRCTDATA[157]) = (0, 0);
( USERCLK *> MAXISRCTDATA[158]) = (0, 0);
( USERCLK *> MAXISRCTDATA[159]) = (0, 0);
( USERCLK *> MAXISRCTDATA[15]) = (0, 0);
( USERCLK *> MAXISRCTDATA[160]) = (0, 0);
( USERCLK *> MAXISRCTDATA[161]) = (0, 0);
( USERCLK *> MAXISRCTDATA[162]) = (0, 0);
( USERCLK *> MAXISRCTDATA[163]) = (0, 0);
( USERCLK *> MAXISRCTDATA[164]) = (0, 0);
( USERCLK *> MAXISRCTDATA[165]) = (0, 0);
( USERCLK *> MAXISRCTDATA[166]) = (0, 0);
( USERCLK *> MAXISRCTDATA[167]) = (0, 0);
( USERCLK *> MAXISRCTDATA[168]) = (0, 0);
( USERCLK *> MAXISRCTDATA[169]) = (0, 0);
( USERCLK *> MAXISRCTDATA[16]) = (0, 0);
( USERCLK *> MAXISRCTDATA[170]) = (0, 0);
( USERCLK *> MAXISRCTDATA[171]) = (0, 0);
( USERCLK *> MAXISRCTDATA[172]) = (0, 0);
( USERCLK *> MAXISRCTDATA[173]) = (0, 0);
( USERCLK *> MAXISRCTDATA[174]) = (0, 0);
( USERCLK *> MAXISRCTDATA[175]) = (0, 0);
( USERCLK *> MAXISRCTDATA[176]) = (0, 0);
( USERCLK *> MAXISRCTDATA[177]) = (0, 0);
( USERCLK *> MAXISRCTDATA[178]) = (0, 0);
( USERCLK *> MAXISRCTDATA[179]) = (0, 0);
( USERCLK *> MAXISRCTDATA[17]) = (0, 0);
( USERCLK *> MAXISRCTDATA[180]) = (0, 0);
( USERCLK *> MAXISRCTDATA[181]) = (0, 0);
( USERCLK *> MAXISRCTDATA[182]) = (0, 0);
( USERCLK *> MAXISRCTDATA[183]) = (0, 0);
( USERCLK *> MAXISRCTDATA[184]) = (0, 0);
( USERCLK *> MAXISRCTDATA[185]) = (0, 0);
( USERCLK *> MAXISRCTDATA[186]) = (0, 0);
( USERCLK *> MAXISRCTDATA[187]) = (0, 0);
( USERCLK *> MAXISRCTDATA[188]) = (0, 0);
( USERCLK *> MAXISRCTDATA[189]) = (0, 0);
( USERCLK *> MAXISRCTDATA[18]) = (0, 0);
( USERCLK *> MAXISRCTDATA[190]) = (0, 0);
( USERCLK *> MAXISRCTDATA[191]) = (0, 0);
( USERCLK *> MAXISRCTDATA[192]) = (0, 0);
( USERCLK *> MAXISRCTDATA[193]) = (0, 0);
( USERCLK *> MAXISRCTDATA[194]) = (0, 0);
( USERCLK *> MAXISRCTDATA[195]) = (0, 0);
( USERCLK *> MAXISRCTDATA[196]) = (0, 0);
( USERCLK *> MAXISRCTDATA[197]) = (0, 0);
( USERCLK *> MAXISRCTDATA[198]) = (0, 0);
( USERCLK *> MAXISRCTDATA[199]) = (0, 0);
( USERCLK *> MAXISRCTDATA[19]) = (0, 0);
( USERCLK *> MAXISRCTDATA[1]) = (0, 0);
( USERCLK *> MAXISRCTDATA[200]) = (0, 0);
( USERCLK *> MAXISRCTDATA[201]) = (0, 0);
( USERCLK *> MAXISRCTDATA[202]) = (0, 0);
( USERCLK *> MAXISRCTDATA[203]) = (0, 0);
( USERCLK *> MAXISRCTDATA[204]) = (0, 0);
( USERCLK *> MAXISRCTDATA[205]) = (0, 0);
( USERCLK *> MAXISRCTDATA[206]) = (0, 0);
( USERCLK *> MAXISRCTDATA[207]) = (0, 0);
( USERCLK *> MAXISRCTDATA[208]) = (0, 0);
( USERCLK *> MAXISRCTDATA[209]) = (0, 0);
( USERCLK *> MAXISRCTDATA[20]) = (0, 0);
( USERCLK *> MAXISRCTDATA[210]) = (0, 0);
( USERCLK *> MAXISRCTDATA[211]) = (0, 0);
( USERCLK *> MAXISRCTDATA[212]) = (0, 0);
( USERCLK *> MAXISRCTDATA[213]) = (0, 0);
( USERCLK *> MAXISRCTDATA[214]) = (0, 0);
( USERCLK *> MAXISRCTDATA[215]) = (0, 0);
( USERCLK *> MAXISRCTDATA[216]) = (0, 0);
( USERCLK *> MAXISRCTDATA[217]) = (0, 0);
( USERCLK *> MAXISRCTDATA[218]) = (0, 0);
( USERCLK *> MAXISRCTDATA[219]) = (0, 0);
( USERCLK *> MAXISRCTDATA[21]) = (0, 0);
( USERCLK *> MAXISRCTDATA[220]) = (0, 0);
( USERCLK *> MAXISRCTDATA[221]) = (0, 0);
( USERCLK *> MAXISRCTDATA[222]) = (0, 0);
( USERCLK *> MAXISRCTDATA[223]) = (0, 0);
( USERCLK *> MAXISRCTDATA[224]) = (0, 0);
( USERCLK *> MAXISRCTDATA[225]) = (0, 0);
( USERCLK *> MAXISRCTDATA[226]) = (0, 0);
( USERCLK *> MAXISRCTDATA[227]) = (0, 0);
( USERCLK *> MAXISRCTDATA[228]) = (0, 0);
( USERCLK *> MAXISRCTDATA[229]) = (0, 0);
( USERCLK *> MAXISRCTDATA[22]) = (0, 0);
( USERCLK *> MAXISRCTDATA[230]) = (0, 0);
( USERCLK *> MAXISRCTDATA[231]) = (0, 0);
( USERCLK *> MAXISRCTDATA[232]) = (0, 0);
( USERCLK *> MAXISRCTDATA[233]) = (0, 0);
( USERCLK *> MAXISRCTDATA[234]) = (0, 0);
( USERCLK *> MAXISRCTDATA[235]) = (0, 0);
( USERCLK *> MAXISRCTDATA[236]) = (0, 0);
( USERCLK *> MAXISRCTDATA[237]) = (0, 0);
( USERCLK *> MAXISRCTDATA[238]) = (0, 0);
( USERCLK *> MAXISRCTDATA[239]) = (0, 0);
( USERCLK *> MAXISRCTDATA[23]) = (0, 0);
( USERCLK *> MAXISRCTDATA[240]) = (0, 0);
( USERCLK *> MAXISRCTDATA[241]) = (0, 0);
( USERCLK *> MAXISRCTDATA[242]) = (0, 0);
( USERCLK *> MAXISRCTDATA[243]) = (0, 0);
( USERCLK *> MAXISRCTDATA[244]) = (0, 0);
( USERCLK *> MAXISRCTDATA[245]) = (0, 0);
( USERCLK *> MAXISRCTDATA[246]) = (0, 0);
( USERCLK *> MAXISRCTDATA[247]) = (0, 0);
( USERCLK *> MAXISRCTDATA[248]) = (0, 0);
( USERCLK *> MAXISRCTDATA[249]) = (0, 0);
( USERCLK *> MAXISRCTDATA[24]) = (0, 0);
( USERCLK *> MAXISRCTDATA[250]) = (0, 0);
( USERCLK *> MAXISRCTDATA[251]) = (0, 0);
( USERCLK *> MAXISRCTDATA[252]) = (0, 0);
( USERCLK *> MAXISRCTDATA[253]) = (0, 0);
( USERCLK *> MAXISRCTDATA[254]) = (0, 0);
( USERCLK *> MAXISRCTDATA[255]) = (0, 0);
( USERCLK *> MAXISRCTDATA[25]) = (0, 0);
( USERCLK *> MAXISRCTDATA[26]) = (0, 0);
( USERCLK *> MAXISRCTDATA[27]) = (0, 0);
( USERCLK *> MAXISRCTDATA[28]) = (0, 0);
( USERCLK *> MAXISRCTDATA[29]) = (0, 0);
( USERCLK *> MAXISRCTDATA[2]) = (0, 0);
( USERCLK *> MAXISRCTDATA[30]) = (0, 0);
( USERCLK *> MAXISRCTDATA[31]) = (0, 0);
( USERCLK *> MAXISRCTDATA[32]) = (0, 0);
( USERCLK *> MAXISRCTDATA[33]) = (0, 0);
( USERCLK *> MAXISRCTDATA[34]) = (0, 0);
( USERCLK *> MAXISRCTDATA[35]) = (0, 0);
( USERCLK *> MAXISRCTDATA[36]) = (0, 0);
( USERCLK *> MAXISRCTDATA[37]) = (0, 0);
( USERCLK *> MAXISRCTDATA[38]) = (0, 0);
( USERCLK *> MAXISRCTDATA[39]) = (0, 0);
( USERCLK *> MAXISRCTDATA[3]) = (0, 0);
( USERCLK *> MAXISRCTDATA[40]) = (0, 0);
( USERCLK *> MAXISRCTDATA[41]) = (0, 0);
( USERCLK *> MAXISRCTDATA[42]) = (0, 0);
( USERCLK *> MAXISRCTDATA[43]) = (0, 0);
( USERCLK *> MAXISRCTDATA[44]) = (0, 0);
( USERCLK *> MAXISRCTDATA[45]) = (0, 0);
( USERCLK *> MAXISRCTDATA[46]) = (0, 0);
( USERCLK *> MAXISRCTDATA[47]) = (0, 0);
( USERCLK *> MAXISRCTDATA[48]) = (0, 0);
( USERCLK *> MAXISRCTDATA[49]) = (0, 0);
( USERCLK *> MAXISRCTDATA[4]) = (0, 0);
( USERCLK *> MAXISRCTDATA[50]) = (0, 0);
( USERCLK *> MAXISRCTDATA[51]) = (0, 0);
( USERCLK *> MAXISRCTDATA[52]) = (0, 0);
( USERCLK *> MAXISRCTDATA[53]) = (0, 0);
( USERCLK *> MAXISRCTDATA[54]) = (0, 0);
( USERCLK *> MAXISRCTDATA[55]) = (0, 0);
( USERCLK *> MAXISRCTDATA[56]) = (0, 0);
( USERCLK *> MAXISRCTDATA[57]) = (0, 0);
( USERCLK *> MAXISRCTDATA[58]) = (0, 0);
( USERCLK *> MAXISRCTDATA[59]) = (0, 0);
( USERCLK *> MAXISRCTDATA[5]) = (0, 0);
( USERCLK *> MAXISRCTDATA[60]) = (0, 0);
( USERCLK *> MAXISRCTDATA[61]) = (0, 0);
( USERCLK *> MAXISRCTDATA[62]) = (0, 0);
( USERCLK *> MAXISRCTDATA[63]) = (0, 0);
( USERCLK *> MAXISRCTDATA[64]) = (0, 0);
( USERCLK *> MAXISRCTDATA[65]) = (0, 0);
( USERCLK *> MAXISRCTDATA[66]) = (0, 0);
( USERCLK *> MAXISRCTDATA[67]) = (0, 0);
( USERCLK *> MAXISRCTDATA[68]) = (0, 0);
( USERCLK *> MAXISRCTDATA[69]) = (0, 0);
( USERCLK *> MAXISRCTDATA[6]) = (0, 0);
( USERCLK *> MAXISRCTDATA[70]) = (0, 0);
( USERCLK *> MAXISRCTDATA[71]) = (0, 0);
( USERCLK *> MAXISRCTDATA[72]) = (0, 0);
( USERCLK *> MAXISRCTDATA[73]) = (0, 0);
( USERCLK *> MAXISRCTDATA[74]) = (0, 0);
( USERCLK *> MAXISRCTDATA[75]) = (0, 0);
( USERCLK *> MAXISRCTDATA[76]) = (0, 0);
( USERCLK *> MAXISRCTDATA[77]) = (0, 0);
( USERCLK *> MAXISRCTDATA[78]) = (0, 0);
( USERCLK *> MAXISRCTDATA[79]) = (0, 0);
( USERCLK *> MAXISRCTDATA[7]) = (0, 0);
( USERCLK *> MAXISRCTDATA[80]) = (0, 0);
( USERCLK *> MAXISRCTDATA[81]) = (0, 0);
( USERCLK *> MAXISRCTDATA[82]) = (0, 0);
( USERCLK *> MAXISRCTDATA[83]) = (0, 0);
( USERCLK *> MAXISRCTDATA[84]) = (0, 0);
( USERCLK *> MAXISRCTDATA[85]) = (0, 0);
( USERCLK *> MAXISRCTDATA[86]) = (0, 0);
( USERCLK *> MAXISRCTDATA[87]) = (0, 0);
( USERCLK *> MAXISRCTDATA[88]) = (0, 0);
( USERCLK *> MAXISRCTDATA[89]) = (0, 0);
( USERCLK *> MAXISRCTDATA[8]) = (0, 0);
( USERCLK *> MAXISRCTDATA[90]) = (0, 0);
( USERCLK *> MAXISRCTDATA[91]) = (0, 0);
( USERCLK *> MAXISRCTDATA[92]) = (0, 0);
( USERCLK *> MAXISRCTDATA[93]) = (0, 0);
( USERCLK *> MAXISRCTDATA[94]) = (0, 0);
( USERCLK *> MAXISRCTDATA[95]) = (0, 0);
( USERCLK *> MAXISRCTDATA[96]) = (0, 0);
( USERCLK *> MAXISRCTDATA[97]) = (0, 0);
( USERCLK *> MAXISRCTDATA[98]) = (0, 0);
( USERCLK *> MAXISRCTDATA[99]) = (0, 0);
( USERCLK *> MAXISRCTDATA[9]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[0]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[1]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[2]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[3]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[4]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[5]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[6]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[7]) = (0, 0);
( USERCLK *> MAXISRCTLAST) = (0, 0);
( USERCLK *> MAXISRCTUSER[0]) = (0, 0);
( USERCLK *> MAXISRCTUSER[10]) = (0, 0);
( USERCLK *> MAXISRCTUSER[11]) = (0, 0);
( USERCLK *> MAXISRCTUSER[12]) = (0, 0);
( USERCLK *> MAXISRCTUSER[13]) = (0, 0);
( USERCLK *> MAXISRCTUSER[14]) = (0, 0);
( USERCLK *> MAXISRCTUSER[15]) = (0, 0);
( USERCLK *> MAXISRCTUSER[16]) = (0, 0);
( USERCLK *> MAXISRCTUSER[17]) = (0, 0);
( USERCLK *> MAXISRCTUSER[18]) = (0, 0);
( USERCLK *> MAXISRCTUSER[19]) = (0, 0);
( USERCLK *> MAXISRCTUSER[1]) = (0, 0);
( USERCLK *> MAXISRCTUSER[20]) = (0, 0);
( USERCLK *> MAXISRCTUSER[21]) = (0, 0);
( USERCLK *> MAXISRCTUSER[22]) = (0, 0);
( USERCLK *> MAXISRCTUSER[23]) = (0, 0);
( USERCLK *> MAXISRCTUSER[24]) = (0, 0);
( USERCLK *> MAXISRCTUSER[25]) = (0, 0);
( USERCLK *> MAXISRCTUSER[26]) = (0, 0);
( USERCLK *> MAXISRCTUSER[27]) = (0, 0);
( USERCLK *> MAXISRCTUSER[28]) = (0, 0);
( USERCLK *> MAXISRCTUSER[29]) = (0, 0);
( USERCLK *> MAXISRCTUSER[2]) = (0, 0);
( USERCLK *> MAXISRCTUSER[30]) = (0, 0);
( USERCLK *> MAXISRCTUSER[31]) = (0, 0);
( USERCLK *> MAXISRCTUSER[32]) = (0, 0);
( USERCLK *> MAXISRCTUSER[33]) = (0, 0);
( USERCLK *> MAXISRCTUSER[34]) = (0, 0);
( USERCLK *> MAXISRCTUSER[35]) = (0, 0);
( USERCLK *> MAXISRCTUSER[36]) = (0, 0);
( USERCLK *> MAXISRCTUSER[37]) = (0, 0);
( USERCLK *> MAXISRCTUSER[38]) = (0, 0);
( USERCLK *> MAXISRCTUSER[39]) = (0, 0);
( USERCLK *> MAXISRCTUSER[3]) = (0, 0);
( USERCLK *> MAXISRCTUSER[40]) = (0, 0);
( USERCLK *> MAXISRCTUSER[41]) = (0, 0);
( USERCLK *> MAXISRCTUSER[42]) = (0, 0);
( USERCLK *> MAXISRCTUSER[43]) = (0, 0);
( USERCLK *> MAXISRCTUSER[44]) = (0, 0);
( USERCLK *> MAXISRCTUSER[45]) = (0, 0);
( USERCLK *> MAXISRCTUSER[46]) = (0, 0);
( USERCLK *> MAXISRCTUSER[47]) = (0, 0);
( USERCLK *> MAXISRCTUSER[48]) = (0, 0);
( USERCLK *> MAXISRCTUSER[49]) = (0, 0);
( USERCLK *> MAXISRCTUSER[4]) = (0, 0);
( USERCLK *> MAXISRCTUSER[50]) = (0, 0);
( USERCLK *> MAXISRCTUSER[51]) = (0, 0);
( USERCLK *> MAXISRCTUSER[52]) = (0, 0);
( USERCLK *> MAXISRCTUSER[53]) = (0, 0);
( USERCLK *> MAXISRCTUSER[54]) = (0, 0);
( USERCLK *> MAXISRCTUSER[55]) = (0, 0);
( USERCLK *> MAXISRCTUSER[56]) = (0, 0);
( USERCLK *> MAXISRCTUSER[57]) = (0, 0);
( USERCLK *> MAXISRCTUSER[58]) = (0, 0);
( USERCLK *> MAXISRCTUSER[59]) = (0, 0);
( USERCLK *> MAXISRCTUSER[5]) = (0, 0);
( USERCLK *> MAXISRCTUSER[60]) = (0, 0);
( USERCLK *> MAXISRCTUSER[61]) = (0, 0);
( USERCLK *> MAXISRCTUSER[62]) = (0, 0);
( USERCLK *> MAXISRCTUSER[63]) = (0, 0);
( USERCLK *> MAXISRCTUSER[64]) = (0, 0);
( USERCLK *> MAXISRCTUSER[65]) = (0, 0);
( USERCLK *> MAXISRCTUSER[66]) = (0, 0);
( USERCLK *> MAXISRCTUSER[67]) = (0, 0);
( USERCLK *> MAXISRCTUSER[68]) = (0, 0);
( USERCLK *> MAXISRCTUSER[69]) = (0, 0);
( USERCLK *> MAXISRCTUSER[6]) = (0, 0);
( USERCLK *> MAXISRCTUSER[70]) = (0, 0);
( USERCLK *> MAXISRCTUSER[71]) = (0, 0);
( USERCLK *> MAXISRCTUSER[72]) = (0, 0);
( USERCLK *> MAXISRCTUSER[73]) = (0, 0);
( USERCLK *> MAXISRCTUSER[74]) = (0, 0);
( USERCLK *> MAXISRCTUSER[7]) = (0, 0);
( USERCLK *> MAXISRCTUSER[8]) = (0, 0);
( USERCLK *> MAXISRCTUSER[9]) = (0, 0);
( USERCLK *> MAXISRCTVALID) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[0]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[1]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[2]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[3]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[4]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[5]) = (0, 0);
( USERCLK *> PCIERQSEQNUMVLD) = (0, 0);
( USERCLK *> PCIERQSEQNUM[0]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[1]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[2]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[3]) = (0, 0);
( USERCLK *> PCIERQTAGAV[0]) = (0, 0);
( USERCLK *> PCIERQTAGAV[1]) = (0, 0);
( USERCLK *> PCIERQTAGVLD) = (0, 0);
( USERCLK *> PCIERQTAG[0]) = (0, 0);
( USERCLK *> PCIERQTAG[1]) = (0, 0);
( USERCLK *> PCIERQTAG[2]) = (0, 0);
( USERCLK *> PCIERQTAG[3]) = (0, 0);
( USERCLK *> PCIERQTAG[4]) = (0, 0);
( USERCLK *> PCIERQTAG[5]) = (0, 0);
( USERCLK *> PCIETFCNPDAV[0]) = (0, 0);
( USERCLK *> PCIETFCNPDAV[1]) = (0, 0);
( USERCLK *> PCIETFCNPHAV[0]) = (0, 0);
( USERCLK *> PCIETFCNPHAV[1]) = (0, 0);
( USERCLK *> SAXISCCTREADY[0]) = (0, 0);
( USERCLK *> SAXISCCTREADY[1]) = (0, 0);
( USERCLK *> SAXISCCTREADY[2]) = (0, 0);
( USERCLK *> SAXISCCTREADY[3]) = (0, 0);
( USERCLK *> SAXISRQTREADY[0]) = (0, 0);
( USERCLK *> SAXISRQTREADY[1]) = (0, 0);
( USERCLK *> SAXISRQTREADY[2]) = (0, 0);
( USERCLK *> SAXISRQTREADY[3]) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PCIE_3_1.v 0000664 0000000 0000000 00004376636 12327044266 0022635 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : PCIE_3_1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PCIE_3_1 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter ARI_CAP_ENABLE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE",
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2,
parameter CRM_CORE_CLK_FREQ_500 = "TRUE",
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2,
parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE",
parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA,
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000,
parameter MCAP_CONFIGURE_OVERRIDE = "FALSE",
parameter MCAP_ENABLE = "FALSE",
parameter MCAP_EOS_DESIGN_SWITCH = "FALSE",
parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000,
parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE",
parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE",
parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE",
parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE",
parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE",
parameter [15:0] MCAP_VSEC_ID = 16'h0000,
parameter [11:0] MCAP_VSEC_LEN = 12'h02C,
parameter [3:0] MCAP_VSEC_REV = 4'h0,
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03,
parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00,
parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
parameter [7:0] PF0_BIST_REGISTER = 8'h00,
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF0_CLASS_CODE = 24'h000000,
parameter [15:0] PF0_DEVICE_ID = 16'h0000,
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE",
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE",
parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000,
parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000,
parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF0_PB_CAP_VER = 4'h1,
parameter [7:0] PF0_PM_CAP_ID = 8'h01,
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
parameter PF0_RBAR_CAP_ENABLE = "FALSE",
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0,
parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0,
parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0,
parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00,
parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00,
parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00,
parameter [2:0] PF0_RBAR_NUM = 3'h1,
parameter [7:0] PF0_REVISION_ID = 8'h00,
parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF0_TPHR_CAP_ENABLE = "FALSE",
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
parameter PF0_VC_CAP_ENABLE = "FALSE",
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_VC_CAP_VER = 4'h1,
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03,
parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00,
parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
parameter [7:0] PF1_BIST_REGISTER = 8'h00,
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF1_CLASS_CODE = 24'h000000,
parameter [15:0] PF1_DEVICE_ID = 16'h0000,
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE",
parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000,
parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000,
parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF1_PB_CAP_VER = 4'h1,
parameter [7:0] PF1_PM_CAP_ID = 8'h01,
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
parameter PF1_RBAR_CAP_ENABLE = "FALSE",
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0,
parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0,
parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0,
parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00,
parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00,
parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00,
parameter [2:0] PF1_RBAR_NUM = 3'h1,
parameter [7:0] PF1_REVISION_ID = 8'h00,
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF1_TPHR_CAP_ENABLE = "FALSE",
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03,
parameter [2:0] PF2_BAR0_CONTROL = 3'h4,
parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00,
parameter [2:0] PF2_BAR1_CONTROL = 3'h0,
parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_BAR2_CONTROL = 3'h4,
parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_BAR3_CONTROL = 3'h0,
parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_BAR4_CONTROL = 3'h4,
parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_BAR5_CONTROL = 3'h0,
parameter [7:0] PF2_BIST_REGISTER = 8'h00,
parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF2_CLASS_CODE = 24'h000000,
parameter [15:0] PF2_DEVICE_ID = 16'h0000,
parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF2_DPA_CAP_VER = 4'h1,
parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF2_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF2_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF2_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF2_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF2_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00,
parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE",
parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000,
parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000,
parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000,
parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF2_PB_CAP_VER = 4'h1,
parameter [7:0] PF2_PM_CAP_ID = 8'h01,
parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3,
parameter PF2_RBAR_CAP_ENABLE = "FALSE",
parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF2_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0,
parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0,
parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0,
parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00,
parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00,
parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00,
parameter [2:0] PF2_RBAR_NUM = 3'h1,
parameter [7:0] PF2_REVISION_ID = 8'h00,
parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000,
parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF2_TPHR_CAP_ENABLE = "FALSE",
parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF2_TPHR_CAP_VER = 4'h1,
parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03,
parameter [2:0] PF3_BAR0_CONTROL = 3'h4,
parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00,
parameter [2:0] PF3_BAR1_CONTROL = 3'h0,
parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_BAR2_CONTROL = 3'h4,
parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_BAR3_CONTROL = 3'h0,
parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_BAR4_CONTROL = 3'h4,
parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_BAR5_CONTROL = 3'h0,
parameter [7:0] PF3_BIST_REGISTER = 8'h00,
parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF3_CLASS_CODE = 24'h000000,
parameter [15:0] PF3_DEVICE_ID = 16'h0000,
parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF3_DPA_CAP_VER = 4'h1,
parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF3_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF3_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF3_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF3_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF3_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00,
parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE",
parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000,
parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000,
parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000,
parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF3_PB_CAP_VER = 4'h1,
parameter [7:0] PF3_PM_CAP_ID = 8'h01,
parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3,
parameter PF3_RBAR_CAP_ENABLE = "FALSE",
parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF3_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0,
parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0,
parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0,
parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00,
parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00,
parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00,
parameter [2:0] PF3_RBAR_NUM = 3'h1,
parameter [7:0] PF3_REVISION_ID = 8'h00,
parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000,
parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF3_TPHR_CAP_ENABLE = "FALSE",
parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF3_TPHR_CAP_VER = 4'h1,
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE",
parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE",
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "FALSE",
parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE",
parameter PL_DISABLE_SCRAMBLING = "FALSE",
parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE",
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3,
parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4,
parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE",
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00,
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4,
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8,
parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
parameter integer PL_N_FTS_GEN1 = 255,
parameter integer PL_N_FTS_GEN2 = 255,
parameter integer PL_N_FTS_GEN3 = 255,
parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE",
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE",
parameter PL_UPSTREAM_FACING = "TRUE",
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC,
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000,
parameter PM_ENABLE_L23_ENTRY = "FALSE",
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000,
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0,
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000,
parameter SIM_VERSION = "1.0",
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SRIOV_CAP_ENABLE = "FALSE",
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20,
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080,
parameter [11:0] TL_CREDITS_CD = 12'h3E0,
parameter [7:0] TL_CREDITS_CH = 8'h20,
parameter [11:0] TL_CREDITS_NPD = 12'h028,
parameter [7:0] TL_CREDITS_NPH = 8'h20,
parameter [11:0] TL_CREDITS_PD = 12'h198,
parameter [7:0] TL_CREDITS_PH = 8'h20,
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_MODE_ENABLE = "FALSE",
parameter [1:0] TL_PF_ENABLE_REG = 2'h0,
parameter TL_TAG_MGMT_ENABLE = "TRUE",
parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE",
parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE",
parameter TWO_LAYER_MODE_ENABLE = "FALSE",
parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE",
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF0_PM_CAP_ID = 8'h01,
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF0_TPHR_CAP_ENABLE = "FALSE",
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF1_PM_CAP_ID = 8'h01,
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF1_TPHR_CAP_ENABLE = "FALSE",
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF2_PM_CAP_ID = 8'h01,
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF2_TPHR_CAP_ENABLE = "FALSE",
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF3_PM_CAP_ID = 8'h01,
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF3_TPHR_CAP_ENABLE = "FALSE",
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF4_PM_CAP_ID = 8'h01,
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF4_TPHR_CAP_ENABLE = "FALSE",
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF5_PM_CAP_ID = 8'h01,
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF5_TPHR_CAP_ENABLE = "FALSE",
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF6_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF6_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF6_PM_CAP_ID = 8'h01,
parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3,
parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF6_TPHR_CAP_ENABLE = "FALSE",
parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF6_TPHR_CAP_VER = 4'h1,
parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000,
parameter integer VF7_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF7_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF7_PM_CAP_ID = 8'h01,
parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3,
parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF7_TPHR_CAP_ENABLE = "FALSE",
parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF7_TPHR_CAP_VER = 4'h1
)(
output [2:0] CFGCURRENTSPEED,
output [3:0] CFGDPASUBSTATECHANGE,
output CFGERRCOROUT,
output CFGERRFATALOUT,
output CFGERRNONFATALOUT,
output [7:0] CFGEXTFUNCTIONNUMBER,
output CFGEXTREADRECEIVED,
output [9:0] CFGEXTREGISTERNUMBER,
output [3:0] CFGEXTWRITEBYTEENABLE,
output [31:0] CFGEXTWRITEDATA,
output CFGEXTWRITERECEIVED,
output [11:0] CFGFCCPLD,
output [7:0] CFGFCCPLH,
output [11:0] CFGFCNPD,
output [7:0] CFGFCNPH,
output [11:0] CFGFCPD,
output [7:0] CFGFCPH,
output [3:0] CFGFLRINPROCESS,
output [11:0] CFGFUNCTIONPOWERSTATE,
output [15:0] CFGFUNCTIONSTATUS,
output CFGHOTRESETOUT,
output [31:0] CFGINTERRUPTMSIDATA,
output [3:0] CFGINTERRUPTMSIENABLE,
output CFGINTERRUPTMSIFAIL,
output CFGINTERRUPTMSIMASKUPDATE,
output [11:0] CFGINTERRUPTMSIMMENABLE,
output CFGINTERRUPTMSISENT,
output [7:0] CFGINTERRUPTMSIVFENABLE,
output [3:0] CFGINTERRUPTMSIXENABLE,
output CFGINTERRUPTMSIXFAIL,
output [3:0] CFGINTERRUPTMSIXMASK,
output CFGINTERRUPTMSIXSENT,
output [7:0] CFGINTERRUPTMSIXVFENABLE,
output [7:0] CFGINTERRUPTMSIXVFMASK,
output CFGINTERRUPTSENT,
output [1:0] CFGLINKPOWERSTATE,
output CFGLOCALERROR,
output CFGLTRENABLE,
output [5:0] CFGLTSSMSTATE,
output [2:0] CFGMAXPAYLOAD,
output [2:0] CFGMAXREADREQ,
output [31:0] CFGMGMTREADDATA,
output CFGMGMTREADWRITEDONE,
output CFGMSGRECEIVED,
output [7:0] CFGMSGRECEIVEDDATA,
output [4:0] CFGMSGRECEIVEDTYPE,
output CFGMSGTRANSMITDONE,
output [3:0] CFGNEGOTIATEDWIDTH,
output [1:0] CFGOBFFENABLE,
output [15:0] CFGPERFUNCSTATUSDATA,
output CFGPERFUNCTIONUPDATEDONE,
output CFGPHYLINKDOWN,
output [1:0] CFGPHYLINKSTATUS,
output CFGPLSTATUSCHANGE,
output CFGPOWERSTATECHANGEINTERRUPT,
output [3:0] CFGRCBSTATUS,
output [3:0] CFGTPHFUNCTIONNUM,
output [3:0] CFGTPHREQUESTERENABLE,
output [11:0] CFGTPHSTMODE,
output [4:0] CFGTPHSTTADDRESS,
output CFGTPHSTTREADENABLE,
output [3:0] CFGTPHSTTWRITEBYTEVALID,
output [31:0] CFGTPHSTTWRITEDATA,
output CFGTPHSTTWRITEENABLE,
output [7:0] CFGVFFLRINPROCESS,
output [23:0] CFGVFPOWERSTATE,
output [15:0] CFGVFSTATUS,
output [7:0] CFGVFTPHREQUESTERENABLE,
output [23:0] CFGVFTPHSTMODE,
output CONFMCAPDESIGNSWITCH,
output CONFMCAPEOS,
output CONFMCAPINUSEBYPCIE,
output CONFREQREADY,
output [31:0] CONFRESPRDATA,
output CONFRESPVALID,
output [15:0] DBGDATAOUT,
output DBGMCAPCSB,
output [31:0] DBGMCAPDATA,
output DBGMCAPEOS,
output DBGMCAPERROR,
output DBGMCAPMODE,
output DBGMCAPRDATAVALID,
output DBGMCAPRDWRB,
output DBGMCAPRESET,
output DBGPLDATABLOCKRECEIVEDAFTEREDS,
output DBGPLGEN3FRAMINGERRORDETECTED,
output DBGPLGEN3SYNCHEADERERRORDETECTED,
output [7:0] DBGPLINFERREDRXELECTRICALIDLE,
output [15:0] DRPDO,
output DRPRDY,
output LL2LMMASTERTLPSENT0,
output LL2LMMASTERTLPSENT1,
output [3:0] LL2LMMASTERTLPSENTTLPID0,
output [3:0] LL2LMMASTERTLPSENTTLPID1,
output [255:0] LL2LMMAXISRXTDATA,
output [17:0] LL2LMMAXISRXTUSER,
output [7:0] LL2LMMAXISRXTVALID,
output [7:0] LL2LMSAXISTXTREADY,
output [255:0] MAXISCQTDATA,
output [7:0] MAXISCQTKEEP,
output MAXISCQTLAST,
output [84:0] MAXISCQTUSER,
output MAXISCQTVALID,
output [255:0] MAXISRCTDATA,
output [7:0] MAXISRCTKEEP,
output MAXISRCTLAST,
output [74:0] MAXISRCTUSER,
output MAXISRCTVALID,
output [9:0] MICOMPLETIONRAMREADADDRESSAL,
output [9:0] MICOMPLETIONRAMREADADDRESSAU,
output [9:0] MICOMPLETIONRAMREADADDRESSBL,
output [9:0] MICOMPLETIONRAMREADADDRESSBU,
output [3:0] MICOMPLETIONRAMREADENABLEL,
output [3:0] MICOMPLETIONRAMREADENABLEU,
output [9:0] MICOMPLETIONRAMWRITEADDRESSAL,
output [9:0] MICOMPLETIONRAMWRITEADDRESSAU,
output [9:0] MICOMPLETIONRAMWRITEADDRESSBL,
output [9:0] MICOMPLETIONRAMWRITEADDRESSBU,
output [71:0] MICOMPLETIONRAMWRITEDATAL,
output [71:0] MICOMPLETIONRAMWRITEDATAU,
output [3:0] MICOMPLETIONRAMWRITEENABLEL,
output [3:0] MICOMPLETIONRAMWRITEENABLEU,
output [8:0] MIREPLAYRAMADDRESS,
output [1:0] MIREPLAYRAMREADENABLE,
output [143:0] MIREPLAYRAMWRITEDATA,
output [1:0] MIREPLAYRAMWRITEENABLE,
output [8:0] MIREQUESTRAMREADADDRESSA,
output [8:0] MIREQUESTRAMREADADDRESSB,
output [3:0] MIREQUESTRAMREADENABLE,
output [8:0] MIREQUESTRAMWRITEADDRESSA,
output [8:0] MIREQUESTRAMWRITEADDRESSB,
output [143:0] MIREQUESTRAMWRITEDATA,
output [3:0] MIREQUESTRAMWRITEENABLE,
output [5:0] PCIECQNPREQCOUNT,
output PCIEPERST0B,
output PCIEPERST1B,
output [3:0] PCIERQSEQNUM,
output PCIERQSEQNUMVLD,
output [5:0] PCIERQTAG,
output [1:0] PCIERQTAGAV,
output PCIERQTAGVLD,
output [1:0] PCIETFCNPDAV,
output [1:0] PCIETFCNPHAV,
output [1:0] PIPERX0EQCONTROL,
output [5:0] PIPERX0EQLPLFFS,
output [3:0] PIPERX0EQLPTXPRESET,
output [2:0] PIPERX0EQPRESET,
output PIPERX0POLARITY,
output [1:0] PIPERX1EQCONTROL,
output [5:0] PIPERX1EQLPLFFS,
output [3:0] PIPERX1EQLPTXPRESET,
output [2:0] PIPERX1EQPRESET,
output PIPERX1POLARITY,
output [1:0] PIPERX2EQCONTROL,
output [5:0] PIPERX2EQLPLFFS,
output [3:0] PIPERX2EQLPTXPRESET,
output [2:0] PIPERX2EQPRESET,
output PIPERX2POLARITY,
output [1:0] PIPERX3EQCONTROL,
output [5:0] PIPERX3EQLPLFFS,
output [3:0] PIPERX3EQLPTXPRESET,
output [2:0] PIPERX3EQPRESET,
output PIPERX3POLARITY,
output [1:0] PIPERX4EQCONTROL,
output [5:0] PIPERX4EQLPLFFS,
output [3:0] PIPERX4EQLPTXPRESET,
output [2:0] PIPERX4EQPRESET,
output PIPERX4POLARITY,
output [1:0] PIPERX5EQCONTROL,
output [5:0] PIPERX5EQLPLFFS,
output [3:0] PIPERX5EQLPTXPRESET,
output [2:0] PIPERX5EQPRESET,
output PIPERX5POLARITY,
output [1:0] PIPERX6EQCONTROL,
output [5:0] PIPERX6EQLPLFFS,
output [3:0] PIPERX6EQLPTXPRESET,
output [2:0] PIPERX6EQPRESET,
output PIPERX6POLARITY,
output [1:0] PIPERX7EQCONTROL,
output [5:0] PIPERX7EQLPLFFS,
output [3:0] PIPERX7EQLPTXPRESET,
output [2:0] PIPERX7EQPRESET,
output PIPERX7POLARITY,
output [1:0] PIPETX0CHARISK,
output PIPETX0COMPLIANCE,
output [31:0] PIPETX0DATA,
output PIPETX0DATAVALID,
output PIPETX0DEEMPH,
output PIPETX0ELECIDLE,
output [1:0] PIPETX0EQCONTROL,
output [5:0] PIPETX0EQDEEMPH,
output [3:0] PIPETX0EQPRESET,
output [2:0] PIPETX0MARGIN,
output [1:0] PIPETX0POWERDOWN,
output [1:0] PIPETX0RATE,
output PIPETX0RCVRDET,
output PIPETX0RESET,
output PIPETX0STARTBLOCK,
output PIPETX0SWING,
output [1:0] PIPETX0SYNCHEADER,
output [1:0] PIPETX1CHARISK,
output PIPETX1COMPLIANCE,
output [31:0] PIPETX1DATA,
output PIPETX1DATAVALID,
output PIPETX1DEEMPH,
output PIPETX1ELECIDLE,
output [1:0] PIPETX1EQCONTROL,
output [5:0] PIPETX1EQDEEMPH,
output [3:0] PIPETX1EQPRESET,
output [2:0] PIPETX1MARGIN,
output [1:0] PIPETX1POWERDOWN,
output [1:0] PIPETX1RATE,
output PIPETX1RCVRDET,
output PIPETX1RESET,
output PIPETX1STARTBLOCK,
output PIPETX1SWING,
output [1:0] PIPETX1SYNCHEADER,
output [1:0] PIPETX2CHARISK,
output PIPETX2COMPLIANCE,
output [31:0] PIPETX2DATA,
output PIPETX2DATAVALID,
output PIPETX2DEEMPH,
output PIPETX2ELECIDLE,
output [1:0] PIPETX2EQCONTROL,
output [5:0] PIPETX2EQDEEMPH,
output [3:0] PIPETX2EQPRESET,
output [2:0] PIPETX2MARGIN,
output [1:0] PIPETX2POWERDOWN,
output [1:0] PIPETX2RATE,
output PIPETX2RCVRDET,
output PIPETX2RESET,
output PIPETX2STARTBLOCK,
output PIPETX2SWING,
output [1:0] PIPETX2SYNCHEADER,
output [1:0] PIPETX3CHARISK,
output PIPETX3COMPLIANCE,
output [31:0] PIPETX3DATA,
output PIPETX3DATAVALID,
output PIPETX3DEEMPH,
output PIPETX3ELECIDLE,
output [1:0] PIPETX3EQCONTROL,
output [5:0] PIPETX3EQDEEMPH,
output [3:0] PIPETX3EQPRESET,
output [2:0] PIPETX3MARGIN,
output [1:0] PIPETX3POWERDOWN,
output [1:0] PIPETX3RATE,
output PIPETX3RCVRDET,
output PIPETX3RESET,
output PIPETX3STARTBLOCK,
output PIPETX3SWING,
output [1:0] PIPETX3SYNCHEADER,
output [1:0] PIPETX4CHARISK,
output PIPETX4COMPLIANCE,
output [31:0] PIPETX4DATA,
output PIPETX4DATAVALID,
output PIPETX4DEEMPH,
output PIPETX4ELECIDLE,
output [1:0] PIPETX4EQCONTROL,
output [5:0] PIPETX4EQDEEMPH,
output [3:0] PIPETX4EQPRESET,
output [2:0] PIPETX4MARGIN,
output [1:0] PIPETX4POWERDOWN,
output [1:0] PIPETX4RATE,
output PIPETX4RCVRDET,
output PIPETX4RESET,
output PIPETX4STARTBLOCK,
output PIPETX4SWING,
output [1:0] PIPETX4SYNCHEADER,
output [1:0] PIPETX5CHARISK,
output PIPETX5COMPLIANCE,
output [31:0] PIPETX5DATA,
output PIPETX5DATAVALID,
output PIPETX5DEEMPH,
output PIPETX5ELECIDLE,
output [1:0] PIPETX5EQCONTROL,
output [5:0] PIPETX5EQDEEMPH,
output [3:0] PIPETX5EQPRESET,
output [2:0] PIPETX5MARGIN,
output [1:0] PIPETX5POWERDOWN,
output [1:0] PIPETX5RATE,
output PIPETX5RCVRDET,
output PIPETX5RESET,
output PIPETX5STARTBLOCK,
output PIPETX5SWING,
output [1:0] PIPETX5SYNCHEADER,
output [1:0] PIPETX6CHARISK,
output PIPETX6COMPLIANCE,
output [31:0] PIPETX6DATA,
output PIPETX6DATAVALID,
output PIPETX6DEEMPH,
output PIPETX6ELECIDLE,
output [1:0] PIPETX6EQCONTROL,
output [5:0] PIPETX6EQDEEMPH,
output [3:0] PIPETX6EQPRESET,
output [2:0] PIPETX6MARGIN,
output [1:0] PIPETX6POWERDOWN,
output [1:0] PIPETX6RATE,
output PIPETX6RCVRDET,
output PIPETX6RESET,
output PIPETX6STARTBLOCK,
output PIPETX6SWING,
output [1:0] PIPETX6SYNCHEADER,
output [1:0] PIPETX7CHARISK,
output PIPETX7COMPLIANCE,
output [31:0] PIPETX7DATA,
output PIPETX7DATAVALID,
output PIPETX7DEEMPH,
output PIPETX7ELECIDLE,
output [1:0] PIPETX7EQCONTROL,
output [5:0] PIPETX7EQDEEMPH,
output [3:0] PIPETX7EQPRESET,
output [2:0] PIPETX7MARGIN,
output [1:0] PIPETX7POWERDOWN,
output [1:0] PIPETX7RATE,
output PIPETX7RCVRDET,
output PIPETX7RESET,
output PIPETX7STARTBLOCK,
output PIPETX7SWING,
output [1:0] PIPETX7SYNCHEADER,
output PLEQINPROGRESS,
output [1:0] PLEQPHASE,
output [3:0] SAXISCCTREADY,
output [3:0] SAXISRQTREADY,
output [31:0] SPAREOUT,
input CFGCONFIGSPACEENABLE,
input [15:0] CFGDEVID,
input [7:0] CFGDSBUSNUMBER,
input [4:0] CFGDSDEVICENUMBER,
input [2:0] CFGDSFUNCTIONNUMBER,
input [63:0] CFGDSN,
input [7:0] CFGDSPORTNUMBER,
input CFGERRCORIN,
input CFGERRUNCORIN,
input [31:0] CFGEXTREADDATA,
input CFGEXTREADDATAVALID,
input [2:0] CFGFCSEL,
input [3:0] CFGFLRDONE,
input CFGHOTRESETIN,
input [3:0] CFGINTERRUPTINT,
input [2:0] CFGINTERRUPTMSIATTR,
input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER,
input [31:0] CFGINTERRUPTMSIINT,
input [31:0] CFGINTERRUPTMSIPENDINGSTATUS,
input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE,
input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM,
input [3:0] CFGINTERRUPTMSISELECT,
input CFGINTERRUPTMSITPHPRESENT,
input [8:0] CFGINTERRUPTMSITPHSTTAG,
input [1:0] CFGINTERRUPTMSITPHTYPE,
input [63:0] CFGINTERRUPTMSIXADDRESS,
input [31:0] CFGINTERRUPTMSIXDATA,
input CFGINTERRUPTMSIXINT,
input [3:0] CFGINTERRUPTPENDING,
input CFGLINKTRAININGENABLE,
input [18:0] CFGMGMTADDR,
input [3:0] CFGMGMTBYTEENABLE,
input CFGMGMTREAD,
input CFGMGMTTYPE1CFGREGACCESS,
input CFGMGMTWRITE,
input [31:0] CFGMGMTWRITEDATA,
input CFGMSGTRANSMIT,
input [31:0] CFGMSGTRANSMITDATA,
input [2:0] CFGMSGTRANSMITTYPE,
input [2:0] CFGPERFUNCSTATUSCONTROL,
input [3:0] CFGPERFUNCTIONNUMBER,
input CFGPERFUNCTIONOUTPUTREQUEST,
input CFGPOWERSTATECHANGEACK,
input CFGREQPMTRANSITIONL23READY,
input [7:0] CFGREVID,
input [15:0] CFGSUBSYSID,
input [15:0] CFGSUBSYSVENDID,
input [31:0] CFGTPHSTTREADDATA,
input CFGTPHSTTREADDATAVALID,
input [15:0] CFGVENDID,
input [7:0] CFGVFFLRDONE,
input CONFMCAPREQUESTBYCONF,
input [31:0] CONFREQDATA,
input [3:0] CONFREQREGNUM,
input [1:0] CONFREQTYPE,
input CONFREQVALID,
input CORECLK,
input CORECLKMICOMPLETIONRAML,
input CORECLKMICOMPLETIONRAMU,
input CORECLKMIREPLAYRAM,
input CORECLKMIREQUESTRAM,
input DBGCFGLOCALMGMTREGOVERRIDE,
input [3:0] DBGDATASEL,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input [13:0] LL2LMSAXISTXTUSER,
input LL2LMSAXISTXTVALID,
input [3:0] LL2LMTXTLPID0,
input [3:0] LL2LMTXTLPID1,
input [21:0] MAXISCQTREADY,
input [21:0] MAXISRCTREADY,
input MCAPCLK,
input MGMTRESETN,
input MGMTSTICKYRESETN,
input [143:0] MICOMPLETIONRAMREADDATA,
input [143:0] MIREPLAYRAMREADDATA,
input [143:0] MIREQUESTRAMREADDATA,
input PCIECQNPREQ,
input PIPECLK,
input [5:0] PIPEEQFS,
input [5:0] PIPEEQLF,
input PIPERESETN,
input [1:0] PIPERX0CHARISK,
input [31:0] PIPERX0DATA,
input PIPERX0DATAVALID,
input PIPERX0ELECIDLE,
input PIPERX0EQDONE,
input PIPERX0EQLPADAPTDONE,
input PIPERX0EQLPLFFSSEL,
input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET,
input PIPERX0PHYSTATUS,
input PIPERX0STARTBLOCK,
input [2:0] PIPERX0STATUS,
input [1:0] PIPERX0SYNCHEADER,
input PIPERX0VALID,
input [1:0] PIPERX1CHARISK,
input [31:0] PIPERX1DATA,
input PIPERX1DATAVALID,
input PIPERX1ELECIDLE,
input PIPERX1EQDONE,
input PIPERX1EQLPADAPTDONE,
input PIPERX1EQLPLFFSSEL,
input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET,
input PIPERX1PHYSTATUS,
input PIPERX1STARTBLOCK,
input [2:0] PIPERX1STATUS,
input [1:0] PIPERX1SYNCHEADER,
input PIPERX1VALID,
input [1:0] PIPERX2CHARISK,
input [31:0] PIPERX2DATA,
input PIPERX2DATAVALID,
input PIPERX2ELECIDLE,
input PIPERX2EQDONE,
input PIPERX2EQLPADAPTDONE,
input PIPERX2EQLPLFFSSEL,
input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET,
input PIPERX2PHYSTATUS,
input PIPERX2STARTBLOCK,
input [2:0] PIPERX2STATUS,
input [1:0] PIPERX2SYNCHEADER,
input PIPERX2VALID,
input [1:0] PIPERX3CHARISK,
input [31:0] PIPERX3DATA,
input PIPERX3DATAVALID,
input PIPERX3ELECIDLE,
input PIPERX3EQDONE,
input PIPERX3EQLPADAPTDONE,
input PIPERX3EQLPLFFSSEL,
input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET,
input PIPERX3PHYSTATUS,
input PIPERX3STARTBLOCK,
input [2:0] PIPERX3STATUS,
input [1:0] PIPERX3SYNCHEADER,
input PIPERX3VALID,
input [1:0] PIPERX4CHARISK,
input [31:0] PIPERX4DATA,
input PIPERX4DATAVALID,
input PIPERX4ELECIDLE,
input PIPERX4EQDONE,
input PIPERX4EQLPADAPTDONE,
input PIPERX4EQLPLFFSSEL,
input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET,
input PIPERX4PHYSTATUS,
input PIPERX4STARTBLOCK,
input [2:0] PIPERX4STATUS,
input [1:0] PIPERX4SYNCHEADER,
input PIPERX4VALID,
input [1:0] PIPERX5CHARISK,
input [31:0] PIPERX5DATA,
input PIPERX5DATAVALID,
input PIPERX5ELECIDLE,
input PIPERX5EQDONE,
input PIPERX5EQLPADAPTDONE,
input PIPERX5EQLPLFFSSEL,
input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET,
input PIPERX5PHYSTATUS,
input PIPERX5STARTBLOCK,
input [2:0] PIPERX5STATUS,
input [1:0] PIPERX5SYNCHEADER,
input PIPERX5VALID,
input [1:0] PIPERX6CHARISK,
input [31:0] PIPERX6DATA,
input PIPERX6DATAVALID,
input PIPERX6ELECIDLE,
input PIPERX6EQDONE,
input PIPERX6EQLPADAPTDONE,
input PIPERX6EQLPLFFSSEL,
input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET,
input PIPERX6PHYSTATUS,
input PIPERX6STARTBLOCK,
input [2:0] PIPERX6STATUS,
input [1:0] PIPERX6SYNCHEADER,
input PIPERX6VALID,
input [1:0] PIPERX7CHARISK,
input [31:0] PIPERX7DATA,
input PIPERX7DATAVALID,
input PIPERX7ELECIDLE,
input PIPERX7EQDONE,
input PIPERX7EQLPADAPTDONE,
input PIPERX7EQLPLFFSSEL,
input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET,
input PIPERX7PHYSTATUS,
input PIPERX7STARTBLOCK,
input [2:0] PIPERX7STATUS,
input [1:0] PIPERX7SYNCHEADER,
input PIPERX7VALID,
input [17:0] PIPETX0EQCOEFF,
input PIPETX0EQDONE,
input [17:0] PIPETX1EQCOEFF,
input PIPETX1EQDONE,
input [17:0] PIPETX2EQCOEFF,
input PIPETX2EQDONE,
input [17:0] PIPETX3EQCOEFF,
input PIPETX3EQDONE,
input [17:0] PIPETX4EQCOEFF,
input PIPETX4EQDONE,
input [17:0] PIPETX5EQCOEFF,
input PIPETX5EQDONE,
input [17:0] PIPETX6EQCOEFF,
input PIPETX6EQDONE,
input [17:0] PIPETX7EQCOEFF,
input PIPETX7EQDONE,
input PLEQRESETEIEOSCOUNT,
input PLGEN2UPSTREAMPREFERDEEMPH,
input RESETN,
input [255:0] SAXISCCTDATA,
input [7:0] SAXISCCTKEEP,
input SAXISCCTLAST,
input [32:0] SAXISCCTUSER,
input SAXISCCTVALID,
input [255:0] SAXISRQTDATA,
input [7:0] SAXISRQTKEEP,
input SAXISRQTLAST,
input [59:0] SAXISRQTUSER,
input SAXISRQTVALID,
input [31:0] SPAREIN,
input USERCLK
);
// define constants
localparam MODULE_NAME = "PCIE_3_1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [40:1] ARI_CAP_ENABLE_REG = ARI_CAP_ENABLE;
localparam [40:1] AXISTEN_IF_CC_ALIGNMENT_MODE_REG = AXISTEN_IF_CC_ALIGNMENT_MODE;
localparam [40:1] AXISTEN_IF_CC_PARITY_CHK_REG = AXISTEN_IF_CC_PARITY_CHK;
localparam [40:1] AXISTEN_IF_CQ_ALIGNMENT_MODE_REG = AXISTEN_IF_CQ_ALIGNMENT_MODE;
localparam [40:1] AXISTEN_IF_ENABLE_CLIENT_TAG_REG = AXISTEN_IF_ENABLE_CLIENT_TAG;
localparam [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE_REG = AXISTEN_IF_ENABLE_MSG_ROUTE;
localparam [40:1] AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG = AXISTEN_IF_ENABLE_RX_MSG_INTFC;
localparam [40:1] AXISTEN_IF_RC_ALIGNMENT_MODE_REG = AXISTEN_IF_RC_ALIGNMENT_MODE;
localparam [40:1] AXISTEN_IF_RC_STRADDLE_REG = AXISTEN_IF_RC_STRADDLE;
localparam [40:1] AXISTEN_IF_RQ_ALIGNMENT_MODE_REG = AXISTEN_IF_RQ_ALIGNMENT_MODE;
localparam [40:1] AXISTEN_IF_RQ_PARITY_CHK_REG = AXISTEN_IF_RQ_PARITY_CHK;
localparam [1:0] AXISTEN_IF_WIDTH_REG = AXISTEN_IF_WIDTH;
localparam [40:1] CRM_CORE_CLK_FREQ_500_REG = CRM_CORE_CLK_FREQ_500;
localparam [1:0] CRM_USER_CLK_FREQ_REG = CRM_USER_CLK_FREQ;
localparam [40:1] DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG = DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE;
localparam [40:1] DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG = DEBUG_PL_DISABLE_EI_INFER_IN_L0;
localparam [40:1] DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG = DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS;
localparam [7:0] DNSTREAM_LINK_NUM_REG = DNSTREAM_LINK_NUM;
localparam [8:0] LL_ACK_TIMEOUT_REG = LL_ACK_TIMEOUT;
localparam [40:1] LL_ACK_TIMEOUT_EN_REG = LL_ACK_TIMEOUT_EN;
localparam [1:0] LL_ACK_TIMEOUT_FUNC_REG = LL_ACK_TIMEOUT_FUNC;
localparam [15:0] LL_CPL_FC_UPDATE_TIMER_REG = LL_CPL_FC_UPDATE_TIMER;
localparam [40:1] LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG = LL_CPL_FC_UPDATE_TIMER_OVERRIDE;
localparam [15:0] LL_FC_UPDATE_TIMER_REG = LL_FC_UPDATE_TIMER;
localparam [40:1] LL_FC_UPDATE_TIMER_OVERRIDE_REG = LL_FC_UPDATE_TIMER_OVERRIDE;
localparam [15:0] LL_NP_FC_UPDATE_TIMER_REG = LL_NP_FC_UPDATE_TIMER;
localparam [40:1] LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG = LL_NP_FC_UPDATE_TIMER_OVERRIDE;
localparam [15:0] LL_P_FC_UPDATE_TIMER_REG = LL_P_FC_UPDATE_TIMER;
localparam [40:1] LL_P_FC_UPDATE_TIMER_OVERRIDE_REG = LL_P_FC_UPDATE_TIMER_OVERRIDE;
localparam [8:0] LL_REPLAY_TIMEOUT_REG = LL_REPLAY_TIMEOUT;
localparam [40:1] LL_REPLAY_TIMEOUT_EN_REG = LL_REPLAY_TIMEOUT_EN;
localparam [1:0] LL_REPLAY_TIMEOUT_FUNC_REG = LL_REPLAY_TIMEOUT_FUNC;
localparam [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG = LTR_TX_MESSAGE_MINIMUM_INTERVAL;
localparam [40:1] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG = LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE;
localparam [40:1] LTR_TX_MESSAGE_ON_LTR_ENABLE_REG = LTR_TX_MESSAGE_ON_LTR_ENABLE;
localparam [11:0] MCAP_CAP_NEXTPTR_REG = MCAP_CAP_NEXTPTR;
localparam [40:1] MCAP_CONFIGURE_OVERRIDE_REG = MCAP_CONFIGURE_OVERRIDE;
localparam [40:1] MCAP_ENABLE_REG = MCAP_ENABLE;
localparam [40:1] MCAP_EOS_DESIGN_SWITCH_REG = MCAP_EOS_DESIGN_SWITCH;
localparam [31:0] MCAP_FPGA_BITSTREAM_VERSION_REG = MCAP_FPGA_BITSTREAM_VERSION;
localparam [40:1] MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_IO_ENABLE_DESIGN_SWITCH;
localparam [40:1] MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG = MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH;
localparam [40:1] MCAP_INPUT_GATE_DESIGN_SWITCH_REG = MCAP_INPUT_GATE_DESIGN_SWITCH;
localparam [40:1] MCAP_INTERRUPT_ON_MCAP_EOS_REG = MCAP_INTERRUPT_ON_MCAP_EOS;
localparam [40:1] MCAP_INTERRUPT_ON_MCAP_ERROR_REG = MCAP_INTERRUPT_ON_MCAP_ERROR;
localparam [15:0] MCAP_VSEC_ID_REG = MCAP_VSEC_ID;
localparam [11:0] MCAP_VSEC_LEN_REG = MCAP_VSEC_LEN;
localparam [3:0] MCAP_VSEC_REV_REG = MCAP_VSEC_REV;
localparam [40:1] PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF0_AER_CAP_ECRC_CHECK_CAPABLE;
localparam [40:1] PF0_AER_CAP_ECRC_GEN_CAPABLE_REG = PF0_AER_CAP_ECRC_GEN_CAPABLE;
localparam [11:0] PF0_AER_CAP_NEXTPTR_REG = PF0_AER_CAP_NEXTPTR;
localparam [11:0] PF0_ARI_CAP_NEXTPTR_REG = PF0_ARI_CAP_NEXTPTR;
localparam [7:0] PF0_ARI_CAP_NEXT_FUNC_REG = PF0_ARI_CAP_NEXT_FUNC;
localparam [3:0] PF0_ARI_CAP_VER_REG = PF0_ARI_CAP_VER;
localparam [5:0] PF0_BAR0_APERTURE_SIZE_REG = PF0_BAR0_APERTURE_SIZE;
localparam [2:0] PF0_BAR0_CONTROL_REG = PF0_BAR0_CONTROL;
localparam [5:0] PF0_BAR1_APERTURE_SIZE_REG = PF0_BAR1_APERTURE_SIZE;
localparam [2:0] PF0_BAR1_CONTROL_REG = PF0_BAR1_CONTROL;
localparam [4:0] PF0_BAR2_APERTURE_SIZE_REG = PF0_BAR2_APERTURE_SIZE;
localparam [2:0] PF0_BAR2_CONTROL_REG = PF0_BAR2_CONTROL;
localparam [4:0] PF0_BAR3_APERTURE_SIZE_REG = PF0_BAR3_APERTURE_SIZE;
localparam [2:0] PF0_BAR3_CONTROL_REG = PF0_BAR3_CONTROL;
localparam [4:0] PF0_BAR4_APERTURE_SIZE_REG = PF0_BAR4_APERTURE_SIZE;
localparam [2:0] PF0_BAR4_CONTROL_REG = PF0_BAR4_CONTROL;
localparam [4:0] PF0_BAR5_APERTURE_SIZE_REG = PF0_BAR5_APERTURE_SIZE;
localparam [2:0] PF0_BAR5_CONTROL_REG = PF0_BAR5_CONTROL;
localparam [7:0] PF0_BIST_REGISTER_REG = PF0_BIST_REGISTER;
localparam [7:0] PF0_CAPABILITY_POINTER_REG = PF0_CAPABILITY_POINTER;
localparam [23:0] PF0_CLASS_CODE_REG = PF0_CLASS_CODE;
localparam [15:0] PF0_DEVICE_ID_REG = PF0_DEVICE_ID;
localparam [40:1] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT;
localparam [40:1] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT;
localparam [40:1] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT;
localparam [40:1] PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG = PF0_DEV_CAP2_ARI_FORWARD_ENABLE;
localparam [40:1] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG = PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE;
localparam [40:1] PF0_DEV_CAP2_LTR_SUPPORT_REG = PF0_DEV_CAP2_LTR_SUPPORT;
localparam [1:0] PF0_DEV_CAP2_OBFF_SUPPORT_REG = PF0_DEV_CAP2_OBFF_SUPPORT;
localparam [40:1] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG = PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT;
localparam [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY;
localparam [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG = PF0_DEV_CAP_ENDPOINT_L1_LATENCY;
localparam [40:1] PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG = PF0_DEV_CAP_EXT_TAG_SUPPORTED;
localparam [40:1] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG = PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE;
localparam [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF0_DEV_CAP_MAX_PAYLOAD_SIZE;
localparam [11:0] PF0_DPA_CAP_NEXTPTR_REG = PF0_DPA_CAP_NEXTPTR;
localparam [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL_REG = PF0_DPA_CAP_SUB_STATE_CONTROL;
localparam [40:1] PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF0_DPA_CAP_SUB_STATE_CONTROL_EN;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6;
localparam [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7;
localparam [3:0] PF0_DPA_CAP_VER_REG = PF0_DPA_CAP_VER;
localparam [11:0] PF0_DSN_CAP_NEXTPTR_REG = PF0_DSN_CAP_NEXTPTR;
localparam [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE_REG = PF0_EXPANSION_ROM_APERTURE_SIZE;
localparam [40:1] PF0_EXPANSION_ROM_ENABLE_REG = PF0_EXPANSION_ROM_ENABLE;
localparam [7:0] PF0_INTERRUPT_LINE_REG = PF0_INTERRUPT_LINE;
localparam [2:0] PF0_INTERRUPT_PIN_REG = PF0_INTERRUPT_PIN;
localparam [1:0] PF0_LINK_CAP_ASPM_SUPPORT_REG = PF0_LINK_CAP_ASPM_SUPPORT;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2;
localparam [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2;
localparam [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3;
localparam [40:1] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG = PF0_LINK_STATUS_SLOT_CLOCK_CONFIG;
localparam [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG = PF0_LTR_CAP_MAX_NOSNOOP_LAT;
localparam [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT_REG = PF0_LTR_CAP_MAX_SNOOP_LAT;
localparam [11:0] PF0_LTR_CAP_NEXTPTR_REG = PF0_LTR_CAP_NEXTPTR;
localparam [3:0] PF0_LTR_CAP_VER_REG = PF0_LTR_CAP_VER;
localparam [7:0] PF0_MSIX_CAP_NEXTPTR_REG = PF0_MSIX_CAP_NEXTPTR;
localparam [2:0] PF0_MSIX_CAP_PBA_BIR_REG = PF0_MSIX_CAP_PBA_BIR;
localparam [28:0] PF0_MSIX_CAP_PBA_OFFSET_REG = PF0_MSIX_CAP_PBA_OFFSET;
localparam [2:0] PF0_MSIX_CAP_TABLE_BIR_REG = PF0_MSIX_CAP_TABLE_BIR;
localparam [28:0] PF0_MSIX_CAP_TABLE_OFFSET_REG = PF0_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] PF0_MSIX_CAP_TABLE_SIZE_REG = PF0_MSIX_CAP_TABLE_SIZE;
localparam [2:0] PF0_MSI_CAP_MULTIMSGCAP_REG = PF0_MSI_CAP_MULTIMSGCAP;
localparam [7:0] PF0_MSI_CAP_NEXTPTR_REG = PF0_MSI_CAP_NEXTPTR;
localparam [40:1] PF0_MSI_CAP_PERVECMASKCAP_REG = PF0_MSI_CAP_PERVECMASKCAP;
localparam [31:0] PF0_PB_CAP_DATA_REG_D0_REG = PF0_PB_CAP_DATA_REG_D0;
localparam [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF0_PB_CAP_DATA_REG_D0_SUSTAINED;
localparam [31:0] PF0_PB_CAP_DATA_REG_D1_REG = PF0_PB_CAP_DATA_REG_D1;
localparam [31:0] PF0_PB_CAP_DATA_REG_D3HOT_REG = PF0_PB_CAP_DATA_REG_D3HOT;
localparam [11:0] PF0_PB_CAP_NEXTPTR_REG = PF0_PB_CAP_NEXTPTR;
localparam [40:1] PF0_PB_CAP_SYSTEM_ALLOCATED_REG = PF0_PB_CAP_SYSTEM_ALLOCATED;
localparam [3:0] PF0_PB_CAP_VER_REG = PF0_PB_CAP_VER;
localparam [7:0] PF0_PM_CAP_ID_REG = PF0_PM_CAP_ID;
localparam [7:0] PF0_PM_CAP_NEXTPTR_REG = PF0_PM_CAP_NEXTPTR;
localparam [40:1] PF0_PM_CAP_PMESUPPORT_D0_REG = PF0_PM_CAP_PMESUPPORT_D0;
localparam [40:1] PF0_PM_CAP_PMESUPPORT_D1_REG = PF0_PM_CAP_PMESUPPORT_D1;
localparam [40:1] PF0_PM_CAP_PMESUPPORT_D3HOT_REG = PF0_PM_CAP_PMESUPPORT_D3HOT;
localparam [40:1] PF0_PM_CAP_SUPP_D1_STATE_REG = PF0_PM_CAP_SUPP_D1_STATE;
localparam [2:0] PF0_PM_CAP_VER_ID_REG = PF0_PM_CAP_VER_ID;
localparam [40:1] PF0_PM_CSR_NOSOFTRESET_REG = PF0_PM_CSR_NOSOFTRESET;
localparam [40:1] PF0_RBAR_CAP_ENABLE_REG = PF0_RBAR_CAP_ENABLE;
localparam [11:0] PF0_RBAR_CAP_NEXTPTR_REG = PF0_RBAR_CAP_NEXTPTR;
localparam [19:0] PF0_RBAR_CAP_SIZE0_REG = PF0_RBAR_CAP_SIZE0;
localparam [19:0] PF0_RBAR_CAP_SIZE1_REG = PF0_RBAR_CAP_SIZE1;
localparam [19:0] PF0_RBAR_CAP_SIZE2_REG = PF0_RBAR_CAP_SIZE2;
localparam [3:0] PF0_RBAR_CAP_VER_REG = PF0_RBAR_CAP_VER;
localparam [2:0] PF0_RBAR_CONTROL_INDEX0_REG = PF0_RBAR_CONTROL_INDEX0;
localparam [2:0] PF0_RBAR_CONTROL_INDEX1_REG = PF0_RBAR_CONTROL_INDEX1;
localparam [2:0] PF0_RBAR_CONTROL_INDEX2_REG = PF0_RBAR_CONTROL_INDEX2;
localparam [4:0] PF0_RBAR_CONTROL_SIZE0_REG = PF0_RBAR_CONTROL_SIZE0;
localparam [4:0] PF0_RBAR_CONTROL_SIZE1_REG = PF0_RBAR_CONTROL_SIZE1;
localparam [4:0] PF0_RBAR_CONTROL_SIZE2_REG = PF0_RBAR_CONTROL_SIZE2;
localparam [2:0] PF0_RBAR_NUM_REG = PF0_RBAR_NUM;
localparam [7:0] PF0_REVISION_ID_REG = PF0_REVISION_ID;
localparam [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG = PF0_SECONDARY_PCIE_CAP_NEXTPTR;
localparam [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE_REG = PF0_SRIOV_BAR0_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR0_CONTROL_REG = PF0_SRIOV_BAR0_CONTROL;
localparam [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE_REG = PF0_SRIOV_BAR1_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR1_CONTROL_REG = PF0_SRIOV_BAR1_CONTROL;
localparam [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE_REG = PF0_SRIOV_BAR2_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR2_CONTROL_REG = PF0_SRIOV_BAR2_CONTROL;
localparam [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE_REG = PF0_SRIOV_BAR3_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR3_CONTROL_REG = PF0_SRIOV_BAR3_CONTROL;
localparam [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE_REG = PF0_SRIOV_BAR4_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR4_CONTROL_REG = PF0_SRIOV_BAR4_CONTROL;
localparam [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE_REG = PF0_SRIOV_BAR5_APERTURE_SIZE;
localparam [2:0] PF0_SRIOV_BAR5_CONTROL_REG = PF0_SRIOV_BAR5_CONTROL;
localparam [15:0] PF0_SRIOV_CAP_INITIAL_VF_REG = PF0_SRIOV_CAP_INITIAL_VF;
localparam [11:0] PF0_SRIOV_CAP_NEXTPTR_REG = PF0_SRIOV_CAP_NEXTPTR;
localparam [15:0] PF0_SRIOV_CAP_TOTAL_VF_REG = PF0_SRIOV_CAP_TOTAL_VF;
localparam [3:0] PF0_SRIOV_CAP_VER_REG = PF0_SRIOV_CAP_VER;
localparam [15:0] PF0_SRIOV_FIRST_VF_OFFSET_REG = PF0_SRIOV_FIRST_VF_OFFSET;
localparam [15:0] PF0_SRIOV_FUNC_DEP_LINK_REG = PF0_SRIOV_FUNC_DEP_LINK;
localparam [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF0_SRIOV_SUPPORTED_PAGE_SIZE;
localparam [15:0] PF0_SRIOV_VF_DEVICE_ID_REG = PF0_SRIOV_VF_DEVICE_ID;
localparam [15:0] PF0_SUBSYSTEM_ID_REG = PF0_SUBSYSTEM_ID;
localparam [40:1] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF0_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] PF0_TPHR_CAP_ENABLE_REG = PF0_TPHR_CAP_ENABLE;
localparam [40:1] PF0_TPHR_CAP_INT_VEC_MODE_REG = PF0_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] PF0_TPHR_CAP_NEXTPTR_REG = PF0_TPHR_CAP_NEXTPTR;
localparam [2:0] PF0_TPHR_CAP_ST_MODE_SEL_REG = PF0_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] PF0_TPHR_CAP_ST_TABLE_LOC_REG = PF0_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE_REG = PF0_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] PF0_TPHR_CAP_VER_REG = PF0_TPHR_CAP_VER;
localparam [40:1] PF0_VC_CAP_ENABLE_REG = PF0_VC_CAP_ENABLE;
localparam [11:0] PF0_VC_CAP_NEXTPTR_REG = PF0_VC_CAP_NEXTPTR;
localparam [3:0] PF0_VC_CAP_VER_REG = PF0_VC_CAP_VER;
localparam [40:1] PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF1_AER_CAP_ECRC_CHECK_CAPABLE;
localparam [40:1] PF1_AER_CAP_ECRC_GEN_CAPABLE_REG = PF1_AER_CAP_ECRC_GEN_CAPABLE;
localparam [11:0] PF1_AER_CAP_NEXTPTR_REG = PF1_AER_CAP_NEXTPTR;
localparam [11:0] PF1_ARI_CAP_NEXTPTR_REG = PF1_ARI_CAP_NEXTPTR;
localparam [7:0] PF1_ARI_CAP_NEXT_FUNC_REG = PF1_ARI_CAP_NEXT_FUNC;
localparam [5:0] PF1_BAR0_APERTURE_SIZE_REG = PF1_BAR0_APERTURE_SIZE;
localparam [2:0] PF1_BAR0_CONTROL_REG = PF1_BAR0_CONTROL;
localparam [5:0] PF1_BAR1_APERTURE_SIZE_REG = PF1_BAR1_APERTURE_SIZE;
localparam [2:0] PF1_BAR1_CONTROL_REG = PF1_BAR1_CONTROL;
localparam [4:0] PF1_BAR2_APERTURE_SIZE_REG = PF1_BAR2_APERTURE_SIZE;
localparam [2:0] PF1_BAR2_CONTROL_REG = PF1_BAR2_CONTROL;
localparam [4:0] PF1_BAR3_APERTURE_SIZE_REG = PF1_BAR3_APERTURE_SIZE;
localparam [2:0] PF1_BAR3_CONTROL_REG = PF1_BAR3_CONTROL;
localparam [4:0] PF1_BAR4_APERTURE_SIZE_REG = PF1_BAR4_APERTURE_SIZE;
localparam [2:0] PF1_BAR4_CONTROL_REG = PF1_BAR4_CONTROL;
localparam [4:0] PF1_BAR5_APERTURE_SIZE_REG = PF1_BAR5_APERTURE_SIZE;
localparam [2:0] PF1_BAR5_CONTROL_REG = PF1_BAR5_CONTROL;
localparam [7:0] PF1_BIST_REGISTER_REG = PF1_BIST_REGISTER;
localparam [7:0] PF1_CAPABILITY_POINTER_REG = PF1_CAPABILITY_POINTER;
localparam [23:0] PF1_CLASS_CODE_REG = PF1_CLASS_CODE;
localparam [15:0] PF1_DEVICE_ID_REG = PF1_DEVICE_ID;
localparam [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF1_DEV_CAP_MAX_PAYLOAD_SIZE;
localparam [11:0] PF1_DPA_CAP_NEXTPTR_REG = PF1_DPA_CAP_NEXTPTR;
localparam [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL_REG = PF1_DPA_CAP_SUB_STATE_CONTROL;
localparam [40:1] PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF1_DPA_CAP_SUB_STATE_CONTROL_EN;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6;
localparam [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7;
localparam [3:0] PF1_DPA_CAP_VER_REG = PF1_DPA_CAP_VER;
localparam [11:0] PF1_DSN_CAP_NEXTPTR_REG = PF1_DSN_CAP_NEXTPTR;
localparam [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE_REG = PF1_EXPANSION_ROM_APERTURE_SIZE;
localparam [40:1] PF1_EXPANSION_ROM_ENABLE_REG = PF1_EXPANSION_ROM_ENABLE;
localparam [7:0] PF1_INTERRUPT_LINE_REG = PF1_INTERRUPT_LINE;
localparam [2:0] PF1_INTERRUPT_PIN_REG = PF1_INTERRUPT_PIN;
localparam [7:0] PF1_MSIX_CAP_NEXTPTR_REG = PF1_MSIX_CAP_NEXTPTR;
localparam [2:0] PF1_MSIX_CAP_PBA_BIR_REG = PF1_MSIX_CAP_PBA_BIR;
localparam [28:0] PF1_MSIX_CAP_PBA_OFFSET_REG = PF1_MSIX_CAP_PBA_OFFSET;
localparam [2:0] PF1_MSIX_CAP_TABLE_BIR_REG = PF1_MSIX_CAP_TABLE_BIR;
localparam [28:0] PF1_MSIX_CAP_TABLE_OFFSET_REG = PF1_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] PF1_MSIX_CAP_TABLE_SIZE_REG = PF1_MSIX_CAP_TABLE_SIZE;
localparam [2:0] PF1_MSI_CAP_MULTIMSGCAP_REG = PF1_MSI_CAP_MULTIMSGCAP;
localparam [7:0] PF1_MSI_CAP_NEXTPTR_REG = PF1_MSI_CAP_NEXTPTR;
localparam [40:1] PF1_MSI_CAP_PERVECMASKCAP_REG = PF1_MSI_CAP_PERVECMASKCAP;
localparam [31:0] PF1_PB_CAP_DATA_REG_D0_REG = PF1_PB_CAP_DATA_REG_D0;
localparam [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF1_PB_CAP_DATA_REG_D0_SUSTAINED;
localparam [31:0] PF1_PB_CAP_DATA_REG_D1_REG = PF1_PB_CAP_DATA_REG_D1;
localparam [31:0] PF1_PB_CAP_DATA_REG_D3HOT_REG = PF1_PB_CAP_DATA_REG_D3HOT;
localparam [11:0] PF1_PB_CAP_NEXTPTR_REG = PF1_PB_CAP_NEXTPTR;
localparam [40:1] PF1_PB_CAP_SYSTEM_ALLOCATED_REG = PF1_PB_CAP_SYSTEM_ALLOCATED;
localparam [3:0] PF1_PB_CAP_VER_REG = PF1_PB_CAP_VER;
localparam [7:0] PF1_PM_CAP_ID_REG = PF1_PM_CAP_ID;
localparam [7:0] PF1_PM_CAP_NEXTPTR_REG = PF1_PM_CAP_NEXTPTR;
localparam [2:0] PF1_PM_CAP_VER_ID_REG = PF1_PM_CAP_VER_ID;
localparam [40:1] PF1_RBAR_CAP_ENABLE_REG = PF1_RBAR_CAP_ENABLE;
localparam [11:0] PF1_RBAR_CAP_NEXTPTR_REG = PF1_RBAR_CAP_NEXTPTR;
localparam [19:0] PF1_RBAR_CAP_SIZE0_REG = PF1_RBAR_CAP_SIZE0;
localparam [19:0] PF1_RBAR_CAP_SIZE1_REG = PF1_RBAR_CAP_SIZE1;
localparam [19:0] PF1_RBAR_CAP_SIZE2_REG = PF1_RBAR_CAP_SIZE2;
localparam [3:0] PF1_RBAR_CAP_VER_REG = PF1_RBAR_CAP_VER;
localparam [2:0] PF1_RBAR_CONTROL_INDEX0_REG = PF1_RBAR_CONTROL_INDEX0;
localparam [2:0] PF1_RBAR_CONTROL_INDEX1_REG = PF1_RBAR_CONTROL_INDEX1;
localparam [2:0] PF1_RBAR_CONTROL_INDEX2_REG = PF1_RBAR_CONTROL_INDEX2;
localparam [4:0] PF1_RBAR_CONTROL_SIZE0_REG = PF1_RBAR_CONTROL_SIZE0;
localparam [4:0] PF1_RBAR_CONTROL_SIZE1_REG = PF1_RBAR_CONTROL_SIZE1;
localparam [4:0] PF1_RBAR_CONTROL_SIZE2_REG = PF1_RBAR_CONTROL_SIZE2;
localparam [2:0] PF1_RBAR_NUM_REG = PF1_RBAR_NUM;
localparam [7:0] PF1_REVISION_ID_REG = PF1_REVISION_ID;
localparam [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE_REG = PF1_SRIOV_BAR0_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR0_CONTROL_REG = PF1_SRIOV_BAR0_CONTROL;
localparam [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE_REG = PF1_SRIOV_BAR1_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR1_CONTROL_REG = PF1_SRIOV_BAR1_CONTROL;
localparam [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE_REG = PF1_SRIOV_BAR2_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR2_CONTROL_REG = PF1_SRIOV_BAR2_CONTROL;
localparam [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE_REG = PF1_SRIOV_BAR3_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR3_CONTROL_REG = PF1_SRIOV_BAR3_CONTROL;
localparam [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE_REG = PF1_SRIOV_BAR4_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR4_CONTROL_REG = PF1_SRIOV_BAR4_CONTROL;
localparam [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE_REG = PF1_SRIOV_BAR5_APERTURE_SIZE;
localparam [2:0] PF1_SRIOV_BAR5_CONTROL_REG = PF1_SRIOV_BAR5_CONTROL;
localparam [15:0] PF1_SRIOV_CAP_INITIAL_VF_REG = PF1_SRIOV_CAP_INITIAL_VF;
localparam [11:0] PF1_SRIOV_CAP_NEXTPTR_REG = PF1_SRIOV_CAP_NEXTPTR;
localparam [15:0] PF1_SRIOV_CAP_TOTAL_VF_REG = PF1_SRIOV_CAP_TOTAL_VF;
localparam [3:0] PF1_SRIOV_CAP_VER_REG = PF1_SRIOV_CAP_VER;
localparam [15:0] PF1_SRIOV_FIRST_VF_OFFSET_REG = PF1_SRIOV_FIRST_VF_OFFSET;
localparam [15:0] PF1_SRIOV_FUNC_DEP_LINK_REG = PF1_SRIOV_FUNC_DEP_LINK;
localparam [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF1_SRIOV_SUPPORTED_PAGE_SIZE;
localparam [15:0] PF1_SRIOV_VF_DEVICE_ID_REG = PF1_SRIOV_VF_DEVICE_ID;
localparam [15:0] PF1_SUBSYSTEM_ID_REG = PF1_SUBSYSTEM_ID;
localparam [40:1] PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF1_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] PF1_TPHR_CAP_ENABLE_REG = PF1_TPHR_CAP_ENABLE;
localparam [40:1] PF1_TPHR_CAP_INT_VEC_MODE_REG = PF1_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] PF1_TPHR_CAP_NEXTPTR_REG = PF1_TPHR_CAP_NEXTPTR;
localparam [2:0] PF1_TPHR_CAP_ST_MODE_SEL_REG = PF1_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] PF1_TPHR_CAP_ST_TABLE_LOC_REG = PF1_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE_REG = PF1_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] PF1_TPHR_CAP_VER_REG = PF1_TPHR_CAP_VER;
localparam [40:1] PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF2_AER_CAP_ECRC_CHECK_CAPABLE;
localparam [40:1] PF2_AER_CAP_ECRC_GEN_CAPABLE_REG = PF2_AER_CAP_ECRC_GEN_CAPABLE;
localparam [11:0] PF2_AER_CAP_NEXTPTR_REG = PF2_AER_CAP_NEXTPTR;
localparam [11:0] PF2_ARI_CAP_NEXTPTR_REG = PF2_ARI_CAP_NEXTPTR;
localparam [7:0] PF2_ARI_CAP_NEXT_FUNC_REG = PF2_ARI_CAP_NEXT_FUNC;
localparam [5:0] PF2_BAR0_APERTURE_SIZE_REG = PF2_BAR0_APERTURE_SIZE;
localparam [2:0] PF2_BAR0_CONTROL_REG = PF2_BAR0_CONTROL;
localparam [5:0] PF2_BAR1_APERTURE_SIZE_REG = PF2_BAR1_APERTURE_SIZE;
localparam [2:0] PF2_BAR1_CONTROL_REG = PF2_BAR1_CONTROL;
localparam [4:0] PF2_BAR2_APERTURE_SIZE_REG = PF2_BAR2_APERTURE_SIZE;
localparam [2:0] PF2_BAR2_CONTROL_REG = PF2_BAR2_CONTROL;
localparam [4:0] PF2_BAR3_APERTURE_SIZE_REG = PF2_BAR3_APERTURE_SIZE;
localparam [2:0] PF2_BAR3_CONTROL_REG = PF2_BAR3_CONTROL;
localparam [4:0] PF2_BAR4_APERTURE_SIZE_REG = PF2_BAR4_APERTURE_SIZE;
localparam [2:0] PF2_BAR4_CONTROL_REG = PF2_BAR4_CONTROL;
localparam [4:0] PF2_BAR5_APERTURE_SIZE_REG = PF2_BAR5_APERTURE_SIZE;
localparam [2:0] PF2_BAR5_CONTROL_REG = PF2_BAR5_CONTROL;
localparam [7:0] PF2_BIST_REGISTER_REG = PF2_BIST_REGISTER;
localparam [7:0] PF2_CAPABILITY_POINTER_REG = PF2_CAPABILITY_POINTER;
localparam [23:0] PF2_CLASS_CODE_REG = PF2_CLASS_CODE;
localparam [15:0] PF2_DEVICE_ID_REG = PF2_DEVICE_ID;
localparam [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF2_DEV_CAP_MAX_PAYLOAD_SIZE;
localparam [11:0] PF2_DPA_CAP_NEXTPTR_REG = PF2_DPA_CAP_NEXTPTR;
localparam [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL_REG = PF2_DPA_CAP_SUB_STATE_CONTROL;
localparam [40:1] PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF2_DPA_CAP_SUB_STATE_CONTROL_EN;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6;
localparam [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7;
localparam [3:0] PF2_DPA_CAP_VER_REG = PF2_DPA_CAP_VER;
localparam [11:0] PF2_DSN_CAP_NEXTPTR_REG = PF2_DSN_CAP_NEXTPTR;
localparam [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE_REG = PF2_EXPANSION_ROM_APERTURE_SIZE;
localparam [40:1] PF2_EXPANSION_ROM_ENABLE_REG = PF2_EXPANSION_ROM_ENABLE;
localparam [7:0] PF2_INTERRUPT_LINE_REG = PF2_INTERRUPT_LINE;
localparam [2:0] PF2_INTERRUPT_PIN_REG = PF2_INTERRUPT_PIN;
localparam [7:0] PF2_MSIX_CAP_NEXTPTR_REG = PF2_MSIX_CAP_NEXTPTR;
localparam [2:0] PF2_MSIX_CAP_PBA_BIR_REG = PF2_MSIX_CAP_PBA_BIR;
localparam [28:0] PF2_MSIX_CAP_PBA_OFFSET_REG = PF2_MSIX_CAP_PBA_OFFSET;
localparam [2:0] PF2_MSIX_CAP_TABLE_BIR_REG = PF2_MSIX_CAP_TABLE_BIR;
localparam [28:0] PF2_MSIX_CAP_TABLE_OFFSET_REG = PF2_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] PF2_MSIX_CAP_TABLE_SIZE_REG = PF2_MSIX_CAP_TABLE_SIZE;
localparam [2:0] PF2_MSI_CAP_MULTIMSGCAP_REG = PF2_MSI_CAP_MULTIMSGCAP;
localparam [7:0] PF2_MSI_CAP_NEXTPTR_REG = PF2_MSI_CAP_NEXTPTR;
localparam [40:1] PF2_MSI_CAP_PERVECMASKCAP_REG = PF2_MSI_CAP_PERVECMASKCAP;
localparam [31:0] PF2_PB_CAP_DATA_REG_D0_REG = PF2_PB_CAP_DATA_REG_D0;
localparam [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF2_PB_CAP_DATA_REG_D0_SUSTAINED;
localparam [31:0] PF2_PB_CAP_DATA_REG_D1_REG = PF2_PB_CAP_DATA_REG_D1;
localparam [31:0] PF2_PB_CAP_DATA_REG_D3HOT_REG = PF2_PB_CAP_DATA_REG_D3HOT;
localparam [11:0] PF2_PB_CAP_NEXTPTR_REG = PF2_PB_CAP_NEXTPTR;
localparam [40:1] PF2_PB_CAP_SYSTEM_ALLOCATED_REG = PF2_PB_CAP_SYSTEM_ALLOCATED;
localparam [3:0] PF2_PB_CAP_VER_REG = PF2_PB_CAP_VER;
localparam [7:0] PF2_PM_CAP_ID_REG = PF2_PM_CAP_ID;
localparam [7:0] PF2_PM_CAP_NEXTPTR_REG = PF2_PM_CAP_NEXTPTR;
localparam [2:0] PF2_PM_CAP_VER_ID_REG = PF2_PM_CAP_VER_ID;
localparam [40:1] PF2_RBAR_CAP_ENABLE_REG = PF2_RBAR_CAP_ENABLE;
localparam [11:0] PF2_RBAR_CAP_NEXTPTR_REG = PF2_RBAR_CAP_NEXTPTR;
localparam [19:0] PF2_RBAR_CAP_SIZE0_REG = PF2_RBAR_CAP_SIZE0;
localparam [19:0] PF2_RBAR_CAP_SIZE1_REG = PF2_RBAR_CAP_SIZE1;
localparam [19:0] PF2_RBAR_CAP_SIZE2_REG = PF2_RBAR_CAP_SIZE2;
localparam [3:0] PF2_RBAR_CAP_VER_REG = PF2_RBAR_CAP_VER;
localparam [2:0] PF2_RBAR_CONTROL_INDEX0_REG = PF2_RBAR_CONTROL_INDEX0;
localparam [2:0] PF2_RBAR_CONTROL_INDEX1_REG = PF2_RBAR_CONTROL_INDEX1;
localparam [2:0] PF2_RBAR_CONTROL_INDEX2_REG = PF2_RBAR_CONTROL_INDEX2;
localparam [4:0] PF2_RBAR_CONTROL_SIZE0_REG = PF2_RBAR_CONTROL_SIZE0;
localparam [4:0] PF2_RBAR_CONTROL_SIZE1_REG = PF2_RBAR_CONTROL_SIZE1;
localparam [4:0] PF2_RBAR_CONTROL_SIZE2_REG = PF2_RBAR_CONTROL_SIZE2;
localparam [2:0] PF2_RBAR_NUM_REG = PF2_RBAR_NUM;
localparam [7:0] PF2_REVISION_ID_REG = PF2_REVISION_ID;
localparam [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE_REG = PF2_SRIOV_BAR0_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR0_CONTROL_REG = PF2_SRIOV_BAR0_CONTROL;
localparam [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE_REG = PF2_SRIOV_BAR1_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR1_CONTROL_REG = PF2_SRIOV_BAR1_CONTROL;
localparam [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE_REG = PF2_SRIOV_BAR2_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR2_CONTROL_REG = PF2_SRIOV_BAR2_CONTROL;
localparam [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE_REG = PF2_SRIOV_BAR3_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR3_CONTROL_REG = PF2_SRIOV_BAR3_CONTROL;
localparam [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE_REG = PF2_SRIOV_BAR4_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR4_CONTROL_REG = PF2_SRIOV_BAR4_CONTROL;
localparam [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE_REG = PF2_SRIOV_BAR5_APERTURE_SIZE;
localparam [2:0] PF2_SRIOV_BAR5_CONTROL_REG = PF2_SRIOV_BAR5_CONTROL;
localparam [15:0] PF2_SRIOV_CAP_INITIAL_VF_REG = PF2_SRIOV_CAP_INITIAL_VF;
localparam [11:0] PF2_SRIOV_CAP_NEXTPTR_REG = PF2_SRIOV_CAP_NEXTPTR;
localparam [15:0] PF2_SRIOV_CAP_TOTAL_VF_REG = PF2_SRIOV_CAP_TOTAL_VF;
localparam [3:0] PF2_SRIOV_CAP_VER_REG = PF2_SRIOV_CAP_VER;
localparam [15:0] PF2_SRIOV_FIRST_VF_OFFSET_REG = PF2_SRIOV_FIRST_VF_OFFSET;
localparam [15:0] PF2_SRIOV_FUNC_DEP_LINK_REG = PF2_SRIOV_FUNC_DEP_LINK;
localparam [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF2_SRIOV_SUPPORTED_PAGE_SIZE;
localparam [15:0] PF2_SRIOV_VF_DEVICE_ID_REG = PF2_SRIOV_VF_DEVICE_ID;
localparam [15:0] PF2_SUBSYSTEM_ID_REG = PF2_SUBSYSTEM_ID;
localparam [40:1] PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF2_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] PF2_TPHR_CAP_ENABLE_REG = PF2_TPHR_CAP_ENABLE;
localparam [40:1] PF2_TPHR_CAP_INT_VEC_MODE_REG = PF2_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] PF2_TPHR_CAP_NEXTPTR_REG = PF2_TPHR_CAP_NEXTPTR;
localparam [2:0] PF2_TPHR_CAP_ST_MODE_SEL_REG = PF2_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] PF2_TPHR_CAP_ST_TABLE_LOC_REG = PF2_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE_REG = PF2_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] PF2_TPHR_CAP_VER_REG = PF2_TPHR_CAP_VER;
localparam [40:1] PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG = PF3_AER_CAP_ECRC_CHECK_CAPABLE;
localparam [40:1] PF3_AER_CAP_ECRC_GEN_CAPABLE_REG = PF3_AER_CAP_ECRC_GEN_CAPABLE;
localparam [11:0] PF3_AER_CAP_NEXTPTR_REG = PF3_AER_CAP_NEXTPTR;
localparam [11:0] PF3_ARI_CAP_NEXTPTR_REG = PF3_ARI_CAP_NEXTPTR;
localparam [7:0] PF3_ARI_CAP_NEXT_FUNC_REG = PF3_ARI_CAP_NEXT_FUNC;
localparam [5:0] PF3_BAR0_APERTURE_SIZE_REG = PF3_BAR0_APERTURE_SIZE;
localparam [2:0] PF3_BAR0_CONTROL_REG = PF3_BAR0_CONTROL;
localparam [5:0] PF3_BAR1_APERTURE_SIZE_REG = PF3_BAR1_APERTURE_SIZE;
localparam [2:0] PF3_BAR1_CONTROL_REG = PF3_BAR1_CONTROL;
localparam [4:0] PF3_BAR2_APERTURE_SIZE_REG = PF3_BAR2_APERTURE_SIZE;
localparam [2:0] PF3_BAR2_CONTROL_REG = PF3_BAR2_CONTROL;
localparam [4:0] PF3_BAR3_APERTURE_SIZE_REG = PF3_BAR3_APERTURE_SIZE;
localparam [2:0] PF3_BAR3_CONTROL_REG = PF3_BAR3_CONTROL;
localparam [4:0] PF3_BAR4_APERTURE_SIZE_REG = PF3_BAR4_APERTURE_SIZE;
localparam [2:0] PF3_BAR4_CONTROL_REG = PF3_BAR4_CONTROL;
localparam [4:0] PF3_BAR5_APERTURE_SIZE_REG = PF3_BAR5_APERTURE_SIZE;
localparam [2:0] PF3_BAR5_CONTROL_REG = PF3_BAR5_CONTROL;
localparam [7:0] PF3_BIST_REGISTER_REG = PF3_BIST_REGISTER;
localparam [7:0] PF3_CAPABILITY_POINTER_REG = PF3_CAPABILITY_POINTER;
localparam [23:0] PF3_CLASS_CODE_REG = PF3_CLASS_CODE;
localparam [15:0] PF3_DEVICE_ID_REG = PF3_DEVICE_ID;
localparam [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG = PF3_DEV_CAP_MAX_PAYLOAD_SIZE;
localparam [11:0] PF3_DPA_CAP_NEXTPTR_REG = PF3_DPA_CAP_NEXTPTR;
localparam [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL_REG = PF3_DPA_CAP_SUB_STATE_CONTROL;
localparam [40:1] PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG = PF3_DPA_CAP_SUB_STATE_CONTROL_EN;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6;
localparam [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG = PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7;
localparam [3:0] PF3_DPA_CAP_VER_REG = PF3_DPA_CAP_VER;
localparam [11:0] PF3_DSN_CAP_NEXTPTR_REG = PF3_DSN_CAP_NEXTPTR;
localparam [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE_REG = PF3_EXPANSION_ROM_APERTURE_SIZE;
localparam [40:1] PF3_EXPANSION_ROM_ENABLE_REG = PF3_EXPANSION_ROM_ENABLE;
localparam [7:0] PF3_INTERRUPT_LINE_REG = PF3_INTERRUPT_LINE;
localparam [2:0] PF3_INTERRUPT_PIN_REG = PF3_INTERRUPT_PIN;
localparam [7:0] PF3_MSIX_CAP_NEXTPTR_REG = PF3_MSIX_CAP_NEXTPTR;
localparam [2:0] PF3_MSIX_CAP_PBA_BIR_REG = PF3_MSIX_CAP_PBA_BIR;
localparam [28:0] PF3_MSIX_CAP_PBA_OFFSET_REG = PF3_MSIX_CAP_PBA_OFFSET;
localparam [2:0] PF3_MSIX_CAP_TABLE_BIR_REG = PF3_MSIX_CAP_TABLE_BIR;
localparam [28:0] PF3_MSIX_CAP_TABLE_OFFSET_REG = PF3_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] PF3_MSIX_CAP_TABLE_SIZE_REG = PF3_MSIX_CAP_TABLE_SIZE;
localparam [2:0] PF3_MSI_CAP_MULTIMSGCAP_REG = PF3_MSI_CAP_MULTIMSGCAP;
localparam [7:0] PF3_MSI_CAP_NEXTPTR_REG = PF3_MSI_CAP_NEXTPTR;
localparam [40:1] PF3_MSI_CAP_PERVECMASKCAP_REG = PF3_MSI_CAP_PERVECMASKCAP;
localparam [31:0] PF3_PB_CAP_DATA_REG_D0_REG = PF3_PB_CAP_DATA_REG_D0;
localparam [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED_REG = PF3_PB_CAP_DATA_REG_D0_SUSTAINED;
localparam [31:0] PF3_PB_CAP_DATA_REG_D1_REG = PF3_PB_CAP_DATA_REG_D1;
localparam [31:0] PF3_PB_CAP_DATA_REG_D3HOT_REG = PF3_PB_CAP_DATA_REG_D3HOT;
localparam [11:0] PF3_PB_CAP_NEXTPTR_REG = PF3_PB_CAP_NEXTPTR;
localparam [40:1] PF3_PB_CAP_SYSTEM_ALLOCATED_REG = PF3_PB_CAP_SYSTEM_ALLOCATED;
localparam [3:0] PF3_PB_CAP_VER_REG = PF3_PB_CAP_VER;
localparam [7:0] PF3_PM_CAP_ID_REG = PF3_PM_CAP_ID;
localparam [7:0] PF3_PM_CAP_NEXTPTR_REG = PF3_PM_CAP_NEXTPTR;
localparam [2:0] PF3_PM_CAP_VER_ID_REG = PF3_PM_CAP_VER_ID;
localparam [40:1] PF3_RBAR_CAP_ENABLE_REG = PF3_RBAR_CAP_ENABLE;
localparam [11:0] PF3_RBAR_CAP_NEXTPTR_REG = PF3_RBAR_CAP_NEXTPTR;
localparam [19:0] PF3_RBAR_CAP_SIZE0_REG = PF3_RBAR_CAP_SIZE0;
localparam [19:0] PF3_RBAR_CAP_SIZE1_REG = PF3_RBAR_CAP_SIZE1;
localparam [19:0] PF3_RBAR_CAP_SIZE2_REG = PF3_RBAR_CAP_SIZE2;
localparam [3:0] PF3_RBAR_CAP_VER_REG = PF3_RBAR_CAP_VER;
localparam [2:0] PF3_RBAR_CONTROL_INDEX0_REG = PF3_RBAR_CONTROL_INDEX0;
localparam [2:0] PF3_RBAR_CONTROL_INDEX1_REG = PF3_RBAR_CONTROL_INDEX1;
localparam [2:0] PF3_RBAR_CONTROL_INDEX2_REG = PF3_RBAR_CONTROL_INDEX2;
localparam [4:0] PF3_RBAR_CONTROL_SIZE0_REG = PF3_RBAR_CONTROL_SIZE0;
localparam [4:0] PF3_RBAR_CONTROL_SIZE1_REG = PF3_RBAR_CONTROL_SIZE1;
localparam [4:0] PF3_RBAR_CONTROL_SIZE2_REG = PF3_RBAR_CONTROL_SIZE2;
localparam [2:0] PF3_RBAR_NUM_REG = PF3_RBAR_NUM;
localparam [7:0] PF3_REVISION_ID_REG = PF3_REVISION_ID;
localparam [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE_REG = PF3_SRIOV_BAR0_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR0_CONTROL_REG = PF3_SRIOV_BAR0_CONTROL;
localparam [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE_REG = PF3_SRIOV_BAR1_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR1_CONTROL_REG = PF3_SRIOV_BAR1_CONTROL;
localparam [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE_REG = PF3_SRIOV_BAR2_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR2_CONTROL_REG = PF3_SRIOV_BAR2_CONTROL;
localparam [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE_REG = PF3_SRIOV_BAR3_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR3_CONTROL_REG = PF3_SRIOV_BAR3_CONTROL;
localparam [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE_REG = PF3_SRIOV_BAR4_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR4_CONTROL_REG = PF3_SRIOV_BAR4_CONTROL;
localparam [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE_REG = PF3_SRIOV_BAR5_APERTURE_SIZE;
localparam [2:0] PF3_SRIOV_BAR5_CONTROL_REG = PF3_SRIOV_BAR5_CONTROL;
localparam [15:0] PF3_SRIOV_CAP_INITIAL_VF_REG = PF3_SRIOV_CAP_INITIAL_VF;
localparam [11:0] PF3_SRIOV_CAP_NEXTPTR_REG = PF3_SRIOV_CAP_NEXTPTR;
localparam [15:0] PF3_SRIOV_CAP_TOTAL_VF_REG = PF3_SRIOV_CAP_TOTAL_VF;
localparam [3:0] PF3_SRIOV_CAP_VER_REG = PF3_SRIOV_CAP_VER;
localparam [15:0] PF3_SRIOV_FIRST_VF_OFFSET_REG = PF3_SRIOV_FIRST_VF_OFFSET;
localparam [15:0] PF3_SRIOV_FUNC_DEP_LINK_REG = PF3_SRIOV_FUNC_DEP_LINK;
localparam [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG = PF3_SRIOV_SUPPORTED_PAGE_SIZE;
localparam [15:0] PF3_SRIOV_VF_DEVICE_ID_REG = PF3_SRIOV_VF_DEVICE_ID;
localparam [15:0] PF3_SUBSYSTEM_ID_REG = PF3_SUBSYSTEM_ID;
localparam [40:1] PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG = PF3_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] PF3_TPHR_CAP_ENABLE_REG = PF3_TPHR_CAP_ENABLE;
localparam [40:1] PF3_TPHR_CAP_INT_VEC_MODE_REG = PF3_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] PF3_TPHR_CAP_NEXTPTR_REG = PF3_TPHR_CAP_NEXTPTR;
localparam [2:0] PF3_TPHR_CAP_ST_MODE_SEL_REG = PF3_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] PF3_TPHR_CAP_ST_TABLE_LOC_REG = PF3_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE_REG = PF3_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] PF3_TPHR_CAP_VER_REG = PF3_TPHR_CAP_VER;
localparam [40:1] PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG = PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3;
localparam [40:1] PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG = PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2;
localparam [40:1] PL_DISABLE_EI_INFER_IN_L0_REG = PL_DISABLE_EI_INFER_IN_L0;
localparam [40:1] PL_DISABLE_GEN3_DC_BALANCE_REG = PL_DISABLE_GEN3_DC_BALANCE;
localparam [40:1] PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG = PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP;
localparam [40:1] PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG = PL_DISABLE_RETRAIN_ON_FRAMING_ERROR;
localparam [40:1] PL_DISABLE_SCRAMBLING_REG = PL_DISABLE_SCRAMBLING;
localparam [40:1] PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG = PL_DISABLE_SYNC_HEADER_FRAMING_ERROR;
localparam [40:1] PL_DISABLE_UPCONFIG_CAPABLE_REG = PL_DISABLE_UPCONFIG_CAPABLE;
localparam [40:1] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG = PL_EQ_ADAPT_DISABLE_COEFF_CHECK;
localparam [40:1] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG = PL_EQ_ADAPT_DISABLE_PRESET_CHECK;
localparam [4:0] PL_EQ_ADAPT_ITER_COUNT_REG = PL_EQ_ADAPT_ITER_COUNT;
localparam [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG = PL_EQ_ADAPT_REJECT_RETRY_COUNT;
localparam [40:1] PL_EQ_BYPASS_PHASE23_REG = PL_EQ_BYPASS_PHASE23;
localparam [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT_REG = PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT;
localparam [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET_REG = PL_EQ_DEFAULT_GEN3_TX_PRESET;
localparam [40:1] PL_EQ_PHASE01_RX_ADAPT_REG = PL_EQ_PHASE01_RX_ADAPT;
localparam [40:1] PL_EQ_SHORT_ADAPT_PHASE_REG = PL_EQ_SHORT_ADAPT_PHASE;
localparam [15:0] PL_LANE0_EQ_CONTROL_REG = PL_LANE0_EQ_CONTROL;
localparam [15:0] PL_LANE1_EQ_CONTROL_REG = PL_LANE1_EQ_CONTROL;
localparam [15:0] PL_LANE2_EQ_CONTROL_REG = PL_LANE2_EQ_CONTROL;
localparam [15:0] PL_LANE3_EQ_CONTROL_REG = PL_LANE3_EQ_CONTROL;
localparam [15:0] PL_LANE4_EQ_CONTROL_REG = PL_LANE4_EQ_CONTROL;
localparam [15:0] PL_LANE5_EQ_CONTROL_REG = PL_LANE5_EQ_CONTROL;
localparam [15:0] PL_LANE6_EQ_CONTROL_REG = PL_LANE6_EQ_CONTROL;
localparam [15:0] PL_LANE7_EQ_CONTROL_REG = PL_LANE7_EQ_CONTROL;
localparam [2:0] PL_LINK_CAP_MAX_LINK_SPEED_REG = PL_LINK_CAP_MAX_LINK_SPEED;
localparam [3:0] PL_LINK_CAP_MAX_LINK_WIDTH_REG = PL_LINK_CAP_MAX_LINK_WIDTH;
localparam [7:0] PL_N_FTS_COMCLK_GEN1_REG = PL_N_FTS_COMCLK_GEN1;
localparam [7:0] PL_N_FTS_COMCLK_GEN2_REG = PL_N_FTS_COMCLK_GEN2;
localparam [7:0] PL_N_FTS_COMCLK_GEN3_REG = PL_N_FTS_COMCLK_GEN3;
localparam [7:0] PL_N_FTS_GEN1_REG = PL_N_FTS_GEN1;
localparam [7:0] PL_N_FTS_GEN2_REG = PL_N_FTS_GEN2;
localparam [7:0] PL_N_FTS_GEN3_REG = PL_N_FTS_GEN3;
localparam [40:1] PL_REPORT_ALL_PHY_ERRORS_REG = PL_REPORT_ALL_PHY_ERRORS;
localparam [40:1] PL_SIM_FAST_LINK_TRAINING_REG = PL_SIM_FAST_LINK_TRAINING;
localparam [40:1] PL_UPSTREAM_FACING_REG = PL_UPSTREAM_FACING;
localparam [15:0] PM_ASPML0S_TIMEOUT_REG = PM_ASPML0S_TIMEOUT;
localparam [19:0] PM_ASPML1_ENTRY_DELAY_REG = PM_ASPML1_ENTRY_DELAY;
localparam [40:1] PM_ENABLE_L23_ENTRY_REG = PM_ENABLE_L23_ENTRY;
localparam [40:1] PM_ENABLE_SLOT_POWER_CAPTURE_REG = PM_ENABLE_SLOT_POWER_CAPTURE;
localparam [31:0] PM_L1_REENTRY_DELAY_REG = PM_L1_REENTRY_DELAY;
localparam [19:0] PM_PME_SERVICE_TIMEOUT_DELAY_REG = PM_PME_SERVICE_TIMEOUT_DELAY;
localparam [15:0] PM_PME_TURNOFF_ACK_DELAY_REG = PM_PME_TURNOFF_ACK_DELAY;
localparam [31:0] SIM_JTAG_IDCODE_REG = SIM_JTAG_IDCODE;
localparam [24:1] SIM_VERSION_REG = SIM_VERSION;
localparam [0:0] SPARE_BIT0_REG = SPARE_BIT0;
localparam [0:0] SPARE_BIT1_REG = SPARE_BIT1;
localparam [0:0] SPARE_BIT2_REG = SPARE_BIT2;
localparam [0:0] SPARE_BIT3_REG = SPARE_BIT3;
localparam [0:0] SPARE_BIT4_REG = SPARE_BIT4;
localparam [0:0] SPARE_BIT5_REG = SPARE_BIT5;
localparam [0:0] SPARE_BIT6_REG = SPARE_BIT6;
localparam [0:0] SPARE_BIT7_REG = SPARE_BIT7;
localparam [0:0] SPARE_BIT8_REG = SPARE_BIT8;
localparam [7:0] SPARE_BYTE0_REG = SPARE_BYTE0;
localparam [7:0] SPARE_BYTE1_REG = SPARE_BYTE1;
localparam [7:0] SPARE_BYTE2_REG = SPARE_BYTE2;
localparam [7:0] SPARE_BYTE3_REG = SPARE_BYTE3;
localparam [31:0] SPARE_WORD0_REG = SPARE_WORD0;
localparam [31:0] SPARE_WORD1_REG = SPARE_WORD1;
localparam [31:0] SPARE_WORD2_REG = SPARE_WORD2;
localparam [31:0] SPARE_WORD3_REG = SPARE_WORD3;
localparam [40:1] SRIOV_CAP_ENABLE_REG = SRIOV_CAP_ENABLE;
localparam [23:0] TL_COMPL_TIMEOUT_REG0_REG = TL_COMPL_TIMEOUT_REG0;
localparam [27:0] TL_COMPL_TIMEOUT_REG1_REG = TL_COMPL_TIMEOUT_REG1;
localparam [11:0] TL_CREDITS_CD_REG = TL_CREDITS_CD;
localparam [7:0] TL_CREDITS_CH_REG = TL_CREDITS_CH;
localparam [11:0] TL_CREDITS_NPD_REG = TL_CREDITS_NPD;
localparam [7:0] TL_CREDITS_NPH_REG = TL_CREDITS_NPH;
localparam [11:0] TL_CREDITS_PD_REG = TL_CREDITS_PD;
localparam [7:0] TL_CREDITS_PH_REG = TL_CREDITS_PH;
localparam [40:1] TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG = TL_ENABLE_MESSAGE_RID_CHECK_ENABLE;
localparam [40:1] TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG = TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE;
localparam [40:1] TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG = TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE;
localparam [40:1] TL_LEGACY_MODE_ENABLE_REG = TL_LEGACY_MODE_ENABLE;
localparam [1:0] TL_PF_ENABLE_REG_REG = TL_PF_ENABLE_REG;
localparam [40:1] TL_TAG_MGMT_ENABLE_REG = TL_TAG_MGMT_ENABLE;
localparam [40:1] TL_TX_MUX_STRICT_PRIORITY_REG = TL_TX_MUX_STRICT_PRIORITY;
localparam [40:1] TWO_LAYER_MODE_DLCMSM_ENABLE_REG = TWO_LAYER_MODE_DLCMSM_ENABLE;
localparam [40:1] TWO_LAYER_MODE_ENABLE_REG = TWO_LAYER_MODE_ENABLE;
localparam [40:1] TWO_LAYER_MODE_WIDTH_256_REG = TWO_LAYER_MODE_WIDTH_256;
localparam [11:0] VF0_ARI_CAP_NEXTPTR_REG = VF0_ARI_CAP_NEXTPTR;
localparam [7:0] VF0_CAPABILITY_POINTER_REG = VF0_CAPABILITY_POINTER;
localparam [2:0] VF0_MSIX_CAP_PBA_BIR_REG = VF0_MSIX_CAP_PBA_BIR;
localparam [28:0] VF0_MSIX_CAP_PBA_OFFSET_REG = VF0_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF0_MSIX_CAP_TABLE_BIR_REG = VF0_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF0_MSIX_CAP_TABLE_OFFSET_REG = VF0_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF0_MSIX_CAP_TABLE_SIZE_REG = VF0_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF0_MSI_CAP_MULTIMSGCAP_REG = VF0_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF0_PM_CAP_ID_REG = VF0_PM_CAP_ID;
localparam [7:0] VF0_PM_CAP_NEXTPTR_REG = VF0_PM_CAP_NEXTPTR;
localparam [2:0] VF0_PM_CAP_VER_ID_REG = VF0_PM_CAP_VER_ID;
localparam [40:1] VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF0_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF0_TPHR_CAP_ENABLE_REG = VF0_TPHR_CAP_ENABLE;
localparam [40:1] VF0_TPHR_CAP_INT_VEC_MODE_REG = VF0_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF0_TPHR_CAP_NEXTPTR_REG = VF0_TPHR_CAP_NEXTPTR;
localparam [2:0] VF0_TPHR_CAP_ST_MODE_SEL_REG = VF0_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF0_TPHR_CAP_ST_TABLE_LOC_REG = VF0_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE_REG = VF0_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF0_TPHR_CAP_VER_REG = VF0_TPHR_CAP_VER;
localparam [11:0] VF1_ARI_CAP_NEXTPTR_REG = VF1_ARI_CAP_NEXTPTR;
localparam [2:0] VF1_MSIX_CAP_PBA_BIR_REG = VF1_MSIX_CAP_PBA_BIR;
localparam [28:0] VF1_MSIX_CAP_PBA_OFFSET_REG = VF1_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF1_MSIX_CAP_TABLE_BIR_REG = VF1_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF1_MSIX_CAP_TABLE_OFFSET_REG = VF1_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF1_MSIX_CAP_TABLE_SIZE_REG = VF1_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF1_MSI_CAP_MULTIMSGCAP_REG = VF1_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF1_PM_CAP_ID_REG = VF1_PM_CAP_ID;
localparam [7:0] VF1_PM_CAP_NEXTPTR_REG = VF1_PM_CAP_NEXTPTR;
localparam [2:0] VF1_PM_CAP_VER_ID_REG = VF1_PM_CAP_VER_ID;
localparam [40:1] VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF1_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF1_TPHR_CAP_ENABLE_REG = VF1_TPHR_CAP_ENABLE;
localparam [40:1] VF1_TPHR_CAP_INT_VEC_MODE_REG = VF1_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF1_TPHR_CAP_NEXTPTR_REG = VF1_TPHR_CAP_NEXTPTR;
localparam [2:0] VF1_TPHR_CAP_ST_MODE_SEL_REG = VF1_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF1_TPHR_CAP_ST_TABLE_LOC_REG = VF1_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE_REG = VF1_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF1_TPHR_CAP_VER_REG = VF1_TPHR_CAP_VER;
localparam [11:0] VF2_ARI_CAP_NEXTPTR_REG = VF2_ARI_CAP_NEXTPTR;
localparam [2:0] VF2_MSIX_CAP_PBA_BIR_REG = VF2_MSIX_CAP_PBA_BIR;
localparam [28:0] VF2_MSIX_CAP_PBA_OFFSET_REG = VF2_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF2_MSIX_CAP_TABLE_BIR_REG = VF2_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF2_MSIX_CAP_TABLE_OFFSET_REG = VF2_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF2_MSIX_CAP_TABLE_SIZE_REG = VF2_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF2_MSI_CAP_MULTIMSGCAP_REG = VF2_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF2_PM_CAP_ID_REG = VF2_PM_CAP_ID;
localparam [7:0] VF2_PM_CAP_NEXTPTR_REG = VF2_PM_CAP_NEXTPTR;
localparam [2:0] VF2_PM_CAP_VER_ID_REG = VF2_PM_CAP_VER_ID;
localparam [40:1] VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF2_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF2_TPHR_CAP_ENABLE_REG = VF2_TPHR_CAP_ENABLE;
localparam [40:1] VF2_TPHR_CAP_INT_VEC_MODE_REG = VF2_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF2_TPHR_CAP_NEXTPTR_REG = VF2_TPHR_CAP_NEXTPTR;
localparam [2:0] VF2_TPHR_CAP_ST_MODE_SEL_REG = VF2_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF2_TPHR_CAP_ST_TABLE_LOC_REG = VF2_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE_REG = VF2_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF2_TPHR_CAP_VER_REG = VF2_TPHR_CAP_VER;
localparam [11:0] VF3_ARI_CAP_NEXTPTR_REG = VF3_ARI_CAP_NEXTPTR;
localparam [2:0] VF3_MSIX_CAP_PBA_BIR_REG = VF3_MSIX_CAP_PBA_BIR;
localparam [28:0] VF3_MSIX_CAP_PBA_OFFSET_REG = VF3_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF3_MSIX_CAP_TABLE_BIR_REG = VF3_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF3_MSIX_CAP_TABLE_OFFSET_REG = VF3_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF3_MSIX_CAP_TABLE_SIZE_REG = VF3_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF3_MSI_CAP_MULTIMSGCAP_REG = VF3_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF3_PM_CAP_ID_REG = VF3_PM_CAP_ID;
localparam [7:0] VF3_PM_CAP_NEXTPTR_REG = VF3_PM_CAP_NEXTPTR;
localparam [2:0] VF3_PM_CAP_VER_ID_REG = VF3_PM_CAP_VER_ID;
localparam [40:1] VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF3_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF3_TPHR_CAP_ENABLE_REG = VF3_TPHR_CAP_ENABLE;
localparam [40:1] VF3_TPHR_CAP_INT_VEC_MODE_REG = VF3_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF3_TPHR_CAP_NEXTPTR_REG = VF3_TPHR_CAP_NEXTPTR;
localparam [2:0] VF3_TPHR_CAP_ST_MODE_SEL_REG = VF3_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF3_TPHR_CAP_ST_TABLE_LOC_REG = VF3_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE_REG = VF3_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF3_TPHR_CAP_VER_REG = VF3_TPHR_CAP_VER;
localparam [11:0] VF4_ARI_CAP_NEXTPTR_REG = VF4_ARI_CAP_NEXTPTR;
localparam [2:0] VF4_MSIX_CAP_PBA_BIR_REG = VF4_MSIX_CAP_PBA_BIR;
localparam [28:0] VF4_MSIX_CAP_PBA_OFFSET_REG = VF4_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF4_MSIX_CAP_TABLE_BIR_REG = VF4_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF4_MSIX_CAP_TABLE_OFFSET_REG = VF4_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF4_MSIX_CAP_TABLE_SIZE_REG = VF4_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF4_MSI_CAP_MULTIMSGCAP_REG = VF4_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF4_PM_CAP_ID_REG = VF4_PM_CAP_ID;
localparam [7:0] VF4_PM_CAP_NEXTPTR_REG = VF4_PM_CAP_NEXTPTR;
localparam [2:0] VF4_PM_CAP_VER_ID_REG = VF4_PM_CAP_VER_ID;
localparam [40:1] VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF4_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF4_TPHR_CAP_ENABLE_REG = VF4_TPHR_CAP_ENABLE;
localparam [40:1] VF4_TPHR_CAP_INT_VEC_MODE_REG = VF4_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF4_TPHR_CAP_NEXTPTR_REG = VF4_TPHR_CAP_NEXTPTR;
localparam [2:0] VF4_TPHR_CAP_ST_MODE_SEL_REG = VF4_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF4_TPHR_CAP_ST_TABLE_LOC_REG = VF4_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE_REG = VF4_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF4_TPHR_CAP_VER_REG = VF4_TPHR_CAP_VER;
localparam [11:0] VF5_ARI_CAP_NEXTPTR_REG = VF5_ARI_CAP_NEXTPTR;
localparam [2:0] VF5_MSIX_CAP_PBA_BIR_REG = VF5_MSIX_CAP_PBA_BIR;
localparam [28:0] VF5_MSIX_CAP_PBA_OFFSET_REG = VF5_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF5_MSIX_CAP_TABLE_BIR_REG = VF5_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF5_MSIX_CAP_TABLE_OFFSET_REG = VF5_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF5_MSIX_CAP_TABLE_SIZE_REG = VF5_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF5_MSI_CAP_MULTIMSGCAP_REG = VF5_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF5_PM_CAP_ID_REG = VF5_PM_CAP_ID;
localparam [7:0] VF5_PM_CAP_NEXTPTR_REG = VF5_PM_CAP_NEXTPTR;
localparam [2:0] VF5_PM_CAP_VER_ID_REG = VF5_PM_CAP_VER_ID;
localparam [40:1] VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF5_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF5_TPHR_CAP_ENABLE_REG = VF5_TPHR_CAP_ENABLE;
localparam [40:1] VF5_TPHR_CAP_INT_VEC_MODE_REG = VF5_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF5_TPHR_CAP_NEXTPTR_REG = VF5_TPHR_CAP_NEXTPTR;
localparam [2:0] VF5_TPHR_CAP_ST_MODE_SEL_REG = VF5_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF5_TPHR_CAP_ST_TABLE_LOC_REG = VF5_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE_REG = VF5_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF5_TPHR_CAP_VER_REG = VF5_TPHR_CAP_VER;
localparam [11:0] VF6_ARI_CAP_NEXTPTR_REG = VF6_ARI_CAP_NEXTPTR;
localparam [2:0] VF6_MSIX_CAP_PBA_BIR_REG = VF6_MSIX_CAP_PBA_BIR;
localparam [28:0] VF6_MSIX_CAP_PBA_OFFSET_REG = VF6_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF6_MSIX_CAP_TABLE_BIR_REG = VF6_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF6_MSIX_CAP_TABLE_OFFSET_REG = VF6_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF6_MSIX_CAP_TABLE_SIZE_REG = VF6_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF6_MSI_CAP_MULTIMSGCAP_REG = VF6_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF6_PM_CAP_ID_REG = VF6_PM_CAP_ID;
localparam [7:0] VF6_PM_CAP_NEXTPTR_REG = VF6_PM_CAP_NEXTPTR;
localparam [2:0] VF6_PM_CAP_VER_ID_REG = VF6_PM_CAP_VER_ID;
localparam [40:1] VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF6_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF6_TPHR_CAP_ENABLE_REG = VF6_TPHR_CAP_ENABLE;
localparam [40:1] VF6_TPHR_CAP_INT_VEC_MODE_REG = VF6_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF6_TPHR_CAP_NEXTPTR_REG = VF6_TPHR_CAP_NEXTPTR;
localparam [2:0] VF6_TPHR_CAP_ST_MODE_SEL_REG = VF6_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF6_TPHR_CAP_ST_TABLE_LOC_REG = VF6_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE_REG = VF6_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF6_TPHR_CAP_VER_REG = VF6_TPHR_CAP_VER;
localparam [11:0] VF7_ARI_CAP_NEXTPTR_REG = VF7_ARI_CAP_NEXTPTR;
localparam [2:0] VF7_MSIX_CAP_PBA_BIR_REG = VF7_MSIX_CAP_PBA_BIR;
localparam [28:0] VF7_MSIX_CAP_PBA_OFFSET_REG = VF7_MSIX_CAP_PBA_OFFSET;
localparam [2:0] VF7_MSIX_CAP_TABLE_BIR_REG = VF7_MSIX_CAP_TABLE_BIR;
localparam [28:0] VF7_MSIX_CAP_TABLE_OFFSET_REG = VF7_MSIX_CAP_TABLE_OFFSET;
localparam [10:0] VF7_MSIX_CAP_TABLE_SIZE_REG = VF7_MSIX_CAP_TABLE_SIZE;
localparam [2:0] VF7_MSI_CAP_MULTIMSGCAP_REG = VF7_MSI_CAP_MULTIMSGCAP;
localparam [7:0] VF7_PM_CAP_ID_REG = VF7_PM_CAP_ID;
localparam [7:0] VF7_PM_CAP_NEXTPTR_REG = VF7_PM_CAP_NEXTPTR;
localparam [2:0] VF7_PM_CAP_VER_ID_REG = VF7_PM_CAP_VER_ID;
localparam [40:1] VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG = VF7_TPHR_CAP_DEV_SPECIFIC_MODE;
localparam [40:1] VF7_TPHR_CAP_ENABLE_REG = VF7_TPHR_CAP_ENABLE;
localparam [40:1] VF7_TPHR_CAP_INT_VEC_MODE_REG = VF7_TPHR_CAP_INT_VEC_MODE;
localparam [11:0] VF7_TPHR_CAP_NEXTPTR_REG = VF7_TPHR_CAP_NEXTPTR;
localparam [2:0] VF7_TPHR_CAP_ST_MODE_SEL_REG = VF7_TPHR_CAP_ST_MODE_SEL;
localparam [1:0] VF7_TPHR_CAP_ST_TABLE_LOC_REG = VF7_TPHR_CAP_ST_TABLE_LOC;
localparam [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE_REG = VF7_TPHR_CAP_ST_TABLE_SIZE;
localparam [3:0] VF7_TPHR_CAP_VER_REG = VF7_TPHR_CAP_VER;
`endif
localparam [40:1] TEST_MODE_PIN_CHAR_REG = "FALSE";
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "PCIE_3_1_dr.v"
`endif
wire CFGERRCOROUT_out;
wire CFGERRFATALOUT_out;
wire CFGERRNONFATALOUT_out;
wire CFGEXTREADRECEIVED_out;
wire CFGEXTWRITERECEIVED_out;
wire CFGHOTRESETOUT_out;
wire CFGINTERRUPTMSIFAIL_out;
wire CFGINTERRUPTMSIMASKUPDATE_out;
wire CFGINTERRUPTMSISENT_out;
wire CFGINTERRUPTMSIXFAIL_out;
wire CFGINTERRUPTMSIXSENT_out;
wire CFGINTERRUPTSENT_out;
wire CFGLOCALERROR_out;
wire CFGLTRENABLE_out;
wire CFGMGMTREADWRITEDONE_out;
wire CFGMSGRECEIVED_out;
wire CFGMSGTRANSMITDONE_out;
wire CFGPERFUNCTIONUPDATEDONE_out;
wire CFGPHYLINKDOWN_out;
wire CFGPLSTATUSCHANGE_out;
wire CFGPOWERSTATECHANGEINTERRUPT_out;
wire CFGTPHSTTREADENABLE_out;
wire CFGTPHSTTWRITEENABLE_out;
wire CONFMCAPDESIGNSWITCH_out;
wire CONFMCAPEOS_out;
wire CONFMCAPINUSEBYPCIE_out;
wire CONFREQREADY_out;
wire CONFRESPVALID_out;
wire DBGMCAPCSB_out;
wire DBGMCAPEOS_out;
wire DBGMCAPERROR_out;
wire DBGMCAPMODE_out;
wire DBGMCAPRDATAVALID_out;
wire DBGMCAPRDWRB_out;
wire DBGMCAPRESET_out;
wire DBGPLDATABLOCKRECEIVEDAFTEREDS_out;
wire DBGPLGEN3FRAMINGERRORDETECTED_out;
wire DBGPLGEN3SYNCHEADERERRORDETECTED_out;
wire DRPRDY_out;
wire LL2LMMASTERTLPSENT0_out;
wire LL2LMMASTERTLPSENT1_out;
wire MAXISCQTLAST_out;
wire MAXISCQTVALID_out;
wire MAXISRCTLAST_out;
wire MAXISRCTVALID_out;
wire PCIEPERST0B_out;
wire PCIEPERST1B_out;
wire PCIERQSEQNUMVLD_out;
wire PCIERQTAGVLD_out;
wire PIPERX0POLARITY_out;
wire PIPERX1POLARITY_out;
wire PIPERX2POLARITY_out;
wire PIPERX3POLARITY_out;
wire PIPERX4POLARITY_out;
wire PIPERX5POLARITY_out;
wire PIPERX6POLARITY_out;
wire PIPERX7POLARITY_out;
wire PIPETX0COMPLIANCE_out;
wire PIPETX0DATAVALID_out;
wire PIPETX0DEEMPH_out;
wire PIPETX0ELECIDLE_out;
wire PIPETX0RCVRDET_out;
wire PIPETX0RESET_out;
wire PIPETX0STARTBLOCK_out;
wire PIPETX0SWING_out;
wire PIPETX1COMPLIANCE_out;
wire PIPETX1DATAVALID_out;
wire PIPETX1DEEMPH_out;
wire PIPETX1ELECIDLE_out;
wire PIPETX1RCVRDET_out;
wire PIPETX1RESET_out;
wire PIPETX1STARTBLOCK_out;
wire PIPETX1SWING_out;
wire PIPETX2COMPLIANCE_out;
wire PIPETX2DATAVALID_out;
wire PIPETX2DEEMPH_out;
wire PIPETX2ELECIDLE_out;
wire PIPETX2RCVRDET_out;
wire PIPETX2RESET_out;
wire PIPETX2STARTBLOCK_out;
wire PIPETX2SWING_out;
wire PIPETX3COMPLIANCE_out;
wire PIPETX3DATAVALID_out;
wire PIPETX3DEEMPH_out;
wire PIPETX3ELECIDLE_out;
wire PIPETX3RCVRDET_out;
wire PIPETX3RESET_out;
wire PIPETX3STARTBLOCK_out;
wire PIPETX3SWING_out;
wire PIPETX4COMPLIANCE_out;
wire PIPETX4DATAVALID_out;
wire PIPETX4DEEMPH_out;
wire PIPETX4ELECIDLE_out;
wire PIPETX4RCVRDET_out;
wire PIPETX4RESET_out;
wire PIPETX4STARTBLOCK_out;
wire PIPETX4SWING_out;
wire PIPETX5COMPLIANCE_out;
wire PIPETX5DATAVALID_out;
wire PIPETX5DEEMPH_out;
wire PIPETX5ELECIDLE_out;
wire PIPETX5RCVRDET_out;
wire PIPETX5RESET_out;
wire PIPETX5STARTBLOCK_out;
wire PIPETX5SWING_out;
wire PIPETX6COMPLIANCE_out;
wire PIPETX6DATAVALID_out;
wire PIPETX6DEEMPH_out;
wire PIPETX6ELECIDLE_out;
wire PIPETX6RCVRDET_out;
wire PIPETX6RESET_out;
wire PIPETX6STARTBLOCK_out;
wire PIPETX6SWING_out;
wire PIPETX7COMPLIANCE_out;
wire PIPETX7DATAVALID_out;
wire PIPETX7DEEMPH_out;
wire PIPETX7ELECIDLE_out;
wire PIPETX7RCVRDET_out;
wire PIPETX7RESET_out;
wire PIPETX7STARTBLOCK_out;
wire PIPETX7SWING_out;
wire PLEQINPROGRESS_out;
wire PMVOUT_out;
wire [11:0] CFGFCCPLD_out;
wire [11:0] CFGFCNPD_out;
wire [11:0] CFGFCPD_out;
wire [11:0] CFGFUNCTIONPOWERSTATE_out;
wire [11:0] CFGINTERRUPTMSIMMENABLE_out;
wire [11:0] CFGTPHSTMODE_out;
wire [143:0] MIREPLAYRAMWRITEDATA_out;
wire [143:0] MIREQUESTRAMWRITEDATA_out;
wire [15:0] CFGFUNCTIONSTATUS_out;
wire [15:0] CFGPERFUNCSTATUSDATA_out;
wire [15:0] CFGVFSTATUS_out;
wire [15:0] DBGDATAOUT_out;
wire [15:0] DRPDO_out;
wire [17:0] LL2LMMAXISRXTUSER_out;
wire [1:0] CFGLINKPOWERSTATE_out;
wire [1:0] CFGOBFFENABLE_out;
wire [1:0] CFGPHYLINKSTATUS_out;
wire [1:0] MIREPLAYRAMREADENABLE_out;
wire [1:0] MIREPLAYRAMWRITEENABLE_out;
wire [1:0] PCIERQTAGAV_out;
wire [1:0] PCIETFCNPDAV_out;
wire [1:0] PCIETFCNPHAV_out;
wire [1:0] PIPERX0EQCONTROL_out;
wire [1:0] PIPERX1EQCONTROL_out;
wire [1:0] PIPERX2EQCONTROL_out;
wire [1:0] PIPERX3EQCONTROL_out;
wire [1:0] PIPERX4EQCONTROL_out;
wire [1:0] PIPERX5EQCONTROL_out;
wire [1:0] PIPERX6EQCONTROL_out;
wire [1:0] PIPERX7EQCONTROL_out;
wire [1:0] PIPETX0CHARISK_out;
wire [1:0] PIPETX0EQCONTROL_out;
wire [1:0] PIPETX0POWERDOWN_out;
wire [1:0] PIPETX0RATE_out;
wire [1:0] PIPETX0SYNCHEADER_out;
wire [1:0] PIPETX1CHARISK_out;
wire [1:0] PIPETX1EQCONTROL_out;
wire [1:0] PIPETX1POWERDOWN_out;
wire [1:0] PIPETX1RATE_out;
wire [1:0] PIPETX1SYNCHEADER_out;
wire [1:0] PIPETX2CHARISK_out;
wire [1:0] PIPETX2EQCONTROL_out;
wire [1:0] PIPETX2POWERDOWN_out;
wire [1:0] PIPETX2RATE_out;
wire [1:0] PIPETX2SYNCHEADER_out;
wire [1:0] PIPETX3CHARISK_out;
wire [1:0] PIPETX3EQCONTROL_out;
wire [1:0] PIPETX3POWERDOWN_out;
wire [1:0] PIPETX3RATE_out;
wire [1:0] PIPETX3SYNCHEADER_out;
wire [1:0] PIPETX4CHARISK_out;
wire [1:0] PIPETX4EQCONTROL_out;
wire [1:0] PIPETX4POWERDOWN_out;
wire [1:0] PIPETX4RATE_out;
wire [1:0] PIPETX4SYNCHEADER_out;
wire [1:0] PIPETX5CHARISK_out;
wire [1:0] PIPETX5EQCONTROL_out;
wire [1:0] PIPETX5POWERDOWN_out;
wire [1:0] PIPETX5RATE_out;
wire [1:0] PIPETX5SYNCHEADER_out;
wire [1:0] PIPETX6CHARISK_out;
wire [1:0] PIPETX6EQCONTROL_out;
wire [1:0] PIPETX6POWERDOWN_out;
wire [1:0] PIPETX6RATE_out;
wire [1:0] PIPETX6SYNCHEADER_out;
wire [1:0] PIPETX7CHARISK_out;
wire [1:0] PIPETX7EQCONTROL_out;
wire [1:0] PIPETX7POWERDOWN_out;
wire [1:0] PIPETX7RATE_out;
wire [1:0] PIPETX7SYNCHEADER_out;
wire [1:0] PLEQPHASE_out;
wire [23:0] CFGVFPOWERSTATE_out;
wire [23:0] CFGVFTPHSTMODE_out;
wire [255:0] LL2LMMAXISRXTDATA_out;
wire [255:0] MAXISCQTDATA_out;
wire [255:0] MAXISRCTDATA_out;
wire [2:0] CFGCURRENTSPEED_out;
wire [2:0] CFGMAXPAYLOAD_out;
wire [2:0] CFGMAXREADREQ_out;
wire [2:0] PIPERX0EQPRESET_out;
wire [2:0] PIPERX1EQPRESET_out;
wire [2:0] PIPERX2EQPRESET_out;
wire [2:0] PIPERX3EQPRESET_out;
wire [2:0] PIPERX4EQPRESET_out;
wire [2:0] PIPERX5EQPRESET_out;
wire [2:0] PIPERX6EQPRESET_out;
wire [2:0] PIPERX7EQPRESET_out;
wire [2:0] PIPETX0MARGIN_out;
wire [2:0] PIPETX1MARGIN_out;
wire [2:0] PIPETX2MARGIN_out;
wire [2:0] PIPETX3MARGIN_out;
wire [2:0] PIPETX4MARGIN_out;
wire [2:0] PIPETX5MARGIN_out;
wire [2:0] PIPETX6MARGIN_out;
wire [2:0] PIPETX7MARGIN_out;
wire [31:0] CFGEXTWRITEDATA_out;
wire [31:0] CFGINTERRUPTMSIDATA_out;
wire [31:0] CFGMGMTREADDATA_out;
wire [31:0] CFGTPHSTTWRITEDATA_out;
wire [31:0] CONFRESPRDATA_out;
wire [31:0] DBGMCAPDATA_out;
wire [31:0] PIPETX0DATA_out;
wire [31:0] PIPETX1DATA_out;
wire [31:0] PIPETX2DATA_out;
wire [31:0] PIPETX3DATA_out;
wire [31:0] PIPETX4DATA_out;
wire [31:0] PIPETX5DATA_out;
wire [31:0] PIPETX6DATA_out;
wire [31:0] PIPETX7DATA_out;
wire [31:0] SPAREOUT_out;
wire [3:0] CFGDPASUBSTATECHANGE_out;
wire [3:0] CFGEXTWRITEBYTEENABLE_out;
wire [3:0] CFGFLRINPROCESS_out;
wire [3:0] CFGINTERRUPTMSIENABLE_out;
wire [3:0] CFGINTERRUPTMSIXENABLE_out;
wire [3:0] CFGINTERRUPTMSIXMASK_out;
wire [3:0] CFGNEGOTIATEDWIDTH_out;
wire [3:0] CFGRCBSTATUS_out;
wire [3:0] CFGTPHFUNCTIONNUM_out;
wire [3:0] CFGTPHREQUESTERENABLE_out;
wire [3:0] CFGTPHSTTWRITEBYTEVALID_out;
wire [3:0] LL2LMMASTERTLPSENTTLPID0_out;
wire [3:0] LL2LMMASTERTLPSENTTLPID1_out;
wire [3:0] MICOMPLETIONRAMREADENABLEL_out;
wire [3:0] MICOMPLETIONRAMREADENABLEU_out;
wire [3:0] MICOMPLETIONRAMWRITEENABLEL_out;
wire [3:0] MICOMPLETIONRAMWRITEENABLEU_out;
wire [3:0] MIREQUESTRAMREADENABLE_out;
wire [3:0] MIREQUESTRAMWRITEENABLE_out;
wire [3:0] PCIERQSEQNUM_out;
wire [3:0] PIPERX0EQLPTXPRESET_out;
wire [3:0] PIPERX1EQLPTXPRESET_out;
wire [3:0] PIPERX2EQLPTXPRESET_out;
wire [3:0] PIPERX3EQLPTXPRESET_out;
wire [3:0] PIPERX4EQLPTXPRESET_out;
wire [3:0] PIPERX5EQLPTXPRESET_out;
wire [3:0] PIPERX6EQLPTXPRESET_out;
wire [3:0] PIPERX7EQLPTXPRESET_out;
wire [3:0] PIPETX0EQPRESET_out;
wire [3:0] PIPETX1EQPRESET_out;
wire [3:0] PIPETX2EQPRESET_out;
wire [3:0] PIPETX3EQPRESET_out;
wire [3:0] PIPETX4EQPRESET_out;
wire [3:0] PIPETX5EQPRESET_out;
wire [3:0] PIPETX6EQPRESET_out;
wire [3:0] PIPETX7EQPRESET_out;
wire [3:0] SAXISCCTREADY_out;
wire [3:0] SAXISRQTREADY_out;
wire [479:0] XILUNCONNBOUT_out;
wire [4:0] CFGMSGRECEIVEDTYPE_out;
wire [4:0] CFGTPHSTTADDRESS_out;
wire [5:0] CFGLTSSMSTATE_out;
wire [5:0] PCIECQNPREQCOUNT_out;
wire [5:0] PCIERQTAG_out;
wire [5:0] PIPERX0EQLPLFFS_out;
wire [5:0] PIPERX1EQLPLFFS_out;
wire [5:0] PIPERX2EQLPLFFS_out;
wire [5:0] PIPERX3EQLPLFFS_out;
wire [5:0] PIPERX4EQLPLFFS_out;
wire [5:0] PIPERX5EQLPLFFS_out;
wire [5:0] PIPERX6EQLPLFFS_out;
wire [5:0] PIPERX7EQLPLFFS_out;
wire [5:0] PIPETX0EQDEEMPH_out;
wire [5:0] PIPETX1EQDEEMPH_out;
wire [5:0] PIPETX2EQDEEMPH_out;
wire [5:0] PIPETX3EQDEEMPH_out;
wire [5:0] PIPETX4EQDEEMPH_out;
wire [5:0] PIPETX5EQDEEMPH_out;
wire [5:0] PIPETX6EQDEEMPH_out;
wire [5:0] PIPETX7EQDEEMPH_out;
wire [71:0] MICOMPLETIONRAMWRITEDATAL_out;
wire [71:0] MICOMPLETIONRAMWRITEDATAU_out;
wire [74:0] MAXISRCTUSER_out;
wire [7:0] CFGEXTFUNCTIONNUMBER_out;
wire [7:0] CFGFCCPLH_out;
wire [7:0] CFGFCNPH_out;
wire [7:0] CFGFCPH_out;
wire [7:0] CFGINTERRUPTMSIVFENABLE_out;
wire [7:0] CFGINTERRUPTMSIXVFENABLE_out;
wire [7:0] CFGINTERRUPTMSIXVFMASK_out;
wire [7:0] CFGMSGRECEIVEDDATA_out;
wire [7:0] CFGVFFLRINPROCESS_out;
wire [7:0] CFGVFTPHREQUESTERENABLE_out;
wire [7:0] DBGPLINFERREDRXELECTRICALIDLE_out;
wire [7:0] LL2LMMAXISRXTVALID_out;
wire [7:0] LL2LMSAXISTXTREADY_out;
wire [7:0] MAXISCQTKEEP_out;
wire [7:0] MAXISRCTKEEP_out;
wire [84:0] MAXISCQTUSER_out;
wire [860:0] XILUNCONNOUT_out;
wire [8:0] MIREPLAYRAMADDRESS_out;
wire [8:0] MIREQUESTRAMREADADDRESSA_out;
wire [8:0] MIREQUESTRAMREADADDRESSB_out;
wire [8:0] MIREQUESTRAMWRITEADDRESSA_out;
wire [8:0] MIREQUESTRAMWRITEADDRESSB_out;
wire [95:0] SCANOUT_out;
wire [9:0] CFGEXTREGISTERNUMBER_out;
wire [9:0] MICOMPLETIONRAMREADADDRESSAL_out;
wire [9:0] MICOMPLETIONRAMREADADDRESSAU_out;
wire [9:0] MICOMPLETIONRAMREADADDRESSBL_out;
wire [9:0] MICOMPLETIONRAMREADADDRESSBU_out;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSAL_out;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSAU_out;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSBL_out;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSBU_out;
wire CFGERRCOROUT_delay;
wire CFGERRFATALOUT_delay;
wire CFGERRNONFATALOUT_delay;
wire CFGEXTREADRECEIVED_delay;
wire CFGEXTWRITERECEIVED_delay;
wire CFGHOTRESETOUT_delay;
wire CFGINTERRUPTMSIFAIL_delay;
wire CFGINTERRUPTMSIMASKUPDATE_delay;
wire CFGINTERRUPTMSISENT_delay;
wire CFGINTERRUPTMSIXFAIL_delay;
wire CFGINTERRUPTMSIXSENT_delay;
wire CFGINTERRUPTSENT_delay;
wire CFGLOCALERROR_delay;
wire CFGLTRENABLE_delay;
wire CFGMGMTREADWRITEDONE_delay;
wire CFGMSGRECEIVED_delay;
wire CFGMSGTRANSMITDONE_delay;
wire CFGPERFUNCTIONUPDATEDONE_delay;
wire CFGPHYLINKDOWN_delay;
wire CFGPLSTATUSCHANGE_delay;
wire CFGPOWERSTATECHANGEINTERRUPT_delay;
wire CFGTPHSTTREADENABLE_delay;
wire CFGTPHSTTWRITEENABLE_delay;
wire CONFMCAPDESIGNSWITCH_delay;
wire CONFMCAPEOS_delay;
wire CONFMCAPINUSEBYPCIE_delay;
wire CONFREQREADY_delay;
wire CONFRESPVALID_delay;
wire DBGMCAPCSB_delay;
wire DBGMCAPEOS_delay;
wire DBGMCAPERROR_delay;
wire DBGMCAPMODE_delay;
wire DBGMCAPRDATAVALID_delay;
wire DBGMCAPRDWRB_delay;
wire DBGMCAPRESET_delay;
wire DBGPLDATABLOCKRECEIVEDAFTEREDS_delay;
wire DBGPLGEN3FRAMINGERRORDETECTED_delay;
wire DBGPLGEN3SYNCHEADERERRORDETECTED_delay;
wire DRPRDY_delay;
wire LL2LMMASTERTLPSENT0_delay;
wire LL2LMMASTERTLPSENT1_delay;
wire MAXISCQTLAST_delay;
wire MAXISCQTVALID_delay;
wire MAXISRCTLAST_delay;
wire MAXISRCTVALID_delay;
wire PCIEPERST0B_delay;
wire PCIEPERST1B_delay;
wire PCIERQSEQNUMVLD_delay;
wire PCIERQTAGVLD_delay;
wire PIPERX0POLARITY_delay;
wire PIPERX1POLARITY_delay;
wire PIPERX2POLARITY_delay;
wire PIPERX3POLARITY_delay;
wire PIPERX4POLARITY_delay;
wire PIPERX5POLARITY_delay;
wire PIPERX6POLARITY_delay;
wire PIPERX7POLARITY_delay;
wire PIPETX0COMPLIANCE_delay;
wire PIPETX0DATAVALID_delay;
wire PIPETX0DEEMPH_delay;
wire PIPETX0ELECIDLE_delay;
wire PIPETX0RCVRDET_delay;
wire PIPETX0RESET_delay;
wire PIPETX0STARTBLOCK_delay;
wire PIPETX0SWING_delay;
wire PIPETX1COMPLIANCE_delay;
wire PIPETX1DATAVALID_delay;
wire PIPETX1DEEMPH_delay;
wire PIPETX1ELECIDLE_delay;
wire PIPETX1RCVRDET_delay;
wire PIPETX1RESET_delay;
wire PIPETX1STARTBLOCK_delay;
wire PIPETX1SWING_delay;
wire PIPETX2COMPLIANCE_delay;
wire PIPETX2DATAVALID_delay;
wire PIPETX2DEEMPH_delay;
wire PIPETX2ELECIDLE_delay;
wire PIPETX2RCVRDET_delay;
wire PIPETX2RESET_delay;
wire PIPETX2STARTBLOCK_delay;
wire PIPETX2SWING_delay;
wire PIPETX3COMPLIANCE_delay;
wire PIPETX3DATAVALID_delay;
wire PIPETX3DEEMPH_delay;
wire PIPETX3ELECIDLE_delay;
wire PIPETX3RCVRDET_delay;
wire PIPETX3RESET_delay;
wire PIPETX3STARTBLOCK_delay;
wire PIPETX3SWING_delay;
wire PIPETX4COMPLIANCE_delay;
wire PIPETX4DATAVALID_delay;
wire PIPETX4DEEMPH_delay;
wire PIPETX4ELECIDLE_delay;
wire PIPETX4RCVRDET_delay;
wire PIPETX4RESET_delay;
wire PIPETX4STARTBLOCK_delay;
wire PIPETX4SWING_delay;
wire PIPETX5COMPLIANCE_delay;
wire PIPETX5DATAVALID_delay;
wire PIPETX5DEEMPH_delay;
wire PIPETX5ELECIDLE_delay;
wire PIPETX5RCVRDET_delay;
wire PIPETX5RESET_delay;
wire PIPETX5STARTBLOCK_delay;
wire PIPETX5SWING_delay;
wire PIPETX6COMPLIANCE_delay;
wire PIPETX6DATAVALID_delay;
wire PIPETX6DEEMPH_delay;
wire PIPETX6ELECIDLE_delay;
wire PIPETX6RCVRDET_delay;
wire PIPETX6RESET_delay;
wire PIPETX6STARTBLOCK_delay;
wire PIPETX6SWING_delay;
wire PIPETX7COMPLIANCE_delay;
wire PIPETX7DATAVALID_delay;
wire PIPETX7DEEMPH_delay;
wire PIPETX7ELECIDLE_delay;
wire PIPETX7RCVRDET_delay;
wire PIPETX7RESET_delay;
wire PIPETX7STARTBLOCK_delay;
wire PIPETX7SWING_delay;
wire PLEQINPROGRESS_delay;
wire [11:0] CFGFCCPLD_delay;
wire [11:0] CFGFCNPD_delay;
wire [11:0] CFGFCPD_delay;
wire [11:0] CFGFUNCTIONPOWERSTATE_delay;
wire [11:0] CFGINTERRUPTMSIMMENABLE_delay;
wire [11:0] CFGTPHSTMODE_delay;
wire [143:0] MIREPLAYRAMWRITEDATA_delay;
wire [143:0] MIREQUESTRAMWRITEDATA_delay;
wire [15:0] CFGFUNCTIONSTATUS_delay;
wire [15:0] CFGPERFUNCSTATUSDATA_delay;
wire [15:0] CFGVFSTATUS_delay;
wire [15:0] DBGDATAOUT_delay;
wire [15:0] DRPDO_delay;
wire [17:0] LL2LMMAXISRXTUSER_delay;
wire [1:0] CFGLINKPOWERSTATE_delay;
wire [1:0] CFGOBFFENABLE_delay;
wire [1:0] CFGPHYLINKSTATUS_delay;
wire [1:0] MIREPLAYRAMREADENABLE_delay;
wire [1:0] MIREPLAYRAMWRITEENABLE_delay;
wire [1:0] PCIERQTAGAV_delay;
wire [1:0] PCIETFCNPDAV_delay;
wire [1:0] PCIETFCNPHAV_delay;
wire [1:0] PIPERX0EQCONTROL_delay;
wire [1:0] PIPERX1EQCONTROL_delay;
wire [1:0] PIPERX2EQCONTROL_delay;
wire [1:0] PIPERX3EQCONTROL_delay;
wire [1:0] PIPERX4EQCONTROL_delay;
wire [1:0] PIPERX5EQCONTROL_delay;
wire [1:0] PIPERX6EQCONTROL_delay;
wire [1:0] PIPERX7EQCONTROL_delay;
wire [1:0] PIPETX0CHARISK_delay;
wire [1:0] PIPETX0EQCONTROL_delay;
wire [1:0] PIPETX0POWERDOWN_delay;
wire [1:0] PIPETX0RATE_delay;
wire [1:0] PIPETX0SYNCHEADER_delay;
wire [1:0] PIPETX1CHARISK_delay;
wire [1:0] PIPETX1EQCONTROL_delay;
wire [1:0] PIPETX1POWERDOWN_delay;
wire [1:0] PIPETX1RATE_delay;
wire [1:0] PIPETX1SYNCHEADER_delay;
wire [1:0] PIPETX2CHARISK_delay;
wire [1:0] PIPETX2EQCONTROL_delay;
wire [1:0] PIPETX2POWERDOWN_delay;
wire [1:0] PIPETX2RATE_delay;
wire [1:0] PIPETX2SYNCHEADER_delay;
wire [1:0] PIPETX3CHARISK_delay;
wire [1:0] PIPETX3EQCONTROL_delay;
wire [1:0] PIPETX3POWERDOWN_delay;
wire [1:0] PIPETX3RATE_delay;
wire [1:0] PIPETX3SYNCHEADER_delay;
wire [1:0] PIPETX4CHARISK_delay;
wire [1:0] PIPETX4EQCONTROL_delay;
wire [1:0] PIPETX4POWERDOWN_delay;
wire [1:0] PIPETX4RATE_delay;
wire [1:0] PIPETX4SYNCHEADER_delay;
wire [1:0] PIPETX5CHARISK_delay;
wire [1:0] PIPETX5EQCONTROL_delay;
wire [1:0] PIPETX5POWERDOWN_delay;
wire [1:0] PIPETX5RATE_delay;
wire [1:0] PIPETX5SYNCHEADER_delay;
wire [1:0] PIPETX6CHARISK_delay;
wire [1:0] PIPETX6EQCONTROL_delay;
wire [1:0] PIPETX6POWERDOWN_delay;
wire [1:0] PIPETX6RATE_delay;
wire [1:0] PIPETX6SYNCHEADER_delay;
wire [1:0] PIPETX7CHARISK_delay;
wire [1:0] PIPETX7EQCONTROL_delay;
wire [1:0] PIPETX7POWERDOWN_delay;
wire [1:0] PIPETX7RATE_delay;
wire [1:0] PIPETX7SYNCHEADER_delay;
wire [1:0] PLEQPHASE_delay;
wire [23:0] CFGVFPOWERSTATE_delay;
wire [23:0] CFGVFTPHSTMODE_delay;
wire [255:0] LL2LMMAXISRXTDATA_delay;
wire [255:0] MAXISCQTDATA_delay;
wire [255:0] MAXISRCTDATA_delay;
wire [2:0] CFGCURRENTSPEED_delay;
wire [2:0] CFGMAXPAYLOAD_delay;
wire [2:0] CFGMAXREADREQ_delay;
wire [2:0] PIPERX0EQPRESET_delay;
wire [2:0] PIPERX1EQPRESET_delay;
wire [2:0] PIPERX2EQPRESET_delay;
wire [2:0] PIPERX3EQPRESET_delay;
wire [2:0] PIPERX4EQPRESET_delay;
wire [2:0] PIPERX5EQPRESET_delay;
wire [2:0] PIPERX6EQPRESET_delay;
wire [2:0] PIPERX7EQPRESET_delay;
wire [2:0] PIPETX0MARGIN_delay;
wire [2:0] PIPETX1MARGIN_delay;
wire [2:0] PIPETX2MARGIN_delay;
wire [2:0] PIPETX3MARGIN_delay;
wire [2:0] PIPETX4MARGIN_delay;
wire [2:0] PIPETX5MARGIN_delay;
wire [2:0] PIPETX6MARGIN_delay;
wire [2:0] PIPETX7MARGIN_delay;
wire [31:0] CFGEXTWRITEDATA_delay;
wire [31:0] CFGINTERRUPTMSIDATA_delay;
wire [31:0] CFGMGMTREADDATA_delay;
wire [31:0] CFGTPHSTTWRITEDATA_delay;
wire [31:0] CONFRESPRDATA_delay;
wire [31:0] DBGMCAPDATA_delay;
wire [31:0] PIPETX0DATA_delay;
wire [31:0] PIPETX1DATA_delay;
wire [31:0] PIPETX2DATA_delay;
wire [31:0] PIPETX3DATA_delay;
wire [31:0] PIPETX4DATA_delay;
wire [31:0] PIPETX5DATA_delay;
wire [31:0] PIPETX6DATA_delay;
wire [31:0] PIPETX7DATA_delay;
wire [31:0] SPAREOUT_delay;
wire [3:0] CFGDPASUBSTATECHANGE_delay;
wire [3:0] CFGEXTWRITEBYTEENABLE_delay;
wire [3:0] CFGFLRINPROCESS_delay;
wire [3:0] CFGINTERRUPTMSIENABLE_delay;
wire [3:0] CFGINTERRUPTMSIXENABLE_delay;
wire [3:0] CFGINTERRUPTMSIXMASK_delay;
wire [3:0] CFGNEGOTIATEDWIDTH_delay;
wire [3:0] CFGRCBSTATUS_delay;
wire [3:0] CFGTPHFUNCTIONNUM_delay;
wire [3:0] CFGTPHREQUESTERENABLE_delay;
wire [3:0] CFGTPHSTTWRITEBYTEVALID_delay;
wire [3:0] LL2LMMASTERTLPSENTTLPID0_delay;
wire [3:0] LL2LMMASTERTLPSENTTLPID1_delay;
wire [3:0] MICOMPLETIONRAMREADENABLEL_delay;
wire [3:0] MICOMPLETIONRAMREADENABLEU_delay;
wire [3:0] MICOMPLETIONRAMWRITEENABLEL_delay;
wire [3:0] MICOMPLETIONRAMWRITEENABLEU_delay;
wire [3:0] MIREQUESTRAMREADENABLE_delay;
wire [3:0] MIREQUESTRAMWRITEENABLE_delay;
wire [3:0] PCIERQSEQNUM_delay;
wire [3:0] PIPERX0EQLPTXPRESET_delay;
wire [3:0] PIPERX1EQLPTXPRESET_delay;
wire [3:0] PIPERX2EQLPTXPRESET_delay;
wire [3:0] PIPERX3EQLPTXPRESET_delay;
wire [3:0] PIPERX4EQLPTXPRESET_delay;
wire [3:0] PIPERX5EQLPTXPRESET_delay;
wire [3:0] PIPERX6EQLPTXPRESET_delay;
wire [3:0] PIPERX7EQLPTXPRESET_delay;
wire [3:0] PIPETX0EQPRESET_delay;
wire [3:0] PIPETX1EQPRESET_delay;
wire [3:0] PIPETX2EQPRESET_delay;
wire [3:0] PIPETX3EQPRESET_delay;
wire [3:0] PIPETX4EQPRESET_delay;
wire [3:0] PIPETX5EQPRESET_delay;
wire [3:0] PIPETX6EQPRESET_delay;
wire [3:0] PIPETX7EQPRESET_delay;
wire [3:0] SAXISCCTREADY_delay;
wire [3:0] SAXISRQTREADY_delay;
wire [4:0] CFGMSGRECEIVEDTYPE_delay;
wire [4:0] CFGTPHSTTADDRESS_delay;
wire [5:0] CFGLTSSMSTATE_delay;
wire [5:0] PCIECQNPREQCOUNT_delay;
wire [5:0] PCIERQTAG_delay;
wire [5:0] PIPERX0EQLPLFFS_delay;
wire [5:0] PIPERX1EQLPLFFS_delay;
wire [5:0] PIPERX2EQLPLFFS_delay;
wire [5:0] PIPERX3EQLPLFFS_delay;
wire [5:0] PIPERX4EQLPLFFS_delay;
wire [5:0] PIPERX5EQLPLFFS_delay;
wire [5:0] PIPERX6EQLPLFFS_delay;
wire [5:0] PIPERX7EQLPLFFS_delay;
wire [5:0] PIPETX0EQDEEMPH_delay;
wire [5:0] PIPETX1EQDEEMPH_delay;
wire [5:0] PIPETX2EQDEEMPH_delay;
wire [5:0] PIPETX3EQDEEMPH_delay;
wire [5:0] PIPETX4EQDEEMPH_delay;
wire [5:0] PIPETX5EQDEEMPH_delay;
wire [5:0] PIPETX6EQDEEMPH_delay;
wire [5:0] PIPETX7EQDEEMPH_delay;
wire [71:0] MICOMPLETIONRAMWRITEDATAL_delay;
wire [71:0] MICOMPLETIONRAMWRITEDATAU_delay;
wire [74:0] MAXISRCTUSER_delay;
wire [7:0] CFGEXTFUNCTIONNUMBER_delay;
wire [7:0] CFGFCCPLH_delay;
wire [7:0] CFGFCNPH_delay;
wire [7:0] CFGFCPH_delay;
wire [7:0] CFGINTERRUPTMSIVFENABLE_delay;
wire [7:0] CFGINTERRUPTMSIXVFENABLE_delay;
wire [7:0] CFGINTERRUPTMSIXVFMASK_delay;
wire [7:0] CFGMSGRECEIVEDDATA_delay;
wire [7:0] CFGVFFLRINPROCESS_delay;
wire [7:0] CFGVFTPHREQUESTERENABLE_delay;
wire [7:0] DBGPLINFERREDRXELECTRICALIDLE_delay;
wire [7:0] LL2LMMAXISRXTVALID_delay;
wire [7:0] LL2LMSAXISTXTREADY_delay;
wire [7:0] MAXISCQTKEEP_delay;
wire [7:0] MAXISRCTKEEP_delay;
wire [84:0] MAXISCQTUSER_delay;
wire [8:0] MIREPLAYRAMADDRESS_delay;
wire [8:0] MIREQUESTRAMREADADDRESSA_delay;
wire [8:0] MIREQUESTRAMREADADDRESSB_delay;
wire [8:0] MIREQUESTRAMWRITEADDRESSA_delay;
wire [8:0] MIREQUESTRAMWRITEADDRESSB_delay;
wire [9:0] CFGEXTREGISTERNUMBER_delay;
wire [9:0] MICOMPLETIONRAMREADADDRESSAL_delay;
wire [9:0] MICOMPLETIONRAMREADADDRESSAU_delay;
wire [9:0] MICOMPLETIONRAMREADADDRESSBL_delay;
wire [9:0] MICOMPLETIONRAMREADADDRESSBU_delay;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSAL_delay;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSAU_delay;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSBL_delay;
wire [9:0] MICOMPLETIONRAMWRITEADDRESSBU_delay;
wire CFGCONFIGSPACEENABLE_in;
wire CFGERRCORIN_in;
wire CFGERRUNCORIN_in;
wire CFGEXTREADDATAVALID_in;
wire CFGHOTRESETIN_in;
wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in;
wire CFGINTERRUPTMSITPHPRESENT_in;
wire CFGINTERRUPTMSIXINT_in;
wire CFGLINKTRAININGENABLE_in;
wire CFGMGMTREAD_in;
wire CFGMGMTTYPE1CFGREGACCESS_in;
wire CFGMGMTWRITE_in;
wire CFGMSGTRANSMIT_in;
wire CFGPERFUNCTIONOUTPUTREQUEST_in;
wire CFGPOWERSTATECHANGEACK_in;
wire CFGREQPMTRANSITIONL23READY_in;
wire CFGTPHSTTREADDATAVALID_in;
wire CONFMCAPREQUESTBYCONF_in;
wire CONFREQVALID_in;
wire CORECLKMICOMPLETIONRAML_in;
wire CORECLKMICOMPLETIONRAMU_in;
wire CORECLKMIREPLAYRAM_in;
wire CORECLKMIREQUESTRAM_in;
wire CORECLK_in;
wire DBGCFGLOCALMGMTREGOVERRIDE_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire LL2LMSAXISTXTVALID_in;
wire MCAPCLK_in;
wire MGMTRESETN_in;
wire MGMTSTICKYRESETN_in;
wire PCIECQNPREQ_in;
wire PIPECLK_in;
wire PIPERESETN_in;
wire PIPERX0DATAVALID_in;
wire PIPERX0ELECIDLE_in;
wire PIPERX0EQDONE_in;
wire PIPERX0EQLPADAPTDONE_in;
wire PIPERX0EQLPLFFSSEL_in;
wire PIPERX0PHYSTATUS_in;
wire PIPERX0STARTBLOCK_in;
wire PIPERX0VALID_in;
wire PIPERX1DATAVALID_in;
wire PIPERX1ELECIDLE_in;
wire PIPERX1EQDONE_in;
wire PIPERX1EQLPADAPTDONE_in;
wire PIPERX1EQLPLFFSSEL_in;
wire PIPERX1PHYSTATUS_in;
wire PIPERX1STARTBLOCK_in;
wire PIPERX1VALID_in;
wire PIPERX2DATAVALID_in;
wire PIPERX2ELECIDLE_in;
wire PIPERX2EQDONE_in;
wire PIPERX2EQLPADAPTDONE_in;
wire PIPERX2EQLPLFFSSEL_in;
wire PIPERX2PHYSTATUS_in;
wire PIPERX2STARTBLOCK_in;
wire PIPERX2VALID_in;
wire PIPERX3DATAVALID_in;
wire PIPERX3ELECIDLE_in;
wire PIPERX3EQDONE_in;
wire PIPERX3EQLPADAPTDONE_in;
wire PIPERX3EQLPLFFSSEL_in;
wire PIPERX3PHYSTATUS_in;
wire PIPERX3STARTBLOCK_in;
wire PIPERX3VALID_in;
wire PIPERX4DATAVALID_in;
wire PIPERX4ELECIDLE_in;
wire PIPERX4EQDONE_in;
wire PIPERX4EQLPADAPTDONE_in;
wire PIPERX4EQLPLFFSSEL_in;
wire PIPERX4PHYSTATUS_in;
wire PIPERX4STARTBLOCK_in;
wire PIPERX4VALID_in;
wire PIPERX5DATAVALID_in;
wire PIPERX5ELECIDLE_in;
wire PIPERX5EQDONE_in;
wire PIPERX5EQLPADAPTDONE_in;
wire PIPERX5EQLPLFFSSEL_in;
wire PIPERX5PHYSTATUS_in;
wire PIPERX5STARTBLOCK_in;
wire PIPERX5VALID_in;
wire PIPERX6DATAVALID_in;
wire PIPERX6ELECIDLE_in;
wire PIPERX6EQDONE_in;
wire PIPERX6EQLPADAPTDONE_in;
wire PIPERX6EQLPLFFSSEL_in;
wire PIPERX6PHYSTATUS_in;
wire PIPERX6STARTBLOCK_in;
wire PIPERX6VALID_in;
wire PIPERX7DATAVALID_in;
wire PIPERX7ELECIDLE_in;
wire PIPERX7EQDONE_in;
wire PIPERX7EQLPADAPTDONE_in;
wire PIPERX7EQLPLFFSSEL_in;
wire PIPERX7PHYSTATUS_in;
wire PIPERX7STARTBLOCK_in;
wire PIPERX7VALID_in;
wire PIPETX0EQDONE_in;
wire PIPETX1EQDONE_in;
wire PIPETX2EQDONE_in;
wire PIPETX3EQDONE_in;
wire PIPETX4EQDONE_in;
wire PIPETX5EQDONE_in;
wire PIPETX6EQDONE_in;
wire PIPETX7EQDONE_in;
wire PLEQRESETEIEOSCOUNT_in;
wire PLGEN2UPSTREAMPREFERDEEMPH_in;
wire PMVENABLEN_in;
wire RESETN_in;
wire SAXISCCTLAST_in;
wire SAXISCCTVALID_in;
wire SAXISRQTLAST_in;
wire SAXISRQTVALID_in;
wire SCANENABLEN_in;
wire SCANMODEN_in;
wire USERCLK_in;
wire [13:0] LL2LMSAXISTXTUSER_in;
wire [143:0] MICOMPLETIONRAMREADDATA_in;
wire [143:0] MIREPLAYRAMREADDATA_in;
wire [143:0] MIREQUESTRAMREADDATA_in;
wire [15:0] CFGDEVID_in;
wire [15:0] CFGSUBSYSID_in;
wire [15:0] CFGSUBSYSVENDID_in;
wire [15:0] CFGVENDID_in;
wire [15:0] DRPDI_in;
wire [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET_in;
wire [17:0] PIPETX0EQCOEFF_in;
wire [17:0] PIPETX1EQCOEFF_in;
wire [17:0] PIPETX2EQCOEFF_in;
wire [17:0] PIPETX3EQCOEFF_in;
wire [17:0] PIPETX4EQCOEFF_in;
wire [17:0] PIPETX5EQCOEFF_in;
wire [17:0] PIPETX6EQCOEFF_in;
wire [17:0] PIPETX7EQCOEFF_in;
wire [18:0] CFGMGMTADDR_in;
wire [1919:0] XILUNCONNBYP_in;
wire [1:0] CFGINTERRUPTMSITPHTYPE_in;
wire [1:0] CONFREQTYPE_in;
wire [1:0] PIPERX0CHARISK_in;
wire [1:0] PIPERX0SYNCHEADER_in;
wire [1:0] PIPERX1CHARISK_in;
wire [1:0] PIPERX1SYNCHEADER_in;
wire [1:0] PIPERX2CHARISK_in;
wire [1:0] PIPERX2SYNCHEADER_in;
wire [1:0] PIPERX3CHARISK_in;
wire [1:0] PIPERX3SYNCHEADER_in;
wire [1:0] PIPERX4CHARISK_in;
wire [1:0] PIPERX4SYNCHEADER_in;
wire [1:0] PIPERX5CHARISK_in;
wire [1:0] PIPERX5SYNCHEADER_in;
wire [1:0] PIPERX6CHARISK_in;
wire [1:0] PIPERX6SYNCHEADER_in;
wire [1:0] PIPERX7CHARISK_in;
wire [1:0] PIPERX7SYNCHEADER_in;
wire [1:0] PMVDIVIDE_in;
wire [21:0] MAXISCQTREADY_in;
wire [21:0] MAXISRCTREADY_in;
wire [255:0] SAXISCCTDATA_in;
wire [255:0] SAXISRQTDATA_in;
wire [2:0] CFGDSFUNCTIONNUMBER_in;
wire [2:0] CFGFCSEL_in;
wire [2:0] CFGINTERRUPTMSIATTR_in;
wire [2:0] CFGMSGTRANSMITTYPE_in;
wire [2:0] CFGPERFUNCSTATUSCONTROL_in;
wire [2:0] PIPERX0STATUS_in;
wire [2:0] PIPERX1STATUS_in;
wire [2:0] PIPERX2STATUS_in;
wire [2:0] PIPERX3STATUS_in;
wire [2:0] PIPERX4STATUS_in;
wire [2:0] PIPERX5STATUS_in;
wire [2:0] PIPERX6STATUS_in;
wire [2:0] PIPERX7STATUS_in;
wire [2:0] PMVSELECT_in;
wire [3188:0] XILUNCONNIN_in;
wire [31:0] CFGEXTREADDATA_in;
wire [31:0] CFGINTERRUPTMSIINT_in;
wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_in;
wire [31:0] CFGINTERRUPTMSIXDATA_in;
wire [31:0] CFGMGMTWRITEDATA_in;
wire [31:0] CFGMSGTRANSMITDATA_in;
wire [31:0] CFGTPHSTTREADDATA_in;
wire [31:0] CONFREQDATA_in;
wire [31:0] PIPERX0DATA_in;
wire [31:0] PIPERX1DATA_in;
wire [31:0] PIPERX2DATA_in;
wire [31:0] PIPERX3DATA_in;
wire [31:0] PIPERX4DATA_in;
wire [31:0] PIPERX5DATA_in;
wire [31:0] PIPERX6DATA_in;
wire [31:0] PIPERX7DATA_in;
wire [31:0] SPAREIN_in;
wire [32:0] SAXISCCTUSER_in;
wire [3:0] CFGFLRDONE_in;
wire [3:0] CFGINTERRUPTINT_in;
wire [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER_in;
wire [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in;
wire [3:0] CFGINTERRUPTMSISELECT_in;
wire [3:0] CFGINTERRUPTPENDING_in;
wire [3:0] CFGMGMTBYTEENABLE_in;
wire [3:0] CFGPERFUNCTIONNUMBER_in;
wire [3:0] CONFREQREGNUM_in;
wire [3:0] DBGDATASEL_in;
wire [3:0] LL2LMTXTLPID0_in;
wire [3:0] LL2LMTXTLPID1_in;
wire [4:0] CFGDSDEVICENUMBER_in;
wire [59:0] SAXISRQTUSER_in;
wire [5:0] PIPEEQFS_in;
wire [5:0] PIPEEQLF_in;
wire [63:0] CFGDSN_in;
wire [63:0] CFGINTERRUPTMSIXADDRESS_in;
wire [7:0] CFGDSBUSNUMBER_in;
wire [7:0] CFGDSPORTNUMBER_in;
wire [7:0] CFGREVID_in;
wire [7:0] CFGVFFLRDONE_in;
wire [7:0] SAXISCCTKEEP_in;
wire [7:0] SAXISRQTKEEP_in;
wire [8:0] CFGINTERRUPTMSITPHSTTAG_in;
wire [950:0] XILUNCONNCLK_in;
wire [95:0] SCANIN_in;
wire [9:0] DRPADDR_in;
wire CFGCONFIGSPACEENABLE_delay;
wire CFGERRCORIN_delay;
wire CFGERRUNCORIN_delay;
wire CFGEXTREADDATAVALID_delay;
wire CFGHOTRESETIN_delay;
wire CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay;
wire CFGINTERRUPTMSITPHPRESENT_delay;
wire CFGINTERRUPTMSIXINT_delay;
wire CFGLINKTRAININGENABLE_delay;
wire CFGMGMTREAD_delay;
wire CFGMGMTTYPE1CFGREGACCESS_delay;
wire CFGMGMTWRITE_delay;
wire CFGMSGTRANSMIT_delay;
wire CFGPERFUNCTIONOUTPUTREQUEST_delay;
wire CFGPOWERSTATECHANGEACK_delay;
wire CFGREQPMTRANSITIONL23READY_delay;
wire CFGTPHSTTREADDATAVALID_delay;
wire CONFMCAPREQUESTBYCONF_delay;
wire CONFREQVALID_delay;
wire CORECLKMICOMPLETIONRAML_delay;
wire CORECLKMICOMPLETIONRAMU_delay;
wire CORECLKMIREPLAYRAM_delay;
wire CORECLKMIREQUESTRAM_delay;
wire CORECLK_delay;
wire DBGCFGLOCALMGMTREGOVERRIDE_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire LL2LMSAXISTXTVALID_delay;
wire MCAPCLK_delay;
wire MGMTRESETN_delay;
wire MGMTSTICKYRESETN_delay;
wire PCIECQNPREQ_delay;
wire PIPECLK_delay;
wire PIPERESETN_delay;
wire PIPERX0DATAVALID_delay;
wire PIPERX0ELECIDLE_delay;
wire PIPERX0EQDONE_delay;
wire PIPERX0EQLPADAPTDONE_delay;
wire PIPERX0EQLPLFFSSEL_delay;
wire PIPERX0PHYSTATUS_delay;
wire PIPERX0STARTBLOCK_delay;
wire PIPERX0VALID_delay;
wire PIPERX1DATAVALID_delay;
wire PIPERX1ELECIDLE_delay;
wire PIPERX1EQDONE_delay;
wire PIPERX1EQLPADAPTDONE_delay;
wire PIPERX1EQLPLFFSSEL_delay;
wire PIPERX1PHYSTATUS_delay;
wire PIPERX1STARTBLOCK_delay;
wire PIPERX1VALID_delay;
wire PIPERX2DATAVALID_delay;
wire PIPERX2ELECIDLE_delay;
wire PIPERX2EQDONE_delay;
wire PIPERX2EQLPADAPTDONE_delay;
wire PIPERX2EQLPLFFSSEL_delay;
wire PIPERX2PHYSTATUS_delay;
wire PIPERX2STARTBLOCK_delay;
wire PIPERX2VALID_delay;
wire PIPERX3DATAVALID_delay;
wire PIPERX3ELECIDLE_delay;
wire PIPERX3EQDONE_delay;
wire PIPERX3EQLPADAPTDONE_delay;
wire PIPERX3EQLPLFFSSEL_delay;
wire PIPERX3PHYSTATUS_delay;
wire PIPERX3STARTBLOCK_delay;
wire PIPERX3VALID_delay;
wire PIPERX4DATAVALID_delay;
wire PIPERX4ELECIDLE_delay;
wire PIPERX4EQDONE_delay;
wire PIPERX4EQLPADAPTDONE_delay;
wire PIPERX4EQLPLFFSSEL_delay;
wire PIPERX4PHYSTATUS_delay;
wire PIPERX4STARTBLOCK_delay;
wire PIPERX4VALID_delay;
wire PIPERX5DATAVALID_delay;
wire PIPERX5ELECIDLE_delay;
wire PIPERX5EQDONE_delay;
wire PIPERX5EQLPADAPTDONE_delay;
wire PIPERX5EQLPLFFSSEL_delay;
wire PIPERX5PHYSTATUS_delay;
wire PIPERX5STARTBLOCK_delay;
wire PIPERX5VALID_delay;
wire PIPERX6DATAVALID_delay;
wire PIPERX6ELECIDLE_delay;
wire PIPERX6EQDONE_delay;
wire PIPERX6EQLPADAPTDONE_delay;
wire PIPERX6EQLPLFFSSEL_delay;
wire PIPERX6PHYSTATUS_delay;
wire PIPERX6STARTBLOCK_delay;
wire PIPERX6VALID_delay;
wire PIPERX7DATAVALID_delay;
wire PIPERX7ELECIDLE_delay;
wire PIPERX7EQDONE_delay;
wire PIPERX7EQLPADAPTDONE_delay;
wire PIPERX7EQLPLFFSSEL_delay;
wire PIPERX7PHYSTATUS_delay;
wire PIPERX7STARTBLOCK_delay;
wire PIPERX7VALID_delay;
wire PIPETX0EQDONE_delay;
wire PIPETX1EQDONE_delay;
wire PIPETX2EQDONE_delay;
wire PIPETX3EQDONE_delay;
wire PIPETX4EQDONE_delay;
wire PIPETX5EQDONE_delay;
wire PIPETX6EQDONE_delay;
wire PIPETX7EQDONE_delay;
wire PLEQRESETEIEOSCOUNT_delay;
wire PLGEN2UPSTREAMPREFERDEEMPH_delay;
wire RESETN_delay;
wire SAXISCCTLAST_delay;
wire SAXISCCTVALID_delay;
wire SAXISRQTLAST_delay;
wire SAXISRQTVALID_delay;
wire USERCLK_delay;
wire [13:0] LL2LMSAXISTXTUSER_delay;
wire [143:0] MICOMPLETIONRAMREADDATA_delay;
wire [143:0] MIREPLAYRAMREADDATA_delay;
wire [143:0] MIREQUESTRAMREADDATA_delay;
wire [15:0] CFGDEVID_delay;
wire [15:0] CFGSUBSYSID_delay;
wire [15:0] CFGSUBSYSVENDID_delay;
wire [15:0] CFGVENDID_delay;
wire [15:0] DRPDI_delay;
wire [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET_delay;
wire [17:0] PIPETX0EQCOEFF_delay;
wire [17:0] PIPETX1EQCOEFF_delay;
wire [17:0] PIPETX2EQCOEFF_delay;
wire [17:0] PIPETX3EQCOEFF_delay;
wire [17:0] PIPETX4EQCOEFF_delay;
wire [17:0] PIPETX5EQCOEFF_delay;
wire [17:0] PIPETX6EQCOEFF_delay;
wire [17:0] PIPETX7EQCOEFF_delay;
wire [18:0] CFGMGMTADDR_delay;
wire [1:0] CFGINTERRUPTMSITPHTYPE_delay;
wire [1:0] CONFREQTYPE_delay;
wire [1:0] PIPERX0CHARISK_delay;
wire [1:0] PIPERX0SYNCHEADER_delay;
wire [1:0] PIPERX1CHARISK_delay;
wire [1:0] PIPERX1SYNCHEADER_delay;
wire [1:0] PIPERX2CHARISK_delay;
wire [1:0] PIPERX2SYNCHEADER_delay;
wire [1:0] PIPERX3CHARISK_delay;
wire [1:0] PIPERX3SYNCHEADER_delay;
wire [1:0] PIPERX4CHARISK_delay;
wire [1:0] PIPERX4SYNCHEADER_delay;
wire [1:0] PIPERX5CHARISK_delay;
wire [1:0] PIPERX5SYNCHEADER_delay;
wire [1:0] PIPERX6CHARISK_delay;
wire [1:0] PIPERX6SYNCHEADER_delay;
wire [1:0] PIPERX7CHARISK_delay;
wire [1:0] PIPERX7SYNCHEADER_delay;
wire [21:0] MAXISCQTREADY_delay;
wire [21:0] MAXISRCTREADY_delay;
wire [255:0] SAXISCCTDATA_delay;
wire [255:0] SAXISRQTDATA_delay;
wire [2:0] CFGDSFUNCTIONNUMBER_delay;
wire [2:0] CFGFCSEL_delay;
wire [2:0] CFGINTERRUPTMSIATTR_delay;
wire [2:0] CFGMSGTRANSMITTYPE_delay;
wire [2:0] CFGPERFUNCSTATUSCONTROL_delay;
wire [2:0] PIPERX0STATUS_delay;
wire [2:0] PIPERX1STATUS_delay;
wire [2:0] PIPERX2STATUS_delay;
wire [2:0] PIPERX3STATUS_delay;
wire [2:0] PIPERX4STATUS_delay;
wire [2:0] PIPERX5STATUS_delay;
wire [2:0] PIPERX6STATUS_delay;
wire [2:0] PIPERX7STATUS_delay;
wire [31:0] CFGEXTREADDATA_delay;
wire [31:0] CFGINTERRUPTMSIINT_delay;
wire [31:0] CFGINTERRUPTMSIPENDINGSTATUS_delay;
wire [31:0] CFGINTERRUPTMSIXDATA_delay;
wire [31:0] CFGMGMTWRITEDATA_delay;
wire [31:0] CFGMSGTRANSMITDATA_delay;
wire [31:0] CFGTPHSTTREADDATA_delay;
wire [31:0] CONFREQDATA_delay;
wire [31:0] PIPERX0DATA_delay;
wire [31:0] PIPERX1DATA_delay;
wire [31:0] PIPERX2DATA_delay;
wire [31:0] PIPERX3DATA_delay;
wire [31:0] PIPERX4DATA_delay;
wire [31:0] PIPERX5DATA_delay;
wire [31:0] PIPERX6DATA_delay;
wire [31:0] PIPERX7DATA_delay;
wire [31:0] SPAREIN_delay;
wire [32:0] SAXISCCTUSER_delay;
wire [3:0] CFGFLRDONE_delay;
wire [3:0] CFGINTERRUPTINT_delay;
wire [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER_delay;
wire [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay;
wire [3:0] CFGINTERRUPTMSISELECT_delay;
wire [3:0] CFGINTERRUPTPENDING_delay;
wire [3:0] CFGMGMTBYTEENABLE_delay;
wire [3:0] CFGPERFUNCTIONNUMBER_delay;
wire [3:0] CONFREQREGNUM_delay;
wire [3:0] DBGDATASEL_delay;
wire [3:0] LL2LMTXTLPID0_delay;
wire [3:0] LL2LMTXTLPID1_delay;
wire [4:0] CFGDSDEVICENUMBER_delay;
wire [59:0] SAXISRQTUSER_delay;
wire [5:0] PIPEEQFS_delay;
wire [5:0] PIPEEQLF_delay;
wire [63:0] CFGDSN_delay;
wire [63:0] CFGINTERRUPTMSIXADDRESS_delay;
wire [7:0] CFGDSBUSNUMBER_delay;
wire [7:0] CFGDSPORTNUMBER_delay;
wire [7:0] CFGREVID_delay;
wire [7:0] CFGVFFLRDONE_delay;
wire [7:0] SAXISCCTKEEP_delay;
wire [7:0] SAXISRQTKEEP_delay;
wire [8:0] CFGINTERRUPTMSITPHSTTAG_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) CFGCURRENTSPEED = CFGCURRENTSPEED_delay;
assign #(out_delay) CFGDPASUBSTATECHANGE = CFGDPASUBSTATECHANGE_delay;
assign #(out_delay) CFGERRCOROUT = CFGERRCOROUT_delay;
assign #(out_delay) CFGERRFATALOUT = CFGERRFATALOUT_delay;
assign #(out_delay) CFGERRNONFATALOUT = CFGERRNONFATALOUT_delay;
assign #(out_delay) CFGEXTFUNCTIONNUMBER = CFGEXTFUNCTIONNUMBER_delay;
assign #(out_delay) CFGEXTREADRECEIVED = CFGEXTREADRECEIVED_delay;
assign #(out_delay) CFGEXTREGISTERNUMBER = CFGEXTREGISTERNUMBER_delay;
assign #(out_delay) CFGEXTWRITEBYTEENABLE = CFGEXTWRITEBYTEENABLE_delay;
assign #(out_delay) CFGEXTWRITEDATA = CFGEXTWRITEDATA_delay;
assign #(out_delay) CFGEXTWRITERECEIVED = CFGEXTWRITERECEIVED_delay;
assign #(out_delay) CFGFCCPLD = CFGFCCPLD_delay;
assign #(out_delay) CFGFCCPLH = CFGFCCPLH_delay;
assign #(out_delay) CFGFCNPD = CFGFCNPD_delay;
assign #(out_delay) CFGFCNPH = CFGFCNPH_delay;
assign #(out_delay) CFGFCPD = CFGFCPD_delay;
assign #(out_delay) CFGFCPH = CFGFCPH_delay;
assign #(out_delay) CFGFLRINPROCESS = CFGFLRINPROCESS_delay;
assign #(out_delay) CFGFUNCTIONPOWERSTATE = CFGFUNCTIONPOWERSTATE_delay;
assign #(out_delay) CFGFUNCTIONSTATUS = CFGFUNCTIONSTATUS_delay;
assign #(out_delay) CFGHOTRESETOUT = CFGHOTRESETOUT_delay;
assign #(out_delay) CFGINTERRUPTMSIDATA = CFGINTERRUPTMSIDATA_delay;
assign #(out_delay) CFGINTERRUPTMSIENABLE = CFGINTERRUPTMSIENABLE_delay;
assign #(out_delay) CFGINTERRUPTMSIFAIL = CFGINTERRUPTMSIFAIL_delay;
assign #(out_delay) CFGINTERRUPTMSIMASKUPDATE = CFGINTERRUPTMSIMASKUPDATE_delay;
assign #(out_delay) CFGINTERRUPTMSIMMENABLE = CFGINTERRUPTMSIMMENABLE_delay;
assign #(out_delay) CFGINTERRUPTMSISENT = CFGINTERRUPTMSISENT_delay;
assign #(out_delay) CFGINTERRUPTMSIVFENABLE = CFGINTERRUPTMSIVFENABLE_delay;
assign #(out_delay) CFGINTERRUPTMSIXENABLE = CFGINTERRUPTMSIXENABLE_delay;
assign #(out_delay) CFGINTERRUPTMSIXFAIL = CFGINTERRUPTMSIXFAIL_delay;
assign #(out_delay) CFGINTERRUPTMSIXMASK = CFGINTERRUPTMSIXMASK_delay;
assign #(out_delay) CFGINTERRUPTMSIXSENT = CFGINTERRUPTMSIXSENT_delay;
assign #(out_delay) CFGINTERRUPTMSIXVFENABLE = CFGINTERRUPTMSIXVFENABLE_delay;
assign #(out_delay) CFGINTERRUPTMSIXVFMASK = CFGINTERRUPTMSIXVFMASK_delay;
assign #(out_delay) CFGINTERRUPTSENT = CFGINTERRUPTSENT_delay;
assign #(out_delay) CFGLINKPOWERSTATE = CFGLINKPOWERSTATE_delay;
assign #(out_delay) CFGLOCALERROR = CFGLOCALERROR_delay;
assign #(out_delay) CFGLTRENABLE = CFGLTRENABLE_delay;
assign #(out_delay) CFGLTSSMSTATE = CFGLTSSMSTATE_delay;
assign #(out_delay) CFGMAXPAYLOAD = CFGMAXPAYLOAD_delay;
assign #(out_delay) CFGMAXREADREQ = CFGMAXREADREQ_delay;
assign #(out_delay) CFGMGMTREADDATA = CFGMGMTREADDATA_delay;
assign #(out_delay) CFGMGMTREADWRITEDONE = CFGMGMTREADWRITEDONE_delay;
assign #(out_delay) CFGMSGRECEIVED = CFGMSGRECEIVED_delay;
assign #(out_delay) CFGMSGRECEIVEDDATA = CFGMSGRECEIVEDDATA_delay;
assign #(out_delay) CFGMSGRECEIVEDTYPE = CFGMSGRECEIVEDTYPE_delay;
assign #(out_delay) CFGMSGTRANSMITDONE = CFGMSGTRANSMITDONE_delay;
assign #(out_delay) CFGNEGOTIATEDWIDTH = CFGNEGOTIATEDWIDTH_delay;
assign #(out_delay) CFGOBFFENABLE = CFGOBFFENABLE_delay;
assign #(out_delay) CFGPERFUNCSTATUSDATA = CFGPERFUNCSTATUSDATA_delay;
assign #(out_delay) CFGPERFUNCTIONUPDATEDONE = CFGPERFUNCTIONUPDATEDONE_delay;
assign #(out_delay) CFGPHYLINKDOWN = CFGPHYLINKDOWN_delay;
assign #(out_delay) CFGPHYLINKSTATUS = CFGPHYLINKSTATUS_delay;
assign #(out_delay) CFGPLSTATUSCHANGE = CFGPLSTATUSCHANGE_delay;
assign #(out_delay) CFGPOWERSTATECHANGEINTERRUPT = CFGPOWERSTATECHANGEINTERRUPT_delay;
assign #(out_delay) CFGRCBSTATUS = CFGRCBSTATUS_delay;
assign #(out_delay) CFGTPHFUNCTIONNUM = CFGTPHFUNCTIONNUM_delay;
assign #(out_delay) CFGTPHREQUESTERENABLE = CFGTPHREQUESTERENABLE_delay;
assign #(out_delay) CFGTPHSTMODE = CFGTPHSTMODE_delay;
assign #(out_delay) CFGTPHSTTADDRESS = CFGTPHSTTADDRESS_delay;
assign #(out_delay) CFGTPHSTTREADENABLE = CFGTPHSTTREADENABLE_delay;
assign #(out_delay) CFGTPHSTTWRITEBYTEVALID = CFGTPHSTTWRITEBYTEVALID_delay;
assign #(out_delay) CFGTPHSTTWRITEDATA = CFGTPHSTTWRITEDATA_delay;
assign #(out_delay) CFGTPHSTTWRITEENABLE = CFGTPHSTTWRITEENABLE_delay;
assign #(out_delay) CFGVFFLRINPROCESS = CFGVFFLRINPROCESS_delay;
assign #(out_delay) CFGVFPOWERSTATE = CFGVFPOWERSTATE_delay;
assign #(out_delay) CFGVFSTATUS = CFGVFSTATUS_delay;
assign #(out_delay) CFGVFTPHREQUESTERENABLE = CFGVFTPHREQUESTERENABLE_delay;
assign #(out_delay) CFGVFTPHSTMODE = CFGVFTPHSTMODE_delay;
assign #(out_delay) CONFMCAPDESIGNSWITCH = CONFMCAPDESIGNSWITCH_delay;
assign #(out_delay) CONFMCAPEOS = CONFMCAPEOS_delay;
assign #(out_delay) CONFMCAPINUSEBYPCIE = CONFMCAPINUSEBYPCIE_delay;
assign #(out_delay) CONFREQREADY = CONFREQREADY_delay;
assign #(out_delay) CONFRESPRDATA = CONFRESPRDATA_delay;
assign #(out_delay) CONFRESPVALID = CONFRESPVALID_delay;
assign #(out_delay) DBGDATAOUT = DBGDATAOUT_delay;
assign #(out_delay) DBGMCAPCSB = DBGMCAPCSB_delay;
assign #(out_delay) DBGMCAPDATA = DBGMCAPDATA_delay;
assign #(out_delay) DBGMCAPEOS = DBGMCAPEOS_delay;
assign #(out_delay) DBGMCAPERROR = DBGMCAPERROR_delay;
assign #(out_delay) DBGMCAPMODE = DBGMCAPMODE_delay;
assign #(out_delay) DBGMCAPRDATAVALID = DBGMCAPRDATAVALID_delay;
assign #(out_delay) DBGMCAPRDWRB = DBGMCAPRDWRB_delay;
assign #(out_delay) DBGMCAPRESET = DBGMCAPRESET_delay;
assign #(out_delay) DBGPLDATABLOCKRECEIVEDAFTEREDS = DBGPLDATABLOCKRECEIVEDAFTEREDS_delay;
assign #(out_delay) DBGPLGEN3FRAMINGERRORDETECTED = DBGPLGEN3FRAMINGERRORDETECTED_delay;
assign #(out_delay) DBGPLGEN3SYNCHEADERERRORDETECTED = DBGPLGEN3SYNCHEADERERRORDETECTED_delay;
assign #(out_delay) DBGPLINFERREDRXELECTRICALIDLE = DBGPLINFERREDRXELECTRICALIDLE_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) LL2LMMASTERTLPSENT0 = LL2LMMASTERTLPSENT0_delay;
assign #(out_delay) LL2LMMASTERTLPSENT1 = LL2LMMASTERTLPSENT1_delay;
assign #(out_delay) LL2LMMASTERTLPSENTTLPID0 = LL2LMMASTERTLPSENTTLPID0_delay;
assign #(out_delay) LL2LMMASTERTLPSENTTLPID1 = LL2LMMASTERTLPSENTTLPID1_delay;
assign #(out_delay) LL2LMMAXISRXTDATA = LL2LMMAXISRXTDATA_delay;
assign #(out_delay) LL2LMMAXISRXTUSER = LL2LMMAXISRXTUSER_delay;
assign #(out_delay) LL2LMMAXISRXTVALID = LL2LMMAXISRXTVALID_delay;
assign #(out_delay) LL2LMSAXISTXTREADY = LL2LMSAXISTXTREADY_delay;
assign #(out_delay) MAXISCQTDATA = MAXISCQTDATA_delay;
assign #(out_delay) MAXISCQTKEEP = MAXISCQTKEEP_delay;
assign #(out_delay) MAXISCQTLAST = MAXISCQTLAST_delay;
assign #(out_delay) MAXISCQTUSER = MAXISCQTUSER_delay;
assign #(out_delay) MAXISCQTVALID = MAXISCQTVALID_delay;
assign #(out_delay) MAXISRCTDATA = MAXISRCTDATA_delay;
assign #(out_delay) MAXISRCTKEEP = MAXISRCTKEEP_delay;
assign #(out_delay) MAXISRCTLAST = MAXISRCTLAST_delay;
assign #(out_delay) MAXISRCTUSER = MAXISRCTUSER_delay;
assign #(out_delay) MAXISRCTVALID = MAXISRCTVALID_delay;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAL = MICOMPLETIONRAMREADADDRESSAL_delay;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAU = MICOMPLETIONRAMREADADDRESSAU_delay;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBL = MICOMPLETIONRAMREADADDRESSBL_delay;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBU = MICOMPLETIONRAMREADADDRESSBU_delay;
assign #(out_delay) MICOMPLETIONRAMREADENABLEL = MICOMPLETIONRAMREADENABLEL_delay;
assign #(out_delay) MICOMPLETIONRAMREADENABLEU = MICOMPLETIONRAMREADENABLEU_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAL = MICOMPLETIONRAMWRITEADDRESSAL_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAU = MICOMPLETIONRAMWRITEADDRESSAU_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBL = MICOMPLETIONRAMWRITEADDRESSBL_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBU = MICOMPLETIONRAMWRITEADDRESSBU_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAL = MICOMPLETIONRAMWRITEDATAL_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAU = MICOMPLETIONRAMWRITEDATAU_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEL = MICOMPLETIONRAMWRITEENABLEL_delay;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEU = MICOMPLETIONRAMWRITEENABLEU_delay;
assign #(out_delay) MIREPLAYRAMADDRESS = MIREPLAYRAMADDRESS_delay;
assign #(out_delay) MIREPLAYRAMREADENABLE = MIREPLAYRAMREADENABLE_delay;
assign #(out_delay) MIREPLAYRAMWRITEDATA = MIREPLAYRAMWRITEDATA_delay;
assign #(out_delay) MIREPLAYRAMWRITEENABLE = MIREPLAYRAMWRITEENABLE_delay;
assign #(out_delay) MIREQUESTRAMREADADDRESSA = MIREQUESTRAMREADADDRESSA_delay;
assign #(out_delay) MIREQUESTRAMREADADDRESSB = MIREQUESTRAMREADADDRESSB_delay;
assign #(out_delay) MIREQUESTRAMREADENABLE = MIREQUESTRAMREADENABLE_delay;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSA = MIREQUESTRAMWRITEADDRESSA_delay;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSB = MIREQUESTRAMWRITEADDRESSB_delay;
assign #(out_delay) MIREQUESTRAMWRITEDATA = MIREQUESTRAMWRITEDATA_delay;
assign #(out_delay) MIREQUESTRAMWRITEENABLE = MIREQUESTRAMWRITEENABLE_delay;
assign #(out_delay) PCIECQNPREQCOUNT = PCIECQNPREQCOUNT_delay;
assign #(out_delay) PCIEPERST0B = PCIEPERST0B_delay;
assign #(out_delay) PCIEPERST1B = PCIEPERST1B_delay;
assign #(out_delay) PCIERQSEQNUM = PCIERQSEQNUM_delay;
assign #(out_delay) PCIERQSEQNUMVLD = PCIERQSEQNUMVLD_delay;
assign #(out_delay) PCIERQTAG = PCIERQTAG_delay;
assign #(out_delay) PCIERQTAGAV = PCIERQTAGAV_delay;
assign #(out_delay) PCIERQTAGVLD = PCIERQTAGVLD_delay;
assign #(out_delay) PCIETFCNPDAV = PCIETFCNPDAV_delay;
assign #(out_delay) PCIETFCNPHAV = PCIETFCNPHAV_delay;
assign #(out_delay) PIPERX0EQCONTROL = PIPERX0EQCONTROL_delay;
assign #(out_delay) PIPERX0EQLPLFFS = PIPERX0EQLPLFFS_delay;
assign #(out_delay) PIPERX0EQLPTXPRESET = PIPERX0EQLPTXPRESET_delay;
assign #(out_delay) PIPERX0EQPRESET = PIPERX0EQPRESET_delay;
assign #(out_delay) PIPERX0POLARITY = PIPERX0POLARITY_delay;
assign #(out_delay) PIPERX1EQCONTROL = PIPERX1EQCONTROL_delay;
assign #(out_delay) PIPERX1EQLPLFFS = PIPERX1EQLPLFFS_delay;
assign #(out_delay) PIPERX1EQLPTXPRESET = PIPERX1EQLPTXPRESET_delay;
assign #(out_delay) PIPERX1EQPRESET = PIPERX1EQPRESET_delay;
assign #(out_delay) PIPERX1POLARITY = PIPERX1POLARITY_delay;
assign #(out_delay) PIPERX2EQCONTROL = PIPERX2EQCONTROL_delay;
assign #(out_delay) PIPERX2EQLPLFFS = PIPERX2EQLPLFFS_delay;
assign #(out_delay) PIPERX2EQLPTXPRESET = PIPERX2EQLPTXPRESET_delay;
assign #(out_delay) PIPERX2EQPRESET = PIPERX2EQPRESET_delay;
assign #(out_delay) PIPERX2POLARITY = PIPERX2POLARITY_delay;
assign #(out_delay) PIPERX3EQCONTROL = PIPERX3EQCONTROL_delay;
assign #(out_delay) PIPERX3EQLPLFFS = PIPERX3EQLPLFFS_delay;
assign #(out_delay) PIPERX3EQLPTXPRESET = PIPERX3EQLPTXPRESET_delay;
assign #(out_delay) PIPERX3EQPRESET = PIPERX3EQPRESET_delay;
assign #(out_delay) PIPERX3POLARITY = PIPERX3POLARITY_delay;
assign #(out_delay) PIPERX4EQCONTROL = PIPERX4EQCONTROL_delay;
assign #(out_delay) PIPERX4EQLPLFFS = PIPERX4EQLPLFFS_delay;
assign #(out_delay) PIPERX4EQLPTXPRESET = PIPERX4EQLPTXPRESET_delay;
assign #(out_delay) PIPERX4EQPRESET = PIPERX4EQPRESET_delay;
assign #(out_delay) PIPERX4POLARITY = PIPERX4POLARITY_delay;
assign #(out_delay) PIPERX5EQCONTROL = PIPERX5EQCONTROL_delay;
assign #(out_delay) PIPERX5EQLPLFFS = PIPERX5EQLPLFFS_delay;
assign #(out_delay) PIPERX5EQLPTXPRESET = PIPERX5EQLPTXPRESET_delay;
assign #(out_delay) PIPERX5EQPRESET = PIPERX5EQPRESET_delay;
assign #(out_delay) PIPERX5POLARITY = PIPERX5POLARITY_delay;
assign #(out_delay) PIPERX6EQCONTROL = PIPERX6EQCONTROL_delay;
assign #(out_delay) PIPERX6EQLPLFFS = PIPERX6EQLPLFFS_delay;
assign #(out_delay) PIPERX6EQLPTXPRESET = PIPERX6EQLPTXPRESET_delay;
assign #(out_delay) PIPERX6EQPRESET = PIPERX6EQPRESET_delay;
assign #(out_delay) PIPERX6POLARITY = PIPERX6POLARITY_delay;
assign #(out_delay) PIPERX7EQCONTROL = PIPERX7EQCONTROL_delay;
assign #(out_delay) PIPERX7EQLPLFFS = PIPERX7EQLPLFFS_delay;
assign #(out_delay) PIPERX7EQLPTXPRESET = PIPERX7EQLPTXPRESET_delay;
assign #(out_delay) PIPERX7EQPRESET = PIPERX7EQPRESET_delay;
assign #(out_delay) PIPERX7POLARITY = PIPERX7POLARITY_delay;
assign #(out_delay) PIPETX0CHARISK = PIPETX0CHARISK_delay;
assign #(out_delay) PIPETX0COMPLIANCE = PIPETX0COMPLIANCE_delay;
assign #(out_delay) PIPETX0DATA = PIPETX0DATA_delay;
assign #(out_delay) PIPETX0DATAVALID = PIPETX0DATAVALID_delay;
assign #(out_delay) PIPETX0DEEMPH = PIPETX0DEEMPH_delay;
assign #(out_delay) PIPETX0ELECIDLE = PIPETX0ELECIDLE_delay;
assign #(out_delay) PIPETX0EQCONTROL = PIPETX0EQCONTROL_delay;
assign #(out_delay) PIPETX0EQDEEMPH = PIPETX0EQDEEMPH_delay;
assign #(out_delay) PIPETX0EQPRESET = PIPETX0EQPRESET_delay;
assign #(out_delay) PIPETX0MARGIN = PIPETX0MARGIN_delay;
assign #(out_delay) PIPETX0POWERDOWN = PIPETX0POWERDOWN_delay;
assign #(out_delay) PIPETX0RATE = PIPETX0RATE_delay;
assign #(out_delay) PIPETX0RCVRDET = PIPETX0RCVRDET_delay;
assign #(out_delay) PIPETX0RESET = PIPETX0RESET_delay;
assign #(out_delay) PIPETX0STARTBLOCK = PIPETX0STARTBLOCK_delay;
assign #(out_delay) PIPETX0SWING = PIPETX0SWING_delay;
assign #(out_delay) PIPETX0SYNCHEADER = PIPETX0SYNCHEADER_delay;
assign #(out_delay) PIPETX1CHARISK = PIPETX1CHARISK_delay;
assign #(out_delay) PIPETX1COMPLIANCE = PIPETX1COMPLIANCE_delay;
assign #(out_delay) PIPETX1DATA = PIPETX1DATA_delay;
assign #(out_delay) PIPETX1DATAVALID = PIPETX1DATAVALID_delay;
assign #(out_delay) PIPETX1DEEMPH = PIPETX1DEEMPH_delay;
assign #(out_delay) PIPETX1ELECIDLE = PIPETX1ELECIDLE_delay;
assign #(out_delay) PIPETX1EQCONTROL = PIPETX1EQCONTROL_delay;
assign #(out_delay) PIPETX1EQDEEMPH = PIPETX1EQDEEMPH_delay;
assign #(out_delay) PIPETX1EQPRESET = PIPETX1EQPRESET_delay;
assign #(out_delay) PIPETX1MARGIN = PIPETX1MARGIN_delay;
assign #(out_delay) PIPETX1POWERDOWN = PIPETX1POWERDOWN_delay;
assign #(out_delay) PIPETX1RATE = PIPETX1RATE_delay;
assign #(out_delay) PIPETX1RCVRDET = PIPETX1RCVRDET_delay;
assign #(out_delay) PIPETX1RESET = PIPETX1RESET_delay;
assign #(out_delay) PIPETX1STARTBLOCK = PIPETX1STARTBLOCK_delay;
assign #(out_delay) PIPETX1SWING = PIPETX1SWING_delay;
assign #(out_delay) PIPETX1SYNCHEADER = PIPETX1SYNCHEADER_delay;
assign #(out_delay) PIPETX2CHARISK = PIPETX2CHARISK_delay;
assign #(out_delay) PIPETX2COMPLIANCE = PIPETX2COMPLIANCE_delay;
assign #(out_delay) PIPETX2DATA = PIPETX2DATA_delay;
assign #(out_delay) PIPETX2DATAVALID = PIPETX2DATAVALID_delay;
assign #(out_delay) PIPETX2DEEMPH = PIPETX2DEEMPH_delay;
assign #(out_delay) PIPETX2ELECIDLE = PIPETX2ELECIDLE_delay;
assign #(out_delay) PIPETX2EQCONTROL = PIPETX2EQCONTROL_delay;
assign #(out_delay) PIPETX2EQDEEMPH = PIPETX2EQDEEMPH_delay;
assign #(out_delay) PIPETX2EQPRESET = PIPETX2EQPRESET_delay;
assign #(out_delay) PIPETX2MARGIN = PIPETX2MARGIN_delay;
assign #(out_delay) PIPETX2POWERDOWN = PIPETX2POWERDOWN_delay;
assign #(out_delay) PIPETX2RATE = PIPETX2RATE_delay;
assign #(out_delay) PIPETX2RCVRDET = PIPETX2RCVRDET_delay;
assign #(out_delay) PIPETX2RESET = PIPETX2RESET_delay;
assign #(out_delay) PIPETX2STARTBLOCK = PIPETX2STARTBLOCK_delay;
assign #(out_delay) PIPETX2SWING = PIPETX2SWING_delay;
assign #(out_delay) PIPETX2SYNCHEADER = PIPETX2SYNCHEADER_delay;
assign #(out_delay) PIPETX3CHARISK = PIPETX3CHARISK_delay;
assign #(out_delay) PIPETX3COMPLIANCE = PIPETX3COMPLIANCE_delay;
assign #(out_delay) PIPETX3DATA = PIPETX3DATA_delay;
assign #(out_delay) PIPETX3DATAVALID = PIPETX3DATAVALID_delay;
assign #(out_delay) PIPETX3DEEMPH = PIPETX3DEEMPH_delay;
assign #(out_delay) PIPETX3ELECIDLE = PIPETX3ELECIDLE_delay;
assign #(out_delay) PIPETX3EQCONTROL = PIPETX3EQCONTROL_delay;
assign #(out_delay) PIPETX3EQDEEMPH = PIPETX3EQDEEMPH_delay;
assign #(out_delay) PIPETX3EQPRESET = PIPETX3EQPRESET_delay;
assign #(out_delay) PIPETX3MARGIN = PIPETX3MARGIN_delay;
assign #(out_delay) PIPETX3POWERDOWN = PIPETX3POWERDOWN_delay;
assign #(out_delay) PIPETX3RATE = PIPETX3RATE_delay;
assign #(out_delay) PIPETX3RCVRDET = PIPETX3RCVRDET_delay;
assign #(out_delay) PIPETX3RESET = PIPETX3RESET_delay;
assign #(out_delay) PIPETX3STARTBLOCK = PIPETX3STARTBLOCK_delay;
assign #(out_delay) PIPETX3SWING = PIPETX3SWING_delay;
assign #(out_delay) PIPETX3SYNCHEADER = PIPETX3SYNCHEADER_delay;
assign #(out_delay) PIPETX4CHARISK = PIPETX4CHARISK_delay;
assign #(out_delay) PIPETX4COMPLIANCE = PIPETX4COMPLIANCE_delay;
assign #(out_delay) PIPETX4DATA = PIPETX4DATA_delay;
assign #(out_delay) PIPETX4DATAVALID = PIPETX4DATAVALID_delay;
assign #(out_delay) PIPETX4DEEMPH = PIPETX4DEEMPH_delay;
assign #(out_delay) PIPETX4ELECIDLE = PIPETX4ELECIDLE_delay;
assign #(out_delay) PIPETX4EQCONTROL = PIPETX4EQCONTROL_delay;
assign #(out_delay) PIPETX4EQDEEMPH = PIPETX4EQDEEMPH_delay;
assign #(out_delay) PIPETX4EQPRESET = PIPETX4EQPRESET_delay;
assign #(out_delay) PIPETX4MARGIN = PIPETX4MARGIN_delay;
assign #(out_delay) PIPETX4POWERDOWN = PIPETX4POWERDOWN_delay;
assign #(out_delay) PIPETX4RATE = PIPETX4RATE_delay;
assign #(out_delay) PIPETX4RCVRDET = PIPETX4RCVRDET_delay;
assign #(out_delay) PIPETX4RESET = PIPETX4RESET_delay;
assign #(out_delay) PIPETX4STARTBLOCK = PIPETX4STARTBLOCK_delay;
assign #(out_delay) PIPETX4SWING = PIPETX4SWING_delay;
assign #(out_delay) PIPETX4SYNCHEADER = PIPETX4SYNCHEADER_delay;
assign #(out_delay) PIPETX5CHARISK = PIPETX5CHARISK_delay;
assign #(out_delay) PIPETX5COMPLIANCE = PIPETX5COMPLIANCE_delay;
assign #(out_delay) PIPETX5DATA = PIPETX5DATA_delay;
assign #(out_delay) PIPETX5DATAVALID = PIPETX5DATAVALID_delay;
assign #(out_delay) PIPETX5DEEMPH = PIPETX5DEEMPH_delay;
assign #(out_delay) PIPETX5ELECIDLE = PIPETX5ELECIDLE_delay;
assign #(out_delay) PIPETX5EQCONTROL = PIPETX5EQCONTROL_delay;
assign #(out_delay) PIPETX5EQDEEMPH = PIPETX5EQDEEMPH_delay;
assign #(out_delay) PIPETX5EQPRESET = PIPETX5EQPRESET_delay;
assign #(out_delay) PIPETX5MARGIN = PIPETX5MARGIN_delay;
assign #(out_delay) PIPETX5POWERDOWN = PIPETX5POWERDOWN_delay;
assign #(out_delay) PIPETX5RATE = PIPETX5RATE_delay;
assign #(out_delay) PIPETX5RCVRDET = PIPETX5RCVRDET_delay;
assign #(out_delay) PIPETX5RESET = PIPETX5RESET_delay;
assign #(out_delay) PIPETX5STARTBLOCK = PIPETX5STARTBLOCK_delay;
assign #(out_delay) PIPETX5SWING = PIPETX5SWING_delay;
assign #(out_delay) PIPETX5SYNCHEADER = PIPETX5SYNCHEADER_delay;
assign #(out_delay) PIPETX6CHARISK = PIPETX6CHARISK_delay;
assign #(out_delay) PIPETX6COMPLIANCE = PIPETX6COMPLIANCE_delay;
assign #(out_delay) PIPETX6DATA = PIPETX6DATA_delay;
assign #(out_delay) PIPETX6DATAVALID = PIPETX6DATAVALID_delay;
assign #(out_delay) PIPETX6DEEMPH = PIPETX6DEEMPH_delay;
assign #(out_delay) PIPETX6ELECIDLE = PIPETX6ELECIDLE_delay;
assign #(out_delay) PIPETX6EQCONTROL = PIPETX6EQCONTROL_delay;
assign #(out_delay) PIPETX6EQDEEMPH = PIPETX6EQDEEMPH_delay;
assign #(out_delay) PIPETX6EQPRESET = PIPETX6EQPRESET_delay;
assign #(out_delay) PIPETX6MARGIN = PIPETX6MARGIN_delay;
assign #(out_delay) PIPETX6POWERDOWN = PIPETX6POWERDOWN_delay;
assign #(out_delay) PIPETX6RATE = PIPETX6RATE_delay;
assign #(out_delay) PIPETX6RCVRDET = PIPETX6RCVRDET_delay;
assign #(out_delay) PIPETX6RESET = PIPETX6RESET_delay;
assign #(out_delay) PIPETX6STARTBLOCK = PIPETX6STARTBLOCK_delay;
assign #(out_delay) PIPETX6SWING = PIPETX6SWING_delay;
assign #(out_delay) PIPETX6SYNCHEADER = PIPETX6SYNCHEADER_delay;
assign #(out_delay) PIPETX7CHARISK = PIPETX7CHARISK_delay;
assign #(out_delay) PIPETX7COMPLIANCE = PIPETX7COMPLIANCE_delay;
assign #(out_delay) PIPETX7DATA = PIPETX7DATA_delay;
assign #(out_delay) PIPETX7DATAVALID = PIPETX7DATAVALID_delay;
assign #(out_delay) PIPETX7DEEMPH = PIPETX7DEEMPH_delay;
assign #(out_delay) PIPETX7ELECIDLE = PIPETX7ELECIDLE_delay;
assign #(out_delay) PIPETX7EQCONTROL = PIPETX7EQCONTROL_delay;
assign #(out_delay) PIPETX7EQDEEMPH = PIPETX7EQDEEMPH_delay;
assign #(out_delay) PIPETX7EQPRESET = PIPETX7EQPRESET_delay;
assign #(out_delay) PIPETX7MARGIN = PIPETX7MARGIN_delay;
assign #(out_delay) PIPETX7POWERDOWN = PIPETX7POWERDOWN_delay;
assign #(out_delay) PIPETX7RATE = PIPETX7RATE_delay;
assign #(out_delay) PIPETX7RCVRDET = PIPETX7RCVRDET_delay;
assign #(out_delay) PIPETX7RESET = PIPETX7RESET_delay;
assign #(out_delay) PIPETX7STARTBLOCK = PIPETX7STARTBLOCK_delay;
assign #(out_delay) PIPETX7SWING = PIPETX7SWING_delay;
assign #(out_delay) PIPETX7SYNCHEADER = PIPETX7SYNCHEADER_delay;
assign #(out_delay) PLEQINPROGRESS = PLEQINPROGRESS_delay;
assign #(out_delay) PLEQPHASE = PLEQPHASE_delay;
assign #(out_delay) SAXISCCTREADY = SAXISCCTREADY_delay;
assign #(out_delay) SAXISRQTREADY = SAXISRQTREADY_delay;
assign #(out_delay) SPAREOUT = SPAREOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CORECLK_delay = CORECLK;
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) PIPECLK_delay = PIPECLK;
assign #(inclk_delay) USERCLK_delay = USERCLK;
assign #(in_delay) CFGCONFIGSPACEENABLE_delay = CFGCONFIGSPACEENABLE;
assign #(in_delay) CFGDEVID_delay = CFGDEVID;
assign #(in_delay) CFGDSBUSNUMBER_delay = CFGDSBUSNUMBER;
assign #(in_delay) CFGDSDEVICENUMBER_delay = CFGDSDEVICENUMBER;
assign #(in_delay) CFGDSFUNCTIONNUMBER_delay = CFGDSFUNCTIONNUMBER;
assign #(in_delay) CFGDSN_delay = CFGDSN;
assign #(in_delay) CFGDSPORTNUMBER_delay = CFGDSPORTNUMBER;
assign #(in_delay) CFGERRCORIN_delay = CFGERRCORIN;
assign #(in_delay) CFGERRUNCORIN_delay = CFGERRUNCORIN;
assign #(in_delay) CFGEXTREADDATAVALID_delay = CFGEXTREADDATAVALID;
assign #(in_delay) CFGEXTREADDATA_delay = CFGEXTREADDATA;
assign #(in_delay) CFGFCSEL_delay = CFGFCSEL;
assign #(in_delay) CFGFLRDONE_delay = CFGFLRDONE;
assign #(in_delay) CFGHOTRESETIN_delay = CFGHOTRESETIN;
assign #(in_delay) CFGINTERRUPTINT_delay = CFGINTERRUPTINT;
assign #(in_delay) CFGINTERRUPTMSIATTR_delay = CFGINTERRUPTMSIATTR;
assign #(in_delay) CFGINTERRUPTMSIFUNCTIONNUMBER_delay = CFGINTERRUPTMSIFUNCTIONNUMBER;
assign #(in_delay) CFGINTERRUPTMSIINT_delay = CFGINTERRUPTMSIINT;
assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay = CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay = CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
assign #(in_delay) CFGINTERRUPTMSIPENDINGSTATUS_delay = CFGINTERRUPTMSIPENDINGSTATUS;
assign #(in_delay) CFGINTERRUPTMSISELECT_delay = CFGINTERRUPTMSISELECT;
assign #(in_delay) CFGINTERRUPTMSITPHPRESENT_delay = CFGINTERRUPTMSITPHPRESENT;
assign #(in_delay) CFGINTERRUPTMSITPHSTTAG_delay = CFGINTERRUPTMSITPHSTTAG;
assign #(in_delay) CFGINTERRUPTMSITPHTYPE_delay = CFGINTERRUPTMSITPHTYPE;
assign #(in_delay) CFGINTERRUPTMSIXADDRESS_delay = CFGINTERRUPTMSIXADDRESS;
assign #(in_delay) CFGINTERRUPTMSIXDATA_delay = CFGINTERRUPTMSIXDATA;
assign #(in_delay) CFGINTERRUPTMSIXINT_delay = CFGINTERRUPTMSIXINT;
assign #(in_delay) CFGINTERRUPTPENDING_delay = CFGINTERRUPTPENDING;
assign #(in_delay) CFGLINKTRAININGENABLE_delay = CFGLINKTRAININGENABLE;
assign #(in_delay) CFGMGMTADDR_delay = CFGMGMTADDR;
assign #(in_delay) CFGMGMTBYTEENABLE_delay = CFGMGMTBYTEENABLE;
assign #(in_delay) CFGMGMTREAD_delay = CFGMGMTREAD;
assign #(in_delay) CFGMGMTTYPE1CFGREGACCESS_delay = CFGMGMTTYPE1CFGREGACCESS;
assign #(in_delay) CFGMGMTWRITEDATA_delay = CFGMGMTWRITEDATA;
assign #(in_delay) CFGMGMTWRITE_delay = CFGMGMTWRITE;
assign #(in_delay) CFGMSGTRANSMITDATA_delay = CFGMSGTRANSMITDATA;
assign #(in_delay) CFGMSGTRANSMITTYPE_delay = CFGMSGTRANSMITTYPE;
assign #(in_delay) CFGMSGTRANSMIT_delay = CFGMSGTRANSMIT;
assign #(in_delay) CFGPERFUNCSTATUSCONTROL_delay = CFGPERFUNCSTATUSCONTROL;
assign #(in_delay) CFGPERFUNCTIONNUMBER_delay = CFGPERFUNCTIONNUMBER;
assign #(in_delay) CFGPERFUNCTIONOUTPUTREQUEST_delay = CFGPERFUNCTIONOUTPUTREQUEST;
assign #(in_delay) CFGPOWERSTATECHANGEACK_delay = CFGPOWERSTATECHANGEACK;
assign #(in_delay) CFGREQPMTRANSITIONL23READY_delay = CFGREQPMTRANSITIONL23READY;
assign #(in_delay) CFGREVID_delay = CFGREVID;
assign #(in_delay) CFGSUBSYSID_delay = CFGSUBSYSID;
assign #(in_delay) CFGSUBSYSVENDID_delay = CFGSUBSYSVENDID;
assign #(in_delay) CFGTPHSTTREADDATAVALID_delay = CFGTPHSTTREADDATAVALID;
assign #(in_delay) CFGTPHSTTREADDATA_delay = CFGTPHSTTREADDATA;
assign #(in_delay) CFGVENDID_delay = CFGVENDID;
assign #(in_delay) CFGVFFLRDONE_delay = CFGVFFLRDONE;
assign #(in_delay) CONFMCAPREQUESTBYCONF_delay = CONFMCAPREQUESTBYCONF;
assign #(in_delay) CONFREQDATA_delay = CONFREQDATA;
assign #(in_delay) CONFREQREGNUM_delay = CONFREQREGNUM;
assign #(in_delay) CONFREQTYPE_delay = CONFREQTYPE;
assign #(in_delay) CONFREQVALID_delay = CONFREQVALID;
assign #(in_delay) DBGCFGLOCALMGMTREGOVERRIDE_delay = DBGCFGLOCALMGMTREGOVERRIDE;
assign #(in_delay) DBGDATASEL_delay = DBGDATASEL;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) LL2LMSAXISTXTUSER_delay = LL2LMSAXISTXTUSER;
assign #(in_delay) LL2LMSAXISTXTVALID_delay = LL2LMSAXISTXTVALID;
assign #(in_delay) LL2LMTXTLPID0_delay = LL2LMTXTLPID0;
assign #(in_delay) LL2LMTXTLPID1_delay = LL2LMTXTLPID1;
assign #(in_delay) MAXISCQTREADY_delay = MAXISCQTREADY;
assign #(in_delay) MAXISRCTREADY_delay = MAXISRCTREADY;
assign #(in_delay) MICOMPLETIONRAMREADDATA_delay = MICOMPLETIONRAMREADDATA;
assign #(in_delay) MIREPLAYRAMREADDATA_delay = MIREPLAYRAMREADDATA;
assign #(in_delay) MIREQUESTRAMREADDATA_delay = MIREQUESTRAMREADDATA;
assign #(in_delay) PCIECQNPREQ_delay = PCIECQNPREQ;
assign #(in_delay) PIPEEQFS_delay = PIPEEQFS;
assign #(in_delay) PIPEEQLF_delay = PIPEEQLF;
assign #(in_delay) PIPERX0CHARISK_delay = PIPERX0CHARISK;
assign #(in_delay) PIPERX0DATAVALID_delay = PIPERX0DATAVALID;
assign #(in_delay) PIPERX0DATA_delay = PIPERX0DATA;
assign #(in_delay) PIPERX0ELECIDLE_delay = PIPERX0ELECIDLE;
assign #(in_delay) PIPERX0EQDONE_delay = PIPERX0EQDONE;
assign #(in_delay) PIPERX0EQLPADAPTDONE_delay = PIPERX0EQLPADAPTDONE;
assign #(in_delay) PIPERX0EQLPLFFSSEL_delay = PIPERX0EQLPLFFSSEL;
assign #(in_delay) PIPERX0EQLPNEWTXCOEFFORPRESET_delay = PIPERX0EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX0PHYSTATUS_delay = PIPERX0PHYSTATUS;
assign #(in_delay) PIPERX0STARTBLOCK_delay = PIPERX0STARTBLOCK;
assign #(in_delay) PIPERX0STATUS_delay = PIPERX0STATUS;
assign #(in_delay) PIPERX0SYNCHEADER_delay = PIPERX0SYNCHEADER;
assign #(in_delay) PIPERX0VALID_delay = PIPERX0VALID;
assign #(in_delay) PIPERX1CHARISK_delay = PIPERX1CHARISK;
assign #(in_delay) PIPERX1DATAVALID_delay = PIPERX1DATAVALID;
assign #(in_delay) PIPERX1DATA_delay = PIPERX1DATA;
assign #(in_delay) PIPERX1ELECIDLE_delay = PIPERX1ELECIDLE;
assign #(in_delay) PIPERX1EQDONE_delay = PIPERX1EQDONE;
assign #(in_delay) PIPERX1EQLPADAPTDONE_delay = PIPERX1EQLPADAPTDONE;
assign #(in_delay) PIPERX1EQLPLFFSSEL_delay = PIPERX1EQLPLFFSSEL;
assign #(in_delay) PIPERX1EQLPNEWTXCOEFFORPRESET_delay = PIPERX1EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX1PHYSTATUS_delay = PIPERX1PHYSTATUS;
assign #(in_delay) PIPERX1STARTBLOCK_delay = PIPERX1STARTBLOCK;
assign #(in_delay) PIPERX1STATUS_delay = PIPERX1STATUS;
assign #(in_delay) PIPERX1SYNCHEADER_delay = PIPERX1SYNCHEADER;
assign #(in_delay) PIPERX1VALID_delay = PIPERX1VALID;
assign #(in_delay) PIPERX2CHARISK_delay = PIPERX2CHARISK;
assign #(in_delay) PIPERX2DATAVALID_delay = PIPERX2DATAVALID;
assign #(in_delay) PIPERX2DATA_delay = PIPERX2DATA;
assign #(in_delay) PIPERX2ELECIDLE_delay = PIPERX2ELECIDLE;
assign #(in_delay) PIPERX2EQDONE_delay = PIPERX2EQDONE;
assign #(in_delay) PIPERX2EQLPADAPTDONE_delay = PIPERX2EQLPADAPTDONE;
assign #(in_delay) PIPERX2EQLPLFFSSEL_delay = PIPERX2EQLPLFFSSEL;
assign #(in_delay) PIPERX2EQLPNEWTXCOEFFORPRESET_delay = PIPERX2EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX2PHYSTATUS_delay = PIPERX2PHYSTATUS;
assign #(in_delay) PIPERX2STARTBLOCK_delay = PIPERX2STARTBLOCK;
assign #(in_delay) PIPERX2STATUS_delay = PIPERX2STATUS;
assign #(in_delay) PIPERX2SYNCHEADER_delay = PIPERX2SYNCHEADER;
assign #(in_delay) PIPERX2VALID_delay = PIPERX2VALID;
assign #(in_delay) PIPERX3CHARISK_delay = PIPERX3CHARISK;
assign #(in_delay) PIPERX3DATAVALID_delay = PIPERX3DATAVALID;
assign #(in_delay) PIPERX3DATA_delay = PIPERX3DATA;
assign #(in_delay) PIPERX3ELECIDLE_delay = PIPERX3ELECIDLE;
assign #(in_delay) PIPERX3EQDONE_delay = PIPERX3EQDONE;
assign #(in_delay) PIPERX3EQLPADAPTDONE_delay = PIPERX3EQLPADAPTDONE;
assign #(in_delay) PIPERX3EQLPLFFSSEL_delay = PIPERX3EQLPLFFSSEL;
assign #(in_delay) PIPERX3EQLPNEWTXCOEFFORPRESET_delay = PIPERX3EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX3PHYSTATUS_delay = PIPERX3PHYSTATUS;
assign #(in_delay) PIPERX3STARTBLOCK_delay = PIPERX3STARTBLOCK;
assign #(in_delay) PIPERX3STATUS_delay = PIPERX3STATUS;
assign #(in_delay) PIPERX3SYNCHEADER_delay = PIPERX3SYNCHEADER;
assign #(in_delay) PIPERX3VALID_delay = PIPERX3VALID;
assign #(in_delay) PIPERX4CHARISK_delay = PIPERX4CHARISK;
assign #(in_delay) PIPERX4DATAVALID_delay = PIPERX4DATAVALID;
assign #(in_delay) PIPERX4DATA_delay = PIPERX4DATA;
assign #(in_delay) PIPERX4ELECIDLE_delay = PIPERX4ELECIDLE;
assign #(in_delay) PIPERX4EQDONE_delay = PIPERX4EQDONE;
assign #(in_delay) PIPERX4EQLPADAPTDONE_delay = PIPERX4EQLPADAPTDONE;
assign #(in_delay) PIPERX4EQLPLFFSSEL_delay = PIPERX4EQLPLFFSSEL;
assign #(in_delay) PIPERX4EQLPNEWTXCOEFFORPRESET_delay = PIPERX4EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX4PHYSTATUS_delay = PIPERX4PHYSTATUS;
assign #(in_delay) PIPERX4STARTBLOCK_delay = PIPERX4STARTBLOCK;
assign #(in_delay) PIPERX4STATUS_delay = PIPERX4STATUS;
assign #(in_delay) PIPERX4SYNCHEADER_delay = PIPERX4SYNCHEADER;
assign #(in_delay) PIPERX4VALID_delay = PIPERX4VALID;
assign #(in_delay) PIPERX5CHARISK_delay = PIPERX5CHARISK;
assign #(in_delay) PIPERX5DATAVALID_delay = PIPERX5DATAVALID;
assign #(in_delay) PIPERX5DATA_delay = PIPERX5DATA;
assign #(in_delay) PIPERX5ELECIDLE_delay = PIPERX5ELECIDLE;
assign #(in_delay) PIPERX5EQDONE_delay = PIPERX5EQDONE;
assign #(in_delay) PIPERX5EQLPADAPTDONE_delay = PIPERX5EQLPADAPTDONE;
assign #(in_delay) PIPERX5EQLPLFFSSEL_delay = PIPERX5EQLPLFFSSEL;
assign #(in_delay) PIPERX5EQLPNEWTXCOEFFORPRESET_delay = PIPERX5EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX5PHYSTATUS_delay = PIPERX5PHYSTATUS;
assign #(in_delay) PIPERX5STARTBLOCK_delay = PIPERX5STARTBLOCK;
assign #(in_delay) PIPERX5STATUS_delay = PIPERX5STATUS;
assign #(in_delay) PIPERX5SYNCHEADER_delay = PIPERX5SYNCHEADER;
assign #(in_delay) PIPERX5VALID_delay = PIPERX5VALID;
assign #(in_delay) PIPERX6CHARISK_delay = PIPERX6CHARISK;
assign #(in_delay) PIPERX6DATAVALID_delay = PIPERX6DATAVALID;
assign #(in_delay) PIPERX6DATA_delay = PIPERX6DATA;
assign #(in_delay) PIPERX6ELECIDLE_delay = PIPERX6ELECIDLE;
assign #(in_delay) PIPERX6EQDONE_delay = PIPERX6EQDONE;
assign #(in_delay) PIPERX6EQLPADAPTDONE_delay = PIPERX6EQLPADAPTDONE;
assign #(in_delay) PIPERX6EQLPLFFSSEL_delay = PIPERX6EQLPLFFSSEL;
assign #(in_delay) PIPERX6EQLPNEWTXCOEFFORPRESET_delay = PIPERX6EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX6PHYSTATUS_delay = PIPERX6PHYSTATUS;
assign #(in_delay) PIPERX6STARTBLOCK_delay = PIPERX6STARTBLOCK;
assign #(in_delay) PIPERX6STATUS_delay = PIPERX6STATUS;
assign #(in_delay) PIPERX6SYNCHEADER_delay = PIPERX6SYNCHEADER;
assign #(in_delay) PIPERX6VALID_delay = PIPERX6VALID;
assign #(in_delay) PIPERX7CHARISK_delay = PIPERX7CHARISK;
assign #(in_delay) PIPERX7DATAVALID_delay = PIPERX7DATAVALID;
assign #(in_delay) PIPERX7DATA_delay = PIPERX7DATA;
assign #(in_delay) PIPERX7ELECIDLE_delay = PIPERX7ELECIDLE;
assign #(in_delay) PIPERX7EQDONE_delay = PIPERX7EQDONE;
assign #(in_delay) PIPERX7EQLPADAPTDONE_delay = PIPERX7EQLPADAPTDONE;
assign #(in_delay) PIPERX7EQLPLFFSSEL_delay = PIPERX7EQLPLFFSSEL;
assign #(in_delay) PIPERX7EQLPNEWTXCOEFFORPRESET_delay = PIPERX7EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) PIPERX7PHYSTATUS_delay = PIPERX7PHYSTATUS;
assign #(in_delay) PIPERX7STARTBLOCK_delay = PIPERX7STARTBLOCK;
assign #(in_delay) PIPERX7STATUS_delay = PIPERX7STATUS;
assign #(in_delay) PIPERX7SYNCHEADER_delay = PIPERX7SYNCHEADER;
assign #(in_delay) PIPERX7VALID_delay = PIPERX7VALID;
assign #(in_delay) PIPETX0EQCOEFF_delay = PIPETX0EQCOEFF;
assign #(in_delay) PIPETX0EQDONE_delay = PIPETX0EQDONE;
assign #(in_delay) PIPETX1EQCOEFF_delay = PIPETX1EQCOEFF;
assign #(in_delay) PIPETX1EQDONE_delay = PIPETX1EQDONE;
assign #(in_delay) PIPETX2EQCOEFF_delay = PIPETX2EQCOEFF;
assign #(in_delay) PIPETX2EQDONE_delay = PIPETX2EQDONE;
assign #(in_delay) PIPETX3EQCOEFF_delay = PIPETX3EQCOEFF;
assign #(in_delay) PIPETX3EQDONE_delay = PIPETX3EQDONE;
assign #(in_delay) PIPETX4EQCOEFF_delay = PIPETX4EQCOEFF;
assign #(in_delay) PIPETX4EQDONE_delay = PIPETX4EQDONE;
assign #(in_delay) PIPETX5EQCOEFF_delay = PIPETX5EQCOEFF;
assign #(in_delay) PIPETX5EQDONE_delay = PIPETX5EQDONE;
assign #(in_delay) PIPETX6EQCOEFF_delay = PIPETX6EQCOEFF;
assign #(in_delay) PIPETX6EQDONE_delay = PIPETX6EQDONE;
assign #(in_delay) PIPETX7EQCOEFF_delay = PIPETX7EQCOEFF;
assign #(in_delay) PIPETX7EQDONE_delay = PIPETX7EQDONE;
assign #(in_delay) PLEQRESETEIEOSCOUNT_delay = PLEQRESETEIEOSCOUNT;
assign #(in_delay) PLGEN2UPSTREAMPREFERDEEMPH_delay = PLGEN2UPSTREAMPREFERDEEMPH;
assign #(in_delay) SAXISCCTDATA_delay = SAXISCCTDATA;
assign #(in_delay) SAXISCCTKEEP_delay = SAXISCCTKEEP;
assign #(in_delay) SAXISCCTLAST_delay = SAXISCCTLAST;
assign #(in_delay) SAXISCCTUSER_delay = SAXISCCTUSER;
assign #(in_delay) SAXISCCTVALID_delay = SAXISCCTVALID;
assign #(in_delay) SAXISRQTDATA_delay = SAXISRQTDATA;
assign #(in_delay) SAXISRQTKEEP_delay = SAXISRQTKEEP;
assign #(in_delay) SAXISRQTLAST_delay = SAXISRQTLAST;
assign #(in_delay) SAXISRQTUSER_delay = SAXISRQTUSER;
assign #(in_delay) SAXISRQTVALID_delay = SAXISRQTVALID;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) CORECLKMICOMPLETIONRAML_delay = CORECLKMICOMPLETIONRAML;
assign #(inclk_delay) CORECLKMICOMPLETIONRAMU_delay = CORECLKMICOMPLETIONRAMU;
assign #(inclk_delay) CORECLKMIREPLAYRAM_delay = CORECLKMIREPLAYRAM;
assign #(inclk_delay) CORECLKMIREQUESTRAM_delay = CORECLKMIREQUESTRAM;
assign #(inclk_delay) MCAPCLK_delay = MCAPCLK;
assign #(in_delay) MGMTRESETN_delay = MGMTRESETN;
assign #(in_delay) MGMTSTICKYRESETN_delay = MGMTSTICKYRESETN;
assign #(in_delay) PIPERESETN_delay = PIPERESETN;
assign #(in_delay) RESETN_delay = RESETN;
assign #(in_delay) SPAREIN_delay = SPAREIN;
assign CFGCURRENTSPEED_delay = CFGCURRENTSPEED_out;
assign CFGDPASUBSTATECHANGE_delay = CFGDPASUBSTATECHANGE_out;
assign CFGERRCOROUT_delay = CFGERRCOROUT_out;
assign CFGERRFATALOUT_delay = CFGERRFATALOUT_out;
assign CFGERRNONFATALOUT_delay = CFGERRNONFATALOUT_out;
assign CFGEXTFUNCTIONNUMBER_delay = CFGEXTFUNCTIONNUMBER_out;
assign CFGEXTREADRECEIVED_delay = CFGEXTREADRECEIVED_out;
assign CFGEXTREGISTERNUMBER_delay = CFGEXTREGISTERNUMBER_out;
assign CFGEXTWRITEBYTEENABLE_delay = CFGEXTWRITEBYTEENABLE_out;
assign CFGEXTWRITEDATA_delay = CFGEXTWRITEDATA_out;
assign CFGEXTWRITERECEIVED_delay = CFGEXTWRITERECEIVED_out;
assign CFGFCCPLD_delay = CFGFCCPLD_out;
assign CFGFCCPLH_delay = CFGFCCPLH_out;
assign CFGFCNPD_delay = CFGFCNPD_out;
assign CFGFCNPH_delay = CFGFCNPH_out;
assign CFGFCPD_delay = CFGFCPD_out;
assign CFGFCPH_delay = CFGFCPH_out;
assign CFGFLRINPROCESS_delay = CFGFLRINPROCESS_out;
assign CFGFUNCTIONPOWERSTATE_delay = CFGFUNCTIONPOWERSTATE_out;
assign CFGFUNCTIONSTATUS_delay = CFGFUNCTIONSTATUS_out;
assign CFGHOTRESETOUT_delay = CFGHOTRESETOUT_out;
assign CFGINTERRUPTMSIDATA_delay = CFGINTERRUPTMSIDATA_out;
assign CFGINTERRUPTMSIENABLE_delay = CFGINTERRUPTMSIENABLE_out;
assign CFGINTERRUPTMSIFAIL_delay = CFGINTERRUPTMSIFAIL_out;
assign CFGINTERRUPTMSIMASKUPDATE_delay = CFGINTERRUPTMSIMASKUPDATE_out;
assign CFGINTERRUPTMSIMMENABLE_delay = CFGINTERRUPTMSIMMENABLE_out;
assign CFGINTERRUPTMSISENT_delay = CFGINTERRUPTMSISENT_out;
assign CFGINTERRUPTMSIVFENABLE_delay = CFGINTERRUPTMSIVFENABLE_out;
assign CFGINTERRUPTMSIXENABLE_delay = CFGINTERRUPTMSIXENABLE_out;
assign CFGINTERRUPTMSIXFAIL_delay = CFGINTERRUPTMSIXFAIL_out;
assign CFGINTERRUPTMSIXMASK_delay = CFGINTERRUPTMSIXMASK_out;
assign CFGINTERRUPTMSIXSENT_delay = CFGINTERRUPTMSIXSENT_out;
assign CFGINTERRUPTMSIXVFENABLE_delay = CFGINTERRUPTMSIXVFENABLE_out;
assign CFGINTERRUPTMSIXVFMASK_delay = CFGINTERRUPTMSIXVFMASK_out;
assign CFGINTERRUPTSENT_delay = CFGINTERRUPTSENT_out;
assign CFGLINKPOWERSTATE_delay = CFGLINKPOWERSTATE_out;
assign CFGLOCALERROR_delay = CFGLOCALERROR_out;
assign CFGLTRENABLE_delay = CFGLTRENABLE_out;
assign CFGLTSSMSTATE_delay = CFGLTSSMSTATE_out;
assign CFGMAXPAYLOAD_delay = CFGMAXPAYLOAD_out;
assign CFGMAXREADREQ_delay = CFGMAXREADREQ_out;
assign CFGMGMTREADDATA_delay = CFGMGMTREADDATA_out;
assign CFGMGMTREADWRITEDONE_delay = CFGMGMTREADWRITEDONE_out;
assign CFGMSGRECEIVEDDATA_delay = CFGMSGRECEIVEDDATA_out;
assign CFGMSGRECEIVEDTYPE_delay = CFGMSGRECEIVEDTYPE_out;
assign CFGMSGRECEIVED_delay = CFGMSGRECEIVED_out;
assign CFGMSGTRANSMITDONE_delay = CFGMSGTRANSMITDONE_out;
assign CFGNEGOTIATEDWIDTH_delay = CFGNEGOTIATEDWIDTH_out;
assign CFGOBFFENABLE_delay = CFGOBFFENABLE_out;
assign CFGPERFUNCSTATUSDATA_delay = CFGPERFUNCSTATUSDATA_out;
assign CFGPERFUNCTIONUPDATEDONE_delay = CFGPERFUNCTIONUPDATEDONE_out;
assign CFGPHYLINKDOWN_delay = CFGPHYLINKDOWN_out;
assign CFGPHYLINKSTATUS_delay = CFGPHYLINKSTATUS_out;
assign CFGPLSTATUSCHANGE_delay = CFGPLSTATUSCHANGE_out;
assign CFGPOWERSTATECHANGEINTERRUPT_delay = CFGPOWERSTATECHANGEINTERRUPT_out;
assign CFGRCBSTATUS_delay = CFGRCBSTATUS_out;
assign CFGTPHFUNCTIONNUM_delay = CFGTPHFUNCTIONNUM_out;
assign CFGTPHREQUESTERENABLE_delay = CFGTPHREQUESTERENABLE_out;
assign CFGTPHSTMODE_delay = CFGTPHSTMODE_out;
assign CFGTPHSTTADDRESS_delay = CFGTPHSTTADDRESS_out;
assign CFGTPHSTTREADENABLE_delay = CFGTPHSTTREADENABLE_out;
assign CFGTPHSTTWRITEBYTEVALID_delay = CFGTPHSTTWRITEBYTEVALID_out;
assign CFGTPHSTTWRITEDATA_delay = CFGTPHSTTWRITEDATA_out;
assign CFGTPHSTTWRITEENABLE_delay = CFGTPHSTTWRITEENABLE_out;
assign CFGVFFLRINPROCESS_delay = CFGVFFLRINPROCESS_out;
assign CFGVFPOWERSTATE_delay = CFGVFPOWERSTATE_out;
assign CFGVFSTATUS_delay = CFGVFSTATUS_out;
assign CFGVFTPHREQUESTERENABLE_delay = CFGVFTPHREQUESTERENABLE_out;
assign CFGVFTPHSTMODE_delay = CFGVFTPHSTMODE_out;
assign CONFMCAPDESIGNSWITCH_delay = CONFMCAPDESIGNSWITCH_out;
assign CONFMCAPEOS_delay = CONFMCAPEOS_out;
assign CONFMCAPINUSEBYPCIE_delay = CONFMCAPINUSEBYPCIE_out;
assign CONFREQREADY_delay = CONFREQREADY_out;
assign CONFRESPRDATA_delay = CONFRESPRDATA_out;
assign CONFRESPVALID_delay = CONFRESPVALID_out;
assign DBGDATAOUT_delay = DBGDATAOUT_out;
assign DBGMCAPCSB_delay = DBGMCAPCSB_out;
assign DBGMCAPDATA_delay = DBGMCAPDATA_out;
assign DBGMCAPEOS_delay = DBGMCAPEOS_out;
assign DBGMCAPERROR_delay = DBGMCAPERROR_out;
assign DBGMCAPMODE_delay = DBGMCAPMODE_out;
assign DBGMCAPRDATAVALID_delay = DBGMCAPRDATAVALID_out;
assign DBGMCAPRDWRB_delay = DBGMCAPRDWRB_out;
assign DBGMCAPRESET_delay = DBGMCAPRESET_out;
assign DBGPLDATABLOCKRECEIVEDAFTEREDS_delay = DBGPLDATABLOCKRECEIVEDAFTEREDS_out;
assign DBGPLGEN3FRAMINGERRORDETECTED_delay = DBGPLGEN3FRAMINGERRORDETECTED_out;
assign DBGPLGEN3SYNCHEADERERRORDETECTED_delay = DBGPLGEN3SYNCHEADERERRORDETECTED_out;
assign DBGPLINFERREDRXELECTRICALIDLE_delay = DBGPLINFERREDRXELECTRICALIDLE_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign LL2LMMASTERTLPSENT0_delay = LL2LMMASTERTLPSENT0_out;
assign LL2LMMASTERTLPSENT1_delay = LL2LMMASTERTLPSENT1_out;
assign LL2LMMASTERTLPSENTTLPID0_delay = LL2LMMASTERTLPSENTTLPID0_out;
assign LL2LMMASTERTLPSENTTLPID1_delay = LL2LMMASTERTLPSENTTLPID1_out;
assign LL2LMMAXISRXTDATA_delay = LL2LMMAXISRXTDATA_out;
assign LL2LMMAXISRXTUSER_delay = LL2LMMAXISRXTUSER_out;
assign LL2LMMAXISRXTVALID_delay = LL2LMMAXISRXTVALID_out;
assign LL2LMSAXISTXTREADY_delay = LL2LMSAXISTXTREADY_out;
assign MAXISCQTDATA_delay = MAXISCQTDATA_out;
assign MAXISCQTKEEP_delay = MAXISCQTKEEP_out;
assign MAXISCQTLAST_delay = MAXISCQTLAST_out;
assign MAXISCQTUSER_delay = MAXISCQTUSER_out;
assign MAXISCQTVALID_delay = MAXISCQTVALID_out;
assign MAXISRCTDATA_delay = MAXISRCTDATA_out;
assign MAXISRCTKEEP_delay = MAXISRCTKEEP_out;
assign MAXISRCTLAST_delay = MAXISRCTLAST_out;
assign MAXISRCTUSER_delay = MAXISRCTUSER_out;
assign MAXISRCTVALID_delay = MAXISRCTVALID_out;
assign MICOMPLETIONRAMREADADDRESSAL_delay = MICOMPLETIONRAMREADADDRESSAL_out;
assign MICOMPLETIONRAMREADADDRESSAU_delay = MICOMPLETIONRAMREADADDRESSAU_out;
assign MICOMPLETIONRAMREADADDRESSBL_delay = MICOMPLETIONRAMREADADDRESSBL_out;
assign MICOMPLETIONRAMREADADDRESSBU_delay = MICOMPLETIONRAMREADADDRESSBU_out;
assign MICOMPLETIONRAMREADENABLEL_delay = MICOMPLETIONRAMREADENABLEL_out;
assign MICOMPLETIONRAMREADENABLEU_delay = MICOMPLETIONRAMREADENABLEU_out;
assign MICOMPLETIONRAMWRITEADDRESSAL_delay = MICOMPLETIONRAMWRITEADDRESSAL_out;
assign MICOMPLETIONRAMWRITEADDRESSAU_delay = MICOMPLETIONRAMWRITEADDRESSAU_out;
assign MICOMPLETIONRAMWRITEADDRESSBL_delay = MICOMPLETIONRAMWRITEADDRESSBL_out;
assign MICOMPLETIONRAMWRITEADDRESSBU_delay = MICOMPLETIONRAMWRITEADDRESSBU_out;
assign MICOMPLETIONRAMWRITEDATAL_delay = MICOMPLETIONRAMWRITEDATAL_out;
assign MICOMPLETIONRAMWRITEDATAU_delay = MICOMPLETIONRAMWRITEDATAU_out;
assign MICOMPLETIONRAMWRITEENABLEL_delay = MICOMPLETIONRAMWRITEENABLEL_out;
assign MICOMPLETIONRAMWRITEENABLEU_delay = MICOMPLETIONRAMWRITEENABLEU_out;
assign MIREPLAYRAMADDRESS_delay = MIREPLAYRAMADDRESS_out;
assign MIREPLAYRAMREADENABLE_delay = MIREPLAYRAMREADENABLE_out;
assign MIREPLAYRAMWRITEDATA_delay = MIREPLAYRAMWRITEDATA_out;
assign MIREPLAYRAMWRITEENABLE_delay = MIREPLAYRAMWRITEENABLE_out;
assign MIREQUESTRAMREADADDRESSA_delay = MIREQUESTRAMREADADDRESSA_out;
assign MIREQUESTRAMREADADDRESSB_delay = MIREQUESTRAMREADADDRESSB_out;
assign MIREQUESTRAMREADENABLE_delay = MIREQUESTRAMREADENABLE_out;
assign MIREQUESTRAMWRITEADDRESSA_delay = MIREQUESTRAMWRITEADDRESSA_out;
assign MIREQUESTRAMWRITEADDRESSB_delay = MIREQUESTRAMWRITEADDRESSB_out;
assign MIREQUESTRAMWRITEDATA_delay = MIREQUESTRAMWRITEDATA_out;
assign MIREQUESTRAMWRITEENABLE_delay = MIREQUESTRAMWRITEENABLE_out;
assign PCIECQNPREQCOUNT_delay = PCIECQNPREQCOUNT_out;
assign PCIEPERST0B_delay = PCIEPERST0B_out;
assign PCIEPERST1B_delay = PCIEPERST1B_out;
assign PCIERQSEQNUMVLD_delay = PCIERQSEQNUMVLD_out;
assign PCIERQSEQNUM_delay = PCIERQSEQNUM_out;
assign PCIERQTAGAV_delay = PCIERQTAGAV_out;
assign PCIERQTAGVLD_delay = PCIERQTAGVLD_out;
assign PCIERQTAG_delay = PCIERQTAG_out;
assign PCIETFCNPDAV_delay = PCIETFCNPDAV_out;
assign PCIETFCNPHAV_delay = PCIETFCNPHAV_out;
assign PIPERX0EQCONTROL_delay = PIPERX0EQCONTROL_out;
assign PIPERX0EQLPLFFS_delay = PIPERX0EQLPLFFS_out;
assign PIPERX0EQLPTXPRESET_delay = PIPERX0EQLPTXPRESET_out;
assign PIPERX0EQPRESET_delay = PIPERX0EQPRESET_out;
assign PIPERX0POLARITY_delay = PIPERX0POLARITY_out;
assign PIPERX1EQCONTROL_delay = PIPERX1EQCONTROL_out;
assign PIPERX1EQLPLFFS_delay = PIPERX1EQLPLFFS_out;
assign PIPERX1EQLPTXPRESET_delay = PIPERX1EQLPTXPRESET_out;
assign PIPERX1EQPRESET_delay = PIPERX1EQPRESET_out;
assign PIPERX1POLARITY_delay = PIPERX1POLARITY_out;
assign PIPERX2EQCONTROL_delay = PIPERX2EQCONTROL_out;
assign PIPERX2EQLPLFFS_delay = PIPERX2EQLPLFFS_out;
assign PIPERX2EQLPTXPRESET_delay = PIPERX2EQLPTXPRESET_out;
assign PIPERX2EQPRESET_delay = PIPERX2EQPRESET_out;
assign PIPERX2POLARITY_delay = PIPERX2POLARITY_out;
assign PIPERX3EQCONTROL_delay = PIPERX3EQCONTROL_out;
assign PIPERX3EQLPLFFS_delay = PIPERX3EQLPLFFS_out;
assign PIPERX3EQLPTXPRESET_delay = PIPERX3EQLPTXPRESET_out;
assign PIPERX3EQPRESET_delay = PIPERX3EQPRESET_out;
assign PIPERX3POLARITY_delay = PIPERX3POLARITY_out;
assign PIPERX4EQCONTROL_delay = PIPERX4EQCONTROL_out;
assign PIPERX4EQLPLFFS_delay = PIPERX4EQLPLFFS_out;
assign PIPERX4EQLPTXPRESET_delay = PIPERX4EQLPTXPRESET_out;
assign PIPERX4EQPRESET_delay = PIPERX4EQPRESET_out;
assign PIPERX4POLARITY_delay = PIPERX4POLARITY_out;
assign PIPERX5EQCONTROL_delay = PIPERX5EQCONTROL_out;
assign PIPERX5EQLPLFFS_delay = PIPERX5EQLPLFFS_out;
assign PIPERX5EQLPTXPRESET_delay = PIPERX5EQLPTXPRESET_out;
assign PIPERX5EQPRESET_delay = PIPERX5EQPRESET_out;
assign PIPERX5POLARITY_delay = PIPERX5POLARITY_out;
assign PIPERX6EQCONTROL_delay = PIPERX6EQCONTROL_out;
assign PIPERX6EQLPLFFS_delay = PIPERX6EQLPLFFS_out;
assign PIPERX6EQLPTXPRESET_delay = PIPERX6EQLPTXPRESET_out;
assign PIPERX6EQPRESET_delay = PIPERX6EQPRESET_out;
assign PIPERX6POLARITY_delay = PIPERX6POLARITY_out;
assign PIPERX7EQCONTROL_delay = PIPERX7EQCONTROL_out;
assign PIPERX7EQLPLFFS_delay = PIPERX7EQLPLFFS_out;
assign PIPERX7EQLPTXPRESET_delay = PIPERX7EQLPTXPRESET_out;
assign PIPERX7EQPRESET_delay = PIPERX7EQPRESET_out;
assign PIPERX7POLARITY_delay = PIPERX7POLARITY_out;
assign PIPETX0CHARISK_delay = PIPETX0CHARISK_out;
assign PIPETX0COMPLIANCE_delay = PIPETX0COMPLIANCE_out;
assign PIPETX0DATAVALID_delay = PIPETX0DATAVALID_out;
assign PIPETX0DATA_delay = PIPETX0DATA_out;
assign PIPETX0DEEMPH_delay = PIPETX0DEEMPH_out;
assign PIPETX0ELECIDLE_delay = PIPETX0ELECIDLE_out;
assign PIPETX0EQCONTROL_delay = PIPETX0EQCONTROL_out;
assign PIPETX0EQDEEMPH_delay = PIPETX0EQDEEMPH_out;
assign PIPETX0EQPRESET_delay = PIPETX0EQPRESET_out;
assign PIPETX0MARGIN_delay = PIPETX0MARGIN_out;
assign PIPETX0POWERDOWN_delay = PIPETX0POWERDOWN_out;
assign PIPETX0RATE_delay = PIPETX0RATE_out;
assign PIPETX0RCVRDET_delay = PIPETX0RCVRDET_out;
assign PIPETX0RESET_delay = PIPETX0RESET_out;
assign PIPETX0STARTBLOCK_delay = PIPETX0STARTBLOCK_out;
assign PIPETX0SWING_delay = PIPETX0SWING_out;
assign PIPETX0SYNCHEADER_delay = PIPETX0SYNCHEADER_out;
assign PIPETX1CHARISK_delay = PIPETX1CHARISK_out;
assign PIPETX1COMPLIANCE_delay = PIPETX1COMPLIANCE_out;
assign PIPETX1DATAVALID_delay = PIPETX1DATAVALID_out;
assign PIPETX1DATA_delay = PIPETX1DATA_out;
assign PIPETX1DEEMPH_delay = PIPETX1DEEMPH_out;
assign PIPETX1ELECIDLE_delay = PIPETX1ELECIDLE_out;
assign PIPETX1EQCONTROL_delay = PIPETX1EQCONTROL_out;
assign PIPETX1EQDEEMPH_delay = PIPETX1EQDEEMPH_out;
assign PIPETX1EQPRESET_delay = PIPETX1EQPRESET_out;
assign PIPETX1MARGIN_delay = PIPETX1MARGIN_out;
assign PIPETX1POWERDOWN_delay = PIPETX1POWERDOWN_out;
assign PIPETX1RATE_delay = PIPETX1RATE_out;
assign PIPETX1RCVRDET_delay = PIPETX1RCVRDET_out;
assign PIPETX1RESET_delay = PIPETX1RESET_out;
assign PIPETX1STARTBLOCK_delay = PIPETX1STARTBLOCK_out;
assign PIPETX1SWING_delay = PIPETX1SWING_out;
assign PIPETX1SYNCHEADER_delay = PIPETX1SYNCHEADER_out;
assign PIPETX2CHARISK_delay = PIPETX2CHARISK_out;
assign PIPETX2COMPLIANCE_delay = PIPETX2COMPLIANCE_out;
assign PIPETX2DATAVALID_delay = PIPETX2DATAVALID_out;
assign PIPETX2DATA_delay = PIPETX2DATA_out;
assign PIPETX2DEEMPH_delay = PIPETX2DEEMPH_out;
assign PIPETX2ELECIDLE_delay = PIPETX2ELECIDLE_out;
assign PIPETX2EQCONTROL_delay = PIPETX2EQCONTROL_out;
assign PIPETX2EQDEEMPH_delay = PIPETX2EQDEEMPH_out;
assign PIPETX2EQPRESET_delay = PIPETX2EQPRESET_out;
assign PIPETX2MARGIN_delay = PIPETX2MARGIN_out;
assign PIPETX2POWERDOWN_delay = PIPETX2POWERDOWN_out;
assign PIPETX2RATE_delay = PIPETX2RATE_out;
assign PIPETX2RCVRDET_delay = PIPETX2RCVRDET_out;
assign PIPETX2RESET_delay = PIPETX2RESET_out;
assign PIPETX2STARTBLOCK_delay = PIPETX2STARTBLOCK_out;
assign PIPETX2SWING_delay = PIPETX2SWING_out;
assign PIPETX2SYNCHEADER_delay = PIPETX2SYNCHEADER_out;
assign PIPETX3CHARISK_delay = PIPETX3CHARISK_out;
assign PIPETX3COMPLIANCE_delay = PIPETX3COMPLIANCE_out;
assign PIPETX3DATAVALID_delay = PIPETX3DATAVALID_out;
assign PIPETX3DATA_delay = PIPETX3DATA_out;
assign PIPETX3DEEMPH_delay = PIPETX3DEEMPH_out;
assign PIPETX3ELECIDLE_delay = PIPETX3ELECIDLE_out;
assign PIPETX3EQCONTROL_delay = PIPETX3EQCONTROL_out;
assign PIPETX3EQDEEMPH_delay = PIPETX3EQDEEMPH_out;
assign PIPETX3EQPRESET_delay = PIPETX3EQPRESET_out;
assign PIPETX3MARGIN_delay = PIPETX3MARGIN_out;
assign PIPETX3POWERDOWN_delay = PIPETX3POWERDOWN_out;
assign PIPETX3RATE_delay = PIPETX3RATE_out;
assign PIPETX3RCVRDET_delay = PIPETX3RCVRDET_out;
assign PIPETX3RESET_delay = PIPETX3RESET_out;
assign PIPETX3STARTBLOCK_delay = PIPETX3STARTBLOCK_out;
assign PIPETX3SWING_delay = PIPETX3SWING_out;
assign PIPETX3SYNCHEADER_delay = PIPETX3SYNCHEADER_out;
assign PIPETX4CHARISK_delay = PIPETX4CHARISK_out;
assign PIPETX4COMPLIANCE_delay = PIPETX4COMPLIANCE_out;
assign PIPETX4DATAVALID_delay = PIPETX4DATAVALID_out;
assign PIPETX4DATA_delay = PIPETX4DATA_out;
assign PIPETX4DEEMPH_delay = PIPETX4DEEMPH_out;
assign PIPETX4ELECIDLE_delay = PIPETX4ELECIDLE_out;
assign PIPETX4EQCONTROL_delay = PIPETX4EQCONTROL_out;
assign PIPETX4EQDEEMPH_delay = PIPETX4EQDEEMPH_out;
assign PIPETX4EQPRESET_delay = PIPETX4EQPRESET_out;
assign PIPETX4MARGIN_delay = PIPETX4MARGIN_out;
assign PIPETX4POWERDOWN_delay = PIPETX4POWERDOWN_out;
assign PIPETX4RATE_delay = PIPETX4RATE_out;
assign PIPETX4RCVRDET_delay = PIPETX4RCVRDET_out;
assign PIPETX4RESET_delay = PIPETX4RESET_out;
assign PIPETX4STARTBLOCK_delay = PIPETX4STARTBLOCK_out;
assign PIPETX4SWING_delay = PIPETX4SWING_out;
assign PIPETX4SYNCHEADER_delay = PIPETX4SYNCHEADER_out;
assign PIPETX5CHARISK_delay = PIPETX5CHARISK_out;
assign PIPETX5COMPLIANCE_delay = PIPETX5COMPLIANCE_out;
assign PIPETX5DATAVALID_delay = PIPETX5DATAVALID_out;
assign PIPETX5DATA_delay = PIPETX5DATA_out;
assign PIPETX5DEEMPH_delay = PIPETX5DEEMPH_out;
assign PIPETX5ELECIDLE_delay = PIPETX5ELECIDLE_out;
assign PIPETX5EQCONTROL_delay = PIPETX5EQCONTROL_out;
assign PIPETX5EQDEEMPH_delay = PIPETX5EQDEEMPH_out;
assign PIPETX5EQPRESET_delay = PIPETX5EQPRESET_out;
assign PIPETX5MARGIN_delay = PIPETX5MARGIN_out;
assign PIPETX5POWERDOWN_delay = PIPETX5POWERDOWN_out;
assign PIPETX5RATE_delay = PIPETX5RATE_out;
assign PIPETX5RCVRDET_delay = PIPETX5RCVRDET_out;
assign PIPETX5RESET_delay = PIPETX5RESET_out;
assign PIPETX5STARTBLOCK_delay = PIPETX5STARTBLOCK_out;
assign PIPETX5SWING_delay = PIPETX5SWING_out;
assign PIPETX5SYNCHEADER_delay = PIPETX5SYNCHEADER_out;
assign PIPETX6CHARISK_delay = PIPETX6CHARISK_out;
assign PIPETX6COMPLIANCE_delay = PIPETX6COMPLIANCE_out;
assign PIPETX6DATAVALID_delay = PIPETX6DATAVALID_out;
assign PIPETX6DATA_delay = PIPETX6DATA_out;
assign PIPETX6DEEMPH_delay = PIPETX6DEEMPH_out;
assign PIPETX6ELECIDLE_delay = PIPETX6ELECIDLE_out;
assign PIPETX6EQCONTROL_delay = PIPETX6EQCONTROL_out;
assign PIPETX6EQDEEMPH_delay = PIPETX6EQDEEMPH_out;
assign PIPETX6EQPRESET_delay = PIPETX6EQPRESET_out;
assign PIPETX6MARGIN_delay = PIPETX6MARGIN_out;
assign PIPETX6POWERDOWN_delay = PIPETX6POWERDOWN_out;
assign PIPETX6RATE_delay = PIPETX6RATE_out;
assign PIPETX6RCVRDET_delay = PIPETX6RCVRDET_out;
assign PIPETX6RESET_delay = PIPETX6RESET_out;
assign PIPETX6STARTBLOCK_delay = PIPETX6STARTBLOCK_out;
assign PIPETX6SWING_delay = PIPETX6SWING_out;
assign PIPETX6SYNCHEADER_delay = PIPETX6SYNCHEADER_out;
assign PIPETX7CHARISK_delay = PIPETX7CHARISK_out;
assign PIPETX7COMPLIANCE_delay = PIPETX7COMPLIANCE_out;
assign PIPETX7DATAVALID_delay = PIPETX7DATAVALID_out;
assign PIPETX7DATA_delay = PIPETX7DATA_out;
assign PIPETX7DEEMPH_delay = PIPETX7DEEMPH_out;
assign PIPETX7ELECIDLE_delay = PIPETX7ELECIDLE_out;
assign PIPETX7EQCONTROL_delay = PIPETX7EQCONTROL_out;
assign PIPETX7EQDEEMPH_delay = PIPETX7EQDEEMPH_out;
assign PIPETX7EQPRESET_delay = PIPETX7EQPRESET_out;
assign PIPETX7MARGIN_delay = PIPETX7MARGIN_out;
assign PIPETX7POWERDOWN_delay = PIPETX7POWERDOWN_out;
assign PIPETX7RATE_delay = PIPETX7RATE_out;
assign PIPETX7RCVRDET_delay = PIPETX7RCVRDET_out;
assign PIPETX7RESET_delay = PIPETX7RESET_out;
assign PIPETX7STARTBLOCK_delay = PIPETX7STARTBLOCK_out;
assign PIPETX7SWING_delay = PIPETX7SWING_out;
assign PIPETX7SYNCHEADER_delay = PIPETX7SYNCHEADER_out;
assign PLEQINPROGRESS_delay = PLEQINPROGRESS_out;
assign PLEQPHASE_delay = PLEQPHASE_out;
assign SAXISCCTREADY_delay = SAXISCCTREADY_out;
assign SAXISRQTREADY_delay = SAXISRQTREADY_out;
assign SPAREOUT_delay = SPAREOUT_out;
assign CFGCONFIGSPACEENABLE_in = CFGCONFIGSPACEENABLE_delay;
assign CFGDEVID_in = CFGDEVID_delay;
assign CFGDSBUSNUMBER_in = CFGDSBUSNUMBER_delay;
assign CFGDSDEVICENUMBER_in = CFGDSDEVICENUMBER_delay;
assign CFGDSFUNCTIONNUMBER_in = CFGDSFUNCTIONNUMBER_delay;
assign CFGDSN_in = CFGDSN_delay;
assign CFGDSPORTNUMBER_in = CFGDSPORTNUMBER_delay;
assign CFGERRCORIN_in = CFGERRCORIN_delay;
assign CFGERRUNCORIN_in = CFGERRUNCORIN_delay;
assign CFGEXTREADDATAVALID_in = CFGEXTREADDATAVALID_delay;
assign CFGEXTREADDATA_in = CFGEXTREADDATA_delay;
assign CFGFCSEL_in = CFGFCSEL_delay;
assign CFGFLRDONE_in = CFGFLRDONE_delay;
assign CFGHOTRESETIN_in = CFGHOTRESETIN_delay;
assign CFGINTERRUPTINT_in = CFGINTERRUPTINT_delay;
assign CFGINTERRUPTMSIATTR_in = CFGINTERRUPTMSIATTR_delay;
assign CFGINTERRUPTMSIFUNCTIONNUMBER_in = CFGINTERRUPTMSIFUNCTIONNUMBER_delay;
assign CFGINTERRUPTMSIINT_in = CFGINTERRUPTMSIINT_delay;
assign CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in = CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay;
assign CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in = CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay;
assign CFGINTERRUPTMSIPENDINGSTATUS_in = CFGINTERRUPTMSIPENDINGSTATUS_delay;
assign CFGINTERRUPTMSISELECT_in = CFGINTERRUPTMSISELECT_delay;
assign CFGINTERRUPTMSITPHPRESENT_in = CFGINTERRUPTMSITPHPRESENT_delay;
assign CFGINTERRUPTMSITPHSTTAG_in = CFGINTERRUPTMSITPHSTTAG_delay;
assign CFGINTERRUPTMSITPHTYPE_in = CFGINTERRUPTMSITPHTYPE_delay;
assign CFGINTERRUPTMSIXADDRESS_in = CFGINTERRUPTMSIXADDRESS_delay;
assign CFGINTERRUPTMSIXDATA_in = CFGINTERRUPTMSIXDATA_delay;
assign CFGINTERRUPTMSIXINT_in = CFGINTERRUPTMSIXINT_delay;
assign CFGINTERRUPTPENDING_in = CFGINTERRUPTPENDING_delay;
assign CFGLINKTRAININGENABLE_in = CFGLINKTRAININGENABLE_delay;
assign CFGMGMTADDR_in = CFGMGMTADDR_delay;
assign CFGMGMTBYTEENABLE_in = CFGMGMTBYTEENABLE_delay;
assign CFGMGMTREAD_in = CFGMGMTREAD_delay;
assign CFGMGMTTYPE1CFGREGACCESS_in = CFGMGMTTYPE1CFGREGACCESS_delay;
assign CFGMGMTWRITEDATA_in = CFGMGMTWRITEDATA_delay;
assign CFGMGMTWRITE_in = CFGMGMTWRITE_delay;
assign CFGMSGTRANSMITDATA_in = CFGMSGTRANSMITDATA_delay;
assign CFGMSGTRANSMITTYPE_in = CFGMSGTRANSMITTYPE_delay;
assign CFGMSGTRANSMIT_in = CFGMSGTRANSMIT_delay;
assign CFGPERFUNCSTATUSCONTROL_in = CFGPERFUNCSTATUSCONTROL_delay;
assign CFGPERFUNCTIONNUMBER_in = CFGPERFUNCTIONNUMBER_delay;
assign CFGPERFUNCTIONOUTPUTREQUEST_in = CFGPERFUNCTIONOUTPUTREQUEST_delay;
assign CFGPOWERSTATECHANGEACK_in = CFGPOWERSTATECHANGEACK_delay;
assign CFGREQPMTRANSITIONL23READY_in = CFGREQPMTRANSITIONL23READY_delay;
assign CFGREVID_in = CFGREVID_delay;
assign CFGSUBSYSID_in = CFGSUBSYSID_delay;
assign CFGSUBSYSVENDID_in = CFGSUBSYSVENDID_delay;
assign CFGTPHSTTREADDATAVALID_in = CFGTPHSTTREADDATAVALID_delay;
assign CFGTPHSTTREADDATA_in = CFGTPHSTTREADDATA_delay;
assign CFGVENDID_in = CFGVENDID_delay;
assign CFGVFFLRDONE_in = CFGVFFLRDONE_delay;
assign CONFMCAPREQUESTBYCONF_in = CONFMCAPREQUESTBYCONF_delay;
assign CONFREQDATA_in = CONFREQDATA_delay;
assign CONFREQREGNUM_in = CONFREQREGNUM_delay;
assign CONFREQTYPE_in = CONFREQTYPE_delay;
assign CONFREQVALID_in = CONFREQVALID_delay;
assign CORECLKMICOMPLETIONRAML_in = CORECLKMICOMPLETIONRAML_delay;
assign CORECLKMICOMPLETIONRAMU_in = CORECLKMICOMPLETIONRAMU_delay;
assign CORECLKMIREPLAYRAM_in = CORECLKMIREPLAYRAM_delay;
assign CORECLKMIREQUESTRAM_in = CORECLKMIREQUESTRAM_delay;
assign CORECLK_in = CORECLK_delay;
assign DBGCFGLOCALMGMTREGOVERRIDE_in = DBGCFGLOCALMGMTREGOVERRIDE_delay;
assign DBGDATASEL_in = DBGDATASEL_delay;
assign DRPADDR_in = DRPADDR_delay;
assign DRPCLK_in = DRPCLK_delay;
assign DRPDI_in = DRPDI_delay;
assign DRPEN_in = DRPEN_delay;
assign DRPWE_in = DRPWE_delay;
assign LL2LMSAXISTXTUSER_in = LL2LMSAXISTXTUSER_delay;
assign LL2LMSAXISTXTVALID_in = LL2LMSAXISTXTVALID_delay;
assign LL2LMTXTLPID0_in = LL2LMTXTLPID0_delay;
assign LL2LMTXTLPID1_in = LL2LMTXTLPID1_delay;
assign MAXISCQTREADY_in = MAXISCQTREADY_delay;
assign MAXISRCTREADY_in = MAXISRCTREADY_delay;
assign MCAPCLK_in = MCAPCLK_delay;
assign MGMTRESETN_in = MGMTRESETN_delay;
assign MGMTSTICKYRESETN_in = MGMTSTICKYRESETN_delay;
assign MICOMPLETIONRAMREADDATA_in = MICOMPLETIONRAMREADDATA_delay;
assign MIREPLAYRAMREADDATA_in = MIREPLAYRAMREADDATA_delay;
assign MIREQUESTRAMREADDATA_in = MIREQUESTRAMREADDATA_delay;
assign PCIECQNPREQ_in = PCIECQNPREQ_delay;
assign PIPECLK_in = PIPECLK_delay;
assign PIPEEQFS_in = PIPEEQFS_delay;
assign PIPEEQLF_in = PIPEEQLF_delay;
assign PIPERESETN_in = PIPERESETN_delay;
assign PIPERX0CHARISK_in = PIPERX0CHARISK_delay;
assign PIPERX0DATAVALID_in = PIPERX0DATAVALID_delay;
assign PIPERX0DATA_in = PIPERX0DATA_delay;
assign PIPERX0ELECIDLE_in = PIPERX0ELECIDLE_delay;
assign PIPERX0EQDONE_in = PIPERX0EQDONE_delay;
assign PIPERX0EQLPADAPTDONE_in = PIPERX0EQLPADAPTDONE_delay;
assign PIPERX0EQLPLFFSSEL_in = PIPERX0EQLPLFFSSEL_delay;
assign PIPERX0EQLPNEWTXCOEFFORPRESET_in = PIPERX0EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX0PHYSTATUS_in = PIPERX0PHYSTATUS_delay;
assign PIPERX0STARTBLOCK_in = PIPERX0STARTBLOCK_delay;
assign PIPERX0STATUS_in = PIPERX0STATUS_delay;
assign PIPERX0SYNCHEADER_in = PIPERX0SYNCHEADER_delay;
assign PIPERX0VALID_in = PIPERX0VALID_delay;
assign PIPERX1CHARISK_in = PIPERX1CHARISK_delay;
assign PIPERX1DATAVALID_in = PIPERX1DATAVALID_delay;
assign PIPERX1DATA_in = PIPERX1DATA_delay;
assign PIPERX1ELECIDLE_in = PIPERX1ELECIDLE_delay;
assign PIPERX1EQDONE_in = PIPERX1EQDONE_delay;
assign PIPERX1EQLPADAPTDONE_in = PIPERX1EQLPADAPTDONE_delay;
assign PIPERX1EQLPLFFSSEL_in = PIPERX1EQLPLFFSSEL_delay;
assign PIPERX1EQLPNEWTXCOEFFORPRESET_in = PIPERX1EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX1PHYSTATUS_in = PIPERX1PHYSTATUS_delay;
assign PIPERX1STARTBLOCK_in = PIPERX1STARTBLOCK_delay;
assign PIPERX1STATUS_in = PIPERX1STATUS_delay;
assign PIPERX1SYNCHEADER_in = PIPERX1SYNCHEADER_delay;
assign PIPERX1VALID_in = PIPERX1VALID_delay;
assign PIPERX2CHARISK_in = PIPERX2CHARISK_delay;
assign PIPERX2DATAVALID_in = PIPERX2DATAVALID_delay;
assign PIPERX2DATA_in = PIPERX2DATA_delay;
assign PIPERX2ELECIDLE_in = PIPERX2ELECIDLE_delay;
assign PIPERX2EQDONE_in = PIPERX2EQDONE_delay;
assign PIPERX2EQLPADAPTDONE_in = PIPERX2EQLPADAPTDONE_delay;
assign PIPERX2EQLPLFFSSEL_in = PIPERX2EQLPLFFSSEL_delay;
assign PIPERX2EQLPNEWTXCOEFFORPRESET_in = PIPERX2EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX2PHYSTATUS_in = PIPERX2PHYSTATUS_delay;
assign PIPERX2STARTBLOCK_in = PIPERX2STARTBLOCK_delay;
assign PIPERX2STATUS_in = PIPERX2STATUS_delay;
assign PIPERX2SYNCHEADER_in = PIPERX2SYNCHEADER_delay;
assign PIPERX2VALID_in = PIPERX2VALID_delay;
assign PIPERX3CHARISK_in = PIPERX3CHARISK_delay;
assign PIPERX3DATAVALID_in = PIPERX3DATAVALID_delay;
assign PIPERX3DATA_in = PIPERX3DATA_delay;
assign PIPERX3ELECIDLE_in = PIPERX3ELECIDLE_delay;
assign PIPERX3EQDONE_in = PIPERX3EQDONE_delay;
assign PIPERX3EQLPADAPTDONE_in = PIPERX3EQLPADAPTDONE_delay;
assign PIPERX3EQLPLFFSSEL_in = PIPERX3EQLPLFFSSEL_delay;
assign PIPERX3EQLPNEWTXCOEFFORPRESET_in = PIPERX3EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX3PHYSTATUS_in = PIPERX3PHYSTATUS_delay;
assign PIPERX3STARTBLOCK_in = PIPERX3STARTBLOCK_delay;
assign PIPERX3STATUS_in = PIPERX3STATUS_delay;
assign PIPERX3SYNCHEADER_in = PIPERX3SYNCHEADER_delay;
assign PIPERX3VALID_in = PIPERX3VALID_delay;
assign PIPERX4CHARISK_in = PIPERX4CHARISK_delay;
assign PIPERX4DATAVALID_in = PIPERX4DATAVALID_delay;
assign PIPERX4DATA_in = PIPERX4DATA_delay;
assign PIPERX4ELECIDLE_in = PIPERX4ELECIDLE_delay;
assign PIPERX4EQDONE_in = PIPERX4EQDONE_delay;
assign PIPERX4EQLPADAPTDONE_in = PIPERX4EQLPADAPTDONE_delay;
assign PIPERX4EQLPLFFSSEL_in = PIPERX4EQLPLFFSSEL_delay;
assign PIPERX4EQLPNEWTXCOEFFORPRESET_in = PIPERX4EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX4PHYSTATUS_in = PIPERX4PHYSTATUS_delay;
assign PIPERX4STARTBLOCK_in = PIPERX4STARTBLOCK_delay;
assign PIPERX4STATUS_in = PIPERX4STATUS_delay;
assign PIPERX4SYNCHEADER_in = PIPERX4SYNCHEADER_delay;
assign PIPERX4VALID_in = PIPERX4VALID_delay;
assign PIPERX5CHARISK_in = PIPERX5CHARISK_delay;
assign PIPERX5DATAVALID_in = PIPERX5DATAVALID_delay;
assign PIPERX5DATA_in = PIPERX5DATA_delay;
assign PIPERX5ELECIDLE_in = PIPERX5ELECIDLE_delay;
assign PIPERX5EQDONE_in = PIPERX5EQDONE_delay;
assign PIPERX5EQLPADAPTDONE_in = PIPERX5EQLPADAPTDONE_delay;
assign PIPERX5EQLPLFFSSEL_in = PIPERX5EQLPLFFSSEL_delay;
assign PIPERX5EQLPNEWTXCOEFFORPRESET_in = PIPERX5EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX5PHYSTATUS_in = PIPERX5PHYSTATUS_delay;
assign PIPERX5STARTBLOCK_in = PIPERX5STARTBLOCK_delay;
assign PIPERX5STATUS_in = PIPERX5STATUS_delay;
assign PIPERX5SYNCHEADER_in = PIPERX5SYNCHEADER_delay;
assign PIPERX5VALID_in = PIPERX5VALID_delay;
assign PIPERX6CHARISK_in = PIPERX6CHARISK_delay;
assign PIPERX6DATAVALID_in = PIPERX6DATAVALID_delay;
assign PIPERX6DATA_in = PIPERX6DATA_delay;
assign PIPERX6ELECIDLE_in = PIPERX6ELECIDLE_delay;
assign PIPERX6EQDONE_in = PIPERX6EQDONE_delay;
assign PIPERX6EQLPADAPTDONE_in = PIPERX6EQLPADAPTDONE_delay;
assign PIPERX6EQLPLFFSSEL_in = PIPERX6EQLPLFFSSEL_delay;
assign PIPERX6EQLPNEWTXCOEFFORPRESET_in = PIPERX6EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX6PHYSTATUS_in = PIPERX6PHYSTATUS_delay;
assign PIPERX6STARTBLOCK_in = PIPERX6STARTBLOCK_delay;
assign PIPERX6STATUS_in = PIPERX6STATUS_delay;
assign PIPERX6SYNCHEADER_in = PIPERX6SYNCHEADER_delay;
assign PIPERX6VALID_in = PIPERX6VALID_delay;
assign PIPERX7CHARISK_in = PIPERX7CHARISK_delay;
assign PIPERX7DATAVALID_in = PIPERX7DATAVALID_delay;
assign PIPERX7DATA_in = PIPERX7DATA_delay;
assign PIPERX7ELECIDLE_in = PIPERX7ELECIDLE_delay;
assign PIPERX7EQDONE_in = PIPERX7EQDONE_delay;
assign PIPERX7EQLPADAPTDONE_in = PIPERX7EQLPADAPTDONE_delay;
assign PIPERX7EQLPLFFSSEL_in = PIPERX7EQLPLFFSSEL_delay;
assign PIPERX7EQLPNEWTXCOEFFORPRESET_in = PIPERX7EQLPNEWTXCOEFFORPRESET_delay;
assign PIPERX7PHYSTATUS_in = PIPERX7PHYSTATUS_delay;
assign PIPERX7STARTBLOCK_in = PIPERX7STARTBLOCK_delay;
assign PIPERX7STATUS_in = PIPERX7STATUS_delay;
assign PIPERX7SYNCHEADER_in = PIPERX7SYNCHEADER_delay;
assign PIPERX7VALID_in = PIPERX7VALID_delay;
assign PIPETX0EQCOEFF_in = PIPETX0EQCOEFF_delay;
assign PIPETX0EQDONE_in = PIPETX0EQDONE_delay;
assign PIPETX1EQCOEFF_in = PIPETX1EQCOEFF_delay;
assign PIPETX1EQDONE_in = PIPETX1EQDONE_delay;
assign PIPETX2EQCOEFF_in = PIPETX2EQCOEFF_delay;
assign PIPETX2EQDONE_in = PIPETX2EQDONE_delay;
assign PIPETX3EQCOEFF_in = PIPETX3EQCOEFF_delay;
assign PIPETX3EQDONE_in = PIPETX3EQDONE_delay;
assign PIPETX4EQCOEFF_in = PIPETX4EQCOEFF_delay;
assign PIPETX4EQDONE_in = PIPETX4EQDONE_delay;
assign PIPETX5EQCOEFF_in = PIPETX5EQCOEFF_delay;
assign PIPETX5EQDONE_in = PIPETX5EQDONE_delay;
assign PIPETX6EQCOEFF_in = PIPETX6EQCOEFF_delay;
assign PIPETX6EQDONE_in = PIPETX6EQDONE_delay;
assign PIPETX7EQCOEFF_in = PIPETX7EQCOEFF_delay;
assign PIPETX7EQDONE_in = PIPETX7EQDONE_delay;
assign PLEQRESETEIEOSCOUNT_in = PLEQRESETEIEOSCOUNT_delay;
assign PLGEN2UPSTREAMPREFERDEEMPH_in = PLGEN2UPSTREAMPREFERDEEMPH_delay;
assign RESETN_in = RESETN_delay;
assign SAXISCCTDATA_in = SAXISCCTDATA_delay;
assign SAXISCCTKEEP_in = SAXISCCTKEEP_delay;
assign SAXISCCTLAST_in = SAXISCCTLAST_delay;
assign SAXISCCTUSER_in = SAXISCCTUSER_delay;
assign SAXISCCTVALID_in = SAXISCCTVALID_delay;
assign SAXISRQTDATA_in = SAXISRQTDATA_delay;
assign SAXISRQTKEEP_in = SAXISRQTKEEP_delay;
assign SAXISRQTLAST_in = SAXISRQTLAST_delay;
assign SAXISRQTUSER_in = SAXISRQTUSER_delay;
assign SAXISRQTVALID_in = SAXISRQTVALID_delay;
assign SPAREIN_in = SPAREIN_delay;
assign USERCLK_in = USERCLK_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((ARI_CAP_ENABLE_REG != "FALSE") &&
(ARI_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ARI_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ARI_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_CC_ALIGNMENT_MODE_REG != "FALSE") &&
(AXISTEN_IF_CC_ALIGNMENT_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_CC_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_CC_ALIGNMENT_MODE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_CC_PARITY_CHK_REG != "TRUE") &&
(AXISTEN_IF_CC_PARITY_CHK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_CC_PARITY_CHK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AXISTEN_IF_CC_PARITY_CHK_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_CQ_ALIGNMENT_MODE_REG != "FALSE") &&
(AXISTEN_IF_CQ_ALIGNMENT_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_CQ_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_CQ_ALIGNMENT_MODE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "FALSE") &&
(AXISTEN_IF_ENABLE_CLIENT_TAG_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_ENABLE_CLIENT_TAG on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_ENABLE_CLIENT_TAG_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "FALSE") &&
(AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_ENABLE_RX_MSG_INTFC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_RC_ALIGNMENT_MODE_REG != "FALSE") &&
(AXISTEN_IF_RC_ALIGNMENT_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_RC_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RC_ALIGNMENT_MODE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_RC_STRADDLE_REG != "FALSE") &&
(AXISTEN_IF_RC_STRADDLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_RC_STRADDLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RC_STRADDLE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_RQ_ALIGNMENT_MODE_REG != "FALSE") &&
(AXISTEN_IF_RQ_ALIGNMENT_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_RQ_ALIGNMENT_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, AXISTEN_IF_RQ_ALIGNMENT_MODE_REG);
attr_err = 1'b1;
end
if ((AXISTEN_IF_RQ_PARITY_CHK_REG != "TRUE") &&
(AXISTEN_IF_RQ_PARITY_CHK_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute AXISTEN_IF_RQ_PARITY_CHK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AXISTEN_IF_RQ_PARITY_CHK_REG);
attr_err = 1'b1;
end
if ((CRM_CORE_CLK_FREQ_500_REG != "TRUE") &&
(CRM_CORE_CLK_FREQ_500_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute CRM_CORE_CLK_FREQ_500 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CRM_CORE_CLK_FREQ_500_REG);
attr_err = 1'b1;
end
if ((DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG != "FALSE") &&
(DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") &&
(DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DEBUG_PL_DISABLE_EI_INFER_IN_L0 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG);
attr_err = 1'b1;
end
if ((DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "FALSE") &&
(DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG);
attr_err = 1'b1;
end
if ((LL_ACK_TIMEOUT_EN_REG != "FALSE") &&
(LL_ACK_TIMEOUT_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_ACK_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_ACK_TIMEOUT_EN_REG);
attr_err = 1'b1;
end
if ((LL_ACK_TIMEOUT_FUNC_REG != 0) &&
(LL_ACK_TIMEOUT_FUNC_REG != 1) &&
(LL_ACK_TIMEOUT_FUNC_REG != 2) &&
(LL_ACK_TIMEOUT_FUNC_REG != 3)) begin
$display("Attribute Syntax Error : The attribute LL_ACK_TIMEOUT_FUNC on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, LL_ACK_TIMEOUT_FUNC_REG, 0);
attr_err = 1'b1;
end
if ((LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") &&
(LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_CPL_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((LL_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") &&
(LL_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_FC_UPDATE_TIMER_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") &&
(LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_NP_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((LL_P_FC_UPDATE_TIMER_OVERRIDE_REG != "FALSE") &&
(LL_P_FC_UPDATE_TIMER_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_P_FC_UPDATE_TIMER_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_P_FC_UPDATE_TIMER_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((LL_REPLAY_TIMEOUT_EN_REG != "FALSE") &&
(LL_REPLAY_TIMEOUT_EN_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LL_REPLAY_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LL_REPLAY_TIMEOUT_EN_REG);
attr_err = 1'b1;
end
if ((LL_REPLAY_TIMEOUT_FUNC_REG != 0) &&
(LL_REPLAY_TIMEOUT_FUNC_REG != 1) &&
(LL_REPLAY_TIMEOUT_FUNC_REG != 2) &&
(LL_REPLAY_TIMEOUT_FUNC_REG != 3)) begin
$display("Attribute Syntax Error : The attribute LL_REPLAY_TIMEOUT_FUNC on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, LL_REPLAY_TIMEOUT_FUNC_REG, 0);
attr_err = 1'b1;
end
if ((LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "FALSE") &&
(LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "FALSE") &&
(LTR_TX_MESSAGE_ON_LTR_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute LTR_TX_MESSAGE_ON_LTR_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, LTR_TX_MESSAGE_ON_LTR_ENABLE_REG);
attr_err = 1'b1;
end
if ((MCAP_CONFIGURE_OVERRIDE_REG != "FALSE") &&
(MCAP_CONFIGURE_OVERRIDE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_CONFIGURE_OVERRIDE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_CONFIGURE_OVERRIDE_REG);
attr_err = 1'b1;
end
if ((MCAP_ENABLE_REG != "FALSE") &&
(MCAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((MCAP_EOS_DESIGN_SWITCH_REG != "FALSE") &&
(MCAP_EOS_DESIGN_SWITCH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_EOS_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_EOS_DESIGN_SWITCH_REG);
attr_err = 1'b1;
end
if ((MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "FALSE") &&
(MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_GATE_IO_ENABLE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG);
attr_err = 1'b1;
end
if ((MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "FALSE") &&
(MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG);
attr_err = 1'b1;
end
if ((MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "FALSE") &&
(MCAP_INPUT_GATE_DESIGN_SWITCH_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_INPUT_GATE_DESIGN_SWITCH on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INPUT_GATE_DESIGN_SWITCH_REG);
attr_err = 1'b1;
end
if ((MCAP_INTERRUPT_ON_MCAP_EOS_REG != "FALSE") &&
(MCAP_INTERRUPT_ON_MCAP_EOS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_INTERRUPT_ON_MCAP_EOS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_EOS_REG);
attr_err = 1'b1;
end
if ((MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "FALSE") &&
(MCAP_INTERRUPT_ON_MCAP_ERROR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute MCAP_INTERRUPT_ON_MCAP_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MCAP_INTERRUPT_ON_MCAP_ERROR_REG);
attr_err = 1'b1;
end
if ((PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") &&
(PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF0_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") &&
(PF0_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_AER_CAP_ECRC_GEN_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") &&
(PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") &&
(PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "TRUE") &&
(PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "FALSE") &&
(PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_ARI_FORWARD_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "TRUE") &&
(PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_LTR_SUPPORT_REG != "TRUE") &&
(PF0_DEV_CAP2_LTR_SUPPORT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_LTR_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP2_LTR_SUPPORT_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "FALSE") &&
(PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 0) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 1) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 2) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 3) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 4) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 5) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 6) &&
(PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP_ENDPOINT_L0S_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG, 0);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 0) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 1) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 2) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 3) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 4) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 5) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 6) &&
(PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP_ENDPOINT_L1_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG, 0);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "TRUE") &&
(PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG);
attr_err = 1'b1;
end
if ((PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "TRUE") &&
(PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") &&
(PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG);
attr_err = 1'b1;
end
if ((PF0_EXPANSION_ROM_ENABLE_REG != "FALSE") &&
(PF0_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_EXPANSION_ROM_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_ASPM_SUPPORT_REG != 0) &&
(PF0_LINK_CAP_ASPM_SUPPORT_REG != 1) &&
(PF0_LINK_CAP_ASPM_SUPPORT_REG != 2) &&
(PF0_LINK_CAP_ASPM_SUPPORT_REG != 3)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_ASPM_SUPPORT on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PF0_LINK_CAP_ASPM_SUPPORT_REG, 0);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 7) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 0) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 1) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 2) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 3) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 4) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 5) &&
(PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 7) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 0) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 1) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 2) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 3) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 4) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 5) &&
(PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG != 6)) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG, 7);
attr_err = 1'b1;
end
if ((PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "TRUE") &&
(PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_LINK_STATUS_SLOT_CLOCK_CONFIG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG);
attr_err = 1'b1;
end
if ((PF0_MSIX_CAP_PBA_BIR_REG != 0) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 1) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 2) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 3) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 4) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 5) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 6) &&
(PF0_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF0_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF0_MSIX_CAP_TABLE_BIR_REG != 0) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 1) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 2) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 3) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 4) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 5) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 6) &&
(PF0_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF0_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF0_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(PF0_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF0_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF0_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((PF0_MSI_CAP_PERVECMASKCAP_REG != "FALSE") &&
(PF0_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_MSI_CAP_PERVECMASKCAP_REG);
attr_err = 1'b1;
end
if ((PF0_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") &&
(PF0_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_PB_CAP_SYSTEM_ALLOCATED_REG);
attr_err = 1'b1;
end
if ((PF0_PM_CAP_PMESUPPORT_D0_REG != "TRUE") &&
(PF0_PM_CAP_PMESUPPORT_D0_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D0_REG);
attr_err = 1'b1;
end
if ((PF0_PM_CAP_PMESUPPORT_D1_REG != "TRUE") &&
(PF0_PM_CAP_PMESUPPORT_D1_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D1_REG);
attr_err = 1'b1;
end
if ((PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "TRUE") &&
(PF0_PM_CAP_PMESUPPORT_D3HOT_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_PM_CAP_PMESUPPORT_D3HOT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_PMESUPPORT_D3HOT_REG);
attr_err = 1'b1;
end
if ((PF0_PM_CAP_SUPP_D1_STATE_REG != "TRUE") &&
(PF0_PM_CAP_SUPP_D1_STATE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_PM_CAP_SUPP_D1_STATE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CAP_SUPP_D1_STATE_REG);
attr_err = 1'b1;
end
if ((PF0_PM_CSR_NOSOFTRESET_REG != "TRUE") &&
(PF0_PM_CSR_NOSOFTRESET_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_PM_CSR_NOSOFTRESET on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_PM_CSR_NOSOFTRESET_REG);
attr_err = 1'b1;
end
if ((PF0_RBAR_CAP_ENABLE_REG != "FALSE") &&
(PF0_RBAR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_RBAR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((PF0_TPHR_CAP_ENABLE_REG != "FALSE") &&
(PF0_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(PF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF0_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF0_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((PF0_VC_CAP_ENABLE_REG != "FALSE") &&
(PF0_VC_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF0_VC_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF0_VC_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") &&
(PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF1_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") &&
(PF1_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_AER_CAP_ECRC_GEN_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") &&
(PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF1_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG);
attr_err = 1'b1;
end
if ((PF1_EXPANSION_ROM_ENABLE_REG != "FALSE") &&
(PF1_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_EXPANSION_ROM_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF1_MSIX_CAP_PBA_BIR_REG != 0) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 1) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 2) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 3) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 4) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 5) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 6) &&
(PF1_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF1_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF1_MSIX_CAP_TABLE_BIR_REG != 0) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 1) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 2) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 3) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 4) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 5) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 6) &&
(PF1_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF1_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF1_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(PF1_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF1_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF1_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((PF1_MSI_CAP_PERVECMASKCAP_REG != "FALSE") &&
(PF1_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_MSI_CAP_PERVECMASKCAP_REG);
attr_err = 1'b1;
end
if ((PF1_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") &&
(PF1_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_PB_CAP_SYSTEM_ALLOCATED_REG);
attr_err = 1'b1;
end
if ((PF1_RBAR_CAP_ENABLE_REG != "FALSE") &&
(PF1_RBAR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_RBAR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((PF1_TPHR_CAP_ENABLE_REG != "FALSE") &&
(PF1_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF1_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF1_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(PF1_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF1_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF1_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") &&
(PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF2_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") &&
(PF2_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_AER_CAP_ECRC_GEN_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") &&
(PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF2_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG);
attr_err = 1'b1;
end
if ((PF2_EXPANSION_ROM_ENABLE_REG != "FALSE") &&
(PF2_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_EXPANSION_ROM_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF2_MSIX_CAP_PBA_BIR_REG != 0) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 1) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 2) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 3) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 4) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 5) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 6) &&
(PF2_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF2_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF2_MSIX_CAP_TABLE_BIR_REG != 0) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 1) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 2) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 3) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 4) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 5) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 6) &&
(PF2_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF2_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF2_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(PF2_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF2_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF2_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((PF2_MSI_CAP_PERVECMASKCAP_REG != "FALSE") &&
(PF2_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_MSI_CAP_PERVECMASKCAP_REG);
attr_err = 1'b1;
end
if ((PF2_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") &&
(PF2_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_PB_CAP_SYSTEM_ALLOCATED_REG);
attr_err = 1'b1;
end
if ((PF2_RBAR_CAP_ENABLE_REG != "FALSE") &&
(PF2_RBAR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_RBAR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((PF2_TPHR_CAP_ENABLE_REG != "FALSE") &&
(PF2_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF2_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF2_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(PF2_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF2_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF2_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG != "FALSE") &&
(PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_AER_CAP_ECRC_CHECK_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF3_AER_CAP_ECRC_GEN_CAPABLE_REG != "FALSE") &&
(PF3_AER_CAP_ECRC_GEN_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_AER_CAP_ECRC_GEN_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_AER_CAP_ECRC_GEN_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "TRUE") &&
(PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF3_DPA_CAP_SUB_STATE_CONTROL_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG);
attr_err = 1'b1;
end
if ((PF3_EXPANSION_ROM_ENABLE_REG != "FALSE") &&
(PF3_EXPANSION_ROM_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_EXPANSION_ROM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_EXPANSION_ROM_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF3_MSIX_CAP_PBA_BIR_REG != 0) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 1) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 2) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 3) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 4) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 5) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 6) &&
(PF3_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF3_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF3_MSIX_CAP_TABLE_BIR_REG != 0) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 1) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 2) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 3) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 4) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 5) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 6) &&
(PF3_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF3_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((PF3_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(PF3_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute PF3_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PF3_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((PF3_MSI_CAP_PERVECMASKCAP_REG != "FALSE") &&
(PF3_MSI_CAP_PERVECMASKCAP_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_MSI_CAP_PERVECMASKCAP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_MSI_CAP_PERVECMASKCAP_REG);
attr_err = 1'b1;
end
if ((PF3_PB_CAP_SYSTEM_ALLOCATED_REG != "FALSE") &&
(PF3_PB_CAP_SYSTEM_ALLOCATED_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_PB_CAP_SYSTEM_ALLOCATED on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_PB_CAP_SYSTEM_ALLOCATED_REG);
attr_err = 1'b1;
end
if ((PF3_RBAR_CAP_ENABLE_REG != "FALSE") &&
(PF3_RBAR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_RBAR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_RBAR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((PF3_TPHR_CAP_ENABLE_REG != "FALSE") &&
(PF3_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PF3_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((PF3_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(PF3_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PF3_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PF3_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "FALSE") &&
(PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "FALSE") &&
(PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_EI_INFER_IN_L0_REG != "FALSE") &&
(PL_DISABLE_EI_INFER_IN_L0_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_EI_INFER_IN_L0 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_EI_INFER_IN_L0_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_GEN3_DC_BALANCE_REG != "FALSE") &&
(PL_DISABLE_GEN3_DC_BALANCE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_GEN3_DC_BALANCE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_GEN3_DC_BALANCE_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG != "FALSE") &&
(PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "FALSE") &&
(PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_RETRAIN_ON_FRAMING_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_SCRAMBLING_REG != "FALSE") &&
(PL_DISABLE_SCRAMBLING_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_SCRAMBLING on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_SCRAMBLING_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG != "FALSE") &&
(PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_SYNC_HEADER_FRAMING_ERROR on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG);
attr_err = 1'b1;
end
if ((PL_DISABLE_UPCONFIG_CAPABLE_REG != "FALSE") &&
(PL_DISABLE_UPCONFIG_CAPABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_DISABLE_UPCONFIG_CAPABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_DISABLE_UPCONFIG_CAPABLE_REG);
attr_err = 1'b1;
end
if ((PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG != "FALSE") &&
(PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_EQ_ADAPT_DISABLE_COEFF_CHECK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG);
attr_err = 1'b1;
end
if ((PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG != "FALSE") &&
(PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_EQ_ADAPT_DISABLE_PRESET_CHECK on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG);
attr_err = 1'b1;
end
if ((PL_EQ_BYPASS_PHASE23_REG != "FALSE") &&
(PL_EQ_BYPASS_PHASE23_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_EQ_BYPASS_PHASE23 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_BYPASS_PHASE23_REG);
attr_err = 1'b1;
end
if ((PL_EQ_PHASE01_RX_ADAPT_REG != "FALSE") &&
(PL_EQ_PHASE01_RX_ADAPT_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_EQ_PHASE01_RX_ADAPT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_PHASE01_RX_ADAPT_REG);
attr_err = 1'b1;
end
if ((PL_EQ_SHORT_ADAPT_PHASE_REG != "FALSE") &&
(PL_EQ_SHORT_ADAPT_PHASE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_EQ_SHORT_ADAPT_PHASE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_EQ_SHORT_ADAPT_PHASE_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_COMCLK_GEN1_REG < 0) || (PL_N_FTS_COMCLK_GEN1_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN1_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_COMCLK_GEN2_REG < 0) || (PL_N_FTS_COMCLK_GEN2_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN2_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_COMCLK_GEN3_REG < 0) || (PL_N_FTS_COMCLK_GEN3_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_COMCLK_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_COMCLK_GEN3_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_GEN1_REG < 0) || (PL_N_FTS_GEN1_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_GEN1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN1_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_GEN2_REG < 0) || (PL_N_FTS_GEN2_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_GEN2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN2_REG);
attr_err = 1'b1;
end
if ((PL_N_FTS_GEN3_REG < 0) || (PL_N_FTS_GEN3_REG > 255)) begin
$display("Attribute Syntax Error : The attribute PL_N_FTS_GEN3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, PL_N_FTS_GEN3_REG);
attr_err = 1'b1;
end
if ((PL_REPORT_ALL_PHY_ERRORS_REG != "TRUE") &&
(PL_REPORT_ALL_PHY_ERRORS_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PL_REPORT_ALL_PHY_ERRORS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PL_REPORT_ALL_PHY_ERRORS_REG);
attr_err = 1'b1;
end
if ((PL_SIM_FAST_LINK_TRAINING_REG != "FALSE") &&
(PL_SIM_FAST_LINK_TRAINING_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PL_SIM_FAST_LINK_TRAINING on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PL_SIM_FAST_LINK_TRAINING_REG);
attr_err = 1'b1;
end
if ((PL_UPSTREAM_FACING_REG != "TRUE") &&
(PL_UPSTREAM_FACING_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PL_UPSTREAM_FACING on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PL_UPSTREAM_FACING_REG);
attr_err = 1'b1;
end
if ((PM_ENABLE_L23_ENTRY_REG != "FALSE") &&
(PM_ENABLE_L23_ENTRY_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PM_ENABLE_L23_ENTRY on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PM_ENABLE_L23_ENTRY_REG);
attr_err = 1'b1;
end
if ((PM_ENABLE_SLOT_POWER_CAPTURE_REG != "TRUE") &&
(PM_ENABLE_SLOT_POWER_CAPTURE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute PM_ENABLE_SLOT_POWER_CAPTURE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_ENABLE_SLOT_POWER_CAPTURE_REG);
attr_err = 1'b1;
end
if ((SIM_VERSION_REG != "1.0") &&
(SIM_VERSION_REG != "1.1") &&
(SIM_VERSION_REG != "1.2") &&
(SIM_VERSION_REG != "1.3") &&
(SIM_VERSION_REG != "2.0") &&
(SIM_VERSION_REG != "3.0") &&
(SIM_VERSION_REG != "4.0")) begin
$display("Attribute Syntax Error : The attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0 or 4.0.", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((SPARE_BIT0_REG != 0) &&
(SPARE_BIT0_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT0_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT1_REG != 0) &&
(SPARE_BIT1_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT1_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT2_REG != 0) &&
(SPARE_BIT2_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT2_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT3_REG != 0) &&
(SPARE_BIT3_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT3_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT4_REG != 0) &&
(SPARE_BIT4_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT4 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT4_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT5_REG != 0) &&
(SPARE_BIT5_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT5 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT5_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT6_REG != 0) &&
(SPARE_BIT6_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT6 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT6_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT7_REG != 0) &&
(SPARE_BIT7_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT7 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT7_REG, 0);
attr_err = 1'b1;
end
if ((SPARE_BIT8_REG != 0) &&
(SPARE_BIT8_REG != 1)) begin
$display("Attribute Syntax Error : The attribute SPARE_BIT8 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SPARE_BIT8_REG, 0);
attr_err = 1'b1;
end
if ((SRIOV_CAP_ENABLE_REG != "FALSE") &&
(SRIOV_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SRIOV_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SRIOV_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG != "TRUE") &&
(TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TL_ENABLE_MESSAGE_RID_CHECK_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") &&
(TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "FALSE") &&
(TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_LEGACY_MODE_ENABLE_REG != "FALSE") &&
(TL_LEGACY_MODE_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TL_LEGACY_MODE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TL_LEGACY_MODE_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_TAG_MGMT_ENABLE_REG != "TRUE") &&
(TL_TAG_MGMT_ENABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TL_TAG_MGMT_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_TAG_MGMT_ENABLE_REG);
attr_err = 1'b1;
end
if ((TL_TX_MUX_STRICT_PRIORITY_REG != "TRUE") &&
(TL_TX_MUX_STRICT_PRIORITY_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TL_TX_MUX_STRICT_PRIORITY on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_TX_MUX_STRICT_PRIORITY_REG);
attr_err = 1'b1;
end
if ((TWO_LAYER_MODE_DLCMSM_ENABLE_REG != "TRUE") &&
(TWO_LAYER_MODE_DLCMSM_ENABLE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_DLCMSM_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TWO_LAYER_MODE_DLCMSM_ENABLE_REG);
attr_err = 1'b1;
end
if ((TWO_LAYER_MODE_ENABLE_REG != "FALSE") &&
(TWO_LAYER_MODE_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TWO_LAYER_MODE_ENABLE_REG);
attr_err = 1'b1;
end
if ((TWO_LAYER_MODE_WIDTH_256_REG != "TRUE") &&
(TWO_LAYER_MODE_WIDTH_256_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute TWO_LAYER_MODE_WIDTH_256 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TWO_LAYER_MODE_WIDTH_256_REG);
attr_err = 1'b1;
end
if ((VF0_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF0_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF0_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF0_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF0_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF0_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF0_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF0_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF0_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF0_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF0_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF0_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF0_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF0_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF0_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF0_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF0_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF1_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF1_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF1_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF1_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF1_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF1_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF1_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF1_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF1_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF1_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF1_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF1_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF1_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF1_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF1_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF1_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF1_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF2_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF2_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF2_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF2_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF2_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF2_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF2_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF2_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF2_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF2_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF2_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF2_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF2_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF2_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF2_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF2_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF2_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF3_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF3_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF3_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF3_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF3_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF3_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF3_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF3_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF3_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF3_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF3_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF3_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF3_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF3_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF3_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF3_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF3_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF4_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF4_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF4_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF4_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF4_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF4_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF4_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF4_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF4_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF4_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF4_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF4_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF4_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF4_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF4_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF4_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF4_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF5_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF5_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF5_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF5_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF5_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF5_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF5_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF5_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF5_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF5_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF5_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF5_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF5_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF5_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF5_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF5_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF5_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF6_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF6_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF6_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF6_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF6_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF6_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF6_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF6_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF6_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF6_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF6_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF6_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF6_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF6_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF6_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF6_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF6_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if ((VF7_MSIX_CAP_PBA_BIR_REG != 0) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 1) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 2) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 3) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 4) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 5) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 6) &&
(VF7_MSIX_CAP_PBA_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF7_MSIX_CAP_PBA_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSIX_CAP_PBA_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF7_MSIX_CAP_TABLE_BIR_REG != 0) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 1) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 2) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 3) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 4) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 5) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 6) &&
(VF7_MSIX_CAP_TABLE_BIR_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF7_MSIX_CAP_TABLE_BIR on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSIX_CAP_TABLE_BIR_REG, 0);
attr_err = 1'b1;
end
if ((VF7_MSI_CAP_MULTIMSGCAP_REG != 0) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 1) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 2) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 3) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 4) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 5) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 6) &&
(VF7_MSI_CAP_MULTIMSGCAP_REG != 7)) begin
$display("Attribute Syntax Error : The attribute VF7_MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, VF7_MSI_CAP_MULTIMSGCAP_REG, 0);
attr_err = 1'b1;
end
if ((VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "TRUE") &&
(VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_DEV_SPECIFIC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG);
attr_err = 1'b1;
end
if ((VF7_TPHR_CAP_ENABLE_REG != "FALSE") &&
(VF7_TPHR_CAP_ENABLE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, VF7_TPHR_CAP_ENABLE_REG);
attr_err = 1'b1;
end
if ((VF7_TPHR_CAP_INT_VEC_MODE_REG != "TRUE") &&
(VF7_TPHR_CAP_INT_VEC_MODE_REG != "FALSE")) begin
$display("Attribute Syntax Error : The attribute VF7_TPHR_CAP_INT_VEC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VF7_TPHR_CAP_INT_VEC_MODE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign XILUNCONNCLK_in = 951'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign PMVDIVIDE_in = 2'b11; // tie off
assign PMVENABLEN_in = 1'b1; // tie off
assign PMVSELECT_in = 3'b111; // tie off
assign SCANENABLEN_in = 1'b1; // tie off
assign SCANIN_in = 96'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign SCANMODEN_in = 1'b1; // tie off
assign XILUNCONNBYP_in = 1920'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign XILUNCONNIN_in = 3189'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
SIP_PCIE_3_1 #(
//Added manually
.SIM_JTAG_IDCODE(SIM_JTAG_IDCODE)
)
SIP_PCIE_3_1_INST (
.ARI_CAP_ENABLE (ARI_CAP_ENABLE_REG),
.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE_REG),
.AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK_REG),
.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE_REG),
.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG_REG),
.AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE_REG),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC_REG),
.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE_REG),
.AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE_REG),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE_REG),
.AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK_REG),
.AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH_REG),
.CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500_REG),
.CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ_REG),
.DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE (DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE_REG),
.DEBUG_PL_DISABLE_EI_INFER_IN_L0 (DEBUG_PL_DISABLE_EI_INFER_IN_L0_REG),
.DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS_REG),
.DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM_REG),
.LL_ACK_TIMEOUT (LL_ACK_TIMEOUT_REG),
.LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN_REG),
.LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC_REG),
.LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER_REG),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE_REG),
.LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER_REG),
.LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE_REG),
.LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER_REG),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE_REG),
.LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER_REG),
.LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE_REG),
.LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT_REG),
.LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN_REG),
.LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC_REG),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL_REG),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_REG),
.LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE_REG),
.MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR_REG),
.MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE_REG),
.MCAP_ENABLE (MCAP_ENABLE_REG),
.MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH_REG),
.MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION_REG),
.MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH_REG),
.MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH_REG),
.MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH_REG),
.MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS_REG),
.MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR_REG),
.MCAP_VSEC_ID (MCAP_VSEC_ID_REG),
.MCAP_VSEC_LEN (MCAP_VSEC_LEN_REG),
.MCAP_VSEC_REV (MCAP_VSEC_REV_REG),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE_REG),
.PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE_REG),
.PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR_REG),
.PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR_REG),
.PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC_REG),
.PF0_ARI_CAP_VER (PF0_ARI_CAP_VER_REG),
.PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE_REG),
.PF0_BAR0_CONTROL (PF0_BAR0_CONTROL_REG),
.PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE_REG),
.PF0_BAR1_CONTROL (PF0_BAR1_CONTROL_REG),
.PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE_REG),
.PF0_BAR2_CONTROL (PF0_BAR2_CONTROL_REG),
.PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE_REG),
.PF0_BAR3_CONTROL (PF0_BAR3_CONTROL_REG),
.PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE_REG),
.PF0_BAR4_CONTROL (PF0_BAR4_CONTROL_REG),
.PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE_REG),
.PF0_BAR5_CONTROL (PF0_BAR5_CONTROL_REG),
.PF0_BIST_REGISTER (PF0_BIST_REGISTER_REG),
.PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER_REG),
.PF0_CLASS_CODE (PF0_CLASS_CODE_REG),
.PF0_DEVICE_ID (PF0_DEVICE_ID_REG),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_REG),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_REG),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_REG),
.PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE_REG),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_REG),
.PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT_REG),
.PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT_REG),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_REG),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_REG),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY_REG),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED_REG),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_REG),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE_REG),
.PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR_REG),
.PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL_REG),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG),
.PF0_DPA_CAP_VER (PF0_DPA_CAP_VER_REG),
.PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR_REG),
.PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE_REG),
.PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE_REG),
.PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE_REG),
.PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN_REG),
.PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_REG),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_REG),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_REG),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_REG),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT_REG),
.PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT_REG),
.PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR_REG),
.PF0_LTR_CAP_VER (PF0_LTR_CAP_VER_REG),
.PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR_REG),
.PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR_REG),
.PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET_REG),
.PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR_REG),
.PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET_REG),
.PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE_REG),
.PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP_REG),
.PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR_REG),
.PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP_REG),
.PF0_PB_CAP_DATA_REG_D0 (PF0_PB_CAP_DATA_REG_D0_REG),
.PF0_PB_CAP_DATA_REG_D0_SUSTAINED (PF0_PB_CAP_DATA_REG_D0_SUSTAINED_REG),
.PF0_PB_CAP_DATA_REG_D1 (PF0_PB_CAP_DATA_REG_D1_REG),
.PF0_PB_CAP_DATA_REG_D3HOT (PF0_PB_CAP_DATA_REG_D3HOT_REG),
.PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR_REG),
.PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED_REG),
.PF0_PB_CAP_VER (PF0_PB_CAP_VER_REG),
.PF0_PM_CAP_ID (PF0_PM_CAP_ID_REG),
.PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR_REG),
.PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0_REG),
.PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1_REG),
.PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT_REG),
.PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE_REG),
.PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID_REG),
.PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET_REG),
.PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE_REG),
.PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR_REG),
.PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0_REG),
.PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1_REG),
.PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2_REG),
.PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER_REG),
.PF0_RBAR_CONTROL_INDEX0 (PF0_RBAR_CONTROL_INDEX0_REG),
.PF0_RBAR_CONTROL_INDEX1 (PF0_RBAR_CONTROL_INDEX1_REG),
.PF0_RBAR_CONTROL_INDEX2 (PF0_RBAR_CONTROL_INDEX2_REG),
.PF0_RBAR_CONTROL_SIZE0 (PF0_RBAR_CONTROL_SIZE0_REG),
.PF0_RBAR_CONTROL_SIZE1 (PF0_RBAR_CONTROL_SIZE1_REG),
.PF0_RBAR_CONTROL_SIZE2 (PF0_RBAR_CONTROL_SIZE2_REG),
.PF0_RBAR_NUM (PF0_RBAR_NUM_REG),
.PF0_REVISION_ID (PF0_REVISION_ID_REG),
.PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR_REG),
.PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL_REG),
.PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL_REG),
.PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL_REG),
.PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL_REG),
.PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL_REG),
.PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE_REG),
.PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL_REG),
.PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF_REG),
.PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR_REG),
.PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF_REG),
.PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER_REG),
.PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET_REG),
.PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK_REG),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE_REG),
.PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID_REG),
.PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID_REG),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE_REG),
.PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE_REG),
.PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR_REG),
.PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL_REG),
.PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC_REG),
.PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE_REG),
.PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER_REG),
.PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE_REG),
.PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR_REG),
.PF0_VC_CAP_VER (PF0_VC_CAP_VER_REG),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE_REG),
.PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE_REG),
.PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR_REG),
.PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR_REG),
.PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC_REG),
.PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE_REG),
.PF1_BAR0_CONTROL (PF1_BAR0_CONTROL_REG),
.PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE_REG),
.PF1_BAR1_CONTROL (PF1_BAR1_CONTROL_REG),
.PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE_REG),
.PF1_BAR2_CONTROL (PF1_BAR2_CONTROL_REG),
.PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE_REG),
.PF1_BAR3_CONTROL (PF1_BAR3_CONTROL_REG),
.PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE_REG),
.PF1_BAR4_CONTROL (PF1_BAR4_CONTROL_REG),
.PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE_REG),
.PF1_BAR5_CONTROL (PF1_BAR5_CONTROL_REG),
.PF1_BIST_REGISTER (PF1_BIST_REGISTER_REG),
.PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER_REG),
.PF1_CLASS_CODE (PF1_CLASS_CODE_REG),
.PF1_DEVICE_ID (PF1_DEVICE_ID_REG),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE_REG),
.PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR_REG),
.PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL_REG),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG),
.PF1_DPA_CAP_VER (PF1_DPA_CAP_VER_REG),
.PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR_REG),
.PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE_REG),
.PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE_REG),
.PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE_REG),
.PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN_REG),
.PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR_REG),
.PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR_REG),
.PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET_REG),
.PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR_REG),
.PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET_REG),
.PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE_REG),
.PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP_REG),
.PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR_REG),
.PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP_REG),
.PF1_PB_CAP_DATA_REG_D0 (PF1_PB_CAP_DATA_REG_D0_REG),
.PF1_PB_CAP_DATA_REG_D0_SUSTAINED (PF1_PB_CAP_DATA_REG_D0_SUSTAINED_REG),
.PF1_PB_CAP_DATA_REG_D1 (PF1_PB_CAP_DATA_REG_D1_REG),
.PF1_PB_CAP_DATA_REG_D3HOT (PF1_PB_CAP_DATA_REG_D3HOT_REG),
.PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR_REG),
.PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED_REG),
.PF1_PB_CAP_VER (PF1_PB_CAP_VER_REG),
.PF1_PM_CAP_ID (PF1_PM_CAP_ID_REG),
.PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR_REG),
.PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID_REG),
.PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE_REG),
.PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR_REG),
.PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0_REG),
.PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1_REG),
.PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2_REG),
.PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER_REG),
.PF1_RBAR_CONTROL_INDEX0 (PF1_RBAR_CONTROL_INDEX0_REG),
.PF1_RBAR_CONTROL_INDEX1 (PF1_RBAR_CONTROL_INDEX1_REG),
.PF1_RBAR_CONTROL_INDEX2 (PF1_RBAR_CONTROL_INDEX2_REG),
.PF1_RBAR_CONTROL_SIZE0 (PF1_RBAR_CONTROL_SIZE0_REG),
.PF1_RBAR_CONTROL_SIZE1 (PF1_RBAR_CONTROL_SIZE1_REG),
.PF1_RBAR_CONTROL_SIZE2 (PF1_RBAR_CONTROL_SIZE2_REG),
.PF1_RBAR_NUM (PF1_RBAR_NUM_REG),
.PF1_REVISION_ID (PF1_REVISION_ID_REG),
.PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL_REG),
.PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL_REG),
.PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL_REG),
.PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL_REG),
.PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL_REG),
.PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE_REG),
.PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL_REG),
.PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF_REG),
.PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR_REG),
.PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF_REG),
.PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER_REG),
.PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET_REG),
.PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK_REG),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE_REG),
.PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID_REG),
.PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID_REG),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE_REG),
.PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE_REG),
.PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR_REG),
.PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL_REG),
.PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC_REG),
.PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE_REG),
.PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER_REG),
.PF2_AER_CAP_ECRC_CHECK_CAPABLE (PF2_AER_CAP_ECRC_CHECK_CAPABLE_REG),
.PF2_AER_CAP_ECRC_GEN_CAPABLE (PF2_AER_CAP_ECRC_GEN_CAPABLE_REG),
.PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR_REG),
.PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR_REG),
.PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC_REG),
.PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE_REG),
.PF2_BAR0_CONTROL (PF2_BAR0_CONTROL_REG),
.PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE_REG),
.PF2_BAR1_CONTROL (PF2_BAR1_CONTROL_REG),
.PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE_REG),
.PF2_BAR2_CONTROL (PF2_BAR2_CONTROL_REG),
.PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE_REG),
.PF2_BAR3_CONTROL (PF2_BAR3_CONTROL_REG),
.PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE_REG),
.PF2_BAR4_CONTROL (PF2_BAR4_CONTROL_REG),
.PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE_REG),
.PF2_BAR5_CONTROL (PF2_BAR5_CONTROL_REG),
.PF2_BIST_REGISTER (PF2_BIST_REGISTER_REG),
.PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER_REG),
.PF2_CLASS_CODE (PF2_CLASS_CODE_REG),
.PF2_DEVICE_ID (PF2_DEVICE_ID_REG),
.PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE_REG),
.PF2_DPA_CAP_NEXTPTR (PF2_DPA_CAP_NEXTPTR_REG),
.PF2_DPA_CAP_SUB_STATE_CONTROL (PF2_DPA_CAP_SUB_STATE_CONTROL_REG),
.PF2_DPA_CAP_SUB_STATE_CONTROL_EN (PF2_DPA_CAP_SUB_STATE_CONTROL_EN_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG),
.PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG),
.PF2_DPA_CAP_VER (PF2_DPA_CAP_VER_REG),
.PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR_REG),
.PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE_REG),
.PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE_REG),
.PF2_INTERRUPT_LINE (PF2_INTERRUPT_LINE_REG),
.PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN_REG),
.PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR_REG),
.PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR_REG),
.PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET_REG),
.PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR_REG),
.PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET_REG),
.PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE_REG),
.PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP_REG),
.PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR_REG),
.PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP_REG),
.PF2_PB_CAP_DATA_REG_D0 (PF2_PB_CAP_DATA_REG_D0_REG),
.PF2_PB_CAP_DATA_REG_D0_SUSTAINED (PF2_PB_CAP_DATA_REG_D0_SUSTAINED_REG),
.PF2_PB_CAP_DATA_REG_D1 (PF2_PB_CAP_DATA_REG_D1_REG),
.PF2_PB_CAP_DATA_REG_D3HOT (PF2_PB_CAP_DATA_REG_D3HOT_REG),
.PF2_PB_CAP_NEXTPTR (PF2_PB_CAP_NEXTPTR_REG),
.PF2_PB_CAP_SYSTEM_ALLOCATED (PF2_PB_CAP_SYSTEM_ALLOCATED_REG),
.PF2_PB_CAP_VER (PF2_PB_CAP_VER_REG),
.PF2_PM_CAP_ID (PF2_PM_CAP_ID_REG),
.PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR_REG),
.PF2_PM_CAP_VER_ID (PF2_PM_CAP_VER_ID_REG),
.PF2_RBAR_CAP_ENABLE (PF2_RBAR_CAP_ENABLE_REG),
.PF2_RBAR_CAP_NEXTPTR (PF2_RBAR_CAP_NEXTPTR_REG),
.PF2_RBAR_CAP_SIZE0 (PF2_RBAR_CAP_SIZE0_REG),
.PF2_RBAR_CAP_SIZE1 (PF2_RBAR_CAP_SIZE1_REG),
.PF2_RBAR_CAP_SIZE2 (PF2_RBAR_CAP_SIZE2_REG),
.PF2_RBAR_CAP_VER (PF2_RBAR_CAP_VER_REG),
.PF2_RBAR_CONTROL_INDEX0 (PF2_RBAR_CONTROL_INDEX0_REG),
.PF2_RBAR_CONTROL_INDEX1 (PF2_RBAR_CONTROL_INDEX1_REG),
.PF2_RBAR_CONTROL_INDEX2 (PF2_RBAR_CONTROL_INDEX2_REG),
.PF2_RBAR_CONTROL_SIZE0 (PF2_RBAR_CONTROL_SIZE0_REG),
.PF2_RBAR_CONTROL_SIZE1 (PF2_RBAR_CONTROL_SIZE1_REG),
.PF2_RBAR_CONTROL_SIZE2 (PF2_RBAR_CONTROL_SIZE2_REG),
.PF2_RBAR_NUM (PF2_RBAR_NUM_REG),
.PF2_REVISION_ID (PF2_REVISION_ID_REG),
.PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL_REG),
.PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL_REG),
.PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL_REG),
.PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL_REG),
.PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL_REG),
.PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE_REG),
.PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL_REG),
.PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF_REG),
.PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR_REG),
.PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF_REG),
.PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER_REG),
.PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET_REG),
.PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK_REG),
.PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE_REG),
.PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID_REG),
.PF2_SUBSYSTEM_ID (PF2_SUBSYSTEM_ID_REG),
.PF2_TPHR_CAP_DEV_SPECIFIC_MODE (PF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.PF2_TPHR_CAP_ENABLE (PF2_TPHR_CAP_ENABLE_REG),
.PF2_TPHR_CAP_INT_VEC_MODE (PF2_TPHR_CAP_INT_VEC_MODE_REG),
.PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR_REG),
.PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL_REG),
.PF2_TPHR_CAP_ST_TABLE_LOC (PF2_TPHR_CAP_ST_TABLE_LOC_REG),
.PF2_TPHR_CAP_ST_TABLE_SIZE (PF2_TPHR_CAP_ST_TABLE_SIZE_REG),
.PF2_TPHR_CAP_VER (PF2_TPHR_CAP_VER_REG),
.PF3_AER_CAP_ECRC_CHECK_CAPABLE (PF3_AER_CAP_ECRC_CHECK_CAPABLE_REG),
.PF3_AER_CAP_ECRC_GEN_CAPABLE (PF3_AER_CAP_ECRC_GEN_CAPABLE_REG),
.PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR_REG),
.PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR_REG),
.PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC_REG),
.PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE_REG),
.PF3_BAR0_CONTROL (PF3_BAR0_CONTROL_REG),
.PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE_REG),
.PF3_BAR1_CONTROL (PF3_BAR1_CONTROL_REG),
.PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE_REG),
.PF3_BAR2_CONTROL (PF3_BAR2_CONTROL_REG),
.PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE_REG),
.PF3_BAR3_CONTROL (PF3_BAR3_CONTROL_REG),
.PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE_REG),
.PF3_BAR4_CONTROL (PF3_BAR4_CONTROL_REG),
.PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE_REG),
.PF3_BAR5_CONTROL (PF3_BAR5_CONTROL_REG),
.PF3_BIST_REGISTER (PF3_BIST_REGISTER_REG),
.PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER_REG),
.PF3_CLASS_CODE (PF3_CLASS_CODE_REG),
.PF3_DEVICE_ID (PF3_DEVICE_ID_REG),
.PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE_REG),
.PF3_DPA_CAP_NEXTPTR (PF3_DPA_CAP_NEXTPTR_REG),
.PF3_DPA_CAP_SUB_STATE_CONTROL (PF3_DPA_CAP_SUB_STATE_CONTROL_REG),
.PF3_DPA_CAP_SUB_STATE_CONTROL_EN (PF3_DPA_CAP_SUB_STATE_CONTROL_EN_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6_REG),
.PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7_REG),
.PF3_DPA_CAP_VER (PF3_DPA_CAP_VER_REG),
.PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR_REG),
.PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE_REG),
.PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE_REG),
.PF3_INTERRUPT_LINE (PF3_INTERRUPT_LINE_REG),
.PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN_REG),
.PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR_REG),
.PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR_REG),
.PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET_REG),
.PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR_REG),
.PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET_REG),
.PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE_REG),
.PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP_REG),
.PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR_REG),
.PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP_REG),
.PF3_PB_CAP_DATA_REG_D0 (PF3_PB_CAP_DATA_REG_D0_REG),
.PF3_PB_CAP_DATA_REG_D0_SUSTAINED (PF3_PB_CAP_DATA_REG_D0_SUSTAINED_REG),
.PF3_PB_CAP_DATA_REG_D1 (PF3_PB_CAP_DATA_REG_D1_REG),
.PF3_PB_CAP_DATA_REG_D3HOT (PF3_PB_CAP_DATA_REG_D3HOT_REG),
.PF3_PB_CAP_NEXTPTR (PF3_PB_CAP_NEXTPTR_REG),
.PF3_PB_CAP_SYSTEM_ALLOCATED (PF3_PB_CAP_SYSTEM_ALLOCATED_REG),
.PF3_PB_CAP_VER (PF3_PB_CAP_VER_REG),
.PF3_PM_CAP_ID (PF3_PM_CAP_ID_REG),
.PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR_REG),
.PF3_PM_CAP_VER_ID (PF3_PM_CAP_VER_ID_REG),
.PF3_RBAR_CAP_ENABLE (PF3_RBAR_CAP_ENABLE_REG),
.PF3_RBAR_CAP_NEXTPTR (PF3_RBAR_CAP_NEXTPTR_REG),
.PF3_RBAR_CAP_SIZE0 (PF3_RBAR_CAP_SIZE0_REG),
.PF3_RBAR_CAP_SIZE1 (PF3_RBAR_CAP_SIZE1_REG),
.PF3_RBAR_CAP_SIZE2 (PF3_RBAR_CAP_SIZE2_REG),
.PF3_RBAR_CAP_VER (PF3_RBAR_CAP_VER_REG),
.PF3_RBAR_CONTROL_INDEX0 (PF3_RBAR_CONTROL_INDEX0_REG),
.PF3_RBAR_CONTROL_INDEX1 (PF3_RBAR_CONTROL_INDEX1_REG),
.PF3_RBAR_CONTROL_INDEX2 (PF3_RBAR_CONTROL_INDEX2_REG),
.PF3_RBAR_CONTROL_SIZE0 (PF3_RBAR_CONTROL_SIZE0_REG),
.PF3_RBAR_CONTROL_SIZE1 (PF3_RBAR_CONTROL_SIZE1_REG),
.PF3_RBAR_CONTROL_SIZE2 (PF3_RBAR_CONTROL_SIZE2_REG),
.PF3_RBAR_NUM (PF3_RBAR_NUM_REG),
.PF3_REVISION_ID (PF3_REVISION_ID_REG),
.PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL_REG),
.PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL_REG),
.PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL_REG),
.PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL_REG),
.PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL_REG),
.PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE_REG),
.PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL_REG),
.PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF_REG),
.PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR_REG),
.PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF_REG),
.PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER_REG),
.PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET_REG),
.PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK_REG),
.PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE_REG),
.PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID_REG),
.PF3_SUBSYSTEM_ID (PF3_SUBSYSTEM_ID_REG),
.PF3_TPHR_CAP_DEV_SPECIFIC_MODE (PF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.PF3_TPHR_CAP_ENABLE (PF3_TPHR_CAP_ENABLE_REG),
.PF3_TPHR_CAP_INT_VEC_MODE (PF3_TPHR_CAP_INT_VEC_MODE_REG),
.PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR_REG),
.PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL_REG),
.PF3_TPHR_CAP_ST_TABLE_LOC (PF3_TPHR_CAP_ST_TABLE_LOC_REG),
.PF3_TPHR_CAP_ST_TABLE_SIZE (PF3_TPHR_CAP_ST_TABLE_SIZE_REG),
.PF3_TPHR_CAP_VER (PF3_TPHR_CAP_VER_REG),
.PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3_REG),
.PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2_REG),
.PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0_REG),
.PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE_REG),
.PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP (PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP_REG),
.PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR_REG),
.PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING_REG),
.PL_DISABLE_SYNC_HEADER_FRAMING_ERROR (PL_DISABLE_SYNC_HEADER_FRAMING_ERROR_REG),
.PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE_REG),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK_REG),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK_REG),
.PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT_REG),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT_REG),
.PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23_REG),
.PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT (PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT_REG),
.PL_EQ_DEFAULT_GEN3_TX_PRESET (PL_EQ_DEFAULT_GEN3_TX_PRESET_REG),
.PL_EQ_PHASE01_RX_ADAPT (PL_EQ_PHASE01_RX_ADAPT_REG),
.PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE_REG),
.PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL_REG),
.PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL_REG),
.PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL_REG),
.PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL_REG),
.PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL_REG),
.PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL_REG),
.PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL_REG),
.PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL_REG),
.PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED_REG),
.PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH_REG),
.PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1_REG),
.PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2_REG),
.PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3_REG),
.PL_N_FTS_GEN1 (PL_N_FTS_GEN1_REG),
.PL_N_FTS_GEN2 (PL_N_FTS_GEN2_REG),
.PL_N_FTS_GEN3 (PL_N_FTS_GEN3_REG),
.PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS_REG),
.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING_REG),
.PL_UPSTREAM_FACING (PL_UPSTREAM_FACING_REG),
.PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT_REG),
.PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY_REG),
.PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY_REG),
.PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE_REG),
.PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY_REG),
.PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY_REG),
.PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY_REG),
.SPARE_BIT0 (SPARE_BIT0_REG),
.SPARE_BIT1 (SPARE_BIT1_REG),
.SPARE_BIT2 (SPARE_BIT2_REG),
.SPARE_BIT3 (SPARE_BIT3_REG),
.SPARE_BIT4 (SPARE_BIT4_REG),
.SPARE_BIT5 (SPARE_BIT5_REG),
.SPARE_BIT6 (SPARE_BIT6_REG),
.SPARE_BIT7 (SPARE_BIT7_REG),
.SPARE_BIT8 (SPARE_BIT8_REG),
.SPARE_BYTE0 (SPARE_BYTE0_REG),
.SPARE_BYTE1 (SPARE_BYTE1_REG),
.SPARE_BYTE2 (SPARE_BYTE2_REG),
.SPARE_BYTE3 (SPARE_BYTE3_REG),
.SPARE_WORD0 (SPARE_WORD0_REG),
.SPARE_WORD1 (SPARE_WORD1_REG),
.SPARE_WORD2 (SPARE_WORD2_REG),
.SPARE_WORD3 (SPARE_WORD3_REG),
.SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE_REG),
.TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG),
.TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0_REG),
.TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1_REG),
.TL_CREDITS_CD (TL_CREDITS_CD_REG),
.TL_CREDITS_CH (TL_CREDITS_CH_REG),
.TL_CREDITS_NPD (TL_CREDITS_NPD_REG),
.TL_CREDITS_NPH (TL_CREDITS_NPH_REG),
.TL_CREDITS_PD (TL_CREDITS_PD_REG),
.TL_CREDITS_PH (TL_CREDITS_PH_REG),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_REG),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_REG),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_REG),
.TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE_REG),
.TL_PF_ENABLE_REG (TL_PF_ENABLE_REG_REG),
.TL_TAG_MGMT_ENABLE (TL_TAG_MGMT_ENABLE_REG),
.TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY_REG),
.TWO_LAYER_MODE_DLCMSM_ENABLE (TWO_LAYER_MODE_DLCMSM_ENABLE_REG),
.TWO_LAYER_MODE_ENABLE (TWO_LAYER_MODE_ENABLE_REG),
.TWO_LAYER_MODE_WIDTH_256 (TWO_LAYER_MODE_WIDTH_256_REG),
.VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR_REG),
.VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER_REG),
.VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR_REG),
.VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET_REG),
.VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR_REG),
.VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET_REG),
.VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE_REG),
.VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP_REG),
.VF0_PM_CAP_ID (VF0_PM_CAP_ID_REG),
.VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR_REG),
.VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID_REG),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE_REG),
.VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE_REG),
.VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR_REG),
.VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL_REG),
.VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC_REG),
.VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER_REG),
.VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR_REG),
.VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR_REG),
.VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET_REG),
.VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR_REG),
.VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET_REG),
.VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE_REG),
.VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP_REG),
.VF1_PM_CAP_ID (VF1_PM_CAP_ID_REG),
.VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR_REG),
.VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID_REG),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE_REG),
.VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE_REG),
.VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR_REG),
.VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL_REG),
.VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC_REG),
.VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER_REG),
.VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR_REG),
.VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR_REG),
.VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET_REG),
.VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR_REG),
.VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET_REG),
.VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE_REG),
.VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP_REG),
.VF2_PM_CAP_ID (VF2_PM_CAP_ID_REG),
.VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR_REG),
.VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID_REG),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE_REG),
.VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE_REG),
.VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR_REG),
.VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL_REG),
.VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC_REG),
.VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER_REG),
.VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR_REG),
.VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR_REG),
.VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET_REG),
.VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR_REG),
.VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET_REG),
.VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE_REG),
.VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP_REG),
.VF3_PM_CAP_ID (VF3_PM_CAP_ID_REG),
.VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR_REG),
.VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID_REG),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE_REG),
.VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE_REG),
.VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR_REG),
.VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL_REG),
.VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC_REG),
.VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER_REG),
.VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR_REG),
.VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR_REG),
.VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET_REG),
.VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR_REG),
.VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET_REG),
.VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE_REG),
.VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP_REG),
.VF4_PM_CAP_ID (VF4_PM_CAP_ID_REG),
.VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR_REG),
.VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID_REG),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE_REG),
.VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE_REG),
.VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR_REG),
.VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL_REG),
.VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC_REG),
.VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER_REG),
.VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR_REG),
.VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR_REG),
.VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET_REG),
.VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR_REG),
.VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET_REG),
.VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE_REG),
.VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP_REG),
.VF5_PM_CAP_ID (VF5_PM_CAP_ID_REG),
.VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR_REG),
.VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID_REG),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE_REG),
.VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE_REG),
.VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR_REG),
.VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL_REG),
.VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC_REG),
.VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER_REG),
.VF6_ARI_CAP_NEXTPTR (VF6_ARI_CAP_NEXTPTR_REG),
.VF6_MSIX_CAP_PBA_BIR (VF6_MSIX_CAP_PBA_BIR_REG),
.VF6_MSIX_CAP_PBA_OFFSET (VF6_MSIX_CAP_PBA_OFFSET_REG),
.VF6_MSIX_CAP_TABLE_BIR (VF6_MSIX_CAP_TABLE_BIR_REG),
.VF6_MSIX_CAP_TABLE_OFFSET (VF6_MSIX_CAP_TABLE_OFFSET_REG),
.VF6_MSIX_CAP_TABLE_SIZE (VF6_MSIX_CAP_TABLE_SIZE_REG),
.VF6_MSI_CAP_MULTIMSGCAP (VF6_MSI_CAP_MULTIMSGCAP_REG),
.VF6_PM_CAP_ID (VF6_PM_CAP_ID_REG),
.VF6_PM_CAP_NEXTPTR (VF6_PM_CAP_NEXTPTR_REG),
.VF6_PM_CAP_VER_ID (VF6_PM_CAP_VER_ID_REG),
.VF6_TPHR_CAP_DEV_SPECIFIC_MODE (VF6_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF6_TPHR_CAP_ENABLE (VF6_TPHR_CAP_ENABLE_REG),
.VF6_TPHR_CAP_INT_VEC_MODE (VF6_TPHR_CAP_INT_VEC_MODE_REG),
.VF6_TPHR_CAP_NEXTPTR (VF6_TPHR_CAP_NEXTPTR_REG),
.VF6_TPHR_CAP_ST_MODE_SEL (VF6_TPHR_CAP_ST_MODE_SEL_REG),
.VF6_TPHR_CAP_ST_TABLE_LOC (VF6_TPHR_CAP_ST_TABLE_LOC_REG),
.VF6_TPHR_CAP_ST_TABLE_SIZE (VF6_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF6_TPHR_CAP_VER (VF6_TPHR_CAP_VER_REG),
.VF7_ARI_CAP_NEXTPTR (VF7_ARI_CAP_NEXTPTR_REG),
.VF7_MSIX_CAP_PBA_BIR (VF7_MSIX_CAP_PBA_BIR_REG),
.VF7_MSIX_CAP_PBA_OFFSET (VF7_MSIX_CAP_PBA_OFFSET_REG),
.VF7_MSIX_CAP_TABLE_BIR (VF7_MSIX_CAP_TABLE_BIR_REG),
.VF7_MSIX_CAP_TABLE_OFFSET (VF7_MSIX_CAP_TABLE_OFFSET_REG),
.VF7_MSIX_CAP_TABLE_SIZE (VF7_MSIX_CAP_TABLE_SIZE_REG),
.VF7_MSI_CAP_MULTIMSGCAP (VF7_MSI_CAP_MULTIMSGCAP_REG),
.VF7_PM_CAP_ID (VF7_PM_CAP_ID_REG),
.VF7_PM_CAP_NEXTPTR (VF7_PM_CAP_NEXTPTR_REG),
.VF7_PM_CAP_VER_ID (VF7_PM_CAP_VER_ID_REG),
.VF7_TPHR_CAP_DEV_SPECIFIC_MODE (VF7_TPHR_CAP_DEV_SPECIFIC_MODE_REG),
.VF7_TPHR_CAP_ENABLE (VF7_TPHR_CAP_ENABLE_REG),
.VF7_TPHR_CAP_INT_VEC_MODE (VF7_TPHR_CAP_INT_VEC_MODE_REG),
.VF7_TPHR_CAP_NEXTPTR (VF7_TPHR_CAP_NEXTPTR_REG),
.VF7_TPHR_CAP_ST_MODE_SEL (VF7_TPHR_CAP_ST_MODE_SEL_REG),
.VF7_TPHR_CAP_ST_TABLE_LOC (VF7_TPHR_CAP_ST_TABLE_LOC_REG),
.VF7_TPHR_CAP_ST_TABLE_SIZE (VF7_TPHR_CAP_ST_TABLE_SIZE_REG),
.VF7_TPHR_CAP_VER (VF7_TPHR_CAP_VER_REG),
.CFGCURRENTSPEED (CFGCURRENTSPEED_out),
.CFGDPASUBSTATECHANGE (CFGDPASUBSTATECHANGE_out),
.CFGERRCOROUT (CFGERRCOROUT_out),
.CFGERRFATALOUT (CFGERRFATALOUT_out),
.CFGERRNONFATALOUT (CFGERRNONFATALOUT_out),
.CFGEXTFUNCTIONNUMBER (CFGEXTFUNCTIONNUMBER_out),
.CFGEXTREADRECEIVED (CFGEXTREADRECEIVED_out),
.CFGEXTREGISTERNUMBER (CFGEXTREGISTERNUMBER_out),
.CFGEXTWRITEBYTEENABLE (CFGEXTWRITEBYTEENABLE_out),
.CFGEXTWRITEDATA (CFGEXTWRITEDATA_out),
.CFGEXTWRITERECEIVED (CFGEXTWRITERECEIVED_out),
.CFGFCCPLD (CFGFCCPLD_out),
.CFGFCCPLH (CFGFCCPLH_out),
.CFGFCNPD (CFGFCNPD_out),
.CFGFCNPH (CFGFCNPH_out),
.CFGFCPD (CFGFCPD_out),
.CFGFCPH (CFGFCPH_out),
.CFGFLRINPROCESS (CFGFLRINPROCESS_out),
.CFGFUNCTIONPOWERSTATE (CFGFUNCTIONPOWERSTATE_out),
.CFGFUNCTIONSTATUS (CFGFUNCTIONSTATUS_out),
.CFGHOTRESETOUT (CFGHOTRESETOUT_out),
.CFGINTERRUPTMSIDATA (CFGINTERRUPTMSIDATA_out),
.CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE_out),
.CFGINTERRUPTMSIFAIL (CFGINTERRUPTMSIFAIL_out),
.CFGINTERRUPTMSIMASKUPDATE (CFGINTERRUPTMSIMASKUPDATE_out),
.CFGINTERRUPTMSIMMENABLE (CFGINTERRUPTMSIMMENABLE_out),
.CFGINTERRUPTMSISENT (CFGINTERRUPTMSISENT_out),
.CFGINTERRUPTMSIVFENABLE (CFGINTERRUPTMSIVFENABLE_out),
.CFGINTERRUPTMSIXENABLE (CFGINTERRUPTMSIXENABLE_out),
.CFGINTERRUPTMSIXFAIL (CFGINTERRUPTMSIXFAIL_out),
.CFGINTERRUPTMSIXMASK (CFGINTERRUPTMSIXMASK_out),
.CFGINTERRUPTMSIXSENT (CFGINTERRUPTMSIXSENT_out),
.CFGINTERRUPTMSIXVFENABLE (CFGINTERRUPTMSIXVFENABLE_out),
.CFGINTERRUPTMSIXVFMASK (CFGINTERRUPTMSIXVFMASK_out),
.CFGINTERRUPTSENT (CFGINTERRUPTSENT_out),
.CFGLINKPOWERSTATE (CFGLINKPOWERSTATE_out),
.CFGLOCALERROR (CFGLOCALERROR_out),
.CFGLTRENABLE (CFGLTRENABLE_out),
.CFGLTSSMSTATE (CFGLTSSMSTATE_out),
.CFGMAXPAYLOAD (CFGMAXPAYLOAD_out),
.CFGMAXREADREQ (CFGMAXREADREQ_out),
.CFGMGMTREADDATA (CFGMGMTREADDATA_out),
.CFGMGMTREADWRITEDONE (CFGMGMTREADWRITEDONE_out),
.CFGMSGRECEIVED (CFGMSGRECEIVED_out),
.CFGMSGRECEIVEDDATA (CFGMSGRECEIVEDDATA_out),
.CFGMSGRECEIVEDTYPE (CFGMSGRECEIVEDTYPE_out),
.CFGMSGTRANSMITDONE (CFGMSGTRANSMITDONE_out),
.CFGNEGOTIATEDWIDTH (CFGNEGOTIATEDWIDTH_out),
.CFGOBFFENABLE (CFGOBFFENABLE_out),
.CFGPERFUNCSTATUSDATA (CFGPERFUNCSTATUSDATA_out),
.CFGPERFUNCTIONUPDATEDONE (CFGPERFUNCTIONUPDATEDONE_out),
.CFGPHYLINKDOWN (CFGPHYLINKDOWN_out),
.CFGPHYLINKSTATUS (CFGPHYLINKSTATUS_out),
.CFGPLSTATUSCHANGE (CFGPLSTATUSCHANGE_out),
.CFGPOWERSTATECHANGEINTERRUPT (CFGPOWERSTATECHANGEINTERRUPT_out),
.CFGRCBSTATUS (CFGRCBSTATUS_out),
.CFGTPHFUNCTIONNUM (CFGTPHFUNCTIONNUM_out),
.CFGTPHREQUESTERENABLE (CFGTPHREQUESTERENABLE_out),
.CFGTPHSTMODE (CFGTPHSTMODE_out),
.CFGTPHSTTADDRESS (CFGTPHSTTADDRESS_out),
.CFGTPHSTTREADENABLE (CFGTPHSTTREADENABLE_out),
.CFGTPHSTTWRITEBYTEVALID (CFGTPHSTTWRITEBYTEVALID_out),
.CFGTPHSTTWRITEDATA (CFGTPHSTTWRITEDATA_out),
.CFGTPHSTTWRITEENABLE (CFGTPHSTTWRITEENABLE_out),
.CFGVFFLRINPROCESS (CFGVFFLRINPROCESS_out),
.CFGVFPOWERSTATE (CFGVFPOWERSTATE_out),
.CFGVFSTATUS (CFGVFSTATUS_out),
.CFGVFTPHREQUESTERENABLE (CFGVFTPHREQUESTERENABLE_out),
.CFGVFTPHSTMODE (CFGVFTPHSTMODE_out),
.CONFMCAPDESIGNSWITCH (CONFMCAPDESIGNSWITCH_out),
.CONFMCAPEOS (CONFMCAPEOS_out),
.CONFMCAPINUSEBYPCIE (CONFMCAPINUSEBYPCIE_out),
.CONFREQREADY (CONFREQREADY_out),
.CONFRESPRDATA (CONFRESPRDATA_out),
.CONFRESPVALID (CONFRESPVALID_out),
.DBGDATAOUT (DBGDATAOUT_out),
.DBGMCAPCSB (DBGMCAPCSB_out),
.DBGMCAPDATA (DBGMCAPDATA_out),
.DBGMCAPEOS (DBGMCAPEOS_out),
.DBGMCAPERROR (DBGMCAPERROR_out),
.DBGMCAPMODE (DBGMCAPMODE_out),
.DBGMCAPRDATAVALID (DBGMCAPRDATAVALID_out),
.DBGMCAPRDWRB (DBGMCAPRDWRB_out),
.DBGMCAPRESET (DBGMCAPRESET_out),
.DBGPLDATABLOCKRECEIVEDAFTEREDS (DBGPLDATABLOCKRECEIVEDAFTEREDS_out),
.DBGPLGEN3FRAMINGERRORDETECTED (DBGPLGEN3FRAMINGERRORDETECTED_out),
.DBGPLGEN3SYNCHEADERERRORDETECTED (DBGPLGEN3SYNCHEADERERRORDETECTED_out),
.DBGPLINFERREDRXELECTRICALIDLE (DBGPLINFERREDRXELECTRICALIDLE_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.LL2LMMASTERTLPSENT0 (LL2LMMASTERTLPSENT0_out),
.LL2LMMASTERTLPSENT1 (LL2LMMASTERTLPSENT1_out),
.LL2LMMASTERTLPSENTTLPID0 (LL2LMMASTERTLPSENTTLPID0_out),
.LL2LMMASTERTLPSENTTLPID1 (LL2LMMASTERTLPSENTTLPID1_out),
.LL2LMMAXISRXTDATA (LL2LMMAXISRXTDATA_out),
.LL2LMMAXISRXTUSER (LL2LMMAXISRXTUSER_out),
.LL2LMMAXISRXTVALID (LL2LMMAXISRXTVALID_out),
.LL2LMSAXISTXTREADY (LL2LMSAXISTXTREADY_out),
.MAXISCQTDATA (MAXISCQTDATA_out),
.MAXISCQTKEEP (MAXISCQTKEEP_out),
.MAXISCQTLAST (MAXISCQTLAST_out),
.MAXISCQTUSER (MAXISCQTUSER_out),
.MAXISCQTVALID (MAXISCQTVALID_out),
.MAXISRCTDATA (MAXISRCTDATA_out),
.MAXISRCTKEEP (MAXISRCTKEEP_out),
.MAXISRCTLAST (MAXISRCTLAST_out),
.MAXISRCTUSER (MAXISRCTUSER_out),
.MAXISRCTVALID (MAXISRCTVALID_out),
.MICOMPLETIONRAMREADADDRESSAL (MICOMPLETIONRAMREADADDRESSAL_out),
.MICOMPLETIONRAMREADADDRESSAU (MICOMPLETIONRAMREADADDRESSAU_out),
.MICOMPLETIONRAMREADADDRESSBL (MICOMPLETIONRAMREADADDRESSBL_out),
.MICOMPLETIONRAMREADADDRESSBU (MICOMPLETIONRAMREADADDRESSBU_out),
.MICOMPLETIONRAMREADENABLEL (MICOMPLETIONRAMREADENABLEL_out),
.MICOMPLETIONRAMREADENABLEU (MICOMPLETIONRAMREADENABLEU_out),
.MICOMPLETIONRAMWRITEADDRESSAL (MICOMPLETIONRAMWRITEADDRESSAL_out),
.MICOMPLETIONRAMWRITEADDRESSAU (MICOMPLETIONRAMWRITEADDRESSAU_out),
.MICOMPLETIONRAMWRITEADDRESSBL (MICOMPLETIONRAMWRITEADDRESSBL_out),
.MICOMPLETIONRAMWRITEADDRESSBU (MICOMPLETIONRAMWRITEADDRESSBU_out),
.MICOMPLETIONRAMWRITEDATAL (MICOMPLETIONRAMWRITEDATAL_out),
.MICOMPLETIONRAMWRITEDATAU (MICOMPLETIONRAMWRITEDATAU_out),
.MICOMPLETIONRAMWRITEENABLEL (MICOMPLETIONRAMWRITEENABLEL_out),
.MICOMPLETIONRAMWRITEENABLEU (MICOMPLETIONRAMWRITEENABLEU_out),
.MIREPLAYRAMADDRESS (MIREPLAYRAMADDRESS_out),
.MIREPLAYRAMREADENABLE (MIREPLAYRAMREADENABLE_out),
.MIREPLAYRAMWRITEDATA (MIREPLAYRAMWRITEDATA_out),
.MIREPLAYRAMWRITEENABLE (MIREPLAYRAMWRITEENABLE_out),
.MIREQUESTRAMREADADDRESSA (MIREQUESTRAMREADADDRESSA_out),
.MIREQUESTRAMREADADDRESSB (MIREQUESTRAMREADADDRESSB_out),
.MIREQUESTRAMREADENABLE (MIREQUESTRAMREADENABLE_out),
.MIREQUESTRAMWRITEADDRESSA (MIREQUESTRAMWRITEADDRESSA_out),
.MIREQUESTRAMWRITEADDRESSB (MIREQUESTRAMWRITEADDRESSB_out),
.MIREQUESTRAMWRITEDATA (MIREQUESTRAMWRITEDATA_out),
.MIREQUESTRAMWRITEENABLE (MIREQUESTRAMWRITEENABLE_out),
.PCIECQNPREQCOUNT (PCIECQNPREQCOUNT_out),
.PCIEPERST0B (PCIEPERST0B_out),
.PCIEPERST1B (PCIEPERST1B_out),
.PCIERQSEQNUM (PCIERQSEQNUM_out),
.PCIERQSEQNUMVLD (PCIERQSEQNUMVLD_out),
.PCIERQTAG (PCIERQTAG_out),
.PCIERQTAGAV (PCIERQTAGAV_out),
.PCIERQTAGVLD (PCIERQTAGVLD_out),
.PCIETFCNPDAV (PCIETFCNPDAV_out),
.PCIETFCNPHAV (PCIETFCNPHAV_out),
.PIPERX0EQCONTROL (PIPERX0EQCONTROL_out),
.PIPERX0EQLPLFFS (PIPERX0EQLPLFFS_out),
.PIPERX0EQLPTXPRESET (PIPERX0EQLPTXPRESET_out),
.PIPERX0EQPRESET (PIPERX0EQPRESET_out),
.PIPERX0POLARITY (PIPERX0POLARITY_out),
.PIPERX1EQCONTROL (PIPERX1EQCONTROL_out),
.PIPERX1EQLPLFFS (PIPERX1EQLPLFFS_out),
.PIPERX1EQLPTXPRESET (PIPERX1EQLPTXPRESET_out),
.PIPERX1EQPRESET (PIPERX1EQPRESET_out),
.PIPERX1POLARITY (PIPERX1POLARITY_out),
.PIPERX2EQCONTROL (PIPERX2EQCONTROL_out),
.PIPERX2EQLPLFFS (PIPERX2EQLPLFFS_out),
.PIPERX2EQLPTXPRESET (PIPERX2EQLPTXPRESET_out),
.PIPERX2EQPRESET (PIPERX2EQPRESET_out),
.PIPERX2POLARITY (PIPERX2POLARITY_out),
.PIPERX3EQCONTROL (PIPERX3EQCONTROL_out),
.PIPERX3EQLPLFFS (PIPERX3EQLPLFFS_out),
.PIPERX3EQLPTXPRESET (PIPERX3EQLPTXPRESET_out),
.PIPERX3EQPRESET (PIPERX3EQPRESET_out),
.PIPERX3POLARITY (PIPERX3POLARITY_out),
.PIPERX4EQCONTROL (PIPERX4EQCONTROL_out),
.PIPERX4EQLPLFFS (PIPERX4EQLPLFFS_out),
.PIPERX4EQLPTXPRESET (PIPERX4EQLPTXPRESET_out),
.PIPERX4EQPRESET (PIPERX4EQPRESET_out),
.PIPERX4POLARITY (PIPERX4POLARITY_out),
.PIPERX5EQCONTROL (PIPERX5EQCONTROL_out),
.PIPERX5EQLPLFFS (PIPERX5EQLPLFFS_out),
.PIPERX5EQLPTXPRESET (PIPERX5EQLPTXPRESET_out),
.PIPERX5EQPRESET (PIPERX5EQPRESET_out),
.PIPERX5POLARITY (PIPERX5POLARITY_out),
.PIPERX6EQCONTROL (PIPERX6EQCONTROL_out),
.PIPERX6EQLPLFFS (PIPERX6EQLPLFFS_out),
.PIPERX6EQLPTXPRESET (PIPERX6EQLPTXPRESET_out),
.PIPERX6EQPRESET (PIPERX6EQPRESET_out),
.PIPERX6POLARITY (PIPERX6POLARITY_out),
.PIPERX7EQCONTROL (PIPERX7EQCONTROL_out),
.PIPERX7EQLPLFFS (PIPERX7EQLPLFFS_out),
.PIPERX7EQLPTXPRESET (PIPERX7EQLPTXPRESET_out),
.PIPERX7EQPRESET (PIPERX7EQPRESET_out),
.PIPERX7POLARITY (PIPERX7POLARITY_out),
.PIPETX0CHARISK (PIPETX0CHARISK_out),
.PIPETX0COMPLIANCE (PIPETX0COMPLIANCE_out),
.PIPETX0DATA (PIPETX0DATA_out),
.PIPETX0DATAVALID (PIPETX0DATAVALID_out),
.PIPETX0DEEMPH (PIPETX0DEEMPH_out),
.PIPETX0ELECIDLE (PIPETX0ELECIDLE_out),
.PIPETX0EQCONTROL (PIPETX0EQCONTROL_out),
.PIPETX0EQDEEMPH (PIPETX0EQDEEMPH_out),
.PIPETX0EQPRESET (PIPETX0EQPRESET_out),
.PIPETX0MARGIN (PIPETX0MARGIN_out),
.PIPETX0POWERDOWN (PIPETX0POWERDOWN_out),
.PIPETX0RATE (PIPETX0RATE_out),
.PIPETX0RCVRDET (PIPETX0RCVRDET_out),
.PIPETX0RESET (PIPETX0RESET_out),
.PIPETX0STARTBLOCK (PIPETX0STARTBLOCK_out),
.PIPETX0SWING (PIPETX0SWING_out),
.PIPETX0SYNCHEADER (PIPETX0SYNCHEADER_out),
.PIPETX1CHARISK (PIPETX1CHARISK_out),
.PIPETX1COMPLIANCE (PIPETX1COMPLIANCE_out),
.PIPETX1DATA (PIPETX1DATA_out),
.PIPETX1DATAVALID (PIPETX1DATAVALID_out),
.PIPETX1DEEMPH (PIPETX1DEEMPH_out),
.PIPETX1ELECIDLE (PIPETX1ELECIDLE_out),
.PIPETX1EQCONTROL (PIPETX1EQCONTROL_out),
.PIPETX1EQDEEMPH (PIPETX1EQDEEMPH_out),
.PIPETX1EQPRESET (PIPETX1EQPRESET_out),
.PIPETX1MARGIN (PIPETX1MARGIN_out),
.PIPETX1POWERDOWN (PIPETX1POWERDOWN_out),
.PIPETX1RATE (PIPETX1RATE_out),
.PIPETX1RCVRDET (PIPETX1RCVRDET_out),
.PIPETX1RESET (PIPETX1RESET_out),
.PIPETX1STARTBLOCK (PIPETX1STARTBLOCK_out),
.PIPETX1SWING (PIPETX1SWING_out),
.PIPETX1SYNCHEADER (PIPETX1SYNCHEADER_out),
.PIPETX2CHARISK (PIPETX2CHARISK_out),
.PIPETX2COMPLIANCE (PIPETX2COMPLIANCE_out),
.PIPETX2DATA (PIPETX2DATA_out),
.PIPETX2DATAVALID (PIPETX2DATAVALID_out),
.PIPETX2DEEMPH (PIPETX2DEEMPH_out),
.PIPETX2ELECIDLE (PIPETX2ELECIDLE_out),
.PIPETX2EQCONTROL (PIPETX2EQCONTROL_out),
.PIPETX2EQDEEMPH (PIPETX2EQDEEMPH_out),
.PIPETX2EQPRESET (PIPETX2EQPRESET_out),
.PIPETX2MARGIN (PIPETX2MARGIN_out),
.PIPETX2POWERDOWN (PIPETX2POWERDOWN_out),
.PIPETX2RATE (PIPETX2RATE_out),
.PIPETX2RCVRDET (PIPETX2RCVRDET_out),
.PIPETX2RESET (PIPETX2RESET_out),
.PIPETX2STARTBLOCK (PIPETX2STARTBLOCK_out),
.PIPETX2SWING (PIPETX2SWING_out),
.PIPETX2SYNCHEADER (PIPETX2SYNCHEADER_out),
.PIPETX3CHARISK (PIPETX3CHARISK_out),
.PIPETX3COMPLIANCE (PIPETX3COMPLIANCE_out),
.PIPETX3DATA (PIPETX3DATA_out),
.PIPETX3DATAVALID (PIPETX3DATAVALID_out),
.PIPETX3DEEMPH (PIPETX3DEEMPH_out),
.PIPETX3ELECIDLE (PIPETX3ELECIDLE_out),
.PIPETX3EQCONTROL (PIPETX3EQCONTROL_out),
.PIPETX3EQDEEMPH (PIPETX3EQDEEMPH_out),
.PIPETX3EQPRESET (PIPETX3EQPRESET_out),
.PIPETX3MARGIN (PIPETX3MARGIN_out),
.PIPETX3POWERDOWN (PIPETX3POWERDOWN_out),
.PIPETX3RATE (PIPETX3RATE_out),
.PIPETX3RCVRDET (PIPETX3RCVRDET_out),
.PIPETX3RESET (PIPETX3RESET_out),
.PIPETX3STARTBLOCK (PIPETX3STARTBLOCK_out),
.PIPETX3SWING (PIPETX3SWING_out),
.PIPETX3SYNCHEADER (PIPETX3SYNCHEADER_out),
.PIPETX4CHARISK (PIPETX4CHARISK_out),
.PIPETX4COMPLIANCE (PIPETX4COMPLIANCE_out),
.PIPETX4DATA (PIPETX4DATA_out),
.PIPETX4DATAVALID (PIPETX4DATAVALID_out),
.PIPETX4DEEMPH (PIPETX4DEEMPH_out),
.PIPETX4ELECIDLE (PIPETX4ELECIDLE_out),
.PIPETX4EQCONTROL (PIPETX4EQCONTROL_out),
.PIPETX4EQDEEMPH (PIPETX4EQDEEMPH_out),
.PIPETX4EQPRESET (PIPETX4EQPRESET_out),
.PIPETX4MARGIN (PIPETX4MARGIN_out),
.PIPETX4POWERDOWN (PIPETX4POWERDOWN_out),
.PIPETX4RATE (PIPETX4RATE_out),
.PIPETX4RCVRDET (PIPETX4RCVRDET_out),
.PIPETX4RESET (PIPETX4RESET_out),
.PIPETX4STARTBLOCK (PIPETX4STARTBLOCK_out),
.PIPETX4SWING (PIPETX4SWING_out),
.PIPETX4SYNCHEADER (PIPETX4SYNCHEADER_out),
.PIPETX5CHARISK (PIPETX5CHARISK_out),
.PIPETX5COMPLIANCE (PIPETX5COMPLIANCE_out),
.PIPETX5DATA (PIPETX5DATA_out),
.PIPETX5DATAVALID (PIPETX5DATAVALID_out),
.PIPETX5DEEMPH (PIPETX5DEEMPH_out),
.PIPETX5ELECIDLE (PIPETX5ELECIDLE_out),
.PIPETX5EQCONTROL (PIPETX5EQCONTROL_out),
.PIPETX5EQDEEMPH (PIPETX5EQDEEMPH_out),
.PIPETX5EQPRESET (PIPETX5EQPRESET_out),
.PIPETX5MARGIN (PIPETX5MARGIN_out),
.PIPETX5POWERDOWN (PIPETX5POWERDOWN_out),
.PIPETX5RATE (PIPETX5RATE_out),
.PIPETX5RCVRDET (PIPETX5RCVRDET_out),
.PIPETX5RESET (PIPETX5RESET_out),
.PIPETX5STARTBLOCK (PIPETX5STARTBLOCK_out),
.PIPETX5SWING (PIPETX5SWING_out),
.PIPETX5SYNCHEADER (PIPETX5SYNCHEADER_out),
.PIPETX6CHARISK (PIPETX6CHARISK_out),
.PIPETX6COMPLIANCE (PIPETX6COMPLIANCE_out),
.PIPETX6DATA (PIPETX6DATA_out),
.PIPETX6DATAVALID (PIPETX6DATAVALID_out),
.PIPETX6DEEMPH (PIPETX6DEEMPH_out),
.PIPETX6ELECIDLE (PIPETX6ELECIDLE_out),
.PIPETX6EQCONTROL (PIPETX6EQCONTROL_out),
.PIPETX6EQDEEMPH (PIPETX6EQDEEMPH_out),
.PIPETX6EQPRESET (PIPETX6EQPRESET_out),
.PIPETX6MARGIN (PIPETX6MARGIN_out),
.PIPETX6POWERDOWN (PIPETX6POWERDOWN_out),
.PIPETX6RATE (PIPETX6RATE_out),
.PIPETX6RCVRDET (PIPETX6RCVRDET_out),
.PIPETX6RESET (PIPETX6RESET_out),
.PIPETX6STARTBLOCK (PIPETX6STARTBLOCK_out),
.PIPETX6SWING (PIPETX6SWING_out),
.PIPETX6SYNCHEADER (PIPETX6SYNCHEADER_out),
.PIPETX7CHARISK (PIPETX7CHARISK_out),
.PIPETX7COMPLIANCE (PIPETX7COMPLIANCE_out),
.PIPETX7DATA (PIPETX7DATA_out),
.PIPETX7DATAVALID (PIPETX7DATAVALID_out),
.PIPETX7DEEMPH (PIPETX7DEEMPH_out),
.PIPETX7ELECIDLE (PIPETX7ELECIDLE_out),
.PIPETX7EQCONTROL (PIPETX7EQCONTROL_out),
.PIPETX7EQDEEMPH (PIPETX7EQDEEMPH_out),
.PIPETX7EQPRESET (PIPETX7EQPRESET_out),
.PIPETX7MARGIN (PIPETX7MARGIN_out),
.PIPETX7POWERDOWN (PIPETX7POWERDOWN_out),
.PIPETX7RATE (PIPETX7RATE_out),
.PIPETX7RCVRDET (PIPETX7RCVRDET_out),
.PIPETX7RESET (PIPETX7RESET_out),
.PIPETX7STARTBLOCK (PIPETX7STARTBLOCK_out),
.PIPETX7SWING (PIPETX7SWING_out),
.PIPETX7SYNCHEADER (PIPETX7SYNCHEADER_out),
.PLEQINPROGRESS (PLEQINPROGRESS_out),
.PLEQPHASE (PLEQPHASE_out),
.PMVOUT (PMVOUT_out),
.SAXISCCTREADY (SAXISCCTREADY_out),
.SAXISRQTREADY (SAXISRQTREADY_out),
.SCANOUT (SCANOUT_out),
.SPAREOUT (SPAREOUT_out),
.XILUNCONNBOUT (XILUNCONNBOUT_out),
.XILUNCONNOUT (XILUNCONNOUT_out),
.CFGCONFIGSPACEENABLE (CFGCONFIGSPACEENABLE_in),
.CFGDEVID (CFGDEVID_in),
.CFGDSBUSNUMBER (CFGDSBUSNUMBER_in),
.CFGDSDEVICENUMBER (CFGDSDEVICENUMBER_in),
.CFGDSFUNCTIONNUMBER (CFGDSFUNCTIONNUMBER_in),
.CFGDSN (CFGDSN_in),
.CFGDSPORTNUMBER (CFGDSPORTNUMBER_in),
.CFGERRCORIN (CFGERRCORIN_in),
.CFGERRUNCORIN (CFGERRUNCORIN_in),
.CFGEXTREADDATA (CFGEXTREADDATA_in),
.CFGEXTREADDATAVALID (CFGEXTREADDATAVALID_in),
.CFGFCSEL (CFGFCSEL_in),
.CFGFLRDONE (CFGFLRDONE_in),
.CFGHOTRESETIN (CFGHOTRESETIN_in),
.CFGINTERRUPTINT (CFGINTERRUPTINT_in),
.CFGINTERRUPTMSIATTR (CFGINTERRUPTMSIATTR_in),
.CFGINTERRUPTMSIFUNCTIONNUMBER (CFGINTERRUPTMSIFUNCTIONNUMBER_in),
.CFGINTERRUPTMSIINT (CFGINTERRUPTMSIINT_in),
.CFGINTERRUPTMSIPENDINGSTATUS (CFGINTERRUPTMSIPENDINGSTATUS_in),
.CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_in),
.CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_in),
.CFGINTERRUPTMSISELECT (CFGINTERRUPTMSISELECT_in),
.CFGINTERRUPTMSITPHPRESENT (CFGINTERRUPTMSITPHPRESENT_in),
.CFGINTERRUPTMSITPHSTTAG (CFGINTERRUPTMSITPHSTTAG_in),
.CFGINTERRUPTMSITPHTYPE (CFGINTERRUPTMSITPHTYPE_in),
.CFGINTERRUPTMSIXADDRESS (CFGINTERRUPTMSIXADDRESS_in),
.CFGINTERRUPTMSIXDATA (CFGINTERRUPTMSIXDATA_in),
.CFGINTERRUPTMSIXINT (CFGINTERRUPTMSIXINT_in),
.CFGINTERRUPTPENDING (CFGINTERRUPTPENDING_in),
.CFGLINKTRAININGENABLE (CFGLINKTRAININGENABLE_in),
.CFGMGMTADDR (CFGMGMTADDR_in),
.CFGMGMTBYTEENABLE (CFGMGMTBYTEENABLE_in),
.CFGMGMTREAD (CFGMGMTREAD_in),
.CFGMGMTTYPE1CFGREGACCESS (CFGMGMTTYPE1CFGREGACCESS_in),
.CFGMGMTWRITE (CFGMGMTWRITE_in),
.CFGMGMTWRITEDATA (CFGMGMTWRITEDATA_in),
.CFGMSGTRANSMIT (CFGMSGTRANSMIT_in),
.CFGMSGTRANSMITDATA (CFGMSGTRANSMITDATA_in),
.CFGMSGTRANSMITTYPE (CFGMSGTRANSMITTYPE_in),
.CFGPERFUNCSTATUSCONTROL (CFGPERFUNCSTATUSCONTROL_in),
.CFGPERFUNCTIONNUMBER (CFGPERFUNCTIONNUMBER_in),
.CFGPERFUNCTIONOUTPUTREQUEST (CFGPERFUNCTIONOUTPUTREQUEST_in),
.CFGPOWERSTATECHANGEACK (CFGPOWERSTATECHANGEACK_in),
.CFGREQPMTRANSITIONL23READY (CFGREQPMTRANSITIONL23READY_in),
.CFGREVID (CFGREVID_in),
.CFGSUBSYSID (CFGSUBSYSID_in),
.CFGSUBSYSVENDID (CFGSUBSYSVENDID_in),
.CFGTPHSTTREADDATA (CFGTPHSTTREADDATA_in),
.CFGTPHSTTREADDATAVALID (CFGTPHSTTREADDATAVALID_in),
.CFGVENDID (CFGVENDID_in),
.CFGVFFLRDONE (CFGVFFLRDONE_in),
.CONFMCAPREQUESTBYCONF (CONFMCAPREQUESTBYCONF_in),
.CONFREQDATA (CONFREQDATA_in),
.CONFREQREGNUM (CONFREQREGNUM_in),
.CONFREQTYPE (CONFREQTYPE_in),
.CONFREQVALID (CONFREQVALID_in),
.CORECLK (CORECLK_in),
.CORECLKMICOMPLETIONRAML (CORECLKMICOMPLETIONRAML_in),
.CORECLKMICOMPLETIONRAMU (CORECLKMICOMPLETIONRAMU_in),
.CORECLKMIREPLAYRAM (CORECLKMIREPLAYRAM_in),
.CORECLKMIREQUESTRAM (CORECLKMIREQUESTRAM_in),
.DBGCFGLOCALMGMTREGOVERRIDE (DBGCFGLOCALMGMTREGOVERRIDE_in),
.DBGDATASEL (DBGDATASEL_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.LL2LMSAXISTXTUSER (LL2LMSAXISTXTUSER_in),
.LL2LMSAXISTXTVALID (LL2LMSAXISTXTVALID_in),
.LL2LMTXTLPID0 (LL2LMTXTLPID0_in),
.LL2LMTXTLPID1 (LL2LMTXTLPID1_in),
.MAXISCQTREADY (MAXISCQTREADY_in),
.MAXISRCTREADY (MAXISRCTREADY_in),
.MCAPCLK (MCAPCLK_in),
.MGMTRESETN (MGMTRESETN_in),
.MGMTSTICKYRESETN (MGMTSTICKYRESETN_in),
.MICOMPLETIONRAMREADDATA (MICOMPLETIONRAMREADDATA_in),
.MIREPLAYRAMREADDATA (MIREPLAYRAMREADDATA_in),
.MIREQUESTRAMREADDATA (MIREQUESTRAMREADDATA_in),
.PCIECQNPREQ (PCIECQNPREQ_in),
.PIPECLK (PIPECLK_in),
.PIPEEQFS (PIPEEQFS_in),
.PIPEEQLF (PIPEEQLF_in),
.PIPERESETN (PIPERESETN_in),
.PIPERX0CHARISK (PIPERX0CHARISK_in),
.PIPERX0DATA (PIPERX0DATA_in),
.PIPERX0DATAVALID (PIPERX0DATAVALID_in),
.PIPERX0ELECIDLE (PIPERX0ELECIDLE_in),
.PIPERX0EQDONE (PIPERX0EQDONE_in),
.PIPERX0EQLPADAPTDONE (PIPERX0EQLPADAPTDONE_in),
.PIPERX0EQLPLFFSSEL (PIPERX0EQLPLFFSSEL_in),
.PIPERX0EQLPNEWTXCOEFFORPRESET (PIPERX0EQLPNEWTXCOEFFORPRESET_in),
.PIPERX0PHYSTATUS (PIPERX0PHYSTATUS_in),
.PIPERX0STARTBLOCK (PIPERX0STARTBLOCK_in),
.PIPERX0STATUS (PIPERX0STATUS_in),
.PIPERX0SYNCHEADER (PIPERX0SYNCHEADER_in),
.PIPERX0VALID (PIPERX0VALID_in),
.PIPERX1CHARISK (PIPERX1CHARISK_in),
.PIPERX1DATA (PIPERX1DATA_in),
.PIPERX1DATAVALID (PIPERX1DATAVALID_in),
.PIPERX1ELECIDLE (PIPERX1ELECIDLE_in),
.PIPERX1EQDONE (PIPERX1EQDONE_in),
.PIPERX1EQLPADAPTDONE (PIPERX1EQLPADAPTDONE_in),
.PIPERX1EQLPLFFSSEL (PIPERX1EQLPLFFSSEL_in),
.PIPERX1EQLPNEWTXCOEFFORPRESET (PIPERX1EQLPNEWTXCOEFFORPRESET_in),
.PIPERX1PHYSTATUS (PIPERX1PHYSTATUS_in),
.PIPERX1STARTBLOCK (PIPERX1STARTBLOCK_in),
.PIPERX1STATUS (PIPERX1STATUS_in),
.PIPERX1SYNCHEADER (PIPERX1SYNCHEADER_in),
.PIPERX1VALID (PIPERX1VALID_in),
.PIPERX2CHARISK (PIPERX2CHARISK_in),
.PIPERX2DATA (PIPERX2DATA_in),
.PIPERX2DATAVALID (PIPERX2DATAVALID_in),
.PIPERX2ELECIDLE (PIPERX2ELECIDLE_in),
.PIPERX2EQDONE (PIPERX2EQDONE_in),
.PIPERX2EQLPADAPTDONE (PIPERX2EQLPADAPTDONE_in),
.PIPERX2EQLPLFFSSEL (PIPERX2EQLPLFFSSEL_in),
.PIPERX2EQLPNEWTXCOEFFORPRESET (PIPERX2EQLPNEWTXCOEFFORPRESET_in),
.PIPERX2PHYSTATUS (PIPERX2PHYSTATUS_in),
.PIPERX2STARTBLOCK (PIPERX2STARTBLOCK_in),
.PIPERX2STATUS (PIPERX2STATUS_in),
.PIPERX2SYNCHEADER (PIPERX2SYNCHEADER_in),
.PIPERX2VALID (PIPERX2VALID_in),
.PIPERX3CHARISK (PIPERX3CHARISK_in),
.PIPERX3DATA (PIPERX3DATA_in),
.PIPERX3DATAVALID (PIPERX3DATAVALID_in),
.PIPERX3ELECIDLE (PIPERX3ELECIDLE_in),
.PIPERX3EQDONE (PIPERX3EQDONE_in),
.PIPERX3EQLPADAPTDONE (PIPERX3EQLPADAPTDONE_in),
.PIPERX3EQLPLFFSSEL (PIPERX3EQLPLFFSSEL_in),
.PIPERX3EQLPNEWTXCOEFFORPRESET (PIPERX3EQLPNEWTXCOEFFORPRESET_in),
.PIPERX3PHYSTATUS (PIPERX3PHYSTATUS_in),
.PIPERX3STARTBLOCK (PIPERX3STARTBLOCK_in),
.PIPERX3STATUS (PIPERX3STATUS_in),
.PIPERX3SYNCHEADER (PIPERX3SYNCHEADER_in),
.PIPERX3VALID (PIPERX3VALID_in),
.PIPERX4CHARISK (PIPERX4CHARISK_in),
.PIPERX4DATA (PIPERX4DATA_in),
.PIPERX4DATAVALID (PIPERX4DATAVALID_in),
.PIPERX4ELECIDLE (PIPERX4ELECIDLE_in),
.PIPERX4EQDONE (PIPERX4EQDONE_in),
.PIPERX4EQLPADAPTDONE (PIPERX4EQLPADAPTDONE_in),
.PIPERX4EQLPLFFSSEL (PIPERX4EQLPLFFSSEL_in),
.PIPERX4EQLPNEWTXCOEFFORPRESET (PIPERX4EQLPNEWTXCOEFFORPRESET_in),
.PIPERX4PHYSTATUS (PIPERX4PHYSTATUS_in),
.PIPERX4STARTBLOCK (PIPERX4STARTBLOCK_in),
.PIPERX4STATUS (PIPERX4STATUS_in),
.PIPERX4SYNCHEADER (PIPERX4SYNCHEADER_in),
.PIPERX4VALID (PIPERX4VALID_in),
.PIPERX5CHARISK (PIPERX5CHARISK_in),
.PIPERX5DATA (PIPERX5DATA_in),
.PIPERX5DATAVALID (PIPERX5DATAVALID_in),
.PIPERX5ELECIDLE (PIPERX5ELECIDLE_in),
.PIPERX5EQDONE (PIPERX5EQDONE_in),
.PIPERX5EQLPADAPTDONE (PIPERX5EQLPADAPTDONE_in),
.PIPERX5EQLPLFFSSEL (PIPERX5EQLPLFFSSEL_in),
.PIPERX5EQLPNEWTXCOEFFORPRESET (PIPERX5EQLPNEWTXCOEFFORPRESET_in),
.PIPERX5PHYSTATUS (PIPERX5PHYSTATUS_in),
.PIPERX5STARTBLOCK (PIPERX5STARTBLOCK_in),
.PIPERX5STATUS (PIPERX5STATUS_in),
.PIPERX5SYNCHEADER (PIPERX5SYNCHEADER_in),
.PIPERX5VALID (PIPERX5VALID_in),
.PIPERX6CHARISK (PIPERX6CHARISK_in),
.PIPERX6DATA (PIPERX6DATA_in),
.PIPERX6DATAVALID (PIPERX6DATAVALID_in),
.PIPERX6ELECIDLE (PIPERX6ELECIDLE_in),
.PIPERX6EQDONE (PIPERX6EQDONE_in),
.PIPERX6EQLPADAPTDONE (PIPERX6EQLPADAPTDONE_in),
.PIPERX6EQLPLFFSSEL (PIPERX6EQLPLFFSSEL_in),
.PIPERX6EQLPNEWTXCOEFFORPRESET (PIPERX6EQLPNEWTXCOEFFORPRESET_in),
.PIPERX6PHYSTATUS (PIPERX6PHYSTATUS_in),
.PIPERX6STARTBLOCK (PIPERX6STARTBLOCK_in),
.PIPERX6STATUS (PIPERX6STATUS_in),
.PIPERX6SYNCHEADER (PIPERX6SYNCHEADER_in),
.PIPERX6VALID (PIPERX6VALID_in),
.PIPERX7CHARISK (PIPERX7CHARISK_in),
.PIPERX7DATA (PIPERX7DATA_in),
.PIPERX7DATAVALID (PIPERX7DATAVALID_in),
.PIPERX7ELECIDLE (PIPERX7ELECIDLE_in),
.PIPERX7EQDONE (PIPERX7EQDONE_in),
.PIPERX7EQLPADAPTDONE (PIPERX7EQLPADAPTDONE_in),
.PIPERX7EQLPLFFSSEL (PIPERX7EQLPLFFSSEL_in),
.PIPERX7EQLPNEWTXCOEFFORPRESET (PIPERX7EQLPNEWTXCOEFFORPRESET_in),
.PIPERX7PHYSTATUS (PIPERX7PHYSTATUS_in),
.PIPERX7STARTBLOCK (PIPERX7STARTBLOCK_in),
.PIPERX7STATUS (PIPERX7STATUS_in),
.PIPERX7SYNCHEADER (PIPERX7SYNCHEADER_in),
.PIPERX7VALID (PIPERX7VALID_in),
.PIPETX0EQCOEFF (PIPETX0EQCOEFF_in),
.PIPETX0EQDONE (PIPETX0EQDONE_in),
.PIPETX1EQCOEFF (PIPETX1EQCOEFF_in),
.PIPETX1EQDONE (PIPETX1EQDONE_in),
.PIPETX2EQCOEFF (PIPETX2EQCOEFF_in),
.PIPETX2EQDONE (PIPETX2EQDONE_in),
.PIPETX3EQCOEFF (PIPETX3EQCOEFF_in),
.PIPETX3EQDONE (PIPETX3EQDONE_in),
.PIPETX4EQCOEFF (PIPETX4EQCOEFF_in),
.PIPETX4EQDONE (PIPETX4EQDONE_in),
.PIPETX5EQCOEFF (PIPETX5EQCOEFF_in),
.PIPETX5EQDONE (PIPETX5EQDONE_in),
.PIPETX6EQCOEFF (PIPETX6EQCOEFF_in),
.PIPETX6EQDONE (PIPETX6EQDONE_in),
.PIPETX7EQCOEFF (PIPETX7EQCOEFF_in),
.PIPETX7EQDONE (PIPETX7EQDONE_in),
.PLEQRESETEIEOSCOUNT (PLEQRESETEIEOSCOUNT_in),
.PLGEN2UPSTREAMPREFERDEEMPH (PLGEN2UPSTREAMPREFERDEEMPH_in),
.PMVDIVIDE (PMVDIVIDE_in),
.PMVENABLEN (PMVENABLEN_in),
.PMVSELECT (PMVSELECT_in),
.RESETN (RESETN_in),
.SAXISCCTDATA (SAXISCCTDATA_in),
.SAXISCCTKEEP (SAXISCCTKEEP_in),
.SAXISCCTLAST (SAXISCCTLAST_in),
.SAXISCCTUSER (SAXISCCTUSER_in),
.SAXISCCTVALID (SAXISCCTVALID_in),
.SAXISRQTDATA (SAXISRQTDATA_in),
.SAXISRQTKEEP (SAXISRQTKEEP_in),
.SAXISRQTLAST (SAXISRQTLAST_in),
.SAXISRQTUSER (SAXISRQTUSER_in),
.SAXISRQTVALID (SAXISRQTVALID_in),
.SCANENABLEN (SCANENABLEN_in),
.SCANIN (SCANIN_in),
.SCANMODEN (SCANMODEN_in),
.SPAREIN (SPAREIN_in),
.USERCLK (USERCLK_in),
.XILUNCONNBYP (XILUNCONNBYP_in),
.XILUNCONNCLK (XILUNCONNCLK_in),
.XILUNCONNIN (XILUNCONNIN_in),
.GSR (glblGSR)
);
specify
(CORECLK => DBGDATAOUT[0]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[10]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[11]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[12]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[13]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[14]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[15]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[1]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[2]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[3]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[4]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[5]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[6]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[7]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[8]) = (0:0:0, 0:0:0);
(CORECLK => DBGDATAOUT[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSAL[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADADDRESSBL[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMREADENABLEL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSAL[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEADDRESSBL[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[10]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[11]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[12]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[13]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[14]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[15]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[16]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[17]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[18]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[19]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[20]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[21]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[22]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[23]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[24]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[25]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[26]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[27]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[28]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[29]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[30]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[31]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[32]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[33]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[34]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[35]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[36]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[37]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[38]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[39]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[40]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[41]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[42]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[43]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[44]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[45]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[46]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[47]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[48]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[49]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[50]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[51]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[52]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[53]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[54]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[55]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[56]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[57]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[58]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[59]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[60]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[61]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[62]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[63]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[64]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[65]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[66]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[67]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[68]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[69]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[70]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[71]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEDATAL[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAML => MICOMPLETIONRAMWRITEENABLEL[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSAU[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADADDRESSBU[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMREADENABLEU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSAU[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEADDRESSBU[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[10]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[11]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[12]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[13]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[14]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[15]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[16]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[17]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[18]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[19]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[20]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[21]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[22]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[23]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[24]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[25]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[26]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[27]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[28]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[29]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[30]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[31]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[32]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[33]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[34]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[35]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[36]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[37]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[38]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[39]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[3]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[40]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[41]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[42]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[43]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[44]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[45]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[46]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[47]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[48]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[49]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[4]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[50]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[51]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[52]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[53]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[54]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[55]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[56]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[57]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[58]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[59]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[5]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[60]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[61]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[62]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[63]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[64]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[65]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[66]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[67]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[68]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[69]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[6]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[70]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[71]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[7]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[8]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEDATAU[9]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[0]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[1]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[2]) = (0:0:0, 0:0:0);
(CORECLKMICOMPLETIONRAMU => MICOMPLETIONRAMWRITEENABLEU[3]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[0]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[1]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[2]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[3]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[4]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[5]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[6]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[7]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMADDRESS[8]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMREADENABLE[0]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMREADENABLE[1]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[0]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[100]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[101]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[102]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[103]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[104]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[105]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[106]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[107]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[108]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[109]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[10]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[110]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[111]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[112]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[113]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[114]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[115]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[116]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[117]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[118]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[119]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[11]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[120]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[121]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[122]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[123]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[124]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[125]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[126]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[127]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[128]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[129]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[12]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[130]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[131]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[132]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[133]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[134]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[135]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[136]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[137]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[138]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[139]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[13]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[140]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[141]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[142]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[143]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[14]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[15]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[16]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[17]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[18]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[19]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[1]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[20]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[21]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[22]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[23]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[24]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[25]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[26]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[27]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[28]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[29]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[2]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[30]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[31]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[32]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[33]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[34]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[35]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[36]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[37]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[38]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[39]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[3]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[40]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[41]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[42]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[43]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[44]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[45]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[46]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[47]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[48]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[49]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[4]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[50]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[51]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[52]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[53]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[54]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[55]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[56]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[57]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[58]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[59]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[5]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[60]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[61]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[62]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[63]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[64]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[65]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[66]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[67]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[68]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[69]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[6]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[70]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[71]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[72]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[73]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[74]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[75]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[76]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[77]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[78]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[79]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[7]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[80]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[81]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[82]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[83]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[84]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[85]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[86]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[87]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[88]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[89]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[8]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[90]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[91]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[92]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[93]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[94]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[95]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[96]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[97]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[98]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[99]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEDATA[9]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEENABLE[0]) = (0:0:0, 0:0:0);
(CORECLKMIREPLAYRAM => MIREPLAYRAMWRITEENABLE[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[4]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[5]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[6]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[7]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSA[8]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[4]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[5]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[6]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[7]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADADDRESSB[8]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMREADENABLE[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[4]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[5]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[6]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[7]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSA[8]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[4]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[5]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[6]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[7]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEADDRESSB[8]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[100]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[101]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[102]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[103]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[104]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[105]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[106]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[107]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[108]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[109]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[10]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[110]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[111]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[112]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[113]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[114]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[115]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[116]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[117]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[118]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[119]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[11]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[120]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[121]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[122]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[123]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[124]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[125]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[126]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[127]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[128]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[129]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[12]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[130]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[131]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[132]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[133]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[134]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[135]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[136]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[137]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[138]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[139]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[13]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[140]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[141]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[142]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[143]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[14]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[15]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[16]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[17]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[18]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[19]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[20]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[21]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[22]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[23]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[24]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[25]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[26]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[27]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[28]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[29]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[30]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[31]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[32]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[33]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[34]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[35]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[36]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[37]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[38]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[39]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[3]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[40]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[41]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[42]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[43]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[44]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[45]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[46]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[47]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[48]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[49]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[4]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[50]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[51]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[52]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[53]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[54]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[55]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[56]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[57]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[58]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[59]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[5]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[60]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[61]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[62]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[63]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[64]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[65]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[66]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[67]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[68]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[69]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[6]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[70]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[71]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[72]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[73]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[74]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[75]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[76]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[77]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[78]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[79]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[7]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[80]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[81]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[82]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[83]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[84]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[85]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[86]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[87]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[88]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[89]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[8]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[90]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[91]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[92]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[93]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[94]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[95]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[96]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[97]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[98]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[99]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEDATA[9]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[0]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[1]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[2]) = (0:0:0, 0:0:0);
(CORECLKMIREQUESTRAM => MIREQUESTRAMWRITEENABLE[3]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[0]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[10]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[11]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[12]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[13]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[14]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[15]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[1]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[2]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[3]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[4]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[5]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[6]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[7]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[8]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPCSB) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[0]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[10]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[11]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[12]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[13]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[14]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[15]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[16]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[17]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[18]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[19]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[1]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[20]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[21]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[22]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[23]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[24]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[25]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[26]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[27]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[28]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[29]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[2]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[30]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[31]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[3]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[4]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[5]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[6]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[7]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[8]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPDATA[9]) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPEOS) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPERROR) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPMODE) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPRDATAVALID) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPRDWRB) = (0:0:0, 0:0:0);
(MCAPCLK => DBGMCAPRESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX0POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX1POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX2POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX3POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX4POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX5POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX6POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPLFFS[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPTXPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPTXPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPTXPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQLPTXPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPERX7POLARITY) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX0SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX1SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX2SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX3SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX4SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX5SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX6SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7CHARISK[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7CHARISK[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7COMPLIANCE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATAVALID) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[10]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[11]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[12]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[13]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[14]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[15]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[16]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[17]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[18]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[19]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[20]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[21]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[22]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[23]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[24]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[25]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[26]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[27]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[28]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[29]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[30]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[31]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[6]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[7]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[8]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DATA[9]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7DEEMPH) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7ELECIDLE) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQCONTROL[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQCONTROL[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[4]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQDEEMPH[5]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQPRESET[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQPRESET[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQPRESET[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7EQPRESET[3]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7MARGIN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7MARGIN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7MARGIN[2]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7POWERDOWN[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7POWERDOWN[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7RATE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7RATE[1]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7RCVRDET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7RESET) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7STARTBLOCK) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7SWING) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7SYNCHEADER[0]) = (0:0:0, 0:0:0);
(PIPECLK => PIPETX7SYNCHEADER[1]) = (0:0:0, 0:0:0);
(PIPECLK => PLEQINPROGRESS) = (0:0:0, 0:0:0);
(PIPECLK => PLEQPHASE[0]) = (0:0:0, 0:0:0);
(PIPECLK => PLEQPHASE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGCURRENTSPEED[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGCURRENTSPEED[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGCURRENTSPEED[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGDPASUBSTATECHANGE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGDPASUBSTATECHANGE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGDPASUBSTATECHANGE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGDPASUBSTATECHANGE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGERRCOROUT) = (0:0:0, 0:0:0);
(USERCLK => CFGERRFATALOUT) = (0:0:0, 0:0:0);
(USERCLK => CFGERRNONFATALOUT) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTFUNCTIONNUMBER[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREADRECEIVED) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTREGISTERNUMBER[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEBYTEENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEBYTEENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEBYTEENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEBYTEENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITEDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGEXTWRITERECEIVED) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLD[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCCPLH[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPD[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCNPH[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPD[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFCPH[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFLRINPROCESS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFLRINPROCESS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFLRINPROCESS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFLRINPROCESS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONPOWERSTATE[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGFUNCTIONSTATUS[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGHOTRESETOUT) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIFAIL) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMASKUPDATE) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIMMENABLE[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSISENT) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIVFENABLE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXFAIL) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXMASK[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXMASK[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXMASK[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXMASK[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXSENT) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFENABLE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTMSIXVFMASK[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGINTERRUPTSENT) = (0:0:0, 0:0:0);
(USERCLK => CFGLINKPOWERSTATE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGLINKPOWERSTATE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGLOCALERROR) = (0:0:0, 0:0:0);
(USERCLK => CFGLTRENABLE) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGLTSSMSTATE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXPAYLOAD[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXPAYLOAD[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXPAYLOAD[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXREADREQ[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXREADREQ[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGMAXREADREQ[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGMGMTREADWRITEDONE) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVED) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDTYPE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDTYPE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDTYPE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDTYPE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGRECEIVEDTYPE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGMSGTRANSMITDONE) = (0:0:0, 0:0:0);
(USERCLK => CFGNEGOTIATEDWIDTH[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGNEGOTIATEDWIDTH[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGNEGOTIATEDWIDTH[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGNEGOTIATEDWIDTH[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGOBFFENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGOBFFENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCSTATUSDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGPERFUNCTIONUPDATEDONE) = (0:0:0, 0:0:0);
(USERCLK => CFGPHYLINKDOWN) = (0:0:0, 0:0:0);
(USERCLK => CFGPHYLINKSTATUS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGPHYLINKSTATUS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGPLSTATUSCHANGE) = (0:0:0, 0:0:0);
(USERCLK => CFGPOWERSTATECHANGEINTERRUPT) = (0:0:0, 0:0:0);
(USERCLK => CFGRCBSTATUS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGRCBSTATUS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGRCBSTATUS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGRCBSTATUS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHFUNCTIONNUM[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHFUNCTIONNUM[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHFUNCTIONNUM[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHFUNCTIONNUM[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHREQUESTERENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHREQUESTERENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHREQUESTERENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHREQUESTERENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTMODE[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTADDRESS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTADDRESS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTADDRESS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTADDRESS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTADDRESS[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTREADENABLE) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEBYTEVALID[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEBYTEVALID[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEBYTEVALID[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEBYTEVALID[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGTPHSTTWRITEENABLE) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFFLRINPROCESS[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFPOWERSTATE[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFSTATUS[9]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHREQUESTERENABLE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[0]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[10]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[11]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[12]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[13]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[14]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[15]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[16]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[17]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[18]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[19]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[1]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[20]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[21]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[22]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[23]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[2]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[3]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[4]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[5]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[6]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[7]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[8]) = (0:0:0, 0:0:0);
(USERCLK => CFGVFTPHSTMODE[9]) = (0:0:0, 0:0:0);
(USERCLK => CONFMCAPDESIGNSWITCH) = (0:0:0, 0:0:0);
(USERCLK => CONFMCAPEOS) = (0:0:0, 0:0:0);
(USERCLK => CONFMCAPINUSEBYPCIE) = (0:0:0, 0:0:0);
(USERCLK => CONFREQREADY) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPRDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => CONFRESPVALID) = (0:0:0, 0:0:0);
(USERCLK => DBGPLDATABLOCKRECEIVEDAFTEREDS) = (0:0:0, 0:0:0);
(USERCLK => DBGPLGEN3FRAMINGERRORDETECTED) = (0:0:0, 0:0:0);
(USERCLK => DBGPLGEN3SYNCHEADERERRORDETECTED) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[0]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[1]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[2]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[3]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[4]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[5]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[6]) = (0:0:0, 0:0:0);
(USERCLK => DBGPLINFERREDRXELECTRICALIDLE[7]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENT0) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENT1) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID0[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID0[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID0[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID0[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID1[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID1[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID1[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMASTERTLPSENTTLPID1[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[100]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[101]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[102]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[103]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[104]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[105]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[106]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[107]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[108]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[109]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[110]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[111]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[112]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[113]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[114]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[115]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[116]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[117]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[118]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[119]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[120]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[121]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[122]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[123]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[124]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[125]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[126]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[127]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[128]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[129]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[130]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[131]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[132]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[133]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[134]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[135]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[136]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[137]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[138]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[139]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[140]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[141]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[142]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[143]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[144]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[145]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[146]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[147]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[148]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[149]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[150]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[151]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[152]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[153]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[154]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[155]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[156]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[157]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[158]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[159]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[160]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[161]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[162]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[163]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[164]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[165]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[166]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[167]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[168]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[169]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[170]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[171]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[172]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[173]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[174]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[175]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[176]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[177]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[178]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[179]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[180]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[181]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[182]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[183]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[184]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[185]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[186]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[187]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[188]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[189]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[190]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[191]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[192]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[193]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[194]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[195]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[196]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[197]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[198]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[199]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[200]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[201]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[202]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[203]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[204]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[205]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[206]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[207]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[208]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[209]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[210]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[211]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[212]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[213]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[214]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[215]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[216]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[217]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[218]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[219]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[220]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[221]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[222]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[223]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[224]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[225]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[226]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[227]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[228]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[229]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[230]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[231]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[232]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[233]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[234]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[235]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[236]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[237]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[238]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[239]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[240]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[241]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[242]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[243]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[244]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[245]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[246]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[247]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[248]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[249]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[250]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[251]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[252]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[253]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[254]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[255]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[32]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[33]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[34]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[35]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[36]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[37]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[38]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[39]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[40]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[41]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[42]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[43]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[44]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[45]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[46]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[47]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[48]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[49]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[50]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[51]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[52]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[53]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[54]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[55]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[56]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[57]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[58]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[59]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[60]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[61]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[62]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[63]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[64]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[65]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[66]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[67]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[68]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[69]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[70]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[71]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[72]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[73]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[74]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[75]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[76]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[77]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[78]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[79]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[80]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[81]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[82]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[83]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[84]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[85]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[86]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[87]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[88]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[89]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[90]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[91]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[92]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[93]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[94]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[95]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[96]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[97]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[98]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[99]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[10]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[11]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[12]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[13]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[14]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[15]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[16]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[17]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[4]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[5]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[6]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[7]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[8]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTUSER[9]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[4]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[5]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[6]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMMAXISRXTVALID[7]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[0]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[1]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[2]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[3]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[4]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[5]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[6]) = (0:0:0, 0:0:0);
(USERCLK => LL2LMSAXISTXTREADY[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[100]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[101]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[102]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[103]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[104]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[105]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[106]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[107]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[108]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[109]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[110]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[111]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[112]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[113]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[114]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[115]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[116]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[117]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[118]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[119]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[120]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[121]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[122]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[123]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[124]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[125]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[126]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[127]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[128]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[129]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[130]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[131]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[132]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[133]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[134]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[135]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[136]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[137]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[138]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[139]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[140]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[141]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[142]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[143]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[144]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[145]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[146]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[147]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[148]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[149]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[150]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[151]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[152]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[153]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[154]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[155]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[156]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[157]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[158]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[159]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[160]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[161]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[162]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[163]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[164]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[165]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[166]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[167]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[168]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[169]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[170]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[171]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[172]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[173]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[174]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[175]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[176]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[177]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[178]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[179]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[180]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[181]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[182]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[183]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[184]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[185]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[186]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[187]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[188]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[189]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[190]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[191]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[192]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[193]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[194]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[195]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[196]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[197]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[198]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[199]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[200]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[201]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[202]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[203]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[204]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[205]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[206]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[207]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[208]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[209]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[210]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[211]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[212]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[213]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[214]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[215]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[216]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[217]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[218]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[219]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[220]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[221]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[222]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[223]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[224]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[225]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[226]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[227]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[228]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[229]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[230]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[231]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[232]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[233]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[234]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[235]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[236]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[237]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[238]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[239]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[240]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[241]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[242]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[243]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[244]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[245]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[246]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[247]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[248]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[249]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[250]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[251]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[252]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[253]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[254]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[255]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[32]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[33]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[34]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[35]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[36]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[37]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[38]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[39]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[40]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[41]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[42]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[43]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[44]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[45]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[46]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[47]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[48]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[49]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[50]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[51]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[52]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[53]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[54]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[55]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[56]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[57]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[58]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[59]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[60]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[61]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[62]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[63]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[64]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[65]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[66]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[67]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[68]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[69]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[70]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[71]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[72]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[73]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[74]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[75]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[76]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[77]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[78]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[79]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[80]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[81]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[82]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[83]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[84]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[85]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[86]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[87]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[88]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[89]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[90]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[91]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[92]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[93]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[94]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[95]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[96]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[97]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[98]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[99]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTKEEP[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTLAST) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[10]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[11]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[12]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[13]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[14]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[15]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[16]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[17]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[18]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[19]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[20]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[21]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[22]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[23]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[24]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[25]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[26]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[27]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[28]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[29]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[30]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[31]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[32]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[33]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[34]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[35]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[36]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[37]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[38]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[39]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[40]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[41]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[42]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[43]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[44]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[45]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[46]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[47]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[48]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[49]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[50]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[51]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[52]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[53]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[54]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[55]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[56]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[57]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[58]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[59]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[60]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[61]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[62]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[63]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[64]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[65]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[66]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[67]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[68]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[69]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[70]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[71]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[72]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[73]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[74]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[75]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[76]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[77]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[78]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[79]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[80]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[81]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[82]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[83]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[84]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[8]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTUSER[9]) = (0:0:0, 0:0:0);
(USERCLK => MAXISCQTVALID) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[100]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[101]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[102]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[103]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[104]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[105]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[106]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[107]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[108]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[109]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[10]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[110]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[111]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[112]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[113]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[114]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[115]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[116]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[117]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[118]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[119]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[11]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[120]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[121]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[122]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[123]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[124]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[125]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[126]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[127]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[128]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[129]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[12]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[130]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[131]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[132]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[133]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[134]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[135]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[136]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[137]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[138]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[139]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[13]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[140]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[141]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[142]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[143]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[144]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[145]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[146]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[147]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[148]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[149]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[14]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[150]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[151]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[152]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[153]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[154]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[155]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[156]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[157]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[158]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[159]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[15]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[160]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[161]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[162]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[163]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[164]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[165]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[166]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[167]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[168]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[169]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[16]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[170]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[171]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[172]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[173]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[174]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[175]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[176]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[177]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[178]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[179]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[17]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[180]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[181]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[182]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[183]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[184]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[185]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[186]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[187]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[188]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[189]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[18]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[190]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[191]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[192]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[193]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[194]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[195]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[196]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[197]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[198]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[199]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[19]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[200]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[201]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[202]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[203]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[204]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[205]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[206]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[207]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[208]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[209]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[20]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[210]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[211]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[212]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[213]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[214]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[215]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[216]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[217]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[218]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[219]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[21]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[220]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[221]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[222]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[223]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[224]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[225]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[226]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[227]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[228]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[229]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[22]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[230]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[231]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[232]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[233]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[234]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[235]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[236]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[237]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[238]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[239]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[23]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[240]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[241]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[242]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[243]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[244]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[245]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[246]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[247]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[248]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[249]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[24]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[250]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[251]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[252]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[253]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[254]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[255]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[25]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[26]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[27]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[28]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[29]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[30]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[31]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[32]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[33]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[34]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[35]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[36]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[37]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[38]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[39]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[40]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[41]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[42]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[43]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[44]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[45]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[46]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[47]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[48]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[49]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[50]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[51]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[52]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[53]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[54]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[55]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[56]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[57]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[58]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[59]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[60]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[61]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[62]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[63]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[64]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[65]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[66]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[67]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[68]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[69]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[70]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[71]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[72]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[73]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[74]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[75]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[76]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[77]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[78]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[79]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[80]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[81]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[82]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[83]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[84]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[85]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[86]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[87]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[88]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[89]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[8]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[90]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[91]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[92]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[93]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[94]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[95]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[96]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[97]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[98]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[99]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTDATA[9]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTKEEP[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTLAST) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[0]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[10]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[11]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[12]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[13]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[14]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[15]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[16]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[17]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[18]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[19]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[1]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[20]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[21]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[22]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[23]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[24]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[25]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[26]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[27]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[28]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[29]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[2]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[30]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[31]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[32]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[33]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[34]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[35]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[36]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[37]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[38]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[39]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[3]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[40]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[41]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[42]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[43]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[44]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[45]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[46]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[47]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[48]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[49]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[4]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[50]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[51]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[52]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[53]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[54]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[55]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[56]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[57]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[58]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[59]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[5]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[60]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[61]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[62]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[63]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[64]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[65]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[66]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[67]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[68]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[69]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[6]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[70]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[71]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[72]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[73]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[74]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[7]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[8]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTUSER[9]) = (0:0:0, 0:0:0);
(USERCLK => MAXISRCTVALID) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[1]) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[2]) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[3]) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[4]) = (0:0:0, 0:0:0);
(USERCLK => PCIECQNPREQCOUNT[5]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQSEQNUMVLD) = (0:0:0, 0:0:0);
(USERCLK => PCIERQSEQNUM[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQSEQNUM[1]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQSEQNUM[2]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQSEQNUM[3]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAGAV[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAGAV[1]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAGVLD) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[1]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[2]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[3]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[4]) = (0:0:0, 0:0:0);
(USERCLK => PCIERQTAG[5]) = (0:0:0, 0:0:0);
(USERCLK => PCIETFCNPDAV[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIETFCNPDAV[1]) = (0:0:0, 0:0:0);
(USERCLK => PCIETFCNPHAV[0]) = (0:0:0, 0:0:0);
(USERCLK => PCIETFCNPHAV[1]) = (0:0:0, 0:0:0);
(USERCLK => SAXISCCTREADY[0]) = (0:0:0, 0:0:0);
(USERCLK => SAXISCCTREADY[1]) = (0:0:0, 0:0:0);
(USERCLK => SAXISCCTREADY[2]) = (0:0:0, 0:0:0);
(USERCLK => SAXISCCTREADY[3]) = (0:0:0, 0:0:0);
(USERCLK => SAXISRQTREADY[0]) = (0:0:0, 0:0:0);
(USERCLK => SAXISRQTREADY[1]) = (0:0:0, 0:0:0);
(USERCLK => SAXISRQTREADY[2]) = (0:0:0, 0:0:0);
(USERCLK => SAXISRQTREADY[3]) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[9]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[9]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[9]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MICOMPLETIONRAMREADDATA_delay[9]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREPLAYRAMREADDATA_delay[9]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[0]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[100]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[101]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[102]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[103]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[104]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[105]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[106]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[107]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[108]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[109]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[10]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[110]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[111]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[112]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[113]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[114]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[115]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[116]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[117]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[118]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[119]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[11]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[120]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[121]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[122]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[123]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[124]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[125]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[126]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[127]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[128]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[129]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[12]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[130]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[131]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[132]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[133]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[134]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[135]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[136]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[137]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[138]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[139]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[13]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[140]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[141]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[142]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[143]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[14]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[15]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[16]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[17]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[18]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[19]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[1]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[20]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[21]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[22]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[23]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[24]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[25]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[26]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[27]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[28]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[29]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[2]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[30]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[31]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[32]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[33]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[34]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[35]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[36]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[37]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[38]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[39]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[3]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[40]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[41]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[42]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[43]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[44]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[45]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[46]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[47]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[48]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[49]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[4]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[50]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[51]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[52]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[53]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[54]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[55]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[56]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[57]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[58]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[59]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[5]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[60]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[61]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[62]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[63]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[64]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[65]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[66]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[67]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[68]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[69]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[6]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[70]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[71]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[72]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[73]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[74]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[75]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[76]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[77]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[78]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[79]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[7]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[80]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[81]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[82]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[83]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[84]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[85]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[86]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[87]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[88]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[89]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[8]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[90]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[91]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[92]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[93]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[94]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[95]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[96]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[97]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[98]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[99]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, CORECLK_delay, MIREQUESTRAMREADDATA_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATAVALID_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[18]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[19]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[20]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[21]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[22]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[23]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[24]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[25]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[26]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[27]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[28]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[29]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[30]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[31]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7ELECIDLE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7PHYSTATUS_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STARTBLOCK_delay);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7VALID_delay);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQDONE_delay);
$setuphold (posedge PIPECLK, negedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLEQRESETEIEOSCOUNT_delay);
$setuphold (posedge PIPECLK, negedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQFS_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPEEQLF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX0VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX1VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX2VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX3VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX4VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX5VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX6VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7CHARISK_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATAVALID_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[18]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[19]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[20]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[21]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[22]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[23]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[24]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[25]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[26]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[27]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[28]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[29]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[30]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[31]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7DATA_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7ELECIDLE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPADAPTDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPLFFSSEL_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7EQLPNEWTXCOEFFORPRESET_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7PHYSTATUS_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STARTBLOCK_delay);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7STATUS_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7SYNCHEADER_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPERX7VALID_delay);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX0EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX1EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX2EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX3EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX4EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX5EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX6EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[0]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[10]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[11]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[12]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[13]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[14]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[15]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[16]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[17]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[1]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[2]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[3]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[4]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[5]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[6]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[7]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[8]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQCOEFF_delay[9]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PIPETX7EQDONE_delay);
$setuphold (posedge PIPECLK, posedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLEQRESETEIEOSCOUNT_delay);
$setuphold (posedge PIPECLK, posedge PLGEN2UPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, PIPECLK_delay, PLGEN2UPSTREAMPREFERDEEMPH_delay);
$setuphold (posedge USERCLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGCONFIGSPACEENABLE_delay);
$setuphold (posedge USERCLK, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[10]);
$setuphold (posedge USERCLK, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[11]);
$setuphold (posedge USERCLK, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[12]);
$setuphold (posedge USERCLK, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[13]);
$setuphold (posedge USERCLK, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[14]);
$setuphold (posedge USERCLK, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[15]);
$setuphold (posedge USERCLK, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[3]);
$setuphold (posedge USERCLK, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[4]);
$setuphold (posedge USERCLK, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[5]);
$setuphold (posedge USERCLK, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[6]);
$setuphold (posedge USERCLK, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[7]);
$setuphold (posedge USERCLK, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[8]);
$setuphold (posedge USERCLK, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[9]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[3]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[4]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[5]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[6]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[7]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[3]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[4]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[10]);
$setuphold (posedge USERCLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[11]);
$setuphold (posedge USERCLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[12]);
$setuphold (posedge USERCLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[13]);
$setuphold (posedge USERCLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[14]);
$setuphold (posedge USERCLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[15]);
$setuphold (posedge USERCLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[16]);
$setuphold (posedge USERCLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[17]);
$setuphold (posedge USERCLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[18]);
$setuphold (posedge USERCLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[19]);
$setuphold (posedge USERCLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[20]);
$setuphold (posedge USERCLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[21]);
$setuphold (posedge USERCLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[22]);
$setuphold (posedge USERCLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[23]);
$setuphold (posedge USERCLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[24]);
$setuphold (posedge USERCLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[25]);
$setuphold (posedge USERCLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[26]);
$setuphold (posedge USERCLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[27]);
$setuphold (posedge USERCLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[28]);
$setuphold (posedge USERCLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[29]);
$setuphold (posedge USERCLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[30]);
$setuphold (posedge USERCLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[31]);
$setuphold (posedge USERCLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[32]);
$setuphold (posedge USERCLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[33]);
$setuphold (posedge USERCLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[34]);
$setuphold (posedge USERCLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[35]);
$setuphold (posedge USERCLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[36]);
$setuphold (posedge USERCLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[37]);
$setuphold (posedge USERCLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[38]);
$setuphold (posedge USERCLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[39]);
$setuphold (posedge USERCLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[3]);
$setuphold (posedge USERCLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[40]);
$setuphold (posedge USERCLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[41]);
$setuphold (posedge USERCLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[42]);
$setuphold (posedge USERCLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[43]);
$setuphold (posedge USERCLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[44]);
$setuphold (posedge USERCLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[45]);
$setuphold (posedge USERCLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[46]);
$setuphold (posedge USERCLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[47]);
$setuphold (posedge USERCLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[48]);
$setuphold (posedge USERCLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[49]);
$setuphold (posedge USERCLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[4]);
$setuphold (posedge USERCLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[50]);
$setuphold (posedge USERCLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[51]);
$setuphold (posedge USERCLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[52]);
$setuphold (posedge USERCLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[53]);
$setuphold (posedge USERCLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[54]);
$setuphold (posedge USERCLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[55]);
$setuphold (posedge USERCLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[56]);
$setuphold (posedge USERCLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[57]);
$setuphold (posedge USERCLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[58]);
$setuphold (posedge USERCLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[59]);
$setuphold (posedge USERCLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[5]);
$setuphold (posedge USERCLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[60]);
$setuphold (posedge USERCLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[61]);
$setuphold (posedge USERCLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[62]);
$setuphold (posedge USERCLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[63]);
$setuphold (posedge USERCLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[6]);
$setuphold (posedge USERCLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[7]);
$setuphold (posedge USERCLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[8]);
$setuphold (posedge USERCLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[9]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[3]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[4]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[5]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[6]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[7]);
$setuphold (posedge USERCLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRCORIN_delay);
$setuphold (posedge USERCLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRUNCORIN_delay);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATAVALID_delay);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[0]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[1]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[2]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[0]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[1]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[2]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[3]);
$setuphold (posedge USERCLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGHOTRESETIN_delay);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHPRESENT_delay);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXINT_delay);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[3]);
$setuphold (posedge USERCLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGLINKTRAININGENABLE_delay);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[9]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTREAD_delay);
$setuphold (posedge USERCLK, negedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTTYPE1CFGREGACCESS_delay);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITE_delay);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMIT_delay);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[3]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONOUTPUTREQUEST_delay);
$setuphold (posedge USERCLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPOWERSTATECHANGEACK_delay);
$setuphold (posedge USERCLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREQPMTRANSITIONL23READY_delay);
$setuphold (posedge USERCLK, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[0]);
$setuphold (posedge USERCLK, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[1]);
$setuphold (posedge USERCLK, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[2]);
$setuphold (posedge USERCLK, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[3]);
$setuphold (posedge USERCLK, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[4]);
$setuphold (posedge USERCLK, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[5]);
$setuphold (posedge USERCLK, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[6]);
$setuphold (posedge USERCLK, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[9]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[9]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATAVALID_delay);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[0]);
$setuphold (posedge USERCLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[10]);
$setuphold (posedge USERCLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[11]);
$setuphold (posedge USERCLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[12]);
$setuphold (posedge USERCLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[13]);
$setuphold (posedge USERCLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[14]);
$setuphold (posedge USERCLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[15]);
$setuphold (posedge USERCLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[1]);
$setuphold (posedge USERCLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[2]);
$setuphold (posedge USERCLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[3]);
$setuphold (posedge USERCLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[4]);
$setuphold (posedge USERCLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[5]);
$setuphold (posedge USERCLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[6]);
$setuphold (posedge USERCLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[7]);
$setuphold (posedge USERCLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[8]);
$setuphold (posedge USERCLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[9]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[0]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[1]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[2]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[3]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[4]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[5]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[6]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[7]);
$setuphold (posedge USERCLK, negedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFMCAPREQUESTBYCONF_delay);
$setuphold (posedge USERCLK, negedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[0]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[10]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[11]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[12]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[13]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[14]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[15]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[16]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[17]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[18]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[19]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[1]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[20]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[21]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[22]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[23]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[24]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[25]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[26]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[27]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[28]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[29]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[2]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[30]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[31]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[3]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[4]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[5]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[6]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[7]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[8]);
$setuphold (posedge USERCLK, negedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[9]);
$setuphold (posedge USERCLK, negedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[0]);
$setuphold (posedge USERCLK, negedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[1]);
$setuphold (posedge USERCLK, negedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[2]);
$setuphold (posedge USERCLK, negedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[3]);
$setuphold (posedge USERCLK, negedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[0]);
$setuphold (posedge USERCLK, negedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[1]);
$setuphold (posedge USERCLK, negedge CONFREQVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQVALID_delay);
$setuphold (posedge USERCLK, negedge DBGCFGLOCALMGMTREGOVERRIDE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGCFGLOCALMGMTREGOVERRIDE_delay);
$setuphold (posedge USERCLK, negedge DBGDATASEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[0]);
$setuphold (posedge USERCLK, negedge DBGDATASEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[1]);
$setuphold (posedge USERCLK, negedge DBGDATASEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[2]);
$setuphold (posedge USERCLK, negedge DBGDATASEL[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[3]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[0]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[10]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[11]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[12]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[13]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[1]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[2]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[3]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[4]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[5]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[6]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[7]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[8]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[9]);
$setuphold (posedge USERCLK, negedge LL2LMSAXISTXTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTVALID_delay);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[0]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[1]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[2]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID0[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[3]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[0]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[1]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[2]);
$setuphold (posedge USERCLK, negedge LL2LMTXTLPID1[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[3]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[0]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[10]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[11]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[12]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[13]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[14]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[15]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[16]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[17]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[18]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[19]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[1]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[20]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[21]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[2]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[3]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[4]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[5]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[6]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[7]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[8]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[9]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[0]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[10]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[11]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[12]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[13]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[14]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[15]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[16]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[17]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[18]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[19]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[1]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[20]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[21]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[2]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[3]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[4]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[5]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[6]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[7]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[8]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[9]);
$setuphold (posedge USERCLK, negedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, PCIECQNPREQ_delay);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[100]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[101]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[102]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[103]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[104]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[105]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[106]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[107]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[108]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[109]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[110]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[111]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[112]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[113]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[114]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[115]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[116]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[117]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[118]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[119]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[120]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[121]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[122]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[123]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[124]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[125]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[126]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[127]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[128]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[129]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[130]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[131]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[132]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[133]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[134]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[135]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[136]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[137]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[138]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[139]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[140]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[141]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[142]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[143]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[144]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[145]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[146]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[147]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[148]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[149]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[150]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[151]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[152]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[153]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[154]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[155]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[156]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[157]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[158]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[159]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[160]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[161]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[162]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[163]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[164]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[165]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[166]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[167]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[168]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[169]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[170]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[171]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[172]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[173]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[174]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[175]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[176]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[177]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[178]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[179]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[180]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[181]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[182]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[183]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[184]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[185]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[186]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[187]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[188]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[189]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[190]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[191]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[192]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[193]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[194]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[195]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[196]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[197]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[198]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[199]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[200]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[201]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[202]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[203]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[204]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[205]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[206]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[207]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[208]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[209]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[210]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[211]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[212]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[213]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[214]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[215]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[216]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[217]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[218]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[219]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[220]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[221]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[222]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[223]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[224]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[225]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[226]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[227]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[228]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[229]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[230]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[231]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[232]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[233]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[234]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[235]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[236]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[237]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[238]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[239]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[240]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[241]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[242]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[243]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[244]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[245]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[246]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[247]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[248]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[249]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[250]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[251]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[252]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[253]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[254]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[255]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[33]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[34]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[35]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[36]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[37]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[38]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[39]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[40]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[41]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[42]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[43]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[44]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[45]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[46]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[47]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[48]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[49]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[50]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[51]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[52]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[53]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[54]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[55]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[56]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[57]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[58]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[59]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[60]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[61]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[62]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[63]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[64]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[65]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[66]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[67]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[68]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[69]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[70]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[71]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[72]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[73]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[74]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[75]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[76]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[77]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[78]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[79]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[80]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[81]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[82]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[83]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[84]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[85]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[86]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[87]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[88]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[89]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[90]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[91]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[92]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[93]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[94]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[95]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[96]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[97]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[98]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[99]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTLAST_delay);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTVALID_delay);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[100]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[101]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[102]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[103]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[104]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[105]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[106]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[107]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[108]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[109]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[110]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[111]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[112]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[113]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[114]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[115]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[116]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[117]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[118]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[119]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[120]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[121]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[122]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[123]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[124]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[125]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[126]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[127]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[128]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[129]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[130]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[131]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[132]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[133]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[134]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[135]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[136]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[137]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[138]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[139]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[140]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[141]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[142]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[143]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[144]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[145]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[146]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[147]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[148]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[149]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[150]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[151]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[152]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[153]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[154]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[155]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[156]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[157]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[158]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[159]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[160]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[161]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[162]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[163]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[164]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[165]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[166]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[167]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[168]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[169]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[170]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[171]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[172]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[173]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[174]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[175]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[176]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[177]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[178]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[179]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[180]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[181]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[182]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[183]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[184]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[185]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[186]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[187]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[188]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[189]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[190]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[191]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[192]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[193]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[194]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[195]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[196]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[197]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[198]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[199]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[200]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[201]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[202]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[203]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[204]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[205]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[206]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[207]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[208]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[209]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[210]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[211]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[212]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[213]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[214]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[215]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[216]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[217]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[218]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[219]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[220]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[221]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[222]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[223]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[224]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[225]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[226]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[227]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[228]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[229]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[230]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[231]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[232]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[233]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[234]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[235]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[236]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[237]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[238]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[239]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[240]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[241]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[242]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[243]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[244]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[245]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[246]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[247]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[248]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[249]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[250]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[251]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[252]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[253]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[254]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[255]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[60]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[61]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[62]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[63]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[64]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[65]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[66]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[67]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[68]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[69]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[70]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[71]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[72]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[73]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[74]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[75]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[76]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[77]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[78]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[79]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[80]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[81]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[82]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[83]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[84]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[85]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[86]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[87]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[88]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[89]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[90]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[91]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[92]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[93]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[94]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[95]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[96]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[97]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[98]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[99]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTLAST_delay);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTVALID_delay);
$setuphold (posedge USERCLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGCONFIGSPACEENABLE_delay);
$setuphold (posedge USERCLK, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[10]);
$setuphold (posedge USERCLK, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[11]);
$setuphold (posedge USERCLK, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[12]);
$setuphold (posedge USERCLK, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[13]);
$setuphold (posedge USERCLK, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[14]);
$setuphold (posedge USERCLK, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[15]);
$setuphold (posedge USERCLK, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[3]);
$setuphold (posedge USERCLK, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[4]);
$setuphold (posedge USERCLK, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[5]);
$setuphold (posedge USERCLK, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[6]);
$setuphold (posedge USERCLK, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[7]);
$setuphold (posedge USERCLK, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[8]);
$setuphold (posedge USERCLK, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDEVID_delay[9]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[3]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[4]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[5]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[6]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSBUSNUMBER_delay[7]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[3]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSDEVICENUMBER_delay[4]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[10]);
$setuphold (posedge USERCLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[11]);
$setuphold (posedge USERCLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[12]);
$setuphold (posedge USERCLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[13]);
$setuphold (posedge USERCLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[14]);
$setuphold (posedge USERCLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[15]);
$setuphold (posedge USERCLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[16]);
$setuphold (posedge USERCLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[17]);
$setuphold (posedge USERCLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[18]);
$setuphold (posedge USERCLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[19]);
$setuphold (posedge USERCLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[20]);
$setuphold (posedge USERCLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[21]);
$setuphold (posedge USERCLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[22]);
$setuphold (posedge USERCLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[23]);
$setuphold (posedge USERCLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[24]);
$setuphold (posedge USERCLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[25]);
$setuphold (posedge USERCLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[26]);
$setuphold (posedge USERCLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[27]);
$setuphold (posedge USERCLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[28]);
$setuphold (posedge USERCLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[29]);
$setuphold (posedge USERCLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[30]);
$setuphold (posedge USERCLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[31]);
$setuphold (posedge USERCLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[32]);
$setuphold (posedge USERCLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[33]);
$setuphold (posedge USERCLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[34]);
$setuphold (posedge USERCLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[35]);
$setuphold (posedge USERCLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[36]);
$setuphold (posedge USERCLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[37]);
$setuphold (posedge USERCLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[38]);
$setuphold (posedge USERCLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[39]);
$setuphold (posedge USERCLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[3]);
$setuphold (posedge USERCLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[40]);
$setuphold (posedge USERCLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[41]);
$setuphold (posedge USERCLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[42]);
$setuphold (posedge USERCLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[43]);
$setuphold (posedge USERCLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[44]);
$setuphold (posedge USERCLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[45]);
$setuphold (posedge USERCLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[46]);
$setuphold (posedge USERCLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[47]);
$setuphold (posedge USERCLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[48]);
$setuphold (posedge USERCLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[49]);
$setuphold (posedge USERCLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[4]);
$setuphold (posedge USERCLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[50]);
$setuphold (posedge USERCLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[51]);
$setuphold (posedge USERCLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[52]);
$setuphold (posedge USERCLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[53]);
$setuphold (posedge USERCLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[54]);
$setuphold (posedge USERCLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[55]);
$setuphold (posedge USERCLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[56]);
$setuphold (posedge USERCLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[57]);
$setuphold (posedge USERCLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[58]);
$setuphold (posedge USERCLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[59]);
$setuphold (posedge USERCLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[5]);
$setuphold (posedge USERCLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[60]);
$setuphold (posedge USERCLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[61]);
$setuphold (posedge USERCLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[62]);
$setuphold (posedge USERCLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[63]);
$setuphold (posedge USERCLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[6]);
$setuphold (posedge USERCLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[7]);
$setuphold (posedge USERCLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[8]);
$setuphold (posedge USERCLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSN_delay[9]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[3]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[4]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[5]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[6]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGDSPORTNUMBER_delay[7]);
$setuphold (posedge USERCLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRCORIN_delay);
$setuphold (posedge USERCLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGERRUNCORIN_delay);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATAVALID_delay);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGEXTREADDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[0]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[1]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFCSEL_delay[2]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[0]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[1]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[2]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGFLRDONE_delay[3]);
$setuphold (posedge USERCLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGHOTRESETIN_delay);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTINT_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIATTR_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIFUNCTIONNUMBER_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIINT_delay[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE_delay);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIPENDINGSTATUS_delay[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSISELECT_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHPRESENT_delay);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHSTTAG_delay[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSITPHTYPE_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[32]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[33]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[34]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[35]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[36]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[37]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[38]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[39]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[40]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[41]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[42]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[43]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[44]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[45]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[46]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[47]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[48]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[49]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[50]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[51]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[52]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[53]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[54]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[55]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[56]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[57]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[58]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[59]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[60]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[61]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[62]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[63]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXADDRESS_delay[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTMSIXINT_delay);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGINTERRUPTPENDING_delay[3]);
$setuphold (posedge USERCLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGLINKTRAININGENABLE_delay);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTADDR_delay[9]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTBYTEENABLE_delay[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTREAD_delay);
$setuphold (posedge USERCLK, posedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTTYPE1CFGREGACCESS_delay);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITE_delay);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMGMTWRITEDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMIT_delay);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGMSGTRANSMITTYPE_delay[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCSTATUSCONTROL_delay[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONNUMBER_delay[3]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPERFUNCTIONOUTPUTREQUEST_delay);
$setuphold (posedge USERCLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGPOWERSTATECHANGEACK_delay);
$setuphold (posedge USERCLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREQPMTRANSITIONL23READY_delay);
$setuphold (posedge USERCLK, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[0]);
$setuphold (posedge USERCLK, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[1]);
$setuphold (posedge USERCLK, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[2]);
$setuphold (posedge USERCLK, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[3]);
$setuphold (posedge USERCLK, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[4]);
$setuphold (posedge USERCLK, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[5]);
$setuphold (posedge USERCLK, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[6]);
$setuphold (posedge USERCLK, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGREVID_delay[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSID_delay[9]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGSUBSYSVENDID_delay[9]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATAVALID_delay);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGTPHSTTREADDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[0]);
$setuphold (posedge USERCLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[10]);
$setuphold (posedge USERCLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[11]);
$setuphold (posedge USERCLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[12]);
$setuphold (posedge USERCLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[13]);
$setuphold (posedge USERCLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[14]);
$setuphold (posedge USERCLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[15]);
$setuphold (posedge USERCLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[1]);
$setuphold (posedge USERCLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[2]);
$setuphold (posedge USERCLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[3]);
$setuphold (posedge USERCLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[4]);
$setuphold (posedge USERCLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[5]);
$setuphold (posedge USERCLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[6]);
$setuphold (posedge USERCLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[7]);
$setuphold (posedge USERCLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[8]);
$setuphold (posedge USERCLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVENDID_delay[9]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[0]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[1]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[2]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[3]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[4]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[5]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[6]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CFGVFFLRDONE_delay[7]);
$setuphold (posedge USERCLK, posedge CONFMCAPREQUESTBYCONF, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFMCAPREQUESTBYCONF_delay);
$setuphold (posedge USERCLK, posedge CONFREQDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[0]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[10]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[11]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[12]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[13]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[14]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[15]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[16]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[17]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[18]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[19]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[1]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[20]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[21]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[22]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[23]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[24]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[25]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[26]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[27]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[28]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[29]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[2]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[30]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[31]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[3]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[4]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[5]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[6]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[7]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[8]);
$setuphold (posedge USERCLK, posedge CONFREQDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQDATA_delay[9]);
$setuphold (posedge USERCLK, posedge CONFREQREGNUM[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[0]);
$setuphold (posedge USERCLK, posedge CONFREQREGNUM[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[1]);
$setuphold (posedge USERCLK, posedge CONFREQREGNUM[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[2]);
$setuphold (posedge USERCLK, posedge CONFREQREGNUM[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQREGNUM_delay[3]);
$setuphold (posedge USERCLK, posedge CONFREQTYPE[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[0]);
$setuphold (posedge USERCLK, posedge CONFREQTYPE[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQTYPE_delay[1]);
$setuphold (posedge USERCLK, posedge CONFREQVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, CONFREQVALID_delay);
$setuphold (posedge USERCLK, posedge DBGCFGLOCALMGMTREGOVERRIDE, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGCFGLOCALMGMTREGOVERRIDE_delay);
$setuphold (posedge USERCLK, posedge DBGDATASEL[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[0]);
$setuphold (posedge USERCLK, posedge DBGDATASEL[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[1]);
$setuphold (posedge USERCLK, posedge DBGDATASEL[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[2]);
$setuphold (posedge USERCLK, posedge DBGDATASEL[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, DBGDATASEL_delay[3]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[0]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[10]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[11]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[12]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[13]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[1]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[2]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[3]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[4]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[5]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[6]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[7]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[8]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTUSER_delay[9]);
$setuphold (posedge USERCLK, posedge LL2LMSAXISTXTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMSAXISTXTVALID_delay);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[0]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[1]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[2]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID0[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID0_delay[3]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[0]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[1]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[2]);
$setuphold (posedge USERCLK, posedge LL2LMTXTLPID1[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, LL2LMTXTLPID1_delay[3]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[0]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[10]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[11]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[12]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[13]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[14]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[15]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[16]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[17]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[18]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[19]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[1]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[20]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[21]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[2]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[3]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[4]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[5]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[6]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[7]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[8]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISCQTREADY_delay[9]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[0]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[10]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[11]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[12]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[13]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[14]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[15]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[16]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[17]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[18]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[19]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[1]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[20]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[21]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[2]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[3]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[4]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[5]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[6]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[7]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[8]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, MAXISRCTREADY_delay[9]);
$setuphold (posedge USERCLK, posedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, PCIECQNPREQ_delay);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[100]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[101]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[102]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[103]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[104]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[105]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[106]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[107]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[108]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[109]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[110]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[111]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[112]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[113]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[114]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[115]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[116]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[117]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[118]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[119]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[120]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[121]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[122]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[123]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[124]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[125]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[126]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[127]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[128]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[129]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[130]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[131]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[132]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[133]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[134]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[135]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[136]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[137]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[138]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[139]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[140]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[141]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[142]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[143]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[144]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[145]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[146]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[147]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[148]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[149]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[150]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[151]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[152]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[153]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[154]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[155]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[156]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[157]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[158]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[159]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[160]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[161]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[162]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[163]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[164]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[165]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[166]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[167]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[168]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[169]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[170]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[171]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[172]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[173]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[174]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[175]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[176]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[177]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[178]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[179]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[180]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[181]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[182]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[183]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[184]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[185]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[186]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[187]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[188]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[189]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[190]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[191]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[192]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[193]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[194]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[195]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[196]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[197]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[198]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[199]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[200]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[201]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[202]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[203]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[204]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[205]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[206]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[207]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[208]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[209]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[210]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[211]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[212]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[213]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[214]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[215]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[216]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[217]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[218]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[219]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[220]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[221]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[222]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[223]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[224]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[225]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[226]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[227]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[228]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[229]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[230]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[231]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[232]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[233]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[234]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[235]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[236]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[237]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[238]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[239]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[240]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[241]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[242]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[243]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[244]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[245]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[246]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[247]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[248]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[249]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[250]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[251]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[252]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[253]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[254]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[255]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[33]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[34]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[35]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[36]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[37]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[38]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[39]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[40]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[41]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[42]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[43]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[44]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[45]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[46]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[47]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[48]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[49]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[50]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[51]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[52]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[53]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[54]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[55]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[56]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[57]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[58]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[59]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[60]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[61]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[62]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[63]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[64]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[65]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[66]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[67]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[68]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[69]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[70]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[71]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[72]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[73]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[74]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[75]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[76]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[77]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[78]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[79]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[80]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[81]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[82]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[83]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[84]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[85]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[86]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[87]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[88]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[89]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[90]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[91]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[92]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[93]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[94]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[95]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[96]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[97]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[98]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[99]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTDATA_delay[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTKEEP_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTLAST_delay);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTUSER_delay[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISCCTVALID_delay);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[100]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[101]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[102]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[103]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[104]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[105]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[106]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[107]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[108]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[109]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[110]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[111]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[112]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[113]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[114]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[115]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[116]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[117]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[118]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[119]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[120]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[121]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[122]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[123]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[124]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[125]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[126]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[127]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[128]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[129]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[130]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[131]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[132]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[133]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[134]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[135]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[136]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[137]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[138]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[139]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[140]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[141]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[142]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[143]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[144]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[145]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[146]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[147]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[148]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[149]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[150]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[151]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[152]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[153]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[154]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[155]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[156]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[157]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[158]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[159]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[160]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[161]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[162]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[163]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[164]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[165]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[166]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[167]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[168]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[169]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[170]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[171]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[172]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[173]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[174]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[175]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[176]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[177]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[178]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[179]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[180]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[181]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[182]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[183]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[184]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[185]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[186]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[187]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[188]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[189]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[190]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[191]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[192]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[193]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[194]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[195]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[196]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[197]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[198]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[199]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[200]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[201]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[202]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[203]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[204]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[205]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[206]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[207]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[208]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[209]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[210]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[211]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[212]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[213]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[214]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[215]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[216]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[217]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[218]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[219]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[220]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[221]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[222]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[223]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[224]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[225]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[226]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[227]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[228]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[229]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[230]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[231]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[232]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[233]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[234]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[235]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[236]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[237]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[238]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[239]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[240]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[241]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[242]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[243]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[244]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[245]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[246]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[247]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[248]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[249]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[250]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[251]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[252]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[253]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[254]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[255]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[60]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[61]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[62]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[63]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[64]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[65]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[66]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[67]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[68]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[69]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[70]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[71]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[72]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[73]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[74]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[75]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[76]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[77]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[78]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[79]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[80]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[81]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[82]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[83]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[84]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[85]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[86]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[87]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[88]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[89]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[90]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[91]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[92]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[93]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[94]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[95]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[96]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[97]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[98]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[99]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTDATA_delay[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTKEEP_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTLAST_delay);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTUSER_delay[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, USERCLK_delay, SAXISRQTVALID_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHASER_IN.v 0000664 0000000 0000000 00000045036 12327044266 0023002 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fujisan PHASER IN
// /__/ /\ Filename : PHASER_IN.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 03JUN2010 yaml update
// 12JUL2010 enable secureip
// 12AUG2010 yaml, rtl update
// 24SEP2010 yaml, rtl update
// 29SEP2010 add width checks
// 13OCT2010 yaml, rtl update
// 26OCT2010 delay yaml, rtl update
// 02NOV2010 yaml update
// 05NOV2010 secureip parameter name update
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 09DEC2010 586079 yaml update, tie off defaults
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default
// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert
// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart
// 22MAY2012 660507 DQS_AUTO_RECAL default value change
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_IN #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CLKOUT_DIV = 4,
parameter DQS_BIAS_MODE = "FALSE",
parameter EN_ISERDES_RST = "FALSE",
parameter integer FINE_DELAY = 0,
parameter FREQ_REF_DIV = "NONE",
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real MEMREFCLK_PERIOD = 0.000,
parameter OUTPUT_CLK_SRC = "PHASE_REF",
parameter real PHASEREFCLK_PERIOD = 0.000,
parameter real REFCLK_PERIOD = 0.000,
parameter integer SEL_CLK_OFFSET = 5,
parameter SYNC_IN_DIV_RST = "FALSE"
) (
output [5:0] COUNTERREADVAL,
output FINEOVERFLOW,
output ICLK,
output ICLKDIV,
output ISERDESRST,
output RCLK,
input COUNTERLOADEN,
input [5:0] COUNTERLOADVAL,
input COUNTERREADEN,
input DIVIDERST,
input EDGEADV,
input FINEENABLE,
input FINEINC,
input FREQREFCLK,
input MEMREFCLK,
input PHASEREFCLK,
input [1:0] RANKSEL,
input RST,
input SYNCIN,
input SYSCLK
);
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_IN";
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg [0:0] BURST_MODE_BINARY;
reg [0:0] CALIB_EDGE_IN_INV_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DQS_AUTO_RECAL_BINARY;
reg [0:0] DQS_BIAS_MODE_BINARY;
reg [0:0] EN_ISERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] GATE_SET_CLK_MUX_BINARY;
reg [0:0] HALF_CYCLE_ADJ_BINARY;
reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
reg [0:0] PHASER_IN_EN_BINARY;
reg [0:0] REG_OPT_1_BINARY;
reg [0:0] REG_OPT_2_BINARY;
reg [0:0] REG_OPT_4_BINARY;
reg [0:0] RST_SEL_BINARY;
reg [0:0] SEL_OUT_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [0:0] TEST_BP_BINARY;
reg [0:0] UPDATE_NONACTIVE_BINARY;
reg [0:0] WR_CYCLES_BINARY;
reg [1:0] FREQ_REF_DIV_BINARY;
reg [1:0] RD_ADDR_INIT_BINARY;
reg [2:0] DQS_FIND_PATTERN_BINARY;
reg [2:0] PD_REVERSE_BINARY;
reg [2:0] SEL_CLK_OFFSET_BINARY;
reg [2:0] STG1_PD_UPDATE_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [3:0] OUTPUT_CLK_SRC_BINARY;
reg [5:0] FINE_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
BURST_MODE_BINARY <= 1'b0;
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
$finish;
end
endcase
CTL_MODE_BINARY <= 1'b0; // model alert
case (DQS_BIAS_MODE)
"FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0;
"TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE);
$finish;
end
endcase
case (EN_ISERDES_RST)
"FALSE" : EN_ISERDES_RST_BINARY <= 1'b0;
"TRUE" : EN_ISERDES_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute EN_ISERDES_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ISERDES_RST);
$finish;
end
endcase
EN_TEST_RING_BINARY <= 1'b0;
case (FREQ_REF_DIV)
"NONE" : FREQ_REF_DIV_BINARY <= 2'b00;
"DIV2" : FREQ_REF_DIV_BINARY <= 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV);
$finish;
end
endcase
HALF_CYCLE_ADJ_BINARY <= 1'b0;
ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1;
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000;
"DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000;
"MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
$finish;
end
endcase
PD_REVERSE_BINARY <= 3'b011;
PHASER_IN_EN_BINARY <= 1'b1;
STG1_PD_UPDATE_BINARY <= 3'b000;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
$finish;
end
endcase
UPDATE_NONACTIVE_BINARY <= 1'b0;
WR_CYCLES_BINARY <= 1'b0;
CALIB_EDGE_IN_INV_BINARY <= 1'b0;
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
DQS_AUTO_RECAL_BINARY <= 1'b1;
DQS_FIND_PATTERN_BINARY <= 3'b001;
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
$finish;
end
GATE_SET_CLK_MUX_BINARY <= 1'b0;
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
$finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
$finish;
end
RD_ADDR_INIT_BINARY <= 2'b00;
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
$finish;
end
REG_OPT_1_BINARY <= 1'b0;
REG_OPT_2_BINARY <= 1'b0;
REG_OPT_4_BINARY <= 1'b0;
RST_SEL_BINARY <= 1'b0;
if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7))
SEL_CLK_OFFSET_BINARY <= 0; // Model Alert
else begin
$display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET);
$finish;
end
SEL_OUT_BINARY <= 1'b0;
TEST_BP_BINARY <= 1'b0;
end
wire [3:0] delay_TESTOUT;
wire [5:0] delay_COUNTERREADVAL;
wire [8:0] delay_STG1REGR;
wire delay_DQSFOUND;
wire delay_DQSOUTOFRANGE;
wire delay_FINEOVERFLOW;
wire delay_ICLK;
wire delay_ICLKDIV;
wire delay_ISERDESRST;
wire delay_PHASELOCKED;
wire delay_RCLK;
wire delay_SCANOUT;
wire delay_STG1OVERFLOW;
wire delay_WRENABLE;
wire [13:0] delay_TESTIN = 14'h3fff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY = 2'b0;
wire [1:0] delay_RANKSEL;
wire [1:0] delay_RANKSELPHY = 2'b0;
wire [5:0] delay_COUNTERLOADVAL;
wire [8:0] delay_STG1REGL = 9'h1ff;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY = 1'b0;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST;
wire delay_EDGEADV;
wire delay_ENSTG1 = 1'b1;
wire delay_ENSTG1ADJUSTB = 1'b1;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_RSTDQSFIND = 1'b1;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELCALORSTG1 = 1'b1;
wire delay_STG1INCDEC = 1'b1;
wire delay_STG1LOAD = 1'b1;
wire delay_STG1READ = 1'b1;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) ICLK = delay_ICLK;
assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV;
assign #(OUTCLK_DELAY) RCLK = delay_RCLK;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) ISERDESRST = delay_ISERDESRST;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
assign #(in_delay) delay_DIVIDERST = DIVIDERST;
assign #(in_delay) delay_EDGEADV = EDGEADV;
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_FREQREFCLK = FREQREFCLK;
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
`ifndef XIL_TIMING
assign #(in_delay) delay_RANKSEL = RANKSEL;
`endif
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_IN # (
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_IN_INST (
.BURST_MODE (BURST_MODE_BINARY),
.CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY),
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY),
.DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY),
.DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY),
.EN_ISERDES_RST (EN_ISERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.FREQ_REF_DIV (FREQ_REF_DIV_BINARY),
.GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY),
.HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY),
.ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PD_REVERSE (PD_REVERSE_BINARY),
.PHASER_IN_EN (PHASER_IN_EN_BINARY),
.RD_ADDR_INIT (RD_ADDR_INIT_BINARY),
.REG_OPT_1 (REG_OPT_1_BINARY),
.REG_OPT_2 (REG_OPT_2_BINARY),
.REG_OPT_4 (REG_OPT_4_BINARY),
.RST_SEL (RST_SEL_BINARY),
.SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY),
.SEL_OUT (SEL_OUT_BINARY),
.STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_BP (TEST_BP_BINARY),
.UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY),
.WR_CYCLES (WR_CYCLES_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.DQSFOUND (delay_DQSFOUND),
.DQSOUTOFRANGE (delay_DQSOUTOFRANGE),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.ICLK (delay_ICLK),
.ICLKDIV (delay_ICLKDIV),
.ISERDESRST (delay_ISERDESRST),
.PHASELOCKED (delay_PHASELOCKED),
.RCLK (delay_RCLK),
.SCANOUT (delay_SCANOUT),
.STG1OVERFLOW (delay_STG1OVERFLOW),
.STG1REGR (delay_STG1REGR),
.TESTOUT (delay_TESTOUT),
.WRENABLE (delay_WRENABLE),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.ENSTG1 (delay_ENSTG1),
.ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RANKSEL (delay_RANKSEL),
.RANKSELPHY (delay_RANKSELPHY),
.RST (delay_RST ^ IS_RST_INVERTED_REG),
.RSTDQSFIND (delay_RSTDQSFIND),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELCALORSTG1 (delay_SELCALORSTG1),
.STG1INCDEC (delay_STG1INCDEC),
.STG1LOAD (delay_STG1LOAD),
.STG1READ (delay_STG1READ),
.STG1REGL (delay_STG1REGL),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST);
$setuphold (posedge SYSCLK, negedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, negedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge DIVIDERST, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_DIVIDERST);
$setuphold (posedge SYSCLK, posedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge RANKSEL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RANKSEL);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_IN
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHASER_IN_PHY.v 0000664 0000000 0000000 00000050104 12327044266 0023512 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fujisan PHASER IN
// /__/ /\ Filename : PHASER_IN_PHY.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 03JUN2010 yaml update
// 12JUL2010 enable secureip
// 12AUG2010 yaml, rtl update
// 24SEP2010 yaml, rtl update
// 29SEP2010 add width checks
// 13OCT2010 yaml, rtl update
// 26OCT2010 delay yaml, rtl update
// 02NOV2010 yaml update
// 05NOV2010 secureip parameter name update
// 11NOV2010 582473 multiple drivers on delay_MEMREFCLK
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 09DEC2010 586079 yaml update, tie off defaults
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default
// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert
// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart
// 22MAY2012 660507 DQS_AUTO_RECAL default value change
// 13JUN2012 664620 Change dly ref clk for DQSFOUND
// 10JUL2012 669266 Make DQS_AUTO_RECAL and DQS_FIND_PATTERN visible
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_IN_PHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BURST_MODE = "FALSE",
parameter integer CLKOUT_DIV = 4,
parameter [0:0] DQS_AUTO_RECAL = 1'b1,
parameter DQS_BIAS_MODE = "FALSE",
parameter [2:0] DQS_FIND_PATTERN = 3'b001,
parameter integer FINE_DELAY = 0,
parameter FREQ_REF_DIV = "NONE",
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real MEMREFCLK_PERIOD = 0.000,
parameter OUTPUT_CLK_SRC = "PHASE_REF",
parameter real PHASEREFCLK_PERIOD = 0.000,
parameter real REFCLK_PERIOD = 0.000,
parameter integer SEL_CLK_OFFSET = 5,
parameter SYNC_IN_DIV_RST = "FALSE",
parameter WR_CYCLES = "FALSE"
) (
output [5:0] COUNTERREADVAL,
output DQSFOUND,
output DQSOUTOFRANGE,
output FINEOVERFLOW,
output ICLK,
output ICLKDIV,
output ISERDESRST,
output PHASELOCKED,
output RCLK,
output WRENABLE,
input BURSTPENDINGPHY,
input COUNTERLOADEN,
input [5:0] COUNTERLOADVAL,
input COUNTERREADEN,
input [1:0] ENCALIBPHY,
input FINEENABLE,
input FINEINC,
input FREQREFCLK,
input MEMREFCLK,
input PHASEREFCLK,
input [1:0] RANKSELPHY,
input RST,
input RSTDQSFIND,
input SYNCIN,
input SYSCLK
);
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_IN_PHY";
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg [0:0] BURST_MODE_BINARY;
reg [0:0] CALIB_EDGE_IN_INV_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DQS_AUTO_RECAL_BINARY;
reg [0:0] DQS_BIAS_MODE_BINARY;
reg [0:0] EN_ISERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] GATE_SET_CLK_MUX_BINARY;
reg [0:0] HALF_CYCLE_ADJ_BINARY;
reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
reg [0:0] PHASER_IN_EN_BINARY;
reg [0:0] REG_OPT_1_BINARY;
reg [0:0] REG_OPT_2_BINARY;
reg [0:0] REG_OPT_4_BINARY;
reg [0:0] RST_SEL_BINARY;
reg [0:0] SEL_OUT_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [0:0] TEST_BP_BINARY;
reg [0:0] UPDATE_NONACTIVE_BINARY;
reg [0:0] WR_CYCLES_BINARY;
reg [1:0] FREQ_REF_DIV_BINARY;
reg [1:0] RD_ADDR_INIT_BINARY;
reg [2:0] DQS_FIND_PATTERN_BINARY;
reg [2:0] PD_REVERSE_BINARY;
reg [2:0] SEL_CLK_OFFSET_BINARY;
reg [2:0] STG1_PD_UPDATE_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [3:0] OUTPUT_CLK_SRC_BINARY;
reg [5:0] FINE_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (BURST_MODE)
"FALSE" : BURST_MODE_BINARY <= 1'b0;
"TRUE" : BURST_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute BURST_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BURST_MODE);
$finish;
end
endcase
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
$finish;
end
endcase
CTL_MODE_BINARY <= 1'b1; // model alert
case (DQS_BIAS_MODE)
"FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0;
"TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE);
$finish;
end
endcase
EN_ISERDES_RST_BINARY <= 1'b0;
EN_TEST_RING_BINARY <= 1'b0;
case (FREQ_REF_DIV)
"NONE" : FREQ_REF_DIV_BINARY <= 2'b00;
"DIV2" : FREQ_REF_DIV_BINARY <= 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV);
$finish;
end
endcase
HALF_CYCLE_ADJ_BINARY <= 1'b0;
ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1;
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000;
"DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000;
"MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
$finish;
end
endcase
PD_REVERSE_BINARY <= 3'b011;
PHASER_IN_EN_BINARY <= 1'b1;
STG1_PD_UPDATE_BINARY <= 3'b000;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
$finish;
end
endcase
UPDATE_NONACTIVE_BINARY <= 1'b0;
case (WR_CYCLES)
"FALSE" : WR_CYCLES_BINARY <= 1'b0;
"TRUE" : WR_CYCLES_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute WR_CYCLES on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, WR_CYCLES);
$finish;
end
endcase
CALIB_EDGE_IN_INV_BINARY <= 1'b0;
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
if ((DQS_AUTO_RECAL >= 1'b0) && (DQS_AUTO_RECAL <= 1'b1))
DQS_AUTO_RECAL_BINARY <= DQS_AUTO_RECAL;
else begin
$display("Attribute Syntax Error : The Attribute DQS_AUTO_RECAL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DQS_AUTO_RECAL);
$finish;
end
if ((DQS_FIND_PATTERN >= 3'b000) && (DQS_FIND_PATTERN <= 3'b111))
DQS_FIND_PATTERN_BINARY <= DQS_FIND_PATTERN;
else begin
$display("Attribute Syntax Error : The Attribute DQS_FIND_PATTERN on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, DQS_FIND_PATTERN);
$finish;
end
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
$finish;
end
GATE_SET_CLK_MUX_BINARY <= 1'b0;
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
$finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
$finish;
end
RD_ADDR_INIT_BINARY <= 2'b00;
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
$finish;
end
REG_OPT_1_BINARY <= 1'b0;
REG_OPT_2_BINARY <= 1'b0;
REG_OPT_4_BINARY <= 1'b0;
RST_SEL_BINARY <= 1'b0;
if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7))
SEL_CLK_OFFSET_BINARY <= 0; // Model Alert
else begin
$display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET);
$finish;
end
SEL_OUT_BINARY <= 1'b0;
TEST_BP_BINARY <= 1'b0;
end
wire [3:0] delay_TESTOUT;
wire [5:0] delay_COUNTERREADVAL;
wire [8:0] delay_STG1REGR;
wire delay_DQSFOUND;
wire delay_DQSOUTOFRANGE;
wire delay_FINEOVERFLOW;
wire delay_ICLK;
wire delay_ICLKDIV;
wire delay_ISERDESRST;
wire delay_PHASELOCKED;
wire delay_RCLK;
wire delay_SCANOUT;
wire delay_STG1OVERFLOW;
wire delay_WRENABLE;
wire [13:0] delay_TESTIN = 14'h3fff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY;
wire [1:0] delay_RANKSEL = 2'b0;
wire [1:0] delay_RANKSELPHY;
wire [5:0] delay_COUNTERLOADVAL;
wire [8:0] delay_STG1REGL = 9'h1ff;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST = 1'b0;
wire delay_EDGEADV = 1'b0;
wire delay_ENSTG1 = 1'b1;
wire delay_ENSTG1ADJUSTB = 1'b1;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_RSTDQSFIND;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELCALORSTG1 = 1'b1;
wire delay_STG1INCDEC = 1'b1;
wire delay_STG1LOAD = 1'b1;
wire delay_STG1READ = 1'b1;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) ICLK = delay_ICLK;
assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV;
assign #(OUTCLK_DELAY) RCLK = delay_RCLK;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) DQSFOUND = delay_DQSFOUND;
assign #(out_delay) DQSOUTOFRANGE = delay_DQSOUTOFRANGE;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) ISERDESRST = delay_ISERDESRST;
assign #(out_delay) PHASELOCKED = delay_PHASELOCKED;
assign #(out_delay) WRENABLE = delay_WRENABLE;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
`endif
assign #(in_delay) delay_BURSTPENDINGPHY = BURSTPENDINGPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
`endif
assign #(in_delay) delay_ENCALIBPHY = ENCALIBPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_FREQREFCLK = FREQREFCLK;
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
assign #(in_delay) delay_RANKSELPHY = RANKSELPHY;
assign #(in_delay) delay_RST = RST;
`ifndef XIL_TIMING
assign #(in_delay) delay_RSTDQSFIND = RSTDQSFIND;
`endif
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_IN # (
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_IN_INST (
.BURST_MODE (BURST_MODE_BINARY),
.CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY),
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY),
.DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY),
.DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY),
.EN_ISERDES_RST (EN_ISERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.FREQ_REF_DIV (FREQ_REF_DIV_BINARY),
.GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY),
.HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY),
.ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PD_REVERSE (PD_REVERSE_BINARY),
.PHASER_IN_EN (PHASER_IN_EN_BINARY),
.RD_ADDR_INIT (RD_ADDR_INIT_BINARY),
.REG_OPT_1 (REG_OPT_1_BINARY),
.REG_OPT_2 (REG_OPT_2_BINARY),
.REG_OPT_4 (REG_OPT_4_BINARY),
.RST_SEL (RST_SEL_BINARY),
.SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY),
.SEL_OUT (SEL_OUT_BINARY),
.STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_BP (TEST_BP_BINARY),
.UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY),
.WR_CYCLES (WR_CYCLES_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.DQSFOUND (delay_DQSFOUND),
.DQSOUTOFRANGE (delay_DQSOUTOFRANGE),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.ICLK (delay_ICLK),
.ICLKDIV (delay_ICLKDIV),
.ISERDESRST (delay_ISERDESRST),
.PHASELOCKED (delay_PHASELOCKED),
.RCLK (delay_RCLK),
.SCANOUT (delay_SCANOUT),
.STG1OVERFLOW (delay_STG1OVERFLOW),
.STG1REGR (delay_STG1REGR),
.TESTOUT (delay_TESTOUT),
.WRENABLE (delay_WRENABLE),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.ENSTG1 (delay_ENSTG1),
.ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RANKSEL (delay_RANKSEL),
.RANKSELPHY (delay_RANKSELPHY),
.RST (delay_RST ^ IS_RST_INVERTED_REG),
.RSTDQSFIND (delay_RSTDQSFIND),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELCALORSTG1 (delay_SELCALORSTG1),
.STG1INCDEC (delay_STG1INCDEC),
.STG1LOAD (delay_STG1LOAD),
.STG1READ (delay_STG1READ),
.STG1REGL (delay_STG1REGL),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, negedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( MEMREFCLK *> DQSFOUND) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( RST *> DQSOUTOFRANGE) = (10:10:10, 10:10:10);
( RST *> PHASELOCKED) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_IN_PHY
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHASER_OUT.v 0000664 0000000 0000000 00000042715 12327044266 0023144 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan PHASER OUT
// /__/ /\ Filename : PHASER_OUT.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 12JUL2010 enable secureip
// 14JUL2010 Hook up GSR
// 26AUG2010 rtl, yaml update
// 24SEP2010 rtl, yaml update
// 29SEP2010 add width checks
// 13OCT2010 rtl, yaml update
// 26OCT2010 rtl update
// delay yaml update
// 02NOV2010 yaml update, correct tieoffs
// 05NOV2010 secureip parameter name update
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC, STG1_BYPASS
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yml update, remove SIM_SPEEDUP make default
// 02SEP2011 623558 dly.yml update
// 15FEB2012 646230 yml update, add param PO
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_OUT (
COARSEOVERFLOW,
COUNTERREADVAL,
FINEOVERFLOW,
OCLK,
OCLKDELAYED,
OCLKDIV,
OSERDESRST,
COARSEENABLE,
COARSEINC,
COUNTERLOADEN,
COUNTERLOADVAL,
COUNTERREADEN,
DIVIDERST,
EDGEADV,
FINEENABLE,
FINEINC,
FREQREFCLK,
MEMREFCLK,
PHASEREFCLK,
RST,
SELFINEOCLKDELAY,
SYNCIN,
SYSCLK
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer CLKOUT_DIV = 4;
parameter COARSE_BYPASS = "FALSE";
parameter integer COARSE_DELAY = 0;
parameter EN_OSERDES_RST = "FALSE";
parameter integer FINE_DELAY = 0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
parameter real MEMREFCLK_PERIOD = 0.000;
parameter OCLKDELAY_INV = "FALSE";
parameter integer OCLK_DELAY = 0;
parameter OUTPUT_CLK_SRC = "PHASE_REF";
parameter real PHASEREFCLK_PERIOD = 0.000;
parameter [2:0] PO = 3'b000;
parameter real REFCLK_PERIOD = 0.000;
parameter SYNC_IN_DIV_RST = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_OUT";
output COARSEOVERFLOW;
output FINEOVERFLOW;
output OCLK;
output OCLKDELAYED;
output OCLKDIV;
output OSERDESRST;
output [8:0] COUNTERREADVAL;
input COARSEENABLE;
input COARSEINC;
input COUNTERLOADEN;
input COUNTERREADEN;
input DIVIDERST;
input EDGEADV;
input FINEENABLE;
input FINEINC;
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
input RST;
input SELFINEOCLKDELAY;
input SYNCIN;
input SYSCLK;
input [8:0] COUNTERLOADVAL;
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
reg [0:0] COARSE_BYPASS_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DATA_CTL_N_BINARY;
reg [0:0] DATA_RD_CYCLES_BINARY;
reg [0:0] EN_OSERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] OCLKDELAY_INV_BINARY;
reg [0:0] PHASER_OUT_EN_BINARY;
reg [0:0] STG1_BYPASS_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [10:0] TEST_OPT_BINARY;
reg [1:0] OUTPUT_CLK_SRC_BINARY;
reg [2:0] PO_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [5:0] COARSE_DELAY_BINARY;
reg [5:0] FINE_DELAY_BINARY;
reg [5:0] OCLK_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
$finish;
end
endcase
case (COARSE_BYPASS)
"FALSE" : COARSE_BYPASS_BINARY <= 1'b0;
"TRUE" : COARSE_BYPASS_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute COARSE_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, COARSE_BYPASS);
$finish;
end
endcase
CTL_MODE_BINARY <= 1'b0; // model alert
DATA_CTL_N_BINARY <= 1'b0;
DATA_RD_CYCLES_BINARY <= 1'b0;
case (EN_OSERDES_RST)
"FALSE" : EN_OSERDES_RST_BINARY <= 1'b0;
"TRUE" : EN_OSERDES_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute EN_OSERDES_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_OSERDES_RST);
$finish;
end
endcase
EN_TEST_RING_BINARY <= 1'b0;
case (OCLKDELAY_INV)
"FALSE" : OCLKDELAY_INV_BINARY <= 1'b0;
"TRUE" : OCLKDELAY_INV_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute OCLKDELAY_INV on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OCLKDELAY_INV);
$finish;
end
endcase
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b00;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b11;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b01;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_PHASE_REF, DELAYED_REF or FREQ_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
$finish;
end
endcase
PHASER_OUT_EN_BINARY <= 1'b1;
if (OUTPUT_CLK_SRC == "DELAYED_PHASE_REF")
STG1_BYPASS_BINARY <= 1'b0;
else
STG1_BYPASS_BINARY <= 1'b1;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
$finish;
end
endcase
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
if ((COARSE_DELAY >= 0) && (COARSE_DELAY <= 63))
COARSE_DELAY_BINARY <= COARSE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute COARSE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, COARSE_DELAY);
$finish;
end
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
$finish;
end
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
$finish;
end
if ((OCLK_DELAY >= 0) && (OCLK_DELAY <= 63))
OCLK_DELAY_BINARY <= OCLK_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute OCLK_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, OCLK_DELAY);
$finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
$finish;
end
if ((PO >= 3'b000) && (PO <= 3'b111))
PO_BINARY <= PO;
else begin
$display("Attribute Syntax Error : The Attribute PO on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PO);
$finish;
end
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
$finish;
end
TEST_OPT_BINARY <= {2'b0,PO,6'b0};
end
wire [1:0] delay_CTSBUS;
wire [1:0] delay_DQSBUS;
wire [1:0] delay_DTSBUS;
wire [3:0] delay_TESTOUT;
wire [8:0] delay_COUNTERREADVAL;
wire delay_COARSEOVERFLOW;
wire delay_FINEOVERFLOW;
wire delay_OCLK;
wire delay_OCLKDELAYED;
wire delay_OCLKDIV;
wire delay_OSERDESRST;
wire delay_RDENABLE;
wire delay_SCANOUT;
wire [15:0] delay_TESTIN = 16'hffff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY = 2'b0;
wire [8:0] delay_COUNTERLOADVAL;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY = 1'b0;
wire delay_COARSEENABLE;
wire delay_COARSEINC;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST;
wire delay_EDGEADV;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELFINEOCLKDELAY;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) OCLKDELAYED = delay_OCLKDELAYED;
assign #(OUTCLK_DELAY) OCLKDIV = delay_OCLKDIV;
assign #(OUTCLK_DELAY) OCLK = delay_OCLK;
assign #(out_delay) COARSEOVERFLOW = delay_COARSEOVERFLOW;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) OSERDESRST = delay_OSERDESRST;
assign #(INCLK_DELAY) delay_FREQREFCLK = FREQREFCLK;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
assign #(in_delay) delay_COARSEENABLE = COARSEENABLE;
assign #(in_delay) delay_COARSEINC = COARSEINC;
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
`endif
assign #(in_delay) delay_DIVIDERST = DIVIDERST;
`ifndef XIL_TIMING
assign #(in_delay) delay_EDGEADV = EDGEADV;
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SELFINEOCLKDELAY = SELFINEOCLKDELAY;
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_OUT #(
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_OUT_INST (
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.COARSE_BYPASS (COARSE_BYPASS_BINARY),
.COARSE_DELAY (COARSE_DELAY_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DATA_CTL_N (DATA_CTL_N_BINARY),
.DATA_RD_CYCLES (DATA_RD_CYCLES_BINARY),
.EN_OSERDES_RST (EN_OSERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.OCLKDELAY_INV (OCLKDELAY_INV_BINARY),
.OCLK_DELAY (OCLK_DELAY_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PHASER_OUT_EN (PHASER_OUT_EN_BINARY),
.STG1_BYPASS (STG1_BYPASS_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_OPT (TEST_OPT_BINARY),
.COARSEOVERFLOW (delay_COARSEOVERFLOW),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.CTSBUS (delay_CTSBUS),
.DQSBUS (delay_DQSBUS),
.DTSBUS (delay_DTSBUS),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.OCLK (delay_OCLK),
.OCLKDELAYED (delay_OCLKDELAYED),
.OCLKDIV (delay_OCLKDIV),
.OSERDESRST (delay_OSERDESRST),
.RDENABLE (delay_RDENABLE),
.SCANOUT (delay_SCANOUT),
.TESTOUT (delay_TESTOUT),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COARSEENABLE (delay_COARSEENABLE),
.COARSEINC (delay_COARSEINC),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RST (delay_RST ^ IS_RST_INVERTED_BIN),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELFINEOCLKDELAY (delay_SELFINEOCLKDELAY),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge FREQREFCLK, 0:0:0, notifier);
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE);
$setuphold (posedge SYSCLK, negedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE);
$setuphold (posedge SYSCLK, posedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge EDGEADV, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_EDGEADV);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
( MEMREFCLK *> OCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10);
( MEMREFCLK *> OCLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> OSERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OSERDESRST) = (10:10:10, 10:10:10);
( SYSCLK *> COARSEOVERFLOW) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_OUT
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHASER_OUT_PHY.v 0000664 0000000 0000000 00000045027 12327044266 0023663 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan PHASER OUT
// /__/ /\ Filename : PHASER_OUT_PHY.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 12JUL2010 enable secureip
// 14JUL2010 Hook up GSR
// 26AUG2010 rtl, yaml update
// 24SEP2010 rtl, yaml update
// 29SEP2010 add width checks
// 13OCT2010 rtl, yaml update
// 26OCT2010 rtl update
// delay yaml update
// 02NOV2010 yaml update, correct tieoffs
// 05NOV2010 secureip parameter name update
// 11NOV2010 582473 multiple drivers on delay_MEMREFCLK
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC, STG1_BYPASS
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 19MAY2011 611139 remove period, setup/hold checks on MEM/PHASEREFCLK, SYNCIN
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yml update, remove SIM_SPEEDUP make default
// 02SEP2011 623558 dly.yml update
// 15FEB2012 646230 yml update, add param PO
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_OUT_PHY (
COARSEOVERFLOW,
COUNTERREADVAL,
CTSBUS,
DQSBUS,
DTSBUS,
FINEOVERFLOW,
OCLK,
OCLKDELAYED,
OCLKDIV,
OSERDESRST,
RDENABLE,
BURSTPENDINGPHY,
COARSEENABLE,
COARSEINC,
COUNTERLOADEN,
COUNTERLOADVAL,
COUNTERREADEN,
ENCALIBPHY,
FINEENABLE,
FINEINC,
FREQREFCLK,
MEMREFCLK,
PHASEREFCLK,
RST,
SELFINEOCLKDELAY,
SYNCIN,
SYSCLK
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer CLKOUT_DIV = 4;
parameter COARSE_BYPASS = "FALSE";
parameter integer COARSE_DELAY = 0;
parameter DATA_CTL_N = "FALSE";
parameter DATA_RD_CYCLES = "FALSE";
parameter integer FINE_DELAY = 0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
parameter real MEMREFCLK_PERIOD = 0.000;
parameter OCLKDELAY_INV = "FALSE";
parameter integer OCLK_DELAY = 0;
parameter OUTPUT_CLK_SRC = "PHASE_REF";
parameter real PHASEREFCLK_PERIOD = 0.000;
parameter [2:0] PO = 3'b000;
parameter real REFCLK_PERIOD = 0.000;
parameter SYNC_IN_DIV_RST = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_OUT_PHY";
output COARSEOVERFLOW;
output FINEOVERFLOW;
output OCLK;
output OCLKDELAYED;
output OCLKDIV;
output OSERDESRST;
output RDENABLE;
output [1:0] CTSBUS;
output [1:0] DQSBUS;
output [1:0] DTSBUS;
output [8:0] COUNTERREADVAL;
input BURSTPENDINGPHY;
input COARSEENABLE;
input COARSEINC;
input COUNTERLOADEN;
input COUNTERREADEN;
input FINEENABLE;
input FINEINC;
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
input RST;
input SELFINEOCLKDELAY;
input SYNCIN;
input SYSCLK;
input [1:0] ENCALIBPHY;
input [8:0] COUNTERLOADVAL;
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
reg [0:0] COARSE_BYPASS_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DATA_CTL_N_BINARY;
reg [0:0] DATA_RD_CYCLES_BINARY;
reg [0:0] EN_OSERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] OCLKDELAY_INV_BINARY;
reg [0:0] PHASER_OUT_EN_BINARY;
reg [0:0] STG1_BYPASS_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [10:0] TEST_OPT_BINARY;
reg [1:0] OUTPUT_CLK_SRC_BINARY;
reg [2:0] PO_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [5:0] COARSE_DELAY_BINARY;
reg [5:0] FINE_DELAY_BINARY;
reg [5:0] OCLK_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
$finish;
end
endcase
case (COARSE_BYPASS)
"FALSE" : COARSE_BYPASS_BINARY <= 1'b0;
"TRUE" : COARSE_BYPASS_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute COARSE_BYPASS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, COARSE_BYPASS);
$finish;
end
endcase
CTL_MODE_BINARY <= 1'b1; // model alert
case (DATA_CTL_N)
"FALSE" : DATA_CTL_N_BINARY <= 1'b0;
"TRUE" : DATA_CTL_N_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_CTL_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_N);
$finish;
end
endcase
case (DATA_RD_CYCLES)
"FALSE" : DATA_RD_CYCLES_BINARY <= 1'b0;
"TRUE" : DATA_RD_CYCLES_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_RD_CYCLES on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_RD_CYCLES);
$finish;
end
endcase
EN_OSERDES_RST_BINARY <= 1'b0;
EN_TEST_RING_BINARY <= 1'b0;
case (OCLKDELAY_INV)
"FALSE" : OCLKDELAY_INV_BINARY <= 1'b0;
"TRUE" : OCLKDELAY_INV_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute OCLKDELAY_INV on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OCLKDELAY_INV);
$finish;
end
endcase
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b00;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b11;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b01;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_PHASE_REF, DELAYED_REF or FREQ_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
$finish;
end
endcase
PHASER_OUT_EN_BINARY <= 1'b1;
if (OUTPUT_CLK_SRC == "DELAYED_PHASE_REF")
STG1_BYPASS_BINARY <= 1'b0;
else
STG1_BYPASS_BINARY <= 1'b1;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
$finish;
end
endcase
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
if ((COARSE_DELAY >= 0) && (COARSE_DELAY <= 63))
COARSE_DELAY_BINARY <= COARSE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute COARSE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, COARSE_DELAY);
$finish;
end
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
$finish;
end
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
$finish;
end
if ((OCLK_DELAY >= 0) && (OCLK_DELAY <= 63))
OCLK_DELAY_BINARY <= OCLK_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute OCLK_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, OCLK_DELAY);
$finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater then 0.000 but less than or equal to 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
$finish;
end
if ((PO >= 3'b000) && (PO <= 3'b111))
PO_BINARY <= PO;
else begin
$display("Attribute Syntax Error : The Attribute PO on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, PO);
$finish;
end
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %1.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
$finish;
end
TEST_OPT_BINARY <= {2'b0,PO,6'b0};
end
wire [1:0] delay_CTSBUS;
wire [1:0] delay_DQSBUS;
wire [1:0] delay_DTSBUS;
wire [3:0] delay_TESTOUT;
wire [8:0] delay_COUNTERREADVAL;
wire delay_COARSEOVERFLOW;
wire delay_FINEOVERFLOW;
wire delay_OCLK;
wire delay_OCLKDELAYED;
wire delay_OCLKDIV;
wire delay_OSERDESRST;
wire delay_RDENABLE;
wire delay_SCANOUT;
wire [15:0] delay_TESTIN = 16'hffff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY;
wire [8:0] delay_COUNTERLOADVAL;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY;
wire delay_COARSEENABLE;
wire delay_COARSEINC;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST = 1'b0;
wire delay_EDGEADV = 1'b0;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELFINEOCLKDELAY;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) OCLKDELAYED = delay_OCLKDELAYED;
assign #(OUTCLK_DELAY) OCLKDIV = delay_OCLKDIV;
assign #(OUTCLK_DELAY) OCLK = delay_OCLK;
assign #(out_delay) COARSEOVERFLOW = delay_COARSEOVERFLOW;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) CTSBUS = delay_CTSBUS;
assign #(out_delay) DQSBUS = delay_DQSBUS;
assign #(out_delay) DTSBUS = delay_DTSBUS;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) OSERDESRST = delay_OSERDESRST;
assign #(out_delay) RDENABLE = delay_RDENABLE;
assign #(INCLK_DELAY) delay_FREQREFCLK = FREQREFCLK;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
`endif
assign #(in_delay) delay_BURSTPENDINGPHY = BURSTPENDINGPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_COARSEENABLE = COARSEENABLE;
assign #(in_delay) delay_COARSEINC = COARSEINC;
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
`endif
assign #(in_delay) delay_ENCALIBPHY = ENCALIBPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
assign #(in_delay) delay_RST = RST;
assign #(in_delay) delay_SELFINEOCLKDELAY = SELFINEOCLKDELAY;
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_OUT #(
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_OUT_INST (
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.COARSE_BYPASS (COARSE_BYPASS_BINARY),
.COARSE_DELAY (COARSE_DELAY_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DATA_CTL_N (DATA_CTL_N_BINARY),
.DATA_RD_CYCLES (DATA_RD_CYCLES_BINARY),
.EN_OSERDES_RST (EN_OSERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.OCLKDELAY_INV (OCLKDELAY_INV_BINARY),
.OCLK_DELAY (OCLK_DELAY_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PHASER_OUT_EN (PHASER_OUT_EN_BINARY),
.STG1_BYPASS (STG1_BYPASS_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_OPT (TEST_OPT_BINARY),
.COARSEOVERFLOW (delay_COARSEOVERFLOW),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.CTSBUS (delay_CTSBUS),
.DQSBUS (delay_DQSBUS),
.DTSBUS (delay_DTSBUS),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.OCLK (delay_OCLK),
.OCLKDELAYED (delay_OCLKDELAYED),
.OCLKDIV (delay_OCLKDIV),
.OSERDESRST (delay_OSERDESRST),
.RDENABLE (delay_RDENABLE),
.SCANOUT (delay_SCANOUT),
.TESTOUT (delay_TESTOUT),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COARSEENABLE (delay_COARSEENABLE),
.COARSEINC (delay_COARSEINC),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RST (delay_RST ^ IS_RST_INVERTED_BIN),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELFINEOCLKDELAY (delay_SELFINEOCLKDELAY),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge FREQREFCLK, 0:0:0, notifier);
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE);
$setuphold (posedge SYSCLK, negedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge COARSEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEENABLE);
$setuphold (posedge SYSCLK, posedge COARSEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COARSEINC);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
( MEMREFCLK *> CTSBUS) = (10:10:10, 10:10:10);
( MEMREFCLK *> DQSBUS) = (10:10:10, 10:10:10);
( MEMREFCLK *> DTSBUS) = (10:10:10, 10:10:10);
( MEMREFCLK *> OCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10);
( MEMREFCLK *> OCLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> OSERDESRST) = (10:10:10, 10:10:10);
( MEMREFCLK *> RDENABLE) = (10:10:10, 10:10:10);
( PHASEREFCLK *> CTSBUS) = (10:10:10, 10:10:10);
( PHASEREFCLK *> DQSBUS) = (10:10:10, 10:10:10);
( PHASEREFCLK *> DTSBUS) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLKDELAYED) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OCLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> OSERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> RDENABLE) = (10:10:10, 10:10:10);
( SYSCLK *> COARSEOVERFLOW) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_OUT_PHY
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHASER_REF.v 0000664 0000000 0000000 00000013351 12327044266 0023103 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan PHASER REF
// /__/ /\ Filename : PHASER_REF.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 23APR2010 Initial UNI/UNP/SIM from yml
// 02JUL2010 add functionality
// 29SEP2010 update functionality based on rtl
// add width checks
// 28OCT2010 CR580289 ref_clock_input_freq_MHz_min/max < vs <=
// 09NOV2010 CR581863 blocking statements, clock counts to lock.
// 11NOV2010 CR582599 warning in place of LOCK
// 01DEC2010 clean up display of real numbers
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP make default
// 16APR2012 655365 else missing from delay_LOCKED always block
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_REF (
LOCKED,
CLKIN,
PWRDWN,
RST
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam INCLK_DELAY = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam INCLK_DELAY = 0;
localparam out_delay = 10;
`endif
localparam MODULE_NAME = "PHASER_REF";
localparam real REF_CLK_JITTER_MAX = 100.000;
output LOCKED;
input CLKIN;
input PWRDWN;
input RST;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire delay_CLKIN;
wire delay_PWRDWN;
wire delay_RST;
wire delay_GSR;
reg delay_LOCKED = 1'b1;
real ref_clock_input_period = 11.0;
real ref_clock_input_freq_MHz = 1.68;
real time_last_rising_edge = 1.0;
real last_ref_clock_input_period = 13.0;
real last_ref_clock_input_freq_MHz = 1.69;
integer same_period_count = 0;
integer different_period_count = 0;
integer same_period_count_last = 0;
integer count_clks = 0;
real ref_clock_input_freq_MHz_min = 400.000; // valid min freq in MHz
real ref_clock_input_freq_MHz_max = 1066.000; // valid max freq in MHz
reg IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
assign #(out_delay) LOCKED = delay_LOCKED;
assign #(INCLK_DELAY) delay_CLKIN = CLKIN;
assign #(in_delay) delay_PWRDWN = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign #(in_delay) delay_RST = RST ^ IS_RST_INVERTED_BIN;
assign delay_GSR = GSR;
always @(posedge delay_CLKIN)
begin
last_ref_clock_input_period <= ref_clock_input_period;
last_ref_clock_input_freq_MHz <= ref_clock_input_freq_MHz;
same_period_count_last <= same_period_count;
ref_clock_input_period <= $time - time_last_rising_edge;
ref_clock_input_freq_MHz <= 1e6/($time - time_last_rising_edge);
time_last_rising_edge <= $time/1.0;
if ( (delay_RST==0) && (delay_PWRDWN ==0) &&
(ref_clock_input_period - last_ref_clock_input_period <= REF_CLK_JITTER_MAX) &&
(last_ref_clock_input_period - ref_clock_input_period <= REF_CLK_JITTER_MAX) )
begin
if (same_period_count < 6) same_period_count <= same_period_count + 1;
if ( same_period_count >= 3 && same_period_count != same_period_count_last && different_period_count != 0)
begin
different_period_count <= 0; //reset different_period_count
end
end
else // detecting different clock-preiod
begin
different_period_count = different_period_count + 1;
if ( different_period_count >= 1 && same_period_count != 0 )
begin
same_period_count <= 0 ; //reset same_period_count
end
end
end
always @(posedge delay_CLKIN or posedge delay_RST or posedge delay_PWRDWN) begin
if ( delay_RST||delay_PWRDWN)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ((same_period_count >= 1) && (count_clks < 6))
begin
count_clks <= count_clks + 1;
end
else if (different_period_count >= 1)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ( (count_clks >= 5) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 >= ref_clock_input_freq_MHz_min ) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 <= ref_clock_input_freq_MHz_max ) )
begin
delay_LOCKED <= 1'b1;
end
end
always @(posedge delay_CLKIN)
if ( (count_clks == 5) &&
( ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 < ref_clock_input_freq_MHz_min) ||
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 > ref_clock_input_freq_MHz_max) ) ) begin
$display("Warning: Invalid average CLKIN frequency detected = %4.3f MHz", (ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000);
$display(" on %s instance %m at time %t ps.", MODULE_NAME, $time);
$display(" The valid CLKIN frequency range is:");
$display(" Minimum = %4.3f MHz", ref_clock_input_freq_MHz_min );
$display(" Maximum = %4.3f MHz", ref_clock_input_freq_MHz_max );
end
`ifdef XIL_TIMING
specify
$period (negedge CLKIN, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_REF
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PHY_CONTROL.v 0000664 0000000 0000000 00000055300 12327044266 0023265 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan Phaser Phy Control
// /__/ /\ Filename : PHY_CONTROL.v
// \ \ / \
// \__\/\__ \
//
// Date: Comment:
// 23APR2010 Initial UNI/UNP/SIM version from yml
// 10JUN2010 yml update
// 02JUL2010 enable secureip
// 20AUG2010 yml, rtl update
// 28SEP2010 yml, rtl update
// 29SEP2010 yml update
// 28OCT2010 rtl update
// 05NOV2010 update defaults
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 14FEB2011 593832 yml, rtl update
// 16MAR2011 601917 dly.yml update
// 14APR2011 606310 yml update
// 15AUG2011 621681 remove SIM_SPEEDUP, make default
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHY_CONTROL (
AUXOUTPUT,
INBURSTPENDING,
INRANKA,
INRANKB,
INRANKC,
INRANKD,
OUTBURSTPENDING,
PCENABLECALIB,
PHYCTLALMOSTFULL,
PHYCTLEMPTY,
PHYCTLFULL,
PHYCTLREADY,
MEMREFCLK,
PHYCLK,
PHYCTLMSTREMPTY,
PHYCTLWD,
PHYCTLWRENABLE,
PLLLOCK,
READCALIBENABLE,
REFDLLLOCK,
RESET,
SYNCIN,
WRITECALIBENABLE
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer AO_TOGGLE = 0;
parameter [3:0] AO_WRLVL_EN = 4'b0000;
parameter BURST_MODE = "FALSE";
parameter integer CLK_RATIO = 1;
parameter integer CMD_OFFSET = 0;
parameter integer CO_DURATION = 0;
parameter DATA_CTL_A_N = "FALSE";
parameter DATA_CTL_B_N = "FALSE";
parameter DATA_CTL_C_N = "FALSE";
parameter DATA_CTL_D_N = "FALSE";
parameter DISABLE_SEQ_MATCH = "TRUE";
parameter integer DI_DURATION = 0;
parameter integer DO_DURATION = 0;
parameter integer EVENTS_DELAY = 63;
parameter integer FOUR_WINDOW_CLOCKS = 63;
parameter MULTI_REGION = "FALSE";
parameter PHY_COUNT_ENABLE = "FALSE";
parameter integer RD_CMD_OFFSET_0 = 0;
parameter integer RD_CMD_OFFSET_1 = 00;
parameter integer RD_CMD_OFFSET_2 = 0;
parameter integer RD_CMD_OFFSET_3 = 0;
parameter integer RD_DURATION_0 = 0;
parameter integer RD_DURATION_1 = 0;
parameter integer RD_DURATION_2 = 0;
parameter integer RD_DURATION_3 = 0;
parameter SYNC_MODE = "FALSE";
parameter integer WR_CMD_OFFSET_0 = 0;
parameter integer WR_CMD_OFFSET_1 = 0;
parameter integer WR_CMD_OFFSET_2 = 0;
parameter integer WR_CMD_OFFSET_3 = 0;
parameter integer WR_DURATION_0 = 0;
parameter integer WR_DURATION_1 = 0;
parameter integer WR_DURATION_2 = 0;
parameter integer WR_DURATION_3 = 0;
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 100;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "PHY_CONTROL";
output PHYCTLALMOSTFULL;
output PHYCTLEMPTY;
output PHYCTLFULL;
output PHYCTLREADY;
output [1:0] INRANKA;
output [1:0] INRANKB;
output [1:0] INRANKC;
output [1:0] INRANKD;
output [1:0] PCENABLECALIB;
output [3:0] AUXOUTPUT;
output [3:0] INBURSTPENDING;
output [3:0] OUTBURSTPENDING;
input MEMREFCLK;
input PHYCLK;
input PHYCTLMSTREMPTY;
input PHYCTLWRENABLE;
input PLLLOCK;
input READCALIBENABLE;
input REFDLLLOCK;
input RESET;
input SYNCIN;
input WRITECALIBENABLE;
input [31:0] PHYCTLWD;
reg [0:0] BURST_MODE_BINARY;
reg [0:0] DATA_CTL_A_N_BINARY;
reg [0:0] DATA_CTL_B_N_BINARY;
reg [0:0] DATA_CTL_C_N_BINARY;
reg [0:0] DATA_CTL_D_N_BINARY;
reg [0:0] DISABLE_SEQ_MATCH_BINARY;
reg [0:0] MULTI_REGION_BINARY;
reg [0:0] PHY_COUNT_ENABLE_BINARY;
reg [0:0] SPARE_BINARY;
reg [0:0] SYNC_MODE_BINARY;
reg [2:0] CLK_RATIO_BINARY;
reg [2:0] CO_DURATION_BINARY;
reg [2:0] DI_DURATION_BINARY;
reg [2:0] DO_DURATION_BINARY;
reg [3:0] AO_TOGGLE_BINARY;
reg [3:0] AO_WRLVL_EN_BINARY;
reg [5:0] CMD_OFFSET_BINARY;
reg [5:0] EVENTS_DELAY_BINARY;
reg [5:0] FOUR_WINDOW_CLOCKS_BINARY;
reg [5:0] RD_CMD_OFFSET_0_BINARY;
reg [5:0] RD_CMD_OFFSET_1_BINARY;
reg [5:0] RD_CMD_OFFSET_2_BINARY;
reg [5:0] RD_CMD_OFFSET_3_BINARY;
reg [5:0] RD_DURATION_0_BINARY;
reg [5:0] RD_DURATION_1_BINARY;
reg [5:0] RD_DURATION_2_BINARY;
reg [5:0] RD_DURATION_3_BINARY;
reg [5:0] WR_CMD_OFFSET_0_BINARY;
reg [5:0] WR_CMD_OFFSET_1_BINARY;
reg [5:0] WR_CMD_OFFSET_2_BINARY;
reg [5:0] WR_CMD_OFFSET_3_BINARY;
reg [5:0] WR_DURATION_0_BINARY;
reg [5:0] WR_DURATION_1_BINARY;
reg [5:0] WR_DURATION_2_BINARY;
reg [5:0] WR_DURATION_3_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (BURST_MODE)
"FALSE" : BURST_MODE_BINARY <= 1'b0;
"TRUE" : BURST_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute BURST_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BURST_MODE);
$finish;
end
endcase
case (CLK_RATIO)
1 : CLK_RATIO_BINARY <= 3'b000;
2 : CLK_RATIO_BINARY <= 3'b001;
4 : CLK_RATIO_BINARY <= 3'b010;
8 : CLK_RATIO_BINARY <= 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_RATIO on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4 or 8.", MODULE_NAME, CLK_RATIO, 1);
$finish;
end
endcase
case (DATA_CTL_A_N)
"FALSE" : DATA_CTL_A_N_BINARY <= 1'b0;
"TRUE" : DATA_CTL_A_N_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_CTL_A_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_A_N);
$finish;
end
endcase
case (DATA_CTL_B_N)
"FALSE" : DATA_CTL_B_N_BINARY <= 1'b0;
"TRUE" : DATA_CTL_B_N_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_CTL_B_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_B_N);
$finish;
end
endcase
case (DATA_CTL_C_N)
"FALSE" : DATA_CTL_C_N_BINARY <= 1'b0;
"TRUE" : DATA_CTL_C_N_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_CTL_C_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_C_N);
$finish;
end
endcase
case (DATA_CTL_D_N)
"FALSE" : DATA_CTL_D_N_BINARY <= 1'b0;
"TRUE" : DATA_CTL_D_N_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DATA_CTL_D_N on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DATA_CTL_D_N);
$finish;
end
endcase
case (DISABLE_SEQ_MATCH)
"TRUE" : DISABLE_SEQ_MATCH_BINARY <= 1'b1;
"FALSE" : DISABLE_SEQ_MATCH_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_SEQ_MATCH on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DISABLE_SEQ_MATCH);
$finish;
end
endcase
case (MULTI_REGION)
"FALSE" : MULTI_REGION_BINARY <= 1'b0;
"TRUE" : MULTI_REGION_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MULTI_REGION on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, MULTI_REGION);
$finish;
end
endcase
case (PHY_COUNT_ENABLE)
"FALSE" : PHY_COUNT_ENABLE_BINARY <= 1'b0;
"TRUE" : PHY_COUNT_ENABLE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PHY_COUNT_ENABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, PHY_COUNT_ENABLE);
$finish;
end
endcase
SPARE_BINARY <= 1'b0;
case (SYNC_MODE)
"TRUE" : SYNC_MODE_BINARY <= 1'b1;
"FALSE" : SYNC_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_MODE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SYNC_MODE);
$finish;
end
endcase
if ((AO_TOGGLE >= 0) && (AO_TOGGLE <= 15))
AO_TOGGLE_BINARY <= AO_TOGGLE;
else begin
$display("Attribute Syntax Error : The Attribute AO_TOGGLE on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, AO_TOGGLE);
$finish;
end
if ((AO_WRLVL_EN >= 4'b0000) && (AO_WRLVL_EN <= 4'b1111))
AO_WRLVL_EN_BINARY <= AO_WRLVL_EN;
else begin
$display("Attribute Syntax Error : The Attribute AO_WRLVL_EN on %s instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", MODULE_NAME, AO_WRLVL_EN);
$finish;
end
if ((CMD_OFFSET >= 0) && (CMD_OFFSET <= 63))
CMD_OFFSET_BINARY <= CMD_OFFSET;
else begin
$display("Attribute Syntax Error : The Attribute CMD_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, CMD_OFFSET);
$finish;
end
if ((CO_DURATION >= 0) && (CO_DURATION <= 7))
CO_DURATION_BINARY <= CO_DURATION;
else begin
$display("Attribute Syntax Error : The Attribute CO_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, CO_DURATION);
$finish;
end
if ((DI_DURATION >= 0) && (DI_DURATION <= 7))
DI_DURATION_BINARY <= DI_DURATION;
else begin
$display("Attribute Syntax Error : The Attribute DI_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DI_DURATION);
$finish;
end
if ((DO_DURATION >= 0) && (DO_DURATION <= 7))
DO_DURATION_BINARY <= DO_DURATION;
else begin
$display("Attribute Syntax Error : The Attribute DO_DURATION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DO_DURATION);
$finish;
end
if ((EVENTS_DELAY >= 0) && (EVENTS_DELAY <= 63))
EVENTS_DELAY_BINARY <= EVENTS_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute EVENTS_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, EVENTS_DELAY);
$finish;
end
if ((FOUR_WINDOW_CLOCKS >= 0) && (FOUR_WINDOW_CLOCKS <= 63))
FOUR_WINDOW_CLOCKS_BINARY <= FOUR_WINDOW_CLOCKS;
else begin
$display("Attribute Syntax Error : The Attribute FOUR_WINDOW_CLOCKS on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FOUR_WINDOW_CLOCKS);
$finish;
end
if ((RD_CMD_OFFSET_0 >= 0) && (RD_CMD_OFFSET_0 <= 63))
RD_CMD_OFFSET_0_BINARY <= RD_CMD_OFFSET_0;
else begin
$display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_0);
$finish;
end
if ((RD_CMD_OFFSET_1 >= 0) && (RD_CMD_OFFSET_1 <= 63))
RD_CMD_OFFSET_1_BINARY <= RD_CMD_OFFSET_1;
else begin
$display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_1);
$finish;
end
if ((RD_CMD_OFFSET_2 >= 0) && (RD_CMD_OFFSET_2 <= 63))
RD_CMD_OFFSET_2_BINARY <= RD_CMD_OFFSET_2;
else begin
$display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_2);
$finish;
end
if ((RD_CMD_OFFSET_3 >= 0) && (RD_CMD_OFFSET_3 <= 63))
RD_CMD_OFFSET_3_BINARY <= RD_CMD_OFFSET_3;
else begin
$display("Attribute Syntax Error : The Attribute RD_CMD_OFFSET_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_CMD_OFFSET_3);
$finish;
end
if ((RD_DURATION_0 >= 0) && (RD_DURATION_0 <= 63))
RD_DURATION_0_BINARY <= RD_DURATION_0;
else begin
$display("Attribute Syntax Error : The Attribute RD_DURATION_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_0);
$finish;
end
if ((RD_DURATION_1 >= 0) && (RD_DURATION_1 <= 63))
RD_DURATION_1_BINARY <= RD_DURATION_1;
else begin
$display("Attribute Syntax Error : The Attribute RD_DURATION_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_1);
$finish;
end
if ((RD_DURATION_2 >= 0) && (RD_DURATION_2 <= 63))
RD_DURATION_2_BINARY <= RD_DURATION_2;
else begin
$display("Attribute Syntax Error : The Attribute RD_DURATION_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_2);
$finish;
end
if ((RD_DURATION_3 >= 0) && (RD_DURATION_3 <= 63))
RD_DURATION_3_BINARY <= RD_DURATION_3;
else begin
$display("Attribute Syntax Error : The Attribute RD_DURATION_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, RD_DURATION_3);
$finish;
end
if ((WR_CMD_OFFSET_0 >= 0) && (WR_CMD_OFFSET_0 <= 63))
WR_CMD_OFFSET_0_BINARY <= WR_CMD_OFFSET_0;
else begin
$display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_0);
$finish;
end
if ((WR_CMD_OFFSET_1 >= 0) && (WR_CMD_OFFSET_1 <= 63))
WR_CMD_OFFSET_1_BINARY <= WR_CMD_OFFSET_1;
else begin
$display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_1);
$finish;
end
if ((WR_CMD_OFFSET_2 >= 0) && (WR_CMD_OFFSET_2 <= 63))
WR_CMD_OFFSET_2_BINARY <= WR_CMD_OFFSET_2;
else begin
$display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_2);
$finish;
end
if ((WR_CMD_OFFSET_3 >= 0) && (WR_CMD_OFFSET_3 <= 63))
WR_CMD_OFFSET_3_BINARY <= WR_CMD_OFFSET_3;
else begin
$display("Attribute Syntax Error : The Attribute WR_CMD_OFFSET_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_CMD_OFFSET_3);
$finish;
end
if ((WR_DURATION_0 >= 0) && (WR_DURATION_0 <= 63))
WR_DURATION_0_BINARY <= WR_DURATION_0;
else begin
$display("Attribute Syntax Error : The Attribute WR_DURATION_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_0);
$finish;
end
if ((WR_DURATION_1 >= 0) && (WR_DURATION_1 <= 63))
WR_DURATION_1_BINARY <= WR_DURATION_1;
else begin
$display("Attribute Syntax Error : The Attribute WR_DURATION_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_1);
$finish;
end
if ((WR_DURATION_2 >= 0) && (WR_DURATION_2 <= 63))
WR_DURATION_2_BINARY <= WR_DURATION_2;
else begin
$display("Attribute Syntax Error : The Attribute WR_DURATION_2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_2);
$finish;
end
if ((WR_DURATION_3 >= 0) && (WR_DURATION_3 <= 63))
WR_DURATION_3_BINARY <= WR_DURATION_3;
else begin
$display("Attribute Syntax Error : The Attribute WR_DURATION_3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, WR_DURATION_3);
$finish;
end
end
wire [15:0] delay_TESTOUTPUT;
wire [1:0] delay_INRANKA;
wire [1:0] delay_INRANKB;
wire [1:0] delay_INRANKC;
wire [1:0] delay_INRANKD;
wire [1:0] delay_PCENABLECALIB;
wire [3:0] delay_AUXOUTPUT;
wire [3:0] delay_INBURSTPENDING;
wire [3:0] delay_OUTBURSTPENDING;
wire delay_PHYCTLALMOSTFULL;
wire delay_PHYCTLEMPTY;
wire delay_PHYCTLFULL;
wire delay_PHYCTLREADY;
wire [15:0] delay_TESTINPUT = 16'hffff;
wire [2:0] delay_TESTSELECT = 3'b111;
wire [31:0] delay_PHYCTLWD;
wire delay_MEMREFCLK;
wire delay_PHYCLK;
wire delay_PHYCTLMSTREMPTY;
wire delay_PHYCTLWRENABLE;
wire delay_PLLLOCK;
wire delay_READCALIBENABLE;
wire delay_REFDLLLOCK;
wire delay_RESET;
wire delay_SCANENABLEN = 1'b1;
wire delay_SYNCIN;
wire delay_WRITECALIBENABLE;
wire delay_GSR;
assign #(out_delay) AUXOUTPUT = delay_AUXOUTPUT;
assign #(out_delay) INBURSTPENDING = delay_INBURSTPENDING;
assign #(out_delay) INRANKA = delay_INRANKA;
assign #(out_delay) INRANKB = delay_INRANKB;
assign #(out_delay) INRANKC = delay_INRANKC;
assign #(out_delay) INRANKD = delay_INRANKD;
assign #(out_delay) OUTBURSTPENDING = delay_OUTBURSTPENDING;
assign #(out_delay) PCENABLECALIB = delay_PCENABLECALIB;
assign #(out_delay) PHYCTLALMOSTFULL = delay_PHYCTLALMOSTFULL;
assign #(out_delay) PHYCTLEMPTY = delay_PHYCTLEMPTY;
assign #(out_delay) PHYCTLFULL = delay_PHYCTLFULL;
assign #(out_delay) PHYCTLREADY = delay_PHYCTLREADY;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_MEMREFCLK = MEMREFCLK;
assign #(INCLK_DELAY) delay_PHYCLK = PHYCLK;
assign #(in_delay) delay_PHYCTLMSTREMPTY = PHYCTLMSTREMPTY;
assign #(in_delay) delay_PHYCTLWD = PHYCTLWD;
assign #(in_delay) delay_PHYCTLWRENABLE = PHYCTLWRENABLE;
`endif
assign #(in_delay) delay_PLLLOCK = PLLLOCK;
assign #(in_delay) delay_READCALIBENABLE = READCALIBENABLE;
assign #(in_delay) delay_REFDLLLOCK = REFDLLLOCK;
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_SYNCIN = SYNCIN;
`endif
assign #(in_delay) delay_WRITECALIBENABLE = WRITECALIBENABLE;
assign delay_GSR = GSR;
SIP_PHY_CONTROL PHY_CONTROL_INST (
.AO_TOGGLE (AO_TOGGLE_BINARY),
.AO_WRLVL_EN (AO_WRLVL_EN_BINARY),
.BURST_MODE (BURST_MODE_BINARY),
.CLK_RATIO (CLK_RATIO_BINARY),
.CMD_OFFSET (CMD_OFFSET_BINARY),
.CO_DURATION (CO_DURATION_BINARY),
.DATA_CTL_A_N (DATA_CTL_A_N_BINARY),
.DATA_CTL_B_N (DATA_CTL_B_N_BINARY),
.DATA_CTL_C_N (DATA_CTL_C_N_BINARY),
.DATA_CTL_D_N (DATA_CTL_D_N_BINARY),
.DISABLE_SEQ_MATCH (DISABLE_SEQ_MATCH_BINARY),
.DI_DURATION (DI_DURATION_BINARY),
.DO_DURATION (DO_DURATION_BINARY),
.EVENTS_DELAY (EVENTS_DELAY_BINARY),
.FOUR_WINDOW_CLOCKS (FOUR_WINDOW_CLOCKS_BINARY),
.MULTI_REGION (MULTI_REGION_BINARY),
.PHY_COUNT_ENABLE (PHY_COUNT_ENABLE_BINARY),
.RD_CMD_OFFSET_0 (RD_CMD_OFFSET_0_BINARY),
.RD_CMD_OFFSET_1 (RD_CMD_OFFSET_1_BINARY),
.RD_CMD_OFFSET_2 (RD_CMD_OFFSET_2_BINARY),
.RD_CMD_OFFSET_3 (RD_CMD_OFFSET_3_BINARY),
.RD_DURATION_0 (RD_DURATION_0_BINARY),
.RD_DURATION_1 (RD_DURATION_1_BINARY),
.RD_DURATION_2 (RD_DURATION_2_BINARY),
.RD_DURATION_3 (RD_DURATION_3_BINARY),
.SPARE (SPARE_BINARY),
.SYNC_MODE (SYNC_MODE_BINARY),
.WR_CMD_OFFSET_0 (WR_CMD_OFFSET_0_BINARY),
.WR_CMD_OFFSET_1 (WR_CMD_OFFSET_1_BINARY),
.WR_CMD_OFFSET_2 (WR_CMD_OFFSET_2_BINARY),
.WR_CMD_OFFSET_3 (WR_CMD_OFFSET_3_BINARY),
.WR_DURATION_0 (WR_DURATION_0_BINARY),
.WR_DURATION_1 (WR_DURATION_1_BINARY),
.WR_DURATION_2 (WR_DURATION_2_BINARY),
.WR_DURATION_3 (WR_DURATION_3_BINARY),
.AUXOUTPUT (delay_AUXOUTPUT),
.INBURSTPENDING (delay_INBURSTPENDING),
.INRANKA (delay_INRANKA),
.INRANKB (delay_INRANKB),
.INRANKC (delay_INRANKC),
.INRANKD (delay_INRANKD),
.OUTBURSTPENDING (delay_OUTBURSTPENDING),
.PCENABLECALIB (delay_PCENABLECALIB),
.PHYCTLALMOSTFULL (delay_PHYCTLALMOSTFULL),
.PHYCTLEMPTY (delay_PHYCTLEMPTY),
.PHYCTLFULL (delay_PHYCTLFULL),
.PHYCTLREADY (delay_PHYCTLREADY),
.TESTOUTPUT (delay_TESTOUTPUT),
.MEMREFCLK (delay_MEMREFCLK),
.PHYCLK (delay_PHYCLK),
.PHYCTLMSTREMPTY (delay_PHYCTLMSTREMPTY),
.PHYCTLWD (delay_PHYCTLWD),
.PHYCTLWRENABLE (delay_PHYCTLWRENABLE),
.PLLLOCK (delay_PLLLOCK),
.READCALIBENABLE (delay_READCALIBENABLE),
.REFDLLLOCK (delay_REFDLLLOCK),
.RESET (delay_RESET),
.SCANENABLEN (delay_SCANENABLEN),
.SYNCIN (delay_SYNCIN),
.TESTINPUT (delay_TESTINPUT),
.TESTSELECT (delay_TESTSELECT),
.WRITECALIBENABLE (delay_WRITECALIBENABLE),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge MEMREFCLK, 0:0:0, notifier);
$period (negedge PHYCLK, 0:0:0, notifier);
$period (posedge MEMREFCLK, 0:0:0, notifier);
$period (posedge PHYCLK, 0:0:0, notifier);
$setuphold (posedge MEMREFCLK, negedge PHYCTLMSTREMPTY, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_PHYCTLMSTREMPTY);
$setuphold (posedge MEMREFCLK, negedge SYNCIN, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_SYNCIN);
$setuphold (posedge MEMREFCLK, posedge PHYCTLMSTREMPTY, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_PHYCTLMSTREMPTY);
$setuphold (posedge MEMREFCLK, posedge SYNCIN, 0:0:0, 0:0:0, notifier,,, delay_MEMREFCLK, delay_SYNCIN);
$setuphold (posedge PHYCLK, negedge PHYCTLWD, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWD);
$setuphold (posedge PHYCLK, negedge PHYCTLWRENABLE, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWRENABLE);
$setuphold (posedge PHYCLK, posedge PHYCTLWD, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWD);
$setuphold (posedge PHYCLK, posedge PHYCTLWRENABLE, 0:0:0, 0:0:0, notifier,,, delay_PHYCLK, delay_PHYCTLWRENABLE);
$width (negedge MEMREFCLK, 0:0:0, 0, notifier);
$width (negedge PHYCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHYCLK, 0:0:0, 0, notifier);
$width (posedge READCALIBENABLE, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge WRITECALIBENABLE, 0:0:0, 0, notifier);
( MEMREFCLK *> AUXOUTPUT) = (10:10:10, 10:10:10);
( MEMREFCLK *> INBURSTPENDING) = (10:10:10, 10:10:10);
( MEMREFCLK *> INRANKA) = (10:10:10, 10:10:10);
( MEMREFCLK *> INRANKB) = (10:10:10, 10:10:10);
( MEMREFCLK *> INRANKC) = (10:10:10, 10:10:10);
( MEMREFCLK *> INRANKD) = (10:10:10, 10:10:10);
( MEMREFCLK *> OUTBURSTPENDING) = (10:10:10, 10:10:10);
( MEMREFCLK *> PCENABLECALIB) = (10:10:10, 10:10:10);
( MEMREFCLK *> PHYCTLEMPTY) = (10:10:10, 10:10:10);
( PHYCLK *> PHYCTLALMOSTFULL) = (10:10:10, 10:10:10);
( PHYCLK *> PHYCTLFULL) = (10:10:10, 10:10:10);
( PHYCLK *> PHYCTLREADY) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHY_CONTROL
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PLLE2_ADV.v 0000664 0000000 0000000 00000364632 12327044266 0022750 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.58)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Phase Lock Loop Clock
// /___/ /\ Filename : PLLE2_ADV.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 12/09/09 - Initial version.
// 03/24/10 - Change CLKFBOUT_MULT defaut to 5, CLKIN_PERIOD range.
// 04/28/10 - Fix CLKIN1_PERIOD check (CR557962)
// 06/03/10 - Change DIVCLK_DIVIDE range to 56 according yaml.
// 07/12/10 - Add RST to LOCKED iopath (CR567807)
// 07/28/10 - Change ref parameter values (CR569262)
// 08/06/10 - Remove CASCADE from COMPENSATION (CR571190)
// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324)
// 09/03/10 - Change to bus timing.
// 09/26/10 - Add RST to LOCKED timing path (CR567807)
// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003)
// 03/03/11 - Keep 100ps dealy only on RST to LOCKED for unisim (CR595354)
// 05/05/11 - Update cp_res table (CR609232)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/26/11 - Add DRC check for samples CLKIN period with parameter setting (CR631150)
// 02/22/12 - Modify DRC (638094).
// 03/07/12 - added vcoflag (CR 638088, CR 636493)
// 04/19/12 - 654951 - rounding issue with clk_out_para_cal
// 05/03/12 - jittery clock (CR 652401)
// 05/03/12 - incorrect period (CR 654951)
// 06/11/12 - update cp and res settings (CR 664278)
// 06/20/12 - modify reset drc (CR 643540)
// 04/04/13 - change error to warning (CR 708090)
// 04/09/13 - Added DRP monitor (CR 695630).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module PLLE2_ADV #(
`ifdef XIL_TIMING //Simprim
parameter real VCOCLK_FREQ_MAX = 2133.000,
parameter real VCOCLK_FREQ_MIN = 800.000,
parameter real CLKIN_FREQ_MAX = 1066.000,
parameter real CLKIN_FREQ_MIN = 19.000,
parameter real CLKPFD_FREQ_MAX = 550.0,
parameter real CLKPFD_FREQ_MIN = 19.0,
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
output [15:0] DO,
output DRDY,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PWRDWN,
input RST
);
`ifndef XIL_TIMING
localparam real VCOCLK_FREQ_MAX = 2133.000;
localparam real VCOCLK_FREQ_MIN = 800.000;
localparam real CLKIN_FREQ_MAX = 1066.000;
localparam real CLKIN_FREQ_MIN = 19.000;
localparam real CLKPFD_FREQ_MAX = 550.0;
localparam real CLKPFD_FREQ_MIN = 19.0;
`endif
localparam VCOCLK_FREQ_TARGET = 1200;
localparam M_MIN = 2;
localparam M_MAX = 64;
localparam D_MIN = 1;
localparam D_MAX = 56;
localparam O_MIN = 1;
localparam O_MAX = 128;
localparam O_MAX_HT_LT = 64;
localparam REF_CLK_JITTER_MAX = 1000;
localparam REF_CLK_JITTER_SCALE = 0.1;
localparam MAX_FEEDBACK_DELAY = 10.0;
localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
localparam PLL_LOCK_TIME = 7;
localparam ps_max = 55;
localparam OSC_P2 = 250;
localparam SIM_DEVICE = "E2";
localparam CLKFBOUT_USE_FINE_PS = "FALSE";
localparam CLKOUT0_USE_FINE_PS = "FALSE";
localparam CLKOUT1_USE_FINE_PS = "FALSE";
localparam CLKOUT2_USE_FINE_PS = "FALSE";
localparam CLKOUT3_USE_FINE_PS = "FALSE";
localparam CLKOUT4_CASCADE = "FALSE";
localparam CLKOUT4_USE_FINE_PS = "FALSE";
localparam CLKOUT5_USE_FINE_PS = "FALSE";
localparam CLKOUT6_USE_FINE_PS = "FALSE";
localparam integer CLKOUT6_DIVIDE = 1;
localparam real CLKOUT6_DUTY_CYCLE = 0.500;
localparam real CLKOUT6_PHASE = 0.000;
tri0 GSR = glbl.GSR;
tri1 p_up;
wire glock;
integer pchk_tmp1, pchk_tmp2;
reg PSCLK = 0, PSINCDEC = 0, PSEN = 0;
integer clkfb_div_frac_int, clk0_div_frac_int, clkfb_div_fint, clk0_div_fint;
integer clkfb_div_fint_tmp1, clkfb_div_fint_odd;
integer clk0_div_fint_tmp1, clk0_div_fint_odd;
real clkfb_div_frac, clk0_div_frac;
reg clk0_frac_out, clkfbm1_frac_out;
reg clk0_nf_out, clkfbm1_nf_out;
integer clk0_frac_en;
integer clkfb_frac_en;
integer ps_in_init;
reg psdone_out, psdone_out1;
integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en;
integer clk5_fps_en, clk6_fps_en, clkfb_fps_en, fps_en;
reg clkinstopped_out;
reg clkin_hold_f = 0;
reg simd_f = 1;
reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0;
integer period_avg_stpi = 0, period_avg_stp = 0;
real tmp_stp1, tmp_stp2;
reg pd_stp_p = 0;
reg vco_stp_f = 0;
reg psen_w = 0;
reg clkinstopped_out_dly = 0;
reg clkinstopped_out1 = 0;
reg clkfbstopped_out1 = 0;
reg clkfb_stop_tmp, clkfbstopped_out, clkin_stop_tmp;
reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0;
reg rst_clkinstopped_rc = 0;
reg rst_clkinstopped_lk, rst_clkfbstopped_lk;
integer clkin_lost_cnt, clkfb_lost_cnt;
reg clkinstopped_hold = 0;
integer ps_in_ps, ps_cnt;
integer ps_in_ps_neg, ps_cnt_neg;
reg clkout_ps, clkout_ps_tmp1, clkout_ps_tmp2;
time clkout_ps_eg = 0;
time clkout_ps_peg = 0;
time clkout_ps_w = 0;
reg clkvco_ps_tmp1, clkvco_ps_tmp2;
reg clkvco_ps_tmp2_en;
integer clkout4_cascade_int;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drdy_out, drdy_out1;
reg drp_lock;
integer drp_lock_lat = 4;
integer drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [160:0] tmp_string;
reg rst_in;
reg pwron_int;
wire orig_rst_in,rst_in_o;
wire locked_out;
reg locked_out1;
reg locked_out_tmp;
wire clk0_out, clkfbm1_out;
reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out;
reg clkfb_out;
reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1;
integer clkout_en_val, clkout_en_t;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
reg clkvco_lk_osc, clkvco, clkvco_lk_tmp, clkvco_lk_tmp_en;
reg clkvco_ps_tmp2_pg;
reg clkvco_lk_dly_tmp;
reg clkvco_lk_en;
reg clkvco_lk;
reg fbclk_tmp;
reg clk_osc, clkin_p, clkfb_p;
reg clkinstopped_vco_f;
time rst_edge, rst_ht;
reg fb_delay_found, fb_delay_found_tmp;
reg clkfb_tst;
real fb_delay_max;
time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay, fbm1_comp_delay_tmp;
time dly_tmp1, tmp_ps_val2;
integer dly_tmp_int, tmp_ps_val1;
time clkin_edge, delay_edge;
real period_clkin, clkin_period_tmp;
integer clkin_period_tmp_t;
integer clkin_period [4:0];
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
integer period_vco_half_rm1, period_vco_half_rm2;
real cmpvco = 0.0;
real clkvco_pdrm;
integer period_vco_mf;
integer period_vco_tmp;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco_max, period_vco_min;
integer period_vco1, period_vco2, period_vco3, period_vco4;
integer period_vco5, period_vco6, period_vco7;
integer period_vco_target, period_vco_target_half;
integer period_fb, period_avg;
integer clk0_frac_lt, clk0_frac_ht;
integer clkfb_frac_lt, clkfb_frac_ht;
integer period_ps, period_ps_old;
reg ps_lock, ps_lock_dly;
real clkvco_freq_init_chk, clkfbm1pm_rl;
real tmp_real;
integer ik0, ik1, ik2, ik3, ik4, ib, i, j;
integer md_product, m_product, m_product2, clkin_stop_max, clkfb_stop_max;
integer mf_product, clk0f_product;
integer clkin_lost_val, clkfb_lost_val, clkin_lost_val_lk;
time pll_locked_delay, clkin_dly_t, clkfb_dly_t;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2, pll_locked_tmp2_dly;
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock;
integer clkin_jit, REF_CLK_JITTER_MAX_tmp;
wire init_trig, clkpll_r, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clk6in;
reg clkpll_tmp1, clkpll;
wire clkfbm1in, clkfbm1ps_en;
reg chk_ok;
wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en;
reg [7:0] clkout_mux, clkout_ps_mux;
reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel;
wire [2:0] clk0pm_sel1, clk5pm_sel1, clk6pm_sel1, clkfbm1pm_sel1;
reg [2:0] clk6pm_sel, clkfbm1pm_sel;
integer clk0pm_sel_int, clkfbm1pm_sel_int;
reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge, clk6_edge;
reg clkfbm1_edge, clkfbm2_edge, clkind_edge;
reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt;
reg clk6_nocnt, clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt;
reg clkfbtmp_nocnti;
reg clkind_edgei, clkind_nocnti;
reg [5:0] clk0_dly_cnt, clkout0_dly;
reg [5:0] clk1_dly_cnt, clkout1_dly;
reg [5:0] clk2_dly_cnt, clkout2_dly;
reg [5:0] clk3_dly_cnt, clkout3_dly;
reg [5:0] clk4_dly_cnt, clkout4_dly;
reg [5:0] clk5_dly_cnt, clkout5_dly;
reg [5:0] clk6_dly_cnt, clkout6_dly;
reg [6:0] clk0_ht, clk0_lt;
reg [6:0] clk1_ht, clk1_lt;
reg [6:0] clk2_ht, clk2_lt;
reg [6:0] clk3_ht, clk3_lt;
reg [6:0] clk4_ht, clk4_lt;
reg [6:0] clk5_ht, clk5_lt;
reg [6:0] clk6_ht, clk6_lt;
reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly;
reg [6:0] clkfbm1_ht, clkfbm1_lt;
reg [6:0] clkfbm2_ht, clkfbm2_lt;
reg [7:0] clkind_ht, clkind_lt;
reg [7:0] clkind_hti, clkind_lti;
reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1;
reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1;
reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1;
reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1;
reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1;
reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1;
reg [7:0] clk6_ht1, clk6_cnt, clk6_div, clk6_div1;
reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1;
real clkfbm1_f_div, clkfbm1_div_t;
integer clkfbm1_div_t_int;
reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti;
reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1;
reg [7:0] clkind_div, clkind_divi, clkind_div1, clkind_cnt, clkind_ht1;
reg clkind_out, clkind_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
wire clkinsel_tmp;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
reg init_chk;
reg rst_clkinsel_flag = 0;
reg clkout0_out, clkout1_out, clkout2_out, clkout3_out, clkout4_out;
reg clkout5_out, clkout6_out;
reg clkfbm2_out, clkfbm2_out_tmp, clk6_out;
reg notifier;
wire [15:0] do_out, di_in;
reg [15:0] do_out1;
wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in;
wire clkinsel_in1;
wire psen_in, psclk_in, psincdec_in, pwrdwn_in;
wire pwrdwn_in1;
reg pwrdwn_in1_h = 0;
reg rst_input_r_h = 0;
reg pchk_clr = 0;
reg psincdec_chg = 0;
reg psincdec_chg_tmp = 0;
wire [6:0] daddr_in;
wire rst_input;
wire rst_input_r;
reg startup_wait_sig;
wire delay_PSINCDEC, delay_PSEN, delay_PSCLK, delay_DCLK, delay_DWE;
wire delay_DEN;
wire [15:0] delay_DI;
wire [6:0] delay_DADDR;
reg vcoflag = 0;
reg [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED;
reg [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
wire PSDONE;
wire CLKINSTOPPED;
wire CLKFBSTOPPED;
`ifndef XIL_TIMING
assign CLKINSTOPPED = clkinstopped_out1;
assign CLKFBSTOPPED = clkfbstopped_out1;
assign clkin1_in = CLKIN1;
assign clkin2_in = CLKIN2;
assign clkfb_in = CLKFBIN;
assign clkinsel_in = ((CLKINSEL === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG;
assign rst_input_r = RST ^ IS_RST_INVERTED_REG;
assign daddr_in = DADDR;
assign di_in = DI;
assign dwe_in = DWE;
assign den_in = DEN;
assign dclk_in = DCLK;
assign psclk_in = PSCLK;
assign psen_in = PSEN;
assign psincdec_in = PSINCDEC;
assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_REG;
assign LOCKED = locked_out1;
assign DRDY = drdy_out1;
assign DO = do_out1;
assign PSDONE = psdone_out1;
//drp monitor
reg den_r1 = 1'b0;
reg den_r2 = 1'b0;
reg dwe_r1 = 1'b0;
reg dwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge dclk_in)
begin
// pipeline the DEN and DWE
den_r1 <= den_in;
dwe_r1 <= dwe_in;
den_r2 <= den_r1;
dwe_r2 <= dwe_r1;
// Check - if DEN or DWE is more than 1 DCLK
if ((den_r1 == 1'b1) && (den_r2 == 1'b1))
begin
$display("DRC Error : DEN is high for more than 1 DCLK on %m instance");
$finish;
end
if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1))
begin
$display("DRC Error : DWE is high for more than 1 DCLK on %m instance");
$finish;
end
//After the 1st DEN pulse, check the DEN and DRDY.
case (sfsm)
FSM_IDLE:
begin
if(den_in == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DEN, 4 cases can happen
// DEN DRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(den_in === 1'b1 && drdy_out1 === 1'b0)
begin
$display("DRC Error : DEN is enabled before DRDY returns on %m instance");
$finish;
end
//Add the check for another DWE pulse
if ((dwe_in === 1'b1) && (den_in === 1'b0))
begin
$display("DRC Error : DWE is enabled before DRDY returns on %m instance");
$finish;
end
if ((drdy_out1 === 1'b1) && (den_in === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((drdy_out1 === 1'b1)&& (den_in === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge DCLK)
//end drp monitor
always @(locked_out_tmp)
locked_out1 = locked_out_tmp;
always @(pll_locked_tmp2)
pll_locked_tmp2_dly = pll_locked_tmp2;
always @(drdy_out)
drdy_out1 = drdy_out;
always @(do_out)
do_out1 = do_out;
always @(psdone_out)
psdone_out1 = psdone_out;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
buf b_LOCK (LOCKED, locked_out_tmp);
buf b_DRDY (DRDY, drdy_out);
buf b_DO[15:0] (DO, do_out);
buf b_PSDONE (PSDONE, psdone_out);
buf b_CLKIN1 (clkin1_in, CLKIN1);
buf b_CLKIN2 (clkin2_in, CLKIN2);
buf b_CLKSRC (clkinsel_in1, CLKINSEL);
assign clkinsel_in = ((clkinsel_in1 === 0) ? 0 : 1) ^ IS_CLKINSEL_INVERTED_REG;
buf b_CLKFB (clkfb_in, CLKFBIN);
buf b_RST (rst_input_r, RST ^ IS_RST_INVERTED_REG);
buf b_DADDR[6:0] (daddr_in, delay_DADDR);
buf b_DI[15:0] (di_in, delay_DI);
buf b_DWE (dwe_in, delay_DWE);
buf b_DEN (den_in, delay_DEN);
buf b_DCLK (dclk_in, delay_DCLK);
buf b_CLKINSTOPPED (CLKINSTOPPED, clkinstopped_out1);
buf b_CLKFBSTOPPED ( CLKFBSTOPPED, clkfbstopped_out1);
buf b_PSEN (psen_in, delay_PSEN);
buf b_PSINCDEC (psincdec_in, delay_PSINCDEC);
buf b_PSCLK (psclk_in, delay_PSCLK);
buf b_PWRDWN (pwrdwn_in, PWRDWN ^ IS_PWRDWN_INVERTED_REG);
always @(pll_locked_tmp2)
pll_locked_tmp2_dly = pll_locked_tmp2;
`endif // `ifdef XIL_TIMING
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the PLLE2_ADV, the simulator resolution must be set to 1ps or smaller.");
$finish;
end
end
initial begin
case (STARTUP_WAIT)
"FALSE" : startup_wait_sig = 0;
"TRUE" : startup_wait_sig = 1;
default : begin
$display("Attribute Syntax Error : The Attribute STARTUP_WAIT on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", STARTUP_WAIT);
$finish;
end
endcase
case (BANDWIDTH)
"OPTIMIZED" : ;
"HIGH" : ;
"LOW" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BANDWIDTH on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are OPTIMIZED, HIGH, or LOW.", BANDWIDTH);
$finish;
end
endcase
case (CLKFBOUT_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKFBOUT_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT0_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT0_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT1_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT1_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT2_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT2_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT3_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT3_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT4_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT5_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT5_USE_FINE_PS);
$finish;
end
endcase
case (CLKOUT6_USE_FINE_PS)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT6_USE_FINE_PS);
$finish;
end
endcase
clkin_hold_f = 0;
// case (CLOCK_HOLD)
// "FALSE" : clkin_hold_f = 0;
// "TRUE" : clkin_hold_f = 1;
// default : begin
// $display("Attribute Syntax Error : The Attribute CLOCK_HOLD on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLOCK_HOLD);
// $finish;
// end
// endcase
case (CLKOUT4_CASCADE)
"FALSE" : clkout4_cascade_int = 0;
"TRUE" : clkout4_cascade_int = 1;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT4_CASCADE on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_CASCADE);
$finish;
end
endcase
case (COMPENSATION)
"ZHOLD" : ;
"BUF_IN" : ;
"EXTERNAL" : ;
"INTERNAL" : ;
default : begin
$display("Attribute Syntax Error : The Attribute COMPENSATION on PLLE2_ADV instance %m is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL, or INTERNAL.", COMPENSATION);
$finish;
end
endcase
clkfbm1_f_div = CLKFBOUT_MULT * 1.0;
clkfb_div_fint = CLKFBOUT_MULT;
clkfb_div_frac = 0.000;
clkfb_frac_en = 0;
clkfb_div_frac_int = 0;
// mf_product = clkfb_div_fint * 8 + clkfb_div_frac_int;
clk0_div_fint = CLKOUT0_DIVIDE;
clk0_div_frac = 0.000;
clk0_frac_en = 0;
clk0_div_frac_int = 0;
ps_in_init = 0;
ps_in_ps = ps_in_init;
ps_cnt = 0;
if (CLKFBOUT_USE_FINE_PS == "TRUE") begin
if (clkfb_frac_en == 1) begin
$display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_USE_FINE_PS);
$finish;
end
else
clkfb_fps_en = 1;
end
else
clkfb_fps_en = 0;
if (CLKOUT0_USE_FINE_PS == "TRUE") begin
if (clk0_frac_en == 1) begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on PLLE2_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_USE_FINE_PS);
$finish;
end
else
clk0_fps_en = 1;
end
else
clk0_fps_en = 0;
if (CLKOUT1_USE_FINE_PS == "TRUE")
clk1_fps_en = 1;
else
clk1_fps_en = 0;
if (CLKOUT2_USE_FINE_PS == "TRUE")
clk2_fps_en = 1;
else
clk2_fps_en = 0;
if (CLKOUT3_USE_FINE_PS == "TRUE")
clk3_fps_en = 1;
else
clk3_fps_en = 0;
if (CLKOUT4_USE_FINE_PS == "TRUE")
clk4_fps_en = 1;
else
clk4_fps_en = 0;
if (CLKOUT5_USE_FINE_PS == "TRUE")
clk5_fps_en = 1;
else
clk5_fps_en = 0;
if (CLKOUT6_USE_FINE_PS == "TRUE")
clk6_fps_en = 1;
else
clk6_fps_en = 0;
fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en
|| clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfb_fps_en;
tmp_string = "CLKOUT0_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT0_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT0_PHASE";
if (clk0_frac_en == 0)
chk_ok = para_real_range_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0);
else
if (CLKOUT0_PHASE != 0.0) begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_PHASE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_PHASE);
$finish;
end
tmp_string = "CLKOUT0_DUTY_CYCLE";
if (clk0_frac_en == 0)
chk_ok = para_real_range_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.001, 0.999);
else
if (CLKOUT0_DUTY_CYCLE != 0.5) begin
$display("Attribute Syntax Error : The Attribute CLKOUT0_DUTY_CYCLE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_DUTY_CYCLE);
$finish;
end
tmp_string = "CLKOUT1_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT1_PHASE";
chk_ok = para_real_range_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT2_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT2_PHASE";
chk_ok = para_real_range_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT3_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT3_PHASE";
chk_ok = para_real_range_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.001, 0.999);
tmp_string = "CLKOUT4_DIVIDE";
chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT4_PHASE";
chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.001, 0.999);
if (clk0_frac_en == 0) begin
tmp_string = "CLKOUT5_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT5_PHASE";
chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.001, 0.999);
end
if (clkfb_frac_en == 0) begin
tmp_string = "CLKOUT6_DIVIDE";
chk_ok = para_int_range_chk (CLKOUT6_DIVIDE, tmp_string, 1, 128);
tmp_string = "CLKOUT6_PHASE";
chk_ok = para_real_range_chk(CLKOUT6_PHASE, tmp_string, -360.0, 360.0);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = para_real_range_chk (CLKOUT6_DUTY_CYCLE, tmp_string, 0.001, 0.999);
end
tmp_string = "CLKFBOUT_MULT";
chk_ok = para_real_range_chk(CLKFBOUT_MULT, tmp_string, 2, 64);
tmp_string = "CLKFBOUT_PHASE";
if (clkfb_frac_en == 0)
chk_ok = para_real_range_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0);
else
if (CLKFBOUT_PHASE != 0.0) begin
$display("Attribute Syntax Error : The Attribute CLKFBOUT_PHASE on PLLE2_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_PHASE);
$finish;
end
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, D_MAX);
tmp_string = "REF_JITTER1";
chk_ok = para_real_range_chk (REF_JITTER1, tmp_string, 0.000, 0.999);
tmp_string = "REF_JITTER2";
chk_ok = para_real_range_chk (REF_JITTER2, tmp_string, 0.000, 0.999);
// if (BANDWIDTH === "LOW")
pll_lfhf = 2'b00;
// else
// pll_lfhf = 2'b00;
if (BANDWIDTH === "LOW")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
3 : begin pll_cp = 4'b0010; pll_res = 4'b0111; end
4 : begin pll_cp = 4'b0010; pll_res = 4'b1101; end
5 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end
6 : begin pll_cp = 4'b0010; pll_res = 4'b0101; end
7 : begin pll_cp = 4'b0010; pll_res = 4'b1001; end
8 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
9 : begin pll_cp = 4'b0010; pll_res = 4'b1110; end
10 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end
11 : begin pll_cp = 4'b0010; pll_res = 4'b0001; end
12 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
13 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
14 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
15 : begin pll_cp = 4'b0010; pll_res = 4'b0110; end
16 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
17 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
18 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
19 : begin pll_cp = 4'b0010; pll_res = 4'b1010; end
20 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
21 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
22 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
27 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
28 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
29 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
30 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end
31 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
32 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
33 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
34 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
35 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
36 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
37 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
38 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
39 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
40 : begin pll_cp = 4'b0010; pll_res = 4'b0010; end
41 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
42 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
43 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
44 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
45 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
46 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
47 : begin pll_cp = 4'b0011; pll_res = 4'b1100; end
48 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
49 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
50 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
51 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
52 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
53 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
54 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
55 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
56 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
57 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
58 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
59 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
60 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
endcase
else if (BANDWIDTH === "HIGH")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end
2 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end
3 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end
4 : begin pll_cp = 4'b0111; pll_res = 4'b1111; end
5 : begin pll_cp = 4'b0111; pll_res = 4'b1011; end
6 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end
7 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end
8 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end
9 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end
10 : begin pll_cp = 4'b1111; pll_res = 4'b0111; end
11 : begin pll_cp = 4'b1111; pll_res = 4'b1011; end
12 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end
14 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
20 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
21 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
22 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
27 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
28 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
29 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
30 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
31 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
32 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
33 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
34 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
35 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
36 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
37 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
38 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
39 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
41 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
47 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
48 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
49 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
50 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
51 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
52 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
53 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
54 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
55 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
56 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
57 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
58 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
59 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
60 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
endcase
else if (BANDWIDTH === "OPTIMIZED")
case (clkfb_div_fint)
1 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end
2 : begin pll_cp = 4'b0011; pll_res = 4'b0111; end
3 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end
4 : begin pll_cp = 4'b0111; pll_res = 4'b1111; end
5 : begin pll_cp = 4'b0111; pll_res = 4'b1011; end
6 : begin pll_cp = 4'b1101; pll_res = 4'b0111; end
7 : begin pll_cp = 4'b1110; pll_res = 4'b1011; end
8 : begin pll_cp = 4'b1110; pll_res = 4'b1101; end
9 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end
10 : begin pll_cp = 4'b1111; pll_res = 4'b0111; end
11 : begin pll_cp = 4'b1111; pll_res = 4'b1011; end
12 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b0011; end
14 : begin pll_cp = 4'b1110; pll_res = 4'b0101; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
20 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
21 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
22 : begin pll_cp = 4'b0111; pll_res = 4'b0110; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
27 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
28 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
29 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
30 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
31 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
32 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
33 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
34 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
35 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
36 : begin pll_cp = 4'b0100; pll_res = 4'b0010; end
37 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
38 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
39 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
40 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
41 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
42 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
43 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
44 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
45 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
46 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
47 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
48 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
49 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
50 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
51 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
52 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
53 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end
54 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
55 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
56 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
57 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
58 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
59 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
60 : begin pll_cp = 4'b0100; pll_res = 4'b1100; end
61 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
62 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
63 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
64 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end
endcase
case (clkfb_div_fint)
1 : begin drp_lock_ref_dly = 5'b00110;
drp_lock_fb_dly = 5'b00110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
2 : begin drp_lock_ref_dly = 5'b00110;
drp_lock_fb_dly = 5'b00110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
3 : begin drp_lock_ref_dly = 5'b01000;
drp_lock_fb_dly = 5'b01000;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
4 : begin drp_lock_ref_dly = 5'b01011;
drp_lock_fb_dly = 5'b01011;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
5 : begin drp_lock_ref_dly = 5'b01110;
drp_lock_fb_dly = 5'b01110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
6 : begin drp_lock_ref_dly = 5'b10001;
drp_lock_fb_dly = 5'b10001;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
7 : begin drp_lock_ref_dly = 5'b10011;
drp_lock_fb_dly = 5'b10011;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
8 : begin drp_lock_ref_dly = 5'b10110;
drp_lock_fb_dly = 5'b10110;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
9 : begin drp_lock_ref_dly = 5'b11001;
drp_lock_fb_dly = 5'b11001;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
10 : begin drp_lock_ref_dly = 5'b11100;
drp_lock_fb_dly = 5'b11100;
drp_lock_cnt = 10'b1111101000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
11 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1110000100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
12 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1100111001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
13 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1011101110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
14 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1010111100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
15 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1010001010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
16 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1001110001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
17 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000111111;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
18 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000100110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
19 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b1000001101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
20 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111110100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
21 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111011011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
22 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0111000010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
23 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110101001;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
24 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110010000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
25 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0110010000;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
26 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101110111;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
27 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101011110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
28 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101011110;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
29 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101000101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
30 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0101000101;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
31 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
32 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
33 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100101100;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
34 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
35 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
36 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0100010011;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
37 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
38 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
39 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
40 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
41 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
42 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
43 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
44 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
45 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
46 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
47 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
48 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
49 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
50 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
51 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
52 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
53 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
54 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
55 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
56 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
57 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
58 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
59 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
60 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
61 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
62 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
63 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
64 : begin drp_lock_ref_dly = 5'b11111;
drp_lock_fb_dly = 5'b11111;
drp_lock_cnt = 10'b0011111010;
drp_lock_sat_high = 10'b1111101001;
drp_unlock_cnt = 10'b0000000001; end
endcase
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX);
if(clkfb_frac_en == 0) begin
tmp_string = "CLKFBOUT_MULT";
chk_ok = para_int_range_chk (CLKFBOUT_MULT, tmp_string, M_MIN, M_MAX);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, tmp_string);
end
if(clk0_frac_en == 0) begin
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string);
end
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string);
period_vco_max = 1000000 / VCOCLK_FREQ_MIN;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clk0f_product = CLKOUT0_DIVIDE * 8;
pll_lock_time = 12;
lock_period_time = 10;
if (clkfb_frac_en == 1) begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT * 8;
clkout_en_val = mf_product - 2;
m_product2 = clkfb_div_fint / 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
md_product = clkfb_div_fint * DIVCLK_DIVIDE;
m_product = clkfb_div_fint;
mf_product = CLKFBOUT_MULT * 8;
m_product2 = clkfb_div_fint / 2;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
clkfb_stop_max = 3;
clkin_stop_max = DIVCLK_DIVIDE + 1;
REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE);
clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE);
clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE);
clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE);
clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50);
tmp_string = "CLKOUT1_PHASE";
clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string);
tmp_string = "CLKOUT2_PHASE";
clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string);
tmp_string = "CLKOUT3_PHASE";
clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string);
tmp_string = "CLKOUT4_PHASE";
clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string);
if (clkfb_frac_en == 1) begin
clkfbm1_dly = clkfb_div_fint /2;
clkout6_dly = clkfb_div_fint /2;
if (clkfb_div_fint_odd > 0) begin
clk6pm_sel = (8 + clkfb_div_frac_int) / 2;
clkfbm1pm_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ;
end
else begin
clkfbm1pm_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2;
clk6pm_sel = clkfb_div_frac_int / 2;
end
end
else begin
tmp_string = "CLKOUT6_PHASE";
clkout_dly_cal (clkout6_dly, clk6pm_sel, CLKOUT6_DIVIDE, CLKOUT6_PHASE, tmp_string);
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, clkfb_div_fint, CLKFBOUT_PHASE, tmp_string);
end
if (clk0_frac_en == 1) begin
clkout0_dly = clk0_div_fint /2;
clkout5_dly = clk0_div_fint /2;
if (clk0_div_fint_odd > 0) begin
clk5pm_sel = (8 + clk0_div_frac_int) / 2;
clk0pm_sel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2;
end
else begin
clk0pm_sel = clk0_div_frac_int - clk0_div_frac_int / 2;
clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2;
clk5pm_sel = clk0_div_frac_int / 2;
end
end
else begin
tmp_string = "CLKOUT0_PHASE";
clkout_dly_cal (clkout0_dly, clk0pm_sel, clk0_div_fint, CLKOUT0_PHASE, tmp_string);
tmp_string = "CLKOUT5_PHASE";
clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string);
end
if (clk0_frac_en == 1) begin
end
else begin
clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, clk0_div_fint, CLKOUT0_DUTY_CYCLE);
clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE);
end
if (clkfb_frac_en == 1) begin
end
else begin
clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50);
clk_out_para_cal (clk6_ht, clk6_lt, clk6_nocnt, clk6_edge, CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE);
end
clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, 1, 0.50);
clkind_div = DIVCLK_DIVIDE;
dr_sram[6] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]};
dr_sram[7] = {5'bx, 3'b0, clk5_edge, clk5_nocnt, clkout5_dly[5:0]};
dr_sram[8] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]};
dr_sram[10] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {6'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]};
dr_sram[12] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]};
dr_sram[13] = {6'bx, 2'b0, clk2_edge, clk2_nocnt, clkout2_dly[5:0]};
dr_sram[14] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]};
dr_sram[15] = {6'bx, 2'b0, clk3_edge, clk3_nocnt, clkout3_dly[5:0]};
dr_sram[16] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]};
dr_sram[17] = {5'bx, 3'b0, clk4_edge, clk4_nocnt, clkout4_dly[5:0]};
dr_sram[18] = {clk6pm_sel[2:0], 1'b1, clk6_ht[5:0], clk6_lt[5:0]};
dr_sram[19] = {6'bx, 2'b0, clk6_edge, clk6_nocnt, clkout6_dly[5:0]};
dr_sram[20] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]};
dr_sram[21] = {1'bx, 7'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]};
dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
dr_sram[116] = {5'bx, 6'b0, 5'b00001};
end
initial begin
clkpll_jitter_unlock = 0;
clkinstopped_vco_f = 0;
rst_clkfbstopped = 0;
rst_clkinstopped = 0;
rst_clkfbstopped_lk = 0;
rst_clkinstopped_lk = 0;
clkfb_stop_tmp = 0;
clkin_stop_tmp = 0;
clkout_ps = 0;
clkout_ps_tmp1 = 0;
clkout_ps_tmp2 = 0;
clkvco_ps_tmp1 = 0;
clkvco_ps_tmp2 = 0;
clkvco_ps_tmp2_en = 0;
clkvco_lk_osc = 0;
clkvco_lk_en = 0;
clkvco_lk_tmp = 0;
clkvco_lk_dly_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
clkind_edgei = 0;
clkind_nocnti = 0;
clkind_hti = 0;
clkind_lti = 0;
clkind_divi = 1;
ps_lock = 0;
ps_lock_dly = 0;
psdone_out = 0;
psdone_out1 = 0;
rst_in = 0;
clkinstopped_out = 0;
clkfbstopped_out = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_period_tmp_t = 0;
period_avg = 0;
period_fb = 0;
clkin_lost_val = 500;
clkfb_lost_val = 500;
clkin_lost_val_lk = 500;
fb_delay = 0;
clkfbm1_div = 1;
clkfbm2_div = 1;
clkfbm1_div1 = 0;
clkfbm2_div1 = 0;
clkvco_delay = 0;
val_tmp = 0;
dly_tmp = 0;
fbm1_comp_delay = 0;
clkfbm1pm_rl = 0;
period_vco = 0;
period_vco1 = 0;
period_vco2 = 0;
period_vco3 = 0;
period_vco4 = 0;
period_vco5 = 0;
period_vco6 = 0;
period_vco7 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
period_ps = 0;
period_ps_old = 0;
clkfb_frac_ht = 0;
clkfb_frac_lt = 0;
clk0_frac_ht = 0;
clk0_frac_lt = 0;
clkvco_rm_cnt = 0;
fb_delay_found = 0;
fb_delay_found_tmp = 0;
clkin_edge = 0;
delay_edge = 0;
fbclk_tmp = 0;
clkfb_tst = 0;
clkout_en = 0;
clkout_en0 = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tmp2_dly = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
clkout_mux = 8'b0;
clkout_ps_mux = 8'b0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
rst_edge = 0;
rst_ht = 0;
drdy_out = 0;
drdy_out1 = 0;
locked_out1 = 0;
locked_out_tmp = 0;
do_out1 = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 0;
clkout0_out = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clk2_dly_cnt = 6'b0;
clk3_dly_cnt = 6'b0;
clk4_dly_cnt = 6'b0;
clk5_dly_cnt = 6'b0;
clk6_dly_cnt = 6'b0;
clkfbm1_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clk2_cnt = 8'b0;
clk3_cnt = 8'b0;
clk4_cnt = 8'b0;
clk5_cnt = 8'b0;
clk6_cnt = 8'b0;
clkfbm1_cnt = 8'b0;
clkfbm2_cnt = 8'b0;
clkind_cnt = 8'b0;
clkout0_out = 0;
clkout1_out = 0;
clkout2_out = 0;
clkout3_out = 0;
clkout4_out = 0;
clkout5_out = 0;
clkout6_out = 0;
clk0_nf_out = 0;
clk0_frac_out = 0;
clk1_out = 0;
clk2_out = 0;
clk3_out = 0;
clk4_out = 0;
clk5_out = 0;
clk6_out = 0;
clkfb_out = 0;
clkfbm1_nf_out = 0;
clkfbm1_frac_out = 0;
clkfbm2_out = 0;
clkfbm2_out_tmp = 0;
clkind_out = 0;
clkind_out_tmp = 0;
clk_osc = 0;
clkin_p = 0;
clkfb_p = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
// assign CLKOUT6 = clkout6_out;
wire CLKOUT3B;
wire CLKOUT2B;
wire CLKOUT1B;
wire CLKOUT0B;
wire CLKFBOUTB;
assign CLKOUT5 = clkout5_out;
assign CLKOUT4 = clkout4_out;
assign CLKOUT3 = clkout3_out;
assign CLKOUT2 = clkout2_out;
assign CLKOUT1 = clkout1_out;
assign CLKOUT0 = clkout0_out;
assign CLKFBOUT = clkfb_out;
assign CLKOUT3B = ~clkout3_out;
assign CLKOUT2B = ~clkout2_out;
assign CLKOUT1B = ~clkout1_out;
assign CLKOUT0B = ~clkout0_out;
assign CLKFBOUTB = ~clkfb_out;
assign #1 clkinsel_tmp = clkinsel_in;
assign glock = (startup_wait_sig) ? locked_out_tmp : 1;
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial begin
init_chk = 0;
#1;
init_chk = 1;
end
always @(clkinsel_in or posedge init_chk ) begin
if ($time > 1 && rst_in === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin
$display("Input Error : Input clock can only be switched when RST=1. CLKINSEL on PLLE2_ADV instance %m at time %t changed when RST low, which should change at RST high.", $time);
$finish;
end
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (clkinsel_in === 1 && $time > 1 || clkinsel_in !== 0 && init_chk == 1) begin
if (CLKIN1_PERIOD > clkin_chk_t1 || CLKIN1_PERIOD < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
else if (clkinsel_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin
if (CLKIN2_PERIOD > clkin_chk_t1 || CLKIN2_PERIOD < clkin_chk_t2) begin
$display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, clkin_chk_t2, clkin_chk_t1);
$finish;
end
end
period_clkin = (clkinsel_in === 0) ? CLKIN2_PERIOD : CLKIN1_PERIOD;
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT) / (period_clkin * DIVCLK_DIVIDE);
if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX);
$finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX);
$finish;
end
end
end
assign init_trig = 1;
assign clkpll_r = (clkinsel_in) ? clkin1_in : clkin2_in;
assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0;
assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkpll_r or posedge rst_input)
if (rst_input)
rst_in <= 1;
else
rst_in <= rst_input ;
assign rst_in_o = (rst_in || rst_clkfbstopped || rst_clkinstopped);
//simprim_rst_h
always @(posedge pwrdwn_in1 or posedge pchk_clr)
if (pwrdwn_in1)
pwrdwn_in1_h <= 1;
else if (pchk_clr)
pwrdwn_in1_h <= 0;
always @(posedge rst_input_r or posedge pchk_clr)
if (rst_input_r)
rst_input_r_h <= 1;
else if (pchk_clr)
rst_input_r_h <= 0;
always @(rst_input )
if (rst_input==1) begin
rst_edge = $time;
pchk_clr = 0;
end
else if (rst_input==0 && rst_edge > 1) begin
rst_ht = $time - rst_edge;
if (rst_ht < 1500) begin
if (rst_input_r_h == 1 && pwrdwn_in1_h == 1)
$display("Input Error : RST and PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0)
$display("Input Error : RST on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1)
$display("Input Error : PWRDWN on instance %m at time %t must be asserted at least for 1.5 ns.", $time);
end
pchk_clr = 1;
end
//endsimprim_rst_h
//
// DRP port read and write
//
assign do_out = dr_sram[daddr_lat];
always @(posedge dclk_in or posedge GSR)
if (GSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 0;
end
else begin
if (den_in == 1) begin
valid_daddr = addr_is_valid(daddr_in);
if (drp_lock == 1) begin
//$display(" Warning : DEN is high at PLLE2_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time);
end
else begin
drp_lock <= 1;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
daddr_lat <= daddr_in;
end
if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 ||
daddr_in == 7'b1001110 || daddr_in == 7'b0101000 ||
(daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) ||
(daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin
end
else begin
$display(" Warning : Address DADDR=%b is unsupported at PLLE2_ADV instance %m at time %t. ", DADDR, $time);
end
if (dwe_in == 1) begin // write process
if (rst_input == 1) begin
if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 ||
daddr_in == 7'b1001110 || daddr_in == 7'b0101000 ||
(daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) ||
(daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin
dr_sram[daddr_in] <= di_in;
end
if (daddr_in == 7'b0001001)
clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in);
if (daddr_in == 7'b0001000)
clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0001011)
clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in);
if (daddr_in == 7'b0001010)
clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0001101)
clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in);
if (daddr_in == 7'b0001100)
clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0001111)
clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in);
if (daddr_in == 7'b0001110)
clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0010001)
clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in);
if (daddr_in == 7'b0010000)
clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0010011)
clkout_delay_para_drp (clkout6_dly, clk6_nocnt, clk6_edge, di_in, daddr_in);
if (daddr_in == 7'b0010010)
clkout_hl_para_drp (clk6_lt, clk6_ht, clk6pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0000111)
clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in);
if (daddr_in == 7'b0000110)
clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in);
if (daddr_in == 7'b0010101) begin
clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in);
clkfbtmp_nocnti = di_in[12];
end
if (daddr_in == 7'b0010100) begin
clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in);
clkfbtmp_lti = {2'b00, di_in[5:0]};
clkfbtmp_hti = {2'b00, di_in[11:6]};
if (clkfbtmp_nocnti == 1)
clkfbtmp_divi = 8'b00000001;
else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0)
clkfbtmp_divi = 8'b10000000;
else if (di_in[5:0] == 6'b0)
clkfbtmp_divi = 64 + clkfbtmp_hti;
else if (di_in[11:6] == 6'b0)
clkfbtmp_divi = 64 + clkfbtmp_lti;
else
clkfbtmp_divi = clkfbtmp_hti + clkfbtmp_lti;
if (SIM_DEVICE == "VIRTEX6") begin
if (clkfbtmp_divi > 64 || (clkfbtmp_divi < 5))
$display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %b and over the range of %d to %d.", daddr_in, di_in, $time, clkfbtmp_divi, 5, 64);
end
else begin
if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN))
$display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d.", daddr_in, di_in, $time, clkfbtmp_divi, M_MIN, M_MAX);
end
end
if (daddr_in == 7'b0010110) begin
clkind_lti = {2'b00, di_in[5:0]};
clkind_hti = {2'b00, di_in[11:6]};
clkind_lt <= clkind_lti;
clkind_ht <= clkind_hti;
clkind_nocnt <= di_in[12];
clkind_nocnti = di_in[12];
clkind_edgei = di_in[13];
clkind_edge <= di_in[13];
if (di_in[12] == 1)
clkind_divi = 8'b00000001;
else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0)
clkind_divi = 8'b10000000;
else if (di_in[5:0] == 6'b0)
clkind_divi = 64 + clkind_hti;
else if (di_in[11:6] == 6'b0)
clkind_divi = 64 + clkind_lti;
else
clkind_divi = clkind_hti + clkind_lti;
clkind_div <= clkind_divi;
if (clkind_divi > D_MAX || (clkind_divi < 1 && clkind_nocnti == 0))
$display(" Input Error : DI at Address DADDR=%b is %h at PLLE2_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to %d.", daddr_in, di_in, clkind_divi, $time, D_MAX);
end
end
else begin
$display(" Error : RST is low at PLLE2_ADV instance %m at time %t. RST need to be high when change PLLE2_ADV paramters through DRP. ", $time);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
end
else begin
drp_lock <= 0;
drdy_out <= 1;
drp_lock_lat_cnt <= 0;
end
end
if (drdy_out == 1) drdy_out <= 0;
end
function addr_is_valid;
input [6:0] daddr_funcin;
begin
addr_is_valid = 1;
for (i=0; i<=6; i=i+1)
if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
addr_is_valid = 0;
end
endfunction
// end process drp;
//
// determine clock period
//
always @(posedge clkpll_r or posedge rst_in or posedge rst_clkinsel_flag)
if (rst_in || rst_clkinsel_flag)
begin
clkin_period[0] <= period_vco_target;
clkin_period[1] <= period_vco_target;
clkin_period[2] <= period_vco_target;
clkin_period[3] <= period_vco_target;
clkin_period[4] <= period_vco_target;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end
else begin
clkin_edge <= $time;
if (clkin_edge != 0 && clkinstopped_out == 0 && rst_clkinsel_flag == 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0)
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
end
if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0)
pll_locked_tm <= 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(posedge pll_locked_tmp1)
if (clkinsel_in === 0) begin
pchk_tmp1 = CLKIN2_PERIOD * 1100;
pchk_tmp2 = CLKIN2_PERIOD * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN2 period and attribute CLKIN2_PERIOD on PLLE2_ADV instance %m are not same.");
$finish;
end
end
else begin
pchk_tmp1 = CLKIN1_PERIOD * 1100;
pchk_tmp2 = CLKIN1_PERIOD * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN1 period and attribute CLKIN1_PERIOD on PLLE2_ADV instance %m are not same.");
$finish;
end
end
always @(m_product or mf_product or clkfb_frac_en)
if (clkfb_frac_en == 0)
clkout_en_val = m_product;
else
clkout_en_val = mf_product - 2;
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
if (clkout_en0_tmp==0 )
clkout_en0 = 0;
else begin
if (clkfb_frac_en == 1) begin
if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
else begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in_o )
if (rst_in_o)
clkout_en = 0;
else
clkout_en = clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 = pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_in)
if (rst_in) begin
assign pll_locked_tmp2 = 0;
assign clkout_en0 = 0;
assign clkout_en1 = 0;
end
else begin
deassign pll_locked_tmp2;
deassign clkout_en0;
deassign clkout_en1;
end
assign locked_out = (pll_locked_tm && pll_locked_tmp2_dly && ~pll_unlock && !unlock_recover) ? 1 : 0;
always @(rst_in or locked_out)
if (rst_in == 1)
locked_out_tmp <= #1000 0;
else
locked_out_tmp <= locked_out;
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4] or period_avg ) begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp_t = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp_t = clkin_period[1] - clkin_period[0];
if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2]
+ clkin_period[3] + clkin_period[4])/5;
end
// assign clkinstopped_hold = (clkin_hold_f == 1) ? clkinstopped_out : 0;
always @(clkinstopped_out_dly or rst_in)
if (rst_in)
clkinstopped_hold = 0;
else begin
if (clkinstopped_out)
clkinstopped_hold <= #1 1;
else begin
if (clkin_hold_f)
clkinstopped_hold = 0;
end
end
always @(posedge clkinstopped_out) begin
period_avg_stpi <= period_avg;
pd_stp_p <= #1 1;
@(negedge clkvco)
pd_stp_p <= #1 0;
end
always @(negedge clkvco or posedge rst_in or posedge pd_stp_p)
if (rst_in) begin
period_avg_stp <= 1000;
vco_stp_f <= 0;
end
else if (pd_stp_p)
period_avg_stp <= period_avg_stpi;
else begin
if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin
if (period_vco > 1739)
vco_stp_f <= 1;
else begin
period_avg_stp <= period_avg_stp + 1;
end
end
end
always @(period_avg or lock_period or clkind_div)
if (period_avg > 500 && lock_period == 1) begin
clkin_lost_val = ((period_avg * 1.5) / 500) - 1;
clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1;
end
always @(clkfb_frac_en or clkfbm1_f_div or clkfbm1_div)
if (clkfb_frac_en)
clkfbm1_div_t = clkfbm1_f_div;
else
clkfbm1_div_t = clkfbm1_div;
always @(period_avg or clkind_div or clkfbm1_div_t or clkinstopped_hold
or period_avg_stp or posedge rst_clkinstopped_rc)
if (period_avg > 0 ) begin
md_product = clkind_div * clkfbm1_div_t;
m_product = clkfbm1_div_t;
m_product2 = clkfbm1_div_t / 2;
period_fb = period_avg * clkind_div;
period_vco_tmp = period_fb / clkfbm1_div_t;
clkvco_pdrm = (period_avg * clkind_div / clkfbm1_div_t) - period_vco_tmp;
period_vco_mf = period_avg * 8;
if (clkinstopped_hold == 1) begin
if (clkin_hold_f)
period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
else
period_vco = period_avg_stp * clkind_div /clkfbm1_div_t;
end
else
period_vco = period_vco_tmp;
clkfbm1_div_t_int = $rtoi(clkfbm1_div_t);
period_vco_rm = period_fb % clkfbm1_div_t_int;
if (period_vco_rm > 1) begin
if (period_vco_rm > m_product2) begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbm1_div_t;
clkin_dly_t = period_avg * (clkind_div + 1.25);
clkfb_dly_t = period_fb * 2.25 ;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco3 = period_vco * 3/ 8;
period_vco4 = period_vco / 2;
period_vco5 = period_vco * 5 / 8;
period_vco6 = period_vco *3 / 4;
period_vco7 = period_vco * 7 / 8;
clk0_frac_ht = period_vco * clkout0_dly + (period_vco * clk0pm_sel_int) / 8;
clk0_frac_lt = period_vco * clkout5_dly + (period_vco * clk5pm_sel) / 8;
clkfb_frac_ht = period_vco * clkfbm1_dly + (period_vco * clkfbm1pm_sel_int) / 8;
clkfb_frac_lt = period_vco * clkout6_dly + (period_vco * clk6pm_sel) / 8;
end
always @(period_vco or ps_in_ps)
if (fps_en == 1) begin
period_ps_old = period_ps;
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && psincdec_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @( clkpll_r )
clkpll_tmp1 <= #(period_avg) clkpll_r;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(posedge clkinstopped_out or posedge rst_in)
if ( rst_in)
clkinstopped_vco_f <= 0;
else begin
clkinstopped_vco_f <= 1;
@(negedge clkinstopped_out or posedge rst_in )
if (rst_in)
clkinstopped_vco_f <= 0;
else begin
@(posedge clkpll);
@(posedge clkpll)
clkinstopped_vco_f <= 0;
end
end
always @(posedge clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out1 <= 0;
else begin
clkinstopped_out1 <= 1;
if (clkin_hold_f == 1) begin
@(posedge locked_out or posedge rst_in)
clkinstopped_out1 <= 0;
end
else begin
if (clkinsel_in == 1)
$display(" Warning : input CLKIN1 of PLLE2_ADV on instance %m is stopped. Reset is required for PLLE2_ADV when input clock returns.");
else
$display(" Warning : input CLKIN2 of PLLE2_ADV on instance %m is stopped. Reset is required for PLLE2_ADV when input clock returns.");
end
end
always @(posedge clkfbstopped_out or posedge rst_in)
if (rst_in)
clkfbstopped_out1 <= 0;
else begin
clkfbstopped_out1 <= 1;
@(posedge locked_out)
clkfbstopped_out1 <= 0;
end
always @(clkout_en_t)
if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val)
rst_clkinstopped_tm = 1;
else
rst_clkinstopped_tm = 0;
always @(negedge clkinstopped_out or posedge rst_in)
if (rst_in)
rst_clkinstopped <= 0;
else
if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin
@(posedge rst_clkinstopped_tm)
rst_clkinstopped <= #period_vco4 1;
@(negedge rst_clkinstopped_tm ) begin
rst_clkinstopped <= #period_vco5 0;
rst_clkinstopped_rc <= #period_vco6 1;
rst_clkinstopped_rc <= #period_vco7 0;
end
end
always @(posedge clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out_dly <= 0;
else begin
clkinstopped_out_dly <= 1;
if (clkin_hold_f == 1) begin
@(negedge rst_clkinstopped_rc or posedge rst_in)
clkinstopped_out_dly <= 0;
end
end
always @(clkinstopped_out or posedge rst_in)
if (rst_in)
clkinstopped_out_dly2 <= 0;
else
clkinstopped_out_dly2 <= #2 clkinstopped_out;
always @(negedge rst_clkinstopped or posedge rst_in)
if (rst_in)
rst_clkinstopped_lk <= 0;
else begin
rst_clkinstopped_lk <= 1;
@(posedge locked_out)
rst_clkinstopped_lk <= 0;
end
always @(clkinstopped_vco_f or clkinstopped_out1 or clkvco_lk or
clkvco_lk_tmp or rst_in)
if (rst_in)
clkvco_lk = 0;
else begin
if (clkinstopped_out1 == 1 && clkin_stop_f == 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else if (clkinstopped_vco_f == 1 && period_vco_half > 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else
clkvco_lk = clkvco_lk_tmp;
end
always @(posedge clkpll)
if (clkfb_frac_en == 1) begin
if (pll_locked_tm ==1 ) begin
clkvco_lk_tmp <= 1;
cmpvco = 0.0;
for (ik1=1; ik1 < mf_product; ik1=ik1+1) begin
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( cmpvco >= 1.0 ) begin
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco - 1.0 + clkvco_pdrm;
end
else if ( cmpvco <= -1.0 ) begin
#(period_vco_half_rm2) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + 1.0 + clkvco_pdrm;
end
else begin
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
cmpvco <= cmpvco + clkvco_pdrm;
end
clkout_en_t <= ik1;
end
clkout_en_t <= ik1;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
else begin
if (pll_locked_tm ==1) begin
clkvco_lk_tmp <= 1;
clkvco_rm_cnt = 0;
clkout_en_t <= 0;
vcoflag = 0;
if ( period_vco_cmp_flag == 1) begin
vcoflag = 1;
for (ik2=1; ik2 < m_product; ik2=ik2+1) begin
clkout_en_t <= ik2;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
// #(period_vco_half1) clkvco_lk_tmp <= 1;
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik2;
end
else if ( period_vco_cmp_flag == 2 ) begin
vcoflag = 1;
for (ik3=1; ik3 < m_product; ik3=ik3+1) begin
clkout_en_t <= ik3;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik3;
end
else begin
vcoflag = 1;
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
end
#(period_vco_half) clkvco_lk_tmp <= 0;
// if (clkpll == 1) begin
if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0) begin
for (ik4=1; ik4 < m_product; ik4=ik4+1) begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
end
always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or clkfbm1pm_rl
or lock_period or ps_in_ps )
if (lock_period == 1) begin
if (clkfb_frac_en == 1) begin
fbm1_comp_delay = 0;
// val_tmp = period_vco * mf_product ;
val_tmp = period_vco_mf;
end
else begin
val_tmp = period_avg * DIVCLK_DIVIDE;
fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl);
end
dly_tmp1 = fb_delay + fbm1_comp_delay;
dly_tmp_int = 1;
if (clkfb_fps_en == 1) begin
if (ps_in_ps < 0) begin
tmp_ps_val1 = -1 * ps_in_ps;
tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0;
if (tmp_ps_val2 > dly_tmp1 ) begin
dly_tmp_int = -1;
dly_tmp = tmp_ps_val2 - dly_tmp1;
end
else if (tmp_ps_val2 == dly_tmp1 ) begin
dly_tmp_int = 0;
dly_tmp = 0;
end
else begin
dly_tmp_int = 1;
dly_tmp = dly_tmp1 - tmp_ps_val2;
end
end
else
dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0;
end
else
dly_tmp = dly_tmp1;
if (dly_tmp_int < 0)
clkvco_delay = dly_tmp;
else begin
if (clkfb_frac_en == 1 && dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
end
always @(period_vco or ps_in_ps )
if (fps_en == 1) begin
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && psincdec_in == 0)
period_ps = period_vco;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @(clkfbm1pm_sel)
case (clkfbm1pm_sel)
3'b000 : clkfbm1pm_rl = 0.0;
3'b001 : clkfbm1pm_rl = 0.125;
3'b010 : clkfbm1pm_rl = 0.25;
3'b011 : clkfbm1pm_rl = 0.375;
3'b100 : clkfbm1pm_rl = 0.50;
3'b101 : clkfbm1pm_rl = 0.625;
3'b110 : clkfbm1pm_rl = 0.75;
3'b111 : clkfbm1pm_rl = 0.875;
endcase
always @(clkvco_lk)
clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk;
always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm)
if ( pll_locked_tm && vco_stp_f == 0) begin
if (dly_tmp == 0)
clkvco = clkvco_lk;
else
clkvco = clkvco_lk_dly_tmp;
end
else
clkvco = 0;
always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge)
clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge);
always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge)
clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge);
always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge)
clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge);
always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge)
clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge);
always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge)
clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge);
always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge)
clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge);
always @(clk6_ht or clk6_lt or clk6_nocnt or init_trig or clk6_edge)
clkout_pm_cal(clk6_ht1, clk6_div, clk6_div1, clk6_ht, clk6_lt, clk6_nocnt, clk6_edge);
always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge)
if (clkfb_frac_en) begin
clkfbm1_div = CLKFBOUT_MULT;
end
else
clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge);
always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge)
clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge);
always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge)
clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge);
always @(posedge psclk_in or posedge rst_in)
if (rst_in) begin
ps_in_ps <= ps_in_init;
ps_cnt <= 0;
psen_w <= 0;
end
else if (fps_en == 1) begin
if (psen_in) begin
if (psen_w == 1)
$display(" Error : PSEN on PLLE2_ADV instance %m is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period.", $time);
psen_w <= 1;
if (ps_lock == 1)
$display(" Warning : Please wait for PSDONE signal on PLLE2_ADV instance %m at time %t before adjusting the Phase Shift.", $time);
else if (psincdec_in == 1) begin
if (ps_cnt < ps_max)
ps_cnt <= ps_cnt + 1;
else
ps_cnt <= 0;
if (ps_in_ps < ps_max)
ps_in_ps <= ps_in_ps + 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
else if (psincdec_in == 0) begin
ps_cnt_neg = (-1) * ps_cnt;
ps_in_ps_neg = (-1) * ps_in_ps;
if (ps_cnt_neg < ps_max)
ps_cnt <= ps_cnt - 1;
else
ps_cnt <= 0;
if (ps_in_ps_neg < ps_max)
ps_in_ps <= ps_in_ps - 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
end
else
psen_w <= 0;
if ( psdone_out == 1)
ps_lock <= 0;
end
always @(posedge ps_lock )
if (fps_en == 1) begin
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
@(posedge psclk_in)
begin
psdone_out = 1;
@(posedge psclk_in);
psdone_out = 0;
end
end
always @(rst_in_o)
if (rst_in_o) begin
assign clkout_mux = 8'b0;
assign clkout_ps_mux = 8'b0;
assign clkout_ps = 0;
assign clkout_ps_tmp1 = 0;
assign clkout_ps_tmp2 = 0;
assign clk0_frac_out = 0;
assign clkfbm1_frac_out = 0;
end
else begin
deassign clkout_mux;
deassign clkout_ps_mux;
deassign clkout_ps;
deassign clkout_ps_tmp1;
deassign clkout_ps_tmp2;
deassign clk0_frac_out;
deassign clkfbm1_frac_out;
end
always @(rst_clkinstopped)
if (rst_clkinstopped) begin
assign clkfb_frac_ht = 50;
assign clkfb_frac_lt = 50;
end
else begin
deassign clkfb_frac_ht;
deassign clkfb_frac_lt;
end
//always @(clkvco or clkout_en )
always @(clkvco)
if (clkout_en) begin
clkout_mux[0] = clkvco;
clkout_mux[1] <= #(period_vco1) clkvco;
clkout_mux[2] <= #(period_vco2) clkvco;
clkout_mux[3] <= #(period_vco3) clkvco;
clkout_mux[4] <= #(period_vco4) clkvco;
clkout_mux[5] <= #(period_vco5) clkvco;
clkout_mux[6] <= #(period_vco6) clkvco;
clkout_mux[7] <= #(period_vco7) clkvco;
end
always @(clkout_ps or clkout_en )
if (clkout_en) begin
clkout_ps_mux[0] = clkout_ps;
clkout_ps_mux[1] <= #(period_vco1) clkout_ps;
clkout_ps_mux[2] <= #(period_vco2) clkout_ps;
clkout_ps_mux[3] <= #(period_vco3) clkout_ps;
clkout_ps_mux[4] <= #(period_vco4) clkout_ps;
clkout_ps_mux[5] <= #(period_vco5) clkout_ps;
clkout_ps_mux[6] <= #(period_vco6) clkout_ps;
clkout_ps_mux[7] <= #(period_vco7) clkout_ps;
end
always @(clkvco or clkout_en )
if ( fps_en == 1) begin
clkvco_ps_tmp1 <= #(period_ps) clkvco;
clkvco_ps_tmp2 <= #(period_ps_old) clkvco;
end
always @(negedge clkout_ps)
clkout_ps_eg <= $time;
always @(posedge clkout_ps)
clkout_ps_peg <= $time;
always @(ps_lock)
ps_lock_dly <= #1 ps_lock;
always @(posedge ps_lock_dly)
if ((period_ps - period_ps_old) > period_vco_half ) begin
if (clkout_ps == 0) begin
if (clkvco_ps_tmp2 == 1) begin
clkout_ps_w = $time - clkout_ps_eg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(negedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
else begin
if (clkvco_ps_tmp2 == 0) begin
clkout_ps_w = $time - clkout_ps_peg;
if (clkout_ps_w > period_vco3)
clkvco_ps_tmp2_en <= 1;
else begin
@(posedge clkvco_ps_tmp2)
clkvco_ps_tmp2_en <= 1;
end
end
else
clkvco_ps_tmp2_en <= 1;
end
@(posedge clkvco_ps_tmp2);
@(negedge clkvco_ps_tmp2)
if (clkvco_ps_tmp1 == 0)
clkvco_ps_tmp2_en <= 0;
else
@(negedge clkvco_ps_tmp1)
clkvco_ps_tmp2_en <= 0;
end
always @(clkvco or clkvco_ps_tmp1 or clkvco_ps_tmp2 or clkvco_ps_tmp2_en )
if (fps_en == 1) begin
if (ps_in_ps == 0 )
clkout_ps = clkvco;
else if (clkvco_ps_tmp2_en == 1)
clkout_ps = clkvco_ps_tmp2;
else
clkout_ps = clkvco_ps_tmp1;
end
assign clk0in = (clk0_fps_en == 1) ? clkout_ps_mux[clk0pm_sel] : clkout_mux[clk0pm_sel1];
assign clk1in = (clk1_fps_en == 1) ? clkout_ps_mux[clk1pm_sel] : clkout_mux[clk1pm_sel];
assign clk2in = (clk2_fps_en == 1) ? clkout_ps_mux[clk2pm_sel] : clkout_mux[clk2pm_sel];
assign clk3in = (clk3_fps_en == 1) ? clkout_ps_mux[clk3pm_sel] : clkout_mux[clk3pm_sel];
assign clk4in = (clk4_fps_en == 1) ? clkout_ps_mux[clk4pm_sel] : ((clkout4_cascade_int == 1) ? clk6_out : clkout_mux[clk4pm_sel]);
assign clk5in = (clk5_fps_en == 1) ? clkout_ps_mux[clk5pm_sel] : clkout_mux[clk5pm_sel1];
assign clk6in = (clk6_fps_en == 1) ? clkout_ps_mux[clk6pm_sel] : clkout_mux[clk6pm_sel1];
assign clkfbm1in = (clkfb_fps_en == 1) ? clkout_ps_mux[clkfbm1pm_sel] : clkout_mux[clkfbm1pm_sel1];
assign clkfbm1pm_sel1 = (clkfb_frac_en) ? 3'b0 : clkfbm1pm_sel;
assign clk6pm_sel1 = (clkfb_frac_en) ? 3'b0 : clk6pm_sel;
assign clk0pm_sel1 = (clk0_frac_en) ? 3'b0 : clk0pm_sel;
assign clk5pm_sel1 = (clk0_frac_en) ? 3'b0 : clk5pm_sel;
assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0;
assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0;
assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0;
assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0;
assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0;
assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0;
assign clk6ps_en = (clk6_dly_cnt == clkout6_dly) ? clkout_en : 0;
assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0;
always @(posedge clk0in)
if (clkout_en && clk0_frac_en) begin
clk0_frac_out <= 1;
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
#(clk0_frac_ht) clk0_frac_out <= 0;
#(clk0_frac_lt) clk0_frac_out <= 1;
end
#(clk0_frac_ht) clk0_frac_out <= 0;
// #(clk0_frac_lt - 50);
#(clk0_frac_lt - period_vco1);
end
always @(posedge clkfbm1in)
if (clkout_en && clkfb_frac_en) begin
clkfbm1_frac_out <= 1;
for (ib=1; ib < 8; ib=ib+1) begin
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt) clkfbm1_frac_out <= 1;
end
#(clkfb_frac_ht) clkfbm1_frac_out <= 0;
#(clkfb_frac_lt - period_vco1);
end
else
clkfbm1_frac_out <= 0;
always @(negedge clk0in or posedge rst_in_o)
if (rst_in_o)
clk0_dly_cnt <= 6'b0;
else if (clkout_en == 1 && clk0_frac_en == 0) begin
if (clk0_dly_cnt < clkout0_dly)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in_o)
if (rst_in_o)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clkout1_dly && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
always @(negedge clk2in or posedge rst_in_o)
if (rst_in_o)
clk2_dly_cnt <= 6'b0;
else
if (clk2_dly_cnt < clkout2_dly && clkout_en ==1)
clk2_dly_cnt <= clk2_dly_cnt + 1;
always @(negedge clk3in or posedge rst_in_o)
if (rst_in_o)
clk3_dly_cnt <= 6'b0;
else
if (clk3_dly_cnt < clkout3_dly && clkout_en ==1)
clk3_dly_cnt <= clk3_dly_cnt + 1;
always @(negedge clk4in or posedge rst_in_o)
if (rst_in_o)
clk4_dly_cnt <= 6'b0;
else
if (clk4_dly_cnt < clkout4_dly && clkout_en ==1)
clk4_dly_cnt <= clk4_dly_cnt + 1;
always @(negedge clk5in or posedge rst_in_o)
if (rst_in_o)
clk5_dly_cnt <= 6'b0;
else if (clkout_en == 1 && clk0_frac_en == 0) begin
if (clk5_dly_cnt < clkout5_dly)
clk5_dly_cnt <= clk5_dly_cnt + 1;
end
always @(negedge clk6in or posedge rst_in_o)
if (rst_in_o)
clk6_dly_cnt <= 6'b0;
else if (clkout_en == 1 && clkfb_frac_en == 0) begin
if (clk6_dly_cnt < clkout6_dly)
clk6_dly_cnt <= clk6_dly_cnt + 1;
end
always @(negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o)
clkfbm1_dly_cnt <= 6'b0;
else if (clkout_en == 1 && clkfb_frac_en == 0) begin
if (clkfbm1_dly_cnt < clkfbm1_dly)
clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
end
always @(posedge clk0in or negedge clk0in or posedge rst_in_o)
if (rst_in_o) begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
else if (clk0ps_en && clk0_frac_en == 0) begin
if (clk0_cnt < clk0_div1)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 8'b0;
if (clk0_cnt < clk0_ht1)
clk0_nf_out <= 1;
else
clk0_nf_out <= 0;
end
else begin
clk0_cnt <= 8'b0;
clk0_nf_out <= 0;
end
assign clk0_out = (clk0_frac_en) ? clk0_frac_out : clk0_nf_out;
always @(posedge clk1in or negedge clk1in or posedge rst_in_o)
if (rst_in_o) begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
else if (clk1ps_en) begin
if (clk1_cnt < clk1_div1)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 8'b0;
if (clk1_cnt < clk1_ht1)
clk1_out <= 1;
else
clk1_out <= 0;
end
else begin
clk1_cnt <= 8'b0;
clk1_out <= 0;
end
always @(posedge clk2in or negedge clk2in or posedge rst_in_o)
if (rst_in_o) begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
else if (clk2ps_en) begin
if (clk2_cnt < clk2_div1)
clk2_cnt <= clk2_cnt + 1;
else
clk2_cnt <= 8'b0;
if (clk2_cnt < clk2_ht1)
clk2_out <= 1;
else
clk2_out <= 0;
end
else begin
clk2_cnt <= 8'b0;
clk2_out <= 0;
end
always @(posedge clk3in or negedge clk3in or posedge rst_in_o)
if (rst_in_o) begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
else if (clk3ps_en) begin
if (clk3_cnt < clk3_div1)
clk3_cnt <= clk3_cnt + 1;
else
clk3_cnt <= 8'b0;
if (clk3_cnt < clk3_ht1)
clk3_out <= 1;
else
clk3_out <= 0;
end
else begin
clk3_cnt <= 8'b0;
clk3_out <= 0;
end
always @(posedge clk4in or negedge clk4in or posedge rst_in_o)
if (rst_in_o) begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
else if (clk4ps_en) begin
if (clk4_cnt < clk4_div1)
clk4_cnt <= clk4_cnt + 1;
else
clk4_cnt <= 8'b0;
if (clk4_cnt < clk4_ht1)
clk4_out <= 1;
else
clk4_out <= 0;
end
else begin
clk4_cnt <= 8'b0;
clk4_out <= 0;
end
always @(posedge clk5in or negedge clk5in or posedge rst_in_o)
if (rst_in_o) begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
else if (clk5ps_en && clk0_frac_en == 0) begin
if (clk5_cnt < clk5_div1)
clk5_cnt <= clk5_cnt + 1;
else
clk5_cnt <= 8'b0;
if (clk5_cnt < clk5_ht1)
clk5_out <= 1;
else
clk5_out <= 0;
end
else begin
clk5_cnt <= 8'b0;
clk5_out <= 0;
end
always @(posedge clk6in or negedge clk6in or posedge rst_in_o)
if (rst_in_o) begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
else if (clk6ps_en && clkfb_frac_en == 0) begin
if (clk6_cnt < clk6_div1)
clk6_cnt <= clk6_cnt + 1;
else
clk6_cnt <= 8'b0;
if (clk6_cnt < clk6_ht1)
clk6_out <= 1;
else
clk6_out <= 0;
end
else begin
clk6_cnt <= 8'b0;
clk6_out <= 0;
end
always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in_o)
if (rst_in_o) begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
else if (clkfbm1ps_en && clkfb_frac_en == 0) begin
if (clkfbm1_cnt < clkfbm1_div1)
clkfbm1_cnt <= clkfbm1_cnt + 1;
else
clkfbm1_cnt <= 8'b0;
if (clkfbm1_cnt < clkfbm1_ht1)
clkfbm1_nf_out <= 1;
else
clkfbm1_nf_out <= 0;
end
else begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
assign clkfbm1_out = (clkfb_frac_en) ? clkfbm1_frac_out : clkfbm1_nf_out;
always @(posedge clkfb_in or negedge clkfb_in or posedge rst_in)
if (rst_in) begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
else if (clkout_en) begin
if (clkfbm2_cnt < clkfbm2_div1)
clkfbm2_cnt <= clkfbm2_cnt + 1;
else
clkfbm2_cnt <= 8'b0;
if (clkfbm2_cnt < clkfbm2_ht1)
clkfbm2_out <= 1;
else
clkfbm2_out <= 0;
end
else begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
always @(posedge clkpll_r or negedge clkpll_r or posedge rst_in)
if (rst_in) begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
else if (clkout_en) begin
if (clkind_cnt < clkind_div1)
clkind_cnt <= clkind_cnt + 1;
else
clkind_cnt <= 8'b0;
if (clkind_cnt < clkind_ht1)
clkind_out <= 1;
else
clkind_out <= 0;
end
else begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
always @(clk0_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout0_out = clk0_out;
else
clkout0_out = clkfb_tst;
always @(clk1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout1_out = clk1_out;
else
clkout1_out = clkfb_tst;
always @(clk2_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout2_out = clk2_out;
else
clkout2_out = clkfb_tst;
always @(clk3_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout3_out = clk3_out;
else
clkout3_out = clkfb_tst;
always @(clk4_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout4_out = clk4_out;
else
clkout4_out = clkfb_tst;
always @(clk5_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout5_out = clk5_out;
else
clkout5_out = clkfb_tst;
always @(clk6_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkout6_out = clk6_out;
else
clkout6_out = clkfb_tst;
always @(clkfbm1_out or clkfb_tst or fb_delay_found)
if (fb_delay_found == 1)
clkfb_out = clkfbm1_out;
else
clkfb_out = clkfb_tst;
//
// determine feedback delay
//
// always @(rst_in)
// if (rst_in)
// assign clkfb_tst = 0;
// else
// deassign clkfb_tst;
always @(posedge clkpll_r )
if (fb_delay_found_tmp == 0 && pwron_int == 0 && rst_in == 0) begin
clkfb_tst <= 1'b1;
end
else
clkfb_tst <= 1'b0;
always @( posedge clkfb_tst or posedge rst_in )
if (rst_in)
delay_edge <= 0;
else
delay_edge <= $time;
always @(posedge clkfb_in or posedge rst_in )
if (rst_in) begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
else
if (fb_delay_found_tmp ==0 ) begin
if ( delay_edge != 0)
fb_delay <= ($time - delay_edge);
else
fb_delay <= 0;
fb_delay_found_tmp <= 1;
end
always @(rst_in)
if (rst_in)
assign fb_delay_found = 0;
else
deassign fb_delay_found;
always @(fb_delay_found_tmp or clkvco_delay )
if (clkvco_delay == 0)
fb_delay_found <= #1000 fb_delay_found_tmp;
else
fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp;
always @(fb_delay)
if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning : The feedback delay on PLLE2_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max);
end
//
// generate unlock signal
//
always @(clk_osc or rst_in)
if (rst_in)
clk_osc <= 0;
else
clk_osc <= #OSC_P2 ~clk_osc;
always @(posedge clkpll_r or negedge clkpll_r) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge clkfb_in or negedge clkfb_in) begin
clkfb_p <= 1;
clkfb_p <= #100 0;
end
always @(posedge clk_osc or posedge rst_in or posedge clkin_p)
if (rst_in == 1) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out == 1) begin
@(posedge clkpll_r) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out <= 0;
end
else
clkinstopped_out <= 1;
end
always @(posedge clk_osc or posedge rst_in or posedge clkfb_p)
if (rst_in == 1 || clkfb_p == 1) begin
clkfbstopped_out <= 0;
clkfb_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfb_lost_cnt < clkfb_lost_val) begin
clkfb_lost_cnt <= clkfb_lost_cnt + 1;
clkfbstopped_out <= 0;
end
else
clkfbstopped_out <= 1;
end
always @(clkin_jit or rst_in )
if (rst_in)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2 && clkfbstopped_out == 0 && clkinstopped_out == 0) begin
if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// tasks
task clkout_dly_cal;
output [5:0] clkout_dly;
output [2:0] clkpm_sel;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
integer clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clkout_dly_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
clkout_dly_tmp = $rtoi(clk_dly_rl);
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of PLLE2_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of PLLE2_ADV", clk_ps_name, clk_ps);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
clk_dly_rem = clk_dly_rl - clkout_dly;
if (clk_dly_rem < 0.125)
clkpm_sel = 0;
else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25)
clkpm_sel = 1;
else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375)
clkpm_sel = 2;
else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5)
clkpm_sel = 3;
else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625)
clkpm_sel = 4;
else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75)
clkpm_sel = 5;
else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875)
clkpm_sel = 6;
else if (clk_dly_rem >= 0.875 )
clkpm_sel = 7;
if (clk_ps < 0.0)
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0;
else
clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv;
if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
$display(" Warning : Attribute %s of PLLE2_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl);
end
endtask
task clk_out_para_cal;
output [6:0] clk_ht;
output [6:0] clk_lt;
output clk_nocnt;
output clk_edge;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
integer CLKOUT_DIVIDE;
real CLKOUT_DUTY_CYCLE;
real tmp_value, tmp_value0, tmp_value_rm;
integer tmp_value_round, tmp_value1, tmp_value_r;
real tmp_value2;
real tmp_value_rm1, tmp_value_r1;
integer tmp_value_r2;
begin
tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE;
tmp_value_r = $rtoi(tmp_value0);
tmp_value_rm = tmp_value0 - tmp_value_r;
if (tmp_value_rm < 0.1)
tmp_value = tmp_value_r * 1.0;
else if (tmp_value_rm > 0.9)
tmp_value = 1.0 * tmp_value_r + 1.0;
else begin
tmp_value_r1 = tmp_value0 * 2.0;
tmp_value_r2 = $rtoi(tmp_value_r1);
tmp_value_rm1 = tmp_value_r1 - tmp_value_r2;
if (tmp_value_rm1 > 0.995)
tmp_value = tmp_value0 + 0.002;
else
tmp_value = tmp_value0;
end
tmp_value_round = tmp_value * 2.0;
tmp_value1 = tmp_value_round % 2;
tmp_value2 = CLKOUT_DIVIDE - tmp_value;
if ((tmp_value2) >= O_MAX_HT_LT) begin
clk_lt = 7'b1000000;
end
else begin
if (tmp_value2 < 1.0)
clk_lt = 1;
else
if ( tmp_value1 != 0)
clk_lt = $rtoi(tmp_value2) + 1;
else
clk_lt = $rtoi(tmp_value2);
end
if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT)
clk_ht = 7'b1000000;
else
clk_ht = CLKOUT_DIVIDE - clk_lt;
clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0;
if ( tmp_value < 1.0)
clk_edge = 1;
else if (tmp_value1 != 0)
clk_edge = 1;
else
clk_edge = 0;
end
endtask
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.0;
CLK_DUTY_CYCLE_MIN_rnd = 0.0;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
end
CLK_DUTY_CYCLE_MAX = 1.0;
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
end
clkout_duty_chk = 1'b1;
end
endfunction
function para_int_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
integer para_in;
integer range_low;
integer range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on PLLE2_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high);
$finish;
end
para_int_range_chk = 1'b1;
end
endfunction
function para_real_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
real para_in;
real range_low;
real range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Attribute Syntax Error : The Attribute %s on PLLE2_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high);
$finish;
end
para_real_range_chk = 1'b0;
end
endfunction
task clkout_pm_cal;
output [7:0] clk_ht1;
output [7:0] clk_div;
output [7:0] clk_div1;
input [6:0] clk_ht;
input [6:0] clk_lt;
input clk_nocnt;
input clk_edge;
begin
if (clk_nocnt ==1) begin
clk_div = 8'b00000001;
clk_div1 = 8'b00000001;
clk_ht1 = 8'b00000001;
end
else begin
if ( clk_edge == 1)
clk_ht1 = 2 * clk_ht + 1;
else
clk_ht1 = 2 * clk_ht;
clk_div = clk_ht + clk_lt ;
clk_div1 = 2 * clk_div -1;
end
end
endtask
task clkout_delay_para_drp;
output [5:0] clkout_dly;
output clk_nocnt;
output clk_edge;
input [15:0] di_in;
input [6:0] daddr_in;
begin
clkout_dly = di_in[5:0];
clk_nocnt = di_in[6];
clk_edge = di_in[7];
end
endtask
task clkout_hl_para_drp;
output [6:0] clk_lt;
output [6:0] clk_ht;
output [2:0] clkpm_sel;
input [15:0] di_in_tmp;
input [6:0] daddr_in_tmp;
begin
if (di_in_tmp[12] != 1) begin
$display(" Error : PLLE2_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time);
end
if ( di_in_tmp[5:0] == 6'b0)
clk_lt = 7'b1000000;
else
clk_lt = { 1'b0, di_in_tmp[5:0]};
if (di_in_tmp[11:6] == 6'b0)
clk_ht = 7'b1000000;
else
clk_ht = { 1'b0, di_in_tmp[11:6]};
clkpm_sel = di_in_tmp[15:13];
end
endtask
specify
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK *> DO) = (100:100:100, 100:100:100);
(RST => LOCKED) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(CLKIN1 => LOCKED) = (100:100:100, 100:100:100);
(CLKIN2 => LOCKED) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKIN2, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DADDR);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DEN);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DI);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, delay_DCLK, delay_DWE);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PLLE2_BASE.v 0000664 0000000 0000000 00000007743 12327044266 0023045 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.i (O.4)
// \ \ Description :
// / /
// /__/ /\ Filename : PLLE2_BASE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 12/09/09 - Initial version
// 03/23/10 - Change CLKFBOUT_MULT default from 1 to 5.
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE2_BASE (
CLKFBOUT,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 5;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE2_ADV #(
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.REF_JITTER1(REF_JITTER1)
)
plle2_adv_1 (
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST (RST)
);
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PLLE3_ADV.v 0000664 0000000 0000000 00000214245 12327044266 0022743 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : PLLE3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/22/2013 700625 - update PLLE3 for yml changes
// 02/28/2013 703674 - update vco_half attribute
// 03/25/2013 PLLE3 sync5 changes
// 04/04/2013 709484 - add PFD check
// 04/02/2013 709723 - fix Lock for lost clock
// 04/08/2013 709729 - Fix clkoutxiphy for CLKIN mode
// 04/09/2013 709725 - Fix clkout0 frequency after reset
// 04/09/2013 709726 - Fix clkout0 frequency
// 04/12/2013 Invertible pin changes
// 04/16/2013 Writer and invertible pin changes
// 04/22/2013 713959 - clkoutphy frequency fix after reset
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter real CLKIN_FREQ_MAX = 1066.000,
parameter real CLKIN_FREQ_MIN = 70.000,
parameter real CLKPFD_FREQ_MAX = 667.500,
parameter real CLKPFD_FREQ_MIN = 70.000,
parameter real VCOCLK_FREQ_MAX = 1335.000,
parameter real VCOCLK_FREQ_MIN = 600.000,
`endif
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUTPHY_MODE = "VCO_2X",
parameter COMPENSATION = "AUTO",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUTPHY,
output [15:0] DO,
output DRDY,
output LOCKED,
input CLKFBIN,
input CLKIN,
input CLKOUTPHYEN,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PWRDWN,
input RST
);
`ifndef XIL_TIMING
localparam real CLKIN_FREQ_MAX = 1066.000;
localparam real CLKIN_FREQ_MIN = 70.000;
localparam real CLKPFD_FREQ_MAX = 667.500;
localparam real CLKPFD_FREQ_MIN = 70.000;
localparam real VCOCLK_FREQ_MAX = 1335.000;
localparam real VCOCLK_FREQ_MIN = 600.000;
`endif //
localparam MODULE_NAME = "PLLE3_ADV";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
`ifndef XIL_DR
localparam [4:0] CLKFBOUT_MULT_REG = CLKFBOUT_MULT;
localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE;
localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX;
localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN;
localparam real CLKIN_PERIOD_REG = CLKIN_PERIOD;
localparam [7:0] CLKOUT0_DIVIDE_REG = CLKOUT0_DIVIDE;
localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE;
localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE;
localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE;
localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE;
localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE;
localparam [64:1] CLKOUTPHY_MODE_REG = CLKOUTPHY_MODE;
localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX;
localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN;
localparam [64:1] COMPENSATION_REG = COMPENSATION;
localparam [3:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN_INVERTED_REG = IS_CLKIN_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REF_JITTER_REG = REF_JITTER;
localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT;
localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX;
localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr=1'b0;
reg attr_err = 1'b0;
`ifdef XIL_DR
`include "PLLE3_ADV_dr.v"
`endif
tri1 p_up;
localparam VCOCLK_FREQ_TARGET = 1200;
localparam M_MIN = 1;
localparam M_MAX = 19;
localparam D_MIN = 1;
localparam D_MAX = 11;
// localparam O_MIN = 1; // not used
localparam O_MAX = 256;
localparam O_MAX_HT_LT = 128; // change from 64
localparam REF_CLK_JITTER_MAX = 1000;
localparam OSC_P2 = 250;
reg [160:0] tmp_string;
reg chk_ok;
reg init_chk;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
real clkvco_freq_init_chk;
real clkpfd_freq_init_chk;
reg startup_wait_sig;
reg [1:0] xiphy_mode;
wire [15:0] do_out;
wire [15:0] di_in;
reg [15:0] do_out1;
integer clkfb_div_fint;
wire locked_out;
reg locked_out1;
reg locked_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drdy_out, drdy_out1;
reg drp_lock;
reg [2:0] drp_lock_lat = 3'b100;
reg [2:0] drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
integer period_vco_max, period_vco_min;
integer period_vco_target, period_vco_target_half;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
integer md_product, m_product, m_product2;
integer clkout_en_val;
reg clkout0_out, clkout1_out;
reg [7:0] clk0_ht, clk0_lt;
reg [7:0] clk1_ht, clk1_lt;
reg clk0_edge, clk1_edge;
reg clk0_nocnt, clk1_nocnt;
reg rst_in = 1'b0;
integer clkin_period_tmp;
integer clkin_period [4:0];
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock = 1'b0;
integer clkin_jit;
integer pchk_tmp1, pchk_tmp2;
integer period_avg, period_fb;
wire clkin_in,clkfb_in;
reg clkout_en, clkout_en0_tmp, clkout_en0_tmp1=0, clkout_en0, clkout_en1;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2, pll_locked_tmp2_dly;
time clkin_edge, delay_edge;
time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay;
time dly_tmp1;
integer dly_tmp_int;
reg fb_delay_found, fb_delay_found_tmp;
real fb_delay_max;
integer period_vco_mf;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
integer period_vco_half_rm1, period_vco_half_rm2;
time pll_locked_delay, clkin_dly_t;
reg clkpll = 1'b0;
reg clkpll_tmp1 = 1'b0;
reg clkvco_lk = 1'b0, clkvco_lk_tmp = 1'b0, clkvco = 1'b0, clkvco_by2 = 1'b0, clkvco_2x = 1'b0;
reg clkvco_by8 = 1'b0;
integer i, ik2, ik3, ik4, j;
reg vcoflag = 1'b0;
integer clkout_en_t;
reg clk_osc, clkin_p, clkfb_p;
reg clkinstopped_out;
reg clkfbstopped_out;
integer clkin_lost_cnt, clkfb_lost_cnt;
integer clkin_lost_val, clkfb_lost_val;
reg clkinstopped_out_dly = 0;
reg pwron_int;
reg clkfb_tst = 1'b0;
reg [7:0] clkind_div;
reg [2:0] clkout_mux;
//reg [2:0] clk0pm_sel, clk1pm_sel, clkfbm1pm_sel;
reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti;
reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1;
reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1;
reg [7:0] clkind_divi, clkind_div1, clkind_cnt, clkind_ht1;
reg clkfbtmp_nocnti;
reg clkind_edgei, clkind_nocnti;
reg clkind_out, clkind_out_tmp;
reg [6:0] clkfbm1_ht, clkfbm1_lt;
reg [6:0] clkfbin_ht, clkfbin_lt;
reg [7:0] clkind_ht, clkind_lt;
reg [7:0] clkind_hti, clkind_lti;
reg clkfbm1_nocnt, clkind_nocnt;
reg clkfbm1_edge, clkind_edge;
reg clkfbin_edge, clkfbin_nocnt;
reg clkfbm1_nf_out;
integer period_vco1;
integer period_vco2;
reg clk0_out;
reg clk1_out;
reg clkfb_out;
wire clkfbm1_out;
reg clkfbm2_out;
reg [5:0] clk0_dly_cnt, clkout0_dly;
reg [5:0] clk1_dly_cnt, clkout1_dly;
reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly;
reg [8:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1;
reg [8:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1;
wire init_trig, clk0in, clk1in;
wire clkoutxiphy_int;
wire xiphyen_in;
reg xiphyen_sync;
reg xiphyen_sync1;
reg xiphyen_sync2;
reg [2:0] clkvco_cnt;
wire IS_CLKFBIN_INVERTED_BIN = IS_CLKFBIN_INVERTED_REG;
wire IS_CLKIN_INVERTED_BIN = IS_CLKIN_INVERTED_REG;
wire IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED_REG;
wire IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire [15:0] DI_delay;
wire [6:0] DADDR_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign DCLK_delay = DCLK;
assign DADDR_delay = DADDR;
assign DEN_delay = DEN;
assign DI_delay = DI;
assign DWE_delay = DWE;
`endif // `ifndef XIL_TIMING
assign clkfb_in = CLKFBIN ^ IS_CLKFBIN_INVERTED_BIN;
assign clkin_in = CLKIN ^ IS_CLKIN_INVERTED_BIN;
assign xiphyen_in = CLKOUTPHYEN;
assign rst_input_r = RST;
assign daddr_in = DADDR_delay;
assign di_in = DI_delay;
assign dwe_in = DWE_delay;
assign den_in = DEN_delay;
assign dclk_in = DCLK_delay;
assign pwrdwn_in = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign rst_input_r = RST ^ IS_RST_INVERTED_BIN;
assign LOCKED = locked_out1;
assign DRDY = drdy_out1;
assign DO = do_out1;
always @(locked_out_tmp)
locked_out1 = locked_out_tmp;
always @(pll_locked_tmp2)
pll_locked_tmp2_dly = pll_locked_tmp2;
always @(drdy_out)
drdy_out1 = drdy_out;
always @(do_out)
do_out1 = do_out;
// `endif // `ifndef XIL_TIMING
initial begin
#1;
trig_attr = ~trig_attr;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the %s, the simulator resolution must be set to 1ps or smaller.", MODULE_NAME);
$finish;
end
end
always @(trig_attr) begin
#1;
case (CLKOUTPHY_MODE_REG)
"VCO_2X" : xiphy_mode = 2'b00;
"VCO" : xiphy_mode = 2'b01;
"VCO_HALF" : xiphy_mode = 2'b10;
"CLKIN" : xiphy_mode = 2'b11;
default : begin
$display("Attribute Syntax Error : The attribute CLKOUTPHY_MODE on %s instance %m is set to %s. Legal values for this attribute are VCO_2X, CLKIN, VCO_HALF or VCO.", MODULE_NAME, CLKOUTPHY_MODE_REG);
attr_err = 1'b1;
end
endcase
case (COMPENSATION_REG)
"AUTO" : ;
"BUF_IN" : ;
"INTERNAL" : ;
default : begin
$display("Attribute Syntax Error : The attribute COMPENSATION on %s instance %m is set to %s. Legal values for this attribute are AUTO, BUF_IN or INTERNAL.", MODULE_NAME, COMPENSATION_REG);
attr_err = 1'b1;
end
endcase
case (STARTUP_WAIT_REG)
"FALSE" : startup_wait_sig = 1'b0;
"TRUE" : startup_wait_sig = 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute STARTUP_WAIT on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, STARTUP_WAIT_REG);
attr_err = 1'b1;
end
endcase
if ((CLKFBOUT_MULT_REG >= 1) && (CLKFBOUT_MULT_REG <= 19));
else begin
$display("Attribute Syntax Error : The attribute CLKFBOUT_MULT on %s instance %m is set to %d. Legal values for this attribute are 1 to 19.", MODULE_NAME, CLKFBOUT_MULT_REG);
attr_err = 1'b1;
end
if ((CLKIN_PERIOD_REG >= 0.000) && (CLKIN_PERIOD_REG <= 14.286));
else begin
$display("Attribute Syntax Error : The attribute CLKIN_PERIOD on %s instance %m is set to %f. Legal values for this attribute are 0.000 to 14.286.", MODULE_NAME, CLKIN_PERIOD_REG);
attr_err = 1'b1;
end
if ((CLKOUT0_DIVIDE_REG >= 1) && (CLKOUT0_DIVIDE_REG <= 256));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT0_DIVIDE on %s instance %m is set to %d. Legal values for this attribute are 1 to 256.", MODULE_NAME, CLKOUT0_DIVIDE_REG);
attr_err = 1'b1;
end
if ((CLKOUT0_DUTY_CYCLE_REG >= 0.001) && (CLKOUT0_DUTY_CYCLE_REG <= 0.999));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT0_DUTY_CYCLE on %s instance %m is set to %f. Legal values for this attribute are 0.001 to 0.999.", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((CLKOUT1_DIVIDE_REG >= 1) && (CLKOUT1_DIVIDE_REG <= 256));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT1_DIVIDE on %s instance %m is set to %f. Legal values for this attribute are 1 to 256.", MODULE_NAME, CLKOUT1_DIVIDE_REG);
attr_err = 1'b1;
end
if ((CLKOUT1_DUTY_CYCLE_REG >= 0.001) && (CLKOUT1_DUTY_CYCLE_REG <= 0.999));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT1_DUTY_CYCLE on %s instance %m is set to %f. Legal values for this attribute are 0.001 to 0.999.", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((CLKOUT0_PHASE_REG >= -360.0) && (CLKOUT0_PHASE_REG <= 360.0));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT0_PHASE on %s instance %m is set to %f. Legal values for this attribute are -360.0 to 360.0.", MODULE_NAME, CLKOUT0_PHASE_REG);
attr_err = 1'b1;
end
if ((CLKOUT1_PHASE_REG >= -360.0) && (CLKOUT1_PHASE_REG <= 360.0));
else begin
$display("Attribute Syntax Error : The attribute CLKOUT1_PHASE on %s instance %m is set to %f. Legal values for this attribute are -360.0 to 360.0.", MODULE_NAME, CLKOUT1_PHASE_REG);
attr_err = 1'b1;
end
if ((CLKFBOUT_PHASE_REG >= -360.0) && (CLKFBOUT_PHASE_REG <= 360.0));
else begin
$display("Attribute Syntax Error : The attribute CLKFBOUT_PHASE on %s instance %m is set to %f. Legal values for this attribute are -360.0 to 360.0.", MODULE_NAME, CLKFBOUT_PHASE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string);
clkfb_div_fint = CLKFBOUT_MULT_REG;
clkfbm1_div = CLKFBOUT_MULT_REG;
clkind_div = DIVCLK_DIVIDE_REG;
period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
pll_lock_time = 12;
lock_period_time = 10;
md_product = clkfb_div_fint * DIVCLK_DIVIDE_REG;
m_product = clkfb_div_fint;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE_REG, CLKOUT0_DUTY_CYCLE_REG);
clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG);
clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE_REG, 0.50);
clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50);
tmp_string = "CLKOUT0_PHASE";
clkout_dly_cal (clkout0_dly, CLKOUT0_DIVIDE_REG, CLKOUT0_PHASE_REG, tmp_string);
tmp_string = "CLKOUT1_PHASE";
clkout_dly_cal (clkout1_dly, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, tmp_string);
tmp_string = "CLKFBOUT_PHASE";
clkout_dly_cal (clkfbm1_dly, clkfb_div_fint, CLKFBOUT_PHASE_REG, tmp_string);
case (clkfb_div_fint)
2 : begin pll_cp = 4'd3; pll_res = 4'd7; end
3 : begin pll_cp = 4'd5; pll_res = 4'd15;end
4 : begin pll_cp = 4'd7; pll_res = 4'd15;end
5 : begin pll_cp = 4'd7; pll_res = 4'd11;end
6 : begin pll_cp = 4'd13; pll_res = 4'd7; end
7 : begin pll_cp = 4'd14; pll_res = 4'd11;end
8 : begin pll_cp = 4'd14; pll_res = 4'd13;end
9 : begin pll_cp = 4'd15; pll_res = 4'd13;end
10 : begin pll_cp = 4'd15; pll_res = 4'd3; end
11 : begin pll_cp = 4'd14; pll_res = 4'd5; end
12 : begin pll_cp = 4'd15; pll_res = 4'd5; end
13 : begin pll_cp = 4'd15; pll_res = 4'd9; end
14 : begin pll_cp = 4'd13; pll_res = 4'd1; end
15 : begin pll_cp = 4'd15; pll_res = 4'd14; end
16 : begin pll_cp = 4'd14; pll_res = 4'd1; end
17 : begin pll_cp = 4'd15; pll_res = 4'd1; end
18 : begin pll_cp = 4'd15; pll_res = 4'd1; end
19 : begin pll_cp = 4'd15; pll_res = 4'd1; end
20 : begin pll_cp = 4'd14; pll_res = 4'd6; end
21 : begin pll_cp = 4'd14; pll_res = 4'd6; end
22 : begin pll_cp = 4'd15; pll_res = 4'd6; end
23 : begin pll_cp = 4'd15; pll_res = 4'd6; end
24 : begin pll_cp = 4'd14; pll_res = 4'd10; end
25 : begin pll_cp = 4'd14; pll_res = 4'd10; end
26 : begin pll_cp = 4'd14; pll_res = 4'd10; end
27 : begin pll_cp = 4'd13; pll_res = 4'd10; end
28 : begin pll_cp = 4'd6; pll_res = 4'd2; end
29 : begin pll_cp = 4'd6; pll_res = 4'd2; end
30 : begin pll_cp = 4'd6; pll_res = 4'd2; end
31 : begin pll_cp = 4'd13; pll_res = 4'd6; end
32 : begin pll_cp = 4'd12; pll_res = 4'd10; end
33 : begin pll_cp = 4'd6; pll_res = 4'd12; end
34 : begin pll_cp = 4'd6; pll_res = 4'd12; end
35 : begin pll_cp = 4'd5; pll_res = 4'd2; end
36 : begin pll_cp = 4'd3; pll_res = 4'd4; end
37 : begin pll_cp = 4'd3; pll_res = 4'd4; end
38 : begin pll_cp = 4'd3; pll_res = 4'd4; end
39 : begin pll_cp = 4'd3; pll_res = 4'd4; end
40 : begin pll_cp = 4'd3; pll_res = 4'd4; end
41 : begin pll_cp = 4'd2; pll_res = 4'd8; end
42 : begin pll_cp = 4'd2; pll_res = 4'd8; end
43 : begin pll_cp = 4'd2; pll_res = 4'd8; end
44 : begin pll_cp = 4'd2; pll_res = 4'd8; end
45 : begin pll_cp = 4'd2; pll_res = 4'd8; end
46 : begin pll_cp = 4'd2; pll_res = 4'd8; end
47 : begin pll_cp = 4'd2; pll_res = 4'd8; end
48 : begin pll_cp = 4'd2; pll_res = 4'd8; end
49 : begin pll_cp = 4'd2; pll_res = 4'd8; end
50 : begin pll_cp = 4'd2; pll_res = 4'd8; end
51 : begin pll_cp = 4'd2; pll_res = 4'd8; end
52 : begin pll_cp = 4'd2; pll_res = 4'd8; end
53 : begin pll_cp = 4'd2; pll_res = 4'd8; end
54 : begin pll_cp = 4'd4; pll_res = 4'd12; end
55 : begin pll_cp = 4'd4; pll_res = 4'd12; end
56 : begin pll_cp = 4'd4; pll_res = 4'd12; end
57 : begin pll_cp = 4'd4; pll_res = 4'd12; end
58 : begin pll_cp = 4'd4; pll_res = 4'd12; end
59 : begin pll_cp = 4'd4; pll_res = 4'd12; end
60 : begin pll_cp = 4'd4; pll_res = 4'd12; end
61 : begin pll_cp = 4'd2; pll_res = 4'd4; end
62 : begin pll_cp = 4'd2; pll_res = 4'd4; end
63 : begin pll_cp = 4'd2; pll_res = 4'd4; end
64 : begin pll_cp = 4'd2; pll_res = 4'd4; end
endcase
case (clkfb_div_fint)
1 : begin
drp_lock_ref_dly = 32'd6;
drp_lock_fb_dly = 32'd6;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
2 : begin
drp_lock_ref_dly = 32'd6;
drp_lock_fb_dly = 32'd6;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
3 : begin
drp_lock_ref_dly = 32'd8;
drp_lock_fb_dly = 32'd8;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
4 : begin
drp_lock_ref_dly = 32'd11;
drp_lock_fb_dly = 32'd11;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
5 : begin
drp_lock_ref_dly = 32'd14;
drp_lock_fb_dly = 32'd14;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
6 : begin
drp_lock_ref_dly = 32'd17;
drp_lock_fb_dly = 32'd17;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
7 : begin
drp_lock_ref_dly = 32'd19;
drp_lock_fb_dly = 32'd19;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
8 : begin
drp_lock_ref_dly = 32'd22;
drp_lock_fb_dly = 32'd22;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
9 : begin
drp_lock_ref_dly = 32'd25;
drp_lock_fb_dly = 32'd25;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
10 : begin
drp_lock_ref_dly = 32'd28;
drp_lock_fb_dly = 32'd28;
drp_lock_cnt = 32'd1000;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
11 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd900;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
12 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd825;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
13 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd750;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
14 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd700;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
15 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd650;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
16 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd625;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
17 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd575;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
18 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd550;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
19 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd525;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
20 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd500;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
21 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd475;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
22 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd450;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
23 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd425;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
24 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd400;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
25 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd400;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
26 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd375;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
27 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd350;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
28 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd350;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
29 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd325;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
30 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd325;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
31 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
32 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
33 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd300;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
34 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
35 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
36 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd275;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
37 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
38 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
39 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
40 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
41 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
42 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
43 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
44 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
45 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
46 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
47 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
48 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
49 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
50 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
51 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
52 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
53 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
54 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
55 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
56 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
57 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
58 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
59 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
60 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
61 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
62 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
63 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
64 : begin
drp_lock_ref_dly = 32'd31;
drp_lock_fb_dly = 32'd31;
drp_lock_cnt = 32'd250;
drp_lock_sat_high = 32'd1001;
drp_unlock_cnt = 32'd1;
end
endcase
dr_sram[8] = {3'bx, 1'b1, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]};
dr_sram[10] = {3'bx, 1'b1, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {1'bx, xiphy_mode[1], xiphy_mode[0],3'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]};
dr_sram[20] = {3'bx, 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]};
dr_sram[21] = {8'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]};
dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]};
dr_sram[23] = {2'bx, clkfbin_edge, clkfbin_nocnt, clkfbin_ht[5:0], clkfbin_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
end
initial
begin
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_lost_val = 500;
clkfb_lost_val = 500;
period_avg = 0;
period_fb = 0;
period_vco = 0;
period_vco1 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
clkvco_rm_cnt = 0;
fb_delay = 0;
fb_delay_found = 0;
fb_delay_found_tmp = 0;
val_tmp = 0;
dly_tmp = 0;
fbm1_comp_delay = 0;
clkin_edge = 0;
delay_edge = 0;
clkfb_tst = 0;
clkout_en = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tmp2_dly = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
clkout_mux = 3'b0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
drdy_out = 0;
drdy_out1 = 0;
locked_out1 = 0;
locked_out_tmp = 0;
do_out1 = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 3'b000;
clkout0_out = 0;
clk0_cnt = 9'b0;
clk1_cnt = 9'b0;
clkout0_out = 0;
clkout1_out = 0;
clk0_out = 0;
clk1_out = 0;
clkind_edgei = 0;
clkind_nocnti = 0;
clkind_hti = 0;
clkind_lti = 0;
clkind_divi = 1;
clkfbm1_div = 1;
clkfbm1_div1 = 0;
clkfbm1_cnt = 8'b0;
clkind_cnt = 8'b0;
clkfbm1_nf_out = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clkfbm1_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clkfbm1_cnt = 8'b0;
clkfbm2_cnt = 8'b0;
clkfb_out = 0;
clkfbm1_nf_out = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
assign CLKOUT0 = clkout0_out;
assign CLKOUT0B = ~clkout0_out;
assign CLKOUT1 = clkout1_out;
assign CLKOUT1B = ~clkout1_out;
assign CLKFBOUT = clkfb_out;
assign clkoutxiphy_int = xiphy_mode[1] ? (xiphy_mode[0] ? clkind_out : clkvco_by2) : (xiphy_mode[0] ? clkvco : clkvco_2x);
// assign CLKOUTPHY = xiphyen_in & clkoutxiphy_int;
assign CLKOUTPHY = xiphyen_in ? clkoutxiphy_int : 1'b0;
assign glock = (startup_wait_sig) ? locked_out_tmp : 1; // Are these needed
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial
begin
init_chk = 0;
#1;
init_chk = 1;
end
always @(posedge init_chk )
begin
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (($time > 1) && (CLKIN_PERIOD_REG > clkin_chk_t1 || CLKIN_PERIOD_REG < clkin_chk_t2))
begin
$display (" Attribute Syntax Error : The attribute CLKIN_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
$finish;
end
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_REG) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG);
if (($time > 1) && (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG))
begin
$display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
$finish;
end
clkpfd_freq_init_chk = (1000.0) / (CLKIN_PERIOD_REG * DIVCLK_DIVIDE_REG);
if ( ($time > 1) && (clkpfd_freq_init_chk > CLKPFD_FREQ_MAX_REG || clkpfd_freq_init_chk < CLKPFD_FREQ_MIN_REG)) begin
$display (" Attribute Syntax Error : The calculation of PFD frequency=%f Mhz. This exceeds the permitted PFD frequency range of %f Mhz to %f Mhz. The PFD frequency is calculated with formula: PFD frequency = 1 /(DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted PFD frequency range.", clkpfd_freq_init_chk, CLKPFD_FREQ_MIN_REG, CLKPFD_FREQ_MAX_REG);
$finish;
end
end
assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0;
assign rst_input = (rst_input_r === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkin_in or posedge rst_input)
begin
if (rst_input)
rst_in <= 1;
else
rst_in <= rst_input ;
end
// DRP port read write
assign do_out = dr_sram[daddr_lat];
always @(posedge dclk_in or posedge glblGSR)
if (glblGSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 3'b000;
end
else begin
if (den_in == 1) begin
valid_daddr = addr_is_valid(daddr_in);
if (drp_lock == 1) begin
$display(" Warning : DEN is high at %s instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time, MODULE_NAME);
end
else begin
drp_lock <= 1;
daddr_lat <= daddr_in;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001;
end
if (valid_daddr && ( daddr_in == 7'b1011100 || daddr_in == 7'b1001111 ||
daddr_in == 7'b1001110 || (daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) ||
daddr_in == 7'b0010110 || (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010))) begin
end
else begin
$display(" Warning : Address DADDR=%b is unsupported at %s instance %m at time %t. ", DADDR, MODULE_NAME,$time);
end
if (dwe_in == 1) begin // write process
if (rst_input == 1) begin
if (valid_daddr &&
((daddr_in >= 7'b0001000 && daddr_in <= 7'b0001011) || // 8 - 11
(daddr_in >= 7'b0010100 && daddr_in <= 7'b0010110) || // 20 - 22
(daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || // 24 - 26
daddr_in == 7'b1001110 || // 78
daddr_in == 7'b1001111 || // 79
daddr_in == 7'b1011100)) begin // 92
dr_sram[daddr_in] <= di_in;
end
if (daddr_in == 7'b0001000) // 8
clkout_hl_para_drp (clk0_lt, clk0_ht, di_in, daddr_in);
if (daddr_in == 7'b0001001) // 9
clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in);
if (daddr_in == 7'b0001010) // 10
clkout_hl_para_drp (clk1_lt, clk1_ht, di_in, daddr_in);
if (daddr_in == 7'b0001011) // 11
clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in);
if (daddr_in == 7'b0010100) begin // 20
clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, di_in, daddr_in);
clkfbtmp_divi = clkfbm1_ht + clkfbm1_lt;
if (clkfbtmp_divi > M_MAX || (clkfbtmp_divi < M_MIN))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d.", daddr_in, di_in, MODULE_NAME, clkfbtmp_divi, $time, M_MIN, M_MAX);
end
if (daddr_in == 7'b0010101) begin // 21
clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in);
clkfbtmp_nocnti = di_in[12];
end
if (daddr_in == 7'b0010110) begin // 22
clkind_lti = {2'b00, di_in[5:0]};
clkind_hti = {2'b00, di_in[11:6]};
clkind_lt <= clkind_lti;
clkind_ht <= clkind_hti;
clkind_nocnt <= di_in[12];
clkind_nocnti = di_in[12];
clkind_edgei = di_in[13];
clkind_edge <= di_in[13];
if (di_in[12] == 1)
clkind_divi = 8'b00000001;
else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0)
clkind_divi = 8'b10000000;
else if (di_in[5:0] == 6'b0)
clkind_divi = 64 + clkind_hti;
else if (di_in[11:6] == 6'b0)
clkind_divi = 64 + clkind_lti;
else
clkind_divi = clkind_hti + clkind_lti;
clkind_div <= clkind_divi;
if (clkind_divi > D_MAX || (clkind_divi < D_MIN && clkind_nocnti == 0))
$display(" Input Error : DI at Address DADDR=%b is %h at %s instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d.", daddr_in, di_in, MODULE_NAME, clkind_divi, $time, D_MIN, D_MAX);
end
end
else begin
$display(" Error : RST is low at %s instance %m at time %t. RST need to be high when change %s paramters through DRP. ", MODULE_NAME, $time, MODULE_NAME);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 3'b001;
end
else begin
drp_lock <= 0;
drp_lock_lat_cnt <= 3'b000;
drdy_out <= 1;
end
end
if (drdy_out == 1) drdy_out <= 0;
end
function addr_is_valid;
input [6:0] daddr_funcin;
begin
addr_is_valid = 1;
for (i=0; i<=6; i=i+1)
if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
addr_is_valid = 0;
end
endfunction
// Determine clock period
always @(posedge pll_locked_tmp1)
begin
pchk_tmp1 = CLKIN_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning : input CLKIN period and attribute CLKIN_PERIOD on %s instance %m are not same.", MODULE_NAME);
end
end
always @(posedge clkin_in or posedge rst_in)
if (rst_in)
begin
clkin_period[0] <= period_vco_target;
clkin_period[1] <= period_vco_target;
clkin_period[2] <= period_vco_target;
clkin_period[3] <= period_vco_target;
clkin_period[4] <= period_vco_target;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end
else begin
clkin_edge <= $time;
if (clkin_edge != 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0)
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
end
if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0)
pll_locked_tm <= 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4] or period_avg )
begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp = clkin_period[1] - clkin_period[0];
if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + clkin_period[3] + clkin_period[4])/5;
end
always @(period_avg or lock_period or clkind_div)
if (period_avg > 500 && lock_period == 1) begin
clkin_lost_val = ((period_avg * 1.5) / 500) - 1;
clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1;
end
assign init_trig = 1;
always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge)
clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge);
always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge)
clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge);
always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge)
clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge);
always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge)
clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge);
// Unlock due to jitter
always @(clkin_jit or rst_in )
begin
if (rst_in)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2) begin
if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
end
// Determine feedback delay - only internal feedback
always @(posedge clkin_in )
begin
if (pwron_int == 0 && rst_in == 0)
clkfb_tst <= 1'b1;
else
clkfb_tst <= 1'b0;
end
always @( posedge clkfb_tst or posedge rst_in )
if (rst_in)
delay_edge <= 0;
else
delay_edge <= $time;
always @(posedge clkfb_in or posedge rst_in )
if (rst_in) begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
else
if (fb_delay_found_tmp ==0 ) begin
if ( delay_edge != 0)
fb_delay <= ($time - delay_edge);
else
fb_delay <= 0;
fb_delay_found_tmp <= 1;
end
always @(rst_in)
if (rst_in)
assign fb_delay_found = 0;
else
deassign fb_delay_found;
always @(fb_delay_found_tmp or clkvco_delay )
if (clkvco_delay == 0)
fb_delay_found <= #1000 fb_delay_found_tmp;
else
fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp;
always @(fb_delay)
if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning : The feedback delay on PLLE3_ADV instance %m at time %t is %f ns. It is over the maximum value %f ns.", $time, fb_delay / 1000.0, fb_delay_max);
end
always @(fb_delay_found_tmp)
fb_delay_found <= #1000 fb_delay_found_tmp;
always @(period_avg or clkind_div or clkfbm1_div)
begin
if (period_avg > 0 )
begin
md_product = clkind_div * clkfbm1_div;
m_product = clkfbm1_div;
m_product2 = clkfbm1_div / 2;
period_fb = period_avg * clkind_div;
period_vco = period_fb / clkfbm1_div;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco_mf = period_avg * 8;
period_vco_rm = period_fb % clkfbm1_div;
if (period_vco_rm > 1)
begin
if (period_vco_rm > m_product2)
begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else
begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbm1_div;
clkin_dly_t = period_avg * (clkind_div + 1.25);
end
end
always @( clkin_in ) // Why these delays?
clkpll_tmp1 <= #(period_avg) clkin_in;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(clkvco or clkvco_lk_tmp or rst_in)
begin
if (rst_in)
clkvco = 0;
else
clkvco = clkvco_lk_tmp;
end
// Xiphy clocks
always @(posedge clkvco or negedge clkvco or posedge rst_in or negedge xiphyen_sync)
begin
if (!xiphyen_sync || rst_in)
clkvco_2x <= 0;
else
begin
clkvco_2x <= 1;
#(period_vco/ 4)
clkvco_2x <= 0;
end
end
always @(posedge clkvco or posedge rst_in)
begin
if (!xiphyen_sync || rst_in)
clkvco_by2 <= 0;
else
clkvco_by2 <= ~clkvco_by2;
end
always @(posedge clkvco or posedge rst_in)
begin
if (rst_in) begin
clkvco_by8 <= 1'b0;
clkvco_cnt <= 3'b0;
end
else if (clkout_en) begin
if (clkvco_cnt == 3'b0) clkvco_by8 <= ~clkvco_by8;
clkvco_cnt <= clkvco_cnt + 3'b001;
end
end
always @(negedge clkvco_by8 or posedge rst_in) begin
if (rst_in) begin
xiphyen_sync1 <= 1'b0;
xiphyen_sync2 <= 1'b0;
end
else begin
xiphyen_sync1 <= xiphyen_in;
xiphyen_sync2 <= xiphyen_sync1;
end
end
always @(negedge clkvco or posedge rst_in) begin
if (rst_in) begin
xiphyen_sync <= 1'b0;
end
else if (clkvco_cnt == 3'b0) begin
xiphyen_sync <= xiphyen_sync2;
end
end
// VCO clock generation
always @(posedge clkpll)
begin
if (pll_locked_tm ==1)
begin
clkvco_lk_tmp <= 1;
clkvco_rm_cnt = 0;
clkout_en_t <= 0;
vcoflag = 0;
if ( period_vco_cmp_flag == 1)
begin
for (ik2=1; ik2 < m_product; ik2=ik2+1)
begin
vcoflag = 1;
clkout_en_t <= ik2;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik2;
end
else if ( period_vco_cmp_flag == 2 )
begin
vcoflag = 1;
for (ik3=1; ik3 < m_product; ik3=ik3+1)
begin
clkout_en_t <= ik3;
#(period_vco_half) clkvco_lk_tmp <= 0;
if ( clkvco_rm_cnt == 1)
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
else
#(period_vco_half_rm1) clkvco_lk_tmp <= 1;
if ( clkvco_rm_cnt == period_vco_cmp_cnt)
clkvco_rm_cnt <= 0;
else
clkvco_rm_cnt <= clkvco_rm_cnt + 1;
end
clkout_en_t <= ik3;
end
else
begin
vcoflag = 1;
for (ik4=1; ik4 < m_product; ik4=ik4+1)
begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
end
#(period_vco_half) clkvco_lk_tmp <= 0;
if (clkpll == 1 && m_product > 1 && m_product != clkind_div && vcoflag == 0)
begin
for (ik4=1; ik4 < m_product; ik4=ik4+1)
begin
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
#(period_vco_half_rm) clkvco_lk_tmp <= 1;
end
clkout_en_t <= ik4;
#(period_vco_half) clkvco_lk_tmp <= 0;
end
end
end
always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or lock_period)
begin
if (lock_period == 1)
begin
val_tmp = period_avg * DIVCLK_DIVIDE;
fbm1_comp_delay = period_vco * clkfbm1_dly;
end
dly_tmp1 = fb_delay + fbm1_comp_delay;
dly_tmp_int = 1;
dly_tmp = dly_tmp1;
if (dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
always @(clkvco)
begin
if (clkout_en)
begin
clkout_mux[0] = clkvco;
clkout_mux[1] <= clkvco;
clkout_mux[2] <= clkvco;
end
end
assign clk0in = clkout_mux[0];
assign clk1in = clkout_mux[1];
assign clkfbm1in = clkout_mux[2];
assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0;
assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0;
assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0;
always @(negedge clk0in or posedge rst_in)
begin
if (rst_in)
clk0_dly_cnt <= 6'b0;
else
if (clk0_dly_cnt < clkout0_dly && clkout_en == 1)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in)
begin
if (rst_in)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clkout1_dly && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
end
always @(negedge clkfbm1in or posedge rst_in)
begin
if (rst_in)
clkfbm1_dly_cnt <= 6'b0;
else
if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en == 1)
clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
end
always @(clk0_out or clkfb_tst or fb_delay_found or rst_in)
begin
if (fb_delay_found == 1)
clkout0_out = clk0_out;
else
if(rst_in == 1'b0)
clkout0_out = clkfb_tst;
end
always @(clk1_out or clkfb_tst or fb_delay_found or rst_in)
begin
if (fb_delay_found == 1)
clkout1_out = clk1_out;
else
if(rst_in == 1'b0)
clkout1_out = clkfb_tst;
end
always @(clkfbm1_out or clkfb_tst or fb_delay_found or rst_in)
begin
if (fb_delay_found == 1)
clkfb_out = clkfbm1_out;
else
if(rst_in == 1'b0)
clkfb_out = clkfb_tst;
end
// Generate unlock signal
always begin
if (rst_in)
clk_osc = 0;
else
clk_osc = ~clk_osc;
#OSC_P2;
end
always @(posedge clkpll or negedge clkpll) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge clkfb_in or negedge clkfb_in) begin
clkfb_p <= 1;
clkfb_p <= #100 0;
end
always @(posedge clk_osc or posedge rst_in or posedge clkin_p)
begin
if (rst_in == 1) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out == 1) begin
@(posedge clkpll) begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out <= 0;
end
else
clkinstopped_out <= 1;
end
end
always @(posedge clkinstopped_out or posedge rst_in)
begin
if (rst_in);
else begin
$display(" Warning : input CLKIN of PLLE3_ADV on instance %m is stopped. Reset is required for PLLE3_ADV when input clock returns.");
end
end
always @(posedge clk_osc or posedge rst_in or posedge clkfb_p)
begin
if (rst_in == 1 || clkfb_p == 1) begin
clkfbstopped_out <= 0;
clkfb_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfb_lost_cnt < clkfb_lost_val) begin
clkfb_lost_cnt <= clkfb_lost_cnt + 1;
clkfbstopped_out <= 0;
end
else
clkfbstopped_out <= 1;
end
end
always @(clkin_jit or rst_in )
begin
if (rst_in)
clkpll_jitter_unlock = 0;
else
begin
if (pll_locked_tmp2)
begin
if ((clkin_jit > REF_CLK_JITTER_MAX && clkin_jit < period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX && clkin_jit > -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
end
end
assign pll_unlock1 = (clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = ( clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// Generate lock signal
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
begin
if (clkout_en0_tmp==0 )
clkout_en0 <= 0;
else
begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #(period_vco-1) clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in )
if (rst_in)
clkout_en <= 0;
else
clkout_en <= clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 <= pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_in)
if (rst_in) begin
assign pll_locked_tmp2 = 0;
assign clkout_en0 = 0;
end
else begin
deassign pll_locked_tmp2;
deassign clkout_en0;
end
assign locked_out = (pll_locked_tm && pll_locked_tmp2_dly && ~pll_unlock && !unlock_recover) ? 1 : 0;
always @(rst_in or locked_out)
if (rst_in == 1)
locked_out_tmp <= #1000 0;
else
locked_out_tmp <= locked_out;
// end of lock
always @(posedge clk0in or negedge clk0in or posedge rst_in)
begin
if (rst_in)
begin
clk0_cnt <= 9'b0;
clk0_out <= 0;
end
else if (clk0ps_en)
begin
begin
if (clk0_cnt < clk0_div1)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 9'b0;
if (clk0_cnt < clk0_ht1)
clk0_out <= 1;
else
clk0_out <= 0;
end
end
end
always @(posedge clk1in or negedge clk1in or posedge rst_in)
begin
if (rst_in)
begin
clk1_cnt <= 9'b0;
clk1_out <= 0;
end
else if (clk1ps_en)
begin
if (clk1_cnt < clk1_div1)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 9'b0;
if (clk1_cnt < clk1_ht1)
clk1_out <= 1;
else
clk1_out <= 0;
end
end
always @(posedge clkpll or negedge clkpll or posedge rst_in)
begin
if (rst_in) begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
else if (clkout_en)
begin
if (clkind_cnt < clkind_div1)
clkind_cnt <= clkind_cnt + 1;
else
clkind_cnt <= 8'b0;
if (clkind_cnt < clkind_ht1)
clkind_out <= 1;
else
clkind_out <= 0;
end
else begin
clkind_cnt <= 8'b0;
clkind_out <= 0;
end
end
always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in)
begin
if (rst_in) begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
else if (clkfbm1ps_en)
begin
if (clkfbm1_cnt < clkfbm1_div1)
clkfbm1_cnt <= clkfbm1_cnt + 1;
else
clkfbm1_cnt <= 8'b0;
if (clkfbm1_cnt < clkfbm1_ht1)
clkfbm1_nf_out <= 1;
else
clkfbm1_nf_out <= 0;
end
else
begin
clkfbm1_cnt <= 8'b0;
clkfbm1_nf_out <= 0;
end
end
assign clkfbm1_out = clkfbm1_nf_out;
always @(posedge clkfb_in or negedge clkfb_in or posedge rst_in)
begin
if (rst_in) begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
else if (clkout_en) begin
if (clkfbm2_cnt < clkfbm2_div1)
clkfbm2_cnt <= clkfbm2_cnt + 1;
else
clkfbm2_cnt <= 8'b0;
if (clkfbm2_cnt < clkfbm2_ht1)
clkfbm2_out <= 1;
else
clkfbm2_out <= 0;
end
else begin
clkfbm2_cnt <= 8'b0;
clkfbm2_out <= 0;
end
end
// Phase task
task clkout_dly_cal;
output [5:0] clkout_dly;
input clkdiv;
input clk_ps;
input reg [160:0] clk_ps_name;
integer clkdiv;
real clk_ps;
real clk_ps_rl;
real clk_dly_rl, clk_dly_rem;
integer clkout_dly_tmp;
begin
if (clk_ps < 0.0)
clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0;
else
clk_dly_rl = clk_ps * clkdiv / 360.0;
//clkout_dly_tmp = $rtoi(clk_dly_rl);
clkout_dly_tmp = clk_dly_rl;
if (clkout_dly_tmp > 63) begin
$display(" Warning : Attribute %s of %s on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of %s", clk_ps_name, MODULE_NAME, clk_ps, MODULE_NAME);
clkout_dly = 6'b111111;
end
else
clkout_dly = clkout_dly_tmp;
end
endtask
// Task to calculate final ht based on clk_edge
task clkout_pm_cal;
output [8:0] clk_ht1;
output [8:0] clk_div;
output [8:0] clk_div1;
input [7:0] clk_ht;
input [7:0] clk_lt;
input clk_nocnt;
input clk_edge;
begin
if (clk_nocnt ==1) begin
clk_div = 9'b000000001;
clk_div1 = 9'b000000001;
clk_ht1 = 9'b000000001;
end
else begin
if ( clk_edge == 1)
clk_ht1 = 2 * clk_ht + 1;
else
clk_ht1 = 2 * clk_ht;
clk_div = clk_ht + clk_lt ;
clk_div1 = 2 * clk_div -1;
end
end
endtask
// Task to calculate ht, lt based on duty cycle
// also detects of clk_edge needs to be 1
task clk_out_para_cal;
output [7:0] clk_ht;
output [7:0] clk_lt;
output clk_nocnt;
output clk_edge;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
integer CLKOUT_DIVIDE;
real CLKOUT_DUTY_CYCLE;
real tmp_value, tmp_value0, tmp_value_rm;
integer tmp_value_round, tmp_value1, tmp_value_r;
real tmp_value2;
real tmp_value_rm1, tmp_value_r1;
integer tmp_value_r2;
begin
tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE;
tmp_value_r = $rtoi(tmp_value0);
tmp_value_rm = tmp_value0 - tmp_value_r;
if (tmp_value_rm < 0.1)
tmp_value = tmp_value_r * 1.0;
else if (tmp_value_rm > 0.9)
tmp_value = 1.0 * tmp_value_r + 1.0;
else begin
tmp_value_r1 = tmp_value0 * 2.0;
tmp_value_r2 = $rtoi(tmp_value_r1);
tmp_value_rm1 = tmp_value_r1 - tmp_value_r2;
if (tmp_value_rm1 > 0.995)
tmp_value = tmp_value0 + 0.002;
else
tmp_value = tmp_value0;
end
tmp_value_round = tmp_value * 2.0;
tmp_value1 = tmp_value_round % 2;
tmp_value2 = CLKOUT_DIVIDE - tmp_value;
if ((tmp_value2) >= O_MAX_HT_LT) begin
clk_lt = 8'b10000000;
end
else begin
if (tmp_value2 < 1.0)
clk_lt = 1;
else
if ( tmp_value1 != 0)
clk_lt = $rtoi(tmp_value2) + 1;
else
clk_lt = $rtoi(tmp_value2);
end
if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT)
clk_ht = 8'b10000000;
else
clk_ht = CLKOUT_DIVIDE - clk_lt;
clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0;
if ( tmp_value < 1.0)
clk_edge = 1;
else if (tmp_value1 != 0)
clk_edge = 1;
else
clk_edge = 0;
end
endtask
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.5;
CLK_DUTY_CYCLE_MIN_rnd = 0.5;
CLK_DUTY_CYCLE_MAX = 0.5;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (CLKOUT_DIVIDE - 0.5)/ CLKOUT_DIVIDE;
end
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
end
clkout_duty_chk = 1'b1;
end
endfunction
task clkout_delay_para_drp;
output [5:0] clkout_dly;
output clk_nocnt;
output clk_edge;
input [15:0] di_in;
input [6:0] daddr_in;
begin
clkout_dly = di_in[5:0];
clk_nocnt = di_in[6];
clk_edge = di_in[7];
end
endtask
task clkout_hl_para_drp;
output [6:0] clk_lt;
output [6:0] clk_ht;
input [15:0] di_in_tmp;
input [6:0] daddr_in_tmp;
begin
// if (di_in_tmp[12] != 1) begin
// $display(" Error : PLLE3_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time);
// end
if ( di_in_tmp[5:0] == 6'b0)
clk_lt = 7'b1000000;
else
clk_lt = { 1'b0, di_in_tmp[5:0]};
if (di_in_tmp[11:6] == 6'b0)
clk_ht = 7'b1000000;
else
clk_ht = { 1'b0, di_in_tmp[11:6]};
end
endtask
specify
(CLKIN => CLKFBOUT) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT0) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT0B) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT1) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT1B) = (0:0:0, 0:0:0);
(CLKIN => CLKOUTPHY) = (0:0:0, 0:0:0);
(DCLK *> DO) = (0:0:0, 0:0:0);
(DCLK => DRDY) = (0:0:0, 0:0:0);
(RST => LOCKED) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKIN, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUTPHY, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUTPHY, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PLLE3_BASE.v 0000664 0000000 0000000 00000011247 12327044266 0023040 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : PLLE3_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE3_BASE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUTPHY_MODE = "VCO_2X",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUTPHY,
output LOCKED,
input CLKFBIN,
input CLKIN,
input CLKOUTPHYEN,
input PWRDWN,
input RST
);
localparam MODULE_NAME = "PLLE3_BASE";
`ifdef XIL_TIMING
reg notifier;
`endif
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE3_ADV #(
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN_PERIOD(CLKIN_PERIOD),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUTPHY_MODE(CLKOUTPHY_MODE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.IS_CLKFBIN_INVERTED(IS_CLKFBIN_INVERTED),
.IS_CLKIN_INVERTED(IS_CLKIN_INVERTED),
.IS_PWRDWN_INVERTED(IS_PWRDWN_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.REF_JITTER(REF_JITTER),
.STARTUP_WAIT(STARTUP_WAIT)
)
plle3_base_1 (
.CLKFBIN (CLKFBIN),
.CLKIN (CLKIN),
.CLKFBOUT (CLKFBOUT),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUTPHY (CLKOUTPHY),
.CLKOUTPHYEN (CLKOUTPHYEN),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.PWRDWN(PWRDWN),
.RST (RST)
);
specify
(CLKIN => CLKFBOUT) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT0) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT0B) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT1) = (0:0:0, 0:0:0);
(CLKIN => CLKOUT1B) = (0:0:0, 0:0:0);
(CLKIN => CLKOUTPHY) = (0:0:0, 0:0:0);
(RST => LOCKED) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKIN, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUTPHY, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUTPHY, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PS7.v 0000664 0000000 0000000 00000066460 12327044266 0022047 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/pele/PS7.v,v 1.1 2010/12/01 17:42:20 harikr Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description :
// / /
// /__/ /\ Filename : PS7.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 04/15/2013 - sync up with ISE
// 05/13/13 - 717829 - Add simulation message
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PS7 (
DMA0DATYPE,
DMA0DAVALID,
DMA0DRREADY,
DMA0RSTN,
DMA1DATYPE,
DMA1DAVALID,
DMA1DRREADY,
DMA1RSTN,
DMA2DATYPE,
DMA2DAVALID,
DMA2DRREADY,
DMA2RSTN,
DMA3DATYPE,
DMA3DAVALID,
DMA3DRREADY,
DMA3RSTN,
EMIOCAN0PHYTX,
EMIOCAN1PHYTX,
EMIOENET0GMIITXD,
EMIOENET0GMIITXEN,
EMIOENET0GMIITXER,
EMIOENET0MDIOMDC,
EMIOENET0MDIOO,
EMIOENET0MDIOTN,
EMIOENET0PTPDELAYREQRX,
EMIOENET0PTPDELAYREQTX,
EMIOENET0PTPPDELAYREQRX,
EMIOENET0PTPPDELAYREQTX,
EMIOENET0PTPPDELAYRESPRX,
EMIOENET0PTPPDELAYRESPTX,
EMIOENET0PTPSYNCFRAMERX,
EMIOENET0PTPSYNCFRAMETX,
EMIOENET0SOFRX,
EMIOENET0SOFTX,
EMIOENET1GMIITXD,
EMIOENET1GMIITXEN,
EMIOENET1GMIITXER,
EMIOENET1MDIOMDC,
EMIOENET1MDIOO,
EMIOENET1MDIOTN,
EMIOENET1PTPDELAYREQRX,
EMIOENET1PTPDELAYREQTX,
EMIOENET1PTPPDELAYREQRX,
EMIOENET1PTPPDELAYREQTX,
EMIOENET1PTPPDELAYRESPRX,
EMIOENET1PTPPDELAYRESPTX,
EMIOENET1PTPSYNCFRAMERX,
EMIOENET1PTPSYNCFRAMETX,
EMIOENET1SOFRX,
EMIOENET1SOFTX,
EMIOGPIOO,
EMIOGPIOTN,
EMIOI2C0SCLO,
EMIOI2C0SCLTN,
EMIOI2C0SDAO,
EMIOI2C0SDATN,
EMIOI2C1SCLO,
EMIOI2C1SCLTN,
EMIOI2C1SDAO,
EMIOI2C1SDATN,
EMIOPJTAGTDO,
EMIOPJTAGTDTN,
EMIOSDIO0BUSPOW,
EMIOSDIO0BUSVOLT,
EMIOSDIO0CLK,
EMIOSDIO0CMDO,
EMIOSDIO0CMDTN,
EMIOSDIO0DATAO,
EMIOSDIO0DATATN,
EMIOSDIO0LED,
EMIOSDIO1BUSPOW,
EMIOSDIO1BUSVOLT,
EMIOSDIO1CLK,
EMIOSDIO1CMDO,
EMIOSDIO1CMDTN,
EMIOSDIO1DATAO,
EMIOSDIO1DATATN,
EMIOSDIO1LED,
EMIOSPI0MO,
EMIOSPI0MOTN,
EMIOSPI0SCLKO,
EMIOSPI0SCLKTN,
EMIOSPI0SO,
EMIOSPI0SSNTN,
EMIOSPI0SSON,
EMIOSPI0STN,
EMIOSPI1MO,
EMIOSPI1MOTN,
EMIOSPI1SCLKO,
EMIOSPI1SCLKTN,
EMIOSPI1SO,
EMIOSPI1SSNTN,
EMIOSPI1SSON,
EMIOSPI1STN,
EMIOTRACECTL,
EMIOTRACEDATA,
EMIOTTC0WAVEO,
EMIOTTC1WAVEO,
EMIOUART0DTRN,
EMIOUART0RTSN,
EMIOUART0TX,
EMIOUART1DTRN,
EMIOUART1RTSN,
EMIOUART1TX,
EMIOUSB0PORTINDCTL,
EMIOUSB0VBUSPWRSELECT,
EMIOUSB1PORTINDCTL,
EMIOUSB1VBUSPWRSELECT,
EMIOWDTRSTO,
EVENTEVENTO,
EVENTSTANDBYWFE,
EVENTSTANDBYWFI,
FCLKCLK,
FCLKRESETN,
FTMTF2PTRIGACK,
FTMTP2FDEBUG,
FTMTP2FTRIG,
IRQP2F,
MAXIGP0ARADDR,
MAXIGP0ARBURST,
MAXIGP0ARCACHE,
MAXIGP0ARESETN,
MAXIGP0ARID,
MAXIGP0ARLEN,
MAXIGP0ARLOCK,
MAXIGP0ARPROT,
MAXIGP0ARQOS,
MAXIGP0ARSIZE,
MAXIGP0ARVALID,
MAXIGP0AWADDR,
MAXIGP0AWBURST,
MAXIGP0AWCACHE,
MAXIGP0AWID,
MAXIGP0AWLEN,
MAXIGP0AWLOCK,
MAXIGP0AWPROT,
MAXIGP0AWQOS,
MAXIGP0AWSIZE,
MAXIGP0AWVALID,
MAXIGP0BREADY,
MAXIGP0RREADY,
MAXIGP0WDATA,
MAXIGP0WID,
MAXIGP0WLAST,
MAXIGP0WSTRB,
MAXIGP0WVALID,
MAXIGP1ARADDR,
MAXIGP1ARBURST,
MAXIGP1ARCACHE,
MAXIGP1ARESETN,
MAXIGP1ARID,
MAXIGP1ARLEN,
MAXIGP1ARLOCK,
MAXIGP1ARPROT,
MAXIGP1ARQOS,
MAXIGP1ARSIZE,
MAXIGP1ARVALID,
MAXIGP1AWADDR,
MAXIGP1AWBURST,
MAXIGP1AWCACHE,
MAXIGP1AWID,
MAXIGP1AWLEN,
MAXIGP1AWLOCK,
MAXIGP1AWPROT,
MAXIGP1AWQOS,
MAXIGP1AWSIZE,
MAXIGP1AWVALID,
MAXIGP1BREADY,
MAXIGP1RREADY,
MAXIGP1WDATA,
MAXIGP1WID,
MAXIGP1WLAST,
MAXIGP1WSTRB,
MAXIGP1WVALID,
SAXIACPARESETN,
SAXIACPARREADY,
SAXIACPAWREADY,
SAXIACPBID,
SAXIACPBRESP,
SAXIACPBVALID,
SAXIACPRDATA,
SAXIACPRID,
SAXIACPRLAST,
SAXIACPRRESP,
SAXIACPRVALID,
SAXIACPWREADY,
SAXIGP0ARESETN,
SAXIGP0ARREADY,
SAXIGP0AWREADY,
SAXIGP0BID,
SAXIGP0BRESP,
SAXIGP0BVALID,
SAXIGP0RDATA,
SAXIGP0RID,
SAXIGP0RLAST,
SAXIGP0RRESP,
SAXIGP0RVALID,
SAXIGP0WREADY,
SAXIGP1ARESETN,
SAXIGP1ARREADY,
SAXIGP1AWREADY,
SAXIGP1BID,
SAXIGP1BRESP,
SAXIGP1BVALID,
SAXIGP1RDATA,
SAXIGP1RID,
SAXIGP1RLAST,
SAXIGP1RRESP,
SAXIGP1RVALID,
SAXIGP1WREADY,
SAXIHP0ARESETN,
SAXIHP0ARREADY,
SAXIHP0AWREADY,
SAXIHP0BID,
SAXIHP0BRESP,
SAXIHP0BVALID,
SAXIHP0RACOUNT,
SAXIHP0RCOUNT,
SAXIHP0RDATA,
SAXIHP0RID,
SAXIHP0RLAST,
SAXIHP0RRESP,
SAXIHP0RVALID,
SAXIHP0WACOUNT,
SAXIHP0WCOUNT,
SAXIHP0WREADY,
SAXIHP1ARESETN,
SAXIHP1ARREADY,
SAXIHP1AWREADY,
SAXIHP1BID,
SAXIHP1BRESP,
SAXIHP1BVALID,
SAXIHP1RACOUNT,
SAXIHP1RCOUNT,
SAXIHP1RDATA,
SAXIHP1RID,
SAXIHP1RLAST,
SAXIHP1RRESP,
SAXIHP1RVALID,
SAXIHP1WACOUNT,
SAXIHP1WCOUNT,
SAXIHP1WREADY,
SAXIHP2ARESETN,
SAXIHP2ARREADY,
SAXIHP2AWREADY,
SAXIHP2BID,
SAXIHP2BRESP,
SAXIHP2BVALID,
SAXIHP2RACOUNT,
SAXIHP2RCOUNT,
SAXIHP2RDATA,
SAXIHP2RID,
SAXIHP2RLAST,
SAXIHP2RRESP,
SAXIHP2RVALID,
SAXIHP2WACOUNT,
SAXIHP2WCOUNT,
SAXIHP2WREADY,
SAXIHP3ARESETN,
SAXIHP3ARREADY,
SAXIHP3AWREADY,
SAXIHP3BID,
SAXIHP3BRESP,
SAXIHP3BVALID,
SAXIHP3RACOUNT,
SAXIHP3RCOUNT,
SAXIHP3RDATA,
SAXIHP3RID,
SAXIHP3RLAST,
SAXIHP3RRESP,
SAXIHP3RVALID,
SAXIHP3WACOUNT,
SAXIHP3WCOUNT,
SAXIHP3WREADY,
DDRA,
DDRBA,
DDRCASB,
DDRCKE,
DDRCKN,
DDRCKP,
DDRCSB,
DDRDM,
DDRDQ,
DDRDQSN,
DDRDQSP,
DDRDRSTB,
DDRODT,
DDRRASB,
DDRVRN,
DDRVRP,
DDRWEB,
MIO,
PSCLK,
PSPORB,
PSSRSTB,
DDRARB,
DMA0ACLK,
DMA0DAREADY,
DMA0DRLAST,
DMA0DRTYPE,
DMA0DRVALID,
DMA1ACLK,
DMA1DAREADY,
DMA1DRLAST,
DMA1DRTYPE,
DMA1DRVALID,
DMA2ACLK,
DMA2DAREADY,
DMA2DRLAST,
DMA2DRTYPE,
DMA2DRVALID,
DMA3ACLK,
DMA3DAREADY,
DMA3DRLAST,
DMA3DRTYPE,
DMA3DRVALID,
EMIOCAN0PHYRX,
EMIOCAN1PHYRX,
EMIOENET0EXTINTIN,
EMIOENET0GMIICOL,
EMIOENET0GMIICRS,
EMIOENET0GMIIRXCLK,
EMIOENET0GMIIRXD,
EMIOENET0GMIIRXDV,
EMIOENET0GMIIRXER,
EMIOENET0GMIITXCLK,
EMIOENET0MDIOI,
EMIOENET1EXTINTIN,
EMIOENET1GMIICOL,
EMIOENET1GMIICRS,
EMIOENET1GMIIRXCLK,
EMIOENET1GMIIRXD,
EMIOENET1GMIIRXDV,
EMIOENET1GMIIRXER,
EMIOENET1GMIITXCLK,
EMIOENET1MDIOI,
EMIOGPIOI,
EMIOI2C0SCLI,
EMIOI2C0SDAI,
EMIOI2C1SCLI,
EMIOI2C1SDAI,
EMIOPJTAGTCK,
EMIOPJTAGTDI,
EMIOPJTAGTMS,
EMIOSDIO0CDN,
EMIOSDIO0CLKFB,
EMIOSDIO0CMDI,
EMIOSDIO0DATAI,
EMIOSDIO0WP,
EMIOSDIO1CDN,
EMIOSDIO1CLKFB,
EMIOSDIO1CMDI,
EMIOSDIO1DATAI,
EMIOSDIO1WP,
EMIOSPI0MI,
EMIOSPI0SCLKI,
EMIOSPI0SI,
EMIOSPI0SSIN,
EMIOSPI1MI,
EMIOSPI1SCLKI,
EMIOSPI1SI,
EMIOSPI1SSIN,
EMIOSRAMINTIN,
EMIOTRACECLK,
EMIOTTC0CLKI,
EMIOTTC1CLKI,
EMIOUART0CTSN,
EMIOUART0DCDN,
EMIOUART0DSRN,
EMIOUART0RIN,
EMIOUART0RX,
EMIOUART1CTSN,
EMIOUART1DCDN,
EMIOUART1DSRN,
EMIOUART1RIN,
EMIOUART1RX,
EMIOUSB0VBUSPWRFAULT,
EMIOUSB1VBUSPWRFAULT,
EMIOWDTCLKI,
EVENTEVENTI,
FCLKCLKTRIGN,
FPGAIDLEN,
FTMDTRACEINATID,
FTMDTRACEINCLOCK,
FTMDTRACEINDATA,
FTMDTRACEINVALID,
FTMTF2PDEBUG,
FTMTF2PTRIG,
FTMTP2FTRIGACK,
IRQF2P,
MAXIGP0ACLK,
MAXIGP0ARREADY,
MAXIGP0AWREADY,
MAXIGP0BID,
MAXIGP0BRESP,
MAXIGP0BVALID,
MAXIGP0RDATA,
MAXIGP0RID,
MAXIGP0RLAST,
MAXIGP0RRESP,
MAXIGP0RVALID,
MAXIGP0WREADY,
MAXIGP1ACLK,
MAXIGP1ARREADY,
MAXIGP1AWREADY,
MAXIGP1BID,
MAXIGP1BRESP,
MAXIGP1BVALID,
MAXIGP1RDATA,
MAXIGP1RID,
MAXIGP1RLAST,
MAXIGP1RRESP,
MAXIGP1RVALID,
MAXIGP1WREADY,
SAXIACPACLK,
SAXIACPARADDR,
SAXIACPARBURST,
SAXIACPARCACHE,
SAXIACPARID,
SAXIACPARLEN,
SAXIACPARLOCK,
SAXIACPARPROT,
SAXIACPARQOS,
SAXIACPARSIZE,
SAXIACPARUSER,
SAXIACPARVALID,
SAXIACPAWADDR,
SAXIACPAWBURST,
SAXIACPAWCACHE,
SAXIACPAWID,
SAXIACPAWLEN,
SAXIACPAWLOCK,
SAXIACPAWPROT,
SAXIACPAWQOS,
SAXIACPAWSIZE,
SAXIACPAWUSER,
SAXIACPAWVALID,
SAXIACPBREADY,
SAXIACPRREADY,
SAXIACPWDATA,
SAXIACPWID,
SAXIACPWLAST,
SAXIACPWSTRB,
SAXIACPWVALID,
SAXIGP0ACLK,
SAXIGP0ARADDR,
SAXIGP0ARBURST,
SAXIGP0ARCACHE,
SAXIGP0ARID,
SAXIGP0ARLEN,
SAXIGP0ARLOCK,
SAXIGP0ARPROT,
SAXIGP0ARQOS,
SAXIGP0ARSIZE,
SAXIGP0ARVALID,
SAXIGP0AWADDR,
SAXIGP0AWBURST,
SAXIGP0AWCACHE,
SAXIGP0AWID,
SAXIGP0AWLEN,
SAXIGP0AWLOCK,
SAXIGP0AWPROT,
SAXIGP0AWQOS,
SAXIGP0AWSIZE,
SAXIGP0AWVALID,
SAXIGP0BREADY,
SAXIGP0RREADY,
SAXIGP0WDATA,
SAXIGP0WID,
SAXIGP0WLAST,
SAXIGP0WSTRB,
SAXIGP0WVALID,
SAXIGP1ACLK,
SAXIGP1ARADDR,
SAXIGP1ARBURST,
SAXIGP1ARCACHE,
SAXIGP1ARID,
SAXIGP1ARLEN,
SAXIGP1ARLOCK,
SAXIGP1ARPROT,
SAXIGP1ARQOS,
SAXIGP1ARSIZE,
SAXIGP1ARVALID,
SAXIGP1AWADDR,
SAXIGP1AWBURST,
SAXIGP1AWCACHE,
SAXIGP1AWID,
SAXIGP1AWLEN,
SAXIGP1AWLOCK,
SAXIGP1AWPROT,
SAXIGP1AWQOS,
SAXIGP1AWSIZE,
SAXIGP1AWVALID,
SAXIGP1BREADY,
SAXIGP1RREADY,
SAXIGP1WDATA,
SAXIGP1WID,
SAXIGP1WLAST,
SAXIGP1WSTRB,
SAXIGP1WVALID,
SAXIHP0ACLK,
SAXIHP0ARADDR,
SAXIHP0ARBURST,
SAXIHP0ARCACHE,
SAXIHP0ARID,
SAXIHP0ARLEN,
SAXIHP0ARLOCK,
SAXIHP0ARPROT,
SAXIHP0ARQOS,
SAXIHP0ARSIZE,
SAXIHP0ARVALID,
SAXIHP0AWADDR,
SAXIHP0AWBURST,
SAXIHP0AWCACHE,
SAXIHP0AWID,
SAXIHP0AWLEN,
SAXIHP0AWLOCK,
SAXIHP0AWPROT,
SAXIHP0AWQOS,
SAXIHP0AWSIZE,
SAXIHP0AWVALID,
SAXIHP0BREADY,
SAXIHP0RDISSUECAP1EN,
SAXIHP0RREADY,
SAXIHP0WDATA,
SAXIHP0WID,
SAXIHP0WLAST,
SAXIHP0WRISSUECAP1EN,
SAXIHP0WSTRB,
SAXIHP0WVALID,
SAXIHP1ACLK,
SAXIHP1ARADDR,
SAXIHP1ARBURST,
SAXIHP1ARCACHE,
SAXIHP1ARID,
SAXIHP1ARLEN,
SAXIHP1ARLOCK,
SAXIHP1ARPROT,
SAXIHP1ARQOS,
SAXIHP1ARSIZE,
SAXIHP1ARVALID,
SAXIHP1AWADDR,
SAXIHP1AWBURST,
SAXIHP1AWCACHE,
SAXIHP1AWID,
SAXIHP1AWLEN,
SAXIHP1AWLOCK,
SAXIHP1AWPROT,
SAXIHP1AWQOS,
SAXIHP1AWSIZE,
SAXIHP1AWVALID,
SAXIHP1BREADY,
SAXIHP1RDISSUECAP1EN,
SAXIHP1RREADY,
SAXIHP1WDATA,
SAXIHP1WID,
SAXIHP1WLAST,
SAXIHP1WRISSUECAP1EN,
SAXIHP1WSTRB,
SAXIHP1WVALID,
SAXIHP2ACLK,
SAXIHP2ARADDR,
SAXIHP2ARBURST,
SAXIHP2ARCACHE,
SAXIHP2ARID,
SAXIHP2ARLEN,
SAXIHP2ARLOCK,
SAXIHP2ARPROT,
SAXIHP2ARQOS,
SAXIHP2ARSIZE,
SAXIHP2ARVALID,
SAXIHP2AWADDR,
SAXIHP2AWBURST,
SAXIHP2AWCACHE,
SAXIHP2AWID,
SAXIHP2AWLEN,
SAXIHP2AWLOCK,
SAXIHP2AWPROT,
SAXIHP2AWQOS,
SAXIHP2AWSIZE,
SAXIHP2AWVALID,
SAXIHP2BREADY,
SAXIHP2RDISSUECAP1EN,
SAXIHP2RREADY,
SAXIHP2WDATA,
SAXIHP2WID,
SAXIHP2WLAST,
SAXIHP2WRISSUECAP1EN,
SAXIHP2WSTRB,
SAXIHP2WVALID,
SAXIHP3ACLK,
SAXIHP3ARADDR,
SAXIHP3ARBURST,
SAXIHP3ARCACHE,
SAXIHP3ARID,
SAXIHP3ARLEN,
SAXIHP3ARLOCK,
SAXIHP3ARPROT,
SAXIHP3ARQOS,
SAXIHP3ARSIZE,
SAXIHP3ARVALID,
SAXIHP3AWADDR,
SAXIHP3AWBURST,
SAXIHP3AWCACHE,
SAXIHP3AWID,
SAXIHP3AWLEN,
SAXIHP3AWLOCK,
SAXIHP3AWPROT,
SAXIHP3AWQOS,
SAXIHP3AWSIZE,
SAXIHP3AWVALID,
SAXIHP3BREADY,
SAXIHP3RDISSUECAP1EN,
SAXIHP3RREADY,
SAXIHP3WDATA,
SAXIHP3WID,
SAXIHP3WLAST,
SAXIHP3WRISSUECAP1EN,
SAXIHP3WSTRB,
SAXIHP3WVALID
);
output DMA0DAVALID;
output DMA0DRREADY;
output DMA0RSTN;
output DMA1DAVALID;
output DMA1DRREADY;
output DMA1RSTN;
output DMA2DAVALID;
output DMA2DRREADY;
output DMA2RSTN;
output DMA3DAVALID;
output DMA3DRREADY;
output DMA3RSTN;
output EMIOCAN0PHYTX;
output EMIOCAN1PHYTX;
output EMIOENET0GMIITXEN;
output EMIOENET0GMIITXER;
output EMIOENET0MDIOMDC;
output EMIOENET0MDIOO;
output EMIOENET0MDIOTN;
output EMIOENET0PTPDELAYREQRX;
output EMIOENET0PTPDELAYREQTX;
output EMIOENET0PTPPDELAYREQRX;
output EMIOENET0PTPPDELAYREQTX;
output EMIOENET0PTPPDELAYRESPRX;
output EMIOENET0PTPPDELAYRESPTX;
output EMIOENET0PTPSYNCFRAMERX;
output EMIOENET0PTPSYNCFRAMETX;
output EMIOENET0SOFRX;
output EMIOENET0SOFTX;
output EMIOENET1GMIITXEN;
output EMIOENET1GMIITXER;
output EMIOENET1MDIOMDC;
output EMIOENET1MDIOO;
output EMIOENET1MDIOTN;
output EMIOENET1PTPDELAYREQRX;
output EMIOENET1PTPDELAYREQTX;
output EMIOENET1PTPPDELAYREQRX;
output EMIOENET1PTPPDELAYREQTX;
output EMIOENET1PTPPDELAYRESPRX;
output EMIOENET1PTPPDELAYRESPTX;
output EMIOENET1PTPSYNCFRAMERX;
output EMIOENET1PTPSYNCFRAMETX;
output EMIOENET1SOFRX;
output EMIOENET1SOFTX;
output EMIOI2C0SCLO;
output EMIOI2C0SCLTN;
output EMIOI2C0SDAO;
output EMIOI2C0SDATN;
output EMIOI2C1SCLO;
output EMIOI2C1SCLTN;
output EMIOI2C1SDAO;
output EMIOI2C1SDATN;
output EMIOPJTAGTDO;
output EMIOPJTAGTDTN;
output EMIOSDIO0BUSPOW;
output EMIOSDIO0CLK;
output EMIOSDIO0CMDO;
output EMIOSDIO0CMDTN;
output EMIOSDIO0LED;
output EMIOSDIO1BUSPOW;
output EMIOSDIO1CLK;
output EMIOSDIO1CMDO;
output EMIOSDIO1CMDTN;
output EMIOSDIO1LED;
output EMIOSPI0MO;
output EMIOSPI0MOTN;
output EMIOSPI0SCLKO;
output EMIOSPI0SCLKTN;
output EMIOSPI0SO;
output EMIOSPI0SSNTN;
output EMIOSPI0STN;
output EMIOSPI1MO;
output EMIOSPI1MOTN;
output EMIOSPI1SCLKO;
output EMIOSPI1SCLKTN;
output EMIOSPI1SO;
output EMIOSPI1SSNTN;
output EMIOSPI1STN;
output EMIOTRACECTL;
output EMIOUART0DTRN;
output EMIOUART0RTSN;
output EMIOUART0TX;
output EMIOUART1DTRN;
output EMIOUART1RTSN;
output EMIOUART1TX;
output EMIOUSB0VBUSPWRSELECT;
output EMIOUSB1VBUSPWRSELECT;
output EMIOWDTRSTO;
output EVENTEVENTO;
output MAXIGP0ARESETN;
output MAXIGP0ARVALID;
output MAXIGP0AWVALID;
output MAXIGP0BREADY;
output MAXIGP0RREADY;
output MAXIGP0WLAST;
output MAXIGP0WVALID;
output MAXIGP1ARESETN;
output MAXIGP1ARVALID;
output MAXIGP1AWVALID;
output MAXIGP1BREADY;
output MAXIGP1RREADY;
output MAXIGP1WLAST;
output MAXIGP1WVALID;
output SAXIACPARESETN;
output SAXIACPARREADY;
output SAXIACPAWREADY;
output SAXIACPBVALID;
output SAXIACPRLAST;
output SAXIACPRVALID;
output SAXIACPWREADY;
output SAXIGP0ARESETN;
output SAXIGP0ARREADY;
output SAXIGP0AWREADY;
output SAXIGP0BVALID;
output SAXIGP0RLAST;
output SAXIGP0RVALID;
output SAXIGP0WREADY;
output SAXIGP1ARESETN;
output SAXIGP1ARREADY;
output SAXIGP1AWREADY;
output SAXIGP1BVALID;
output SAXIGP1RLAST;
output SAXIGP1RVALID;
output SAXIGP1WREADY;
output SAXIHP0ARESETN;
output SAXIHP0ARREADY;
output SAXIHP0AWREADY;
output SAXIHP0BVALID;
output SAXIHP0RLAST;
output SAXIHP0RVALID;
output SAXIHP0WREADY;
output SAXIHP1ARESETN;
output SAXIHP1ARREADY;
output SAXIHP1AWREADY;
output SAXIHP1BVALID;
output SAXIHP1RLAST;
output SAXIHP1RVALID;
output SAXIHP1WREADY;
output SAXIHP2ARESETN;
output SAXIHP2ARREADY;
output SAXIHP2AWREADY;
output SAXIHP2BVALID;
output SAXIHP2RLAST;
output SAXIHP2RVALID;
output SAXIHP2WREADY;
output SAXIHP3ARESETN;
output SAXIHP3ARREADY;
output SAXIHP3AWREADY;
output SAXIHP3BVALID;
output SAXIHP3RLAST;
output SAXIHP3RVALID;
output SAXIHP3WREADY;
output [11:0] MAXIGP0ARID;
output [11:0] MAXIGP0AWID;
output [11:0] MAXIGP0WID;
output [11:0] MAXIGP1ARID;
output [11:0] MAXIGP1AWID;
output [11:0] MAXIGP1WID;
output [1:0] DMA0DATYPE;
output [1:0] DMA1DATYPE;
output [1:0] DMA2DATYPE;
output [1:0] DMA3DATYPE;
output [1:0] EMIOUSB0PORTINDCTL;
output [1:0] EMIOUSB1PORTINDCTL;
output [1:0] EVENTSTANDBYWFE;
output [1:0] EVENTSTANDBYWFI;
output [1:0] MAXIGP0ARBURST;
output [1:0] MAXIGP0ARLOCK;
output [1:0] MAXIGP0ARSIZE;
output [1:0] MAXIGP0AWBURST;
output [1:0] MAXIGP0AWLOCK;
output [1:0] MAXIGP0AWSIZE;
output [1:0] MAXIGP1ARBURST;
output [1:0] MAXIGP1ARLOCK;
output [1:0] MAXIGP1ARSIZE;
output [1:0] MAXIGP1AWBURST;
output [1:0] MAXIGP1AWLOCK;
output [1:0] MAXIGP1AWSIZE;
output [1:0] SAXIACPBRESP;
output [1:0] SAXIACPRRESP;
output [1:0] SAXIGP0BRESP;
output [1:0] SAXIGP0RRESP;
output [1:0] SAXIGP1BRESP;
output [1:0] SAXIGP1RRESP;
output [1:0] SAXIHP0BRESP;
output [1:0] SAXIHP0RRESP;
output [1:0] SAXIHP1BRESP;
output [1:0] SAXIHP1RRESP;
output [1:0] SAXIHP2BRESP;
output [1:0] SAXIHP2RRESP;
output [1:0] SAXIHP3BRESP;
output [1:0] SAXIHP3RRESP;
output [28:0] IRQP2F;
output [2:0] EMIOSDIO0BUSVOLT;
output [2:0] EMIOSDIO1BUSVOLT;
output [2:0] EMIOSPI0SSON;
output [2:0] EMIOSPI1SSON;
output [2:0] EMIOTTC0WAVEO;
output [2:0] EMIOTTC1WAVEO;
output [2:0] MAXIGP0ARPROT;
output [2:0] MAXIGP0AWPROT;
output [2:0] MAXIGP1ARPROT;
output [2:0] MAXIGP1AWPROT;
output [2:0] SAXIACPBID;
output [2:0] SAXIACPRID;
output [2:0] SAXIHP0RACOUNT;
output [2:0] SAXIHP1RACOUNT;
output [2:0] SAXIHP2RACOUNT;
output [2:0] SAXIHP3RACOUNT;
output [31:0] EMIOTRACEDATA;
output [31:0] FTMTP2FDEBUG;
output [31:0] MAXIGP0ARADDR;
output [31:0] MAXIGP0AWADDR;
output [31:0] MAXIGP0WDATA;
output [31:0] MAXIGP1ARADDR;
output [31:0] MAXIGP1AWADDR;
output [31:0] MAXIGP1WDATA;
output [31:0] SAXIGP0RDATA;
output [31:0] SAXIGP1RDATA;
output [3:0] EMIOSDIO0DATAO;
output [3:0] EMIOSDIO0DATATN;
output [3:0] EMIOSDIO1DATAO;
output [3:0] EMIOSDIO1DATATN;
output [3:0] FCLKCLK;
output [3:0] FCLKRESETN;
output [3:0] FTMTF2PTRIGACK;
output [3:0] FTMTP2FTRIG;
output [3:0] MAXIGP0ARCACHE;
output [3:0] MAXIGP0ARLEN;
output [3:0] MAXIGP0ARQOS;
output [3:0] MAXIGP0AWCACHE;
output [3:0] MAXIGP0AWLEN;
output [3:0] MAXIGP0AWQOS;
output [3:0] MAXIGP0WSTRB;
output [3:0] MAXIGP1ARCACHE;
output [3:0] MAXIGP1ARLEN;
output [3:0] MAXIGP1ARQOS;
output [3:0] MAXIGP1AWCACHE;
output [3:0] MAXIGP1AWLEN;
output [3:0] MAXIGP1AWQOS;
output [3:0] MAXIGP1WSTRB;
output [5:0] SAXIGP0BID;
output [5:0] SAXIGP0RID;
output [5:0] SAXIGP1BID;
output [5:0] SAXIGP1RID;
output [5:0] SAXIHP0BID;
output [5:0] SAXIHP0RID;
output [5:0] SAXIHP0WACOUNT;
output [5:0] SAXIHP1BID;
output [5:0] SAXIHP1RID;
output [5:0] SAXIHP1WACOUNT;
output [5:0] SAXIHP2BID;
output [5:0] SAXIHP2RID;
output [5:0] SAXIHP2WACOUNT;
output [5:0] SAXIHP3BID;
output [5:0] SAXIHP3RID;
output [5:0] SAXIHP3WACOUNT;
output [63:0] EMIOGPIOO;
output [63:0] EMIOGPIOTN;
output [63:0] SAXIACPRDATA;
output [63:0] SAXIHP0RDATA;
output [63:0] SAXIHP1RDATA;
output [63:0] SAXIHP2RDATA;
output [63:0] SAXIHP3RDATA;
output [7:0] EMIOENET0GMIITXD;
output [7:0] EMIOENET1GMIITXD;
output [7:0] SAXIHP0RCOUNT;
output [7:0] SAXIHP0WCOUNT;
output [7:0] SAXIHP1RCOUNT;
output [7:0] SAXIHP1WCOUNT;
output [7:0] SAXIHP2RCOUNT;
output [7:0] SAXIHP2WCOUNT;
output [7:0] SAXIHP3RCOUNT;
output [7:0] SAXIHP3WCOUNT;
inout DDRCASB;
inout DDRCKE;
inout DDRCKN;
inout DDRCKP;
inout DDRCSB;
inout DDRDRSTB;
inout DDRODT;
inout DDRRASB;
inout DDRVRN;
inout DDRVRP;
inout DDRWEB;
inout PSCLK;
inout PSPORB;
inout PSSRSTB;
inout [14:0] DDRA;
inout [2:0] DDRBA;
inout [31:0] DDRDQ;
inout [3:0] DDRDM;
inout [3:0] DDRDQSN;
inout [3:0] DDRDQSP;
inout [53:0] MIO;
input DMA0ACLK;
input DMA0DAREADY;
input DMA0DRLAST;
input DMA0DRVALID;
input DMA1ACLK;
input DMA1DAREADY;
input DMA1DRLAST;
input DMA1DRVALID;
input DMA2ACLK;
input DMA2DAREADY;
input DMA2DRLAST;
input DMA2DRVALID;
input DMA3ACLK;
input DMA3DAREADY;
input DMA3DRLAST;
input DMA3DRVALID;
input EMIOCAN0PHYRX;
input EMIOCAN1PHYRX;
input EMIOENET0EXTINTIN;
input EMIOENET0GMIICOL;
input EMIOENET0GMIICRS;
input EMIOENET0GMIIRXCLK;
input EMIOENET0GMIIRXDV;
input EMIOENET0GMIIRXER;
input EMIOENET0GMIITXCLK;
input EMIOENET0MDIOI;
input EMIOENET1EXTINTIN;
input EMIOENET1GMIICOL;
input EMIOENET1GMIICRS;
input EMIOENET1GMIIRXCLK;
input EMIOENET1GMIIRXDV;
input EMIOENET1GMIIRXER;
input EMIOENET1GMIITXCLK;
input EMIOENET1MDIOI;
input EMIOI2C0SCLI;
input EMIOI2C0SDAI;
input EMIOI2C1SCLI;
input EMIOI2C1SDAI;
input EMIOPJTAGTCK;
input EMIOPJTAGTDI;
input EMIOPJTAGTMS;
input EMIOSDIO0CDN;
input EMIOSDIO0CLKFB;
input EMIOSDIO0CMDI;
input EMIOSDIO0WP;
input EMIOSDIO1CDN;
input EMIOSDIO1CLKFB;
input EMIOSDIO1CMDI;
input EMIOSDIO1WP;
input EMIOSPI0MI;
input EMIOSPI0SCLKI;
input EMIOSPI0SI;
input EMIOSPI0SSIN;
input EMIOSPI1MI;
input EMIOSPI1SCLKI;
input EMIOSPI1SI;
input EMIOSPI1SSIN;
input EMIOSRAMINTIN;
input EMIOTRACECLK;
input EMIOUART0CTSN;
input EMIOUART0DCDN;
input EMIOUART0DSRN;
input EMIOUART0RIN;
input EMIOUART0RX;
input EMIOUART1CTSN;
input EMIOUART1DCDN;
input EMIOUART1DSRN;
input EMIOUART1RIN;
input EMIOUART1RX;
input EMIOUSB0VBUSPWRFAULT;
input EMIOUSB1VBUSPWRFAULT;
input EMIOWDTCLKI;
input EVENTEVENTI;
input FPGAIDLEN;
input FTMDTRACEINCLOCK;
input FTMDTRACEINVALID;
input MAXIGP0ACLK;
input MAXIGP0ARREADY;
input MAXIGP0AWREADY;
input MAXIGP0BVALID;
input MAXIGP0RLAST;
input MAXIGP0RVALID;
input MAXIGP0WREADY;
input MAXIGP1ACLK;
input MAXIGP1ARREADY;
input MAXIGP1AWREADY;
input MAXIGP1BVALID;
input MAXIGP1RLAST;
input MAXIGP1RVALID;
input MAXIGP1WREADY;
input SAXIACPACLK;
input SAXIACPARVALID;
input SAXIACPAWVALID;
input SAXIACPBREADY;
input SAXIACPRREADY;
input SAXIACPWLAST;
input SAXIACPWVALID;
input SAXIGP0ACLK;
input SAXIGP0ARVALID;
input SAXIGP0AWVALID;
input SAXIGP0BREADY;
input SAXIGP0RREADY;
input SAXIGP0WLAST;
input SAXIGP0WVALID;
input SAXIGP1ACLK;
input SAXIGP1ARVALID;
input SAXIGP1AWVALID;
input SAXIGP1BREADY;
input SAXIGP1RREADY;
input SAXIGP1WLAST;
input SAXIGP1WVALID;
input SAXIHP0ACLK;
input SAXIHP0ARVALID;
input SAXIHP0AWVALID;
input SAXIHP0BREADY;
input SAXIHP0RDISSUECAP1EN;
input SAXIHP0RREADY;
input SAXIHP0WLAST;
input SAXIHP0WRISSUECAP1EN;
input SAXIHP0WVALID;
input SAXIHP1ACLK;
input SAXIHP1ARVALID;
input SAXIHP1AWVALID;
input SAXIHP1BREADY;
input SAXIHP1RDISSUECAP1EN;
input SAXIHP1RREADY;
input SAXIHP1WLAST;
input SAXIHP1WRISSUECAP1EN;
input SAXIHP1WVALID;
input SAXIHP2ACLK;
input SAXIHP2ARVALID;
input SAXIHP2AWVALID;
input SAXIHP2BREADY;
input SAXIHP2RDISSUECAP1EN;
input SAXIHP2RREADY;
input SAXIHP2WLAST;
input SAXIHP2WRISSUECAP1EN;
input SAXIHP2WVALID;
input SAXIHP3ACLK;
input SAXIHP3ARVALID;
input SAXIHP3AWVALID;
input SAXIHP3BREADY;
input SAXIHP3RDISSUECAP1EN;
input SAXIHP3RREADY;
input SAXIHP3WLAST;
input SAXIHP3WRISSUECAP1EN;
input SAXIHP3WVALID;
input [11:0] MAXIGP0BID;
input [11:0] MAXIGP0RID;
input [11:0] MAXIGP1BID;
input [11:0] MAXIGP1RID;
input [19:0] IRQF2P;
input [1:0] DMA0DRTYPE;
input [1:0] DMA1DRTYPE;
input [1:0] DMA2DRTYPE;
input [1:0] DMA3DRTYPE;
input [1:0] MAXIGP0BRESP;
input [1:0] MAXIGP0RRESP;
input [1:0] MAXIGP1BRESP;
input [1:0] MAXIGP1RRESP;
input [1:0] SAXIACPARBURST;
input [1:0] SAXIACPARLOCK;
input [1:0] SAXIACPARSIZE;
input [1:0] SAXIACPAWBURST;
input [1:0] SAXIACPAWLOCK;
input [1:0] SAXIACPAWSIZE;
input [1:0] SAXIGP0ARBURST;
input [1:0] SAXIGP0ARLOCK;
input [1:0] SAXIGP0ARSIZE;
input [1:0] SAXIGP0AWBURST;
input [1:0] SAXIGP0AWLOCK;
input [1:0] SAXIGP0AWSIZE;
input [1:0] SAXIGP1ARBURST;
input [1:0] SAXIGP1ARLOCK;
input [1:0] SAXIGP1ARSIZE;
input [1:0] SAXIGP1AWBURST;
input [1:0] SAXIGP1AWLOCK;
input [1:0] SAXIGP1AWSIZE;
input [1:0] SAXIHP0ARBURST;
input [1:0] SAXIHP0ARLOCK;
input [1:0] SAXIHP0ARSIZE;
input [1:0] SAXIHP0AWBURST;
input [1:0] SAXIHP0AWLOCK;
input [1:0] SAXIHP0AWSIZE;
input [1:0] SAXIHP1ARBURST;
input [1:0] SAXIHP1ARLOCK;
input [1:0] SAXIHP1ARSIZE;
input [1:0] SAXIHP1AWBURST;
input [1:0] SAXIHP1AWLOCK;
input [1:0] SAXIHP1AWSIZE;
input [1:0] SAXIHP2ARBURST;
input [1:0] SAXIHP2ARLOCK;
input [1:0] SAXIHP2ARSIZE;
input [1:0] SAXIHP2AWBURST;
input [1:0] SAXIHP2AWLOCK;
input [1:0] SAXIHP2AWSIZE;
input [1:0] SAXIHP3ARBURST;
input [1:0] SAXIHP3ARLOCK;
input [1:0] SAXIHP3ARSIZE;
input [1:0] SAXIHP3AWBURST;
input [1:0] SAXIHP3AWLOCK;
input [1:0] SAXIHP3AWSIZE;
input [2:0] EMIOTTC0CLKI;
input [2:0] EMIOTTC1CLKI;
input [2:0] SAXIACPARID;
input [2:0] SAXIACPARPROT;
input [2:0] SAXIACPAWID;
input [2:0] SAXIACPAWPROT;
input [2:0] SAXIACPWID;
input [2:0] SAXIGP0ARPROT;
input [2:0] SAXIGP0AWPROT;
input [2:0] SAXIGP1ARPROT;
input [2:0] SAXIGP1AWPROT;
input [2:0] SAXIHP0ARPROT;
input [2:0] SAXIHP0AWPROT;
input [2:0] SAXIHP1ARPROT;
input [2:0] SAXIHP1AWPROT;
input [2:0] SAXIHP2ARPROT;
input [2:0] SAXIHP2AWPROT;
input [2:0] SAXIHP3ARPROT;
input [2:0] SAXIHP3AWPROT;
input [31:0] FTMDTRACEINDATA;
input [31:0] FTMTF2PDEBUG;
input [31:0] MAXIGP0RDATA;
input [31:0] MAXIGP1RDATA;
input [31:0] SAXIACPARADDR;
input [31:0] SAXIACPAWADDR;
input [31:0] SAXIGP0ARADDR;
input [31:0] SAXIGP0AWADDR;
input [31:0] SAXIGP0WDATA;
input [31:0] SAXIGP1ARADDR;
input [31:0] SAXIGP1AWADDR;
input [31:0] SAXIGP1WDATA;
input [31:0] SAXIHP0ARADDR;
input [31:0] SAXIHP0AWADDR;
input [31:0] SAXIHP1ARADDR;
input [31:0] SAXIHP1AWADDR;
input [31:0] SAXIHP2ARADDR;
input [31:0] SAXIHP2AWADDR;
input [31:0] SAXIHP3ARADDR;
input [31:0] SAXIHP3AWADDR;
input [3:0] DDRARB;
input [3:0] EMIOSDIO0DATAI;
input [3:0] EMIOSDIO1DATAI;
input [3:0] FCLKCLKTRIGN;
input [3:0] FTMDTRACEINATID;
input [3:0] FTMTF2PTRIG;
input [3:0] FTMTP2FTRIGACK;
input [3:0] SAXIACPARCACHE;
input [3:0] SAXIACPARLEN;
input [3:0] SAXIACPARQOS;
input [3:0] SAXIACPAWCACHE;
input [3:0] SAXIACPAWLEN;
input [3:0] SAXIACPAWQOS;
input [3:0] SAXIGP0ARCACHE;
input [3:0] SAXIGP0ARLEN;
input [3:0] SAXIGP0ARQOS;
input [3:0] SAXIGP0AWCACHE;
input [3:0] SAXIGP0AWLEN;
input [3:0] SAXIGP0AWQOS;
input [3:0] SAXIGP0WSTRB;
input [3:0] SAXIGP1ARCACHE;
input [3:0] SAXIGP1ARLEN;
input [3:0] SAXIGP1ARQOS;
input [3:0] SAXIGP1AWCACHE;
input [3:0] SAXIGP1AWLEN;
input [3:0] SAXIGP1AWQOS;
input [3:0] SAXIGP1WSTRB;
input [3:0] SAXIHP0ARCACHE;
input [3:0] SAXIHP0ARLEN;
input [3:0] SAXIHP0ARQOS;
input [3:0] SAXIHP0AWCACHE;
input [3:0] SAXIHP0AWLEN;
input [3:0] SAXIHP0AWQOS;
input [3:0] SAXIHP1ARCACHE;
input [3:0] SAXIHP1ARLEN;
input [3:0] SAXIHP1ARQOS;
input [3:0] SAXIHP1AWCACHE;
input [3:0] SAXIHP1AWLEN;
input [3:0] SAXIHP1AWQOS;
input [3:0] SAXIHP2ARCACHE;
input [3:0] SAXIHP2ARLEN;
input [3:0] SAXIHP2ARQOS;
input [3:0] SAXIHP2AWCACHE;
input [3:0] SAXIHP2AWLEN;
input [3:0] SAXIHP2AWQOS;
input [3:0] SAXIHP3ARCACHE;
input [3:0] SAXIHP3ARLEN;
input [3:0] SAXIHP3ARQOS;
input [3:0] SAXIHP3AWCACHE;
input [3:0] SAXIHP3AWLEN;
input [3:0] SAXIHP3AWQOS;
input [4:0] SAXIACPARUSER;
input [4:0] SAXIACPAWUSER;
input [5:0] SAXIGP0ARID;
input [5:0] SAXIGP0AWID;
input [5:0] SAXIGP0WID;
input [5:0] SAXIGP1ARID;
input [5:0] SAXIGP1AWID;
input [5:0] SAXIGP1WID;
input [5:0] SAXIHP0ARID;
input [5:0] SAXIHP0AWID;
input [5:0] SAXIHP0WID;
input [5:0] SAXIHP1ARID;
input [5:0] SAXIHP1AWID;
input [5:0] SAXIHP1WID;
input [5:0] SAXIHP2ARID;
input [5:0] SAXIHP2AWID;
input [5:0] SAXIHP2WID;
input [5:0] SAXIHP3ARID;
input [5:0] SAXIHP3AWID;
input [5:0] SAXIHP3WID;
input [63:0] EMIOGPIOI;
input [63:0] SAXIACPWDATA;
input [63:0] SAXIHP0WDATA;
input [63:0] SAXIHP1WDATA;
input [63:0] SAXIHP2WDATA;
input [63:0] SAXIHP3WDATA;
input [7:0] EMIOENET0GMIIRXD;
input [7:0] EMIOENET1GMIIRXD;
input [7:0] SAXIACPWSTRB;
input [7:0] SAXIHP0WSTRB;
input [7:0] SAXIHP1WSTRB;
input [7:0] SAXIHP2WSTRB;
input [7:0] SAXIHP3WSTRB;
initial
begin
$display("Warning on instance %m : The Zynq-7000 All Programmable SoC does not have a simulation model. Behavioral simulation of Zynq-7000 (e.g. Zynq PS7 block) is not supported in any simulator. Please use the AXI BFM simulation model to verify the AXI transactions.");
end
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PULLDOWN.v 0000664 0000000 0000000 00000002103 12327044266 0022662 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/PULLDOWN.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Resistor to GND
// /___/ /\ Filename : PULLDOWN.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module PULLDOWN (O);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
wire A;
pulldown (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/PULLUP.v 0000664 0000000 0000000 00000002075 12327044266 0022447 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/PULLUP.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Resistor to VCC
// /___/ /\ Filename : PULLUP.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module PULLUP (O);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
wire A;
pullup (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM128X1D.v 0000664 0000000 0000000 00000013465 12327044266 0022622 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 128-Deep by 1-Wide
// /___/ /\ Filename : RAMD128.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM128X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [127:0] INIT = 128'h00000000000000000000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DPO,
output SPO,
input [6:0] A,
input [6:0] DPRA,
input D,
input WCLK,
input WE
);
reg [127:0] mem;
wire [6:0] A_dly;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in;
reg notifier;
assign SPO = mem[A_dly];
assign DPO = mem[DPRA];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] = 1'bx;
`ifndef XIL_TIMING
assign A_dly = A;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A[0] => SPO) = (0:0:0, 0:0:0);
(A[1] => SPO) = (0:0:0, 0:0:0);
(A[2] => SPO) = (0:0:0, 0:0:0);
(A[3] => SPO) = (0:0:0, 0:0:0);
(A[4] => SPO) = (0:0:0, 0:0:0);
(A[5] => SPO) = (0:0:0, 0:0:0);
(A[6] => SPO) = (0:0:0, 0:0:0);
(DPRA[0] => DPO) = (0:0:0, 0:0:0);
(DPRA[1] => DPO) = (0:0:0, 0:0:0);
(DPRA[2] => DPO) = (0:0:0, 0:0:0);
(DPRA[3] => DPO) = (0:0:0, 0:0:0);
(DPRA[4] => DPO) = (0:0:0, 0:0:0);
(DPRA[5] => DPO) = (0:0:0, 0:0:0);
(DPRA[6] => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM128X1S.v 0000664 0000000 0000000 00000013157 12327044266 0022637 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 128-Deep by 1-Wide
// /___/ /\ Filename : RAM128X1S.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM128X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [127:0] INIT = 128'h00000000000000000000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input A6,
input D,
input WCLK,
input WE
);
reg [127:0] mem;
wire [6:0] A_dly;
reg notifier;
wire D_dly, WCLK_dly, WE_dly;
wire WCLK_in;
assign O = mem[A_dly];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] <= 1'bx;
`ifndef XIL_TIMING
assign A_dly[0] = A0;
assign A_dly[1] = A1;
assign A_dly[2] = A2;
assign A_dly[3] = A3;
assign A_dly[4] = A4;
assign A_dly[5] = A5;
assign A_dly[6] = A6;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
(A5 => O) = (0:0:0, 0:0:0);
(A6 => O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM256X1D.v 0000664 0000000 0000000 00000014034 12327044266 0022615 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.3
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 256-Deep by 1-Wide
// /___/ /\ Filename : RAMD256.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 07/02/12 - Initial version, from RAM128X1D
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM256X1D # (
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output DPO,
output SPO,
input [7:0] A,
input D,
input [7:0] DPRA,
input WCLK,
input WE
);
reg [255:0] mem;
wire [7:0] A_dly, A_in;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in, WE_in, D_in;
`ifdef XIL_TIMING
reg notifier;
`endif
assign SPO = mem[A_in];
assign DPO = mem[DPRA];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier)
mem[A_in] = 1'bx;
`endif
`ifndef XIL_TIMING
assign A_dly = A;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED;
assign A_in = A_dly;
assign D_in = D_dly;
assign WE_in = WE_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A[0] => SPO) = (0:0:0, 0:0:0);
(A[1] => SPO) = (0:0:0, 0:0:0);
(A[2] => SPO) = (0:0:0, 0:0:0);
(A[3] => SPO) = (0:0:0, 0:0:0);
(A[4] => SPO) = (0:0:0, 0:0:0);
(A[5] => SPO) = (0:0:0, 0:0:0);
(A[6] => SPO) = (0:0:0, 0:0:0);
(A[7] => SPO) = (0:0:0, 0:0:0);
(DPRA[0] => DPO) = (0:0:0, 0:0:0);
(DPRA[1] => DPO) = (0:0:0, 0:0:0);
(DPRA[2] => DPO) = (0:0:0, 0:0:0);
(DPRA[3] => DPO) = (0:0:0, 0:0:0);
(DPRA[4] => DPO) = (0:0:0, 0:0:0);
(DPRA[5] => DPO) = (0:0:0, 0:0:0);
(DPRA[6] => DPO) = (0:0:0, 0:0:0);
(DPRA[7] => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM256X1S.v 0000664 0000000 0000000 00000013044 12327044266 0022634 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 256-Deep by 1-Wide
// /___/ /\ Filename : RAM256X1S.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM256X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [255:0] INIT = 256'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input [7:0] A,
input D,
input WCLK,
input WE
);
reg [255:0] mem;
wire [7:0] A_dly;
reg notifier;
wire D_dly, WCLK_dly, WE_dly;
wire WCLK_in;
assign O = mem[A_dly];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] <= 1'bx;
`ifndef XIL_TIMING
assign A_dly = A;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A *> O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM32M.v 0000664 0000000 0000000 00000022574 12327044266 0022335 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 32-Deep by 8-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM32M.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 03/21/06 - Initial version.
// 12/01/06 - Fix cut/past error for port C and D (CR 430051)
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM32M #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input WCLK,
input WE
);
wire [4:0] ADDRD_dly;
wire [1:0] DIA_dly, DIB_dly, DIC_dly, DID_dly;
wire WCLK_dly, WE_dly;
wire WCLK_in;
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [5:0] addrd_in2, addrd_in1;
reg notifier;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(ADDRD_dly) begin
addrd_in2 = 2 * ADDRD_dly;
addrd_in1 = 2 * ADDRD_dly + 1;
end
always @(posedge WCLK_in)
if (WE_dly) begin
mem_a[addrd_in2] <= #100 DIA_dly[0];
mem_a[addrd_in1] <= #100 DIA_dly[1];
mem_b[addrd_in2] <= #100 DIB_dly[0];
mem_b[addrd_in1] <= #100 DIB_dly[1];
mem_c[addrd_in2] <= #100 DIC_dly[0];
mem_c[addrd_in1] <= #100 DIC_dly[1];
mem_d[addrd_in2] <= #100 DID_dly[0];
mem_d[addrd_in1] <= #100 DID_dly[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD];
assign DOD[1] = mem_d[2*ADDRD + 1];
always @(notifier) begin
mem_a[addrd_in2] <= 1'bx;
mem_a[addrd_in1] <= 1'bx;
mem_b[addrd_in2] <= 1'bx;
mem_b[addrd_in1] <= 1'bx;
mem_c[addrd_in2] <= 1'bx;
mem_c[addrd_in1] <= 1'bx;
mem_d[addrd_in2] <= 1'bx;
mem_d[addrd_in1] <= 1'bx;
end
`ifndef XIL_TIMING
assign DIA_dly = DIA;
assign DIB_dly = DIB;
assign DIC_dly = DIC;
assign DID_dly = DID;
assign ADDRD_dly = ADDRD;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => DOA[0]) = (0:0:0, 0:0:0);
(WCLK => DOA[1]) = (0:0:0, 0:0:0);
(WCLK => DOB[0]) = (0:0:0, 0:0:0);
(WCLK => DOB[1]) = (0:0:0, 0:0:0);
(WCLK => DOC[0]) = (0:0:0, 0:0:0);
(WCLK => DOC[1]) = (0:0:0, 0:0:0);
(WCLK => DOD[0]) = (0:0:0, 0:0:0);
(WCLK => DOD[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[0]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[1]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[0]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[1]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[0]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[1]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[0]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[1]) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM32M16.v 0000664 0000000 0000000 00000035036 12327044266 0022501 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.3
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 32-Deep by 16-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM32M16.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 07/02/12 - Initial version, from RAM32M
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM32M16 # (
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [63:0] INIT_E = 64'h0000000000000000,
parameter [63:0] INIT_F = 64'h0000000000000000,
parameter [63:0] INIT_G = 64'h0000000000000000,
parameter [63:0] INIT_H = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
output [1:0] DOE,
output [1:0] DOF,
output [1:0] DOG,
output [1:0] DOH,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [4:0] ADDRE,
input [4:0] ADDRF,
input [4:0] ADDRG,
input [4:0] ADDRH,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input [1:0] DIE,
input [1:0] DIF,
input [1:0] DIG,
input [1:0] DIH,
input WCLK,
input WE
);
wire [4:0] ADDRH_dly, ADDRH_in;
wire [1:0] DIA_dly, DIB_dly, DIC_dly, DID_dly, DIE_dly, DIF_dly, DIG_dly, DIH_dly;
wire [1:0] DIA_in, DIB_in, DIC_in, DID_in, DIE_in, DIF_in, DIG_in, DIH_in;
wire WCLK_dly, WE_dly;
wire WCLK_in, WE_in;
reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
reg [5:0] addrh_in2, addrh_in1;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
mem_e = INIT_E;
mem_f = INIT_F;
mem_g = INIT_G;
mem_h = INIT_H;
end
always @(ADDRH_in) begin
addrh_in2 = 2 * ADDRH_in;
addrh_in1 = 2 * ADDRH_in + 1;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[addrh_in2] <= #100 DIA_in[0];
mem_a[addrh_in1] <= #100 DIA_in[1];
mem_b[addrh_in2] <= #100 DIB_in[0];
mem_b[addrh_in1] <= #100 DIB_in[1];
mem_c[addrh_in2] <= #100 DIC_in[0];
mem_c[addrh_in1] <= #100 DIC_in[1];
mem_d[addrh_in2] <= #100 DID_in[0];
mem_d[addrh_in1] <= #100 DID_in[1];
mem_e[addrh_in2] <= #100 DIE_in[0];
mem_e[addrh_in1] <= #100 DIE_in[1];
mem_f[addrh_in2] <= #100 DIF_in[0];
mem_f[addrh_in1] <= #100 DIF_in[1];
mem_g[addrh_in2] <= #100 DIG_in[0];
mem_g[addrh_in1] <= #100 DIG_in[1];
mem_h[addrh_in2] <= #100 DIH_in[0];
mem_h[addrh_in1] <= #100 DIH_in[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD];
assign DOD[1] = mem_d[2*ADDRD + 1];
assign DOE[0] = mem_e[2*ADDRE];
assign DOE[1] = mem_e[2*ADDRE + 1];
assign DOF[0] = mem_f[2*ADDRF];
assign DOF[1] = mem_f[2*ADDRF + 1];
assign DOG[0] = mem_g[2*ADDRG];
assign DOG[1] = mem_g[2*ADDRG + 1];
assign DOH[0] = mem_h[2*ADDRH_in];
assign DOH[1] = mem_h[2*ADDRH_in + 1];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[addrh_in2] <= 1'bx;
mem_a[addrh_in1] <= 1'bx;
mem_b[addrh_in2] <= 1'bx;
mem_b[addrh_in1] <= 1'bx;
mem_c[addrh_in2] <= 1'bx;
mem_c[addrh_in1] <= 1'bx;
mem_d[addrh_in2] <= 1'bx;
mem_d[addrh_in1] <= 1'bx;
mem_e[addrh_in2] <= 1'bx;
mem_e[addrh_in1] <= 1'bx;
mem_f[addrh_in2] <= 1'bx;
mem_f[addrh_in1] <= 1'bx;
mem_g[addrh_in2] <= 1'bx;
mem_g[addrh_in1] <= 1'bx;
mem_h[addrh_in2] <= 1'bx;
mem_h[addrh_in1] <= 1'bx;
end
`endif
`ifndef XIL_TIMING
assign DIA_dly = DIA;
assign DIB_dly = DIB;
assign DIC_dly = DIC;
assign DID_dly = DID;
assign DIE_dly = DIE;
assign DIF_dly = DIF;
assign DIG_dly = DIG;
assign DIH_dly = DIH;
assign ADDRH_dly = ADDRH;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign DIE_in = DIE_dly;
assign DIF_in = DIF_dly;
assign DIG_in = DIG_dly;
assign DIH_in = DIH_dly;
assign ADDRH_in = ADDRH_dly;
assign WE_in = WE_dly;
`ifdef XIL_TIMING
specify
(WCLK => DOA[0]) = (0:0:0, 0:0:0);
(WCLK => DOA[1]) = (0:0:0, 0:0:0);
(WCLK => DOB[0]) = (0:0:0, 0:0:0);
(WCLK => DOB[1]) = (0:0:0, 0:0:0);
(WCLK => DOC[0]) = (0:0:0, 0:0:0);
(WCLK => DOC[1]) = (0:0:0, 0:0:0);
(WCLK => DOD[0]) = (0:0:0, 0:0:0);
(WCLK => DOD[1]) = (0:0:0, 0:0:0);
(WCLK => DOE[0]) = (0:0:0, 0:0:0);
(WCLK => DOE[1]) = (0:0:0, 0:0:0);
(WCLK => DOF[0]) = (0:0:0, 0:0:0);
(WCLK => DOF[1]) = (0:0:0, 0:0:0);
(WCLK => DOG[0]) = (0:0:0, 0:0:0);
(WCLK => DOG[1]) = (0:0:0, 0:0:0);
(WCLK => DOH[0]) = (0:0:0, 0:0:0);
(WCLK => DOH[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[0]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[1]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[0]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[1]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[0]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[1]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[0]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[1]) = (0:0:0, 0:0:0);
(ADDRE *> DOE[0]) = (0:0:0, 0:0:0);
(ADDRE *> DOE[1]) = (0:0:0, 0:0:0);
(ADDRF *> DOF[0]) = (0:0:0, 0:0:0);
(ADDRF *> DOF[1]) = (0:0:0, 0:0:0);
(ADDRG *> DOG[0]) = (0:0:0, 0:0:0);
(ADDRG *> DOG[1]) = (0:0:0, 0:0:0);
(ADDRH *> DOH[0]) = (0:0:0, 0:0:0);
(ADDRH *> DOH[1]) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge DIE[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[0]);
$setuphold (posedge WCLK, negedge DIE[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[0]);
$setuphold (posedge WCLK, posedge DIE[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[1]);
$setuphold (posedge WCLK, negedge DIE[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[1]);
$setuphold (posedge WCLK, posedge DIF[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[0]);
$setuphold (posedge WCLK, negedge DIF[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[0]);
$setuphold (posedge WCLK, posedge DIF[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[1]);
$setuphold (posedge WCLK, negedge DIF[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[1]);
$setuphold (posedge WCLK, posedge DIG[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[0]);
$setuphold (posedge WCLK, negedge DIG[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[0]);
$setuphold (posedge WCLK, posedge DIG[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[1]);
$setuphold (posedge WCLK, negedge DIG[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[1]);
$setuphold (posedge WCLK, posedge DIH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[0]);
$setuphold (posedge WCLK, negedge DIH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[0]);
$setuphold (posedge WCLK, posedge DIH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[1]);
$setuphold (posedge WCLK, negedge DIH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[1]);
$setuphold (posedge WCLK, posedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, negedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, posedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, negedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, posedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, negedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, posedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, negedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, posedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, negedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIA[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIB[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DIC[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge DID[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge DIE[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[0]);
$setuphold (negedge WCLK, negedge DIE[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[0]);
$setuphold (negedge WCLK, posedge DIE[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[1]);
$setuphold (negedge WCLK, negedge DIE[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly[1]);
$setuphold (negedge WCLK, posedge DIF[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[0]);
$setuphold (negedge WCLK, negedge DIF[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[0]);
$setuphold (negedge WCLK, posedge DIF[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[1]);
$setuphold (negedge WCLK, negedge DIF[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly[1]);
$setuphold (negedge WCLK, posedge DIG[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[0]);
$setuphold (negedge WCLK, negedge DIG[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[0]);
$setuphold (negedge WCLK, posedge DIG[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[1]);
$setuphold (negedge WCLK, negedge DIG[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly[1]);
$setuphold (negedge WCLK, posedge DIH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[0]);
$setuphold (negedge WCLK, negedge DIH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[0]);
$setuphold (negedge WCLK, posedge DIH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[1]);
$setuphold (negedge WCLK, negedge DIH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly[1]);
$setuphold (negedge WCLK, posedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, negedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, posedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, negedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, posedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, negedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, posedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, negedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, posedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, negedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM32X1D.v 0000664 0000000 0000000 00000012244 12327044266 0022526 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMD32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM32X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DPO,
output SPO,
input A0,
input A1,
input A2,
input A3,
input A4,
input D,
input DPRA0,
input DPRA1,
input DPRA2,
input DPRA3,
input DPRA4,
input WCLK,
input WE
);
reg [32:0] mem;
wire [4:0] A_dly, A_in;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in, WE_in, D_in;
wire wclk_is_inverted;
reg notifier;
assign SPO = mem[A_in];
assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge(WCLK_in))
if (WE_in == 1'b1)
mem[A_in] <= #100 D_in;
always @(notifier)
mem[A_in] = 1'bx;
`ifndef XIL_TIMING
assign A_dly = {A4, A3, A2, A1, A0};
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign wclk_is_inverted = IS_WCLK_INVERTED;
assign WCLK_in = wclk_is_inverted ^ WCLK_dly;
assign WE_in = WE_dly;
assign A_in = A_dly;
assign D_in = D_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A0 => SPO) = (0:0:0, 0:0:0);
(A1 => SPO) = (0:0:0, 0:0:0);
(A2 => SPO) = (0:0:0, 0:0:0);
(A3 => SPO) = (0:0:0, 0:0:0);
(A4 => SPO) = (0:0:0, 0:0:0);
(DPRA0 => DPO) = (0:0:0, 0:0:0);
(DPRA1 => DPO) = (0:0:0, 0:0:0);
(DPRA2 => DPO) = (0:0:0, 0:0:0);
(DPRA3 => DPO) = (0:0:0, 0:0:0);
(DPRA4 => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM32X1S.v 0000664 0000000 0000000 00000011322 12327044266 0022541 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAM32X1S.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM32X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input D,
input WCLK,
input WE
);
reg [31:0] mem;
wire [4:0] A_dly;
reg notifier;
wire D_dly, WCLK_dly, WE_dly;
wire WCLK_in;
assign O = mem[A_dly];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] <= 1'bx;
`ifndef XIL_TIMING
assign A_dly[0] = A0;
assign A_dly[1] = A1;
assign A_dly[2] = A2;
assign A_dly[3] = A3;
assign A_dly[4] = A4;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM512X1S.v 0000664 0000000 0000000 00000013612 12327044266 0022630 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Static Synchronous RAM 512-Deep by 1-Wide
// /___/ /\ Filename : RAM512X1S.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 07/02/12 - Initial version, from RAM256X1S
// 09/17/12 - 678488 fix file name
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM512X1S # (
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [511:0] INIT = 512'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output O,
input [8:0] A,
input D,
input WCLK,
input WE
);
reg [511:0] mem;
wire [8:0] A_dly, A_in;
`ifdef XIL_TIMING
reg notifier;
`endif
wire D_dly, WCLK_dly, WE_dly;
wire D_in, WCLK_in, WE_in;
assign O = mem[A_in];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign A_dly = A;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED;
assign A_in = A_dly;
assign D_in = D_dly;
assign WE_in = WE_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A *> O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, posedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (posedge WCLK, negedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, posedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (negedge WCLK, negedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM64M.v 0000664 0000000 0000000 00000016213 12327044266 0022333 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 64-Deep by 4-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM64M.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 03/21/06 - Initial version.
// 12/01/06 - Fix the cut/past error for port C and D (CR 430051)
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM64M #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DOA,
output DOB,
output DOC,
output DOD,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,
input DID,
input WCLK,
input WE
);
reg [63:0] mem_a, mem_b, mem_c, mem_d;
wire [5:0] ADDRD_dly;
wire DIA_dly, DIB_dly, DIC_dly, DID_dly, WCLK_dly, WE_dly;
wire WCLK_in;
reg notifier;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(posedge WCLK_in)
if (WE_dly) begin
mem_a[ADDRD_dly] <= #100 DIA_dly;
mem_b[ADDRD_dly] <= #100 DIB_dly;
mem_c[ADDRD_dly] <= #100 DIC_dly;
mem_d[ADDRD_dly] <= #100 DID_dly;
end
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
always @(notifier) begin
mem_a[ADDRD_dly] <= 1'bx;
mem_b[ADDRD_dly] <= 1'bx;
mem_c[ADDRD_dly] <= 1'bx;
mem_d[ADDRD_dly] <= 1'bx;
end
`ifndef XIL_TIMING
assign DIA_dly = DIA;
assign DIB_dly = DIB;
assign DIC_dly = DIC;
assign DID_dly = DID;
assign ADDRD_dly = ADDRD;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, negedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, posedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, negedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, posedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, negedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, posedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, negedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, posedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge ADDRD[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, negedge ADDRD[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, negedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, posedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, negedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, posedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, negedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, posedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, negedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, posedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge ADDRD[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge ADDRD[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, negedge ADDRD[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM64M8.v 0000664 0000000 0000000 00000024353 12327044266 0022427 0 ustar 00root root 0000000 0000000 // $Header:
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.3
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 64-Deep by 8-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM64M8.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 07/02/12 - Initial version, from RAM64M
// 09/17/12 - 678604 - fix compilation errors
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM64M8 # (
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [63:0] INIT_E = 64'h0000000000000000,
parameter [63:0] INIT_F = 64'h0000000000000000,
parameter [63:0] INIT_G = 64'h0000000000000000,
parameter [63:0] INIT_H = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output DOA,
output DOB,
output DOC,
output DOD,
output DOE,
output DOF,
output DOG,
output DOH,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input [5:0] ADDRE,
input [5:0] ADDRF,
input [5:0] ADDRG,
input [5:0] ADDRH,
input DIA,
input DIB,
input DIC,
input DID,
input DIE,
input DIF,
input DIG,
input DIH,
input WCLK,
input WE
);
reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
wire [5:0] ADDRH_dly, ADDRH_in;
wire DIA_dly, DIB_dly, DIC_dly, DID_dly, DIE_dly, DIF_dly, DIG_dly, DIH_dly;
wire DIA_in, DIB_in, DIC_in, DID_in, DIE_in, DIF_in, DIG_in, DIH_in;
wire WCLK_dly, WE_dly;
wire WCLK_in, WE_in;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
mem_e = INIT_E;
mem_f = INIT_F;
mem_g = INIT_G;
mem_h = INIT_H;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[ADDRH_in] <= #100 DIA_in;
mem_b[ADDRH_in] <= #100 DIB_in;
mem_c[ADDRH_in] <= #100 DIC_in;
mem_d[ADDRH_in] <= #100 DID_in;
mem_e[ADDRH_in] <= #100 DIE_in;
mem_f[ADDRH_in] <= #100 DIF_in;
mem_g[ADDRH_in] <= #100 DIG_in;
mem_h[ADDRH_in] <= #100 DIH_in;
end
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
assign DOE = mem_e[ADDRE];
assign DOF = mem_f[ADDRF];
assign DOG = mem_g[ADDRG];
assign DOH = mem_h[ADDRH_in];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[ADDRH_in] <= 1'bx;
mem_b[ADDRH_in] <= 1'bx;
mem_c[ADDRH_in] <= 1'bx;
mem_d[ADDRH_in] <= 1'bx;
mem_e[ADDRH_in] <= 1'bx;
mem_f[ADDRH_in] <= 1'bx;
mem_g[ADDRH_in] <= 1'bx;
mem_h[ADDRH_in] <= 1'bx;
end
`endif
`ifndef XIL_TIMING
assign DIA_dly = DIA;
assign DIB_dly = DIB;
assign DIC_dly = DIC;
assign DID_dly = DID;
assign DIE_dly = DIE;
assign DIF_dly = DIF;
assign DIG_dly = DIG;
assign DIH_dly = DIH;
assign ADDRH_dly = ADDRH;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign DIE_in = DIE_dly;
assign DIF_in = DIF_dly;
assign DIG_in = DIG_dly;
assign DIH_in = DIH_dly;
assign ADDRH_in = ADDRH_dly;
assign WE_in = WE_dly;
`ifdef XIL_TIMING
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(WCLK => DOE) = (0:0:0, 0:0:0);
(WCLK => DOF) = (0:0:0, 0:0:0);
(WCLK => DOG) = (0:0:0, 0:0:0);
(WCLK => DOH) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
(ADDRE *> DOE) = (0:0:0, 0:0:0);
(ADDRF *> DOF) = (0:0:0, 0:0:0);
(ADDRG *> DOG) = (0:0:0, 0:0:0);
(ADDRH *> DOH) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, negedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, posedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, negedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, posedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, negedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, posedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, negedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, posedge DIE &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly);
$setuphold (posedge WCLK, negedge DIE &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly);
$setuphold (posedge WCLK, posedge DIF &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly);
$setuphold (posedge WCLK, negedge DIF &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly);
$setuphold (posedge WCLK, posedge DIG &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly);
$setuphold (posedge WCLK, negedge DIG &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly);
$setuphold (posedge WCLK, posedge DIH &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly);
$setuphold (posedge WCLK, negedge DIH &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly);
$setuphold (posedge WCLK, posedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, negedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, posedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, negedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, posedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, negedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, posedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, negedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, posedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, negedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, posedge ADDRH[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[5]);
$setuphold (posedge WCLK, negedge ADDRH[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[5]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, negedge DIA &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, posedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, negedge DIB &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, posedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, negedge DIC &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, posedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, negedge DID &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, posedge DIE &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly);
$setuphold (negedge WCLK, negedge DIE &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIE_dly);
$setuphold (negedge WCLK, posedge DIF &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly);
$setuphold (negedge WCLK, negedge DIF &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIF_dly);
$setuphold (negedge WCLK, posedge DIG &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly);
$setuphold (negedge WCLK, negedge DIG &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIG_dly);
$setuphold (negedge WCLK, posedge DIH &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly);
$setuphold (negedge WCLK, negedge DIH &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,DIH_dly);
$setuphold (negedge WCLK, posedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, negedge ADDRH[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, posedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, negedge ADDRH[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, posedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, negedge ADDRH[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, posedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, negedge ADDRH[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, posedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, negedge ADDRH[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, posedge ADDRH[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[5]);
$setuphold (negedge WCLK, negedge ADDRH[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,ADDRH_dly[5]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM64X1D.v 0000664 0000000 0000000 00000013126 12327044266 0022533 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMD64.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM64X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DPO,
output SPO,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input D,
input DPRA0,
input DPRA1,
input DPRA2,
input DPRA3,
input DPRA4,
input DPRA5,
input WCLK,
input WE
);
reg [63:0] mem;
wire [5:0] A_dly;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in;
reg notifier;
assign SPO = mem[A_dly];
assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] = 1'bx;
`ifndef XIL_TIMING
assign A_dly[0] = A0;
assign A_dly[1] = A1;
assign A_dly[2] = A2;
assign A_dly[3] = A3;
assign A_dly[4] = A4;
assign A_dly[5] = A5;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A0 => SPO) = (0:0:0, 0:0:0);
(A1 => SPO) = (0:0:0, 0:0:0);
(A2 => SPO) = (0:0:0, 0:0:0);
(A3 => SPO) = (0:0:0, 0:0:0);
(A4 => SPO) = (0:0:0, 0:0:0);
(A5 => SPO) = (0:0:0, 0:0:0);
(DPRA0 => DPO) = (0:0:0, 0:0:0);
(DPRA1 => DPO) = (0:0:0, 0:0:0);
(DPRA2 => DPO) = (0:0:0, 0:0:0);
(DPRA3 => DPO) = (0:0:0, 0:0:0);
(DPRA4 => DPO) = (0:0:0, 0:0:0);
(DPRA5 => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAM64X1S.v 0000664 0000000 0000000 00000012237 12327044266 0022554 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAM64X1S.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM64X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input D,
input WCLK,
input WE
);
reg [63:0] mem;
wire [5:0] A_dly;
reg notifier;
wire D_dly, WCLK_dly, WE_dly;
wire WCLK_in;
assign O = mem[A_dly];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_dly == 1'b1)
mem[A_dly] <= #100 D_dly;
always @(notifier)
mem[A_dly] <= 1'bx;
`ifndef XIL_TIMING
assign A_dly[0] = A0;
assign A_dly[1] = A1;
assign A_dly[2] = A2;
assign A_dly[3] = A3;
assign A_dly[4] = A4;
assign A_dly[5] = A5;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
(A5 => O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMB18E1.v 0000664 0000000 0000000 00000710500 12327044266 0022505 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2008 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
// /___/ /\ Filename : RAMB18E1.v
// \ \ / \ Timestamp : Tue Feb 26 13:49:08 PST 2008
// \___\/\___\
//
// Revision:
// 02/26/08 - Initial version.
// 07/25/08 - Fixed ECC in register mode. (IR 477257)
// 07/30/08 - Updated to support SDP mode with smaller port width <= 18. (IR 477258)
// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964)
// 03/11/09 - X's the unused bits of outputs (CR 511363).
// 03/12/09 - Removed parameter from specify block (CR 503821).
// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167).
// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450).
// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327).
// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010).
// 11/18/09 - Define tasks and functions before calling (CR 532610).
// 12/16/09 - Enhanced memory initialization (CR 540764).
// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010).
// 04/01/10 - Fixed clocks detection for collision (CR 552123).
// 05/11/10 - Updated clocks detection for collision (CR 557624).
// - Added attribute RDADDR_COLLISION_HWCONFIG. (CR 557971).
// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807).
// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971).
// 07/08/10 - Added SIM_DEVICE attribute (CR 567633).
// 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672).
// 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924).
// 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953).
// 12/10/10 - Converted parameter to wire in specify block (CR 574534).
// 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053).
// 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004).
// 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942).
// 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942).
// 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129).
// 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482).
// 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399).
// 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454).
// 03/15/12 - Reverted CR 584399 (CR 651279).
// 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934).
// 07/25/13 - Added invertible pins support (CR 715417).
// 09/04/13 - Removed warning for memp (CR 728988).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAMB18E1 (DOADO, DOBDO, DOPADOP, DOPBDOP,
ADDRARDADDR, ADDRBWRADDR, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter INIT_FILE = "NONE";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
localparam SETUP_ALL = 1000;
localparam SETUP_READ_FIRST = 3000;
output [15:0] DOADO;
output [15:0] DOBDO;
output [1:0] DOPADOP;
output [1:0] DOPBDOP;
input CLKARDCLK;
input CLKBWRCLK;
input ENARDEN;
input ENBWREN;
input REGCEAREGCE;
input REGCEB;
input RSTRAMARSTRAM;
input RSTRAMB;
input RSTREGARSTREG;
input RSTREGB;
input [13:0] ADDRARDADDR;
input [13:0] ADDRBWRADDR;
input [15:0] DIADI;
input [15:0] DIBDI;
input [1:0] DIPADIP;
input [1:0] DIPBDIP;
input [1:0] WEA;
input [3:0] WEBWE;
tri0 GSR = glbl.GSR;
wire [7:0] dangle_out8;
wire dangle_out;
wire [1:0] dangle_out2;
wire [3:0] dangle_out4;
wire [5:0] dangle_out6;
wire [8:0] dangle_out9;
wire [15:0] dangle_out16;
wire [31:0] dangle_out32;
wire [47:0] dangle_out48;
wire [15:0] doado_wire, dobdo_wire;
wire [1:0] dopadop_wire, dopbdop_wire;
reg [15:0] doado_out, dobdo_out;
reg [1:0] dopadop_out, dopbdop_out;
reg notifier, notifier_a, notifier_b;
reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4;
reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9;
reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13;
reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4;
reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9;
reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13;
reg attr_err = 1'b0;
assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED;
assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED;
assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED;
assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED;
assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED;
assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED;
assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED;
assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED;
initial begin
if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end // initial begin
// special handle for sdp width = 36
localparam init_sdp = (READ_WIDTH_A == 36) ? {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : {INIT_B, INIT_A};
localparam srval_sdp = (READ_WIDTH_A == 36) ? {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : {SRVAL_B, SRVAL_A};
generate
case (RAM_MODE)
"TDP" : begin
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_FILE(INIT_FILE),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_TDP (.ADDRA({2'b0,ADDRARDADDR}),
.ADDRB({2'b0,ADDRBWRADDR}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA({48'b0,DIADI}),
.DIB({48'b0,DIBDI}),
.DIPA({2'b0,DIPADIP}),
.DIPB({6'b0,DIPBDIP}),
.DOA({dangle_out48,doado_wire}),
.DOB({dangle_out16,dobdo_wire}),
.DOPA({dangle_out6,dopadop_wire}),
.DOPB({dangle_out2,dopbdop_wire}),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA({4{WEA}}),
.WEB({2{WEBWE}}));
end // case: "TDP"
"SDP" : begin
if (WRITE_WIDTH_B == 36) begin
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A({36'b0,init_sdp}),
.INIT_B({36'b0,init_sdp}),
.INIT_FILE(INIT_FILE),
.SRVAL_A({36'b0,{srval_sdp}}),
.SRVAL_B({36'b0,{srval_sdp}}),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_SDP (.ADDRA({2'b0,ADDRARDADDR}),
.ADDRB({2'b0,ADDRBWRADDR}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA(64'b0),
.DIB({32'b0,DIBDI,DIADI}),
.DIPA(4'b0),
.DIPB({4'b0,DIPBDIP,DIPADIP}),
.DOA({dangle_out32,dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dangle_out4,dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA(8'b0),
.WEB({2{WEBWE}}));
end // if (WRITE_WIDTH_B == 36)
else begin
RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A({36'b0,init_sdp}),
.INIT_B({36'b0,init_sdp}),
.INIT_FILE(INIT_FILE),
.SRVAL_A({36'b0,{srval_sdp}}),
.SRVAL_B({36'b0,{srval_sdp}}),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.BRAM_SIZE(18),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07))
INT_RAMB_SDP (.ADDRA({2'b0,ADDRARDADDR}),
.ADDRB({2'b0,ADDRBWRADDR}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(dangle_out),
.CASCADEOUTB(dangle_out),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(dangle_out),
.DIA(64'b0),
.DIB({48'b0,DIBDI}),
.DIPA(4'b0),
.DIPB({6'b0,DIPBDIP}),
.DOA({dangle_out32,dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dangle_out4,dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(dangle_out8),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(dangle_out9),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(dangle_out),
.WEA(8'b0),
.WEB({2{WEBWE}}));
end // else: !if(WRITE_WIDTH_B == 36)
end // case: "SDP"
endcase // case(RAM_MODE)
endgenerate
//*** Timing Checks Start here
always @(doado_wire or clkardclk_in) doado_out = doado_wire;
always @(dobdo_wire or clkbwrclk_in) dobdo_out = dobdo_wire;
always @(dopadop_wire or clkardclk_in) dopadop_out = dopadop_wire;
always @(dopbdop_wire or clkbwrclk_in) dopbdop_out = dopbdop_wire;
assign DOADO = doado_out;
assign DOBDO = dobdo_out;
assign DOPADOP = dopadop_out;
assign DOPBDOP = dopbdop_out;
`ifdef XIL_TIMING
wire diadi0_enable = (RAM_MODE == "TDP") && enarden_in && WEA[0];
wire diadi1_enable = (RAM_MODE == "TDP") && enarden_in && WEA[1];
wire dibdi0_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[0]) : (ENBWREN && WEBWE[2]) ;
wire dibdi1_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[1]) : (ENBWREN && WEBWE[3]) ;
wire sdp_dia0_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[0];
wire sdp_dia1_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[1];
always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or
notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or
notifier_addra11 or notifier_addra12 or notifier_addra13) begin
doado_out <= 16'hxxxx;
dopadop_out <= 2'bxx;
end
always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or
notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or
notifier_addrb11 or notifier_addrb12 or notifier_addrb13) begin
dobdo_out <= 16'hxxxx;
dopbdop_out <= 2'bxx;
if (RAM_MODE == "SDP") begin
doado_out <= 16'hxxxx;
dopadop_out <= 2'bxx;
end
end
always @(notifier_addra0) begin
task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK");
end
always @(notifier_addra1) begin
task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK");
end
always @(notifier_addra2) begin
task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK");
end
always @(notifier_addra3) begin
task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK");
end
always @(notifier_addra4) begin
task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK");
end
always @(notifier_addra5) begin
task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK");
end
always @(notifier_addra6) begin
task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK");
end
always @(notifier_addra7) begin
task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK");
end
always @(notifier_addra8) begin
task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK");
end
always @(notifier_addra9) begin
task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK");
end
always @(notifier_addra10) begin
task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK");
end
always @(notifier_addra11) begin
task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK");
end
always @(notifier_addra12) begin
task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK");
end
always @(notifier_addra13) begin
task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK");
end
always @(notifier_addrb0) begin
task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK");
end
always @(notifier_addrb1) begin
task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK");
end
always @(notifier_addrb2) begin
task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK");
end
always @(notifier_addrb3) begin
task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK");
end
always @(notifier_addrb4) begin
task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK");
end
always @(notifier_addrb5) begin
task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK");
end
always @(notifier_addrb6) begin
task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK");
end
always @(notifier_addrb7) begin
task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK");
end
always @(notifier_addrb8) begin
task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK");
end
always @(notifier_addrb9) begin
task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK");
end
always @(notifier_addrb10) begin
task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK");
end
always @(notifier_addrb11) begin
task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK");
end
always @(notifier_addrb12) begin
task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK");
end
always @(notifier_addrb13) begin
task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK");
end
task task_warn_msg;
input [8*15:1] addr_str;
input [8*9:1] clk_str;
begin
$display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str);
end
endtask // task_warn_msg
`endif // `ifdef XIL_TIMING
wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0;
specify
(CLKARDCLK *> DOADO) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR &&& ENARDEN, 0:0:0, 0:0:0, notifier_addra0);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR &&& ENARDEN, 0:0:0, 0:0:0, notifier_addra0);
$setuphold (posedge CLKARDCLK, posedge DIADI &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge DIADI &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge DIPADIP &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge DIPADIP &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge WEA &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge WEA &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR &&& ENBWREN, 0:0:0, 0:0:0, notifier_addrb0);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR &&& ENBWREN, 0:0:0, 0:0:0, notifier_addrb0);
$setuphold (posedge CLKBWRCLK, posedge DIADI &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIADI &&& sdp_dia1_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIPADIP &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIPADIP &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIBDI &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIBDI &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIPBDIP &&& dibdi1_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIPBDIP &&& dibdi1_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge WEBWE &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge WEBWE &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$period (posedge CLKARDCLK, 0:0:0, notifier_a);
$period (posedge CLKBWRCLK, 0:0:0, notifier_b);
$width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
$width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // RAMB18E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. RAMB18E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module RB18_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR,
ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB);
output CASCADEOUTA;
output CASCADEOUTB;
output SBITERR, DBITERR;
output [8:0] RDADDRECC;
output [63:0] DOA;
output [31:0] DOB;
output [7:0] DOPA;
output [3:0] DOPB;
output [7:0] ECCPARITY;
input ENA, CLKA, CASCADEINA, REGCEA;
input ENB, CLKB, CASCADEINB, REGCEB;
input GSR;
input RSTRAMA, RSTRAMB;
input RSTREGA, RSTREGB;
input INJECTDBITERR, INJECTSBITERR;
input [15:0] ADDRA;
input [15:0] ADDRB;
input [63:0] DIA;
input [63:0] DIB;
input [3:0] DIPA;
input [7:0] DIPB;
input [7:0] WEA;
input [7:0] WEB;
parameter DOA_REG = 0;
parameter DOB_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INIT_A = 72'h0;
parameter INIT_B = 72'h0;
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SETUP_ALL = 1000;
parameter SETUP_READ_FIRST = 3000;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 72'h0;
parameter SRVAL_B = 72'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter INIT_FILE = "NONE";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameters are changed.
parameter BRAM_SIZE = 36;
// xilinx_internal_parameter off
integer count, countp, init_mult, initp_mult, large_width;
integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset;
integer viol_time = 0;
integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int;
integer ram_mode_int, en_ecc_write_int, en_ecc_read_int;
integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0;
reg addra_in_15_reg_bram, addrb_in_15_reg_bram;
reg addra_in_15_reg, addrb_in_15_reg;
reg addra_in_15_reg1, addrb_in_15_reg1;
reg junk1;
reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b;
reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0, doa_out_out;
reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0, dob_out_out;
reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0, dopb_out_out;
reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0, dopa_out_out;
reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0;
reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0;
reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0;
reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, syndrome = 8'b0;
reg [7:0] dipb_in_ecc;
reg [71:0] ecc_bit_position;
reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected;
reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_outreg = 0, sbiterr_outreg = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [7:0] wea_reg;
reg enb_reg;
reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg;
reg outp_a = 1'b0, outp_b = 1'b0, junkp;
reg rising_clka = 1'b0, rising_clkb = 1'b0;
reg [15:0] addra_reg, addrb_reg;
reg [63:0] dia_reg, dib_reg;
reg [3:0] dipa_reg;
reg [7:0] dipb_reg;
reg [1:0] viol_type = 2'b00;
reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1;
reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0;
reg [8:0] rdaddrecc_out_out = 9'b0;
reg finish_error = 0;
time time_port_a, time_port_b;
wire [63:0] dib_in;
wire [63:0] dia_in;
wire [15:0] addra_in, addrb_in;
wire clka_in, clkb_in;
wire [7:0] dipb_in;
wire [3:0] dipa_in;
wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in;
wire [7:0] wea_in;
wire [7:0] web_in;
wire cascadeina_in, cascadeinb_in;
wire injectdbiterr_in, injectsbiterr_in;
wire rstrega_in, rstregb_in;
wire [15:0] ox_addra_reconstruct, ox_addrb_reconstruct;
reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg;
wire temp_wire; // trigger NCsim at initial time
assign temp_wire = 1;
time time_clka_period, time_clkb_period, time_period;
reg time_skew_a_flag = 0;
reg time_skew_b_flag = 0;
assign addra_in = ADDRA;
assign addrb_in = ADDRB;
assign clka_in = CLKA;
assign clkb_in = CLKB;
assign dia_in = DIA;
assign dib_in = DIB;
assign dipa_in = DIPA;
assign dipb_in = DIPB;
assign DOA = doa_out_out;
assign DOPA = dopa_out_out;
assign DOB = dob_out_out;
assign DOPB = dopb_out_out;
assign ena_in = ENA;
assign enb_in = ENB;
assign gsr_in = GSR;
assign regcea_in = REGCEA;
assign regceb_in = REGCEB;
assign rstrama_in = RSTRAMA;
assign rstramb_in = RSTRAMB;
assign wea_in = WEA;
assign web_in = WEB;
assign cascadeina_in = CASCADEINA;
assign cascadeinb_in = CASCADEINB;
assign CASCADEOUTA = doa_out_out[0];
assign CASCADEOUTB = dob_out_out[0];
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
assign RDADDRECC = rdaddrecc_out_out;
assign injectdbiterr_in = INJECTDBITERR;
assign injectsbiterr_in = INJECTSBITERR;
assign rstrega_in = RSTREGA;
assign rstregb_in = RSTREGB;
localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100;
// Determine memory size
localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A &&
WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A :
(WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A &&
WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B :
(READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B &&
READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A :
(READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B &&
READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 64;
localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 :
(WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 :
(WRITE_WIDTH_A == 72) ? 64 : 64;
localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 :
(WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 :
(WRITE_WIDTH_B == 72) ? 64 : 64;
localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 :
(WRITE_WIDTH_A == 72) ? 8 : 8;
localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 :
(WRITE_WIDTH_B == 72) ? 8 : 8;
localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 :
(READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 :
(READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 1) ? 1 :
(READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 :
(READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : (READ_WIDTH_B == 72) ? 64 : 64) : 64;
localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 :
(READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 :
(READ_WIDTH_B == 72) ? 64 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 1) ? 1 :
(READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 :
(READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : (READ_WIDTH_A == 72) ? 64 : 64) : 64;
localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 :
(READ_WIDTH_A == 72) ? 8 : 8;
localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 :
(READ_WIDTH_B == 72) ? 8 : 8;
localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 :
(widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 :
(widest_width == 72) ? 6 : 0;
assign ox_addra_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ?
((BRAM_SIZE == 36) ? {1'b0,addra_in[14:8],8'b0} :
(BRAM_SIZE == 18) ? {2'b0,addra_in[13:7],7'b0} : addra_in) : addra_in;
assign ox_addrb_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ?
((BRAM_SIZE == 36) ? {1'b0,addrb_in[14:8],8'b0} :
(BRAM_SIZE == 18) ? {2'b0,addrb_in[13:7],7'b0} : addrb_in) : addrb_in;
localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 :
(widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 :
(widest_width == 72) ? 64 : 64;
localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 :
(widest_width == 72) ? 8 : 8;
localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : 10) : 10;
localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : 10) : 10;
localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 :
(WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 :
(WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 :
(WRITE_WIDTH_A == 72) ? 6 : 10;
localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 :
(WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 :
(WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 :
(WRITE_WIDTH_B == 72) ? 6 : 10;
localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10;
localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768;
localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384;
localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192;
localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096;
localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048;
localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024;
localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512;
localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 :
(widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 32768;
localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 4096;
reg [widest_width-1:0] tmp_mem [mem_depth-1:0];
reg [width-1:0] mem [mem_depth-1:0];
reg [widthp-1:0] memp [memp_depth-1:0];
integer index = 0;
/******************************************** task and function **************************************/
task task_ram;
input ram_we;
input [7:0] ram_di;
input ram_dip;
inout [7:0] mem_task;
inout memp_task;
begin
if (ram_we == 1'b1) begin
mem_task = ram_di;
if (width >= 8)
memp_task = ram_dip;
end
end
endtask // task_ram
task task_ram_col;
input ram_col_we_o;
input ram_col_we;
input [7:0] ram_col_di;
input ram_col_dip;
inout [7:0] ram_col_mem_task;
inout ram_col_memp_task;
integer ram_col_i;
begin
if (ram_col_we == 1'b1) begin
for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1)
if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))
ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i];
if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)))
ram_col_memp_task = ram_col_dip;
end
end
endtask // task_ram_col
task task_ram_ox;
input ram_ox_we_o;
input ram_ox_we;
input [7:0] ram_ox_di;
input ram_ox_dip;
inout [7:0] ram_ox_mem_task;
inout ram_ox_memp_task;
integer ram_ox_i;
begin
if (ram_ox_we == 1'b1) begin
for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1)
ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i];
if (width >= 8)
ram_ox_memp_task = ram_ox_dip;
end
end
endtask // task_ram_ox
task task_x_buf;
input [1:0] wr_rd_mode;
input integer do_uindex;
input integer do_lindex;
input integer dop_index;
input [63:0] do_ltmp;
inout [63:0] x_buf_do_tmp;
input [7:0] dop_ltmp;
inout [7:0] x_buf_dop_tmp;
integer i;
begin
if (wr_rd_mode == 2'b01) begin
for (i = do_lindex; i <= do_uindex; i = i + 1) begin
if (do_ltmp[i] === 1'bx)
x_buf_do_tmp[i] = 1'bx;
end
if (dop_ltmp[dop_index] === 1'bx)
x_buf_dop_tmp[dop_index] = 1'bx;
end // if (wr_rd_mode == 2'b01)
else begin
x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8];
x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index];
end // else: !if(wr_rd_mode == 2'b01)
end
endtask // task_x_buf
task task_col_wr_ram_a;
input [1:0] col_wr_ram_a_seq;
input [7:0] col_wr_ram_a_web_tmp;
input [7:0] col_wr_ram_a_wea_tmp;
input [63:0] col_wr_ram_a_dia_tmp;
input [7:0] col_wr_ram_a_dipa_tmp;
input [15:0] col_wr_ram_a_addrb_tmp;
input [15:0] col_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : begin
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][16 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][24 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][32 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][40 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][48 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][56 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_col_wr_ram_a
task task_ox_wr_ram_a;
input [1:0] ox_wr_ram_a_seq;
input [7:0] ox_wr_ram_a_web_tmp;
input [7:0] ox_wr_ram_a_wea_tmp;
input [63:0] ox_wr_ram_a_dia_tmp;
input [7:0] ox_wr_ram_a_dipa_tmp;
input [15:0] ox_wr_ram_a_addrb_tmp;
input [15:0] ox_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][16 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][24 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][32 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][40 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][48 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][56 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_ox_wr_ram_a
task task_col_wr_ram_b;
input [1:0] col_wr_ram_b_seq;
input [7:0] col_wr_ram_b_wea_tmp;
input [7:0] col_wr_ram_b_web_tmp;
input [63:0] col_wr_ram_b_dib_tmp;
input [7:0] col_wr_ram_b_dipb_tmp;
input [15:0] col_wr_ram_b_addra_tmp;
input [15:0] col_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 16
32 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 32
64 : begin
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_col_wr_ram_b
task task_ox_wr_ram_b;
input [1:0] ox_wr_ram_b_seq;
input [7:0] ox_wr_ram_b_wea_tmp;
input [7:0] ox_wr_ram_b_web_tmp;
input [63:0] ox_wr_ram_b_dib_tmp;
input [7:0] ox_wr_ram_b_dipb_tmp;
input [15:0] ox_wr_ram_b_addra_tmp;
input [15:0] ox_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 16
32 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 32
64 : begin
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_ox_wr_ram_b
task task_wr_ram_a;
input [7:0] wr_ram_a_wea_tmp;
input [63:0] dia_tmp;
input [7:0] dipa_tmp;
input [15:0] wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
end
8 : begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
end
16 : begin
if (wa_width >= width) begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
end
else begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
end // else: !if(wa_width >= wb_width)
end // case: 16
32 : begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
end // case: 32
endcase // case(wa_width)
end
endtask // task_wr_ram_a
task task_wr_ram_b;
input [7:0] wr_ram_b_web_tmp;
input [63:0] dib_tmp;
input [7:0] dipb_tmp;
input [15:0] wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
end
8 : begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
end
16 : begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
end
else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
end
end // case: 16
32 : begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
end
else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
end // else: !if(wb_width >= width)
end // case: 32
64 : begin // only valid with ECC single bit correction for 64 bits
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
end // case: 64
endcase // case(wb_width)
end
endtask // task_wr_ram_b
task task_col_rd_ram_a;
input [1:0] col_rd_ram_a_seq; // 1 is bypass
input [7:0] col_rd_ram_a_web_tmp;
input [7:0] col_rd_ram_a_wea_tmp;
input [15:0] col_rd_ram_a_addra_tmp;
inout [63:0] col_rd_ram_a_doa_tmp;
inout [7:0] col_rd_ram_a_dopa_tmp;
reg [63:0] doa_ltmp;
reg [7:0] dopa_ltmp;
begin
doa_ltmp= 64'b0;
dopa_ltmp= 8'b0;
case (ra_width)
1, 2, 4 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width)
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 1, 2, 4
8 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]];
end
else begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 8) +: 8];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 8
16 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1];
end
else begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) +: 8];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1];
end
else begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) + 8) +: 8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
32 : begin
if (ra_width >= width) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][23:16];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][31:24];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // if (ra_width >= width)
end
64 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][23:16];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][31:24];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin
doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][39:32];
dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin
doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][47:40];
dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin
doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][55:48];
dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin
doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][63:56];
dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
endcase // case(ra_width)
end
endtask // task_col_rd_ram_a
task task_col_rd_ram_b;
input [1:0] col_rd_ram_b_seq; // 1 is bypass
input [7:0] col_rd_ram_b_wea_tmp;
input [7:0] col_rd_ram_b_web_tmp;
input [15:0] col_rd_ram_b_addrb_tmp;
inout [63:0] col_rd_ram_b_dob_tmp;
inout [7:0] col_rd_ram_b_dopb_tmp;
reg [63:0] col_rd_ram_b_dob_ltmp;
reg [7:0] col_rd_ram_b_dopb_ltmp;
begin
col_rd_ram_b_dob_ltmp= 64'b0;
col_rd_ram_b_dopb_ltmp= 8'b0;
case (rb_width)
1, 2, 4 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width)
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width];
task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 1, 2, 4
8 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]];
end
else begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 8
16 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 8];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) + 8) +: 8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
32 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) +: 8];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 8) +: 8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][23:16];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 16) +: 8];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1];
end
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][31:24];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 24) +: 8];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1];
end
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
64 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][23:16];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][31:24];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][39:32];
col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][47:40];
col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][55:48];
col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][63:56];
col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
endcase // case(rb_width)
end
endtask // task_col_rd_ram_b
task task_rd_ram_a;
input [15:0] rd_ram_a_addra_tmp;
inout [63:0] doa_tmp;
inout [7:0] dopa_tmp;
begin
case (ra_width)
1, 2, 4 : begin
if (ra_width >= width)
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
end
8 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:3]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * 8) +: 8];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1];
end
end
16 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:4]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) +: 16];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 2];
end
end
32 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:5]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * 32) +: 32];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * 4) +: 4];
end
end
64 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:6]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]];
end
end
endcase // case(ra_width)
end
endtask // task_rd_ram_a
task task_rd_ram_b;
input [15:0] rd_ram_b_addrb_tmp;
inout [31:0] dob_tmp;
inout [3:0] dopb_tmp;
begin
case (rb_width)
1, 2, 4 : begin
if (rb_width >= width)
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width];
end
8 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
end
16 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2];
end
end
32 : begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]];
end
64 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]];
end
end
endcase
end
endtask // task_rd_ram_b
task chk_for_col_msg;
input wea_tmp;
input web_tmp;
input [15:0] addra_tmp;
input [15:0] addrb_tmp;
begin
if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY")
if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
col_wr_wr_msg = 0;
end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1)
else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp);
end // else: !if(chk_ox_msg == 1)
col_wra_rdb_msg = 0;
end
else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01))
$display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp);
end // else: !if(chk_ox_msg == 1)
col_wrb_rda_msg = 0;
end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1)
end
endtask // chk_for_col_msg
task task_col_ecc_read;
inout [63:0] do_tmp;
inout [7:0] dop_tmp;
input [15:0] addr_tmp;
reg [71:0] task_ecc_bit_position;
reg [7:0] task_dopr_ecc, task_syndrome;
reg [63:0] task_di_in_ecc_corrected;
reg [7:0] task_dip_in_ecc_corrected;
begin
if (|do_tmp === 1'bx) begin // if there is collision
dbiterr_out <= 1'bx;
sbiterr_out <= 1'bx;
end
else begin
task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp);
task_syndrome = task_dopr_ecc ^ dop_tmp;
if (task_syndrome !== 0) begin
if (task_syndrome[7]) begin // dectect single bit error
task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]};
if (task_syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output
task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory
do_tmp = task_di_in_ecc_corrected;
task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_tmp = task_dip_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!task_syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (task_syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(task_syndrome !== 0)
end
end
endtask // task_col_ecc_read
function [7:0] fn_dip_ecc;
input encode;
input [63:0] di_in;
input [7:0] dip_in;
begin
fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
if (encode == 1'b1)
fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
else
fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
end
endfunction // fn_dip_ecc
/******************************************** END task and function **************************************/
initial begin
if (INIT_FILE == "NONE") begin // memory initialization from attributes
init_mult = 256/width;
for (count = 0; count < init_mult; count = count + 1) begin
init_offset = count * width;
mem[count] = INIT_00[init_offset +:width];
mem[count + (init_mult * 1)] = INIT_01[init_offset +:width];
mem[count + (init_mult * 2)] = INIT_02[init_offset +:width];
mem[count + (init_mult * 3)] = INIT_03[init_offset +:width];
mem[count + (init_mult * 4)] = INIT_04[init_offset +:width];
mem[count + (init_mult * 5)] = INIT_05[init_offset +:width];
mem[count + (init_mult * 6)] = INIT_06[init_offset +:width];
mem[count + (init_mult * 7)] = INIT_07[init_offset +:width];
mem[count + (init_mult * 8)] = INIT_08[init_offset +:width];
mem[count + (init_mult * 9)] = INIT_09[init_offset +:width];
mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width];
mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width];
mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width];
mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width];
mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width];
mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width];
mem[count + (init_mult * 16)] = INIT_10[init_offset +:width];
mem[count + (init_mult * 17)] = INIT_11[init_offset +:width];
mem[count + (init_mult * 18)] = INIT_12[init_offset +:width];
mem[count + (init_mult * 19)] = INIT_13[init_offset +:width];
mem[count + (init_mult * 20)] = INIT_14[init_offset +:width];
mem[count + (init_mult * 21)] = INIT_15[init_offset +:width];
mem[count + (init_mult * 22)] = INIT_16[init_offset +:width];
mem[count + (init_mult * 23)] = INIT_17[init_offset +:width];
mem[count + (init_mult * 24)] = INIT_18[init_offset +:width];
mem[count + (init_mult * 25)] = INIT_19[init_offset +:width];
mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width];
mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width];
mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width];
mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width];
mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width];
mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width];
mem[count + (init_mult * 32)] = INIT_20[init_offset +:width];
mem[count + (init_mult * 33)] = INIT_21[init_offset +:width];
mem[count + (init_mult * 34)] = INIT_22[init_offset +:width];
mem[count + (init_mult * 35)] = INIT_23[init_offset +:width];
mem[count + (init_mult * 36)] = INIT_24[init_offset +:width];
mem[count + (init_mult * 37)] = INIT_25[init_offset +:width];
mem[count + (init_mult * 38)] = INIT_26[init_offset +:width];
mem[count + (init_mult * 39)] = INIT_27[init_offset +:width];
mem[count + (init_mult * 40)] = INIT_28[init_offset +:width];
mem[count + (init_mult * 41)] = INIT_29[init_offset +:width];
mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width];
mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width];
mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width];
mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width];
mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width];
mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width];
mem[count + (init_mult * 48)] = INIT_30[init_offset +:width];
mem[count + (init_mult * 49)] = INIT_31[init_offset +:width];
mem[count + (init_mult * 50)] = INIT_32[init_offset +:width];
mem[count + (init_mult * 51)] = INIT_33[init_offset +:width];
mem[count + (init_mult * 52)] = INIT_34[init_offset +:width];
mem[count + (init_mult * 53)] = INIT_35[init_offset +:width];
mem[count + (init_mult * 54)] = INIT_36[init_offset +:width];
mem[count + (init_mult * 55)] = INIT_37[init_offset +:width];
mem[count + (init_mult * 56)] = INIT_38[init_offset +:width];
mem[count + (init_mult * 57)] = INIT_39[init_offset +:width];
mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width];
mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width];
mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width];
mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width];
mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width];
mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width];
if (BRAM_SIZE == 36) begin
mem[count + (init_mult * 64)] = INIT_40[init_offset +:width];
mem[count + (init_mult * 65)] = INIT_41[init_offset +:width];
mem[count + (init_mult * 66)] = INIT_42[init_offset +:width];
mem[count + (init_mult * 67)] = INIT_43[init_offset +:width];
mem[count + (init_mult * 68)] = INIT_44[init_offset +:width];
mem[count + (init_mult * 69)] = INIT_45[init_offset +:width];
mem[count + (init_mult * 70)] = INIT_46[init_offset +:width];
mem[count + (init_mult * 71)] = INIT_47[init_offset +:width];
mem[count + (init_mult * 72)] = INIT_48[init_offset +:width];
mem[count + (init_mult * 73)] = INIT_49[init_offset +:width];
mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width];
mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width];
mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width];
mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width];
mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width];
mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width];
mem[count + (init_mult * 80)] = INIT_50[init_offset +:width];
mem[count + (init_mult * 81)] = INIT_51[init_offset +:width];
mem[count + (init_mult * 82)] = INIT_52[init_offset +:width];
mem[count + (init_mult * 83)] = INIT_53[init_offset +:width];
mem[count + (init_mult * 84)] = INIT_54[init_offset +:width];
mem[count + (init_mult * 85)] = INIT_55[init_offset +:width];
mem[count + (init_mult * 86)] = INIT_56[init_offset +:width];
mem[count + (init_mult * 87)] = INIT_57[init_offset +:width];
mem[count + (init_mult * 88)] = INIT_58[init_offset +:width];
mem[count + (init_mult * 89)] = INIT_59[init_offset +:width];
mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width];
mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width];
mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width];
mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width];
mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width];
mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width];
mem[count + (init_mult * 96)] = INIT_60[init_offset +:width];
mem[count + (init_mult * 97)] = INIT_61[init_offset +:width];
mem[count + (init_mult * 98)] = INIT_62[init_offset +:width];
mem[count + (init_mult * 99)] = INIT_63[init_offset +:width];
mem[count + (init_mult * 100)] = INIT_64[init_offset +:width];
mem[count + (init_mult * 101)] = INIT_65[init_offset +:width];
mem[count + (init_mult * 102)] = INIT_66[init_offset +:width];
mem[count + (init_mult * 103)] = INIT_67[init_offset +:width];
mem[count + (init_mult * 104)] = INIT_68[init_offset +:width];
mem[count + (init_mult * 105)] = INIT_69[init_offset +:width];
mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width];
mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width];
mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width];
mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width];
mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width];
mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width];
mem[count + (init_mult * 112)] = INIT_70[init_offset +:width];
mem[count + (init_mult * 113)] = INIT_71[init_offset +:width];
mem[count + (init_mult * 114)] = INIT_72[init_offset +:width];
mem[count + (init_mult * 115)] = INIT_73[init_offset +:width];
mem[count + (init_mult * 116)] = INIT_74[init_offset +:width];
mem[count + (init_mult * 117)] = INIT_75[init_offset +:width];
mem[count + (init_mult * 118)] = INIT_76[init_offset +:width];
mem[count + (init_mult * 119)] = INIT_77[init_offset +:width];
mem[count + (init_mult * 120)] = INIT_78[init_offset +:width];
mem[count + (init_mult * 121)] = INIT_79[init_offset +:width];
mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width];
mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width];
mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width];
mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width];
mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width];
mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width];
end // if (BRAM_SIZE == 36)
end // for (count = 0; count < init_mult; count = count + 1)
if (width >= 8) begin
initp_mult = 256/widthp;
for (countp = 0; countp < initp_mult; countp = countp + 1) begin
initp_offset = countp * widthp;
memp[countp] = INITP_00[initp_offset +:widthp];
memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp];
memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp];
memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp];
memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp];
memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp];
memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp];
memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp];
if (BRAM_SIZE == 36) begin
memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp];
memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp];
memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp];
memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp];
memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp];
memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp];
memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp];
memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp];
end
end // for (countp = 0; countp < initp_mult; countp = countp + 1)
end // if (width >= 8)
end // if (INIT_FILE == "NONE")
else begin // memory initialization from memory file
for (j = 0; j < mem_depth; j = j + 1) begin
for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin
tmp_mem[j][j1] = 1'b0;
end
end
$readmemh (INIT_FILE, tmp_mem);
case (widest_width)
1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1)
mem[i_mem] = tmp_mem [i_mem];
9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 8];
memp[i_mem] = tmp_mem[i_mem][8 +: 1];
end
18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 16];
memp[i_mem] = tmp_mem[i_mem][16 +: 2];
end
36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 32];
memp[i_mem] = tmp_mem[i_mem][32 +: 4];
end
72 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 64];
memp[i_mem] = tmp_mem[i_mem][64 +: 8];
end
endcase // case(widest_width)
end // else: !if(INIT_FILE == "NONE")
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int = 1;
"FALSE" : en_ecc_write_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int = 1;
"FALSE" : en_ecc_read_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
case (RAM_MODE)
"TDP" : begin
ram_mode_int = 1;
if (en_ecc_write_int == 1) begin
$display("DRC Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE);
finish_error = 1;
end
if (en_ecc_read_int == 1) begin
$display("DRC Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ);
finish_error = 1;
end
end // case: "TDP"
"SDP" : begin
ram_mode_int = 0;
if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin
$display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB18E1 instance %m.");
finish_error = 1;
end
if (BRAM_SIZE == 18) begin
if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP.");
finish_error = 1;
end
end
else begin
if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP.");
finish_error = 1;
end
end // else: !if(BRAM_SIZE == 18)
end // case: "SDP"
default : begin
$display("Attribute Syntax Error : The attribute RAM_MODE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE);
finish_error = 1;
end
endcase
case (WRITE_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_A)
case (WRITE_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_B)
case (READ_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_A)
case (READ_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_B)
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin
$display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB18E1 instance %m, both can not be 0.");
finish_error = 1;
end
case (WRITE_MODE_A)
"WRITE_FIRST" : wr_mode_a = 2'b00;
"READ_FIRST" : wr_mode_a = 2'b01;
"NO_CHANGE" : wr_mode_a = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
finish_error = 1;
end
endcase
case (WRITE_MODE_B)
"WRITE_FIRST" : wr_mode_b = 2'b00;
"READ_FIRST" : wr_mode_b = 2'b01;
"NO_CHANGE" : wr_mode_b = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_A)
"UPPER" : cascade_a = 2'b11;
"LOWER" : cascade_a = 2'b01;
"NONE" : cascade_a = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_B)
"UPPER" : cascade_b = 2'b11;
"LOWER" : cascade_b = 2'b01;
"NONE" : cascade_b = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B);
finish_error = 1;
end
endcase
if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin
$display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB18E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
finish_error = 1;
end
case (RSTREG_PRIORITY_A)
"RSTREG" : rstreg_priority_a_int = 1;
"REGCE" : rstreg_priority_a_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A);
finish_error = 1;
end
endcase
case (RSTREG_PRIORITY_B)
"RSTREG" : rstreg_priority_b_int = 1;
"REGCE" : rstreg_priority_b_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B);
finish_error = 1;
end
endcase
if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin
$display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB18E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE.");
finish_error = 1;
end
case (RDADDR_COLLISION_HWCONFIG)
"DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0;
"PERFORMANCE" : rdaddr_collision_hwconfig_int = 1;
default : begin
$display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB18E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG);
finish_error = 1;
end
endcase
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
$finish;
end // initial begin
// GSR
always @(gsr_in)
if (gsr_in) begin
assign doa_out = INIT_A[0 +: ra_width];
if (ra_width >= 8) begin
assign dopa_out = INIT_A[ra_width +: ra_widthp];
end
assign dob_out = INIT_B[0 +: rb_width];
if (rb_width >= 8) begin
assign dopb_out = INIT_B[rb_width +: rb_widthp];
end
assign dbiterr_out = 0;
assign sbiterr_out = 0;
assign rdaddrecc_out = 9'b0;
end
else begin
deassign doa_out;
deassign dopa_out;
deassign dob_out;
deassign dopb_out;
deassign dbiterr_out;
deassign sbiterr_out;
deassign rdaddrecc_out;
end
always @(time_clka_period or time_clkb_period) begin
if (time_clka_period != 0 && time_clkb_period != 0) begin
if (time_clka_period <= time_clkb_period) begin
if (time_clka_period <= SETUP_READ_FIRST) begin
time_period = time_clka_period;
end
else begin
time_period = SETUP_READ_FIRST;
end
end
else if (time_clkb_period <= SETUP_READ_FIRST)
time_period = time_clkb_period;
else
time_period = SETUP_READ_FIRST;
end
end
// registering signals
always @(posedge clka_in) begin
rising_clka = 1;
if ($time > 110000 && time_skew_a_flag == 0) begin
time_clka_period = $time - time_port_a;
time_skew_a_flag = 1;
end
if (ena_in === 1'b1) begin
time_port_a = $time;
addra_reg = addra_in;
wea_reg = wea_in;
dia_reg = dia_in;
dipa_reg = dipa_in;
ox_addra_reconstruct_reg = ox_addra_reconstruct;
end
end
always @(posedge clkb_in) begin
rising_clkb = 1;
if ($time > 110000 && time_skew_b_flag == 0) begin
time_clkb_period = $time - time_port_b;
time_skew_b_flag = 1;
end
if (enb_in === 1'b1) begin
time_port_b = $time;
addrb_reg = addrb_in;
web_reg = web_in;
enb_reg = enb_in;
dib_reg = dib_in;
dipb_reg = dipb_in;
ox_addrb_reconstruct_reg = ox_addrb_reconstruct;
end
end // always @ (posedge clkb_in)
// CLKA and CLKB
always @(posedge rising_clka or posedge rising_clkb) begin
// Registering addr[15] for cascade mode
if (rising_clka)
if (cascade_a[1])
addra_in_15_reg_bram = ~addra_in[15];
else
addra_in_15_reg_bram = addra_in[15];
if (rising_clkb)
if (cascade_b[1])
addrb_in_15_reg_bram = ~addrb_in[15];
else
addrb_in_15_reg_bram = addrb_in[15];
if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
/************************************* Collision starts *****************************************/
if (SIM_COLLISION_CHECK != "NONE") begin
if (gsr_in === 1'b0) begin
if (time_port_a > time_port_b) begin
if (time_port_a - time_port_b <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_a - time_port_b <= time_period) begin
viol_time = 2;
end
end
else begin
if (time_port_b - time_port_a <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_b - time_port_a <= time_period) begin
viol_time = 2;
end
end // else: !if(time_port_a > time_port_b)
if (ena_in === 1'b0 || enb_in === 1'b0)
viol_time = 0;
if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))
if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))
viol_time = 0;
if (viol_time != 0) begin
if (SIM_DEVICE == "VIRTEX6") begin
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b10, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b01;
chk_ox_msg = 1;
chk_ox_same_clk = 1;
if (time_port_a > time_port_b)
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
else if (time_port_b > time_port_a)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_ox_msg = 0;
chk_ox_same_clk = 0;
task_ox_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_ox_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if (rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, web_in, 8'hff, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b10, wea_in, 8'hff, di_x, di_x[7:0], addra_in, addrb_in);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && rising_clkb)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b10, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin
viol_type = 2'b10;
chk_ox_msg = 1;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
// get msg
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_ox_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b10, wea_in, 8'hff, di_x, di_x[7:0], addra_in, addrb_reg);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b11;
chk_ox_msg = 1;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
// get msg
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_ox_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, 8'hff, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, addrb_in);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // if (SIM_DEVICE == "VIRTEX6")
else begin // 7series
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_in, addrb_in, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if ((rising_clka && rising_clkb) || viol_time == 1)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_in, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, addrb_in, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // else: !if(SIM_DEVICE == "VIRTEX6")
end // if (viol_time != 0)
end // if (gsr_in === 1'b0)
if (SIM_COLLISION_CHECK == "WARNING_ONLY")
viol_time = 0;
end // if (SIM_COLLISION_CHECK != "NONE")
/*************************************** end collision ********************************/
end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00)))
/**************************** Port A ****************************************/
if (rising_clka) begin
// DRC
if (rstrama_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m.");
// end DRC
// registering addra_in[15] the second time
if (regcea_in)
addra_in_15_reg1 = addra_in_15_reg;
if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || rstrama_in == 1'b1))
if (cascade_a[1])
addra_in_15_reg = ~addra_in[15];
else
addra_in_15_reg = addra_in[15];
if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin
// SRVAL
if (rstrama_in === 1'b1) begin
doa_buf = SRVAL_A[0 +: ra_width];
doa_out = SRVAL_A[0 +: ra_width];
if (ra_width >= 8) begin
dopa_buf = SRVAL_A[ra_width +: ra_widthp];
dopa_out = SRVAL_A[ra_width +: ra_widthp];
end
end
if (viol_time == 0) begin
// Read first
if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
// ECC decode
if (ram_mode_int == 0 && en_ecc_read_int == 1) begin
dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf);
syndrome = dopr_ecc ^ dopa_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
doa_buf = dia_in_ecc_corrected;
dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dopa_buf = dipa_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(syndrome !== 0)
// output of rdaddrecc
rdaddrecc_out[8:0] <= addra_in[14:6];
end // if (ram_mode_int == 0 && en_ecc_read_int == 1)
end // if (wr_mode_a == 2'b01)
// Write
task_wr_ram_a (wea_in, dia_in, dipa_in, addra_in);
// Read if not read first
if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1))
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
end // if (viol_time == 0)
end // if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)))
end // if (rising_clka)
// end of port A
/************************************** port B ***************************************************************/
if (rising_clkb) begin
// DRC
if (rstramb_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m.");
if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin
if (injectsbiterr_in === 1)
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m.");
if (injectdbiterr_in === 1)
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m.");
end
// End DRC
if (regceb_in)
addrb_in_15_reg1 = addrb_in_15_reg;
if (enb_in && (wr_mode_b != 2'b10 || web_in[0] == 0 || rstramb_in == 1'b1))
if (cascade_b[1])
addrb_in_15_reg = ~addrb_in[15];
else
addrb_in_15_reg = addrb_in[15];
if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
// SRVAL
if (rstramb_in === 1'b1) begin
dob_buf = SRVAL_B[0 +: rb_width];
dob_out = SRVAL_B[0 +: rb_width];
if (rb_width >= 8) begin
dopb_buf = SRVAL_B[rb_width +: rb_widthp];
dopb_out = SRVAL_B[rb_width +: rb_widthp];
end
end
if (viol_time == 0) begin
// ECC encode
if (ram_mode_int == 0 && en_ecc_write_int == 1) begin
dip_ecc = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc;
dipb_in_ecc = dip_ecc;
end
else
dipb_in_ecc = dipb_in;
dib_in_ecc = dib_in;
// injecting error
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin // double bit
dib_in_ecc[30] = ~dib_in_ecc[30];
dib_in_ecc[62] = ~dib_in_ecc[62];
end
else if (injectsbiterr_in === 1) begin // single bit
dib_in_ecc[30] = ~dib_in_ecc[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
// Read first
if (wr_mode_b == 2'b01 && rstramb_in === 1'b0)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
// Write
task_wr_ram_b (web_in, dib_in_ecc, dipb_in_ecc, addrb_in);
// Read if not read first
if (wr_mode_b != 2'b01 && rstramb_in === 1'b0)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end // if (viol_time == 0)
end // if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0))
end // if (rising_clkb)
// end of port B
if (gsr_in == 1'b0) begin
// writing outputs of port A
if (ena_in && (rising_clka || viol_time != 0)) begin
if (rstrama_in === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))) begin
doa_out <= doa_buf;
if (ra_width >= 8)
dopa_out <= dopa_buf;
end
end
// writing outputs of port B
if (enb_in && (rising_clkb || viol_time != 0)) begin
if (rstramb_in === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))) begin
dob_out <= dob_buf;
if (rb_width >= 8)
dopb_out <= dopb_buf;
end
end
end // if (gsr_in == 1'b0)
viol_time = 0;
rising_clka = 0;
rising_clkb = 0;
viol_type = 2'b00;
col_wr_wr_msg = 1;
col_wra_rdb_msg = 1;
col_wrb_rda_msg = 1;
end // always @ (posedge rising_clka or posedge rising_clkb)
// ********* Cascade Port A ********
always @(posedge clka_in or cascadeina_in or addra_in_15_reg or doa_out or dopa_out) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin
doa_out_mux[0] = cascadeina_in;
end
else begin
doa_out_mux = doa_out;
if (ra_width >= 8)
dopa_out_mux = dopa_out;
end
end
// output register mode
always @(posedge clka_in or cascadeina_in or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin
doa_outreg_mux[0] = cascadeina_in;
end
else begin
doa_outreg_mux = doa_outreg;
if (ra_width >= 8)
dopa_outreg_mux = dopa_outreg;
end
end
// ********* Cascade Port B ********
always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg or dob_out or dopb_out) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin
dob_out_mux[0] = cascadeinb_in;
end
else begin
dob_out_mux = dob_out;
if (rb_width >= 8)
dopb_out_mux = dopb_out;
end
end
// output register mode
always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin
dob_outreg_mux[0] = cascadeinb_in;
end
else begin
dob_outreg_mux = dob_outreg;
if (rb_width >= 8)
dopb_outreg_mux = dopb_outreg;
end
end // always @ (posedge regclkb_in or cascadeinregb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg)
// ***** Output Registers **** Port A *****
always @(posedge clka_in or posedge gsr_in) begin
if (DOA_REG == 1) begin
if (gsr_in == 1'b1) begin
rdaddrecc_outreg <= 9'b0;
dbiterr_outreg <= 0;
sbiterr_outreg <= 0;
doa_outreg <= INIT_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= INIT_A[ra_width +: ra_widthp];
end
else if (gsr_in == 1'b0) begin
if (regcea_in === 1'b1) begin
dbiterr_outreg <= dbiterr_out;
sbiterr_outreg <= sbiterr_out;
rdaddrecc_outreg <= rdaddrecc_out;
end
if (rstreg_priority_a_int == 0) begin // Virtex5 behavior
if (regcea_in == 1'b1) begin
if (rstrega_in == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (rstrega_in == 1'b0) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end // if (regcea_in == 1'b1)
end // if (rstreg_priority_a_int == 1'b0)
else begin
if (rstrega_in == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (rstrega_in == 1'b0) begin
if (regcea_in == 1'b1) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end
end // else: !if(rstreg_priority_a_int == 1'b0)
end // if (gsr_in == 1'b0)
end // if (DOA_REG == 1)
end // always @ (posedge clka_in or posedge gsr_in)
always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin
case (DOA_REG)
0 : begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
rdaddrecc_out_out = rdaddrecc_out;
doa_out_out[0 +: ra_width] = doa_out_mux[0 +: ra_width];
if (ra_width >= 8)
dopa_out_out[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp];
end
1 : begin
dbiterr_out_out = dbiterr_outreg;
sbiterr_out_out = sbiterr_outreg;
doa_out_out[0 +: ra_width] = doa_outreg_mux[0 +: ra_width];
rdaddrecc_out_out = rdaddrecc_outreg;
if (ra_width >= 8)
dopa_out_out[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOA_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG);
$finish;
end
endcase
end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg)
// ***** Output Registers **** Port B *****
always @(posedge clkb_in or posedge gsr_in) begin
if (DOB_REG == 1) begin
if (gsr_in == 1'b1) begin
dob_outreg <= INIT_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= INIT_B[rb_width +: rb_widthp];
end
else if (gsr_in == 1'b0) begin
if (rstreg_priority_b_int == 0) begin // Virtex5 behavior
if (regceb_in == 1'b1) begin
if (rstregb_in == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (rstregb_in == 1'b0) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end // if (regceb_in == 1'b1)
end // if (rstreg_priority_b_int == 1'b0)
else begin
if (rstregb_in == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (rstregb_in == 1'b0) begin
if (regceb_in == 1'b1) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end
end // else: !if(rstreg_priority_b_int == 1'b0)
end // if (gsr_in == 1'b0)
end // if (DOB_REG == 1)
end // always @ (posedge clkb_in or posedge gsr_in)
always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin
case (DOB_REG)
0 : begin
dob_out_out[0 +: rb_width] = dob_out_mux[0 +: rb_width];
if (rb_width >= 8)
dopb_out_out[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp];
end
1 : begin
dob_out_out[0 +: rb_width] = dob_outreg_mux[0 +: rb_width];
if (rb_width >= 8)
dopb_out_out[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOB_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG);
$finish;
end
endcase
end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux)
endmodule // RB18_INTERNAL_VLOG
`endcelldefine
// end of RB18_INTERNAL_VLOG - Note: Not an user primitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMB18E2.v 0000664 0000000 0000000 00000340075 12327044266 0022514 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : RAMB18E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/28/2013 - intial from FIFO
// 03/09/2013 - update from various initial CR - collisions
// 03/22/2013 - sync5 yaml update, port ordering
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - revert NO_CHANGE fix
// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP
// 04/23/2013 - PR683925 - add invertible pin support.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAMB18E2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter integer DOA_REG = 1,
parameter integer DOB_REG = 1,
parameter ENADDRENA = "FALSE",
parameter ENADDRENB = "FALSE",
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [17:0] INIT_A = 18'h00000,
parameter [17:0] INIT_B = 18'h00000,
parameter INIT_FILE = "NONE",
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0,
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0,
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0,
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0,
parameter RDADDRCHANGEA = "FALSE",
parameter RDADDRCHANGEB = "FALSE",
parameter integer READ_WIDTH_A = 0,
parameter integer READ_WIDTH_B = 0,
parameter RSTREG_PRIORITY_A = "RSTREG",
parameter RSTREG_PRIORITY_B = "RSTREG",
parameter SIM_COLLISION_CHECK = "ALL",
parameter SLEEP_ASYNC = "FALSE",
parameter [17:0] SRVAL_A = 18'h00000,
parameter [17:0] SRVAL_B = 18'h00000,
parameter WRITE_MODE_A = "NO_CHANGE",
parameter WRITE_MODE_B = "NO_CHANGE",
parameter integer WRITE_WIDTH_A = 0,
parameter integer WRITE_WIDTH_B = 0
)(
output [15:0] CASDOUTA,
output [15:0] CASDOUTB,
output [1:0] CASDOUTPA,
output [1:0] CASDOUTPB,
output [15:0] DOUTADOUT,
output [15:0] DOUTBDOUT,
output [1:0] DOUTPADOUTP,
output [1:0] DOUTPBDOUTP,
input [13:0] ADDRARDADDR,
input [13:0] ADDRBWRADDR,
input ADDRENA,
input ADDRENB,
input CASDIMUXA,
input CASDIMUXB,
input [15:0] CASDINA,
input [15:0] CASDINB,
input [1:0] CASDINPA,
input [1:0] CASDINPB,
input CASDOMUXA,
input CASDOMUXB,
input CASDOMUXEN_A,
input CASDOMUXEN_B,
input CASOREGIMUXA,
input CASOREGIMUXB,
input CASOREGIMUXEN_A,
input CASOREGIMUXEN_B,
input CLKARDCLK,
input CLKBWRCLK,
input [15:0] DINADIN,
input [15:0] DINBDIN,
input [1:0] DINPADINP,
input [1:0] DINPBDINP,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input SLEEP,
input [1:0] WEA,
input [3:0] WEBWE
);
// define constants
localparam MODULE_NAME = "RAMB18E2";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
integer t_coll_min = 48;
integer t_coll_max = 2998;
localparam integer ADDR_WIDTH = 14;
localparam integer INIT_WIDTH = 36;
localparam integer D_WIDTH = 32;
localparam integer DP_WIDTH = 4;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_depth = 16384;
localparam memp_depth = 2048;
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam DOA_REG_0 = 1;
localparam DOA_REG_1 = 0;
localparam DOB_REG_0 = 1;
localparam DOB_REG_1 = 0;
localparam ENADDRENA_FALSE = 0;
localparam ENADDRENA_TRUE = 1;
localparam ENADDRENB_FALSE = 0;
localparam ENADDRENB_TRUE = 1;
localparam RDADDRCHANGEA_FALSE = 0;
localparam RDADDRCHANGEA_TRUE = 1;
localparam RDADDRCHANGEB_FALSE = 0;
localparam RDADDRCHANGEB_TRUE = 1;
localparam READ_WIDTH_A_0 = 1;
localparam READ_WIDTH_A_1 = 1;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_2 = 2;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_9 = 8;
localparam READ_WIDTH_B_0 = 1;
localparam READ_WIDTH_B_1 = 1;
localparam READ_WIDTH_B_18 = 16;
localparam READ_WIDTH_B_2 = 2;
localparam READ_WIDTH_B_4 = 4;
localparam READ_WIDTH_B_9 = 8;
localparam RSTREG_PRIORITY_A_REGCE = 1;
localparam RSTREG_PRIORITY_A_RSTREG = 0;
localparam RSTREG_PRIORITY_B_REGCE = 1;
localparam RSTREG_PRIORITY_B_RSTREG = 0;
localparam SIM_COLLISION_CHECK_ALL = 0;
localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1;
localparam SIM_COLLISION_CHECK_NONE = 2;
localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRITE_MODE_A_NO_CHANGE = 0;
localparam WRITE_MODE_A_READ_FIRST = 1;
localparam WRITE_MODE_A_WRITE_FIRST = 2;
localparam WRITE_MODE_B_NO_CHANGE = 0;
localparam WRITE_MODE_B_READ_FIRST = 1;
localparam WRITE_MODE_B_WRITE_FIRST = 2;
localparam WRITE_WIDTH_A_0 = 1;
localparam WRITE_WIDTH_A_1 = 1;
localparam WRITE_WIDTH_A_18 = 16;
localparam WRITE_WIDTH_A_2 = 2;
localparam WRITE_WIDTH_A_4 = 4;
localparam WRITE_WIDTH_A_9 = 8;
localparam WRITE_WIDTH_B_0 = 1;
localparam WRITE_WIDTH_B_1 = 1;
localparam WRITE_WIDTH_B_18 = 16;
localparam WRITE_WIDTH_B_2 = 2;
localparam WRITE_WIDTH_B_36 = 32;
localparam WRITE_WIDTH_B_4 = 4;
localparam WRITE_WIDTH_B_9 = 8;
`ifndef XIL_DR
localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [0:0] DOA_REG_REG = DOA_REG;
localparam [0:0] DOB_REG_REG = DOB_REG;
localparam [40:1] ENADDRENA_REG = ENADDRENA;
localparam [40:1] ENADDRENB_REG = ENADDRENB;
localparam [255:0] INITP_00_REG = INITP_00;
localparam [255:0] INITP_01_REG = INITP_01;
localparam [255:0] INITP_02_REG = INITP_02;
localparam [255:0] INITP_03_REG = INITP_03;
localparam [255:0] INITP_04_REG = INITP_04;
localparam [255:0] INITP_05_REG = INITP_05;
localparam [255:0] INITP_06_REG = INITP_06;
localparam [255:0] INITP_07_REG = INITP_07;
localparam [255:0] INIT_00_REG = INIT_00;
localparam [255:0] INIT_01_REG = INIT_01;
localparam [255:0] INIT_02_REG = INIT_02;
localparam [255:0] INIT_03_REG = INIT_03;
localparam [255:0] INIT_04_REG = INIT_04;
localparam [255:0] INIT_05_REG = INIT_05;
localparam [255:0] INIT_06_REG = INIT_06;
localparam [255:0] INIT_07_REG = INIT_07;
localparam [255:0] INIT_08_REG = INIT_08;
localparam [255:0] INIT_09_REG = INIT_09;
localparam [255:0] INIT_0A_REG = INIT_0A;
localparam [255:0] INIT_0B_REG = INIT_0B;
localparam [255:0] INIT_0C_REG = INIT_0C;
localparam [255:0] INIT_0D_REG = INIT_0D;
localparam [255:0] INIT_0E_REG = INIT_0E;
localparam [255:0] INIT_0F_REG = INIT_0F;
localparam [255:0] INIT_10_REG = INIT_10;
localparam [255:0] INIT_11_REG = INIT_11;
localparam [255:0] INIT_12_REG = INIT_12;
localparam [255:0] INIT_13_REG = INIT_13;
localparam [255:0] INIT_14_REG = INIT_14;
localparam [255:0] INIT_15_REG = INIT_15;
localparam [255:0] INIT_16_REG = INIT_16;
localparam [255:0] INIT_17_REG = INIT_17;
localparam [255:0] INIT_18_REG = INIT_18;
localparam [255:0] INIT_19_REG = INIT_19;
localparam [255:0] INIT_1A_REG = INIT_1A;
localparam [255:0] INIT_1B_REG = INIT_1B;
localparam [255:0] INIT_1C_REG = INIT_1C;
localparam [255:0] INIT_1D_REG = INIT_1D;
localparam [255:0] INIT_1E_REG = INIT_1E;
localparam [255:0] INIT_1F_REG = INIT_1F;
localparam [255:0] INIT_20_REG = INIT_20;
localparam [255:0] INIT_21_REG = INIT_21;
localparam [255:0] INIT_22_REG = INIT_22;
localparam [255:0] INIT_23_REG = INIT_23;
localparam [255:0] INIT_24_REG = INIT_24;
localparam [255:0] INIT_25_REG = INIT_25;
localparam [255:0] INIT_26_REG = INIT_26;
localparam [255:0] INIT_27_REG = INIT_27;
localparam [255:0] INIT_28_REG = INIT_28;
localparam [255:0] INIT_29_REG = INIT_29;
localparam [255:0] INIT_2A_REG = INIT_2A;
localparam [255:0] INIT_2B_REG = INIT_2B;
localparam [255:0] INIT_2C_REG = INIT_2C;
localparam [255:0] INIT_2D_REG = INIT_2D;
localparam [255:0] INIT_2E_REG = INIT_2E;
localparam [255:0] INIT_2F_REG = INIT_2F;
localparam [255:0] INIT_30_REG = INIT_30;
localparam [255:0] INIT_31_REG = INIT_31;
localparam [255:0] INIT_32_REG = INIT_32;
localparam [255:0] INIT_33_REG = INIT_33;
localparam [255:0] INIT_34_REG = INIT_34;
localparam [255:0] INIT_35_REG = INIT_35;
localparam [255:0] INIT_36_REG = INIT_36;
localparam [255:0] INIT_37_REG = INIT_37;
localparam [255:0] INIT_38_REG = INIT_38;
localparam [255:0] INIT_39_REG = INIT_39;
localparam [255:0] INIT_3A_REG = INIT_3A;
localparam [255:0] INIT_3B_REG = INIT_3B;
localparam [255:0] INIT_3C_REG = INIT_3C;
localparam [255:0] INIT_3D_REG = INIT_3D;
localparam [255:0] INIT_3E_REG = INIT_3E;
localparam [255:0] INIT_3F_REG = INIT_3F;
localparam [17:0] INIT_A_REG = INIT_A;
localparam [17:0] INIT_B_REG = INIT_B;
localparam INIT_FILE_REG = INIT_FILE;
localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED;
localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED;
localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED;
localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED;
localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED;
localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED;
localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED;
localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED;
localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA;
localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB;
localparam [5:0] READ_WIDTH_A_REG = READ_WIDTH_A;
localparam [4:0] READ_WIDTH_B_REG = READ_WIDTH_B;
localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A;
localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B;
localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [17:0] SRVAL_A_REG = SRVAL_A;
localparam [17:0] SRVAL_B_REG = SRVAL_B;
localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A;
localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B;
localparam [4:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A;
localparam [5:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B;
`endif
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire CLOCK_DOMAINS_BIN;
wire DOA_REG_BIN;
wire DOB_REG_BIN;
wire ENADDRENA_BIN;
wire ENADDRENB_BIN;
wire [255:0] INITP_BIN [0:7];
reg [255:0] INITP_TMP;
wire [255:0] INIT_BIN [0:63];
reg [255:0] INIT_TMP;
wire [INIT_WIDTH/2-1:0] INIT_A_BIN;
wire [INIT_WIDTH/2-1:0] INIT_B_BIN;
// wire INIT_FILE_BIN;
wire IS_CLKARDCLK_INVERTED_BIN;
wire IS_CLKBWRCLK_INVERTED_BIN;
wire IS_ENARDEN_INVERTED_BIN;
wire IS_ENBWREN_INVERTED_BIN;
wire IS_RSTRAMARSTRAM_INVERTED_BIN;
wire IS_RSTRAMB_INVERTED_BIN;
wire IS_RSTREGARSTREG_INVERTED_BIN;
wire IS_RSTREGB_INVERTED_BIN;
wire RDADDRCHANGEA_BIN;
wire RDADDRCHANGEB_BIN;
wire [5:0] READ_WIDTH_A_BIN;
wire [5:0] READ_WIDTH_B_BIN;
wire RSTREG_PRIORITY_A_BIN;
wire RSTREG_PRIORITY_B_BIN;
wire [1:0] SIM_COLLISION_CHECK_BIN;
wire SLEEP_ASYNC_BIN;
wire [INIT_WIDTH/2-1:0] SRVAL_A_BIN;
wire [INIT_WIDTH/2-1:0] SRVAL_B_BIN;
wire [1:0] WRITE_MODE_A_BIN;
wire [1:0] WRITE_MODE_B_BIN;
wire [6:0] WRITE_WIDTH_A_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
reg trig_gsr = 1'b0;
tri0 glblGSR = glbl.GSR || trig_gsr;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RAMB18E2_dr.v"
`endif
wire [D_WIDTH/2-1:0] CASDOUTA_out;
wire [D_WIDTH/2-1:0] CASDOUTB_out;
wire [DP_WIDTH/2-1:0] CASDOUTPA_out;
wire [DP_WIDTH/2-1:0] CASDOUTPB_out;
wire [D_WIDTH/2-1:0] DOUTADOUT_out;
wire [D_WIDTH/2-1:0] DOUTBDOUT_out;
wire [DP_WIDTH/2-1:0] DOUTPADOUTP_out;
wire [DP_WIDTH/2-1:0] DOUTPBDOUTP_out;
wire [15:0] CASDOUTA_delay;
wire [15:0] CASDOUTB_delay;
wire [15:0] DOUTADOUT_delay;
wire [15:0] DOUTBDOUT_delay;
wire [1:0] CASDOUTPA_delay;
wire [1:0] CASDOUTPB_delay;
wire [1:0] DOUTPADOUTP_delay;
wire [1:0] DOUTPBDOUTP_delay;
wire ADDRENA_in;
wire ADDRENB_in;
wire CASDIMUXA_in;
wire CASDIMUXB_in;
wire CASDOMUXA_in;
wire CASDOMUXB_in;
wire CASDOMUXEN_A_in;
wire CASDOMUXEN_B_in;
wire CASOREGIMUXA_in;
wire CASOREGIMUXB_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXEN_B_in;
wire CLKARDCLK_in;
wire CLKBWRCLK_in;
wire ENARDEN_in;
wire ENBWREN_in;
wire REGCEAREGCE_in;
wire REGCEB_in;
wire RSTRAMARSTRAM_in;
wire RSTRAMB_in;
wire RSTREGARSTREG_in;
wire RSTREGB_in;
wire SLEEP_in;
wire [13:0] ADDRARDADDR_in;
wire [13:0] ADDRBWRADDR_in;
wire [D_WIDTH/2-1:0] CASDINA_in;
wire [D_WIDTH/2-1:0] CASDINB_in;
wire [D_WIDTH/2-1:0] DINADIN_in;
wire [D_WIDTH/2-1:0] DINBDIN_in;
wire [1:0] CASDINPA_in;
wire [1:0] CASDINPB_in;
wire [DP_WIDTH/2-1:0] DINPADINP_in;
wire [DP_WIDTH/2-1:0] DINPBDINP_in;
wire [1:0] WEA_in;
wire [3:0] WEBWE_in;
wire ADDRENA_delay;
wire ADDRENB_delay;
wire CASDIMUXA_delay;
wire CASDIMUXB_delay;
wire CASDOMUXA_delay;
wire CASDOMUXB_delay;
wire CASDOMUXEN_A_delay;
wire CASDOMUXEN_B_delay;
wire CASOREGIMUXA_delay;
wire CASOREGIMUXB_delay;
wire CASOREGIMUXEN_A_delay;
wire CASOREGIMUXEN_B_delay;
wire CLKARDCLK_delay;
wire CLKBWRCLK_delay;
wire ENARDEN_delay;
wire ENBWREN_delay;
wire REGCEAREGCE_delay;
wire REGCEB_delay;
wire RSTRAMARSTRAM_delay;
wire RSTRAMB_delay;
wire RSTREGARSTREG_delay;
wire RSTREGB_delay;
wire SLEEP_delay;
wire [13:0] ADDRARDADDR_delay;
wire [13:0] ADDRBWRADDR_delay;
wire [15:0] CASDINA_delay;
wire [15:0] CASDINB_delay;
wire [15:0] DINADIN_delay;
wire [15:0] DINBDIN_delay;
wire [1:0] CASDINPA_delay;
wire [1:0] CASDINPB_delay;
wire [1:0] DINPADINP_delay;
wire [1:0] DINPBDINP_delay;
wire [1:0] WEA_delay;
wire [3:0] WEBWE_delay;
// internal variables, signals, busses
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer wb=0;
integer rb=0;
integer rbb=0;
integer wa=0;
integer rd_loops_a = 1;
integer wr_loops_a = 1;
integer rd_loops_b = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
reg INIT_MEM = 0;
wire SLEEP_int;
reg SLEEP_reg = 1'b0;
reg SLEEP_reg1 = 1'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire RSTREG_B_int;
wire REGCE_B_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
reg CASDOMUXB_reg = 1'b0;
reg CASOREGIMUXB_reg = 1'b0;
wire CASDOMUXB_int;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire [INIT_WIDTH/2-1:0] INIT_B_int;
wire [INIT_WIDTH/2-1:0] SRVAL_B_int;
wire mem_wr_clk_a;
wire mem_wr_en_a;
reg mem_wr_en_a_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_a;
wire [DP_WIDTH-1:0] memp_we_a;
wire [D_WIDTH/2-1:0] mem_rm_doutb;
wire [DP_WIDTH/2-1:0] memp_rm_doutb;
wire [D_WIDTH-1:0] mem_rm_a;
wire [D_WIDTH-1:0] mem_rm_b;
wire [D_WIDTH-1:0] mem_wm_a;
wire [D_WIDTH-1:0] mem_wm_b;
reg wr_data_matches = 0;
reg wr_a_data_matches_rd_b_data = 0;
reg wr_b_data_matches_rd_a_data = 0;
wire mem_wr_clk_b;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_clk_a;
wire mem_rd_en_a;
wire mem_rst_a;
wire mem_rd_clk_b;
wire mem_rd_en_b;
wire mem_rst_b;
reg mem [0 : mem_depth-1];
wire [D_WIDTH/2-1 : 0] mem_wr_a;
reg wr_a_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_a;
reg [D_WIDTH-1 : 0] mem_rd_a_rf;
reg [D_WIDTH-1 : 0] mem_rd_a_wf;
wire [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
wire [D_WIDTH-1 : 0] mem_a_reg_mux;
wire [D_WIDTH-1 : 0] mem_a_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
wire [D_WIDTH-1 : 0] mem_a_out;
reg [D_WIDTH/2-1 : 0] mem_b_reg;
wire [D_WIDTH/2-1 : 0] mem_b_reg_mux;
wire [D_WIDTH/2-1 : 0] mem_b_mux;
reg [D_WIDTH/2-1 : 0] mem_b_lat;
wire [D_WIDTH/2-1 : 0] mem_b_out;
reg memp [0 : memp_depth - 1];
wire [DP_WIDTH-1 : 0] memp_wr_a;
reg [DP_WIDTH-1 : 0] memp_rd_a;
reg [DP_WIDTH-1 : 0] memp_rd_a_rf;
reg [DP_WIDTH-1 : 0] memp_rd_a_wf;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
wire [DP_WIDTH-1 : 0] memp_a_reg_mux;
wire [DP_WIDTH-1 : 0] memp_a_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
wire [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH/2-1 : 0] memp_b_reg;
wire [DP_WIDTH/2-1 : 0] memp_b_reg_mux;
wire [DP_WIDTH/2-1 : 0] memp_b_mux;
reg [DP_WIDTH/2-1 : 0] memp_b_lat;
wire [DP_WIDTH/2-1 : 0] memp_b_out;
wire [ADDR_WIDTH-1:0] rd_addr_a_mask;
wire [ADDR_WIDTH-1:0] rd_addr_b_mask;
wire [ADDR_WIDTH-1:0] wr_addr_a_mask;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] rd_addr_b = 0;
reg [ADDR_WIDTH-1:0] wr_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
wire wr_a_rd_b_addr_coll;
wire wr_addr_coll;
wire wr_b_rd_a_addr_coll;
wire sdp_mode;
wire sdp_mode_wr;
wire sdp_mode_rd;
// clk period for collision window variables
integer t_max_a=3000, t_max_b=3000;
reg clka_done=1'b0, clkb_done=1'b0, clkb_toggled=1'b0;
reg clka_timeout=0, clkb_timeout=0;
wire clks_done;
reg en_clk_sync = 1'b0;
// input output assignments
assign #(out_delay) CASDOUTA = CASDOUTA_delay;
assign #(out_delay) CASDOUTB = CASDOUTB_delay;
assign #(out_delay) CASDOUTPA = CASDOUTPA_delay;
assign #(out_delay) CASDOUTPB = CASDOUTPB_delay;
assign #(out_delay) DOUTADOUT = DOUTADOUT_delay;
assign #(out_delay) DOUTBDOUT = DOUTBDOUT_delay;
assign #(out_delay) DOUTPADOUTP = DOUTPADOUTP_delay;
assign #(out_delay) DOUTPBDOUTP = DOUTPBDOUTP_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLKARDCLK_delay = CLKARDCLK;
assign #(inclk_delay) CLKBWRCLK_delay = CLKBWRCLK;
assign #(in_delay) ADDRARDADDR_delay = ADDRARDADDR;
assign #(in_delay) ADDRBWRADDR_delay = ADDRBWRADDR;
assign #(in_delay) ADDRENA_delay = ADDRENA;
assign #(in_delay) ADDRENB_delay = ADDRENB;
assign #(in_delay) CASDIMUXA_delay = CASDIMUXA;
assign #(in_delay) CASDIMUXB_delay = CASDIMUXB;
assign #(in_delay) CASDINA_delay = CASDINA;
assign #(in_delay) CASDINB_delay = CASDINB;
assign #(in_delay) CASDINPA_delay = CASDINPA;
assign #(in_delay) CASDINPB_delay = CASDINPB;
assign #(in_delay) CASDOMUXA_delay = CASDOMUXA;
assign #(in_delay) CASDOMUXB_delay = CASDOMUXB;
assign #(in_delay) CASDOMUXEN_A_delay = CASDOMUXEN_A;
assign #(in_delay) CASDOMUXEN_B_delay = CASDOMUXEN_B;
assign #(in_delay) CASOREGIMUXA_delay = CASOREGIMUXA;
assign #(in_delay) CASOREGIMUXB_delay = CASOREGIMUXB;
assign #(in_delay) CASOREGIMUXEN_A_delay = CASOREGIMUXEN_A;
assign #(in_delay) CASOREGIMUXEN_B_delay = CASOREGIMUXEN_B;
assign #(in_delay) DINADIN_delay = DINADIN;
assign #(in_delay) DINBDIN_delay = DINBDIN;
assign #(in_delay) DINPADINP_delay = DINPADINP;
assign #(in_delay) DINPBDINP_delay = DINPBDINP;
assign #(in_delay) ENARDEN_delay = ENARDEN;
assign #(in_delay) ENBWREN_delay = ENBWREN;
assign #(in_delay) REGCEAREGCE_delay = REGCEAREGCE;
assign #(in_delay) REGCEB_delay = REGCEB;
assign #(in_delay) RSTRAMARSTRAM_delay = RSTRAMARSTRAM;
assign #(in_delay) RSTRAMB_delay = RSTRAMB;
assign #(in_delay) RSTREGARSTREG_delay = RSTREGARSTREG;
assign #(in_delay) RSTREGB_delay = RSTREGB;
assign #(in_delay) SLEEP_delay = SLEEP;
assign #(in_delay) WEA_delay = WEA;
assign #(in_delay) WEBWE_delay = WEBWE;
`endif // `ifndef XIL_TIMING
assign CASDOUTA_delay = CASDOUTA_out;
assign CASDOUTB_delay = CASDOUTB_out;
assign CASDOUTPA_delay = CASDOUTPA_out;
assign CASDOUTPB_delay = CASDOUTPB_out;
assign DOUTADOUT_delay = DOUTADOUT_out;
assign DOUTBDOUT_delay = DOUTBDOUT_out;
assign DOUTPADOUTP_delay = DOUTPADOUTP_out;
assign DOUTPBDOUTP_delay = DOUTPBDOUTP_out;
assign ADDRARDADDR_in = ADDRARDADDR_delay;
assign ADDRBWRADDR_in = ADDRBWRADDR_delay;
assign ADDRENA_in = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_delay : 1'b1;
assign ADDRENB_in = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_delay : 1'b1;
assign CASDIMUXA_in = CASDIMUXA_delay;
assign CASDIMUXB_in = CASDIMUXB_delay;
assign CASDINA_in = CASDINA_delay;
assign CASDINB_in = CASDINB_delay;
assign CASDINPA_in = CASDINPA_delay;
assign CASDINPB_in = CASDINPB_delay;
assign CASDOMUXA_in = CASDOMUXA_delay;
assign CASDOMUXB_in = CASDOMUXB_delay;
assign CASDOMUXEN_A_in = CASDOMUXEN_A_delay;
assign CASDOMUXEN_B_in = CASDOMUXEN_B_delay;
assign CASOREGIMUXA_in = CASOREGIMUXA_delay;
assign CASOREGIMUXB_in = CASOREGIMUXB_delay;
assign CASOREGIMUXEN_A_in = CASOREGIMUXEN_A_delay;
assign CASOREGIMUXEN_B_in = CASOREGIMUXEN_B_delay;
assign CLKARDCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT) ||
(en_clk_sync == 1'b0) || (clkb_toggled == 1'b0)) ?
CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN :
CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN;
assign CLKBWRCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT) ||
(en_clk_sync == 1'b0) || (clkb_toggled == 1'b1) ||
(clka_done == 1'b0)) ?
CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN :
CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN;
assign DINPADINP_in = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXA_in) ?
CASDINPA_delay : DINPADINP_delay;
assign DINADIN_in = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXA_in) ?
CASDINA_delay : DINADIN_delay;
assign DINPBDINP_in = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXB_in) ?
CASDINPB_delay : DINPBDINP_delay;
assign DINBDIN_in = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXB_in) ?
CASDINB_delay : DINBDIN_delay;
assign ENARDEN_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN;
assign ENBWREN_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN;
assign REGCEAREGCE_in = REGCEAREGCE_delay;
assign REGCEB_in = REGCEB_delay;
assign RSTRAMARSTRAM_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN;
assign RSTRAMB_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN;
assign RSTREGARSTREG_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN;
assign RSTREGB_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN;
assign SLEEP_in = SLEEP_delay;
assign WEA_in = WEA_delay;
assign WEBWE_in = WEBWE_delay;
assign mem_rd_clk_a = CLKARDCLK_in;
assign mem_rd_clk_b = sdp_mode ? 1'b0 : CLKBWRCLK_in;
assign mem_wr_clk_a = sdp_mode ? 1'b0 : CLKARDCLK_in;
assign mem_wr_clk_b = CLKBWRCLK_in;
assign mem_rst_a = RSTRAMARSTRAM_in;
assign mem_rst_b = sdp_mode ? RSTRAMARSTRAM_in : RSTRAMB_in;
assign mem_wr_a = {16'h0, DINADIN_in};
assign mem_wr_b = (WRITE_WIDTH_B_BIN != WRITE_WIDTH_B_36) ? {16'h0, DINBDIN_in} :
{DINBDIN_in, DINADIN_in};
assign mem_wr_en_a = sdp_mode ? 1'b0 : ENARDEN_in && |WEA_in;
assign mem_rd_en_a = (WRITE_MODE_A_BIN == WRITE_MODE_A_NO_CHANGE) ?
ENARDEN_in && (~mem_wr_en_a || mem_rst_a) : ENARDEN_in;
assign mem_wr_en_b = ENBWREN_in && (sdp_mode ? |WEBWE_in : |WEBWE_in[DP_WIDTH/2-1:0]);
assign mem_rd_en_b = sdp_mode ? 1'b0 :
(WRITE_MODE_B_BIN == WRITE_MODE_B_NO_CHANGE) ?
ENBWREN_in && (~mem_wr_en_b || mem_rst_b) : ENBWREN_in;
assign memp_wr_b[3] = DINPBDINP_in[1];
assign memp_wr_b[2] = DINPBDINP_in[0];
assign memp_wr_b[1] = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_36) ? DINPADINP_in[1] : DINPBDINP_in[1];
assign memp_wr_b[0] = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_36) ? DINPADINP_in[0] : DINPBDINP_in[0];
assign memp_wr_a[3] = 1'b0;
assign memp_wr_a[2] = 1'b0;
assign memp_wr_a[1] = DINPADINP_in[1];
assign memp_wr_a[0] = DINPADINP_in[0];
initial begin
trig_attr <= #1 ~trig_attr;
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
CASCADE_ORDER_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign DOA_REG_BIN =
(DOA_REG_REG == 1) ? DOA_REG_1 :
(DOA_REG_REG == 0) ? DOA_REG_0 :
DOA_REG_1;
assign DOB_REG_BIN =
(DOB_REG_REG == 1) ? DOB_REG_1 :
(DOB_REG_REG == 0) ? DOB_REG_0 :
DOB_REG_1;
assign ENADDRENA_BIN =
(ENADDRENA_REG == "FALSE") ? ENADDRENA_FALSE :
(ENADDRENA_REG == "TRUE") ? ENADDRENA_TRUE :
ENADDRENA_FALSE;
assign ENADDRENB_BIN =
(ENADDRENB_REG == "FALSE") ? ENADDRENB_FALSE :
(ENADDRENB_REG == "TRUE") ? ENADDRENB_TRUE :
ENADDRENB_FALSE;
assign INITP_BIN['h00] = INITP_00_REG;
assign INITP_BIN['h01] = INITP_01_REG;
assign INITP_BIN['h02] = INITP_02_REG;
assign INITP_BIN['h03] = INITP_03_REG;
assign INITP_BIN['h04] = INITP_04_REG;
assign INITP_BIN['h05] = INITP_05_REG;
assign INITP_BIN['h06] = INITP_06_REG;
assign INITP_BIN['h07] = INITP_07_REG;
assign INIT_BIN['h00] = INIT_00_REG;
assign INIT_BIN['h01] = INIT_01_REG;
assign INIT_BIN['h02] = INIT_02_REG;
assign INIT_BIN['h03] = INIT_03_REG;
assign INIT_BIN['h04] = INIT_04_REG;
assign INIT_BIN['h05] = INIT_05_REG;
assign INIT_BIN['h06] = INIT_06_REG;
assign INIT_BIN['h07] = INIT_07_REG;
assign INIT_BIN['h08] = INIT_08_REG;
assign INIT_BIN['h09] = INIT_09_REG;
assign INIT_BIN['h0A] = INIT_0A_REG;
assign INIT_BIN['h0B] = INIT_0B_REG;
assign INIT_BIN['h0C] = INIT_0C_REG;
assign INIT_BIN['h0D] = INIT_0D_REG;
assign INIT_BIN['h0E] = INIT_0E_REG;
assign INIT_BIN['h0F] = INIT_0F_REG;
assign INIT_BIN['h10] = INIT_10_REG;
assign INIT_BIN['h11] = INIT_11_REG;
assign INIT_BIN['h12] = INIT_12_REG;
assign INIT_BIN['h13] = INIT_13_REG;
assign INIT_BIN['h14] = INIT_14_REG;
assign INIT_BIN['h15] = INIT_15_REG;
assign INIT_BIN['h16] = INIT_16_REG;
assign INIT_BIN['h17] = INIT_17_REG;
assign INIT_BIN['h18] = INIT_18_REG;
assign INIT_BIN['h19] = INIT_19_REG;
assign INIT_BIN['h1A] = INIT_1A_REG;
assign INIT_BIN['h1B] = INIT_1B_REG;
assign INIT_BIN['h1C] = INIT_1C_REG;
assign INIT_BIN['h1D] = INIT_1D_REG;
assign INIT_BIN['h1E] = INIT_1E_REG;
assign INIT_BIN['h1F] = INIT_1F_REG;
assign INIT_BIN['h20] = INIT_20_REG;
assign INIT_BIN['h21] = INIT_21_REG;
assign INIT_BIN['h22] = INIT_22_REG;
assign INIT_BIN['h23] = INIT_23_REG;
assign INIT_BIN['h24] = INIT_24_REG;
assign INIT_BIN['h25] = INIT_25_REG;
assign INIT_BIN['h26] = INIT_26_REG;
assign INIT_BIN['h27] = INIT_27_REG;
assign INIT_BIN['h28] = INIT_28_REG;
assign INIT_BIN['h29] = INIT_29_REG;
assign INIT_BIN['h2A] = INIT_2A_REG;
assign INIT_BIN['h2B] = INIT_2B_REG;
assign INIT_BIN['h2C] = INIT_2C_REG;
assign INIT_BIN['h2D] = INIT_2D_REG;
assign INIT_BIN['h2E] = INIT_2E_REG;
assign INIT_BIN['h2F] = INIT_2F_REG;
assign INIT_BIN['h30] = INIT_30_REG;
assign INIT_BIN['h31] = INIT_31_REG;
assign INIT_BIN['h32] = INIT_32_REG;
assign INIT_BIN['h33] = INIT_33_REG;
assign INIT_BIN['h34] = INIT_34_REG;
assign INIT_BIN['h35] = INIT_35_REG;
assign INIT_BIN['h36] = INIT_36_REG;
assign INIT_BIN['h37] = INIT_37_REG;
assign INIT_BIN['h38] = INIT_38_REG;
assign INIT_BIN['h39] = INIT_39_REG;
assign INIT_BIN['h3A] = INIT_3A_REG;
assign INIT_BIN['h3B] = INIT_3B_REG;
assign INIT_BIN['h3C] = INIT_3C_REG;
assign INIT_BIN['h3D] = INIT_3D_REG;
assign INIT_BIN['h3E] = INIT_3E_REG;
assign INIT_BIN['h3F] = INIT_3F_REG;
assign INIT_A_BIN = INIT_A_REG;
assign INIT_B_BIN = INIT_B_REG;
// assign INIT_FILE_BIN =
// (INIT_FILE_REG == "NONE") ? INIT_FILE_NONE :
// INIT_FILE_NONE;
assign IS_CLKARDCLK_INVERTED_BIN = IS_CLKARDCLK_INVERTED_REG;
assign IS_CLKBWRCLK_INVERTED_BIN = IS_CLKBWRCLK_INVERTED_REG;
assign IS_ENARDEN_INVERTED_BIN = IS_ENARDEN_INVERTED_REG;
assign IS_ENBWREN_INVERTED_BIN = IS_ENBWREN_INVERTED_REG;
assign IS_RSTRAMARSTRAM_INVERTED_BIN = IS_RSTRAMARSTRAM_INVERTED_REG;
assign IS_RSTRAMB_INVERTED_BIN = IS_RSTRAMB_INVERTED_REG;
assign IS_RSTREGARSTREG_INVERTED_BIN = IS_RSTREGARSTREG_INVERTED_REG;
assign IS_RSTREGB_INVERTED_BIN = IS_RSTREGB_INVERTED_REG;
assign RDADDRCHANGEA_BIN =
(RDADDRCHANGEA_REG == "FALSE") ? RDADDRCHANGEA_FALSE :
(RDADDRCHANGEA_REG == "TRUE") ? RDADDRCHANGEA_TRUE :
RDADDRCHANGEA_FALSE;
assign RDADDRCHANGEB_BIN =
(RDADDRCHANGEB_REG == "FALSE") ? RDADDRCHANGEB_FALSE :
(RDADDRCHANGEB_REG == "TRUE") ? RDADDRCHANGEB_TRUE :
RDADDRCHANGEB_FALSE;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_A_REG == 0) ? READ_WIDTH_A_0 :
(READ_WIDTH_A_REG == 1) ? READ_WIDTH_A_1 :
(READ_WIDTH_A_REG == 2) ? READ_WIDTH_A_2 :
(READ_WIDTH_A_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_A_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_A_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_A_REG == 36) ? READ_WIDTH_A_36 :
READ_WIDTH_A_0;
assign READ_WIDTH_B_BIN =
(READ_WIDTH_B_REG == 0) ? READ_WIDTH_B_0 :
(READ_WIDTH_B_REG == 1) ? READ_WIDTH_B_1 :
(READ_WIDTH_B_REG == 2) ? READ_WIDTH_B_2 :
(READ_WIDTH_B_REG == 4) ? READ_WIDTH_B_4 :
(READ_WIDTH_B_REG == 9) ? READ_WIDTH_B_9 :
(READ_WIDTH_B_REG == 18) ? READ_WIDTH_B_18 :
READ_WIDTH_B_0;
assign RSTREG_PRIORITY_A_BIN =
(RSTREG_PRIORITY_A_REG == "RSTREG") ? RSTREG_PRIORITY_A_RSTREG :
(RSTREG_PRIORITY_A_REG == "REGCE") ? RSTREG_PRIORITY_A_REGCE :
RSTREG_PRIORITY_A_RSTREG;
assign RSTREG_PRIORITY_B_BIN =
(RSTREG_PRIORITY_B_REG == "RSTREG") ? RSTREG_PRIORITY_B_RSTREG :
(RSTREG_PRIORITY_B_REG == "REGCE") ? RSTREG_PRIORITY_B_REGCE :
RSTREG_PRIORITY_B_RSTREG;
assign SIM_COLLISION_CHECK_BIN =
(SIM_COLLISION_CHECK_REG == "ALL") ? SIM_COLLISION_CHECK_ALL :
(SIM_COLLISION_CHECK_REG == "GENERATE_X_ONLY") ? SIM_COLLISION_CHECK_GENERATE_X_ONLY :
(SIM_COLLISION_CHECK_REG == "NONE") ? SIM_COLLISION_CHECK_NONE :
(SIM_COLLISION_CHECK_REG == "WARNING_ONLY") ? SIM_COLLISION_CHECK_WARNING_ONLY :
SIM_COLLISION_CHECK_ALL;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_A_BIN = SRVAL_A_REG;
assign SRVAL_B_BIN = SRVAL_B_REG;
assign WRITE_MODE_A_BIN =
(WRITE_MODE_A_REG == "NO_CHANGE") ? WRITE_MODE_A_NO_CHANGE :
(WRITE_MODE_A_REG == "READ_FIRST") ? WRITE_MODE_A_READ_FIRST :
(WRITE_MODE_A_REG == "WRITE_FIRST") ? WRITE_MODE_A_WRITE_FIRST :
WRITE_MODE_A_NO_CHANGE;
assign WRITE_MODE_B_BIN =
(WRITE_MODE_B_REG == "NO_CHANGE") ? WRITE_MODE_B_NO_CHANGE :
(WRITE_MODE_B_REG == "READ_FIRST") ? WRITE_MODE_B_READ_FIRST :
(WRITE_MODE_B_REG == "WRITE_FIRST") ? WRITE_MODE_B_WRITE_FIRST :
WRITE_MODE_B_NO_CHANGE;
assign WRITE_WIDTH_A_BIN =
(WRITE_WIDTH_A_REG == 0) ? WRITE_WIDTH_A_0 :
(WRITE_WIDTH_A_REG == 1) ? WRITE_WIDTH_A_1 :
(WRITE_WIDTH_A_REG == 2) ? WRITE_WIDTH_A_2 :
(WRITE_WIDTH_A_REG == 4) ? WRITE_WIDTH_A_4 :
(WRITE_WIDTH_A_REG == 9) ? WRITE_WIDTH_A_9 :
(WRITE_WIDTH_A_REG == 18) ? WRITE_WIDTH_A_18 :
WRITE_WIDTH_A_0;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_B_REG == 0) ? WRITE_WIDTH_B_0 :
(WRITE_WIDTH_B_REG == 1) ? WRITE_WIDTH_B_1 :
(WRITE_WIDTH_B_REG == 2) ? WRITE_WIDTH_B_2 :
(WRITE_WIDTH_B_REG == 4) ? WRITE_WIDTH_B_4 :
(WRITE_WIDTH_B_REG == 9) ? WRITE_WIDTH_B_9 :
(WRITE_WIDTH_B_REG == 18) ? WRITE_WIDTH_B_18 :
(WRITE_WIDTH_B_REG == 36) ? WRITE_WIDTH_B_36 :
WRITE_WIDTH_B_0;
always @ (trig_attr) begin
#1;
if ((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER_A on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE.", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER_B on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE.", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON")) begin
$display("Attribute Syntax Error : The attribute CLOCK_DOMAINS on %s instance %m is set to %s. Legal values for this attribute are INDEPENDENT or COMMON.", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((DOA_REG_REG != 1) &&
(DOA_REG_REG != 0)) begin
$display("Attribute Syntax Error : The attribute DOA_REG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DOA_REG_REG);
attr_err = 1'b1;
end
if ((DOB_REG_REG != 1) &&
(DOB_REG_REG != 0)) begin
$display("Attribute Syntax Error : The attribute DOB_REG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DOB_REG_REG);
attr_err = 1'b1;
end
if ((ENADDRENA_REG != "FALSE") &&
(ENADDRENA_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ENADDRENA on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ENADDRENA_REG);
attr_err = 1'b1;
end
if ((ENADDRENB_REG != "FALSE") &&
(ENADDRENB_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ENADDRENB on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ENADDRENB_REG);
attr_err = 1'b1;
end
if (INIT_FILE_REG != "NONE") begin
$display("INFO : The attribute INIT_FILE on %s instance %m is set to (%s) but loading memory contents from a file is not yet supported.", MODULE_NAME, INIT_FILE_REG);
end
if ((IS_CLKARDCLK_INVERTED_REG < 1'b0) || (IS_CLKARDCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLKARDCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLKBWRCLK_INVERTED_REG < 1'b0) || (IS_CLKBWRCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLKBWRCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_ENARDEN_INVERTED_REG < 1'b0) || (IS_ENARDEN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_ENARDEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_ENBWREN_INVERTED_REG < 1'b0) || (IS_ENBWREN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_ENBWREN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTRAMARSTRAM_INVERTED_REG < 1'b0) || (IS_RSTRAMARSTRAM_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTRAMARSTRAM_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTRAMB_INVERTED_REG < 1'b0) || (IS_RSTRAMB_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTRAMB_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREGARSTREG_INVERTED_REG < 1'b0) || (IS_RSTREGARSTREG_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREGARSTREG_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREGB_INVERTED_REG < 1'b0) || (IS_RSTREGB_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREGB_INVERTED_REG);
attr_err = 1'b1;
end
if ((RDADDRCHANGEA_REG != "FALSE") &&
(RDADDRCHANGEA_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RDADDRCHANGEA on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RDADDRCHANGEA_REG);
attr_err = 1'b1;
end
if ((RDADDRCHANGEB_REG != "FALSE") &&
(RDADDRCHANGEB_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RDADDRCHANGEB on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RDADDRCHANGEB_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_A_REG != 0) &&
(READ_WIDTH_A_REG != 1) &&
(READ_WIDTH_A_REG != 2) &&
(READ_WIDTH_A_REG != 4) &&
(READ_WIDTH_A_REG != 9) &&
(READ_WIDTH_A_REG != 18) &&
(READ_WIDTH_A_REG != 36)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", MODULE_NAME, READ_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_B_REG != 0) &&
(READ_WIDTH_B_REG != 1) &&
(READ_WIDTH_B_REG != 2) &&
(READ_WIDTH_B_REG != 4) &&
(READ_WIDTH_B_REG != 9) &&
(READ_WIDTH_B_REG != 18)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", MODULE_NAME, READ_WIDTH_B_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_A_REG != "RSTREG") &&
(RSTREG_PRIORITY_A_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_A_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_B_REG != "RSTREG") &&
(RSTREG_PRIORITY_B_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_B_REG);
attr_err = 1'b1;
end
if ((SIM_COLLISION_CHECK_REG != "ALL") &&
(SIM_COLLISION_CHECK_REG != "GENERATE_X_ONLY") &&
(SIM_COLLISION_CHECK_REG != "NONE") &&
(SIM_COLLISION_CHECK_REG != "WARNING_ONLY")) begin
$display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on %s instance %m is set to %s. Legal values for this attribute are ALL, GENERATE_X_ONLY, NONE or WARNING_ONLY.", MODULE_NAME, SIM_COLLISION_CHECK_REG);
attr_err = 1'b1;
end
if ((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SLEEP_ASYNC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((WRITE_MODE_A_REG != "NO_CHANGE") &&
(WRITE_MODE_A_REG != "READ_FIRST") &&
(WRITE_MODE_A_REG != "WRITE_FIRST")) begin
$display("Attribute Syntax Error : The attribute WRITE_MODE_A on %s instance %m is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST.", MODULE_NAME, WRITE_MODE_A_REG);
attr_err = 1'b1;
end
if ((WRITE_MODE_B_REG != "NO_CHANGE") &&
(WRITE_MODE_B_REG != "READ_FIRST") &&
(WRITE_MODE_B_REG != "WRITE_FIRST")) begin
$display("Attribute Syntax Error : The attribute WRITE_MODE_B on %s instance %m is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST.", MODULE_NAME, WRITE_MODE_B_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_A_REG != 0) &&
(WRITE_WIDTH_A_REG != 1) &&
(WRITE_WIDTH_A_REG != 2) &&
(WRITE_WIDTH_A_REG != 4) &&
(WRITE_WIDTH_A_REG != 9) &&
(WRITE_WIDTH_A_REG != 18)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", MODULE_NAME, WRITE_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_B_REG != 0) &&
(WRITE_WIDTH_B_REG != 1) &&
(WRITE_WIDTH_B_REG != 2) &&
(WRITE_WIDTH_B_REG != 4) &&
(WRITE_WIDTH_B_REG != 9) &&
(WRITE_WIDTH_B_REG != 18) &&
(WRITE_WIDTH_B_REG != 36)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", MODULE_NAME, WRITE_WIDTH_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign rd_addr_a_mask =
(READ_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign rd_addr_b_mask =
(READ_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_a_mask =
(WRITE_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_b_mask =
(WRITE_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(READ_WIDTH_B_BIN) rd_loops_b <= READ_WIDTH_B_BIN;
always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
// determine clk period for collision window.
assign clks_done = clka_done && clkb_done;
//always @(negedge glblGSR) begin
initial begin
@(negedge glblGSR);
clka_timeout = 0;
clka_timeout <= #6000 1;
@(posedge mem_rd_clk_a or posedge clka_timeout);
if (~clka_timeout) begin
t_max_a = 0;
for (i=0;i<2000;i=i+1) begin
if (~clka_done) begin
if (mem_rd_clk_a) begin
#1;
t_max_a = t_max_a + 1;
end
else begin
t_max_a = t_max_a - 1;
clka_done = 1;
i = 2000;
end
end
end
end
clka_done = 1;
end
initial begin
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
clkb_toggled = 1'b1;
end
initial begin
@(negedge glblGSR);
clkb_timeout = 0;
clkb_timeout <= #6000 1;
@(posedge CLKBWRCLK_in or posedge clkb_timeout);
if (~clkb_timeout) begin
t_max_b = 0;
for (j=0;j<2000;j=j+1) begin
if (~clkb_done) begin
if (CLKBWRCLK_in) begin
#1;
t_max_b = t_max_b + 1;
end
else begin
t_max_b = t_max_b - 1;
clkb_done = 1;
j = 2000;
end
end
end
end
clkb_done = 1;
end
initial begin
@(posedge clks_done);
if (((t_max_a > 50) && (t_max_a < 1500)) &&
((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 2;
if (((t_max_b > 50) && (t_max_b < 1500)) &&
((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 2;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
SLEEP_reg <= 1'b0;
SLEEP_reg1 <= 1'b0;
end
else begin
SLEEP_reg <= SLEEP_in;
SLEEP_reg1 <= SLEEP_reg;
end
end
assign SLEEP_int = (SLEEP_ASYNC_BIN == SLEEP_ASYNC_FALSE) ? SLEEP_reg : SLEEP_in;
assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_36) ? 1'b1 : 1'b0;
assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? 1'b1 : 1'b0;
assign sdp_mode = sdp_mode_rd || sdp_mode_wr;
// assign REGCE_A_int = mem_rd_en_a && REGCEAREGCE_in;
// assign REGCE_B_int = mem_rd_en_b && REGCEB_in;
assign REGCE_A_int = REGCEAREGCE_in;
assign REGCE_B_int = REGCEB_in;
assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ?
RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in);
assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ?
RSTREGB_in : (RSTREGB_in && REGCEB_in);
assign DOUTADOUT_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINA_in : (mem_a_mux ^ mem_rm_douta);
assign DOUTPADOUTP_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINPA_in : (memp_a_mux ^ memp_rm_douta);
assign DOUTBDOUT_out = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXB_int) ?
CASDINB_in : (mem_b_mux ^ mem_rm_doutb);
assign DOUTPBDOUTP_out = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXB_int) ?
CASDINPB_in : (memp_b_mux ^ memp_rm_doutb);
assign mem_a_mux = (DOA_REG_BIN == DOA_REG_1) ? mem_a_reg : mem_a_out;
assign memp_a_mux = (DOA_REG_BIN == DOA_REG_1) ? memp_a_reg : memp_a_out;
assign mem_a_out = mem_wr_en_a_wf ? mem_rd_a_wf : mem_a_lat;
assign memp_a_out = mem_wr_en_a_wf ? memp_rd_a_wf : memp_a_lat;
assign mem_b_out = mem_wr_en_b_wf ? mem_rd_b_wf : mem_b_lat;
assign memp_b_out = mem_wr_en_b_wf ? memp_rd_b_wf : memp_b_lat;
assign mem_b_mux = sdp_mode_rd ?
((DOA_REG_BIN == DOA_REG_1) ? mem_a_reg[31:16] : mem_a_out[31:16]) :
((DOB_REG_BIN == DOB_REG_1) ? mem_b_reg : mem_b_out);
assign memp_b_mux = sdp_mode_rd ?
((DOA_REG_BIN == DOA_REG_1) ? memp_a_reg[3:2] : memp_a_out[3:2]) :
((DOB_REG_BIN == DOB_REG_1) ? memp_b_reg : memp_b_out);
assign INIT_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{4{INIT_A_BIN[8]}}, {4{INIT_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{2{INIT_A_BIN[17:16]}}, {2{INIT_A_BIN[15:0]}}} :
{INIT_B_BIN[17:16],INIT_A_BIN[17:16],INIT_B_BIN[15:0],INIT_A_BIN[15:0]};
assign INIT_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{2{INIT_B_BIN[8]}}, {2{INIT_B_BIN[7:0]}}} :
INIT_B_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{4{SRVAL_A_BIN[8]}}, {4{SRVAL_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{2{SRVAL_A_BIN[17:16]}}, {2{SRVAL_A_BIN[15:0]}}} :
{SRVAL_B_BIN[17:16],SRVAL_A_BIN[17:16],SRVAL_B_BIN[15:0],SRVAL_A_BIN[15:0]};
assign SRVAL_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{2{SRVAL_B_BIN[8]}}, {2{SRVAL_B_BIN[7:0]}}} :
SRVAL_B_BIN;
// cascade out
assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTADOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTBDOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}};
// start model internals
// cascade control
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_36) ?
CASDOMUXA_reg : CASDOMUXB_reg;
always @ (posedge mem_rd_clk_b) begin
if (glblGSR) CASDOMUXB_reg <= 1'b0;
else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in;
end
always @ (posedge mem_rd_clk_b) begin
if (glblGSR) CASOREGIMUXB_reg <= 1'b0;
else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in;
end
// collison detection
wire coll_win_wr_clk_a_min;
wire coll_win_wr_clk_b_min;
wire coll_win_rd_clk_a_min;
wire coll_win_rd_clk_b_min;
reg coll_win_wr_clk_a_ind_min = 1'b0;
reg coll_win_wr_clk_b_ind_min = 1'b0;
reg coll_win_rd_clk_a_ind_min = 1'b0;
reg coll_win_rd_clk_b_ind_min = 1'b0;
reg coll_win_wr_clk_a_max = 1'b0;
reg coll_win_wr_clk_b_max = 1'b0;
reg coll_win_rd_clk_a_max = 1'b0;
reg coll_win_rd_clk_b_max = 1'b0;
wire mem_wr_clk_a_coll;
wire mem_wr_clk_b_coll;
wire mem_rd_clk_a_coll;
wire mem_rd_clk_b_coll;
reg wr_b_wr_a_coll = 1'b0;
reg wr_b_rd_a_coll = 1'b0;
reg rd_b_wr_a_coll = 1'b0;
reg wr_a_wr_b_coll = 1'b0;
reg wr_a_rd_b_coll = 1'b0;
reg rd_a_wr_b_coll = 1'b0;
wire coll_wr_sim;
wire coll_wr_b_wr_a;
wire coll_wr_b_rd_a_sim;
wire coll_wr_b_rd_a;
wire coll_rd_b_wr_a_sim;
wire coll_rd_b_wr_a;
wire coll_wr_a_wr_b;
wire coll_wr_a_rd_b_sim;
wire coll_wr_a_rd_b;
wire coll_rd_a_wr_b_sim;
wire coll_rd_a_wr_b;
//assign coll_win_wr_clk_a_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_wr_en_a : coll_win_wr_clk_a_ind_min;
//assign coll_win_wr_clk_b_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_wr_en_b : coll_win_wr_clk_b_ind_min;
//assign coll_win_rd_clk_a_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_rd_en_a : coll_win_rd_clk_a_ind_min;
//assign coll_win_rd_clk_b_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_rd_en_b : coll_win_rd_clk_b_ind_min;
assign coll_win_wr_clk_a_min = coll_win_wr_clk_a_ind_min;
assign coll_win_wr_clk_b_min = coll_win_wr_clk_b_ind_min;
assign coll_win_rd_clk_a_min = coll_win_rd_clk_a_ind_min;
assign coll_win_rd_clk_b_min = coll_win_rd_clk_b_ind_min;
assign mem_wr_clk_a_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_wr_clk_a;
assign mem_wr_clk_b_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_wr_clk_b;
assign mem_rd_clk_a_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_rd_clk_a;
assign mem_rd_clk_b_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_rd_clk_b;
assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min;
assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min;
assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max;
assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min;
assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min;
assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max;
assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min;
assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
always @(posedge mem_wr_clk_a_coll) begin
if (mem_wr_en_a === 1'b1) begin
coll_win_wr_clk_a_ind_min <= 1'b1;
coll_win_wr_clk_a_max <= #50 1'b1;
coll_win_wr_clk_a_ind_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_sim) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_wr_b) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge mem_wr_clk_b_coll) begin
if (mem_wr_en_b === 1'b1) begin
coll_win_wr_clk_b_ind_min <= 1'b1;
coll_win_wr_clk_b_max <= #50 1'b1;
coll_win_wr_clk_b_ind_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_b_wr_a) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge mem_rd_clk_a_coll) begin
if (mem_rd_en_a === 1'b1) begin
coll_win_rd_clk_a_ind_min <= 1'b1;
coll_win_rd_clk_a_max <= #50 1'b1;
coll_win_rd_clk_a_ind_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_a_wr_b_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_a_wr_b) begin
if (~wr_b_data_matches_rd_a_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge mem_rd_clk_b_coll) begin
if (mem_rd_en_b === 1'b1) begin
coll_win_rd_clk_b_ind_min <= 1'b1;
coll_win_rd_clk_b_max <= #50 1'b1;
coll_win_rd_clk_b_ind_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_b_wr_a_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h).", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_b_wr_a) begin
if (~wr_a_data_matches_rd_b_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
// output register
assign mem_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? {CASDINB_in, CASDINA_in} : mem_a_out;
assign memp_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? {CASDINPB_in, CASDINPA_in} : memp_a_out;
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= mem_a_reg_mux;
memp_a_reg <= memp_a_reg_mux;
end
end
assign mem_b_reg_mux = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXB_reg) ? CASDINB_in : mem_b_out;
assign memp_b_reg_mux = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXB_reg) ? CASDINPB_in : memp_b_out;
always @ (posedge mem_rd_clk_b or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_b_reg, mem_b_reg} <= INIT_B_int;
end
else if (RSTREG_B_int) begin
{memp_b_reg, mem_b_reg} <= SRVAL_B_int;
end
else if (REGCE_B_int) begin
mem_b_reg <= mem_b_reg_mux;
memp_b_reg <= memp_b_reg_mux;
end
end
// read engine
always @ (posedge mem_wr_clk_a) begin
if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && mem_rd_en_a) begin
mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a;
end
end
always @ (posedge mem_wr_clk_b) begin
if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b) begin
mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b;
end
end
always @ (wr_a_event or INIT_MEM) begin
if (~coll_rd_a_wr_b && ~coll_rd_a_wr_b_sim
&& ~coll_wr_b_rd_a && ~coll_wr_b_rd_a_sim) begin
for (raa=0;raa> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_a) begin
$display("DRC Error : READ on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (ra=0;ra> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if (rd_a_wr_b_coll) begin
if (~wr_b_data_matches_rd_a_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (ra=0;ra> rb;
if (rb> (D_WIDTH/2+rb);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_b) begin
$display("DRC Error : READ on port B attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (rb=0;rb> rb;
if (rb> (D_WIDTH/2+rb);
end
end
end
else if (rd_b_wr_a_coll) begin
if (~wr_a_data_matches_rd_b_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (rb=0;rb>(max_rd_loops-rd_loops_a);
assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b);
assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a);
assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b);
assign wr_a_rd_b_addr_coll = ~sdp_mode && ((wr_addr_a & rd_addr_b_mask) == (rd_addr_b & wr_addr_a_mask)) && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b;
assign wr_addr_coll = ~sdp_mode && ((wr_addr_a & wr_addr_b_mask) == (wr_addr_b & wr_addr_a_mask)) && mem_wr_en_b && mem_wr_en_a;
assign wr_b_rd_a_addr_coll = ((wr_addr_b & rd_addr_a_mask) == (rd_addr_a & wr_addr_b_mask)) && mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a;
assign mem_we_a = {{D_WIDTH/2{1'b0}},{8{WEA_in[1]}},{8{WEA_in[0]}}} & ({D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a));
assign mem_we_b = {{8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}} & ({D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b));
assign memp_we_a = (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) ? {2'b0,WEA_in} : 4'b0;
assign memp_we_b = (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) ? WEBWE_in : 4'b0;
specify
( CASDINA *> CASDOUTA) = (0:0:0, 0:0:0);
( CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0);
( CASDINB *> CASDOUTB) = (0:0:0, 0:0:0);
( CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0);
( CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0);
( CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0);
( CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTA) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTB) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTPA) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTADOUT) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTPADOUTP) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
( CLKBWRCLK *> CASDOUTB) = (0:0:0, 0:0:0);
( CLKBWRCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
( CLKBWRCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CLKBWRCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKARDCLK, 0:0:0, notifier);
$period (negedge CLKBWRCLK, 0:0:0, notifier);
$period (posedge CLKARDCLK, 0:0:0, notifier);
$period (posedge CLKBWRCLK, 0:0:0, notifier);
$setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMB36E1.v 0000664 0000000 0000000 00000750547 12327044266 0022524 0 ustar 00root root 0000000 0000000 // $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2008 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
// /___/ /\ Filename : RAMB36E1.v
// \ \ / \ Timestamp : Tue Feb 26 13:49:08 PST 2008
// \___\/\___\
//
// Revision:
// 02/26/08 - Initial version.
// 07/25/08 - Fixed ECC in register mode. (IR 477257)
// 07/30/08 - Updated to support SDP mode with smaller port width <= 36. (IR 477258)
// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964)
// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976).
// 11/20/08 - Changed RDADDRECC[12:0] to [8:0] (IR 496907).
// 03/11/09 - X's the unused bits of outputs (CR 511363).
// 03/12/09 - Removed parameter from specify block (CR 503821).
// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167).
// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450).
// 04/17/09 - Implemented X's in sbiterr and dbiterr outputs during collision in ECC mode (CR 508071).
// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327).
// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010).
// 11/16/09 - Implemented DRC for ADDR[15] in non-cascade mode (CR 535882).
// 11/18/09 - Define tasks and functions before calling (CR 532610).
// 11/24/09 - Undo CR 535882, bitgen or map is going to tie off ADDR[15] instead.
// 12/16/09 - Enhanced memory initialization (CR 540764).
// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010).
// 04/01/10 - Fixed clocks detection for collision (CR 552123).
// 05/11/10 - Updated clocks detection for collision (CR 557624).
// - Added attribute RDADDR_COLLISION_HWCONFIG (CR 557971).
// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807).
// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971).
// 07/08/10 - Added SIM_DEVICE attribute (CR 567633).
// 07/09/10 - Fixed INJECTSBITERR and INJECTDBITERR behaviors (CR 565234).
// 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672).
// 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924).
// 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953).
// 12/10/10 - Converted parameter to wire in specify block (CR 574534).
// 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053).
// 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004).
// 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942).
// 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942).
// 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129).
// 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482).
// 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399).
// 02/23/12 - Fixed SDP mode when write width is 32 and read width is 64 (CR 647335).
// 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454).
// 03/15/12 - Reverted CR 584399 (CR 651279).
// 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934).
// 07/25/13 - Added invertible pins support (CR 715417).
// 09/04/13 - Removed warning for memp (CR 728988).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMB36E1 (CASCADEOUTA, CASCADEOUTB, DBITERR, DOADO, DOBDO, DOPADOP, DOPBDOP, ECCPARITY, RDADDRECC, SBITERR,
ADDRARDADDR, ADDRBWRADDR, CASCADEINA, CASCADEINB, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
localparam SETUP_ALL = 1000;
localparam SETUP_READ_FIRST = 3000;
output CASCADEOUTA;
output CASCADEOUTB;
output [31:0] DOADO;
output [31:0] DOBDO;
output [3:0] DOPADOP;
output [3:0] DOPBDOP;
output [7:0] ECCPARITY;
output [8:0] RDADDRECC;
output SBITERR, DBITERR;
input ENARDEN, CLKARDCLK, RSTRAMARSTRAM, RSTREGARSTREG, CASCADEINA, REGCEAREGCE;
input ENBWREN, CLKBWRCLK, RSTRAMB, RSTREGB, CASCADEINB, REGCEB;
input INJECTDBITERR, INJECTSBITERR;
input [15:0] ADDRARDADDR;
input [15:0] ADDRBWRADDR;
input [31:0] DIADI;
input [31:0] DIBDI;
input [3:0] DIPADIP;
input [3:0] DIPBDIP;
input [3:0] WEA;
input [7:0] WEBWE;
tri0 GSR = glbl.GSR;
wire [3:0] dangle_out4;
wire [31:0] dangle_out32;
wire [31:0] doado_wire, dobdo_wire;
wire [3:0] dopadop_wire, dopbdop_wire;
wire cascadeouta_wire, cascadeoutb_wire;
reg [31:0] doado_out, dobdo_out;
reg [3:0] dopadop_out, dopbdop_out;
reg cascadeouta_out, cascadeoutb_out;
reg notifier, notifier_a, notifier_b;
reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4;
reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9;
reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13, notifier_addra14;
reg notifier_addra15;
reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4;
reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9;
reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13, notifier_addrb14;
reg notifier_addrb15;
reg attr_err = 1'b0;
wire clkardclk_in;
wire clkbwrclk_in;
wire enarden_in;
wire enbwren_in;
wire rstramarstram_in;
wire rstramb_in;
wire rstregarstreg_in;
wire rstregb_in;
assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED;
assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED;
assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED;
assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED;
assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED;
assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED;
assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED;
assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED;
initial begin
if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED);
attr_err = 1'b1;
end
if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB36E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end // initial begin
// special handle for sdp width = 72 and < 72
// localparam init_sdp = (READ_WIDTH_A == 72) ? {INIT_B[35:32],INIT_A[35:32],INIT_B[31:0],INIT_A[31:0]} : {INIT_B, INIT_A};
// localparam srval_sdp = (READ_WIDTH_A == 72) ? {SRVAL_B[35:32],SRVAL_A[35:32],SRVAL_B[31:0],SRVAL_A[31:0]} : {SRVAL_B, SRVAL_A};
// Fixing iverilog problem
localparam init_sdp = (READ_WIDTH_A == 72) ?
(((INIT_B & 36'hf00000000)<<68) |
((INIT_A & 36'hf00000000)<<64) |
((INIT_B & 32'hffffffff)<<32) |
(INIT_A & 32'hffffffff)) :
{INIT_B, INIT_A};
localparam srval_sdp = (READ_WIDTH_A == 72) ?
(((SRVAL_B & 36'hf00000000)<<68) |
((SRVAL_A & 36'hf00000000)<<64) |
((SRVAL_B & 32'hffffffff)<<32) |
(SRVAL_A & 32'hffffffff)):
{SRVAL_B, SRVAL_A};
generate
case (RAM_MODE)
"TDP" : begin
RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_FILE(INIT_FILE),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.RAM_EXTENSION_A(RAM_EXTENSION_A),
.RAM_EXTENSION_B(RAM_EXTENSION_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.EN_ECC_READ(EN_ECC_READ),
.EN_ECC_WRITE(EN_ECC_WRITE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INIT_40(INIT_40),
.INIT_41(INIT_41),
.INIT_42(INIT_42),
.INIT_43(INIT_43),
.INIT_44(INIT_44),
.INIT_45(INIT_45),
.INIT_46(INIT_46),
.INIT_47(INIT_47),
.INIT_48(INIT_48),
.INIT_49(INIT_49),
.INIT_4A(INIT_4A),
.INIT_4B(INIT_4B),
.INIT_4C(INIT_4C),
.INIT_4D(INIT_4D),
.INIT_4E(INIT_4E),
.INIT_4F(INIT_4F),
.INIT_50(INIT_50),
.INIT_51(INIT_51),
.INIT_52(INIT_52),
.INIT_53(INIT_53),
.INIT_54(INIT_54),
.INIT_55(INIT_55),
.INIT_56(INIT_56),
.INIT_57(INIT_57),
.INIT_58(INIT_58),
.INIT_59(INIT_59),
.INIT_5A(INIT_5A),
.INIT_5B(INIT_5B),
.INIT_5C(INIT_5C),
.INIT_5D(INIT_5D),
.INIT_5E(INIT_5E),
.INIT_5F(INIT_5F),
.INIT_60(INIT_60),
.INIT_61(INIT_61),
.INIT_62(INIT_62),
.INIT_63(INIT_63),
.INIT_64(INIT_64),
.INIT_65(INIT_65),
.INIT_66(INIT_66),
.INIT_67(INIT_67),
.INIT_68(INIT_68),
.INIT_69(INIT_69),
.INIT_6A(INIT_6A),
.INIT_6B(INIT_6B),
.INIT_6C(INIT_6C),
.INIT_6D(INIT_6D),
.INIT_6E(INIT_6E),
.INIT_6F(INIT_6F),
.INIT_70(INIT_70),
.INIT_71(INIT_71),
.INIT_72(INIT_72),
.INIT_73(INIT_73),
.INIT_74(INIT_74),
.INIT_75(INIT_75),
.INIT_76(INIT_76),
.INIT_77(INIT_77),
.INIT_78(INIT_78),
.INIT_79(INIT_79),
.INIT_7A(INIT_7A),
.INIT_7B(INIT_7B),
.INIT_7C(INIT_7C),
.INIT_7D(INIT_7D),
.INIT_7E(INIT_7E),
.INIT_7F(INIT_7F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07),
.INITP_08(INITP_08),
.INITP_09(INITP_09),
.INITP_0A(INITP_0A),
.INITP_0B(INITP_0B),
.INITP_0C(INITP_0C),
.INITP_0D(INITP_0D),
.INITP_0E(INITP_0E),
.INITP_0F(INITP_0F))
INT_RAMB_TDP (.ADDRA(ADDRARDADDR),
.ADDRB(ADDRBWRADDR),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(cascadeouta_wire),
.CASCADEOUTB(cascadeoutb_wire),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(DBITERR),
.DIA({32'b0,DIADI}),
.DIB({32'b0,DIBDI}),
.DIPA(DIPADIP),
.DIPB({4'b0,DIPBDIP}),
.DOA({dangle_out32,doado_wire}),
.DOB(dobdo_wire),
.DOPA({dangle_out4,dopadop_wire}),
.DOPB(dopbdop_wire),
.ECCPARITY(ECCPARITY),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(RDADDRECC),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(SBITERR),
.WEA({2{WEA}}),
.WEB(WEBWE));
end // case: "TDP"
"SDP" : begin
if (WRITE_WIDTH_B == 72) begin
RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A(init_sdp),
.INIT_B(init_sdp),
.INIT_FILE(INIT_FILE),
.SRVAL_A(srval_sdp),
.SRVAL_B(srval_sdp),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.RAM_EXTENSION_A(RAM_EXTENSION_A),
.RAM_EXTENSION_B(RAM_EXTENSION_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.EN_ECC_READ(EN_ECC_READ),
.EN_ECC_WRITE(EN_ECC_WRITE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INIT_40(INIT_40),
.INIT_41(INIT_41),
.INIT_42(INIT_42),
.INIT_43(INIT_43),
.INIT_44(INIT_44),
.INIT_45(INIT_45),
.INIT_46(INIT_46),
.INIT_47(INIT_47),
.INIT_48(INIT_48),
.INIT_49(INIT_49),
.INIT_4A(INIT_4A),
.INIT_4B(INIT_4B),
.INIT_4C(INIT_4C),
.INIT_4D(INIT_4D),
.INIT_4E(INIT_4E),
.INIT_4F(INIT_4F),
.INIT_50(INIT_50),
.INIT_51(INIT_51),
.INIT_52(INIT_52),
.INIT_53(INIT_53),
.INIT_54(INIT_54),
.INIT_55(INIT_55),
.INIT_56(INIT_56),
.INIT_57(INIT_57),
.INIT_58(INIT_58),
.INIT_59(INIT_59),
.INIT_5A(INIT_5A),
.INIT_5B(INIT_5B),
.INIT_5C(INIT_5C),
.INIT_5D(INIT_5D),
.INIT_5E(INIT_5E),
.INIT_5F(INIT_5F),
.INIT_60(INIT_60),
.INIT_61(INIT_61),
.INIT_62(INIT_62),
.INIT_63(INIT_63),
.INIT_64(INIT_64),
.INIT_65(INIT_65),
.INIT_66(INIT_66),
.INIT_67(INIT_67),
.INIT_68(INIT_68),
.INIT_69(INIT_69),
.INIT_6A(INIT_6A),
.INIT_6B(INIT_6B),
.INIT_6C(INIT_6C),
.INIT_6D(INIT_6D),
.INIT_6E(INIT_6E),
.INIT_6F(INIT_6F),
.INIT_70(INIT_70),
.INIT_71(INIT_71),
.INIT_72(INIT_72),
.INIT_73(INIT_73),
.INIT_74(INIT_74),
.INIT_75(INIT_75),
.INIT_76(INIT_76),
.INIT_77(INIT_77),
.INIT_78(INIT_78),
.INIT_79(INIT_79),
.INIT_7A(INIT_7A),
.INIT_7B(INIT_7B),
.INIT_7C(INIT_7C),
.INIT_7D(INIT_7D),
.INIT_7E(INIT_7E),
.INIT_7F(INIT_7F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07),
.INITP_08(INITP_08),
.INITP_09(INITP_09),
.INITP_0A(INITP_0A),
.INITP_0B(INITP_0B),
.INITP_0C(INITP_0C),
.INITP_0D(INITP_0D),
.INITP_0E(INITP_0E),
.INITP_0F(INITP_0F))
INT_RAMB_SDP (.ADDRA(ADDRARDADDR),
.ADDRB(ADDRBWRADDR),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(cascadeouta_wire),
.CASCADEOUTB(cascadeoutb_wire),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(DBITERR),
.DIA(64'b0),
.DIB({DIBDI,DIADI}),
.DIPA(4'b0),
.DIPB({DIPBDIP,DIPADIP}),
.DOA({dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(ECCPARITY),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(INJECTDBITERR),
.INJECTSBITERR(INJECTSBITERR),
.RDADDRECC(RDADDRECC),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(SBITERR),
.WEA(8'b0),
.WEB(WEBWE));
end // if (WRITE_WIDTH_B == 72)
else begin
RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE),
.INIT_A(init_sdp),
.INIT_B(init_sdp),
.INIT_FILE(INIT_FILE),
.SRVAL_A(srval_sdp),
.SRVAL_B(srval_sdp),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_A),
.WRITE_WIDTH_A(WRITE_WIDTH_B),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.RAM_EXTENSION_A(RAM_EXTENSION_A),
.RAM_EXTENSION_B(RAM_EXTENSION_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.SETUP_ALL(SETUP_ALL),
.SETUP_READ_FIRST(SETUP_READ_FIRST),
.SIM_COLLISION_CHECK(SIM_COLLISION_CHECK),
.SIM_DEVICE(SIM_DEVICE),
.EN_ECC_READ(EN_ECC_READ),
.EN_ECC_WRITE(EN_ECC_WRITE),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.INIT_40(INIT_40),
.INIT_41(INIT_41),
.INIT_42(INIT_42),
.INIT_43(INIT_43),
.INIT_44(INIT_44),
.INIT_45(INIT_45),
.INIT_46(INIT_46),
.INIT_47(INIT_47),
.INIT_48(INIT_48),
.INIT_49(INIT_49),
.INIT_4A(INIT_4A),
.INIT_4B(INIT_4B),
.INIT_4C(INIT_4C),
.INIT_4D(INIT_4D),
.INIT_4E(INIT_4E),
.INIT_4F(INIT_4F),
.INIT_50(INIT_50),
.INIT_51(INIT_51),
.INIT_52(INIT_52),
.INIT_53(INIT_53),
.INIT_54(INIT_54),
.INIT_55(INIT_55),
.INIT_56(INIT_56),
.INIT_57(INIT_57),
.INIT_58(INIT_58),
.INIT_59(INIT_59),
.INIT_5A(INIT_5A),
.INIT_5B(INIT_5B),
.INIT_5C(INIT_5C),
.INIT_5D(INIT_5D),
.INIT_5E(INIT_5E),
.INIT_5F(INIT_5F),
.INIT_60(INIT_60),
.INIT_61(INIT_61),
.INIT_62(INIT_62),
.INIT_63(INIT_63),
.INIT_64(INIT_64),
.INIT_65(INIT_65),
.INIT_66(INIT_66),
.INIT_67(INIT_67),
.INIT_68(INIT_68),
.INIT_69(INIT_69),
.INIT_6A(INIT_6A),
.INIT_6B(INIT_6B),
.INIT_6C(INIT_6C),
.INIT_6D(INIT_6D),
.INIT_6E(INIT_6E),
.INIT_6F(INIT_6F),
.INIT_70(INIT_70),
.INIT_71(INIT_71),
.INIT_72(INIT_72),
.INIT_73(INIT_73),
.INIT_74(INIT_74),
.INIT_75(INIT_75),
.INIT_76(INIT_76),
.INIT_77(INIT_77),
.INIT_78(INIT_78),
.INIT_79(INIT_79),
.INIT_7A(INIT_7A),
.INIT_7B(INIT_7B),
.INIT_7C(INIT_7C),
.INIT_7D(INIT_7D),
.INIT_7E(INIT_7E),
.INIT_7F(INIT_7F),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07),
.INITP_08(INITP_08),
.INITP_09(INITP_09),
.INITP_0A(INITP_0A),
.INITP_0B(INITP_0B),
.INITP_0C(INITP_0C),
.INITP_0D(INITP_0D),
.INITP_0E(INITP_0E),
.INITP_0F(INITP_0F))
INT_RAMB_SDP (.ADDRA(ADDRARDADDR),
.ADDRB(ADDRBWRADDR),
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
.CASCADEOUTA(cascadeouta_wire),
.CASCADEOUTB(cascadeoutb_wire),
.CLKA(clkardclk_in),
.CLKB(clkbwrclk_in),
.DBITERR(DBITERR),
.DIA(64'b0),
.DIB({32'b0,DIBDI}),
.DIPA(4'b0),
.DIPB({4'b0,DIPBDIP}),
.DOA({dobdo_wire,doado_wire}),
.DOB(dangle_out32),
.DOPA({dopbdop_wire,dopadop_wire}),
.DOPB(dangle_out4),
.ECCPARITY(ECCPARITY),
.ENA(enarden_in),
.ENB(enbwren_in),
.GSR(GSR),
.INJECTDBITERR(INJECTDBITERR),
.INJECTSBITERR(INJECTSBITERR),
.RDADDRECC(RDADDRECC),
.REGCEA(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMA(rstramarstram_in),
.RSTRAMB(rstramb_in),
.RSTREGA(rstregarstreg_in),
.RSTREGB(rstregb_in),
.SBITERR(SBITERR),
.WEA(8'b0),
.WEB(WEBWE));
end // else: !if(WRITE_WIDTH_B == 72)
end // case: "SDP"
endcase // case(RAM_MODE)
endgenerate
//*** Timing Checks Start here
always @(doado_wire or clkardclk_in) doado_out = doado_wire;
always @(dobdo_wire or clkbwrclk_in) dobdo_out = dobdo_wire;
always @(dopadop_wire or clkardclk_in) dopadop_out = dopadop_wire;
always @(dopbdop_wire or clkbwrclk_in) dopbdop_out = dopbdop_wire;
always @(cascadeouta_wire or clkardclk_in) cascadeouta_out = cascadeouta_wire;
always @(cascadeoutb_wire or clkbwrclk_in) cascadeoutb_out = cascadeoutb_wire;
assign DOADO = doado_out;
assign DOBDO = dobdo_out;
assign DOPADOP = dopadop_out;
assign DOPBDOP = dopbdop_out;
assign CASCADEOUTA = cascadeouta_out;
assign CASCADEOUTB = cascadeoutb_out;
`ifdef XIL_TIMING
wire diadi0_enable = (RAM_MODE == "TDP") && enarden_in && WEA[0];
wire diadi1_enable = (RAM_MODE == "TDP") && enarden_in && WEA[1];
wire diadi2_enable = (RAM_MODE == "TDP") && enarden_in && WEA[2];
wire diadi3_enable = (RAM_MODE == "TDP") && enarden_in && WEA[3];
wire dibdi0_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[0]) : (enbwren_in && WEBWE[4]) ;
wire dibdi1_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[1]) : (enbwren_in && WEBWE[5]) ;
wire dibdi2_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[2]) : (enbwren_in && WEBWE[6]) ;
wire dibdi3_enable = (RAM_MODE == "TDP") ? (enbwren_in && WEBWE[3]) : (enbwren_in && WEBWE[7]) ;
wire sdp_dia0_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[0];
wire sdp_dia1_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[1];
wire sdp_dia2_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[2];
wire sdp_dia3_clkwr = (RAM_MODE == "SDP") && enbwren_in && WEBWE[3];
always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or
notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or
notifier_addra11 or notifier_addra12 or notifier_addra13 or notifier_addra14 or notifier_addra15) begin
doado_out <= 32'hxxxxxxxx;
dopadop_out <= 4'hx;
cascadeouta_out <= 1'bx;
end
always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or
notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or
notifier_addrb11 or notifier_addrb12 or notifier_addrb13 or notifier_addrb14 or notifier_addrb15) begin
dobdo_out <= 32'hxxxxxxxx;
dopbdop_out <= 4'hx;
cascadeoutb_out <= 1'bx;
if (RAM_MODE == "SDP") begin
doado_out <= 32'hxxxxxxxx;
dopadop_out <= 4'hx;
cascadeouta_out <= 1'bx;
end
end
always @(notifier_addra0) begin
task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK");
end
always @(notifier_addra1) begin
task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK");
end
always @(notifier_addra2) begin
task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK");
end
always @(notifier_addra3) begin
task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK");
end
always @(notifier_addra4) begin
task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK");
end
always @(notifier_addra5) begin
task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK");
end
always @(notifier_addra6) begin
task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK");
end
always @(notifier_addra7) begin
task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK");
end
always @(notifier_addra8) begin
task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK");
end
always @(notifier_addra9) begin
task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK");
end
always @(notifier_addra10) begin
task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK");
end
always @(notifier_addra11) begin
task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK");
end
always @(notifier_addra12) begin
task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK");
end
always @(notifier_addra13) begin
task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK");
end
always @(notifier_addra14) begin
task_warn_msg ("ADDRARDADDR[14]", "CLKARDCLK");
end
always @(notifier_addra15) begin
task_warn_msg ("ADDRARDADDR[15]", "CLKARDCLK");
end
always @(notifier_addrb0) begin
task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK");
end
always @(notifier_addrb1) begin
task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK");
end
always @(notifier_addrb2) begin
task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK");
end
always @(notifier_addrb3) begin
task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK");
end
always @(notifier_addrb4) begin
task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK");
end
always @(notifier_addrb5) begin
task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK");
end
always @(notifier_addrb6) begin
task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK");
end
always @(notifier_addrb7) begin
task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK");
end
always @(notifier_addrb8) begin
task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK");
end
always @(notifier_addrb9) begin
task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK");
end
always @(notifier_addrb10) begin
task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK");
end
always @(notifier_addrb11) begin
task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK");
end
always @(notifier_addrb12) begin
task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK");
end
always @(notifier_addrb13) begin
task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK");
end
always @(notifier_addrb14) begin
task_warn_msg ("ADDRBWRADDR[14]", "CLKBWRCLK");
end
always @(notifier_addrb15) begin
task_warn_msg ("ADDRBWRADDR[15]", "CLKBWRCLK");
end
task task_warn_msg;
input [8*15:1] addr_str;
input [8*9:1] clk_str;
begin
$display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str);
end
endtask // task_warn_msg
`endif // `ifdef XIL_TIMING
wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0;
`ifdef XIL_TIMING
wire ram_extension_a_wire = (RAM_EXTENSION_A == "UPPER") ? 1 : 0;
wire ram_extension_b_wire = (RAM_EXTENSION_B == "UPPER") ? 1 : 0;
`endif // `ifdef XIL_TIMING
specify
(CLKARDCLK *> DOADO) = (100:100:100, 100:100:100);
(CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100);
(CLKARDCLK *> RDADDRECC) = (100:100:100, 100:100:100);
(CLKARDCLK => DBITERR) = (100:100:100, 100:100:100);
(CLKARDCLK => SBITERR) = (100:100:100, 100:100:100);
(CLKARDCLK => CASCADEOUTA) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100);
if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100);
(CLKBWRCLK *> ECCPARITY) = (100:100:100, 100:100:100);
(CLKBWRCLK => CASCADEOUTB) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
if (ram_extension_a_wire == 1) (CASCADEINA => DOADO[0]) = (0:0:0, 0:0:0);
if (ram_extension_b_wire == 1) (CASCADEINB => DOBDO[0]) = (0:0:0, 0:0:0);
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR &&& ENARDEN, 0:0:0, 0:0:0, notifier_addra0);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR &&& ENARDEN, 0:0:0, 0:0:0, notifier_addra0);
$setuphold (posedge CLKARDCLK, posedge DIADI &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge DIADI &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge DIPADIP &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge DIPADIP &&& diadi0_enable, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, posedge WEA &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKARDCLK, negedge WEA &&& ENARDEN, 0:0:0, 0:0:0, notifier_a);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR &&& ENBWREN, 0:0:0, 0:0:0, notifier_addrb0);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR &&& ENBWREN, 0:0:0, 0:0:0, notifier_addrb0);
$setuphold (posedge CLKBWRCLK, posedge DIADI &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIADI &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIPADIP &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIPADIP &&& sdp_dia0_clkwr, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIBDI &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIBDI &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge DIPBDIP &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge DIPBDIP &&& dibdi0_enable, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, posedge WEBWE &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$setuphold (posedge CLKBWRCLK, negedge WEBWE &&& ENBWREN, 0:0:0, 0:0:0, notifier_b);
$period (posedge CLKARDCLK, 0:0:0, notifier_a);
$period (posedge CLKBWRCLK, 0:0:0, notifier_b);
$width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a);
$width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
$width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // RAMB36E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. RAMB36E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module RB36_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR,
ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB);
output CASCADEOUTA;
output CASCADEOUTB;
output SBITERR, DBITERR;
output [8:0] RDADDRECC;
output [63:0] DOA;
output [31:0] DOB;
output [7:0] DOPA;
output [3:0] DOPB;
output [7:0] ECCPARITY;
input ENA, CLKA, CASCADEINA, REGCEA;
input ENB, CLKB, CASCADEINB, REGCEB;
input GSR;
input RSTRAMA, RSTRAMB;
input RSTREGA, RSTREGB;
input INJECTDBITERR, INJECTSBITERR;
input [15:0] ADDRA;
input [15:0] ADDRB;
input [63:0] DIA;
input [63:0] DIB;
input [3:0] DIPA;
input [7:0] DIPB;
input [7:0] WEA;
input [7:0] WEB;
parameter DOA_REG = 0;
parameter DOB_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INIT_A = 72'h0;
parameter INIT_B = 72'h0;
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SETUP_ALL = 1000;
parameter SETUP_READ_FIRST = 3000;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 72'h0;
parameter SRVAL_B = 72'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter INIT_FILE = "NONE";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameters are changed.
parameter BRAM_SIZE = 36;
// xilinx_internal_parameter off
integer count, countp, init_mult, initp_mult, large_width;
integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset;
integer viol_time = 0;
integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int;
integer ram_mode_int, en_ecc_write_int, en_ecc_read_int;
integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0;
reg addra_in_15_reg_bram, addrb_in_15_reg_bram;
reg addra_in_15_reg, addrb_in_15_reg;
reg addra_in_15_reg1, addrb_in_15_reg1;
reg junk1;
reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b;
reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0, doa_out_out;
reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0, dob_out_out;
reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0, dopb_out_out;
reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0, dopa_out_out;
reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0;
reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0;
reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0;
reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, syndrome = 8'b0;
reg [7:0] dipb_in_ecc;
reg [71:0] ecc_bit_position;
reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected;
reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_outreg = 0, sbiterr_outreg = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [7:0] wea_reg;
reg enb_reg;
reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg;
reg outp_a = 1'b0, outp_b = 1'b0, junkp;
reg rising_clka = 1'b0, rising_clkb = 1'b0;
reg [15:0] addra_reg, addrb_reg;
reg [63:0] dia_reg, dib_reg;
reg [3:0] dipa_reg;
reg [7:0] dipb_reg;
reg [1:0] viol_type = 2'b00;
reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1;
reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0;
reg [8:0] rdaddrecc_out_out = 9'b0;
reg finish_error = 0;
time time_port_a, time_port_b;
wire [63:0] dib_in;
wire [63:0] dia_in;
wire [15:0] addra_in, addrb_in;
wire clka_in, clkb_in;
wire [7:0] dipb_in;
wire [3:0] dipa_in;
wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in;
wire [7:0] wea_in;
wire [7:0] web_in;
wire cascadeina_in, cascadeinb_in;
wire injectdbiterr_in, injectsbiterr_in;
wire rstrega_in, rstregb_in;
wire [15:0] ox_addra_reconstruct, ox_addrb_reconstruct;
reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg;
wire temp_wire; // trigger NCsim at initial time
assign temp_wire = 1;
time time_clka_period, time_clkb_period, time_period;
reg time_skew_a_flag = 0;
reg time_skew_b_flag = 0;
assign addra_in = ADDRA;
assign addrb_in = ADDRB;
assign clka_in = CLKA;
assign clkb_in = CLKB;
assign dia_in = DIA;
assign dib_in = DIB;
assign dipa_in = DIPA;
assign dipb_in = DIPB;
assign DOA = doa_out_out;
assign DOPA = dopa_out_out;
assign DOB = dob_out_out;
assign DOPB = dopb_out_out;
assign ena_in = ENA;
assign enb_in = ENB;
assign gsr_in = GSR;
assign regcea_in = REGCEA;
assign regceb_in = REGCEB;
assign rstrama_in = RSTRAMA;
assign rstramb_in = RSTRAMB;
assign wea_in = WEA;
assign web_in = WEB;
assign cascadeina_in = CASCADEINA;
assign cascadeinb_in = CASCADEINB;
assign CASCADEOUTA = doa_out_out[0];
assign CASCADEOUTB = dob_out_out[0];
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
assign RDADDRECC = rdaddrecc_out_out;
assign injectdbiterr_in = INJECTDBITERR;
assign injectsbiterr_in = INJECTSBITERR;
assign rstrega_in = RSTREGA;
assign rstregb_in = RSTREGB;
localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100;
// Determine memory size
localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A &&
WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A :
(WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A &&
WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B :
(READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B &&
READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A :
(READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B &&
READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 64;
localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 :
(WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 :
(WRITE_WIDTH_A == 72) ? 64 : 64;
localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 :
(WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 :
(WRITE_WIDTH_B == 72) ? 64 : 64;
localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 :
(WRITE_WIDTH_A == 72) ? 8 : 8;
localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 :
(WRITE_WIDTH_B == 72) ? 8 : 8;
localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 :
(READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 :
(READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 1) ? 1 :
(READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 :
(READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : (READ_WIDTH_B == 72) ? 64 : 64) : 64;
localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 :
(READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 :
(READ_WIDTH_B == 72) ? 64 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 1) ? 1 :
(READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 :
(READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : (READ_WIDTH_A == 72) ? 64 : 64) : 64;
localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 :
(READ_WIDTH_A == 72) ? 8 : 8;
localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 :
(READ_WIDTH_B == 72) ? 8 : 8;
localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 :
(widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 :
(widest_width == 72) ? 6 : 0;
assign ox_addra_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ?
((BRAM_SIZE == 36) ? {1'b0,addra_in[14:8],8'b0} :
(BRAM_SIZE == 18) ? {2'b0,addra_in[13:7],7'b0} : addra_in) : addra_in;
assign ox_addrb_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ?
((BRAM_SIZE == 36) ? {1'b0,addrb_in[14:8],8'b0} :
(BRAM_SIZE == 18) ? {2'b0,addrb_in[13:7],7'b0} : addrb_in) : addrb_in;
localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 :
(widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 :
(widest_width == 72) ? 64 : 64;
localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 :
(widest_width == 72) ? 8 : 8;
localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : 10) : 10;
localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 :
(READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 :
(READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 :
(READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 :
(READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 :
(READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 :
(READ_WIDTH_A == 72) ? 6 : 10) : 10;
localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 :
(WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 :
(WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 :
(WRITE_WIDTH_A == 72) ? 6 : 10;
localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 :
(WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 :
(WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 :
(WRITE_WIDTH_B == 72) ? 6 : 10;
localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ?
((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 :
(WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 :
(WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 :
(WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 :
(WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ?
((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 :
(READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 :
(READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10;
localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10;
localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10;
localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 :
(WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10;
localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10;
localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 :
(READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 :
(READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 :
(READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10;
localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 :
(READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10;
localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768;
localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384;
localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192;
localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096;
localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048;
localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024;
localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512;
localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 :
(widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 32768;
localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 :
(widest_width == 72) ? mem_size72 : 4096;
reg [widest_width-1:0] tmp_mem [mem_depth-1:0];
reg [width-1:0] mem [mem_depth-1:0];
reg [widthp-1:0] memp [memp_depth-1:0];
integer index = 0;
/******************************************** task and function **************************************/
task task_ram;
input ram_we;
input [7:0] ram_di;
input ram_dip;
inout [7:0] mem_task;
inout memp_task;
begin
if (ram_we == 1'b1) begin
mem_task = ram_di;
if (width >= 8)
memp_task = ram_dip;
end
end
endtask // task_ram
task task_ram_col;
input ram_col_we_o;
input ram_col_we;
input [7:0] ram_col_di;
input ram_col_dip;
inout [7:0] ram_col_mem_task;
inout ram_col_memp_task;
integer ram_col_i;
begin
if (ram_col_we == 1'b1) begin
for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1)
if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))
ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i];
if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)))
ram_col_memp_task = ram_col_dip;
end
end
endtask // task_ram_col
task task_ram_ox;
input ram_ox_we_o;
input ram_ox_we;
input [7:0] ram_ox_di;
input ram_ox_dip;
inout [7:0] ram_ox_mem_task;
inout ram_ox_memp_task;
integer ram_ox_i;
begin
if (ram_ox_we == 1'b1) begin
for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1)
ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i];
if (width >= 8)
ram_ox_memp_task = ram_ox_dip;
end
end
endtask // task_ram_ox
task task_x_buf;
input [1:0] wr_rd_mode;
input integer do_uindex;
input integer do_lindex;
input integer dop_index;
input [63:0] do_ltmp;
inout [63:0] x_buf_do_tmp;
input [7:0] dop_ltmp;
inout [7:0] x_buf_dop_tmp;
integer i;
begin
if (wr_rd_mode == 2'b01) begin
for (i = do_lindex; i <= do_uindex; i = i + 1) begin
if (do_ltmp[i] === 1'bx)
x_buf_do_tmp[i] = 1'bx;
end
if (dop_ltmp[dop_index] === 1'bx)
x_buf_dop_tmp[dop_index] = 1'bx;
end // if (wr_rd_mode == 2'b01)
else begin
x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8];
x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index];
end // else: !if(wr_rd_mode == 2'b01)
end
endtask // task_x_buf
task task_col_wr_ram_a;
input [1:0] col_wr_ram_a_seq;
input [7:0] col_wr_ram_a_web_tmp;
input [7:0] col_wr_ram_a_wea_tmp;
input [63:0] col_wr_ram_a_dia_tmp;
input [7:0] col_wr_ram_a_dipa_tmp;
input [15:0] col_wr_ram_a_addrb_tmp;
input [15:0] col_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : begin
if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : begin
task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][0 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][8 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][16 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][24 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][32 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][40 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][48 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][56 +: 8], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_a_seq == 2'b00)
chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_col_wr_ram_a
task task_ox_wr_ram_a;
input [1:0] ox_wr_ram_a_seq;
input [7:0] ox_wr_ram_a_web_tmp;
input [7:0] ox_wr_ram_a_wea_tmp;
input [63:0] ox_wr_ram_a_dia_tmp;
input [7:0] ox_wr_ram_a_dipa_tmp;
input [15:0] ox_wr_ram_a_addrb_tmp;
input [15:0] ox_wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10)
end // case: 1, 2, 4
8 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 8
16 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
if (wa_width >= width)
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 16
32 : begin
if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // if (wa_width <= wb_width)
end // case: 32
64 : begin
task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][0 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][8 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][16 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][24 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][32 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][40 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][48 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][56 +: 8], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_a_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp);
end // case: 64
endcase // case(wa_width)
end
endtask // task_ox_wr_ram_a
task task_col_wr_ram_b;
input [1:0] col_wr_ram_b_seq;
input [7:0] col_wr_ram_b_wea_tmp;
input [7:0] col_wr_ram_b_web_tmp;
input [63:0] col_wr_ram_b_dib_tmp;
input [7:0] col_wr_ram_b_dipb_tmp;
input [15:0] col_wr_ram_b_addra_tmp;
input [15:0] col_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 16
32 : begin
if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10)
end // case: 32
64 : begin
task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (col_wr_ram_b_seq == 2'b00)
chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_col_wr_ram_b
task task_ox_wr_ram_b;
input [1:0] ox_wr_ram_b_seq;
input [7:0] ox_wr_ram_b_wea_tmp;
input [7:0] ox_wr_ram_b_web_tmp;
input [63:0] ox_wr_ram_b_dib_tmp;
input [7:0] ox_wr_ram_b_dipb_tmp;
input [15:0] ox_wr_ram_b_addra_tmp;
input [15:0] ox_wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 1, 2, 4
8 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (wb_width <= wa_width)
end // case: 8
16 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 16
32 : begin
if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
if (wb_width >= width)
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
else
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10)
end // case: 32
64 : begin
task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
if (ox_wr_ram_b_seq == 2'b00)
chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp);
end // case: 64
endcase // case(wb_width)
end
endtask // task_ox_wr_ram_b
task task_wr_ram_a;
input [7:0] wr_ram_a_wea_tmp;
input [63:0] dia_tmp;
input [7:0] dipa_tmp;
input [15:0] wr_ram_a_addra_tmp;
begin
case (wa_width)
1, 2, 4 : begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1);
end
8 : begin
if (wa_width >= width)
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]);
else
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]);
end
16 : begin
if (wa_width >= width) begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][0 +: 8], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][8 +: 8], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]);
end
else begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]);
end // else: !if(wa_width >= wb_width)
end // case: 16
32 : begin
task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][0 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][8 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][16 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][24 +: 8], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]);
end // case: 32
endcase // case(wa_width)
end
endtask // task_wr_ram_a
task task_wr_ram_b;
input [7:0] wr_ram_b_web_tmp;
input [63:0] dib_tmp;
input [7:0] dipb_tmp;
input [15:0] wr_ram_b_addrb_tmp;
begin
case (wb_width)
1, 2, 4 : begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1);
end
8 : begin
if (wb_width >= width)
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]);
else
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]);
end
16 : begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]);
end
else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]);
end
end // case: 16
32 : begin
if (wb_width >= width) begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][16 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][24 +: 8], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]);
end
else begin
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]);
end // else: !if(wb_width >= width)
end // case: 32
64 : begin // only valid with ECC single bit correction for 64 bits
task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][0 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]);
task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][8 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]);
task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][16 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]);
task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][24 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]);
task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][32 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]);
task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][40 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]);
task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][48 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]);
task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][56 +: 8], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]);
end // case: 64
endcase // case(wb_width)
end
endtask // task_wr_ram_b
task task_col_rd_ram_a;
input [1:0] col_rd_ram_a_seq; // 1 is bypass
input [7:0] col_rd_ram_a_web_tmp;
input [7:0] col_rd_ram_a_wea_tmp;
input [15:0] col_rd_ram_a_addra_tmp;
inout [63:0] col_rd_ram_a_doa_tmp;
inout [7:0] col_rd_ram_a_dopa_tmp;
reg [63:0] doa_ltmp;
reg [7:0] dopa_ltmp;
begin
doa_ltmp= 64'b0;
dopa_ltmp= 8'b0;
case (ra_width)
1, 2, 4 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width)
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 1, 2, 4
8 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]];
end
else begin
doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 8) +: 8];
dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // case: 8
16 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1];
end
else begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) +: 8];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
if (ra_width >= width) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1];
end
else begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) + 8) +: 8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
32 : begin
if (ra_width >= width) begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][23:16];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][31:24];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end // if (ra_width >= width)
end
64 : begin
if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin
doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][7:0];
dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin
doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][15:8];
dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin
doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][23:16];
dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin
doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][31:24];
dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin
doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][39:32];
dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin
doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][47:40];
dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin
doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][55:48];
dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin
doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][63:56];
dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp);
end
end
endcase // case(ra_width)
end
endtask // task_col_rd_ram_a
task task_col_rd_ram_b;
input [1:0] col_rd_ram_b_seq; // 1 is bypass
input [7:0] col_rd_ram_b_wea_tmp;
input [7:0] col_rd_ram_b_web_tmp;
input [15:0] col_rd_ram_b_addrb_tmp;
inout [63:0] col_rd_ram_b_dob_tmp;
inout [7:0] col_rd_ram_b_dopb_tmp;
reg [63:0] col_rd_ram_b_dob_ltmp;
reg [7:0] col_rd_ram_b_dopb_ltmp;
begin
col_rd_ram_b_dob_ltmp= 64'b0;
col_rd_ram_b_dopb_ltmp= 8'b0;
case (rb_width)
1, 2, 4 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width)
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width];
task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 1, 2, 4
8 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]];
end
else begin
col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8];
col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end // case: 8
16 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 8];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) + 8) +: 8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
32 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) +: 8];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1];
end
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 8) +: 8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1];
end
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][23:16];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 16) +: 8];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1];
end
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
if (rb_width >= width) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][31:24];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1];
end
else begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 32) + 24) +: 8];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1];
end
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
64 : begin
if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][7:0];
col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1];
task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][15:8];
col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1];
task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][23:16];
col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1];
task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][31:24];
col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1];
task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][39:32];
col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1];
task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][47:40];
col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1];
task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][55:48];
col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1];
task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin
col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][63:56];
col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1];
task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp);
end
end
endcase // case(rb_width)
end
endtask // task_col_rd_ram_b
task task_rd_ram_a;
input [15:0] rd_ram_a_addra_tmp;
inout [63:0] doa_tmp;
inout [7:0] dopa_tmp;
begin
case (ra_width)
1, 2, 4 : begin
if (ra_width >= width)
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]];
else
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width];
end
8 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:3]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * 8) +: 8];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1];
end
end
16 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:4]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * 16) +: 16];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 2];
end
end
32 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:5]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]];
end
else begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * 32) +: 32];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * 4) +: 4];
end
end
64 : begin
if (ra_width >= width) begin
doa_tmp = mem[rd_ram_a_addra_tmp[14:6]];
dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]];
end
end
endcase // case(ra_width)
end
endtask // task_rd_ram_a
task task_rd_ram_b;
input [15:0] rd_ram_b_addrb_tmp;
inout [31:0] dob_tmp;
inout [3:0] dopb_tmp;
begin
case (rb_width)
1, 2, 4 : begin
if (rb_width >= width)
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]];
else
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width];
end
8 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1];
end
end
16 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]];
end
else begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2];
end
end
32 : begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]];
end
64 : begin
if (rb_width >= width) begin
dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]];
dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]];
end
end
endcase
end
endtask // task_rd_ram_b
task chk_for_col_msg;
input wea_tmp;
input web_tmp;
input [15:0] addra_tmp;
input [15:0] addrb_tmp;
begin
if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY")
if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else
$display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp);
col_wr_wr_msg = 0;
end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1)
else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01))
$display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp);
end // else: !if(chk_ox_msg == 1)
col_wra_rdb_msg = 0;
end
else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin
if (chk_ox_msg == 1) begin
if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1))
$display("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp);
end
else begin
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6"))
$display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp);
else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01))
$display("Memory Collision Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp);
end // else: !if(chk_ox_msg == 1)
col_wrb_rda_msg = 0;
end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1)
end
endtask // chk_for_col_msg
task task_col_ecc_read;
inout [63:0] do_tmp;
inout [7:0] dop_tmp;
input [15:0] addr_tmp;
reg [71:0] task_ecc_bit_position;
reg [7:0] task_dopr_ecc, task_syndrome;
reg [63:0] task_di_in_ecc_corrected;
reg [7:0] task_dip_in_ecc_corrected;
begin
if (|do_tmp === 1'bx) begin // if there is collision
dbiterr_out <= 1'bx;
sbiterr_out <= 1'bx;
end
else begin
task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp);
task_syndrome = task_dopr_ecc ^ dop_tmp;
if (task_syndrome !== 0) begin
if (task_syndrome[7]) begin // dectect single bit error
task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]};
if (task_syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output
task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory
do_tmp = task_di_in_ecc_corrected;
task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_tmp = task_dip_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!task_syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (task_syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(task_syndrome !== 0)
end
end
endtask // task_col_ecc_read
function [7:0] fn_dip_ecc;
input encode;
input [63:0] di_in;
input [7:0] dip_in;
begin
fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8]
^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19]
^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28]
^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38]
^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48]
^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59]
^di_in[61]^di_in[63];
fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9]
^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17]
^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28]
^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39]
^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48]
^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59]
^di_in[62]^di_in[63];
fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17]
^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48]
^di_in[53]^di_in[54]^di_in[55]^di_in[56]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]
^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56];
fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
if (encode == 1'b1)
fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
else
fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6]
^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9]
^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19]
^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29]
^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39]
^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49]
^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59]
^di_in[60]^di_in[61]^di_in[62]^di_in[63];
end
endfunction // fn_dip_ecc
/******************************************** END task and function **************************************/
initial begin
if (INIT_FILE == "NONE") begin // memory initialization from attributes
init_mult = 256/width;
for (count = 0; count < init_mult; count = count + 1) begin
init_offset = count * width;
mem[count] = INIT_00[init_offset +:width];
mem[count + (init_mult * 1)] = INIT_01[init_offset +:width];
mem[count + (init_mult * 2)] = INIT_02[init_offset +:width];
mem[count + (init_mult * 3)] = INIT_03[init_offset +:width];
mem[count + (init_mult * 4)] = INIT_04[init_offset +:width];
mem[count + (init_mult * 5)] = INIT_05[init_offset +:width];
mem[count + (init_mult * 6)] = INIT_06[init_offset +:width];
mem[count + (init_mult * 7)] = INIT_07[init_offset +:width];
mem[count + (init_mult * 8)] = INIT_08[init_offset +:width];
mem[count + (init_mult * 9)] = INIT_09[init_offset +:width];
mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width];
mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width];
mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width];
mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width];
mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width];
mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width];
mem[count + (init_mult * 16)] = INIT_10[init_offset +:width];
mem[count + (init_mult * 17)] = INIT_11[init_offset +:width];
mem[count + (init_mult * 18)] = INIT_12[init_offset +:width];
mem[count + (init_mult * 19)] = INIT_13[init_offset +:width];
mem[count + (init_mult * 20)] = INIT_14[init_offset +:width];
mem[count + (init_mult * 21)] = INIT_15[init_offset +:width];
mem[count + (init_mult * 22)] = INIT_16[init_offset +:width];
mem[count + (init_mult * 23)] = INIT_17[init_offset +:width];
mem[count + (init_mult * 24)] = INIT_18[init_offset +:width];
mem[count + (init_mult * 25)] = INIT_19[init_offset +:width];
mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width];
mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width];
mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width];
mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width];
mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width];
mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width];
mem[count + (init_mult * 32)] = INIT_20[init_offset +:width];
mem[count + (init_mult * 33)] = INIT_21[init_offset +:width];
mem[count + (init_mult * 34)] = INIT_22[init_offset +:width];
mem[count + (init_mult * 35)] = INIT_23[init_offset +:width];
mem[count + (init_mult * 36)] = INIT_24[init_offset +:width];
mem[count + (init_mult * 37)] = INIT_25[init_offset +:width];
mem[count + (init_mult * 38)] = INIT_26[init_offset +:width];
mem[count + (init_mult * 39)] = INIT_27[init_offset +:width];
mem[count + (init_mult * 40)] = INIT_28[init_offset +:width];
mem[count + (init_mult * 41)] = INIT_29[init_offset +:width];
mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width];
mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width];
mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width];
mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width];
mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width];
mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width];
mem[count + (init_mult * 48)] = INIT_30[init_offset +:width];
mem[count + (init_mult * 49)] = INIT_31[init_offset +:width];
mem[count + (init_mult * 50)] = INIT_32[init_offset +:width];
mem[count + (init_mult * 51)] = INIT_33[init_offset +:width];
mem[count + (init_mult * 52)] = INIT_34[init_offset +:width];
mem[count + (init_mult * 53)] = INIT_35[init_offset +:width];
mem[count + (init_mult * 54)] = INIT_36[init_offset +:width];
mem[count + (init_mult * 55)] = INIT_37[init_offset +:width];
mem[count + (init_mult * 56)] = INIT_38[init_offset +:width];
mem[count + (init_mult * 57)] = INIT_39[init_offset +:width];
mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width];
mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width];
mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width];
mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width];
mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width];
mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width];
if (BRAM_SIZE == 36) begin
mem[count + (init_mult * 64)] = INIT_40[init_offset +:width];
mem[count + (init_mult * 65)] = INIT_41[init_offset +:width];
mem[count + (init_mult * 66)] = INIT_42[init_offset +:width];
mem[count + (init_mult * 67)] = INIT_43[init_offset +:width];
mem[count + (init_mult * 68)] = INIT_44[init_offset +:width];
mem[count + (init_mult * 69)] = INIT_45[init_offset +:width];
mem[count + (init_mult * 70)] = INIT_46[init_offset +:width];
mem[count + (init_mult * 71)] = INIT_47[init_offset +:width];
mem[count + (init_mult * 72)] = INIT_48[init_offset +:width];
mem[count + (init_mult * 73)] = INIT_49[init_offset +:width];
mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width];
mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width];
mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width];
mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width];
mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width];
mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width];
mem[count + (init_mult * 80)] = INIT_50[init_offset +:width];
mem[count + (init_mult * 81)] = INIT_51[init_offset +:width];
mem[count + (init_mult * 82)] = INIT_52[init_offset +:width];
mem[count + (init_mult * 83)] = INIT_53[init_offset +:width];
mem[count + (init_mult * 84)] = INIT_54[init_offset +:width];
mem[count + (init_mult * 85)] = INIT_55[init_offset +:width];
mem[count + (init_mult * 86)] = INIT_56[init_offset +:width];
mem[count + (init_mult * 87)] = INIT_57[init_offset +:width];
mem[count + (init_mult * 88)] = INIT_58[init_offset +:width];
mem[count + (init_mult * 89)] = INIT_59[init_offset +:width];
mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width];
mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width];
mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width];
mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width];
mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width];
mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width];
mem[count + (init_mult * 96)] = INIT_60[init_offset +:width];
mem[count + (init_mult * 97)] = INIT_61[init_offset +:width];
mem[count + (init_mult * 98)] = INIT_62[init_offset +:width];
mem[count + (init_mult * 99)] = INIT_63[init_offset +:width];
mem[count + (init_mult * 100)] = INIT_64[init_offset +:width];
mem[count + (init_mult * 101)] = INIT_65[init_offset +:width];
mem[count + (init_mult * 102)] = INIT_66[init_offset +:width];
mem[count + (init_mult * 103)] = INIT_67[init_offset +:width];
mem[count + (init_mult * 104)] = INIT_68[init_offset +:width];
mem[count + (init_mult * 105)] = INIT_69[init_offset +:width];
mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width];
mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width];
mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width];
mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width];
mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width];
mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width];
mem[count + (init_mult * 112)] = INIT_70[init_offset +:width];
mem[count + (init_mult * 113)] = INIT_71[init_offset +:width];
mem[count + (init_mult * 114)] = INIT_72[init_offset +:width];
mem[count + (init_mult * 115)] = INIT_73[init_offset +:width];
mem[count + (init_mult * 116)] = INIT_74[init_offset +:width];
mem[count + (init_mult * 117)] = INIT_75[init_offset +:width];
mem[count + (init_mult * 118)] = INIT_76[init_offset +:width];
mem[count + (init_mult * 119)] = INIT_77[init_offset +:width];
mem[count + (init_mult * 120)] = INIT_78[init_offset +:width];
mem[count + (init_mult * 121)] = INIT_79[init_offset +:width];
mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width];
mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width];
mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width];
mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width];
mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width];
mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width];
end // if (BRAM_SIZE == 36)
end // for (count = 0; count < init_mult; count = count + 1)
if (width >= 8) begin
initp_mult = 256/widthp;
for (countp = 0; countp < initp_mult; countp = countp + 1) begin
initp_offset = countp * widthp;
memp[countp] = INITP_00[initp_offset +:widthp];
memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp];
memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp];
memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp];
memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp];
memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp];
memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp];
memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp];
if (BRAM_SIZE == 36) begin
memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp];
memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp];
memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp];
memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp];
memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp];
memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp];
memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp];
memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp];
end
end // for (countp = 0; countp < initp_mult; countp = countp + 1)
end // if (width >= 8)
end // if (INIT_FILE == "NONE")
else begin // memory initialization from memory file
for (j = 0; j < mem_depth; j = j + 1) begin
for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin
tmp_mem[j][j1] = 1'b0;
end
end
$readmemh (INIT_FILE, tmp_mem);
case (widest_width)
1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1)
mem[i_mem] = tmp_mem [i_mem];
9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 8];
memp[i_mem] = tmp_mem[i_mem][8 +: 1];
end
18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 16];
memp[i_mem] = tmp_mem[i_mem][16 +: 2];
end
36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 32];
memp[i_mem] = tmp_mem[i_mem][32 +: 4];
end
72 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin
mem[i_mem] = tmp_mem[i_mem][0 +: 64];
memp[i_mem] = tmp_mem[i_mem][64 +: 8];
end
endcase // case(widest_width)
end // else: !if(INIT_FILE == "NONE")
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int = 1;
"FALSE" : en_ecc_write_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int = 1;
"FALSE" : en_ecc_read_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
case (RAM_MODE)
"TDP" : begin
ram_mode_int = 1;
if (en_ecc_write_int == 1) begin
$display("DRC Error : The attribute EN_ECC_WRITE on RAMB36E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE);
finish_error = 1;
end
if (en_ecc_read_int == 1) begin
$display("DRC Error : The attribute EN_ECC_READ on RAMB36E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ);
finish_error = 1;
end
end // case: "TDP"
"SDP" : begin
ram_mode_int = 0;
if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin
$display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB36E1 instance %m.");
finish_error = 1;
end
if (BRAM_SIZE == 18) begin
if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP.");
finish_error = 1;
end
end
else begin
if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin
$display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP.");
finish_error = 1;
end
end // else: !if(BRAM_SIZE == 18)
end // case: "SDP"
default : begin
$display("Attribute Syntax Error : The attribute RAM_MODE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE);
finish_error = 1;
end
endcase
case (WRITE_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_A)
case (WRITE_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B);
finish_error = 1;
end
end
endcase // case(WRITE_WIDTH_B)
case (READ_WIDTH_A)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_A)
case (READ_WIDTH_B)
0, 1, 2, 4, 9, 18 : ;
36 : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
end
72 : begin
if (BRAM_SIZE == 18) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
default : begin
if (BRAM_SIZE == 18 && ram_mode_int == 1) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B);
finish_error = 1;
end
else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB36E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B);
finish_error = 1;
end
end
endcase // case(READ_WIDTH_B)
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin
$display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1.");
finish_error = 1;
end
if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin
$display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB36E1 instance %m, both can not be 0.");
finish_error = 1;
end
case (WRITE_MODE_A)
"WRITE_FIRST" : wr_mode_a = 2'b00;
"READ_FIRST" : wr_mode_a = 2'b01;
"NO_CHANGE" : wr_mode_a = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
finish_error = 1;
end
endcase
case (WRITE_MODE_B)
"WRITE_FIRST" : wr_mode_b = 2'b00;
"READ_FIRST" : wr_mode_b = 2'b01;
"NO_CHANGE" : wr_mode_b = 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_A)
"UPPER" : cascade_a = 2'b11;
"LOWER" : cascade_a = 2'b01;
"NONE" : cascade_a = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A);
finish_error = 1;
end
endcase
case (RAM_EXTENSION_B)
"UPPER" : cascade_b = 2'b11;
"LOWER" : cascade_b = 2'b01;
"NONE" : cascade_b = 2'b00;
default : begin
$display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B);
finish_error = 1;
end
endcase
if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin
$display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB36E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
finish_error = 1;
end
case (RSTREG_PRIORITY_A)
"RSTREG" : rstreg_priority_a_int = 1;
"REGCE" : rstreg_priority_a_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB36E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A);
finish_error = 1;
end
endcase
case (RSTREG_PRIORITY_B)
"RSTREG" : rstreg_priority_b_int = 1;
"REGCE" : rstreg_priority_b_int = 0;
default : begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB36E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B);
finish_error = 1;
end
endcase
if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin
$display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB36E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE.");
finish_error = 1;
end
case (RDADDR_COLLISION_HWCONFIG)
"DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0;
"PERFORMANCE" : rdaddr_collision_hwconfig_int = 1;
default : begin
$display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB36E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG);
finish_error = 1;
end
endcase
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB36E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
$finish;
end // initial begin
// GSR
always @(gsr_in)
if (gsr_in) begin
assign doa_out = INIT_A[0 +: ra_width];
if (ra_width >= 8) begin
assign dopa_out = INIT_A[ra_width +: ra_widthp];
end
assign dob_out = INIT_B[0 +: rb_width];
if (rb_width >= 8) begin
assign dopb_out = INIT_B[rb_width +: rb_widthp];
end
assign dbiterr_out = 0;
assign sbiterr_out = 0;
assign rdaddrecc_out = 9'b0;
end
else begin
deassign doa_out;
deassign dopa_out;
deassign dob_out;
deassign dopb_out;
deassign dbiterr_out;
deassign sbiterr_out;
deassign rdaddrecc_out;
end
always @(time_clka_period or time_clkb_period) begin
if (time_clka_period != 0 && time_clkb_period != 0) begin
if (time_clka_period <= time_clkb_period) begin
if (time_clka_period <= SETUP_READ_FIRST) begin
time_period = time_clka_period;
end
else begin
time_period = SETUP_READ_FIRST;
end
end
else if (time_clkb_period <= SETUP_READ_FIRST)
time_period = time_clkb_period;
else
time_period = SETUP_READ_FIRST;
end
end
// registering signals
always @(posedge clka_in) begin
rising_clka = 1;
if ($time > 110000 && time_skew_a_flag == 0) begin
time_clka_period = $time - time_port_a;
time_skew_a_flag = 1;
end
if (ena_in === 1'b1) begin
time_port_a = $time;
addra_reg = addra_in;
wea_reg = wea_in;
dia_reg = dia_in;
dipa_reg = dipa_in;
ox_addra_reconstruct_reg = ox_addra_reconstruct;
end
end
always @(posedge clkb_in) begin
rising_clkb = 1;
if ($time > 110000 && time_skew_b_flag == 0) begin
time_clkb_period = $time - time_port_b;
time_skew_b_flag = 1;
end
if (enb_in === 1'b1) begin
time_port_b = $time;
addrb_reg = addrb_in;
web_reg = web_in;
enb_reg = enb_in;
dib_reg = dib_in;
dipb_reg = dipb_in;
ox_addrb_reconstruct_reg = ox_addrb_reconstruct;
end
end // always @ (posedge clkb_in)
// CLKA and CLKB
always @(posedge rising_clka or posedge rising_clkb) begin
// Registering addr[15] for cascade mode
if (rising_clka)
if (cascade_a[1])
addra_in_15_reg_bram = ~addra_in[15];
else
addra_in_15_reg_bram = addra_in[15];
if (rising_clkb)
if (cascade_b[1])
addrb_in_15_reg_bram = ~addrb_in[15];
else
addrb_in_15_reg_bram = addrb_in[15];
if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
/************************************* Collision starts *****************************************/
if (SIM_COLLISION_CHECK != "NONE") begin
if (gsr_in === 1'b0) begin
if (time_port_a > time_port_b) begin
if (time_port_a - time_port_b <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_a - time_port_b <= time_period) begin
viol_time = 2;
end
end
else begin
if (time_port_b - time_port_a <= sync_clk_skew) begin
viol_time = 1;
end
else if (time_port_b - time_port_a <= time_period) begin
viol_time = 2;
end
end // else: !if(time_port_a > time_port_b)
if (ena_in === 1'b0 || enb_in === 1'b0)
viol_time = 0;
if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))
if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))
viol_time = 0;
if (viol_time != 0) begin
if (SIM_DEVICE == "VIRTEX6") begin
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b10, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b01;
chk_ox_msg = 1;
chk_ox_same_clk = 1;
if (time_port_a > time_port_b)
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
else if (time_port_b > time_port_a)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_ox_msg = 0;
chk_ox_same_clk = 0;
task_ox_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_ox_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if (rdaddr_collision_hwconfig_int == 1) begin
task_col_wr_ram_a (2'b10, web_in, 8'hff, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b10, wea_in, 8'hff, di_x, di_x[7:0], addra_in, addrb_in);
end
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && rising_clkb)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b10, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin
viol_type = 2'b10;
chk_ox_msg = 1;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
// get msg
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_ox_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b10, wea_in, 8'hff, di_x, di_x[7:0], addra_in, addrb_reg);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]))
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin
task_col_wr_ram_a (2'b10, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
end
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin
viol_type = 2'b11;
chk_ox_msg = 1;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
// get msg
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
chk_ox_msg = 0;
task_ox_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_ox_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_ox_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, 8'hff, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, addrb_in);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]))
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // if (SIM_DEVICE == "VIRTEX6")
else begin // 7series
// Clka and clkb rise at the same time
if ((rising_clka && rising_clkb) || viol_time == 1) begin
if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b01;
chk_col_same_clk = 1;
if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin
doa_buf = dob_buf;
dopa_buf = dopb_buf;
end
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin
dob_buf = doa_buf;
dopb_buf = dopa_buf;
end
else begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end
task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);
chk_col_same_clk = 0;
task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);
if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb)))
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_in, addrb_in, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if ((rising_clka && rising_clkb) || viol_time == 1)
// Clkb before clka
else if (rising_clka && !rising_clkb) begin
if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin
viol_type = 2'b10;
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);
task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);
task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);
dib_ecc_col = dib_reg;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg);
end
else
task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_in);
end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_in, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (rising_clka && !rising_clkb)
// Clka before clkb
else if (!rising_clka && rising_clkb) begin
if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin
viol_type = 2'b11;
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);
task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);
task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);
dib_ecc_col = dib_in;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
dib_ecc_col[62] = ~dib_ecc_col[62];
end
else if (injectsbiterr_in === 1) begin
dib_ecc_col[30] = ~dib_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin
dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc_col;
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in);
end
else
task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in);
if (wr_mode_a != 2'b01)
task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);
if (wr_mode_b != 2'b01)
task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);
if (ram_mode_int == 0 && en_ecc_read_int == 1)
task_col_ecc_read (doa_buf, dopa_buf, addra_reg);
end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb])
else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin
$display ("Address Overlap Error on RAMB36E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, addrb_in, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B );
$finish;
end
else
viol_time = 0;
end // if (!rising_clka && rising_clkb)
end // else: !if(SIM_DEVICE == "VIRTEX6")
end // if (viol_time != 0)
end // if (gsr_in === 1'b0)
if (SIM_COLLISION_CHECK == "WARNING_ONLY")
viol_time = 0;
end // if (SIM_COLLISION_CHECK != "NONE")
/*************************************** end collision ********************************/
end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00)))
/**************************** Port A ****************************************/
if (rising_clka) begin
// DRC
if (rstrama_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB36E1 instance %m.");
// end DRC
// registering addra_in[15] the second time
if (regcea_in)
addra_in_15_reg1 = addra_in_15_reg;
if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || rstrama_in == 1'b1))
if (cascade_a[1])
addra_in_15_reg = ~addra_in[15];
else
addra_in_15_reg = addra_in[15];
if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin
// SRVAL
if (rstrama_in === 1'b1) begin
doa_buf = SRVAL_A[0 +: ra_width];
doa_out = SRVAL_A[0 +: ra_width];
if (ra_width >= 8) begin
dopa_buf = SRVAL_A[ra_width +: ra_widthp];
dopa_out = SRVAL_A[ra_width +: ra_widthp];
end
end
if (viol_time == 0) begin
// Read first
if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
// ECC decode
if (ram_mode_int == 0 && en_ecc_read_int == 1) begin
dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf);
syndrome = dopr_ecc ^ dopa_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
$finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
doa_buf = dia_in_ecc_corrected;
dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dopa_buf = dipa_in_ecc_corrected;
dbiterr_out <= 0;
sbiterr_out <= 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out <= 0;
dbiterr_out <= 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out <= 0;
sbiterr_out <= 0;
end // else: !if(syndrome !== 0)
// output of rdaddrecc
rdaddrecc_out[8:0] <= addra_in[14:6];
end // if (ram_mode_int == 0 && en_ecc_read_int == 1)
end // if (wr_mode_a == 2'b01)
// Write
task_wr_ram_a (wea_in, dia_in, dipa_in, addra_in);
// Read if not read first
if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1))
task_rd_ram_a (addra_in, doa_buf, dopa_buf);
end // if (viol_time == 0)
end // if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)))
end // if (rising_clka)
// end of port A
/************************************** port B ***************************************************************/
if (rising_clkb) begin
// DRC
if (rstramb_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB36E1 instance %m.");
if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin
if (injectsbiterr_in === 1)
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB36E1 instance %m.");
if (injectdbiterr_in === 1)
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB36E1 instance %m.");
end
// End DRC
if (regceb_in)
addrb_in_15_reg1 = addrb_in_15_reg;
if (enb_in && (wr_mode_b != 2'b10 || web_in[0] == 0 || rstramb_in == 1'b1))
if (cascade_b[1])
addrb_in_15_reg = ~addrb_in[15];
else
addrb_in_15_reg = addrb_in[15];
if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin
// SRVAL
if (rstramb_in === 1'b1) begin
dob_buf = SRVAL_B[0 +: rb_width];
dob_out = SRVAL_B[0 +: rb_width];
if (rb_width >= 8) begin
dopb_buf = SRVAL_B[rb_width +: rb_widthp];
dopb_out = SRVAL_B[rb_width +: rb_widthp];
end
end
if (viol_time == 0) begin
// ECC encode
if (ram_mode_int == 0 && en_ecc_write_int == 1) begin
dip_ecc = fn_dip_ecc(1'b1, dib_in, dipb_in);
eccparity_out = dip_ecc;
dipb_in_ecc = dip_ecc;
end
else
dipb_in_ecc = dipb_in;
dib_in_ecc = dib_in;
// injecting error
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (injectdbiterr_in === 1) begin // double bit
dib_in_ecc[30] = ~dib_in_ecc[30];
dib_in_ecc[62] = ~dib_in_ecc[62];
end
else if (injectsbiterr_in === 1) begin // single bit
dib_in_ecc[30] = ~dib_in_ecc[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
// Read first
if (wr_mode_b == 2'b01 && rstramb_in === 1'b0)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
// Write
task_wr_ram_b (web_in, dib_in_ecc, dipb_in_ecc, addrb_in);
// Read if not read first
if (wr_mode_b != 2'b01 && rstramb_in === 1'b0)
task_rd_ram_b (addrb_in, dob_buf, dopb_buf);
end // if (viol_time == 0)
end // if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0))
end // if (rising_clkb)
// end of port B
if (gsr_in == 1'b0) begin
// writing outputs of port A
if (ena_in && (rising_clka || viol_time != 0)) begin
if (rstrama_in === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))) begin
doa_out <= doa_buf;
if (ra_width >= 8)
dopa_out <= dopa_buf;
end
end
// writing outputs of port B
if (enb_in && (rising_clkb || viol_time != 0)) begin
if (rstramb_in === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))) begin
dob_out <= dob_buf;
if (rb_width >= 8)
dopb_out <= dopb_buf;
end
end
end // if (gsr_in == 1'b0)
viol_time = 0;
rising_clka = 0;
rising_clkb = 0;
viol_type = 2'b00;
col_wr_wr_msg = 1;
col_wra_rdb_msg = 1;
col_wrb_rda_msg = 1;
end // always @ (posedge rising_clka or posedge rising_clkb)
// ********* Cascade Port A ********
always @(posedge clka_in or cascadeina_in or addra_in_15_reg or doa_out or dopa_out) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin
doa_out_mux[0] = cascadeina_in;
end
else begin
doa_out_mux = doa_out;
if (ra_width >= 8)
dopa_out_mux = dopa_out;
end
end
// output register mode
always @(posedge clka_in or cascadeina_in or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin
if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin
doa_outreg_mux[0] = cascadeina_in;
end
else begin
doa_outreg_mux = doa_outreg;
if (ra_width >= 8)
dopa_outreg_mux = dopa_outreg;
end
end
// ********* Cascade Port B ********
always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg or dob_out or dopb_out) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin
dob_out_mux[0] = cascadeinb_in;
end
else begin
dob_out_mux = dob_out;
if (rb_width >= 8)
dopb_out_mux = dopb_out;
end
end
// output register mode
always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin
if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin
dob_outreg_mux[0] = cascadeinb_in;
end
else begin
dob_outreg_mux = dob_outreg;
if (rb_width >= 8)
dopb_outreg_mux = dopb_outreg;
end
end // always @ (posedge regclkb_in or cascadeinregb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg)
// ***** Output Registers **** Port A *****
always @(posedge clka_in or posedge gsr_in) begin
if (DOA_REG == 1) begin
if (gsr_in == 1'b1) begin
rdaddrecc_outreg <= 9'b0;
dbiterr_outreg <= 0;
sbiterr_outreg <= 0;
doa_outreg <= INIT_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= INIT_A[ra_width +: ra_widthp];
end
else if (gsr_in == 1'b0) begin
if (regcea_in === 1'b1) begin
dbiterr_outreg <= dbiterr_out;
sbiterr_outreg <= sbiterr_out;
rdaddrecc_outreg <= rdaddrecc_out;
end
if (rstreg_priority_a_int == 0) begin // Virtex5 behavior
if (regcea_in == 1'b1) begin
if (rstrega_in == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (rstrega_in == 1'b0) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end // if (regcea_in == 1'b1)
end // if (rstreg_priority_a_int == 1'b0)
else begin
if (rstrega_in == 1'b1) begin
doa_outreg <= SRVAL_A[0 +: ra_width];
if (ra_width >= 8)
dopa_outreg <= SRVAL_A[ra_width +: ra_widthp];
end
else if (rstrega_in == 1'b0) begin
if (regcea_in == 1'b1) begin
doa_outreg <= doa_out;
if (ra_width >= 8)
dopa_outreg <= dopa_out;
end
end
end // else: !if(rstreg_priority_a_int == 1'b0)
end // if (gsr_in == 1'b0)
end // if (DOA_REG == 1)
end // always @ (posedge clka_in or posedge gsr_in)
always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin
case (DOA_REG)
0 : begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
rdaddrecc_out_out = rdaddrecc_out;
doa_out_out[0 +: ra_width] = doa_out_mux[0 +: ra_width];
if (ra_width >= 8)
dopa_out_out[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp];
end
1 : begin
dbiterr_out_out = dbiterr_outreg;
sbiterr_out_out = sbiterr_outreg;
doa_out_out[0 +: ra_width] = doa_outreg_mux[0 +: ra_width];
rdaddrecc_out_out = rdaddrecc_outreg;
if (ra_width >= 8)
dopa_out_out[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOA_REG on RAMB36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG);
$finish;
end
endcase
end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg)
// ***** Output Registers **** Port B *****
always @(posedge clkb_in or posedge gsr_in) begin
if (DOB_REG == 1) begin
if (gsr_in == 1'b1) begin
dob_outreg <= INIT_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= INIT_B[rb_width +: rb_widthp];
end
else if (gsr_in == 1'b0) begin
if (rstreg_priority_b_int == 0) begin // Virtex5 behavior
if (regceb_in == 1'b1) begin
if (rstregb_in == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (rstregb_in == 1'b0) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end // if (regceb_in == 1'b1)
end // if (rstreg_priority_b_int == 1'b0)
else begin
if (rstregb_in == 1'b1) begin
dob_outreg <= SRVAL_B[0 +: rb_width];
if (rb_width >= 8)
dopb_outreg <= SRVAL_B[rb_width +: rb_widthp];
end
else if (rstregb_in == 1'b0) begin
if (regceb_in == 1'b1) begin
dob_outreg <= dob_out;
if (rb_width >= 8)
dopb_outreg <= dopb_out;
end
end
end // else: !if(rstreg_priority_b_int == 1'b0)
end // if (gsr_in == 1'b0)
end // if (DOB_REG == 1)
end // always @ (posedge clkb_in or posedge gsr_in)
always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin
case (DOB_REG)
0 : begin
dob_out_out[0 +: rb_width] = dob_out_mux[0 +: rb_width];
if (rb_width >= 8)
dopb_out_out[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp];
end
1 : begin
dob_out_out[0 +: rb_width] = dob_outreg_mux[0 +: rb_width];
if (rb_width >= 8)
dopb_out_out[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp];
end
default : begin
$display("Attribute Syntax Error : The attribute DOB_REG on RAMB36E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG);
$finish;
end
endcase
end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux)
endmodule // RB36_INTERNAL_VLOG
`endcelldefine
// end of RB36_INTERNAL_VLOG - Note: Not an user primitive
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMB36E2.v 0000664 0000000 0000000 00000443430 12327044266 0022513 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : RAMB36E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/28/2013 - intial from FIFO
// 03/09/2013 - update from various initial CR - collisions
// 03/19/2013 - 707443 - RDADDRECC not hooked up
// 03/22/2013 - sync5 yaml update, port ordering
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - revert NO_CHANGE fix
// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP
// 04/23/2013 - PR683925 - add invertible pin support.
// 04/26/2013 - 714182 - RDADDRECC bits shifted by 1.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAMB36E2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter integer DOA_REG = 1,
parameter integer DOB_REG = 1,
parameter ENADDRENA = "FALSE",
parameter ENADDRENB = "FALSE",
parameter EN_ECC_PIPE = "FALSE",
parameter EN_ECC_READ = "FALSE",
parameter EN_ECC_WRITE = "FALSE",
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [35:0] INIT_A = 36'h000000000,
parameter [35:0] INIT_B = 36'h000000000,
parameter INIT_FILE = "NONE",
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0,
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0,
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0,
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0,
parameter RDADDRCHANGEA = "FALSE",
parameter RDADDRCHANGEB = "FALSE",
parameter integer READ_WIDTH_A = 0,
parameter integer READ_WIDTH_B = 0,
parameter RSTREG_PRIORITY_A = "RSTREG",
parameter RSTREG_PRIORITY_B = "RSTREG",
parameter SIM_COLLISION_CHECK = "ALL",
parameter SLEEP_ASYNC = "FALSE",
parameter [35:0] SRVAL_A = 36'h000000000,
parameter [35:0] SRVAL_B = 36'h000000000,
parameter WRITE_MODE_A = "NO_CHANGE",
parameter WRITE_MODE_B = "NO_CHANGE",
parameter integer WRITE_WIDTH_A = 0,
parameter integer WRITE_WIDTH_B = 0
)(
output [31:0] CASDOUTA,
output [31:0] CASDOUTB,
output [3:0] CASDOUTPA,
output [3:0] CASDOUTPB,
output CASOUTDBITERR,
output CASOUTSBITERR,
output DBITERR,
output [31:0] DOUTADOUT,
output [31:0] DOUTBDOUT,
output [3:0] DOUTPADOUTP,
output [3:0] DOUTPBDOUTP,
output [7:0] ECCPARITY,
output [8:0] RDADDRECC,
output SBITERR,
input [14:0] ADDRARDADDR,
input [14:0] ADDRBWRADDR,
input ADDRENA,
input ADDRENB,
input CASDIMUXA,
input CASDIMUXB,
input [31:0] CASDINA,
input [31:0] CASDINB,
input [3:0] CASDINPA,
input [3:0] CASDINPB,
input CASDOMUXA,
input CASDOMUXB,
input CASDOMUXEN_A,
input CASDOMUXEN_B,
input CASINDBITERR,
input CASINSBITERR,
input CASOREGIMUXA,
input CASOREGIMUXB,
input CASOREGIMUXEN_A,
input CASOREGIMUXEN_B,
input CLKARDCLK,
input CLKBWRCLK,
input [31:0] DINADIN,
input [31:0] DINBDIN,
input [3:0] DINPADINP,
input [3:0] DINPBDINP,
input ECCPIPECE,
input ENARDEN,
input ENBWREN,
input INJECTDBITERR,
input INJECTSBITERR,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input SLEEP,
input [3:0] WEA,
input [7:0] WEBWE
);
// define constants
localparam MODULE_NAME = "RAMB36E2";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
integer t_coll_min = 48;
integer t_coll_max = 2998;
localparam integer ADDR_WIDTH = 15;
localparam integer INIT_WIDTH = 72;
localparam integer D_WIDTH = 64;
localparam integer DP_WIDTH = 8;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_depth = 32768;
localparam memp_depth = 4096;
localparam encode = 1'b1;
localparam decode = 1'b0;
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam DOA_REG_0 = 1;
localparam DOA_REG_1 = 0;
localparam DOB_REG_0 = 1;
localparam DOB_REG_1 = 0;
localparam ENADDRENA_FALSE = 0;
localparam ENADDRENA_TRUE = 1;
localparam ENADDRENB_FALSE = 0;
localparam ENADDRENB_TRUE = 1;
localparam EN_ECC_PIPE_FALSE = 0;
localparam EN_ECC_PIPE_TRUE = 1;
localparam EN_ECC_READ_FALSE = 0;
localparam EN_ECC_READ_TRUE = 1;
localparam EN_ECC_WRITE_FALSE = 0;
localparam EN_ECC_WRITE_TRUE = 1;
localparam RDADDRCHANGEA_FALSE = 0;
localparam RDADDRCHANGEA_TRUE = 1;
localparam RDADDRCHANGEB_FALSE = 0;
localparam RDADDRCHANGEB_TRUE = 1;
localparam READ_WIDTH_A_0 = 1;
localparam READ_WIDTH_A_1 = 1;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_2 = 2;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_72 = 64;
localparam READ_WIDTH_A_9 = 8;
localparam READ_WIDTH_B_0 = 1;
localparam READ_WIDTH_B_1 = 1;
localparam READ_WIDTH_B_18 = 16;
localparam READ_WIDTH_B_2 = 2;
localparam READ_WIDTH_B_36 = 32;
localparam READ_WIDTH_B_4 = 4;
localparam READ_WIDTH_B_9 = 8;
localparam RSTREG_PRIORITY_A_REGCE = 1;
localparam RSTREG_PRIORITY_A_RSTREG = 0;
localparam RSTREG_PRIORITY_B_REGCE = 1;
localparam RSTREG_PRIORITY_B_RSTREG = 0;
localparam SIM_COLLISION_CHECK_ALL = 0;
localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1;
localparam SIM_COLLISION_CHECK_NONE = 2;
localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRITE_MODE_A_NO_CHANGE = 0;
localparam WRITE_MODE_A_READ_FIRST = 1;
localparam WRITE_MODE_A_WRITE_FIRST = 2;
localparam WRITE_MODE_B_NO_CHANGE = 0;
localparam WRITE_MODE_B_READ_FIRST = 1;
localparam WRITE_MODE_B_WRITE_FIRST = 2;
localparam WRITE_WIDTH_A_0 = 1;
localparam WRITE_WIDTH_A_1 = 1;
localparam WRITE_WIDTH_A_18 = 16;
localparam WRITE_WIDTH_A_2 = 2;
localparam WRITE_WIDTH_A_36 = 32;
localparam WRITE_WIDTH_A_4 = 4;
localparam WRITE_WIDTH_A_9 = 8;
localparam WRITE_WIDTH_B_0 = 1;
localparam WRITE_WIDTH_B_1 = 1;
localparam WRITE_WIDTH_B_18 = 16;
localparam WRITE_WIDTH_B_2 = 2;
localparam WRITE_WIDTH_B_36 = 32;
localparam WRITE_WIDTH_B_4 = 4;
localparam WRITE_WIDTH_B_72 = 64;
localparam WRITE_WIDTH_B_9 = 8;
`ifndef XIL_DR
localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [0:0] DOA_REG_REG = DOA_REG;
localparam [0:0] DOB_REG_REG = DOB_REG;
localparam [40:1] ENADDRENA_REG = ENADDRENA;
localparam [40:1] ENADDRENB_REG = ENADDRENB;
localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE;
localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ;
localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE;
localparam [255:0] INITP_00_REG = INITP_00;
localparam [255:0] INITP_01_REG = INITP_01;
localparam [255:0] INITP_02_REG = INITP_02;
localparam [255:0] INITP_03_REG = INITP_03;
localparam [255:0] INITP_04_REG = INITP_04;
localparam [255:0] INITP_05_REG = INITP_05;
localparam [255:0] INITP_06_REG = INITP_06;
localparam [255:0] INITP_07_REG = INITP_07;
localparam [255:0] INITP_08_REG = INITP_08;
localparam [255:0] INITP_09_REG = INITP_09;
localparam [255:0] INITP_0A_REG = INITP_0A;
localparam [255:0] INITP_0B_REG = INITP_0B;
localparam [255:0] INITP_0C_REG = INITP_0C;
localparam [255:0] INITP_0D_REG = INITP_0D;
localparam [255:0] INITP_0E_REG = INITP_0E;
localparam [255:0] INITP_0F_REG = INITP_0F;
localparam [255:0] INIT_00_REG = INIT_00;
localparam [255:0] INIT_01_REG = INIT_01;
localparam [255:0] INIT_02_REG = INIT_02;
localparam [255:0] INIT_03_REG = INIT_03;
localparam [255:0] INIT_04_REG = INIT_04;
localparam [255:0] INIT_05_REG = INIT_05;
localparam [255:0] INIT_06_REG = INIT_06;
localparam [255:0] INIT_07_REG = INIT_07;
localparam [255:0] INIT_08_REG = INIT_08;
localparam [255:0] INIT_09_REG = INIT_09;
localparam [255:0] INIT_0A_REG = INIT_0A;
localparam [255:0] INIT_0B_REG = INIT_0B;
localparam [255:0] INIT_0C_REG = INIT_0C;
localparam [255:0] INIT_0D_REG = INIT_0D;
localparam [255:0] INIT_0E_REG = INIT_0E;
localparam [255:0] INIT_0F_REG = INIT_0F;
localparam [255:0] INIT_10_REG = INIT_10;
localparam [255:0] INIT_11_REG = INIT_11;
localparam [255:0] INIT_12_REG = INIT_12;
localparam [255:0] INIT_13_REG = INIT_13;
localparam [255:0] INIT_14_REG = INIT_14;
localparam [255:0] INIT_15_REG = INIT_15;
localparam [255:0] INIT_16_REG = INIT_16;
localparam [255:0] INIT_17_REG = INIT_17;
localparam [255:0] INIT_18_REG = INIT_18;
localparam [255:0] INIT_19_REG = INIT_19;
localparam [255:0] INIT_1A_REG = INIT_1A;
localparam [255:0] INIT_1B_REG = INIT_1B;
localparam [255:0] INIT_1C_REG = INIT_1C;
localparam [255:0] INIT_1D_REG = INIT_1D;
localparam [255:0] INIT_1E_REG = INIT_1E;
localparam [255:0] INIT_1F_REG = INIT_1F;
localparam [255:0] INIT_20_REG = INIT_20;
localparam [255:0] INIT_21_REG = INIT_21;
localparam [255:0] INIT_22_REG = INIT_22;
localparam [255:0] INIT_23_REG = INIT_23;
localparam [255:0] INIT_24_REG = INIT_24;
localparam [255:0] INIT_25_REG = INIT_25;
localparam [255:0] INIT_26_REG = INIT_26;
localparam [255:0] INIT_27_REG = INIT_27;
localparam [255:0] INIT_28_REG = INIT_28;
localparam [255:0] INIT_29_REG = INIT_29;
localparam [255:0] INIT_2A_REG = INIT_2A;
localparam [255:0] INIT_2B_REG = INIT_2B;
localparam [255:0] INIT_2C_REG = INIT_2C;
localparam [255:0] INIT_2D_REG = INIT_2D;
localparam [255:0] INIT_2E_REG = INIT_2E;
localparam [255:0] INIT_2F_REG = INIT_2F;
localparam [255:0] INIT_30_REG = INIT_30;
localparam [255:0] INIT_31_REG = INIT_31;
localparam [255:0] INIT_32_REG = INIT_32;
localparam [255:0] INIT_33_REG = INIT_33;
localparam [255:0] INIT_34_REG = INIT_34;
localparam [255:0] INIT_35_REG = INIT_35;
localparam [255:0] INIT_36_REG = INIT_36;
localparam [255:0] INIT_37_REG = INIT_37;
localparam [255:0] INIT_38_REG = INIT_38;
localparam [255:0] INIT_39_REG = INIT_39;
localparam [255:0] INIT_3A_REG = INIT_3A;
localparam [255:0] INIT_3B_REG = INIT_3B;
localparam [255:0] INIT_3C_REG = INIT_3C;
localparam [255:0] INIT_3D_REG = INIT_3D;
localparam [255:0] INIT_3E_REG = INIT_3E;
localparam [255:0] INIT_3F_REG = INIT_3F;
localparam [255:0] INIT_40_REG = INIT_40;
localparam [255:0] INIT_41_REG = INIT_41;
localparam [255:0] INIT_42_REG = INIT_42;
localparam [255:0] INIT_43_REG = INIT_43;
localparam [255:0] INIT_44_REG = INIT_44;
localparam [255:0] INIT_45_REG = INIT_45;
localparam [255:0] INIT_46_REG = INIT_46;
localparam [255:0] INIT_47_REG = INIT_47;
localparam [255:0] INIT_48_REG = INIT_48;
localparam [255:0] INIT_49_REG = INIT_49;
localparam [255:0] INIT_4A_REG = INIT_4A;
localparam [255:0] INIT_4B_REG = INIT_4B;
localparam [255:0] INIT_4C_REG = INIT_4C;
localparam [255:0] INIT_4D_REG = INIT_4D;
localparam [255:0] INIT_4E_REG = INIT_4E;
localparam [255:0] INIT_4F_REG = INIT_4F;
localparam [255:0] INIT_50_REG = INIT_50;
localparam [255:0] INIT_51_REG = INIT_51;
localparam [255:0] INIT_52_REG = INIT_52;
localparam [255:0] INIT_53_REG = INIT_53;
localparam [255:0] INIT_54_REG = INIT_54;
localparam [255:0] INIT_55_REG = INIT_55;
localparam [255:0] INIT_56_REG = INIT_56;
localparam [255:0] INIT_57_REG = INIT_57;
localparam [255:0] INIT_58_REG = INIT_58;
localparam [255:0] INIT_59_REG = INIT_59;
localparam [255:0] INIT_5A_REG = INIT_5A;
localparam [255:0] INIT_5B_REG = INIT_5B;
localparam [255:0] INIT_5C_REG = INIT_5C;
localparam [255:0] INIT_5D_REG = INIT_5D;
localparam [255:0] INIT_5E_REG = INIT_5E;
localparam [255:0] INIT_5F_REG = INIT_5F;
localparam [255:0] INIT_60_REG = INIT_60;
localparam [255:0] INIT_61_REG = INIT_61;
localparam [255:0] INIT_62_REG = INIT_62;
localparam [255:0] INIT_63_REG = INIT_63;
localparam [255:0] INIT_64_REG = INIT_64;
localparam [255:0] INIT_65_REG = INIT_65;
localparam [255:0] INIT_66_REG = INIT_66;
localparam [255:0] INIT_67_REG = INIT_67;
localparam [255:0] INIT_68_REG = INIT_68;
localparam [255:0] INIT_69_REG = INIT_69;
localparam [255:0] INIT_6A_REG = INIT_6A;
localparam [255:0] INIT_6B_REG = INIT_6B;
localparam [255:0] INIT_6C_REG = INIT_6C;
localparam [255:0] INIT_6D_REG = INIT_6D;
localparam [255:0] INIT_6E_REG = INIT_6E;
localparam [255:0] INIT_6F_REG = INIT_6F;
localparam [255:0] INIT_70_REG = INIT_70;
localparam [255:0] INIT_71_REG = INIT_71;
localparam [255:0] INIT_72_REG = INIT_72;
localparam [255:0] INIT_73_REG = INIT_73;
localparam [255:0] INIT_74_REG = INIT_74;
localparam [255:0] INIT_75_REG = INIT_75;
localparam [255:0] INIT_76_REG = INIT_76;
localparam [255:0] INIT_77_REG = INIT_77;
localparam [255:0] INIT_78_REG = INIT_78;
localparam [255:0] INIT_79_REG = INIT_79;
localparam [255:0] INIT_7A_REG = INIT_7A;
localparam [255:0] INIT_7B_REG = INIT_7B;
localparam [255:0] INIT_7C_REG = INIT_7C;
localparam [255:0] INIT_7D_REG = INIT_7D;
localparam [255:0] INIT_7E_REG = INIT_7E;
localparam [255:0] INIT_7F_REG = INIT_7F;
localparam [35:0] INIT_A_REG = INIT_A;
localparam [35:0] INIT_B_REG = INIT_B;
localparam INIT_FILE_REG = INIT_FILE;
localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED;
localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED;
localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED;
localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED;
localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED;
localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED;
localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED;
localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED;
localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA;
localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB;
localparam [6:0] READ_WIDTH_A_REG = READ_WIDTH_A;
localparam [5:0] READ_WIDTH_B_REG = READ_WIDTH_B;
localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A;
localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B;
localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [35:0] SRVAL_A_REG = SRVAL_A;
localparam [35:0] SRVAL_B_REG = SRVAL_B;
localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A;
localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B;
localparam [5:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A;
localparam [6:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B;
`endif
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire CLOCK_DOMAINS_BIN;
wire DOA_REG_BIN;
wire DOB_REG_BIN;
wire ENADDRENA_BIN;
wire ENADDRENB_BIN;
wire EN_ECC_PIPE_BIN;
wire EN_ECC_READ_BIN;
wire EN_ECC_WRITE_BIN;
wire [255:0] INITP_BIN [0:15];
reg [255:0] INITP_TMP;
wire [255:0] INIT_BIN [0:127];
reg [255:0] INIT_TMP;
wire [INIT_WIDTH/2-1:0] INIT_A_BIN;
wire [INIT_WIDTH/2-1:0] INIT_B_BIN;
// wire INIT_FILE_BIN;
wire IS_CLKARDCLK_INVERTED_BIN;
wire IS_CLKBWRCLK_INVERTED_BIN;
wire IS_ENARDEN_INVERTED_BIN;
wire IS_ENBWREN_INVERTED_BIN;
wire IS_RSTRAMARSTRAM_INVERTED_BIN;
wire IS_RSTRAMB_INVERTED_BIN;
wire IS_RSTREGARSTREG_INVERTED_BIN;
wire IS_RSTREGB_INVERTED_BIN;
wire RDADDRCHANGEA_BIN;
wire RDADDRCHANGEB_BIN;
wire [6:0] READ_WIDTH_A_BIN;
wire [6:0] READ_WIDTH_B_BIN;
wire RSTREG_PRIORITY_A_BIN;
wire RSTREG_PRIORITY_B_BIN;
wire [1:0] SIM_COLLISION_CHECK_BIN;
wire SLEEP_ASYNC_BIN;
wire [INIT_WIDTH/2-1:0] SRVAL_A_BIN;
wire [INIT_WIDTH/2-1:0] SRVAL_B_BIN;
wire [1:0] WRITE_MODE_A_BIN;
wire [1:0] WRITE_MODE_B_BIN;
wire [6:0] WRITE_WIDTH_A_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
reg trig_gsr = 1'b0;
tri0 glblGSR = glbl.GSR || trig_gsr;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RAMB36E2_dr.v"
`endif
wire CASOUTDBITERR_out;
wire CASOUTSBITERR_out;
wire DBITERR_out;
wire SBITERR_out;
wire [D_WIDTH/2-1:0] CASDOUTA_out;
wire [D_WIDTH/2-1:0] CASDOUTB_out;
wire [DP_WIDTH/2-1:0] CASDOUTPA_out;
wire [DP_WIDTH/2-1:0] CASDOUTPB_out;
wire [D_WIDTH/2-1:0] DOUTADOUT_out;
wire [D_WIDTH/2-1:0] DOUTBDOUT_out;
wire [DP_WIDTH/2-1:0] DOUTPADOUTP_out;
wire [DP_WIDTH/2-1:0] DOUTPBDOUTP_out;
wire [7:0] ECCPARITY_out;
wire [8:0] RDADDRECC_out;
wire CASOUTDBITERR_delay;
wire CASOUTSBITERR_delay;
wire DBITERR_delay;
wire SBITERR_delay;
wire [31:0] CASDOUTA_delay;
wire [31:0] CASDOUTB_delay;
wire [31:0] DOUTADOUT_delay;
wire [31:0] DOUTBDOUT_delay;
wire [3:0] CASDOUTPA_delay;
wire [3:0] CASDOUTPB_delay;
wire [3:0] DOUTPADOUTP_delay;
wire [3:0] DOUTPBDOUTP_delay;
wire [7:0] ECCPARITY_delay;
wire [8:0] RDADDRECC_delay;
wire ADDRENA_in;
wire ADDRENB_in;
wire CASDIMUXA_in;
wire CASDIMUXB_in;
wire CASDOMUXA_in;
wire CASDOMUXB_in;
wire CASDOMUXEN_A_in;
wire CASDOMUXEN_B_in;
wire CASINDBITERR_in;
wire CASINSBITERR_in;
wire CASOREGIMUXA_in;
wire CASOREGIMUXB_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXEN_B_in;
wire CLKARDCLK_in;
wire CLKBWRCLK_in;
wire ECCPIPECE_in;
wire ENARDEN_in;
wire ENBWREN_in;
wire INJECTDBITERR_in;
wire INJECTSBITERR_in;
wire REGCEAREGCE_in;
wire REGCEB_in;
wire RSTRAMARSTRAM_in;
wire RSTRAMB_in;
wire RSTREGARSTREG_in;
wire RSTREGB_in;
wire SLEEP_in;
wire [14:0] ADDRARDADDR_in;
wire [14:0] ADDRBWRADDR_in;
wire [D_WIDTH/2-1:0] CASDINA_in;
wire [D_WIDTH/2-1:0] CASDINB_in;
wire [D_WIDTH/2-1:0] DINADIN_in;
wire [D_WIDTH/2-1:0] DINBDIN_in;
wire [3:0] CASDINPA_in;
wire [3:0] CASDINPB_in;
wire [DP_WIDTH/2-1:0] DINPADINP_in;
wire [DP_WIDTH/2-1:0] DINPBDINP_in;
wire [3:0] WEA_in;
wire [7:0] WEBWE_in;
wire ADDRENA_delay;
wire ADDRENB_delay;
wire CASDIMUXA_delay;
wire CASDIMUXB_delay;
wire CASDOMUXA_delay;
wire CASDOMUXB_delay;
wire CASDOMUXEN_A_delay;
wire CASDOMUXEN_B_delay;
wire CASINDBITERR_delay;
wire CASINSBITERR_delay;
wire CASOREGIMUXA_delay;
wire CASOREGIMUXB_delay;
wire CASOREGIMUXEN_A_delay;
wire CASOREGIMUXEN_B_delay;
wire CLKARDCLK_delay;
wire CLKBWRCLK_delay;
wire ECCPIPECE_delay;
wire ENARDEN_delay;
wire ENBWREN_delay;
wire INJECTDBITERR_delay;
wire INJECTSBITERR_delay;
wire REGCEAREGCE_delay;
wire REGCEB_delay;
wire RSTRAMARSTRAM_delay;
wire RSTRAMB_delay;
wire RSTREGARSTREG_delay;
wire RSTREGB_delay;
wire SLEEP_delay;
wire [14:0] ADDRARDADDR_delay;
wire [14:0] ADDRBWRADDR_delay;
wire [31:0] CASDINA_delay;
wire [31:0] CASDINB_delay;
wire [31:0] DINADIN_delay;
wire [31:0] DINBDIN_delay;
wire [3:0] CASDINPA_delay;
wire [3:0] CASDINPB_delay;
wire [3:0] DINPADINP_delay;
wire [3:0] DINPBDINP_delay;
wire [3:0] WEA_delay;
wire [7:0] WEBWE_delay;
// internal variables, signals, busses
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer wb=0;
integer rb=0;
integer rbb=0;
integer wa=0;
integer rd_loops_a = 1;
integer wr_loops_a = 1;
integer rd_loops_b = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
reg INIT_MEM = 0;
wire RDEN_ecc;
wire SLEEP_int;
reg SLEEP_reg = 1'b0;
reg SLEEP_reg1 = 1'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire RSTREG_B_int;
wire REGCE_B_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
reg CASDOMUXB_reg = 1'b0;
reg CASOREGIMUXB_reg = 1'b0;
wire CASDOMUXB_int;
reg [6:0] error_bit = 7'b0;
reg [DP_WIDTH-1:0] eccparity_reg;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire [INIT_WIDTH/2-1:0] INIT_B_int;
wire [INIT_WIDTH/2-1:0] SRVAL_B_int;
wire mem_wr_clk_a;
wire mem_wr_en_a;
reg mem_wr_en_a_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_a;
wire [DP_WIDTH-1:0] memp_we_a;
wire [D_WIDTH/2-1:0] mem_rm_doutb;
wire [DP_WIDTH/2-1:0] memp_rm_doutb;
wire [D_WIDTH-1:0] mem_rm_a;
wire [D_WIDTH-1:0] mem_rm_b;
wire [D_WIDTH-1:0] mem_wm_a;
wire [D_WIDTH-1:0] mem_wm_b;
reg wr_data_matches = 0;
reg wr_a_data_matches_rd_b_data = 0;
reg wr_b_data_matches_rd_a_data = 0;
wire mem_wr_clk_b;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_clk_a;
wire mem_rd_en_a;
wire mem_rst_a;
wire mem_rd_clk_b;
wire mem_rd_en_b;
wire mem_rst_b;
reg mem [0 : mem_depth-1];
wire [D_WIDTH/2-1 : 0] mem_wr_a;
reg wr_a_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_a;
reg [D_WIDTH-1 : 0] mem_rd_a_rf;
reg [D_WIDTH-1 : 0] mem_rd_a_wf;
wire [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
wire [D_WIDTH-1 : 0] mem_a_reg_mux;
wire [D_WIDTH-1 : 0] mem_a_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
wire [D_WIDTH-1 : 0] mem_a_out;
reg [D_WIDTH-1 : 0] mem_a_pipe;
reg [D_WIDTH/2-1 : 0] mem_b_reg;
wire [D_WIDTH/2-1 : 0] mem_b_reg_mux;
wire [D_WIDTH/2-1 : 0] mem_b_mux;
reg [D_WIDTH/2-1 : 0] mem_b_lat;
wire [D_WIDTH/2-1 : 0] mem_b_out;
reg memp [0 : memp_depth - 1];
wire [DP_WIDTH-1 : 0] memp_wr_a;
reg [DP_WIDTH-1 : 0] memp_rd_a;
reg [DP_WIDTH-1 : 0] memp_rd_a_rf;
reg [DP_WIDTH-1 : 0] memp_rd_a_wf;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
wire [DP_WIDTH-1 : 0] memp_a_reg_mux;
wire [DP_WIDTH-1 : 0] memp_a_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
wire [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH-1 : 0] memp_a_pipe;
reg [DP_WIDTH/2-1 : 0] memp_b_reg;
wire [DP_WIDTH/2-1 : 0] memp_b_reg_mux;
wire [DP_WIDTH/2-1 : 0] memp_b_mux;
reg [DP_WIDTH/2-1 : 0] memp_b_lat;
wire [DP_WIDTH/2-1 : 0] memp_b_out;
wire dbit_int;
wire sbit_int;
reg dbit_lat = 0;
reg sbit_lat = 0;
reg dbit_pipe = 0;
reg sbit_pipe = 0;
reg dbit_reg = 0;
reg sbit_reg = 0;
wire [8:0] r_a_ecc_int;
wire [8:0] r_a_ecc_ecc;
reg [8:0] r_a_ecc_lat = 9'b0;
reg [8:0] r_a_ecc_pipe = 9'b0;
reg [8:0] r_a_ecc_reg = 9'b0;
wire [D_WIDTH-1 : 0] mem_a_ecc;
wire [D_WIDTH-1 : 0] mem_a_ecc_cor;
wire [DP_WIDTH-1 : 0] memp_a_ecc;
wire [DP_WIDTH-1 : 0] memp_a_ecc_cor;
wire [ADDR_WIDTH-1:0] rd_addr_a_mask;
wire [ADDR_WIDTH-1:0] rd_addr_b_mask;
wire [ADDR_WIDTH-1:0] wr_addr_a_mask;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] rd_addr_b = 0;
reg [ADDR_WIDTH-1:0] wr_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
wire wr_a_rd_b_addr_coll;
wire wr_addr_coll;
wire wr_b_rd_a_addr_coll;
wire [7:0] synd_wr;
wire [7:0] synd_rd;
wire [7:0] synd_ecc;
wire wrclk_ecc_out;
wire sdp_mode;
wire sdp_mode_wr;
wire sdp_mode_rd;
// clk period for collision window variables
integer t_max_a=3000, t_max_b=3000;
reg clka_done=1'b0, clkb_done=1'b0, clkb_toggled=1'b0;
reg clka_timeout=0, clkb_timeout=0;
wire clks_done;
reg en_clk_sync = 1'b0;
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
// input output assignments
assign #(out_delay) CASDOUTA = CASDOUTA_delay;
assign #(out_delay) CASDOUTB = CASDOUTB_delay;
assign #(out_delay) CASDOUTPA = CASDOUTPA_delay;
assign #(out_delay) CASDOUTPB = CASDOUTPB_delay;
assign #(out_delay) CASOUTDBITERR = CASOUTDBITERR_delay;
assign #(out_delay) CASOUTSBITERR = CASOUTSBITERR_delay;
assign #(out_delay) DBITERR = DBITERR_delay;
assign #(out_delay) DOUTADOUT = DOUTADOUT_delay;
assign #(out_delay) DOUTBDOUT = DOUTBDOUT_delay;
assign #(out_delay) DOUTPADOUTP = DOUTPADOUTP_delay;
assign #(out_delay) DOUTPBDOUTP = DOUTPBDOUTP_delay;
assign #(out_delay) ECCPARITY = ECCPARITY_delay;
assign #(out_delay) RDADDRECC = RDADDRECC_delay;
assign #(out_delay) SBITERR = SBITERR_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLKARDCLK_delay = CLKARDCLK;
assign #(inclk_delay) CLKBWRCLK_delay = CLKBWRCLK;
assign #(in_delay) ADDRARDADDR_delay = ADDRARDADDR;
assign #(in_delay) ADDRBWRADDR_delay = ADDRBWRADDR;
assign #(in_delay) ADDRENA_delay = ADDRENA;
assign #(in_delay) ADDRENB_delay = ADDRENB;
assign #(in_delay) CASDIMUXA_delay = CASDIMUXA;
assign #(in_delay) CASDIMUXB_delay = CASDIMUXB;
assign #(in_delay) CASDINA_delay = CASDINA;
assign #(in_delay) CASDINB_delay = CASDINB;
assign #(in_delay) CASDINPA_delay = CASDINPA;
assign #(in_delay) CASDINPB_delay = CASDINPB;
assign #(in_delay) CASDOMUXA_delay = CASDOMUXA;
assign #(in_delay) CASDOMUXB_delay = CASDOMUXB;
assign #(in_delay) CASDOMUXEN_A_delay = CASDOMUXEN_A;
assign #(in_delay) CASDOMUXEN_B_delay = CASDOMUXEN_B;
assign #(in_delay) CASINDBITERR_delay = CASINDBITERR;
assign #(in_delay) CASINSBITERR_delay = CASINSBITERR;
assign #(in_delay) CASOREGIMUXA_delay = CASOREGIMUXA;
assign #(in_delay) CASOREGIMUXB_delay = CASOREGIMUXB;
assign #(in_delay) CASOREGIMUXEN_A_delay = CASOREGIMUXEN_A;
assign #(in_delay) CASOREGIMUXEN_B_delay = CASOREGIMUXEN_B;
assign #(in_delay) DINADIN_delay = DINADIN;
assign #(in_delay) DINBDIN_delay = DINBDIN;
assign #(in_delay) DINPADINP_delay = DINPADINP;
assign #(in_delay) DINPBDINP_delay = DINPBDINP;
assign #(in_delay) ECCPIPECE_delay = ECCPIPECE;
assign #(in_delay) ENARDEN_delay = ENARDEN;
assign #(in_delay) ENBWREN_delay = ENBWREN;
assign #(in_delay) INJECTDBITERR_delay = INJECTDBITERR;
assign #(in_delay) INJECTSBITERR_delay = INJECTSBITERR;
assign #(in_delay) REGCEAREGCE_delay = REGCEAREGCE;
assign #(in_delay) REGCEB_delay = REGCEB;
assign #(in_delay) RSTRAMARSTRAM_delay = RSTRAMARSTRAM;
assign #(in_delay) RSTRAMB_delay = RSTRAMB;
assign #(in_delay) RSTREGARSTREG_delay = RSTREGARSTREG;
assign #(in_delay) RSTREGB_delay = RSTREGB;
assign #(in_delay) SLEEP_delay = SLEEP;
assign #(in_delay) WEA_delay = WEA;
assign #(in_delay) WEBWE_delay = WEBWE;
`endif // `ifndef XIL_TIMING
assign CASDOUTA_delay = CASDOUTA_out;
assign CASDOUTB_delay = CASDOUTB_out;
assign CASDOUTPA_delay = CASDOUTPA_out;
assign CASDOUTPB_delay = CASDOUTPB_out;
assign CASOUTDBITERR_delay = CASOUTDBITERR_out;
assign CASOUTSBITERR_delay = CASOUTSBITERR_out;
assign DBITERR_delay = DBITERR_out;
assign DOUTADOUT_delay = DOUTADOUT_out;
assign DOUTBDOUT_delay = DOUTBDOUT_out;
assign DOUTPADOUTP_delay = DOUTPADOUTP_out;
assign DOUTPBDOUTP_delay = DOUTPBDOUTP_out;
assign ECCPARITY_delay = ECCPARITY_out;
assign RDADDRECC_delay = RDADDRECC_out;
assign SBITERR_delay = SBITERR_out;
assign ADDRARDADDR_in = ADDRARDADDR_delay;
assign ADDRBWRADDR_in = ADDRBWRADDR_delay;
assign ADDRENA_in = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_delay : 1'b1;
assign ADDRENB_in = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_delay : 1'b1;
assign CASDIMUXA_in = CASDIMUXA_delay;
assign CASDIMUXB_in = CASDIMUXB_delay;
assign CASDINA_in = CASDINA_delay;
assign CASDINB_in = CASDINB_delay;
assign CASDINPA_in = CASDINPA_delay;
assign CASDINPB_in = CASDINPB_delay;
assign CASDOMUXA_in = CASDOMUXA_delay;
assign CASDOMUXB_in = CASDOMUXB_delay;
assign CASDOMUXEN_A_in = CASDOMUXEN_A_delay;
assign CASDOMUXEN_B_in = CASDOMUXEN_B_delay;
assign CASINDBITERR_in = CASINDBITERR_delay;
assign CASINSBITERR_in = CASINSBITERR_delay;
assign CASOREGIMUXA_in = CASOREGIMUXA_delay;
assign CASOREGIMUXB_in = CASOREGIMUXB_delay;
assign CASOREGIMUXEN_A_in = CASOREGIMUXEN_A_delay;
assign CASOREGIMUXEN_B_in = CASOREGIMUXEN_B_delay;
assign CLKARDCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT) ||
(en_clk_sync == 1'b0) || (clkb_toggled == 1'b0)) ?
CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN :
CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN;
assign CLKBWRCLK_in = ((CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT) ||
(en_clk_sync == 1'b0) || (clkb_toggled == 1'b1) ||
(clka_done == 1'b0)) ?
CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN :
CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN;
assign DINPADINP_in = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXA_in) ?
CASDINPA_delay : DINPADINP_delay;
assign DINADIN_in = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXA_in) ?
CASDINA_delay : DINADIN_delay;
assign DINPBDINP_in = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXB_in) ?
CASDINPB_delay : DINPBDINP_delay;
assign DINBDIN_in = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDIMUXB_in) ?
CASDINB_delay : DINBDIN_delay;
assign ECCPIPECE_in = ECCPIPECE_delay;
assign ENARDEN_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN;
assign ENBWREN_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN;
assign INJECTDBITERR_in = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTDBITERR_delay;
assign INJECTSBITERR_in = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTSBITERR_delay || INJECTDBITERR_delay;
assign REGCEAREGCE_in = REGCEAREGCE_delay;
assign REGCEB_in = REGCEB_delay;
assign RSTRAMARSTRAM_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN;
assign RSTRAMB_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN;
assign RSTREGARSTREG_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN;
assign RSTREGB_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN;
assign SLEEP_in = SLEEP_delay;
assign WEA_in = WEA_delay;
assign WEBWE_in = WEBWE_delay;
assign mem_rd_clk_a = CLKARDCLK_in;
assign mem_rd_clk_b = sdp_mode ? 1'b0 : CLKBWRCLK_in;
assign mem_wr_clk_a = sdp_mode ? 1'b0 : CLKARDCLK_in;
assign mem_wr_clk_b = CLKBWRCLK_in;
assign mem_rst_a = RSTRAMARSTRAM_in;
assign mem_rst_b = sdp_mode ? RSTRAMARSTRAM_in : RSTRAMB_in;
wire [35:0] bit_err_pat;
assign bit_err_pat = INJECTDBITERR_in ? 36'h400000004 : INJECTSBITERR_in ? 36'h000000004 : 36'h0;
assign mem_wr_a = {32'h0, DINADIN_in};
assign mem_wr_b = (WRITE_WIDTH_B_BIN != WRITE_WIDTH_B_72) ? {32'h0, DINBDIN_in} :
{DINBDIN_in, DINADIN_in} ^ {bit_err_pat, 28'h0};
assign mem_wr_en_a = sdp_mode ? 1'b0 : ENARDEN_in && |WEA_in;
assign mem_rd_en_a = (WRITE_MODE_A_BIN == WRITE_MODE_A_NO_CHANGE) ?
ENARDEN_in && (~mem_wr_en_a || mem_rst_a) : ENARDEN_in;
assign mem_wr_en_b = ENBWREN_in && (sdp_mode ? |WEBWE_in : |WEBWE_in[DP_WIDTH/2-1:0]);
assign mem_rd_en_b = sdp_mode ? 1'b0 :
(WRITE_MODE_B_BIN == WRITE_MODE_B_NO_CHANGE) ?
ENBWREN_in && (~mem_wr_en_b || mem_rst_b) : ENBWREN_in;
assign memp_wr_b[7] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[7] : DINPBDINP_in[3];
assign memp_wr_b[6] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[6] : DINPBDINP_in[2];
assign memp_wr_b[5] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[5] : DINPBDINP_in[1];
assign memp_wr_b[4] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[4] : DINPBDINP_in[0];
assign memp_wr_b[3] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[3] :
(WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? DINPADINP_in[3] : DINPBDINP_in[3];
assign memp_wr_b[2] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[2] :
(WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? DINPADINP_in[2] : DINPBDINP_in[2];
assign memp_wr_b[1] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[1] :
(WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? DINPADINP_in[1] : DINPBDINP_in[1];
assign memp_wr_b[0] = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr[0] :
(WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? DINPADINP_in[0] : DINPBDINP_in[0];
assign memp_wr_a[7] = 1'b0;
assign memp_wr_a[6] = 1'b0;
assign memp_wr_a[5] = 1'b0;
assign memp_wr_a[4] = 1'b0;
assign memp_wr_a[3] = DINPADINP_in[3];
assign memp_wr_a[2] = DINPADINP_in[2];
assign memp_wr_a[1] = DINPADINP_in[1];
assign memp_wr_a[0] = DINPADINP_in[0];
initial begin
trig_attr <= #1 ~trig_attr;
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
CASCADE_ORDER_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign DOA_REG_BIN =
(DOA_REG_REG == 1) ? DOA_REG_1 :
(DOA_REG_REG == 0) ? DOA_REG_0 :
DOA_REG_1;
assign DOB_REG_BIN =
(DOB_REG_REG == 1) ? DOB_REG_1 :
(DOB_REG_REG == 0) ? DOB_REG_0 :
DOB_REG_1;
assign ENADDRENA_BIN =
(ENADDRENA_REG == "FALSE") ? ENADDRENA_FALSE :
(ENADDRENA_REG == "TRUE") ? ENADDRENA_TRUE :
ENADDRENA_FALSE;
assign ENADDRENB_BIN =
(ENADDRENB_REG == "FALSE") ? ENADDRENB_FALSE :
(ENADDRENB_REG == "TRUE") ? ENADDRENB_TRUE :
ENADDRENB_FALSE;
assign EN_ECC_PIPE_BIN =
(EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE :
(EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE :
EN_ECC_PIPE_FALSE;
assign EN_ECC_READ_BIN =
(EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE :
(EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE :
EN_ECC_READ_FALSE;
assign EN_ECC_WRITE_BIN =
(EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE :
(EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE :
EN_ECC_WRITE_FALSE;
assign INITP_BIN['h00] = INITP_00_REG;
assign INITP_BIN['h01] = INITP_01_REG;
assign INITP_BIN['h02] = INITP_02_REG;
assign INITP_BIN['h03] = INITP_03_REG;
assign INITP_BIN['h04] = INITP_04_REG;
assign INITP_BIN['h05] = INITP_05_REG;
assign INITP_BIN['h06] = INITP_06_REG;
assign INITP_BIN['h07] = INITP_07_REG;
assign INITP_BIN['h08] = INITP_08_REG;
assign INITP_BIN['h09] = INITP_09_REG;
assign INITP_BIN['h0A] = INITP_0A_REG;
assign INITP_BIN['h0B] = INITP_0B_REG;
assign INITP_BIN['h0C] = INITP_0C_REG;
assign INITP_BIN['h0D] = INITP_0D_REG;
assign INITP_BIN['h0E] = INITP_0E_REG;
assign INITP_BIN['h0F] = INITP_0F_REG;
assign INIT_BIN['h00] = INIT_00_REG;
assign INIT_BIN['h01] = INIT_01_REG;
assign INIT_BIN['h02] = INIT_02_REG;
assign INIT_BIN['h03] = INIT_03_REG;
assign INIT_BIN['h04] = INIT_04_REG;
assign INIT_BIN['h05] = INIT_05_REG;
assign INIT_BIN['h06] = INIT_06_REG;
assign INIT_BIN['h07] = INIT_07_REG;
assign INIT_BIN['h08] = INIT_08_REG;
assign INIT_BIN['h09] = INIT_09_REG;
assign INIT_BIN['h0A] = INIT_0A_REG;
assign INIT_BIN['h0B] = INIT_0B_REG;
assign INIT_BIN['h0C] = INIT_0C_REG;
assign INIT_BIN['h0D] = INIT_0D_REG;
assign INIT_BIN['h0E] = INIT_0E_REG;
assign INIT_BIN['h0F] = INIT_0F_REG;
assign INIT_BIN['h10] = INIT_10_REG;
assign INIT_BIN['h11] = INIT_11_REG;
assign INIT_BIN['h12] = INIT_12_REG;
assign INIT_BIN['h13] = INIT_13_REG;
assign INIT_BIN['h14] = INIT_14_REG;
assign INIT_BIN['h15] = INIT_15_REG;
assign INIT_BIN['h16] = INIT_16_REG;
assign INIT_BIN['h17] = INIT_17_REG;
assign INIT_BIN['h18] = INIT_18_REG;
assign INIT_BIN['h19] = INIT_19_REG;
assign INIT_BIN['h1A] = INIT_1A_REG;
assign INIT_BIN['h1B] = INIT_1B_REG;
assign INIT_BIN['h1C] = INIT_1C_REG;
assign INIT_BIN['h1D] = INIT_1D_REG;
assign INIT_BIN['h1E] = INIT_1E_REG;
assign INIT_BIN['h1F] = INIT_1F_REG;
assign INIT_BIN['h20] = INIT_20_REG;
assign INIT_BIN['h21] = INIT_21_REG;
assign INIT_BIN['h22] = INIT_22_REG;
assign INIT_BIN['h23] = INIT_23_REG;
assign INIT_BIN['h24] = INIT_24_REG;
assign INIT_BIN['h25] = INIT_25_REG;
assign INIT_BIN['h26] = INIT_26_REG;
assign INIT_BIN['h27] = INIT_27_REG;
assign INIT_BIN['h28] = INIT_28_REG;
assign INIT_BIN['h29] = INIT_29_REG;
assign INIT_BIN['h2A] = INIT_2A_REG;
assign INIT_BIN['h2B] = INIT_2B_REG;
assign INIT_BIN['h2C] = INIT_2C_REG;
assign INIT_BIN['h2D] = INIT_2D_REG;
assign INIT_BIN['h2E] = INIT_2E_REG;
assign INIT_BIN['h2F] = INIT_2F_REG;
assign INIT_BIN['h30] = INIT_30_REG;
assign INIT_BIN['h31] = INIT_31_REG;
assign INIT_BIN['h32] = INIT_32_REG;
assign INIT_BIN['h33] = INIT_33_REG;
assign INIT_BIN['h34] = INIT_34_REG;
assign INIT_BIN['h35] = INIT_35_REG;
assign INIT_BIN['h36] = INIT_36_REG;
assign INIT_BIN['h37] = INIT_37_REG;
assign INIT_BIN['h38] = INIT_38_REG;
assign INIT_BIN['h39] = INIT_39_REG;
assign INIT_BIN['h3A] = INIT_3A_REG;
assign INIT_BIN['h3B] = INIT_3B_REG;
assign INIT_BIN['h3C] = INIT_3C_REG;
assign INIT_BIN['h3D] = INIT_3D_REG;
assign INIT_BIN['h3E] = INIT_3E_REG;
assign INIT_BIN['h3F] = INIT_3F_REG;
assign INIT_BIN['h40] = INIT_40_REG;
assign INIT_BIN['h41] = INIT_41_REG;
assign INIT_BIN['h42] = INIT_42_REG;
assign INIT_BIN['h43] = INIT_43_REG;
assign INIT_BIN['h44] = INIT_44_REG;
assign INIT_BIN['h45] = INIT_45_REG;
assign INIT_BIN['h46] = INIT_46_REG;
assign INIT_BIN['h47] = INIT_47_REG;
assign INIT_BIN['h48] = INIT_48_REG;
assign INIT_BIN['h49] = INIT_49_REG;
assign INIT_BIN['h4A] = INIT_4A_REG;
assign INIT_BIN['h4B] = INIT_4B_REG;
assign INIT_BIN['h4C] = INIT_4C_REG;
assign INIT_BIN['h4D] = INIT_4D_REG;
assign INIT_BIN['h4E] = INIT_4E_REG;
assign INIT_BIN['h4F] = INIT_4F_REG;
assign INIT_BIN['h50] = INIT_50_REG;
assign INIT_BIN['h51] = INIT_51_REG;
assign INIT_BIN['h52] = INIT_52_REG;
assign INIT_BIN['h53] = INIT_53_REG;
assign INIT_BIN['h54] = INIT_54_REG;
assign INIT_BIN['h55] = INIT_55_REG;
assign INIT_BIN['h56] = INIT_56_REG;
assign INIT_BIN['h57] = INIT_57_REG;
assign INIT_BIN['h58] = INIT_58_REG;
assign INIT_BIN['h59] = INIT_59_REG;
assign INIT_BIN['h5A] = INIT_5A_REG;
assign INIT_BIN['h5B] = INIT_5B_REG;
assign INIT_BIN['h5C] = INIT_5C_REG;
assign INIT_BIN['h5D] = INIT_5D_REG;
assign INIT_BIN['h5E] = INIT_5E_REG;
assign INIT_BIN['h5F] = INIT_5F_REG;
assign INIT_BIN['h60] = INIT_60_REG;
assign INIT_BIN['h61] = INIT_61_REG;
assign INIT_BIN['h62] = INIT_62_REG;
assign INIT_BIN['h63] = INIT_63_REG;
assign INIT_BIN['h64] = INIT_64_REG;
assign INIT_BIN['h65] = INIT_65_REG;
assign INIT_BIN['h66] = INIT_66_REG;
assign INIT_BIN['h67] = INIT_67_REG;
assign INIT_BIN['h68] = INIT_68_REG;
assign INIT_BIN['h69] = INIT_69_REG;
assign INIT_BIN['h6A] = INIT_6A_REG;
assign INIT_BIN['h6B] = INIT_6B_REG;
assign INIT_BIN['h6C] = INIT_6C_REG;
assign INIT_BIN['h6D] = INIT_6D_REG;
assign INIT_BIN['h6E] = INIT_6E_REG;
assign INIT_BIN['h6F] = INIT_6F_REG;
assign INIT_BIN['h70] = INIT_70_REG;
assign INIT_BIN['h71] = INIT_71_REG;
assign INIT_BIN['h72] = INIT_72_REG;
assign INIT_BIN['h73] = INIT_73_REG;
assign INIT_BIN['h74] = INIT_74_REG;
assign INIT_BIN['h75] = INIT_75_REG;
assign INIT_BIN['h76] = INIT_76_REG;
assign INIT_BIN['h77] = INIT_77_REG;
assign INIT_BIN['h78] = INIT_78_REG;
assign INIT_BIN['h79] = INIT_79_REG;
assign INIT_BIN['h7A] = INIT_7A_REG;
assign INIT_BIN['h7B] = INIT_7B_REG;
assign INIT_BIN['h7C] = INIT_7C_REG;
assign INIT_BIN['h7D] = INIT_7D_REG;
assign INIT_BIN['h7E] = INIT_7E_REG;
assign INIT_BIN['h7F] = INIT_7F_REG;
assign INIT_A_BIN = INIT_A_REG;
assign INIT_B_BIN = INIT_B_REG;
// assign INIT_FILE_BIN =
// (INIT_FILE_REG == "NONE") ? INIT_FILE_NONE :
// INIT_FILE_NONE;
assign IS_CLKARDCLK_INVERTED_BIN = IS_CLKARDCLK_INVERTED_REG;
assign IS_CLKBWRCLK_INVERTED_BIN = IS_CLKBWRCLK_INVERTED_REG;
assign IS_ENARDEN_INVERTED_BIN = IS_ENARDEN_INVERTED_REG;
assign IS_ENBWREN_INVERTED_BIN = IS_ENBWREN_INVERTED_REG;
assign IS_RSTRAMARSTRAM_INVERTED_BIN = IS_RSTRAMARSTRAM_INVERTED_REG;
assign IS_RSTRAMB_INVERTED_BIN = IS_RSTRAMB_INVERTED_REG;
assign IS_RSTREGARSTREG_INVERTED_BIN = IS_RSTREGARSTREG_INVERTED_REG;
assign IS_RSTREGB_INVERTED_BIN = IS_RSTREGB_INVERTED_REG;
assign RDADDRCHANGEA_BIN =
(RDADDRCHANGEA_REG == "FALSE") ? RDADDRCHANGEA_FALSE :
(RDADDRCHANGEA_REG == "TRUE") ? RDADDRCHANGEA_TRUE :
RDADDRCHANGEA_FALSE;
assign RDADDRCHANGEB_BIN =
(RDADDRCHANGEB_REG == "FALSE") ? RDADDRCHANGEB_FALSE :
(RDADDRCHANGEB_REG == "TRUE") ? RDADDRCHANGEB_TRUE :
RDADDRCHANGEB_FALSE;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_A_REG == 0) ? READ_WIDTH_A_0 :
(READ_WIDTH_A_REG == 1) ? READ_WIDTH_A_1 :
(READ_WIDTH_A_REG == 2) ? READ_WIDTH_A_2 :
(READ_WIDTH_A_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_A_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_A_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_A_REG == 36) ? READ_WIDTH_A_36 :
(READ_WIDTH_A_REG == 72) ? READ_WIDTH_A_72 :
READ_WIDTH_A_0;
assign READ_WIDTH_B_BIN =
(READ_WIDTH_B_REG == 0) ? READ_WIDTH_B_0 :
(READ_WIDTH_B_REG == 1) ? READ_WIDTH_B_1 :
(READ_WIDTH_B_REG == 2) ? READ_WIDTH_B_2 :
(READ_WIDTH_B_REG == 4) ? READ_WIDTH_B_4 :
(READ_WIDTH_B_REG == 9) ? READ_WIDTH_B_9 :
(READ_WIDTH_B_REG == 18) ? READ_WIDTH_B_18 :
(READ_WIDTH_B_REG == 36) ? READ_WIDTH_B_36 :
READ_WIDTH_B_0;
assign RSTREG_PRIORITY_A_BIN =
(RSTREG_PRIORITY_A_REG == "RSTREG") ? RSTREG_PRIORITY_A_RSTREG :
(RSTREG_PRIORITY_A_REG == "REGCE") ? RSTREG_PRIORITY_A_REGCE :
RSTREG_PRIORITY_A_RSTREG;
assign RSTREG_PRIORITY_B_BIN =
(RSTREG_PRIORITY_B_REG == "RSTREG") ? RSTREG_PRIORITY_B_RSTREG :
(RSTREG_PRIORITY_B_REG == "REGCE") ? RSTREG_PRIORITY_B_REGCE :
RSTREG_PRIORITY_B_RSTREG;
assign SIM_COLLISION_CHECK_BIN =
(SIM_COLLISION_CHECK_REG == "ALL") ? SIM_COLLISION_CHECK_ALL :
(SIM_COLLISION_CHECK_REG == "GENERATE_X_ONLY") ? SIM_COLLISION_CHECK_GENERATE_X_ONLY :
(SIM_COLLISION_CHECK_REG == "NONE") ? SIM_COLLISION_CHECK_NONE :
(SIM_COLLISION_CHECK_REG == "WARNING_ONLY") ? SIM_COLLISION_CHECK_WARNING_ONLY :
SIM_COLLISION_CHECK_ALL;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_A_BIN = SRVAL_A_REG;
assign SRVAL_B_BIN = SRVAL_B_REG;
assign WRITE_MODE_A_BIN =
(WRITE_MODE_A_REG == "NO_CHANGE") ? WRITE_MODE_A_NO_CHANGE :
(WRITE_MODE_A_REG == "READ_FIRST") ? WRITE_MODE_A_READ_FIRST :
(WRITE_MODE_A_REG == "WRITE_FIRST") ? WRITE_MODE_A_WRITE_FIRST :
WRITE_MODE_A_NO_CHANGE;
assign WRITE_MODE_B_BIN =
(WRITE_MODE_B_REG == "NO_CHANGE") ? WRITE_MODE_B_NO_CHANGE :
(WRITE_MODE_B_REG == "READ_FIRST") ? WRITE_MODE_B_READ_FIRST :
(WRITE_MODE_B_REG == "WRITE_FIRST") ? WRITE_MODE_B_WRITE_FIRST :
WRITE_MODE_B_NO_CHANGE;
assign WRITE_WIDTH_A_BIN =
(WRITE_WIDTH_A_REG == 0) ? WRITE_WIDTH_A_0 :
(WRITE_WIDTH_A_REG == 1) ? WRITE_WIDTH_A_1 :
(WRITE_WIDTH_A_REG == 2) ? WRITE_WIDTH_A_2 :
(WRITE_WIDTH_A_REG == 4) ? WRITE_WIDTH_A_4 :
(WRITE_WIDTH_A_REG == 9) ? WRITE_WIDTH_A_9 :
(WRITE_WIDTH_A_REG == 18) ? WRITE_WIDTH_A_18 :
(WRITE_WIDTH_A_REG == 36) ? WRITE_WIDTH_A_36 :
WRITE_WIDTH_A_0;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_B_REG == 0) ? WRITE_WIDTH_B_0 :
(WRITE_WIDTH_B_REG == 1) ? WRITE_WIDTH_B_1 :
(WRITE_WIDTH_B_REG == 2) ? WRITE_WIDTH_B_2 :
(WRITE_WIDTH_B_REG == 4) ? WRITE_WIDTH_B_4 :
(WRITE_WIDTH_B_REG == 9) ? WRITE_WIDTH_B_9 :
(WRITE_WIDTH_B_REG == 18) ? WRITE_WIDTH_B_18 :
(WRITE_WIDTH_B_REG == 36) ? WRITE_WIDTH_B_36 :
(WRITE_WIDTH_B_REG == 72) ? WRITE_WIDTH_B_72 :
WRITE_WIDTH_B_0;
always @ (trig_attr) begin
#1;
if ((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER_A on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE.", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE")) begin
$display("Attribute Syntax Error : The attribute CASCADE_ORDER_B on %s instance %m is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE.", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON")) begin
$display("Attribute Syntax Error : The attribute CLOCK_DOMAINS on %s instance %m is set to %s. Legal values for this attribute are INDEPENDENT or COMMON.", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((DOA_REG_REG != 1) &&
(DOA_REG_REG != 0)) begin
$display("Attribute Syntax Error : The attribute DOA_REG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DOA_REG_REG);
attr_err = 1'b1;
end
if ((DOB_REG_REG != 1) &&
(DOB_REG_REG != 0)) begin
$display("Attribute Syntax Error : The attribute DOB_REG on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, DOB_REG_REG);
attr_err = 1'b1;
end
if ((ENADDRENA_REG != "FALSE") &&
(ENADDRENA_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ENADDRENA on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ENADDRENA_REG);
attr_err = 1'b1;
end
if ((ENADDRENB_REG != "FALSE") &&
(ENADDRENB_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute ENADDRENB on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, ENADDRENB_REG);
attr_err = 1'b1;
end
if ((EN_ECC_PIPE_REG != "FALSE") &&
(EN_ECC_PIPE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_PIPE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_PIPE_REG);
attr_err = 1'b1;
end
if ((EN_ECC_READ_REG != "FALSE") &&
(EN_ECC_READ_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_READ_REG);
attr_err = 1'b1;
end
if ((EN_ECC_WRITE_REG != "FALSE") &&
(EN_ECC_WRITE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, EN_ECC_WRITE_REG);
attr_err = 1'b1;
end
if (INIT_FILE_REG != "NONE") begin
$display("INFO : The attribute INIT_FILE on %s instance %m is set to (%s) but loading memory contents from a file is not yet supported.", MODULE_NAME, INIT_FILE_REG);
end
if ((IS_CLKARDCLK_INVERTED_REG < 1'b0) || (IS_CLKARDCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLKARDCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLKBWRCLK_INVERTED_REG < 1'b0) || (IS_CLKBWRCLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLKBWRCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_ENARDEN_INVERTED_REG < 1'b0) || (IS_ENARDEN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_ENARDEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_ENBWREN_INVERTED_REG < 1'b0) || (IS_ENBWREN_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_ENBWREN_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTRAMARSTRAM_INVERTED_REG < 1'b0) || (IS_RSTRAMARSTRAM_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTRAMARSTRAM_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTRAMB_INVERTED_REG < 1'b0) || (IS_RSTRAMB_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTRAMB_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREGARSTREG_INVERTED_REG < 1'b0) || (IS_RSTREGARSTREG_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREGARSTREG_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RSTREGB_INVERTED_REG < 1'b0) || (IS_RSTREGB_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RSTREGB_INVERTED_REG);
attr_err = 1'b1;
end
if ((RDADDRCHANGEA_REG != "FALSE") &&
(RDADDRCHANGEA_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RDADDRCHANGEA on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RDADDRCHANGEA_REG);
attr_err = 1'b1;
end
if ((RDADDRCHANGEB_REG != "FALSE") &&
(RDADDRCHANGEB_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute RDADDRCHANGEB on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, RDADDRCHANGEB_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_A_REG != 0) &&
(READ_WIDTH_A_REG != 1) &&
(READ_WIDTH_A_REG != 2) &&
(READ_WIDTH_A_REG != 4) &&
(READ_WIDTH_A_REG != 9) &&
(READ_WIDTH_A_REG != 18) &&
(READ_WIDTH_A_REG != 36) &&
(READ_WIDTH_A_REG != 72)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_A on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72.", MODULE_NAME, READ_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((READ_WIDTH_B_REG != 0) &&
(READ_WIDTH_B_REG != 1) &&
(READ_WIDTH_B_REG != 2) &&
(READ_WIDTH_B_REG != 4) &&
(READ_WIDTH_B_REG != 9) &&
(READ_WIDTH_B_REG != 18) &&
(READ_WIDTH_B_REG != 36)) begin
$display("Attribute Syntax Error : The attribute READ_WIDTH_B on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", MODULE_NAME, READ_WIDTH_B_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_A_REG != "RSTREG") &&
(RSTREG_PRIORITY_A_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_A_REG);
attr_err = 1'b1;
end
if ((RSTREG_PRIORITY_B_REG != "RSTREG") &&
(RSTREG_PRIORITY_B_REG != "REGCE")) begin
$display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on %s instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", MODULE_NAME, RSTREG_PRIORITY_B_REG);
attr_err = 1'b1;
end
if ((SIM_COLLISION_CHECK_REG != "ALL") &&
(SIM_COLLISION_CHECK_REG != "GENERATE_X_ONLY") &&
(SIM_COLLISION_CHECK_REG != "NONE") &&
(SIM_COLLISION_CHECK_REG != "WARNING_ONLY")) begin
$display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on %s instance %m is set to %s. Legal values for this attribute are ALL, GENERATE_X_ONLY, NONE or WARNING_ONLY.", MODULE_NAME, SIM_COLLISION_CHECK_REG);
attr_err = 1'b1;
end
if ((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute SLEEP_ASYNC on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((WRITE_MODE_A_REG != "NO_CHANGE") &&
(WRITE_MODE_A_REG != "READ_FIRST") &&
(WRITE_MODE_A_REG != "WRITE_FIRST")) begin
$display("Attribute Syntax Error : The attribute WRITE_MODE_A on %s instance %m is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST.", MODULE_NAME, WRITE_MODE_A_REG);
attr_err = 1'b1;
end
if ((WRITE_MODE_B_REG != "NO_CHANGE") &&
(WRITE_MODE_B_REG != "READ_FIRST") &&
(WRITE_MODE_B_REG != "WRITE_FIRST")) begin
$display("Attribute Syntax Error : The attribute WRITE_MODE_B on %s instance %m is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST.", MODULE_NAME, WRITE_MODE_B_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_A_REG != 0) &&
(WRITE_WIDTH_A_REG != 1) &&
(WRITE_WIDTH_A_REG != 2) &&
(WRITE_WIDTH_A_REG != 4) &&
(WRITE_WIDTH_A_REG != 9) &&
(WRITE_WIDTH_A_REG != 18) &&
(WRITE_WIDTH_A_REG != 36)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", MODULE_NAME, WRITE_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((WRITE_WIDTH_B_REG != 0) &&
(WRITE_WIDTH_B_REG != 1) &&
(WRITE_WIDTH_B_REG != 2) &&
(WRITE_WIDTH_B_REG != 4) &&
(WRITE_WIDTH_B_REG != 9) &&
(WRITE_WIDTH_B_REG != 18) &&
(WRITE_WIDTH_B_REG != 36) &&
(WRITE_WIDTH_B_REG != 72)) begin
$display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72.", MODULE_NAME, WRITE_WIDTH_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign rd_addr_a_mask =
(READ_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign rd_addr_b_mask =
(READ_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_a_mask =
(WRITE_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_b_mask =
(WRITE_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(READ_WIDTH_B_BIN) rd_loops_b <= READ_WIDTH_B_BIN;
always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
// determine clk period for collision window.
assign clks_done = clka_done && clkb_done;
//always @(negedge glblGSR) begin
initial begin
@(negedge glblGSR);
clka_timeout = 0;
clka_timeout <= #6000 1;
@(posedge mem_rd_clk_a or posedge clka_timeout);
if (~clka_timeout) begin
t_max_a = 0;
for (i=0;i<2000;i=i+1) begin
if (~clka_done) begin
if (mem_rd_clk_a) begin
#1;
t_max_a = t_max_a + 1;
end
else begin
t_max_a = t_max_a - 1;
clka_done = 1;
i = 2000;
end
end
end
end
clka_done = 1;
end
initial begin
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
clkb_toggled = 1'b1;
end
initial begin
@(negedge glblGSR);
clkb_timeout = 0;
clkb_timeout <= #6000 1;
@(posedge CLKBWRCLK_in or posedge clkb_timeout);
if (~clkb_timeout) begin
t_max_b = 0;
for (j=0;j<2000;j=j+1) begin
if (~clkb_done) begin
if (CLKBWRCLK_in) begin
#1;
t_max_b = t_max_b + 1;
end
else begin
t_max_b = t_max_b - 1;
clkb_done = 1;
j = 2000;
end
end
end
end
clkb_done = 1;
end
initial begin
@(posedge clks_done);
if (((t_max_a > 50) && (t_max_a < 1500)) &&
((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 2;
if (((t_max_b > 50) && (t_max_b < 1500)) &&
((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 2;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) begin
SLEEP_reg <= 1'b0;
SLEEP_reg1 <= 1'b0;
end
else begin
SLEEP_reg <= SLEEP_in;
SLEEP_reg1 <= SLEEP_reg;
end
end
assign SLEEP_int = (SLEEP_ASYNC_BIN == SLEEP_ASYNC_FALSE) ? SLEEP_reg : SLEEP_in;
assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? 1'b1 : 1'b0;
assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ? 1'b1 : 1'b0;
assign sdp_mode = sdp_mode_rd || sdp_mode_wr;
// assign REGCE_A_int = mem_rd_en_a && REGCEAREGCE_in;
// assign REGCE_B_int = mem_rd_en_b && REGCEB_in;
assign REGCE_A_int = REGCEAREGCE_in;
assign REGCE_B_int = REGCEB_in;
assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ?
RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in);
assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ?
RSTREGB_in : (RSTREGB_in && REGCEB_in);
assign RDEN_ecc = mem_rd_en_a;
assign DOUTADOUT_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINA_in : (mem_a_mux ^ mem_rm_douta);
assign DOUTPADOUTP_out = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg) ?
CASDINPA_in : (memp_a_mux ^ memp_rm_douta);
assign DOUTBDOUT_out = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXB_int) ?
CASDINB_in : (mem_b_mux ^ mem_rm_doutb);
assign DOUTPBDOUTP_out = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXB_int) ?
CASDINPB_in : (memp_b_mux ^ memp_rm_doutb);
assign mem_a_mux = (DOA_REG_BIN == DOA_REG_1) ? mem_a_reg : mem_a_out;
assign memp_a_mux = (DOA_REG_BIN == DOA_REG_1) ? memp_a_reg : memp_a_out;
assign mem_a_out = mem_wr_en_a_wf ? mem_rd_a_wf : mem_a_lat;
assign memp_a_out = mem_wr_en_a_wf ? memp_rd_a_wf : memp_a_lat;
assign mem_b_out = mem_wr_en_b_wf ? mem_rd_b_wf : mem_b_lat;
assign memp_b_out = mem_wr_en_b_wf ? memp_rd_b_wf : memp_b_lat;
assign mem_b_mux = sdp_mode_rd ?
((DOA_REG_BIN == DOA_REG_1) ? mem_a_reg[63:32] : mem_a_out[63:32]) :
((DOB_REG_BIN == DOB_REG_1) ? mem_b_reg : mem_b_out);
assign memp_b_mux = sdp_mode_rd ?
((DOA_REG_BIN == DOA_REG_1) ? memp_a_reg[7:4] : memp_a_out[7:4]) :
((DOB_REG_BIN == DOB_REG_1) ? memp_b_reg : memp_b_out);
assign ECCPARITY_out = eccparity_reg;
assign mem_a_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? mem_a_pipe : mem_a_ecc_cor;
assign memp_a_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? memp_a_pipe : memp_a_ecc_cor;
assign dbit_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? dbit_pipe : dbit_int;
assign sbit_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? sbit_pipe : sbit_int;
assign r_a_ecc_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? r_a_ecc_pipe : r_a_ecc_int;
assign DBITERR_out = (DOA_REG_BIN == DOA_REG_1) ? dbit_reg : dbit_lat;
assign SBITERR_out = (DOA_REG_BIN == DOA_REG_1) ? sbit_reg : sbit_lat;
assign RDADDRECC_out = (DOA_REG_BIN == DOA_REG_1) ? r_a_ecc_reg : r_a_ecc_lat;
assign INIT_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{INIT_A_BIN[8]}}, {8{INIT_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{INIT_A_BIN[17:16]}}, {4{INIT_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{INIT_A_BIN[35:32]}}, {2{INIT_A_BIN[31:0]}}} :
{INIT_B_BIN[35:32],INIT_A_BIN[35:32],INIT_B_BIN[31:0],INIT_A_BIN[31:0]};
assign INIT_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{INIT_B_BIN[8]}}, {4{INIT_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{INIT_B_BIN[17:16]}}, {2{INIT_B_BIN[15:0]}}} :
INIT_B_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{SRVAL_A_BIN[8]}}, {8{SRVAL_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{SRVAL_A_BIN[17:16]}}, {4{SRVAL_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{SRVAL_A_BIN[35:32]}}, {2{SRVAL_A_BIN[31:0]}}} :
{SRVAL_B_BIN[35:32],SRVAL_A_BIN[35:32],SRVAL_B_BIN[31:0],SRVAL_A_BIN[31:0]};
assign SRVAL_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{SRVAL_B_BIN[8]}}, {4{SRVAL_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{SRVAL_B_BIN[17:16]}}, {2{SRVAL_B_BIN[15:0]}}} :
SRVAL_B_BIN;
// cascade out
assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTADOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTBDOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}};
// start model internals
// cascade control
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge mem_rd_clk_a) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ?
CASDOMUXA_reg : CASDOMUXB_reg;
always @ (posedge mem_rd_clk_b) begin
if (glblGSR) CASDOMUXB_reg <= 1'b0;
else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in;
end
always @ (posedge mem_rd_clk_b) begin
if (glblGSR) CASOREGIMUXB_reg <= 1'b0;
else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in;
end
// collison detection
wire coll_win_wr_clk_a_min;
wire coll_win_wr_clk_b_min;
wire coll_win_rd_clk_a_min;
wire coll_win_rd_clk_b_min;
reg coll_win_wr_clk_a_ind_min = 1'b0;
reg coll_win_wr_clk_b_ind_min = 1'b0;
reg coll_win_rd_clk_a_ind_min = 1'b0;
reg coll_win_rd_clk_b_ind_min = 1'b0;
reg coll_win_wr_clk_a_max = 1'b0;
reg coll_win_wr_clk_b_max = 1'b0;
reg coll_win_rd_clk_a_max = 1'b0;
reg coll_win_rd_clk_b_max = 1'b0;
wire mem_wr_clk_a_coll;
wire mem_wr_clk_b_coll;
wire mem_rd_clk_a_coll;
wire mem_rd_clk_b_coll;
reg wr_b_wr_a_coll = 1'b0;
reg wr_b_rd_a_coll = 1'b0;
reg rd_b_wr_a_coll = 1'b0;
reg wr_a_wr_b_coll = 1'b0;
reg wr_a_rd_b_coll = 1'b0;
reg rd_a_wr_b_coll = 1'b0;
wire coll_wr_sim;
wire coll_wr_b_wr_a;
wire coll_wr_b_rd_a_sim;
wire coll_wr_b_rd_a;
wire coll_rd_b_wr_a_sim;
wire coll_rd_b_wr_a;
wire coll_wr_a_wr_b;
wire coll_wr_a_rd_b_sim;
wire coll_wr_a_rd_b;
wire coll_rd_a_wr_b_sim;
wire coll_rd_a_wr_b;
//assign coll_win_wr_clk_a_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_wr_en_a : coll_win_wr_clk_a_ind_min;
//assign coll_win_wr_clk_b_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_wr_en_b : coll_win_wr_clk_b_ind_min;
//assign coll_win_rd_clk_a_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_rd_en_a : coll_win_rd_clk_a_ind_min;
//assign coll_win_rd_clk_b_min = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ?
// mem_rd_en_b : coll_win_rd_clk_b_ind_min;
assign coll_win_wr_clk_a_min = coll_win_wr_clk_a_ind_min;
assign coll_win_wr_clk_b_min = coll_win_wr_clk_b_ind_min;
assign coll_win_rd_clk_a_min = coll_win_rd_clk_a_ind_min;
assign coll_win_rd_clk_b_min = coll_win_rd_clk_b_ind_min;
assign mem_wr_clk_a_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_wr_clk_a;
assign mem_wr_clk_b_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_wr_clk_b;
assign mem_rd_clk_a_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_rd_clk_a;
assign mem_rd_clk_b_coll = (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_NONE) ?
1'b0 : mem_rd_clk_b;
assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min;
assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min;
assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max;
assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min;
assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min;
assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max;
assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min;
assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
always @(posedge mem_wr_clk_a_coll) begin
if (mem_wr_en_a === 1'b1) begin
coll_win_wr_clk_a_ind_min <= 1'b1;
coll_win_wr_clk_a_max <= #50 1'b1;
coll_win_wr_clk_a_ind_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_sim) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_wr_b) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge mem_wr_clk_b_coll) begin
if (mem_wr_en_b === 1'b1) begin
coll_win_wr_clk_b_ind_min <= 1'b1;
coll_win_wr_clk_b_max <= #50 1'b1;
coll_win_wr_clk_b_ind_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_b_wr_a) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge mem_rd_clk_a_coll) begin
if (mem_rd_en_a === 1'b1) begin
coll_win_rd_clk_a_ind_min <= 1'b1;
coll_win_rd_clk_a_max <= #50 1'b1;
coll_win_rd_clk_a_ind_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_a_wr_b_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_a_wr_b) begin
if (~wr_b_data_matches_rd_a_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge mem_rd_clk_b_coll) begin
if (mem_rd_en_b === 1'b1) begin
coll_win_rd_clk_b_ind_min <= 1'b1;
coll_win_rd_clk_b_max <= #50 1'b1;
coll_win_rd_clk_b_ind_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_b_wr_a_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h).", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_b_wr_a) begin
if (~wr_a_data_matches_rd_b_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted.", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Memory Collision Error on %s : instance %m at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
// output register
assign mem_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? {CASDINB_in, CASDINA_in} : mem_a_out;
assign memp_a_reg_mux = (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) ? {CASDINPB_in, CASDINPA_in} : memp_a_out;
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= mem_a_reg_mux;
memp_a_reg <= memp_a_reg_mux;
end
end
assign mem_b_reg_mux = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXB_reg) ? CASDINB_in : mem_b_out;
assign memp_b_reg_mux = (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXB_reg) ? CASDINPB_in : memp_b_out;
always @ (posedge mem_rd_clk_b or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_b_reg, mem_b_reg} <= INIT_B_int;
end
else if (RSTREG_B_int) begin
{memp_b_reg, mem_b_reg} <= SRVAL_B_int;
end
else if (REGCE_B_int) begin
mem_b_reg <= mem_b_reg_mux;
memp_b_reg <= memp_b_reg_mux;
end
end
// bit err reg
always @ (posedge mem_rd_clk_a or glblGSR) begin
if (glblGSR || RSTREG_A_int) begin
dbit_reg <= 1'b0;
sbit_reg <= 1'b0;
r_a_ecc_reg <= 9'h0;
end
else if (REGCE_A_int) begin
dbit_reg <= dbit_lat;
sbit_reg <= sbit_lat;
r_a_ecc_reg <= r_a_ecc_lat;
end
end
// ecc pipe register
always @ (posedge mem_rd_clk_a or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_pipe, mem_a_pipe} <= INIT_A_int;
dbit_pipe <= 1'b0;
sbit_pipe <= 1'b0;
r_a_ecc_pipe <= 9'b0;
end
else if (RSTREG_A_int) begin
{memp_a_pipe, mem_a_pipe} <= SRVAL_A_int;
dbit_pipe <= 1'b0;
sbit_pipe <= 1'b0;
r_a_ecc_pipe <= 9'b0;
end
else if (RDEN_ecc) begin
mem_a_pipe <= mem_a_ecc_cor;
memp_a_pipe <= memp_a_ecc_cor;
dbit_pipe <= dbit_int;
sbit_pipe <= sbit_int;
r_a_ecc_pipe <= r_a_ecc_int;
end
end
// read engine
always @ (posedge mem_wr_clk_a) begin
if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && mem_rd_en_a) begin
mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a;
end
end
always @ (posedge mem_wr_clk_b) begin
if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b) begin
mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b;
end
end
always @ (wr_a_event or INIT_MEM) begin
if (~coll_rd_a_wr_b && ~coll_rd_a_wr_b_sim
&& ~coll_wr_b_rd_a && ~coll_wr_b_rd_a_sim) begin
for (raa=0;raa> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_a) begin
$display("DRC Error : READ on port A attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (ra=0;ra> ra;
if (ra> (D_WIDTH+ra);
end
end
end
else if (rd_a_wr_b_coll) begin
if (~wr_b_data_matches_rd_a_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (ra=0;ra> rb;
if (rb> (D_WIDTH/2+rb);
end
end
end
else if ((SLEEP_in || SLEEP_int) && mem_rd_en_b) begin
$display("DRC Error : READ on port B attempted while in SLEEP mode on %s instance %m.", MODULE_NAME);
for (rb=0;rb> rb;
if (rb> (D_WIDTH/2+rb);
end
end
end
else if (rd_b_wr_a_coll) begin
if (~wr_a_data_matches_rd_b_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (rb=0;rb>(max_rd_loops-rd_loops_a);
assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b);
assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a);
assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b);
assign wr_a_rd_b_addr_coll = ~sdp_mode && ((wr_addr_a & rd_addr_b_mask) == (rd_addr_b & wr_addr_a_mask)) && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b;
assign wr_addr_coll = ~sdp_mode && ((wr_addr_a & wr_addr_b_mask) == (wr_addr_b & wr_addr_a_mask)) && mem_wr_en_b && mem_wr_en_a;
assign wr_b_rd_a_addr_coll = ((wr_addr_b & rd_addr_a_mask) == (rd_addr_a & wr_addr_b_mask)) && mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a;
assign mem_we_a = {{D_WIDTH/2{1'b0}},{8{WEA_in[3]}},{8{WEA_in[2]}},{8{WEA_in[1]}},{8{WEA_in[0]}}} & ({D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a));
assign mem_we_b = {{8{WEBWE_in[7]}},{8{WEBWE_in[6]}},{8{WEBWE_in[5]}},{8{WEBWE_in[4]}},
{8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}} & ({D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b));
assign memp_we_a = (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) ? {4'b0,WEA_in} : 8'b0;
assign memp_we_b = (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) ? WEBWE_in : 8'b0;
// eccparity is flopped
assign synd_wr = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ?
fn_ecc(encode, {DINBDIN_in, DINADIN_in}, {DINPBDINP_in, DINPADINP_in}) : 8'b0;
assign synd_rd = (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) ?
fn_ecc(decode, mem_rd_a, memp_rd_a) : 8'b0;
assign synd_ecc = (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) ?
synd_rd ^ memp_rd_a : 8'b0;
assign sbit_int = (|synd_ecc && synd_ecc[7]);
assign dbit_int = (|synd_ecc && ~synd_ecc[7]);
assign r_a_ecc_int = rd_addr_a[ADDR_WIDTH-1:ADDR_WIDTH-9];
// make sure new read has happend before checking for error.
// INIT/SRVAL values shouldn't cause error.
always @(posedge mem_rd_clk_a) begin
if (mem_rd_en_a && mem_rst_a) begin
sbit_lat <= 1'b0;
dbit_lat <= 1'b0;
error_bit <= 7'b0;
r_a_ecc_lat <= 9'b0;
end
else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin
sbit_lat <= sbit_ecc;
dbit_lat <= dbit_ecc;
error_bit <= synd_ecc[6:0];
r_a_ecc_lat <= r_a_ecc_ecc;
end
end
assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ?
fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) :
{memp_rd_a, mem_rd_a};
assign wrclk_ecc_out = mem_wr_clk_b && (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE);
always @ (posedge wrclk_ecc_out or glblGSR) begin
if(glblGSR)
eccparity_reg <= 8'h00;
else if (ENBWREN_in)
eccparity_reg <= synd_wr;
end
specify
( CASDINA *> CASDOUTA) = (0:0:0, 0:0:0);
( CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0);
( CASDINB *> CASDOUTB) = (0:0:0, 0:0:0);
( CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0);
( CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0);
( CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0);
( CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
( CASINDBITERR *> CASOUTDBITERR) = (0:0:0, 0:0:0);
( CASINDBITERR *> DBITERR) = (0:0:0, 0:0:0);
( CASINSBITERR *> CASOUTSBITERR) = (0:0:0, 0:0:0);
( CASINSBITERR *> SBITERR) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTA) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTB) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTPA) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASOUTDBITERR) = (0:0:0, 0:0:0);
( CLKARDCLK *> CASOUTSBITERR) = (0:0:0, 0:0:0);
( CLKARDCLK *> DBITERR) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTADOUT) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTPADOUTP) = (0:0:0, 0:0:0);
( CLKARDCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
( CLKARDCLK *> RDADDRECC) = (0:0:0, 0:0:0);
( CLKARDCLK *> SBITERR) = (0:0:0, 0:0:0);
( CLKBWRCLK *> CASDOUTB) = (0:0:0, 0:0:0);
( CLKBWRCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
( CLKBWRCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
( CLKBWRCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
( CLKBWRCLK *> ECCPARITY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge CLKARDCLK, 0:0:0, notifier);
$period (negedge CLKBWRCLK, 0:0:0, notifier);
$period (posedge CLKARDCLK, 0:0:0, notifier);
$period (posedge CLKBWRCLK, 0:0:0, notifier);
$setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMD32.v 0000664 0000000 0000000 00000012157 12327044266 0022320 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMD32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMD32 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output O,
input CLK,
input I,
input RADR0,
input RADR1,
input RADR2,
input RADR3,
input RADR4,
input WADR0,
input WADR1,
input WADR2,
input WADR3,
input WADR4,
input WE
);
reg [31:0] mem;
wire [4:0] WADR_dly;
wire [4:0] radr;
wire I_dly, CLK_dly, WE_dly;
wire CLK_in;
localparam MODULE_NAME = "RAMD32";
initial begin
mem[31:0] = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
assign radr[4:0] = {RADR4, RADR3, RADR2, RADR1, RADR0};
always @(posedge CLK_in)
if (WE_dly == 1'b1)
mem[WADR_dly] <= #100 I_dly;
assign O = mem[radr];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[WADR_dly] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign WADR_dly = {WADR4, WADR3, WADR2, WADR1, WADR0};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
specify
`ifdef XIL_TIMING
(CLK => O) = (0:0:0, 0:0:0);
(RADR0 => O) = (0:0:0, 0:0:0);
(RADR1 => O) = (0:0:0, 0:0:0);
(RADR2 => O) = (0:0:0, 0:0:0);
(RADR3 => O) = (0:0:0, 0:0:0);
(RADR4 => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (posedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (posedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (posedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (negedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (negedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (negedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (negedge CLK &&& WE, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMD64E.v 0000664 0000000 0000000 00000015345 12327044266 0022434 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMD64E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/21/12 - CR649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7.
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMD64E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [1:0] RAM_ADDRESS_MASK = 2'b00,
parameter [1:0] RAM_ADDRESS_SPACE = 2'b00
)(
output O,
input CLK,
input I,
input RADR0,
input RADR1,
input RADR2,
input RADR3,
input RADR4,
input RADR5,
input WADR0,
input WADR1,
input WADR2,
input WADR3,
input WADR4,
input WADR5,
input WADR6,
input WADR7,
input WE
);
reg [63:0] mem;
wire [5:0] ADR_dly;
wire [5:0] radr;
wire CLK_dly, I_dly;
wire WADR6_dly;
wire WADR7_dly;
wire WE_dly;
wire CLK_in;
localparam MODULE_NAME = "RAMD64E";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
assign radr[5:0] = {RADR5, RADR4, RADR3, RADR2, RADR1, RADR0};
always @(posedge CLK_in)
if (WE_dly == 1'b1 &&
(RAM_ADDRESS_MASK[1] || WADR7_dly == RAM_ADDRESS_SPACE[1]) &&
(RAM_ADDRESS_MASK[0] || WADR6_dly == RAM_ADDRESS_SPACE[0]) )
mem[ADR_dly] <= #100 I_dly;
assign O = mem[radr];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_dly] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {WADR5, WADR4, WADR3, WADR2, WADR1, WADR0};
assign WADR6_dly = WADR6;
assign WADR7_dly = WADR7;
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
`ifdef XIL_TIMING
specify
(CLK => O) = (0:0:0, 0:0:0);
(RADR0 => O) = (0:0:0, 0:0:0);
(RADR1 => O) = (0:0:0, 0:0:0);
(RADR2 => O) = (0:0:0, 0:0:0);
(RADR3 => O) = (0:0:0, 0:0:0);
(RADR4 => O) = (0:0:0, 0:0:0);
(RADR5 => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, negedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (posedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (posedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (posedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, negedge WADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (negedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (negedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (negedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (negedge CLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMS32.v 0000664 0000000 0000000 00000011630 12327044266 0022332 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMS32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMS32 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output O,
input ADR0,
input ADR1,
input ADR2,
input ADR3,
input ADR4,
input CLK,
input I,
input WE
);
reg [31:0] mem;
wire [4:0] ADR_dly;
wire I_dly, CLK_dly, WE_dly;
wire CLK_in;
localparam MODULE_NAME = "RAMS32";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
always @(posedge CLK_in)
if (WE_dly == 1'b1)
mem[ADR_dly] <= #100 I_dly;
assign O = mem[ADR_dly];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_dly] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {ADR4, ADR3, ADR2, ADR1, ADR0};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
specify
`ifdef XIL_TIMING
(CLK => O) = (0:0:0, 0:0:0);
(ADR0 => O) = (0:0:0, 0:0:0);
(ADR1 => O) = (0:0:0, 0:0:0);
(ADR2 => O) = (0:0:0, 0:0:0);
(ADR3 => O) = (0:0:0, 0:0:0);
(ADR4 => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (negedge CLK &&& WE, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMS64E.v 0000664 0000000 0000000 00000015024 12327044266 0022445 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Single Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMS64E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/21/12 - CR649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMS64E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [1:0] RAM_ADDRESS_MASK = 2'b00,
parameter [1:0] RAM_ADDRESS_SPACE = 2'b00
)(
output O,
input ADR0,
input ADR1,
input ADR2,
input ADR3,
input ADR4,
input ADR5,
input CLK,
input I,
input WADR6,
input WADR7,
input WE
);
reg [63:0] mem;
wire [5:0] ADR_dly;
wire CLK_dly, I_dly;
wire WADR6_dly;
wire WADR7_dly;
wire WE_dly;
wire CLK_in;
localparam MODULE_NAME = "RAMS64E";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
always @(posedge CLK_in)
if (WE_dly == 1'b1 &&
(RAM_ADDRESS_MASK[1] || WADR7_dly == RAM_ADDRESS_SPACE[1]) &&
(RAM_ADDRESS_MASK[0] || WADR6_dly == RAM_ADDRESS_SPACE[0]) )
mem[ADR_dly] <= #100 I_dly;
assign O = mem[ADR_dly];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_dly] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {ADR5, ADR4, ADR3, ADR2, ADR1, ADR0};
assign WADR6_dly = WADR6;
assign WADR7_dly = WADR7;
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
`ifdef XIL_TIMING
specify
(CLK => O) = (0:0:0, 0:0:0);
(ADR0 => O) = (0:0:0, 0:0:0);
(ADR1 => O) = (0:0:0, 0:0:0);
(ADR2 => O) = (0:0:0, 0:0:0);
(ADR3 => O) = (0:0:0, 0:0:0);
(ADR4 => O) = (0:0:0, 0:0:0);
(ADR5 => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (posedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (posedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (posedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (negedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR6_dly);
$setuphold (negedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (negedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR7_dly);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (negedge CLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RAMS64E1.v 0000664 0000000 0000000 00000015512 12327044266 0022530 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.6
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Single Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMS64E1.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/16/13 - Initial from RAMS64E
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMS64E1 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [2:0] RAM_ADDRESS_MASK = 3'b000,
parameter [2:0] RAM_ADDRESS_SPACE = 3'b000
)(
output O,
input ADR0,
input ADR1,
input ADR2,
input ADR3,
input ADR4,
input ADR5,
input CLK,
input I,
input WADR6,
input WADR7,
input WADR8,
input WE
);
reg [63:0] mem;
wire [5:0] ADR_dly, ADR_in;
wire CLK_dly, I_dly;
wire CLK_in, I_in;
wire [2:0] WADR_dly, WADR_in;
wire WE_dly, WE_in;
localparam MODULE_NAME = "RAMS64E1";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
always @(posedge CLK_in)
if (WE_in == 1'b1 &&
(RAM_ADDRESS_MASK[2] || WADR_in[2] == RAM_ADDRESS_SPACE[2]) &&
(RAM_ADDRESS_MASK[1] || WADR_in[1] == RAM_ADDRESS_SPACE[1]) &&
(RAM_ADDRESS_MASK[0] || WADR_in[0] == RAM_ADDRESS_SPACE[0]) )
mem[ADR_in] <= #100 I_in;
assign O = mem[ADR_in];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {ADR5, ADR4, ADR3, ADR2, ADR1, ADR0};
assign WADR_dly = {WADR8, WADR7, WADR6};
assign WE_dly = WE;
`endif
assign CLK_in = CLK_dly ^ IS_CLK_INVERTED;
assign I_in = I_dly;
assign ADR_in = ADR_dly;
assign WADR_in = WADR_dly;
assign WE_in = WE_dly;
`ifdef XIL_TIMING
specify
(CLK => O) = (0:0:0, 0:0:0);
(ADR0 => O) = (0:0:0, 0:0:0);
(ADR1 => O) = (0:0:0, 0:0:0);
(ADR2 => O) = (0:0:0, 0:0:0);
(ADR3 => O) = (0:0:0, 0:0:0);
(ADR4 => O) = (0:0:0, 0:0:0);
(ADR5 => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, posedge WADR8 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, negedge WADR8 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, posedge WADR8 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, negedge WADR8 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$period (negedge CLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RIU_OR.v 0000664 0000000 0000000 00000005572 12327044266 0022472 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : RIU_OR.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RIU_OR
`ifdef XIL_TIMING //Simprim adding LOC only
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [15:0] RIU_RD_DATA,
output RIU_RD_VALID,
input [15:0] RIU_RD_DATA_LOW,
input [15:0] RIU_RD_DATA_UPP,
input RIU_RD_VALID_LOW,
input RIU_RD_VALID_UPP
);
// define constants
localparam MODULE_NAME = "RIU_OR";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire RIU_RD_VALID_out;
wire [15:0] RIU_RD_DATA_out;
wire RIU_RD_VALID_delay;
wire [15:0] RIU_RD_DATA_delay;
wire RIU_RD_VALID_LOW_in;
wire RIU_RD_VALID_UPP_in;
wire [15:0] RIU_RD_DATA_LOW_in;
wire [15:0] RIU_RD_DATA_UPP_in;
wire RIU_RD_VALID_LOW_delay;
wire RIU_RD_VALID_UPP_delay;
wire [15:0] RIU_RD_DATA_LOW_delay;
wire [15:0] RIU_RD_DATA_UPP_delay;
// input output assignments
assign #(out_delay) RIU_RD_DATA = RIU_RD_DATA_delay;
assign #(out_delay) RIU_RD_VALID = RIU_RD_VALID_delay;
assign #(in_delay) RIU_RD_DATA_LOW_delay = RIU_RD_DATA_LOW;
assign #(in_delay) RIU_RD_DATA_UPP_delay = RIU_RD_DATA_UPP;
assign #(in_delay) RIU_RD_VALID_LOW_delay = RIU_RD_VALID_LOW;
assign #(in_delay) RIU_RD_VALID_UPP_delay = RIU_RD_VALID_UPP;
assign RIU_RD_DATA_delay = RIU_RD_DATA_out;
assign RIU_RD_VALID_delay = RIU_RD_VALID_out;
assign RIU_RD_DATA_LOW_in = RIU_RD_DATA_LOW_delay;
assign RIU_RD_DATA_UPP_in = RIU_RD_DATA_UPP_delay;
assign RIU_RD_VALID_LOW_in = RIU_RD_VALID_LOW_delay;
assign RIU_RD_VALID_UPP_in = RIU_RD_VALID_UPP_delay;
assign RIU_RD_DATA_out = RIU_RD_DATA_UPP_in | RIU_RD_DATA_LOW_in;
assign RIU_RD_VALID_out = RIU_RD_VALID_UPP_in | RIU_RD_VALID_LOW_in;
specify
(RIU_RD_DATA_LOW *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_DATA_UPP *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_VALID_LOW => RIU_RD_VALID) = (0:0:0, 0:0:0);
(RIU_RD_VALID_UPP => RIU_RD_VALID) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RXTX_BITSLICE.v 0000664 0000000 0000000 00000100757 12327044266 0023517 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : RXTX_BITSLICE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RXTX_BITSLICE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_RX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_INVERTED = 1'b0,
parameter [0:0] IS_TX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_INVERTED = 1'b0,
parameter PRE_EMPHASIS = "OFF",
parameter RX_DATA_TYPE = "NONE",
parameter integer RX_DATA_WIDTH = 8,
parameter RX_DELAY_FORMAT = "TIME",
parameter RX_DELAY_TYPE = "FIXED",
parameter integer RX_DELAY_VALUE = 0,
parameter real RX_REFCLK_FREQUENCY = 300.0,
parameter RX_UPDATE_MODE = "ASYNC",
parameter TBYTE_CTL = "TBYTE_IN",
parameter integer TX_DATA_WIDTH = 8,
parameter TX_DELAY_FORMAT = "TIME",
parameter TX_DELAY_TYPE = "FIXED",
parameter integer TX_DELAY_VALUE = 0,
parameter TX_OUTPUT_PHASE_90 = "FALSE",
parameter real TX_REFCLK_FREQUENCY = 300.0,
parameter TX_UPDATE_MODE = "ASYNC"
)(
output FIFO_EMPTY,
output FIFO_WRCLK_OUT,
output O,
output [7:0] Q,
output [34:0] RX_BIT_CTRL_OUT,
output [8:0] RX_CNTVALUEOUT,
output [29:0] TX_BIT_CTRL_OUT,
output [8:0] TX_CNTVALUEOUT,
output T_OUT,
input [7:0] D,
input DATAIN,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input [23:0] RX_BIT_CTRL_IN,
input RX_CE,
input RX_CLK,
input [8:0] RX_CNTVALUEIN,
input RX_EN_VTC,
input RX_INC,
input RX_LOAD,
input RX_RST,
input RX_RST_DLY,
input T,
input TBYTE_IN,
input [26:0] TX_BIT_CTRL_IN,
input TX_CE,
input TX_CLK,
input [8:0] TX_CNTVALUEIN,
input TX_EN_VTC,
input TX_INC,
input TX_LOAD,
input TX_RST,
input TX_RST_DLY
);
// define constants
localparam MODULE_NAME = "RXTX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_RX_CLK_INVERTED_REG = IS_RX_CLK_INVERTED;
localparam [0:0] IS_RX_RST_DLY_INVERTED_REG = IS_RX_RST_DLY_INVERTED;
localparam [0:0] IS_RX_RST_INVERTED_REG = IS_RX_RST_INVERTED;
localparam [0:0] IS_TX_CLK_INVERTED_REG = IS_TX_CLK_INVERTED;
localparam [0:0] IS_TX_RST_DLY_INVERTED_REG = IS_TX_RST_DLY_INVERTED;
localparam [0:0] IS_TX_RST_INVERTED_REG = IS_TX_RST_INVERTED;
localparam [24:1] PRE_EMPHASIS_REG = PRE_EMPHASIS;
localparam [112:1] RX_DATA_TYPE_REG = RX_DATA_TYPE;
localparam [3:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [40:1] RX_DELAY_FORMAT_REG = RX_DELAY_FORMAT;
localparam [64:1] RX_DELAY_TYPE_REG = RX_DELAY_TYPE;
localparam [10:0] RX_DELAY_VALUE_REG = RX_DELAY_VALUE;
localparam real RX_REFCLK_FREQUENCY_REG = RX_REFCLK_FREQUENCY;
localparam [48:1] RX_UPDATE_MODE_REG = RX_UPDATE_MODE;
localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL;
localparam [3:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [40:1] TX_DELAY_FORMAT_REG = TX_DELAY_FORMAT;
localparam [64:1] TX_DELAY_TYPE_REG = TX_DELAY_TYPE;
localparam [10:0] TX_DELAY_VALUE_REG = TX_DELAY_VALUE;
localparam [40:1] TX_OUTPUT_PHASE_90_REG = TX_OUTPUT_PHASE_90;
localparam real TX_REFCLK_FREQUENCY_REG = TX_REFCLK_FREQUENCY;
localparam [48:1] TX_UPDATE_MODE_REG = TX_UPDATE_MODE;
`endif
localparam [40:1] DDR_DIS_DQS_REG = "TRUE";
localparam [40:1] LOOPBACK_REG = "FALSE";
localparam [0:0] RECALIBRATE_EN_REG = 1'b0;
localparam [0:0] RX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] RX_FDLY_REG = 3'b000;
localparam [2:0] RX_FDLY_RES_REG = 3'b000;
reg [63:0] RX_REFCLK_FREQUENCY_INT = RX_REFCLK_FREQUENCY * 1000;
localparam [40:1] TXRX_LOOPBACK_REG = "FALSE";
localparam [0:0] TX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] TX_FDLY_REG = 3'b000;
localparam [2:0] TX_FDLY_RES_REG = 3'b000;
reg [63:0] TX_REFCLK_FREQUENCY_INT = TX_REFCLK_FREQUENCY * 1000;
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
localparam [8*5:1] RX_Q4_ROUTETHRU_REG = "FALSE";
localparam [8*5:1] RX_Q5_ROUTETHRU_REG = "FALSE";
localparam [8*5:1] TX_Q_ROUTETHRU_REG = "FALSE";
localparam [8*5:1] TX_T_OUT_ROUTETHRU_REG = "FALSE";
wire IS_RX_CLK_INVERTED_BIN;
wire IS_RX_RST_DLY_INVERTED_BIN;
wire IS_RX_RST_INVERTED_BIN;
wire IS_TX_CLK_INVERTED_BIN;
wire IS_TX_RST_DLY_INVERTED_BIN;
wire IS_TX_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RXTX_BITSLICE_dr.v"
`endif
wire FIFO_EMPTY_out;
wire FIFO_WRCLK_OUT_out;
wire O_out;
wire TX2RX_CASC_OUT_out;
wire T_OUT_out;
wire [29:0] TX_BIT_CTRL_OUT_out;
wire [34:0] RX_BIT_CTRL_OUT_out;
wire [7:0] Q_out;
wire [8:0] RX_CNTVALUEOUT_out;
wire [8:0] TX_CNTVALUEOUT_out;
wire FIFO_EMPTY_delay;
wire FIFO_WRCLK_OUT_delay;
wire O_delay;
wire T_OUT_delay;
wire [29:0] TX_BIT_CTRL_OUT_delay;
wire [34:0] RX_BIT_CTRL_OUT_delay;
wire [7:0] Q_delay;
wire [8:0] RX_CNTVALUEOUT_delay;
wire [8:0] TX_CNTVALUEOUT_delay;
wire DATAIN_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire OFD_CE_in;
wire RX2TX_CASC_RETURN_IN_in;
wire RX_CE_in;
wire RX_CLKDIV_in;
wire RX_CLK_C_B_in;
wire RX_CLK_C_in;
wire RX_CLK_in;
wire RX_DATAIN1_in;
wire RX_EN_VTC_in;
wire RX_INC_in;
wire RX_LOAD_in;
wire RX_RST_DLY_in;
wire RX_RST_in;
wire TBYTE_IN_in;
wire TX2RX_CASC_IN_in;
wire TX_CE_in;
wire TX_CLK_in;
wire TX_EN_VTC_in;
wire TX_INC_in;
wire TX_LOAD_in;
wire TX_OCLKDIV_in;
wire TX_OCLK_in;
wire TX_RST_DLY_in;
wire TX_RST_in;
wire T_in;
wire [23:0] RX_BIT_CTRL_IN_in;
wire [26:0] TX_BIT_CTRL_IN_in;
wire [7:0] D_in;
wire [8:0] RX_CNTVALUEIN_in;
wire [8:0] TX_CNTVALUEIN_in;
wire DATAIN_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire RX_CE_delay;
wire RX_CLK_delay;
wire RX_EN_VTC_delay;
wire RX_INC_delay;
wire RX_LOAD_delay;
wire RX_RST_DLY_delay;
wire RX_RST_delay;
wire TBYTE_IN_delay;
wire TX_CE_delay;
wire TX_CLK_delay;
wire TX_EN_VTC_delay;
wire TX_INC_delay;
wire TX_LOAD_delay;
wire TX_RST_DLY_delay;
wire TX_RST_delay;
wire T_delay;
wire [23:0] RX_BIT_CTRL_IN_delay;
wire [26:0] TX_BIT_CTRL_IN_delay;
wire [7:0] D_delay;
wire [8:0] RX_CNTVALUEIN_delay;
wire [8:0] TX_CNTVALUEIN_delay;
wire IDELAY_DATAIN0_out;
wire IDELAY_DATAOUT_out;
wire OSERDES_Q_out;
wire BITSLICE_WRITE_Q_out;
wire ODELAY_DATAIN0_out;
wire ODELAY_DATAOUT_out;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) Q = Q_delay;
assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay;
assign #(out_delay) RX_CNTVALUEOUT = RX_CNTVALUEOUT_delay;
assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay;
assign #(out_delay) TX_CNTVALUEOUT = TX_CNTVALUEOUT_delay;
assign #(out_delay) T_OUT = T_OUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(inclk_delay) RX_CLK_delay = RX_CLK;
assign #(inclk_delay) TX_CLK_delay = TX_CLK;
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) D_delay = D;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN;
assign #(in_delay) RX_CE_delay = RX_CE;
assign #(in_delay) RX_CNTVALUEIN_delay = RX_CNTVALUEIN;
assign #(in_delay) RX_INC_delay = RX_INC;
assign #(in_delay) RX_LOAD_delay = RX_LOAD;
assign #(in_delay) RX_RST_DLY_delay = RX_RST_DLY;
assign #(in_delay) RX_RST_delay = RX_RST;
assign #(in_delay) TX_BIT_CTRL_IN_delay = TX_BIT_CTRL_IN;
assign #(in_delay) TX_CE_delay = TX_CE;
assign #(in_delay) TX_CNTVALUEIN_delay = TX_CNTVALUEIN;
assign #(in_delay) TX_INC_delay = TX_INC;
assign #(in_delay) TX_LOAD_delay = TX_LOAD;
assign #(in_delay) TX_RST_DLY_delay = TX_RST_DLY;
assign #(in_delay) TX_RST_delay = TX_RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) RX_EN_VTC_delay = RX_EN_VTC;
assign #(in_delay) TBYTE_IN_delay = TBYTE_IN;
assign #(in_delay) TX_EN_VTC_delay = TX_EN_VTC;
assign #(in_delay) T_delay = T;
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out;
assign O_delay = O_out;
assign Q_delay = Q_out;
assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out;
assign RX_CNTVALUEOUT_delay = RX_CNTVALUEOUT_out;
assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out;
assign TX_CNTVALUEOUT_delay = TX_CNTVALUEOUT_out;
assign T_OUT_delay = T_OUT_out;
assign DATAIN_in = DATAIN_delay;
assign D_in = D_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay;
assign RX_CE_in = RX_CE_delay;
assign RX_CLK_in = RX_CLK_delay ^ IS_RX_CLK_INVERTED_BIN;
assign RX_CNTVALUEIN_in = RX_CNTVALUEIN_delay;
assign RX_EN_VTC_in = RX_EN_VTC_delay;
assign RX_INC_in = RX_INC_delay;
assign RX_LOAD_in = RX_LOAD_delay;
assign RX_RST_DLY_in = RX_RST_DLY_delay ^ IS_RX_RST_DLY_INVERTED_BIN;
assign RX_RST_in = RX_RST_delay ^ IS_RX_RST_INVERTED_BIN;
assign TBYTE_IN_in = TBYTE_IN_delay;
assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay;
assign TX_CE_in = TX_CE_delay;
assign TX_CLK_in = TX_CLK_delay ^ IS_TX_CLK_INVERTED_BIN;
assign TX_CNTVALUEIN_in = TX_CNTVALUEIN_delay;
assign TX_EN_VTC_in = TX_EN_VTC_delay;
assign TX_INC_in = TX_INC_delay;
assign TX_LOAD_in = TX_LOAD_delay;
assign TX_RST_DLY_in = TX_RST_DLY_delay ^ IS_TX_RST_DLY_INVERTED_BIN;
assign TX_RST_in = TX_RST_delay ^ IS_TX_RST_INVERTED_BIN;
assign T_in = T_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_RX_CLK_INVERTED_BIN = IS_RX_CLK_INVERTED_REG;
assign IS_RX_RST_DLY_INVERTED_BIN = IS_RX_RST_DLY_INVERTED_REG;
assign IS_RX_RST_INVERTED_BIN = IS_RX_RST_INVERTED_REG;
assign IS_TX_CLK_INVERTED_BIN = IS_TX_CLK_INVERTED_REG;
assign IS_TX_RST_DLY_INVERTED_BIN = IS_TX_RST_DLY_INVERTED_REG;
assign IS_TX_RST_INVERTED_BIN = IS_TX_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIFO_SYNC_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((INIT_REG < 1'b0) || (INIT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((IS_RX_CLK_INVERTED_REG < 1'b0) || (IS_RX_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RX_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RX_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RX_RST_DLY_INVERTED_REG < 1'b0) || (IS_RX_RST_DLY_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RX_RST_DLY_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RX_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RX_RST_INVERTED_REG < 1'b0) || (IS_RX_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RX_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RX_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_TX_CLK_INVERTED_REG < 1'b0) || (IS_TX_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_TX_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_TX_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_TX_RST_DLY_INVERTED_REG < 1'b0) || (IS_TX_RST_DLY_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_TX_RST_DLY_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_TX_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_TX_RST_INVERTED_REG < 1'b0) || (IS_TX_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_TX_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_TX_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((PRE_EMPHASIS_REG != "OFF") &&
(PRE_EMPHASIS_REG != "ON")) begin
$display("Attribute Syntax Error : The attribute PRE_EMPHASIS on %s instance %m is set to %s. Legal values for this attribute are OFF or ON.", MODULE_NAME, PRE_EMPHASIS_REG);
attr_err = 1'b1;
end
if ((RX_DATA_TYPE_REG != "NONE") &&
(RX_DATA_TYPE_REG != "CLOCK") &&
(RX_DATA_TYPE_REG != "DATA") &&
(RX_DATA_TYPE_REG != "DATA_AND_CLOCK")) begin
$display("Attribute Syntax Error : The attribute RX_DATA_TYPE on %s instance %m is set to %s. Legal values for this attribute are NONE, CLOCK, DATA or DATA_AND_CLOCK.", MODULE_NAME, RX_DATA_TYPE_REG);
attr_err = 1'b1;
end
if ((RX_DATA_WIDTH_REG != 8) &&
(RX_DATA_WIDTH_REG != 2) &&
(RX_DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute RX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, RX_DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((RX_DELAY_FORMAT_REG != "TIME") &&
(RX_DELAY_FORMAT_REG != "COUNT")) begin
$display("Attribute Syntax Error : The attribute RX_DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, RX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((RX_DELAY_TYPE_REG != "FIXED") &&
(RX_DELAY_TYPE_REG != "VARIABLE") &&
(RX_DELAY_TYPE_REG != "VAR_LOAD")) begin
$display("Attribute Syntax Error : The attribute RX_DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, RX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute RX_DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, RX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((RX_UPDATE_MODE_REG != "ASYNC") &&
(RX_UPDATE_MODE_REG != "MANUAL") &&
(RX_UPDATE_MODE_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute RX_UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, RX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((TBYTE_CTL_REG != "TBYTE_IN") &&
(TBYTE_CTL_REG != "T")) begin
$display("Attribute Syntax Error : The attribute TBYTE_CTL on %s instance %m is set to %s. Legal values for this attribute are TBYTE_IN or T.", MODULE_NAME, TBYTE_CTL_REG);
attr_err = 1'b1;
end
if ((TX_DATA_WIDTH_REG != 8) &&
(TX_DATA_WIDTH_REG != 2) &&
(TX_DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute TX_DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, TX_DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((TX_DELAY_FORMAT_REG != "TIME") &&
(TX_DELAY_FORMAT_REG != "COUNT")) begin
$display("Attribute Syntax Error : The attribute TX_DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, TX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((TX_DELAY_TYPE_REG != "FIXED") &&
(TX_DELAY_TYPE_REG != "VARIABLE") &&
(TX_DELAY_TYPE_REG != "VAR_LOAD")) begin
$display("Attribute Syntax Error : The attribute TX_DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, TX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute TX_DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, TX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((TX_OUTPUT_PHASE_90_REG != "FALSE") &&
(TX_OUTPUT_PHASE_90_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute TX_OUTPUT_PHASE_90 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, TX_OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((TX_UPDATE_MODE_REG != "ASYNC") &&
(TX_UPDATE_MODE_REG != "MANUAL") &&
(TX_UPDATE_MODE_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute TX_UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, TX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if (RX_REFCLK_FREQUENCY_REG >= 300.0 && RX_REFCLK_FREQUENCY_REG <= 1333.0) begin // float
RX_REFCLK_FREQUENCY_INT <= RX_REFCLK_FREQUENCY_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute RX_REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, RX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (TX_REFCLK_FREQUENCY_REG >= 300.0 && TX_REFCLK_FREQUENCY_REG <= 1333.0) begin // float
TX_REFCLK_FREQUENCY_INT <= TX_REFCLK_FREQUENCY_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute TX_REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, TX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign RX_CLKDIV_in = 1'b1; // tie off
assign RX_CLK_C_B_in = 1'b1; // tie off
assign RX_CLK_C_in = 1'b1; // tie off
assign TX_OCLKDIV_in = 1'b1; // tie off
assign TX_OCLK_in = 1'b1; // tie off
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX2TX_CASC_RETURN_IN_in = 1'b1; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign TX2RX_CASC_IN_in = 1'b1; // tie off
SIP_RXTX_BITSLICE SIP_RXTX_BITSLICE_INST (
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.INIT (INIT_REG),
.LOOPBACK (LOOPBACK_REG),
.PRE_EMPHASIS (PRE_EMPHASIS_REG),
.RECALIBRATE_EN (RECALIBRATE_EN_REG),
.RX_DATA_TYPE (RX_DATA_TYPE_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG),
.RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG),
.RX_DELAY_TYPE (RX_DELAY_TYPE_REG),
.RX_DELAY_VALUE (RX_DELAY_VALUE_REG),
.RX_FDLY (RX_FDLY_REG),
.RX_FDLY_RES (RX_FDLY_RES_REG),
.RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_INT),
.RX_UPDATE_MODE (RX_UPDATE_MODE_REG),
.TBYTE_CTL (TBYTE_CTL_REG),
.TXRX_LOOPBACK (TXRX_LOOPBACK_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG),
.TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG),
.TX_DELAY_TYPE (TX_DELAY_TYPE_REG),
.TX_DELAY_VALUE (TX_DELAY_VALUE_REG),
.TX_FDLY (TX_FDLY_REG),
.TX_FDLY_RES (TX_FDLY_RES_REG),
.TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG),
.TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_INT),
.TX_UPDATE_MODE (TX_UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.O (O_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.RX_CNTVALUEOUT (RX_CNTVALUEOUT_out),
.TX2RX_CASC_OUT (TX2RX_CASC_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.TX_CNTVALUEOUT (TX_CNTVALUEOUT_out),
.T_OUT (T_OUT_out),
.D (D_in),
.DATAIN (DATAIN_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.OFD_CE (OFD_CE_in),
.RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CLKDIV (RX_CLKDIV_in),
.RX_CLK_C (RX_CLK_C_in),
.RX_CLK_C_B (RX_CLK_C_B_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RST (RX_RST_in),
.RX_RST_DLY (RX_RST_DLY_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.TX2RX_CASC_IN (TX2RX_CASC_IN_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_CE (TX_CE_in),
.TX_CLK (TX_CLK_in),
.TX_CNTVALUEIN (TX_CNTVALUEIN_in),
.TX_EN_VTC (TX_EN_VTC_in),
.TX_INC (TX_INC_in),
.TX_LOAD (TX_LOAD_in),
.TX_OCLK (TX_OCLK_in),
.TX_OCLKDIV (TX_OCLKDIV_in),
.TX_RST (TX_RST_in),
.TX_RST_DLY (TX_RST_DLY_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SIM_OSERDES_Q(OSERDES_Q_out),
.SIM_BITSLICE_WRITE_Q(BITSLICE_WRITE_Q_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
specify
(D *> O) = (0:0:0, 0:0:0);
(D *> T_OUT) = (0:0:0, 0:0:0);
(DATAIN *> Q) = (0:0:0, 0:0:0);
(DATAIN *> RX_BIT_CTRL_OUT) = (0:0:0, 0:0:0);
(FIFO_RD_CLK *> Q) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => FIFO_EMPTY) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN *> Q) = (0:0:0, 0:0:0);
(TBYTE_IN => T_OUT) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN *> O) = (0:0:0, 0:0:0);
(TX_BIT_CTRL_IN *> T_OUT) = (0:0:0, 0:0:0);
(negedge RX_RST *> (Q +: 0)) = (0:0:0, 0:0:0);
(negedge TX_RST => (O +: 0)) = (0:0:0, 0:0:0);
(posedge RX_RST *> (Q +: 0)) = (0:0:0, 0:0:0);
(posedge TX_RST => (O +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (negedge RX_BIT_CTRL_IN[21], 0:0:0, notifier);
$period (negedge RX_CLK, 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[0], 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (negedge TX_CLK, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge RX_BIT_CTRL_IN[21], 0:0:0, notifier);
$period (posedge RX_CLK, 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[0], 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (posedge TX_CLK, 0:0:0, notifier);
$recrem ( negedge RX_RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_delay, FIFO_RD_CLK_delay);
$recrem ( negedge RX_RST, posedge RX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RX_RST_delay, RX_BIT_CTRL_IN_delay);
$recrem ( negedge RX_RST_DLY, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_CLK_delay);
$recrem ( negedge RX_RST_DLY, posedge RX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_BIT_CTRL_IN_delay);
$recrem ( negedge RX_RST_DLY, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_CLK_delay);
$recrem ( negedge TX_RST, negedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_delay, TX_BIT_CTRL_IN_delay);
$recrem ( negedge TX_RST, posedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_delay, TX_BIT_CTRL_IN_delay);
$recrem ( negedge TX_RST_DLY, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_CLK_delay);
$recrem ( negedge TX_RST_DLY, posedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_BIT_CTRL_IN_delay);
$recrem ( negedge TX_RST_DLY, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_CLK_delay);
$recrem ( posedge RX_RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_delay, FIFO_RD_CLK_delay);
$recrem ( posedge RX_RST, posedge RX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RX_RST_delay, RX_BIT_CTRL_IN_delay);
$recrem ( posedge RX_RST_DLY, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_CLK_delay);
$recrem ( posedge RX_RST_DLY, posedge RX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_BIT_CTRL_IN_delay);
$recrem ( posedge RX_RST_DLY, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RST_DLY_delay, RX_CLK_delay);
$recrem ( posedge TX_RST, negedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_delay, TX_BIT_CTRL_IN_delay);
$recrem ( posedge TX_RST, posedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_delay, TX_BIT_CTRL_IN_delay);
$recrem ( posedge TX_RST_DLY, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_CLK_delay);
$recrem ( posedge TX_RST_DLY, posedge TX_BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_BIT_CTRL_IN_delay);
$recrem ( posedge TX_RST_DLY, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RST_DLY_delay, TX_CLK_delay);
$setuphold (negedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay);
$setuphold (negedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay);
$setuphold (negedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge TX_BIT_CTRL_IN, negedge D, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, D_delay);
$setuphold (negedge TX_BIT_CTRL_IN, posedge D, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, D_delay);
$setuphold (negedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay);
$setuphold (negedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (negedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay);
$setuphold (negedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge RX_BIT_CTRL_IN, negedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_CE_delay);
$setuphold (posedge RX_BIT_CTRL_IN, negedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_CNTVALUEIN_delay);
$setuphold (posedge RX_BIT_CTRL_IN, negedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_INC_delay);
$setuphold (posedge RX_BIT_CTRL_IN, negedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_LOAD_delay);
$setuphold (posedge RX_BIT_CTRL_IN, posedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_CE_delay);
$setuphold (posedge RX_BIT_CTRL_IN, posedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_CNTVALUEIN_delay);
$setuphold (posedge RX_BIT_CTRL_IN, posedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_INC_delay);
$setuphold (posedge RX_BIT_CTRL_IN, posedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_BIT_CTRL_IN_delay, RX_LOAD_delay);
$setuphold (posedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay);
$setuphold (posedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay);
$setuphold (posedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge D, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, D_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge DATAIN, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, DATAIN_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_CE_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_CNTVALUEIN_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_INC_delay);
$setuphold (posedge TX_BIT_CTRL_IN, negedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_LOAD_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge D, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, D_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge DATAIN, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, DATAIN_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_CE_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_CNTVALUEIN_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_INC_delay);
$setuphold (posedge TX_BIT_CTRL_IN, posedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay, TX_LOAD_delay);
$setuphold (posedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay);
$setuphold (posedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay);
$setuphold (posedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (negedge RX_BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (negedge RX_CLK, 0:0:0, 0, notifier);
$width (negedge TX_BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (negedge TX_CLK, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge RX_BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (posedge RX_CLK, 0:0:0, 0, notifier);
$width (posedge TX_BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (posedge TX_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/RX_BITSLICE.v 0000664 0000000 0000000 00000060232 12327044266 0023234 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : RX_BITSLICE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RX_BITSLICE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CASCADE = "FALSE",
parameter DATA_TYPE = "NONE",
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter integer DELAY_VALUE_EXT = 0,
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REFCLK_FREQUENCY = 300.0,
parameter UPDATE_MODE = "ASYNC",
parameter UPDATE_MODE_EXT = "ASYNC"
)(
output [34:0] BIT_CTRL_OUT,
output [28:0] BIT_CTRL_OUT_EXT,
output [8:0] CNTVALUEOUT,
output [8:0] CNTVALUEOUT_EXT,
output FIFO_EMPTY,
output FIFO_WRCLK_OUT,
output [7:0] Q,
input [23:0] BIT_CTRL_IN,
input [14:0] BIT_CTRL_IN_EXT,
input CE,
input CE_EXT,
input CLK,
input CLK_EXT,
input [8:0] CNTVALUEIN,
input [8:0] CNTVALUEIN_EXT,
input DATAIN,
input EN_VTC,
input EN_VTC_EXT,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input INC,
input INC_EXT,
input LOAD,
input LOAD_EXT,
input RST,
input RST_DLY,
input RST_DLY_EXT
);
// define constants
localparam MODULE_NAME = "RX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [40:1] CASCADE_REG = CASCADE;
localparam [112:1] DATA_TYPE_REG = DATA_TYPE;
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT;
localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE;
localparam [10:0] DELAY_VALUE_REG = DELAY_VALUE;
localparam [10:0] DELAY_VALUE_EXT_REG = DELAY_VALUE_EXT;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [0:0] IS_CLK_EXT_INVERTED_REG = IS_CLK_EXT_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_DLY_EXT_INVERTED_REG = IS_RST_DLY_EXT_INVERTED;
localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE;
localparam [48:1] UPDATE_MODE_EXT_REG = UPDATE_MODE_EXT;
`endif
localparam [0:0] DC_ADJ_EN_REG = 1'b0;
localparam [0:0] DC_ADJ_EN_EXT_REG = 1'b0;
localparam [40:1] DDR_DIS_DQS_REG = "TRUE";
localparam [2:0] FDLY_REG = 3'b000;
localparam [2:0] FDLY_EXT_REG = 3'b000;
localparam [2:0] FDLY_RES_REG = 3'b000;
localparam [2:0] FDLY_RES_EXT_REG = 3'b000;
localparam [0:0] RECALIBRATE_EN_REG = 1'b0;
reg [63:0] REFCLK_FREQUENCY_INT = REFCLK_FREQUENCY * 1000;
localparam [64:1] TBYTE_CTL_REG = "T";
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_CLK_EXT_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_DLY_EXT_INVERTED_BIN;
wire IS_RST_DLY_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RX_BITSLICE_dr.v"
`endif
wire FIFO_EMPTY_out;
wire FIFO_WRCLK_OUT_out;
wire [28:0] BIT_CTRL_OUT_EXT_out;
wire [34:0] BIT_CTRL_OUT_out;
wire [7:0] Q_out;
wire [8:0] CNTVALUEOUT_EXT_out;
wire [8:0] CNTVALUEOUT_out;
wire FIFO_EMPTY_delay;
wire FIFO_WRCLK_OUT_delay;
wire [28:0] BIT_CTRL_OUT_EXT_delay;
wire [34:0] BIT_CTRL_OUT_delay;
wire [7:0] Q_delay;
wire [8:0] CNTVALUEOUT_EXT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CE_EXT_in;
wire CE_in;
wire CLK_EXT_in;
wire CLK_in;
wire DATAIN_in;
wire EN_VTC_EXT_in;
wire EN_VTC_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire INC_EXT_in;
wire INC_in;
wire LOAD_EXT_in;
wire LOAD_in;
wire OFD_CE_in;
wire RST_DLY_EXT_in;
wire RST_DLY_in;
wire RST_in;
wire RX_DATAIN1_in;
wire TX_RST_in;
wire T_in;
wire [14:0] BIT_CTRL_IN_EXT_in;
wire [23:0] BIT_CTRL_IN_in;
wire [7:0] TX_D_in;
wire [8:0] CNTVALUEIN_EXT_in;
wire [8:0] CNTVALUEIN_in;
wire CE_EXT_delay;
wire CE_delay;
wire CLK_EXT_delay;
wire CLK_delay;
wire DATAIN_delay;
wire EN_VTC_EXT_delay;
wire EN_VTC_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire INC_EXT_delay;
wire INC_delay;
wire LOAD_EXT_delay;
wire LOAD_delay;
wire RST_DLY_EXT_delay;
wire RST_DLY_delay;
wire RST_delay;
wire [14:0] BIT_CTRL_IN_EXT_delay;
wire [23:0] BIT_CTRL_IN_delay;
wire [8:0] CNTVALUEIN_EXT_delay;
wire [8:0] CNTVALUEIN_delay;
wire IDELAY_DATAIN0_out;
wire IDELAY_DATAOUT_out;
assign #(out_delay) BIT_CTRL_OUT = BIT_CTRL_OUT_delay;
assign #(out_delay) BIT_CTRL_OUT_EXT = BIT_CTRL_OUT_EXT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) CNTVALUEOUT_EXT = CNTVALUEOUT_EXT_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay;
assign #(out_delay) Q = Q_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_EXT_delay = CLK_EXT;
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) BIT_CTRL_IN_EXT_delay = BIT_CTRL_IN_EXT;
assign #(in_delay) BIT_CTRL_IN_delay = BIT_CTRL_IN;
assign #(in_delay) CE_EXT_delay = CE_EXT;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_EXT_delay = CNTVALUEIN_EXT;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) INC_EXT_delay = INC_EXT;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_EXT_delay = LOAD_EXT;
assign #(in_delay) LOAD_delay = LOAD;
assign #(in_delay) RST_DLY_EXT_delay = RST_DLY_EXT;
assign #(in_delay) RST_DLY_delay = RST_DLY;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) EN_VTC_EXT_delay = EN_VTC_EXT;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign BIT_CTRL_OUT_EXT_delay = BIT_CTRL_OUT_EXT_out;
assign BIT_CTRL_OUT_delay = BIT_CTRL_OUT_out;
assign CNTVALUEOUT_EXT_delay = CNTVALUEOUT_EXT_out;
assign CNTVALUEOUT_delay = CNTVALUEOUT_out;
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out;
assign Q_delay = Q_out;
assign BIT_CTRL_IN_EXT_in = BIT_CTRL_IN_EXT_delay;
assign BIT_CTRL_IN_in = BIT_CTRL_IN_delay;
assign CE_EXT_in = CE_EXT_delay;
assign CE_in = CE_delay;
assign CLK_EXT_in = CLK_EXT_delay ^ IS_CLK_EXT_INVERTED_BIN;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CNTVALUEIN_EXT_in = CNTVALUEIN_EXT_delay;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign DATAIN_in = DATAIN_delay;
assign EN_VTC_EXT_in = EN_VTC_EXT_delay;
assign EN_VTC_in = EN_VTC_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign INC_EXT_in = INC_EXT_delay;
assign INC_in = INC_delay;
assign LOAD_EXT_in = LOAD_EXT_delay;
assign LOAD_in = LOAD_delay;
assign RST_DLY_EXT_in = RST_DLY_EXT_delay ^ IS_RST_DLY_EXT_INVERTED_BIN;
assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLK_EXT_INVERTED_BIN = IS_CLK_EXT_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_DLY_EXT_INVERTED_BIN = IS_RST_DLY_EXT_INVERTED_REG;
assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((CASCADE_REG != "FALSE") &&
(CASCADE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute CASCADE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, CASCADE_REG);
attr_err = 1'b1;
end
if ((DATA_TYPE_REG != "NONE") &&
(DATA_TYPE_REG != "CLOCK") &&
(DATA_TYPE_REG != "DATA") &&
(DATA_TYPE_REG != "DATA_AND_CLOCK")) begin
$display("Attribute Syntax Error : The attribute DATA_TYPE on %s instance %m is set to %s. Legal values for this attribute are NONE, CLOCK, DATA or DATA_AND_CLOCK.", MODULE_NAME, DATA_TYPE_REG);
attr_err = 1'b1;
end
if ((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 2) &&
(DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((DELAY_FORMAT_REG != "TIME") &&
(DELAY_FORMAT_REG != "COUNT")) begin
$display("Attribute Syntax Error : The attribute DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((DELAY_TYPE_REG != "FIXED") &&
(DELAY_TYPE_REG != "VARIABLE") &&
(DELAY_TYPE_REG != "VAR_LOAD")) begin
$display("Attribute Syntax Error : The attribute DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((DELAY_VALUE_EXT_REG < 0) || (DELAY_VALUE_EXT_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE_EXT on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_EXT_REG);
attr_err = 1'b1;
end
if ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute FIFO_SYNC_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((IS_CLK_EXT_INVERTED_REG < 1'b0) || (IS_CLK_EXT_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_EXT_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_EXT_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG < 1'b0) || (IS_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_DLY_EXT_INVERTED_REG < 1'b0) || (IS_RST_DLY_EXT_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_DLY_EXT_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_DLY_EXT_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_DLY_INVERTED_REG < 1'b0) || (IS_RST_DLY_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_DLY_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((UPDATE_MODE_EXT_REG != "ASYNC") &&
(UPDATE_MODE_EXT_REG != "MANUAL") &&
(UPDATE_MODE_EXT_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE_EXT on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_EXT_REG);
attr_err = 1'b1;
end
if ((UPDATE_MODE_REG != "ASYNC") &&
(UPDATE_MODE_REG != "MANUAL") &&
(UPDATE_MODE_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
if (REFCLK_FREQUENCY_REG >= 300.0 && REFCLK_FREQUENCY_REG <= 1333.0) begin // float
REFCLK_FREQUENCY_INT <= REFCLK_FREQUENCY_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign TX_D_in = 8'b00000000; // tie off
assign TX_RST_in = 1'b1; // tie off
assign T_in = 1'b1; // tie off
SIP_RX_BITSLICE SIP_RX_BITSLICE_INST (
.CASCADE (CASCADE_REG),
.DATA_TYPE (DATA_TYPE_REG),
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DC_ADJ_EN_EXT (DC_ADJ_EN_EXT_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.DELAY_VALUE_EXT (DELAY_VALUE_EXT_REG),
.FDLY (FDLY_REG),
.FDLY_EXT (FDLY_EXT_REG),
.FDLY_RES (FDLY_RES_REG),
.FDLY_RES_EXT (FDLY_RES_EXT_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.RECALIBRATE_EN (RECALIBRATE_EN_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_INT),
.TBYTE_CTL (TBYTE_CTL_REG),
.UPDATE_MODE (UPDATE_MODE_REG),
.UPDATE_MODE_EXT (UPDATE_MODE_EXT_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.BIT_CTRL_OUT (BIT_CTRL_OUT_out),
.BIT_CTRL_OUT_EXT (BIT_CTRL_OUT_EXT_out),
.CNTVALUEOUT (CNTVALUEOUT_out),
.CNTVALUEOUT_EXT (CNTVALUEOUT_EXT_out),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.Q (Q_out),
.BIT_CTRL_IN (BIT_CTRL_IN_in),
.BIT_CTRL_IN_EXT (BIT_CTRL_IN_EXT_in),
.CE (CE_in),
.CE_EXT (CE_EXT_in),
.CLK (CLK_in),
.CLK_EXT (CLK_EXT_in),
.CNTVALUEIN (CNTVALUEIN_in),
.CNTVALUEIN_EXT (CNTVALUEIN_EXT_in),
.DATAIN (DATAIN_in),
.EN_VTC (EN_VTC_in),
.EN_VTC_EXT (EN_VTC_EXT_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.INC (INC_in),
.INC_EXT (INC_EXT_in),
.LOAD (LOAD_in),
.LOAD_EXT (LOAD_EXT_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.RST_DLY_EXT (RST_DLY_EXT_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.T (T_in),
.TX_D (TX_D_in),
.TX_RST (TX_RST_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.GSR (glblGSR)
);
specify
(BIT_CTRL_IN *> Q) = (0:0:0, 0:0:0);
(DATAIN *> BIT_CTRL_OUT) = (0:0:0, 0:0:0);
(DATAIN *> Q) = (0:0:0, 0:0:0);
(FIFO_RD_CLK *> Q) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => FIFO_EMPTY) = (0:0:0, 0:0:0);
(negedge RST *> (Q +: 0)) = (0:0:0, 0:0:0);
(posedge RST *> (Q +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge BIT_CTRL_IN[21], 0:0:0, notifier);
$period (negedge BIT_CTRL_IN_EXT[0], 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLK_EXT, 0:0:0, notifier);
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge BIT_CTRL_IN[21], 0:0:0, notifier);
$period (posedge BIT_CTRL_IN_EXT[0], 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLK_EXT, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$recrem ( negedge RST, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( negedge RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, FIFO_RD_CLK_delay);
$recrem ( negedge RST_DLY, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( negedge RST_DLY, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, BIT_CTRL_IN_delay);
$recrem ( negedge RST_DLY, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( negedge RST_DLY_EXT, negedge CLK_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, CLK_EXT_delay);
$recrem ( negedge RST_DLY_EXT, posedge BIT_CTRL_IN_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, BIT_CTRL_IN_EXT_delay);
$recrem ( negedge RST_DLY_EXT, posedge CLK_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, CLK_EXT_delay);
$recrem ( posedge RST, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( posedge RST, posedge FIFO_RD_CLK, 0:0:0, 0:0:0, notifier,,, RST_delay, FIFO_RD_CLK_delay);
$recrem ( posedge RST_DLY, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( posedge RST_DLY, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, BIT_CTRL_IN_delay);
$recrem ( posedge RST_DLY, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( posedge RST_DLY_EXT, negedge CLK_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, CLK_EXT_delay);
$recrem ( posedge RST_DLY_EXT, posedge BIT_CTRL_IN_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, BIT_CTRL_IN_EXT_delay);
$recrem ( posedge RST_DLY_EXT, posedge CLK_EXT, 0:0:0, 0:0:0, notifier,,, RST_DLY_EXT_delay, CLK_EXT_delay);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CE_EXT_delay);
$setuphold (negedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (negedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, INC_EXT_delay);
$setuphold (negedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (negedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CE_EXT_delay);
$setuphold (negedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (negedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, INC_EXT_delay);
$setuphold (negedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, negedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, negedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, posedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, posedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, CE_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, INC_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, CE_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, INC_EXT_delay);
$setuphold (posedge BIT_CTRL_IN_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK_EXT, negedge CE_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CE_EXT_delay);
$setuphold (posedge CLK_EXT, negedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge CLK_EXT, negedge INC_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, INC_EXT_delay);
$setuphold (posedge CLK_EXT, negedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge CLK_EXT, posedge CE_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CE_EXT_delay);
$setuphold (posedge CLK_EXT, posedge CNTVALUEIN_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, CNTVALUEIN_EXT_delay);
$setuphold (posedge CLK_EXT, posedge INC_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, INC_EXT_delay);
$setuphold (posedge CLK_EXT, posedge LOAD_EXT, 0:0:0, 0:0:0, notifier,,, CLK_EXT_delay, LOAD_EXT_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$width (negedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (negedge BIT_CTRL_IN_EXT, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLK_EXT, 0:0:0, 0, notifier);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (posedge BIT_CTRL_IN_EXT, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK_EXT, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SIM_CONFIGE2.v 0000664 0000000 0000000 00000240722 12327044266 0023275 0 ustar 00root root 0000000 0000000 //////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.66)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Configuration Simulation Model
// /___/ /\ Filename : SIM_CONFIGE2.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 12/04/10 - Initial version
// 03/14/11 - Make crc_ck 1 cycle long (CR599232)
// 03/17/11 - Handle CSB toggle (CR601925)
// 03/24/11 - Add cbi_b_ins to sync to negedge clock(CR603092)
// 05/03/11 - delay outbus 1 cycle (CR605404)
// 05/20/11 - initial done_cycle_reg (CR611383)
// 07/01/11 - Generate startup_set_pulse when rw_en=1 (595934)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/21/13 - Updated output latency to 3 clock cycles (CR 701426).
// 09/09/13 - Fixed output IDCODE (CR 727695).
// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079).
// End Revision
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module SIM_CONFIGE2 (
CSOB,
DONE,
CCLK,
CSB,
D,
INITB,
M,
PROGB,
RDWRB
);
output CSOB;
inout DONE;
input CCLK;
input CSB;
inout [31:0] D;
inout INITB;
input [2:0] M;
input PROGB;
input RDWRB;
parameter DEVICE_ID = 32'h0;
parameter ICAP_SUPPORT = "FALSE";
parameter ICAP_WIDTH = "X8";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt";
localparam cfg_Tprog = 250000; // min PROG must be low
localparam cfg_Tpl = 100000; // max program latency us.
localparam STARTUP_PH0 = 3'b000;
localparam STARTUP_PH1 = 3'b001;
localparam STARTUP_PH2 = 3'b010;
localparam STARTUP_PH3 = 3'b011;
localparam STARTUP_PH4 = 3'b100;
localparam STARTUP_PH5 = 3'b101;
localparam STARTUP_PH6 = 3'b110;
localparam STARTUP_PH7 = 3'b111;
// tri0 GSR, GTS, GWE;
wire GSR;
wire GTS;
wire GWE;
wire cclk_in;
wire init_b_in;
wire prog_b_in;
wire rdwr_b_in;
reg rdwr_b_in1;
reg checka_en = 0;
reg init_b_out = 1;
reg [3:0] done_o = 4'b0;
integer frame_data_fd;
integer farn = 0;
integer ib, ib_skp, ci, bi;
reg frame_data_wen = 0;
tri1 p_up;
reg por_b;
wire [2:0] m_in;
wire [31:0] d_in;
wire [31:0] d_out;
wire busy_out;
wire cso_b_out;
wire csi_b_in;
reg csi_b_ins = 1;
wire d_out_en;
wire pll_locked;
reg pll_lockwt;
wire init_b_t;
wire prog_b_t;
wire bus_en;
wire [3:0] desync_flag;
wire [3:0] crc_rst;
reg [3:0] crc_bypass = 0;
reg icap_on = 0;
reg icap_clr = 0;
reg icap_sync = 0;
reg icap_desynch = 0;
reg rd_desynch = 0;
reg rd_desynch_tmp = 0;
reg icap_init_done = 0;
reg icap_init_done_dly = 0;
wire [3:0] desynch_set1;
reg [1:0] icap_bw = 2'b00;
assign DONE = p_up;
assign INITB = p_up;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
assign glbl.PROGB_GLBL = PROGB;
assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1;
buf buf_cso (CSOB, cso_b_out);
buf buf_cclk (cclk_in, CCLK);
buf buf_cs (csi_b_in, CSB);
buf buf_din[31:0] (d_in, D);
bufif1 buf_dout[31:0] (D, d_out, d_out_en);
buf buf_init (init_b_in, INITB);
buf buf_m_0 (m_in[0], M[0]);
buf buf_m_1 (m_in[1], M[1]);
buf buf_m_2 (m_in[2], M[2]);
buf buf_prog (prog_b_in, PROGB);
buf buf_rw (rdwr_b_in, RDWRB);
time prog_pulse_low_edge = 0;
time prog_pulse_low = 0;
reg mode_sample_flag = 0;
reg [3:0] buswid_flag_init = 4'b0;
reg [3:0] buswid_flag = 4'b0;
reg [1:0] buswidth[3:0];
wire [1:0] buswidth_ibtmp;
reg [1:0] buswidth_tmp[3:0];
reg [31:0] pack_in_reg[3:0];
reg [31:0] pack_in_reg_tmp0 = 32'b0;
reg [31:0] pack_in_reg_tmps0 = 32'b0;
reg [31:0] pack_in_reg_tmp = 32'b0;
reg [4:0] reg_addr[3:0];
reg [4:0] reg_addr_tmp;
reg [3:0] new_data_in_flag = 4'b0;
reg [3:0] wr_flag = 4'b0;
reg [3:0] rd_flag = 4'b0;
reg [3:0] cmd_wr_flag = 4'b0;
reg [3:0] cmd_reg_new_flag = 4'b0;
reg [3:0] cmd_rd_flag = 4'b0;
reg [3:0] bus_sync_flag = 4'b0;
reg [3:0] conti_data_flag = 4'b0;
integer wr_cnt[3:0];
integer conti_data_cnt[3:0];
integer rd_data_cnt[3:0];
integer abort_cnt;
reg [2:0] st_state0 = STARTUP_PH0;
reg [2:0] st_state1 = STARTUP_PH0;
reg [2:0] st_state2 = STARTUP_PH0;
reg [2:0] st_state3 = STARTUP_PH0;
reg [2:0] st_state0i = STARTUP_PH0;
reg [2:0] st_state1i = STARTUP_PH0;
reg [2:0] st_state2i = STARTUP_PH0;
reg [2:0] st_state3i = STARTUP_PH0;
reg startup_begin_flag0 = 0;
reg startup_end_flag0 = 0;
reg startup_begin_flag1 = 0;
reg startup_end_flag1 = 0;
reg startup_begin_flag2 = 0;
reg startup_end_flag2 = 0;
reg startup_begin_flag3 = 0;
reg startup_end_flag3 = 0;
reg [3:0] crc_ck = 4'b0;
reg [3:0] crc_ck_en = 4'b1111;
reg [3:0] crc_err_flag = 4'b0;
wire [3:0] crc_err_flag_tot;
reg [3:0] crc_err_flag_reg = 4'b0;
wire [3:0] crc_en;
reg [31:0] crc_curr[3:0];
reg [31:0] crc_curr_tmp;
wire [31:0] crc_curr_cktmp;
reg [31:0] crc_new;
reg [36:0] crc_input;
reg [31:0] rbcrc_curr[3:0];
reg [31:0] rbcrc_new;
reg [36:0] rbcrc_input;
reg [3:0] gwe_out = 4'b0;
reg [3:0] gts_out = 4'b1111;
reg [31:0] d_o = 32'h0;
reg [31:0] outbus = 32'h0;
reg [31:0] outbus_dly = 32'h0;
reg [31:0] outbus_dly1 = 32'h0;
reg busy_o = 0;
reg [31:0] tmp_val1;
reg [31:0] tmp_val2;
reg [31:0] crc_reg[3:0];
reg [31:0] crc_reg_tmp;
wire [31:0] crc_reg_cktmp;
reg [31:0] far_reg[3:0];
reg [31:0] far_addr;
reg [31:0] fdri_reg[3:0];
reg [31:0] fdro_reg[3:0];
reg [4:0] cmd_reg[3:0];
reg [31:0] ctl0_reg[3:0];
reg [31:0] mask_reg[3:0];
wire [31:0] stat_reg[3:0];
wire [31:0] stat_reg_tmp0;
wire [31:0] stat_reg_tmp1;
wire [31:0] stat_reg_tmp2;
wire [31:0] stat_reg_tmp3;
reg [31:0] lout_reg[3:0];
reg [31:0] cor0_reg[3:0];
reg [31:0] cor0_reg_tmp0 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp1 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp2 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp3 = 32'b00000000000000000011111111101100;
reg [31:0] mfwr_reg[3:0];
reg [31:0] cbc_reg[3:0];
reg [31:0] idcode_reg[3:0];
reg [31:0] axss_reg[3:0];
reg [31:0] cor1_reg[3:0];
reg [31:0] cor1_reg_tmp0 = 32'b0;
reg [31:0] cor1_reg_tmp1 = 32'b0;
reg [31:0] cor1_reg_tmp2 = 32'b0;
reg [31:0] cor1_reg_tmp3 = 32'b0;
reg [31:0] csob_reg[3:0];
reg [31:0] wbstar_reg[3:0];
reg [31:0] timer_reg[3:0];
reg [31:0] rbcrc_hw_reg[3:0];
reg [31:0] rbcrc_sw_reg[3:0];
reg [31:0] rbcrc_live_reg[3:0];
reg [31:0] efar_reg[3:0];
reg [31:0] bootsts_reg[3:0];
reg [31:0] ctl1_reg[3:0];
reg [31:0] testmode_reg[3:0];
reg [31:0] memrd_param_reg[3:0];
reg [31:0] dwc_reg[3:0];
reg [31:0] trim_reg[3:0];
reg [31:0] bout_reg[3:0];
reg [31:0] bspi_reg[3:0];
reg [2:0] mode_pin_in = 3'b0;
reg [2:0] mode_reg;
reg [3:0] crc_reset = 4'b0;
reg [3:0] gsr_set = 4'b0;
reg [3:0] gts_usr_b = 4'b111;
reg [3:0] done_pin_drv = 4'b0;
reg [3:0] shutdown_set = 4'b0;
reg [3:0] desynch_set = 4'b0;
reg [2:0] done_cycle_reg0 = 3'b011;
reg [2:0] done_cycle_reg1 = 3'b011;
reg [2:0] done_cycle_reg2 = 3'b011;
reg [2:0] done_cycle_reg3 = 3'b011;
reg [2:0] gts_cycle_reg0 = 3'b101;
reg [2:0] gts_cycle_reg1 = 3'b101;
reg [2:0] gts_cycle_reg2 = 3'b101;
reg [2:0] gts_cycle_reg3 = 3'b101;
reg [2:0] gwe_cycle_reg0 = 3'b100;
reg [2:0] gwe_cycle_reg1 = 3'b100;
reg [2:0] gwe_cycle_reg2 = 3'b100;
reg [2:0] gwe_cycle_reg3 = 3'b100;
reg init_pin;
reg init_rst = 0;
reg [2:0] nx_st_state0 = 3'b0;
reg [2:0] nx_st_state1 = 3'b0;
reg [2:0] nx_st_state2 = 3'b0;
reg [2:0] nx_st_state3 = 3'b0;
reg [3:0] ghigh_b = 4'b0;
reg [3:0] gts_cfg_b = 4'b0;
reg [3:0] eos_startup = 4'b0;
reg [3:0] startup_set = 4'b0;
reg [1:0] startup_set_pulse0 = 2'b0;
reg [1:0] startup_set_pulse1 = 2'b0;
reg [1:0] startup_set_pulse2 = 2'b0;
reg [1:0] startup_set_pulse3 = 2'b0;
reg abort_out_en = 0;
reg [31:0] tmp_dword;
reg [15:0] tmp_word;
reg [7:0] tmp_byte;
reg [3:0] id_error_flag = 4'b0;
wire id_error_flag_t;
reg [3:0] iprog_b = 4'b1111;
wire iprog_b_t;
reg [3:0] i_init_b_cmd = 4'b1111;
wire i_init_b_cmd_t;
reg i_init_b = 0;
reg [7:0] abort_status = 8'b0;
reg [3:0] persist_en = 0;
reg [3:0] rst_sync = 0;
reg [3:0] abort_dis = 0;
reg [2:0] lock_cycle_reg0 = 3'b0;
reg [2:0] lock_cycle_reg1 = 3'b0;
reg [2:0] lock_cycle_reg2 = 3'b0;
reg [2:0] lock_cycle_reg3 = 3'b0;
reg [3:0] rbcrc_no_pin = 4'b0;
reg abort_flag_rst = 0;
reg [3:0] gsr_st_out = 4'b1111;
reg [3:0] gsr_cmd_out = 4'b0;
reg [3:0] gsr_cmd_out_pulse = 4'b0;
reg d_o_en = 0;
wire rst_intl;
wire rw_en_tmp1;
wire [3:0] rw_en;
wire [3:0] gsr_out;
wire [3:0] cfgerr_b_flag;
reg [3:0] abort_flag = 4'b0;
integer downcont_cnt = 0;
reg rst_en = 0;
reg prog_b_a = 1;
reg [3:0] csbo_flag = 4'b0;
reg [3:0] bout_flag = 4'b0;
reg [3:0] bout_flags = 4'b0;
reg [3:0] bout_bf = 4'b0;
reg [3:0] bout_en = 4'b0001;
reg rd_sw_en = 0;
integer csbo_cnt[3:0];
integer bout_cnt[3:0];
integer bout_cnt_tmp;
reg [4:0] rd_reg_addr[3:0];
reg done_release = 0;
triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out;
triand (weak1, strong0) DONE= done_o[0];
assign DONE= (bout_en[1] == 1) ? done_o[1] : p_up;
assign DONE= (bout_en[2] == 1) ? done_o[2] : p_up;
assign DONE= (bout_en[3] == 1) ? done_o[3] : p_up;
initial begin
if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093")
bout_en = 4'b0011;
else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093")
bout_en = 4'b0111;
else if (DEVICE_ID == "036A6093")
bout_en = 4'b1111;
end
initial begin
buswidth_tmp[0] = 2'b00;
buswidth_tmp[1] = 2'b00;
buswidth_tmp[2] = 2'b00;
buswidth_tmp[3] = 2'b00;
pack_in_reg[0] = 32'b0;
pack_in_reg[1] = 32'b0;
pack_in_reg[2] = 32'b0;
pack_in_reg[3] = 32'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
pack_in_reg_tmp = 32'b0;
crc_curr[0] = 32'b0;
crc_curr[1] = 32'b0;
crc_curr[2] = 32'b0;
crc_curr[3] = 32'b0;
rbcrc_curr[0] = 32'b0;
rbcrc_curr[1] = 32'b0;
rbcrc_curr[2] = 32'b0;
rbcrc_curr[3] = 32'b0;
ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
cor0_reg[0] = 32'b00000000000000000011111111101100;
cor0_reg[1] = 32'b00000000000000000011111111101100;
cor0_reg[2] = 32'b00000000000000000011111111101100;
cor0_reg[3] = 32'b00000000000000000011111111101100;
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
done_cycle_reg1 = cor0_reg_tmp0[14:12];
lock_cycle_reg1 = cor0_reg_tmp0[8:6];
done_cycle_reg2 = cor0_reg_tmp0[14:12];
lock_cycle_reg2 = cor0_reg_tmp0[8:6];
done_cycle_reg3 = cor0_reg_tmp0[14:12];
lock_cycle_reg3 = cor0_reg_tmp0[8:6];
cor1_reg[0] = 32'b0;
cor1_reg[1] = 32'b0;
cor1_reg[2] = 32'b0;
cor1_reg[3] = 32'b0;
wbstar_reg[0] = 32'b0;
wbstar_reg[1] = 32'b0;
wbstar_reg[2] = 32'b0;
wbstar_reg[3] = 32'b0;
timer_reg[0] = 32'b0;
timer_reg[1] = 32'b0;
timer_reg[2] = 32'b0;
timer_reg[3] = 32'b0;
bootsts_reg[0] = 32'b0;
bootsts_reg[1] = 32'b0;
bootsts_reg[2] = 32'b0;
bootsts_reg[3] = 32'b0;
ctl1_reg[0] = 32'b0;
ctl1_reg[1] = 32'b0;
ctl1_reg[2] = 32'b0;
ctl1_reg[3] = 32'b0;
testmode_reg[0] = 32'b0;
testmode_reg[1] = 32'b0;
testmode_reg[2] = 32'b0;
testmode_reg[3] = 32'b0;
memrd_param_reg[0] = 32'b0;
memrd_param_reg[1] = 32'b0;
memrd_param_reg[2] = 32'b0;
memrd_param_reg[3] = 32'b0;
dwc_reg[0] = 32'b0;
dwc_reg[1] = 32'b0;
dwc_reg[2] = 32'b0;
dwc_reg[3] = 32'b0;
trim_reg[0] = 32'b0;
trim_reg[1] = 32'b0;
trim_reg[2] = 32'b0;
trim_reg[3] = 32'b0;
bout_reg[0] = 32'b0;
bout_reg[1] = 32'b0;
bout_reg[2] = 32'b0;
bout_reg[3] = 32'b0;
bspi_reg[0] = 32'h000B;
bspi_reg[1] = 32'h000B;
bspi_reg[2] = 32'h000B;
bspi_reg[3] = 32'h000B;
rd_reg_addr[0] = 5'b0;
rd_reg_addr[1] = 5'b0;
rd_reg_addr[2] = 5'b0;
rd_reg_addr[3] = 5'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
bout_cnt[0] = 0;
bout_cnt[1] = 0;
bout_cnt[2] = 0;
bout_cnt[3] = 0;
done_o = 4'b0;
end
initial begin
case (ICAP_SUPPORT)
"FALSE" : icap_on = 0;
"TRUE" : icap_on = 1;
default : icap_on = 0;
endcase
if (DEVICE_ID == 32'h0 && icap_on == 0) begin
$display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIGE2 instance %m is not set.");
end
if (ICAP_SUPPORT == "TRUE") begin
case (ICAP_WIDTH)
"X8" : icap_bw = 2'b01;
"X16" : icap_bw = 2'b10;
"X32" : icap_bw = 2'b11;
default : icap_bw = 2'b01;
endcase
frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w");
if (frame_data_fd != 0) begin
frame_data_wen = 1;
$fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n");
end
end
else begin
icap_bw = 2'b00;
frame_data_wen = 0;
end
icap_sync = 0;
end
assign GSR = gsr_out[0];
assign GTS = gts_out[0];
assign GWE = gwe_out[0];
assign busy_out = busy_o;
assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0];
assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1];
assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2];
assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3];
assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0];
assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1];
assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2];
assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3];
assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0];
assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8];
assign d_out_en = d_o_en;
assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1;
assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111;
always @(posedge cclk_in) begin
outbus_dly <= outbus_dly1;
outbus_dly1 <= outbus;
end
always @(posedge cclk_in or csi_b_in)
if (csi_b_in == 1)
csi_b_ins <= csi_b_in;
else begin
if (cclk_in != 1)
csi_b_ins <= csi_b_in;
else
@(negedge cclk_in)
csi_b_ins <= csi_b_in;
end
always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] )
if (abort_out_en == 1)
d_o_en = 1;
else
d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib];
assign init_b_t = init_b_in & i_init_b_cmd_t;
always @( negedge prog_b_in) begin
rst_en = 0;
rst_en <= #cfg_Tprog 1;
end
assign iprog_b_0 = iprog_b[0];
assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1;
assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1;
assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1;
assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0;
assign i_init_b_cmd_0 = i_init_b_cmd[0];
assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1;
assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1;
assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1;
assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2
& i_init_b_cmd_3;
always @( rst_en or init_rst or prog_b_in or iprog_b_t )
if (icap_on == 0) begin
if (init_rst == 1)
init_b_out <= 0;
else begin
if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0))
init_b_out <= 0;
else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1))
init_b_out <= #(cfg_Tpl) 1;
end
end
assign id_error_flag_t = &id_error_flag;
always @(posedge id_error_flag_t) begin
init_rst <= 1;
init_rst <= #cfg_Tprog 0;
end
always @( rst_en or prog_b_in or prog_pulse_low)
if (rst_en == 1) begin
if (prog_pulse_low==cfg_Tprog) begin
prog_b_a = 0;
prog_b_a <= #500 1;
end
else
prog_b_a = prog_b_in;
end
else
prog_b_a = 1;
initial begin
por_b = 0;
por_b = #400000 1;
end
assign prog_b_t = prog_b_a & iprog_b_t & por_b;
assign rst_intl = (prog_b_t==0 ) ? 0 : 1;
always @( init_b_t or prog_b_t)
if (prog_b_t == 0)
mode_sample_flag <= 0;
else if (init_b_t && mode_sample_flag == 0) begin
if (prog_b_t == 1) begin
mode_pin_in <= m_in;
if (m_in !== 3'b110) begin
mode_sample_flag <= 0;
if ( icap_on == 0)
$display("Error: input M is %h. Only Slave SelectMAP mode M=110 supported on SIM_CONFIGE2 instance %m.", m_in);
end
else
mode_sample_flag <= #1 1;
end
end
always @(posedge init_b_t )
if (prog_b_t != 1) begin
if ($time != 0 && icap_on == 0)
$display("Error: PROGB is not high when INITB goes high on SIM_CONFIGE2 instance %m at time %t.", $time);
end
always @(m_in)
if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0)
$display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIGE2 instance %m at time %t.", $time);
always @(posedge prog_b_in or negedge prog_b_in)
if (prog_b_in == 0)
prog_pulse_low_edge <= $time;
else if (prog_b_in == 1 && $time > 0) begin
prog_pulse_low = $time - prog_pulse_low_edge;
if (prog_pulse_low < cfg_Tprog && icap_on == 0)
$display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIGE2 instance %m at time %t.", cfg_Tprog, $time);
end
assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0;
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0 ) begin
buswid_flag_init <= 4'b0;
buswid_flag <= 4'b0;
buswidth_tmp[0] <= 2'b00;
buswidth_tmp[1] <= 2'b00;
buswidth_tmp[2] <= 2'b00;
buswidth_tmp[3] <= 2'b00;
end
else
if (buswid_flag[ib] == 0) begin
if (bus_en == 1 && rdwr_b_in == 0) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (buswid_flag_init[ib] == 0) begin
if (tmp_byte == 8'hBB)
buswid_flag_init[ib] <= 1;
end
else begin
if (tmp_byte == 8'h11) begin
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b01;
end
else if (tmp_byte == 8'h22) begin
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b10;
end
else if (tmp_byte == 8'h44) begin
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b11;
end
else begin
buswid_flag[ib] <= 0;
buswidth_tmp[ib] <= 2'b00;
buswid_flag_init[ib] <= 0;
if (icap_on == 0)
$display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB on SIM_CONFIGE2 instance %m at time %t.", $time);
else
$display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE2 instance %m at time %t.", $time);
end
end
end
end
assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib];
always @(buswidth_ibtmp)
buswidth[ib] = buswidth_ibtmp;
assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0;
assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0;
assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0;
assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0;
assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0;
assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch;
assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch;
assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch;
assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch;
assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0];
assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1];
assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2];
assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3];
always @(posedge eos_startup[0])
if (icap_on == 1) begin
$fclose(frame_data_fd);
icap_init_done <= 1;
@(posedge cclk_in);
@(posedge cclk_in)
if (icap_init_done_dly == 0)
icap_desynch <= 1;
@(posedge cclk_in);
@(posedge cclk_in) begin
icap_desynch <= 0;
icap_init_done_dly <= 1;
end
@(posedge cclk_in);
@(posedge cclk_in);
@(posedge cclk_in);
end
else begin
icap_clr <= 0;
icap_desynch <= 0;
end
always @(posedge cclk_in or negedge rdwr_b_in)
if (rdwr_b_in == 0)
rd_sw_en <= 0;
else begin
if (csi_b_in == 1 && rdwr_b_in ==1)
rd_sw_en <= 1;
end
assign desync_flag_t = |desync_flag;
always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin
if (desync_flag[ib] == 1) begin
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
if (desync_flag[0] == 1 ) begin
new_data_in_flag[0] = 0;
bus_sync_flag[0] = 0;
wr_cnt[0] = 0;
wr_flag[0] = 0;
rd_flag[0] = 0;
end
if (desync_flag[1] == 1 ) begin
new_data_in_flag[1] = 0;
bus_sync_flag[1] = 0;
wr_cnt[1] = 0;
wr_flag[1] = 0;
rd_flag[1] = 0;
end
if (desync_flag[2] == 1 ) begin
new_data_in_flag[2] = 0;
bus_sync_flag[2] = 0;
wr_cnt[2] = 0;
wr_flag[2] = 0;
rd_flag[2] = 0;
end
if (desync_flag[3] == 1 ) begin
new_data_in_flag[3] = 0;
bus_sync_flag[3] = 0;
wr_cnt[3] = 0;
wr_flag[3] = 0;
rd_flag[3] = 0;
end
if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin
new_data_in_flag = 4'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else begin
if (icap_clr == 1) begin
new_data_in_flag <= 4'b0;
wr_cnt[0] <= 0;
wr_cnt[1] <= 0;
wr_cnt[2] <= 0;
wr_cnt[3] <= 0;
wr_flag <= 4'b0;
rd_flag <= 4'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin
if (rdwr_b_in == 0) begin
wr_flag[ib] <= 1;
rd_flag[ib] <= 0;
if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99
&& pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16];
pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8];
pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
end
end
else begin
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[31:24] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[23:16] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 2;
end
else if (wr_cnt[ib] == 2) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[15:8] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 3;
end
else if (wr_cnt[ib] == 3) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b10) begin
tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])};
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin
wr_cnt[ib] <= 0;
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0];
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0[31:16] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b11 ) begin
tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]),
bit_revers8(d_in[7:0])};
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
if (bus_sync_flag[ib] == 0) begin
if (tmp_dword == 32'hAA995566) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
new_data_in_flag[ib] <= 1;
end
end
end
else begin
wr_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
if (rd_sw_en ==1)
rd_flag[ib] <= 1;
end
end
else begin
wr_flag[ib] <= 0;
rd_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
end
end
end
always @(pack_in_reg_tmps0 or desync_flag or icap_clr)
begin
if (desync_flag[0] == 1 || icap_clr == 1)
pack_in_reg[0] = 32'b0;
if (desync_flag[1] == 1 || icap_clr == 1)
pack_in_reg[1] = 32'b0;
if (desync_flag[2] == 1 || icap_clr == 1)
pack_in_reg[2] = 32'b0;
if (desync_flag[3] == 1 || icap_clr == 1)
pack_in_reg[3] = 32'b0;
if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin
pack_in_reg[0] = pack_in_reg_tmps0;
end
else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0)
pack_in_reg[1] = pack_in_reg_tmps0;
else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0)
pack_in_reg[2] = pack_in_reg_tmps0;
else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0)
pack_in_reg[3] = pack_in_reg_tmps0;
end
task rst_pack_dec;
input ib_d;
begin
conti_data_flag[ib_d] <= 0;
conti_data_cnt[ib_d] <= 0;
cmd_wr_flag[ib_d] <= 0;
cmd_rd_flag[ib_d] <= 0;
id_error_flag[ib_d] <= 0;
crc_curr[ib_d] <= 32'b0;
crc_ck[ib_d] <= 0;
csbo_cnt[ib_d] <= 0;
csbo_flag[ib_d] <= 0;
downcont_cnt <= 0;
rd_data_cnt[ib_d] <= 0;
end
endtask
always @(negedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
else begin
if (icap_clr == 1) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
if (crc_reset[ib] == 1 ) begin
crc_reg[ib] <= 32'b0;
crc_ck[ib] <= 0;
crc_curr[ib] <= 32'b0;
end
if (crc_ck[ib] == 1) begin
crc_curr[ib] <= 32'b0;
crc_ck[ib] <= 0;
end
if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin
bout_flag[0] <= 0;
bout_cnt[0] <= 0;
rst_pack_dec(0);
end
if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin
bout_flag[1] <= 0;
bout_cnt[1] <= 0;
rst_pack_dec(1);
end
if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin
bout_flag[2] <= 0;
bout_cnt[2] <= 0;
rst_pack_dec(2);
end
if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin
bout_flag[3] <= 0;
bout_cnt[3] <= 0;
rst_pack_dec(3);
end
if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0
&& desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin
pack_in_reg_tmp = pack_in_reg[ib];
if (conti_data_flag[ib] == 1 ) begin
reg_addr_tmp = reg_addr[ib];
case (reg_addr_tmp)
5'b00000 : begin
crc_reg[ib] <= pack_in_reg[ib];
crc_reg_tmp <= pack_in_reg[ib];
crc_ck[ib] <= 1;
end
5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]};
5'b00010 : fdri_reg[ib] <= pack_in_reg[ib];
5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0];
5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]);
5'b00110 : mask_reg[ib] <= pack_in_reg[ib];
5'b01000 : lout_reg[ib] <= pack_in_reg[ib];
5'b01001 : cor0_reg[ib] <= pack_in_reg[ib];
5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib];
5'b01011 : cbc_reg[ib] <= pack_in_reg[ib];
5'b01100 : begin
idcode_reg[ib] <= pack_in_reg[ib];
if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin
id_error_flag[ib] <= 1;
if (icap_on == 0)
$display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIGE2 instance %m at time %t.", pack_in_reg[ib], DEVICE_ID, $time);
else
$display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on ICAPE2 instance %m at time %t.", pack_in_reg[ib], DEVICE_ID, $time);
end
else
id_error_flag[ib] <= 0;
end
5'b01101 : axss_reg[ib] <= pack_in_reg[ib];
5'b01110 : cor1_reg[ib] <= pack_in_reg[ib];
5'b01111 : csob_reg[ib] <= pack_in_reg[ib];
5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib];
5'b10001 : timer_reg[ib] <= pack_in_reg[ib];
5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib];
5'b10111 : testmode_reg[ib] <= pack_in_reg[ib];
5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]);
5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11011 : trim_reg[ib] <= pack_in_reg[ib];
5'b11110 : bout_reg[ib] <= pack_in_reg[ib];
5'b11111 : bspi_reg[ib] <= pack_in_reg[ib];
endcase
if (reg_addr[ib] != 5'b00000)
crc_ck[ib] <= 0;
if (reg_addr_tmp == 5'b00100)
cmd_reg_new_flag[ib] <= 1;
else
cmd_reg_new_flag[ib] <= 0;
if (crc_en[ib] == 1) begin
if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111)
crc_curr[ib] = 32'b0;
else begin
if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14
&& reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin
crc_input = {reg_addr[ib], pack_in_reg_tmp};
crc_curr_tmp = crc_curr[ib];
crc_new = bcc_next(crc_curr_tmp, crc_input);
crc_curr[ib] <= crc_new;
end
end
end
if (conti_data_cnt[ib] <= 1) begin
conti_data_cnt[ib] <= 0;
end
else
conti_data_cnt[ib] <= conti_data_cnt[ib] - 1;
end
else if (conti_data_flag[ib] == 0 ) begin
if ( downcont_cnt >= 1) begin
if (crc_en[ib] == 1) begin
crc_input[36:0] = {5'b00010, pack_in_reg[ib]};
crc_new = bcc_next(crc_curr[ib], crc_input);
crc_curr[ib] <= crc_new;
end
if (ib == 0) begin
if (farn <= 80)
farn <= farn + 1;
else begin
far_addr <= far_addr + 1;
farn <= 0;
end
if (frame_data_wen == 1 && icap_init_done == 0) begin
rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]};
rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input);
rbcrc_curr[ib] <= rbcrc_new;
$fwriteh(frame_data_fd, far_addr);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, pack_in_reg[ib]);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, rbcrc_new);
$fwriteh(frame_data_fd, "\n");
end
end
end
if (pack_in_reg_tmp[31:29] == 3'b010 ) begin
bout_cnt_tmp = bout_cnt[ib];
if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
downcont_cnt <= pack_in_reg_tmp[26:0];
far_addr <= far_reg[ib];
end
else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
bout_flag[ib] <= 1;
bout_cnt[ib] <= pack_in_reg_tmp[26:0];
end
else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
csbo_flag[ib] <= 1;
csbo_cnt[ib] <= pack_in_reg_tmp[26:0];
end
end
else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package
if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[10:0] != 11'b0) begin
cmd_rd_flag[ib] <= 1;
cmd_wr_flag[ib] <= 0;
rd_data_cnt[ib] <= 4;
conti_data_cnt[ib] <= 0;
conti_data_flag[ib] <= 0;
rd_reg_addr[ib] <= pack_in_reg_tmp[17:13];
end
end
else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg
lout_reg[ib] <= pack_in_reg_tmp;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib] <= 5'b0;
end
else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg
bout_reg[ib] <= pack_in_reg_tmp;
bout_flags[ib] <= 1;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib]<= 5'b0;
end
else begin
if (pack_in_reg_tmp[10:0] != 10'b0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 1;
conti_data_cnt[ib] <= pack_in_reg_tmp[10:0];
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
else begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
end
end
else begin
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
end
end
end // if (conti_data_flag == 0 )
if (csbo_cnt[ib] != 0 ) begin
if (csbo_flag[ib] == 1)
csbo_cnt[ib] <= csbo_cnt[ib] - 1;
end
else
csbo_flag[ib] <= 0;
if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin
if (bout_cnt[0] == 1) begin
bout_cnt[0] <= 0;
bout_flag[0] <= 0;
end
else
bout_cnt[0] <= bout_cnt[0] - 1;
end
if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin
if (bout_cnt[1] == 1) begin
bout_cnt[1] <= 0;
bout_flag[1] <= 0;
end
else
bout_cnt[1] <= bout_cnt[1] - 1;
end
if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin
bout_cnt[2] <= bout_cnt[2] - 1;
if (bout_cnt[2] == 1) begin
bout_cnt[2] <= 0;
bout_flag[2] <= 0;
end
else
bout_cnt[2] <= bout_cnt[2] - 1;
end
if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin
if (bout_cnt[3] == 1) begin
bout_cnt[3] <= 0;
bout_flag[3] <= 0;
end
else
bout_cnt[3] <= bout_cnt[3] - 1;
end
if (conti_data_cnt[ib] == 5'b00001 )
conti_data_flag[ib] <= 0;
if (crc_ck[ib] == 1 || icap_init_done == 1)
crc_ck[ib] <= 0;
end
if (rw_en[ib] == 1 && csi_b_ins == 0) begin
if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= 0;
else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin
cmd_rd_flag[ib] <= 0;
end
else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= rd_data_cnt[ib] - 1;
if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1)
downcont_cnt <= downcont_cnt - 1;
end
if (cmd_reg_new_flag[ib] == 1 )
cmd_reg_new_flag[ib] <= 0;
end
always @(bout_flag)
if (bout_flag[3] == 1) begin
ib = 3;
ib_skp = 1;
end
else if (bout_flag[2] == 1) begin
ib = 3;
ib_skp = 0;
end
else if (bout_flag[1] == 1) begin
ib = 2;
ib_skp = 0;
end
else if (bout_flag[0] == 1) begin
ib = 1;
ib_skp = 0;
end
else begin
ib = 0;
ib_skp = 0;
end
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
outbus <= 32'b0;
end
else begin
if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin
case (rd_reg_addr[ib])
5'b00000 : if (buswidth[ib] == 2'b01)
rdbk_byte(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]);
5'b00001 : if (buswidth[ib] == 2'b01)
rdbk_byte(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(far_reg[ib], rd_data_cnt[ib]);
5'b00011 : if (buswidth[ib] == 2'b01)
rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]);
5'b00100 : if (buswidth[ib] == 2'b01)
rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]);
5'b00101 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]);
5'b00110 : if (buswidth[ib] == 2'b01)
rdbk_byte(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]);
5'b00111 : if (buswidth[ib] == 2'b01)
rdbk_byte(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]);
5'b01001 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]);
5'b01100 : if (buswidth[ib] == 2'b01)
rdbk_byte(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]);
5'b01101 : if (buswidth[ib] == 2'b01)
rdbk_byte(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]);
5'b01110 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]);
5'b10000 : if (buswidth[ib] == 2'b01)
rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]);
5'b10001 : if (buswidth[ib] == 2'b01)
rdbk_byte(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]);
5'b10010 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
5'b10011 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
5'b10100 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
5'b10101 : if (buswidth[ib] == 2'b01)
rdbk_byte(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]);
5'b10110 : if (buswidth[ib] == 2'b01)
rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]);
5'b11000 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]);
5'b11001 : if (buswidth[ib] == 2'b01)
rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]);
5'b11010 : if (buswidth[ib] == 2'b01)
rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]);
5'b11011 : if (buswidth[ib] == 2'b01)
rdbk_byte(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]);
5'b11111 : if (buswidth[ib] == 2'b01)
rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]);
endcase
if (ib != 0) begin
if (rd_data_cnt[ib] == 1)
rd_desynch_tmp <= 1;
end
end
else begin
outbus <= 32'b0;
rd_desynch <= rd_desynch_tmp;
rd_desynch_tmp <= 0;
end
end
assign crc_rst[0] = crc_reset[0] | ~rst_intl;
assign crc_rst[1] = crc_reset[1] | ~rst_intl;
assign crc_rst[2] = crc_reset[2] | ~rst_intl;
assign crc_rst[3] = crc_reset[3] | ~rst_intl;
assign crc_curr_cktmp = crc_curr[0];
assign crc_reg_cktmp = crc_reg[0];
always @(posedge cclk_in or posedge crc_rst[0] )
if (crc_rst[0] == 1) begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
else
if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin
if (crc_curr[0] != crc_reg[0])
crc_err_flag[0] <= 1;
else
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 0;
end
else begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[1] )
if (crc_rst[1] == 1) begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
else
if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin
if (crc_curr[1] != crc_reg[1])
crc_err_flag[1] <= 1;
else
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 0;
end
else begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[2] )
if (crc_rst[2] == 1) begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
else
if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin
if (crc_curr[2] != crc_reg[2])
crc_err_flag[2] <= 1;
else
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 0;
end
else begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[3] )
if (crc_rst[3] == 1) begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
else
if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin
if (crc_curr[3] != crc_reg[3])
crc_err_flag[3] <= 1;
else
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 0;
end
else begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0])
if (rst_intl == 0)
crc_err_flag_reg[0] <= 0;
else if (crc_err_flag[0] == 1)
crc_err_flag_reg[0] <= 1;
else
crc_err_flag_reg[0] <= 0;
always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1])
if (rst_intl == 0)
crc_err_flag_reg[1] <= 0;
else if (crc_err_flag[1] == 1)
crc_err_flag_reg[1] <= 1;
else
crc_err_flag_reg[1] <= 0;
always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2])
if (rst_intl == 0)
crc_err_flag_reg[2] <= 0;
else if (crc_err_flag[2] == 1)
crc_err_flag_reg[2] <= 1;
else
crc_err_flag_reg[2] <= 0;
always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3])
if (rst_intl == 0)
crc_err_flag_reg[3] <= 0;
else if (crc_err_flag[3] == 1)
crc_err_flag_reg[3] <= 1;
else
crc_err_flag_reg[3] <= 0;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
startup_set <= 4'b0;
crc_reset <= 4'b0;
gsr_cmd_out <= 4'b0;
shutdown_set <= 4'b0;
desynch_set <= 4'b0;
ghigh_b <= 4'b0;
end
else
for (ci = 0; ci <=3; ci = ci+1) begin
if (cmd_reg_new_flag[ci] == 1) begin
if (cmd_reg[ci] == 5'b00011)
ghigh_b[ci] <= 1;
else if (cmd_reg[ci] == 5'b01000)
ghigh_b[ci] <= 0;
if (cmd_reg[ci] == 5'b00101)
startup_set[ci] <= 1;
else
startup_set[ci] <= 0;
if (cmd_reg[ci] == 5'b00111)
crc_reset[ci] <= 1;
else
crc_reset[ci] <= 0;
if (cmd_reg[ci] == 5'b01010)
gsr_cmd_out[ci] <= 1;
else
gsr_cmd_out[ci] <= 0;
if (cmd_reg[ci] == 5'b01011)
shutdown_set[ci] <= 1;
else
shutdown_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01101)
desynch_set[ci] <= 1;
else
desynch_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01111) begin
iprog_b[ci] <= 0;
i_init_b_cmd[ci] <= 0;
iprog_b[ci] <= #cfg_Tprog 1;
i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1;
end
end
else begin
startup_set[ci] <= 0;
crc_reset[ci] <= 0;
gsr_cmd_out[ci] <= 0;
shutdown_set[ci] <= 0;
desynch_set[ci] <= 0;
end
end
always @(posedge startup_set[0] or posedge desynch_set[0] or negedge rw_en[0] )
if (rw_en[0] == 1)
begin
if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin
if (icap_on == 0)
startup_set_pulse0 <= 2'b01;
else begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
always @(posedge startup_set[1] or posedge desynch_set[1] or negedge rw_en[1] )
if (rw_en[1] == 1)
begin
if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin
if (icap_on == 0)
startup_set_pulse1 <= 2'b01;
else begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
always @(posedge startup_set[2] or posedge desynch_set[2] or negedge rw_en[2])
if (rw_en[2] == 1)
begin
if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin
if (icap_on == 0)
startup_set_pulse2 <= 2'b01;
else begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
always @(posedge startup_set[3] or posedge desynch_set[3] or negedge rw_en[3])
if (rw_en[3] == 1)
begin
if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin
if (icap_on == 0)
startup_set_pulse3 <= 2'b01;
else begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
always @(posedge gsr_cmd_out[0] or negedge rw_en[0])
if (rw_en[0] == 0)
gsr_cmd_out_pulse[0] <= 0;
else
begin
gsr_cmd_out_pulse[0] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[0] <= 0;
end
always @(posedge gsr_cmd_out[1] or negedge rw_en[1])
if (rw_en[1] == 0)
gsr_cmd_out_pulse[1] <= 0;
else
begin
gsr_cmd_out_pulse[1] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[1] <= 0;
end
always @(posedge gsr_cmd_out[2] or negedge rw_en[2])
if (rw_en[2] == 0)
gsr_cmd_out_pulse[2] <= 0;
else
begin
gsr_cmd_out_pulse[2] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[2] <= 0;
end
always @(posedge gsr_cmd_out[3] or negedge rw_en[3])
if (rw_en[3] == 0)
gsr_cmd_out_pulse[3] <= 0;
else
begin
gsr_cmd_out_pulse[3] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[3] <= 0;
end
reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3;
always @(ctl0_reg[0]) begin
ctl0_reg_tmp0 = ctl0_reg[0];
if (ctl0_reg_tmp0[9] == 1)
abort_dis[0] = 1;
else
abort_dis[0] = 0;
if (ctl0_reg_tmp0[3] == 1)
persist_en[0] = 1;
else
persist_en[0] = 0;
if (ctl0_reg_tmp0[0] == 1)
gts_usr_b[0] = 1;
else
gts_usr_b[0] = 0;
end
always @(ctl0_reg[1]) begin
ctl0_reg_tmp1 = ctl0_reg[1];
if (ctl0_reg_tmp1[9] == 1)
abort_dis[1] = 1;
else
abort_dis[1] = 0;
if (ctl0_reg_tmp1[3] == 1)
persist_en[1] = 1;
else
persist_en[1] = 0;
if (ctl0_reg_tmp1[0] == 1)
gts_usr_b[1] = 1;
else
gts_usr_b[1] = 0;
end
always @(ctl0_reg[2]) begin
ctl0_reg_tmp2 = ctl0_reg[2];
if (ctl0_reg_tmp2[9] == 1)
abort_dis[2] = 1;
else
abort_dis[2] = 0;
if (ctl0_reg_tmp2[3] == 1)
persist_en[2] = 1;
else
persist_en[2] = 0;
if (ctl0_reg_tmp0[2] == 1)
gts_usr_b[2] = 1;
else
gts_usr_b[2] = 0;
end
always @(ctl0_reg[3]) begin
ctl0_reg_tmp3 = ctl0_reg[3];
if (ctl0_reg_tmp3[9] == 1)
abort_dis[3] = 1;
else
abort_dis[3] = 0;
if (ctl0_reg_tmp3[3] == 1)
persist_en[3] = 1;
else
persist_en[3] = 0;
if (ctl0_reg_tmp3[0] == 1)
gts_usr_b[3] = 1;
else
gts_usr_b[3] = 0;
end
always @(cor0_reg[0])
begin
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
gts_cycle_reg0 = cor0_reg_tmp0[5:3];
gwe_cycle_reg0 = cor0_reg_tmp0[2:0];
if (cor0_reg_tmp0[24] == 1'b1)
done_pin_drv[0] = 1;
else
done_pin_drv[0] = 0;
if (cor0_reg_tmp0[28] == 1'b1)
crc_bypass[0] = 1;
else
crc_bypass[0] = 0;
end
always @(cor0_reg[1])
begin
cor0_reg_tmp1 = cor0_reg[1];
done_cycle_reg1 = cor0_reg_tmp1[14:12];
lock_cycle_reg1 = cor0_reg_tmp1[8:6];
gts_cycle_reg1 = cor0_reg_tmp1[5:3];
gwe_cycle_reg1 = cor0_reg_tmp1[2:0];
if (cor0_reg_tmp1[24] == 1'b1)
done_pin_drv[1] = 1;
else
done_pin_drv[1] = 0;
if (cor0_reg_tmp1[28] == 1'b1)
crc_bypass[1] = 1;
else
crc_bypass[1] = 0;
end
always @(cor0_reg[2])
begin
cor0_reg_tmp2 = cor0_reg[2];
done_cycle_reg2 = cor0_reg_tmp2[14:12];
lock_cycle_reg2 = cor0_reg_tmp2[8:6];
gts_cycle_reg2 = cor0_reg_tmp2[5:3];
gwe_cycle_reg2 = cor0_reg_tmp2[2:0];
if (cor0_reg_tmp2[24] == 1'b1)
done_pin_drv[2] = 1;
else
done_pin_drv[2] = 0;
if (cor0_reg_tmp2[28] == 1'b1)
crc_bypass[2] = 1;
else
crc_bypass[2] = 0;
end
always @(cor0_reg[3])
begin
cor0_reg_tmp3 = cor0_reg[3];
done_cycle_reg3 = cor0_reg_tmp3[14:12];
lock_cycle_reg3 = cor0_reg_tmp3[8:6];
gts_cycle_reg3 = cor0_reg_tmp3[5:3];
gwe_cycle_reg3 = cor0_reg_tmp3[2:0];
if (cor0_reg_tmp3[24] == 1'b1)
done_pin_drv[3] = 1;
else
done_pin_drv[3] = 0;
if (cor0_reg_tmp3[28] == 1'b1)
crc_bypass[3] = 1;
else
crc_bypass[3] = 0;
end
always @(cor1_reg[0]) begin
cor1_reg_tmp0 = cor1_reg[0];
rbcrc_no_pin[0] = cor1_reg_tmp0[8];
end
always @(cor1_reg[1]) begin
cor1_reg_tmp1 = cor1_reg[1];
rbcrc_no_pin[1] = cor1_reg_tmp1[8];
end
always @(cor1_reg[2]) begin
cor1_reg_tmp2 = cor1_reg[2];
rbcrc_no_pin[2] = cor1_reg_tmp2[8];
end
always @(cor1_reg[3]) begin
cor1_reg_tmp3 = cor1_reg[3];
rbcrc_no_pin[3] = cor1_reg_tmp3[8];
end
assign stat_reg_tmp0[31:27] = 5'b00000;
assign stat_reg_tmp1[31:27] = 5'b00000;
assign stat_reg_tmp2[31:27] = 5'b00000;
assign stat_reg_tmp3[31:27] = 5'b00000;
assign stat_reg_tmp0[24:21] = 4'bxxx0;
assign stat_reg_tmp1[24:21] = 4'bxxx0;
assign stat_reg_tmp2[24:21] = 4'bxxx0;
assign stat_reg_tmp3[24:21] = 4'bxxx0;
assign stat_reg_tmp0[17:16] = 2'b0;
assign stat_reg_tmp1[17:16] = 2'b0;
assign stat_reg_tmp2[17:16] = 2'b0;
assign stat_reg_tmp3[17:16] = 2'b0;
assign stat_reg_tmp0[14] = DONE;
assign stat_reg_tmp1[14] = DONE;
assign stat_reg_tmp2[14] = DONE;
assign stat_reg_tmp3[14] = DONE;
assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0;
assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0;
assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0;
assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0;
assign stat_reg_tmp0[12] = INITB;
assign stat_reg_tmp1[12] = INITB;
assign stat_reg_tmp2[12] = INITB;
assign stat_reg_tmp3[12] = INITB;
assign stat_reg_tmp0[11] = mode_sample_flag;
assign stat_reg_tmp1[11] = mode_sample_flag;
assign stat_reg_tmp2[11] = mode_sample_flag;
assign stat_reg_tmp3[11] = mode_sample_flag;
assign stat_reg_tmp0[10:8] = mode_pin_in;
assign stat_reg_tmp1[10:8] = mode_pin_in;
assign stat_reg_tmp2[10:8] = mode_pin_in;
assign stat_reg_tmp3[10:8] = mode_pin_in;
assign stat_reg_tmp0[3] = 1'b1;
assign stat_reg_tmp1[3] = 1'b1;
assign stat_reg_tmp2[3] = 1'b1;
assign stat_reg_tmp3[3] = 1'b1;
assign stat_reg_tmp0[2] = pll_locked;
assign stat_reg_tmp1[2] = pll_locked;
assign stat_reg_tmp2[2] = pll_locked;
assign stat_reg_tmp3[2] = pll_locked;
assign stat_reg_tmp0[1] = 1'b0;
assign stat_reg_tmp1[1] = 1'b0;
assign stat_reg_tmp2[1] = 1'b0;
assign stat_reg_tmp3[1] = 1'b0;
assign stat_reg_tmp0[26:25] = buswidth[0];
assign stat_reg_tmp0[20:18] = st_state0;
assign stat_reg_tmp0[15] = id_error_flag[0];
assign stat_reg_tmp0[7] = ghigh_b[0];
assign stat_reg_tmp0[6] = gwe_out[0];
assign stat_reg_tmp0[5] = gts_cfg_b[0];
assign stat_reg_tmp0[4] = eos_startup[0];
assign stat_reg_tmp0[0] = crc_err_flag_reg[0];
assign stat_reg_tmp1[26:25] = buswidth[1];
assign stat_reg_tmp1[20:18] = st_state1;
assign stat_reg_tmp1[15] = id_error_flag[1];
assign stat_reg_tmp1[7] = ghigh_b[1];
assign stat_reg_tmp1[6] = gwe_out[1];
assign stat_reg_tmp1[5] = gts_cfg_b[1];
assign stat_reg_tmp1[4] = eos_startup[1];
assign stat_reg_tmp1[0] = crc_err_flag_reg[1];
assign stat_reg_tmp2[26:25] = buswidth[2];
assign stat_reg_tmp2[20:18] = st_state2;
assign stat_reg_tmp2[15] = id_error_flag[2];
assign stat_reg_tmp2[7] = ghigh_b[2];
assign stat_reg_tmp2[6] = gwe_out[2];
assign stat_reg_tmp2[5] = gts_cfg_b[2];
assign stat_reg_tmp2[4] = eos_startup[2];
assign stat_reg_tmp2[0] = crc_err_flag_reg[2];
assign stat_reg_tmp3[26:25] = buswidth[3];
assign stat_reg_tmp3[20:18] = st_state3;
assign stat_reg_tmp3[15] = id_error_flag[3];
assign stat_reg_tmp3[7] = ghigh_b[3];
assign stat_reg_tmp3[6] = gwe_out[3];
assign stat_reg_tmp3[5] = gts_cfg_b[3];
assign stat_reg_tmp3[4] = eos_startup[3];
assign stat_reg_tmp3[0] = crc_err_flag_reg[3];
assign stat_reg[0] = stat_reg_tmp0;
assign stat_reg[1] = stat_reg_tmp1;
assign stat_reg[2] = stat_reg_tmp2;
assign stat_reg[3] = stat_reg_tmp3;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
st_state0 <= STARTUP_PH0;
st_state1 <= STARTUP_PH0;
st_state2 <= STARTUP_PH0;
st_state3 <= STARTUP_PH0;
startup_begin_flag0 <= 0;
startup_begin_flag1 <= 0;
startup_begin_flag2 <= 0;
startup_begin_flag3 <= 0;
startup_end_flag0 <= 0;
startup_end_flag1 <= 0;
startup_end_flag2 <= 0;
startup_end_flag3 <= 0;
end
else begin
st_state0i = st_state0;
cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0,
st_state0i, nx_st_state0,lock_cycle_reg0);
st_state1i = st_state1;
cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1,
st_state1i, nx_st_state1,lock_cycle_reg1);
st_state2i = st_state2;
cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2,
st_state2i, nx_st_state2,lock_cycle_reg2);
st_state3i = st_state3;
cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3,
st_state3i, nx_st_state3,lock_cycle_reg3);
end
task cur_st_tsk;
output stup_bflag;
output stup_eflag;
output [2:0] cst_o;
input [2:0] cst_in;
input [2:0] nst_in;
input [2:0] lock_cycle_in;
begin
if (nst_in == STARTUP_PH1) begin
stup_bflag = 1;
stup_eflag = 0;
end
else if (cst_in == STARTUP_PH7) begin
stup_eflag = 1;
stup_bflag = 0;
end
if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin
cst_o = nst_in;
end
else
cst_o = cst_in;
end
endtask
always @(st_state0 or startup_set_pulse0 or DONE ) begin
nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0);
end
always @(st_state1 or startup_set_pulse1 or DONE ) begin
nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1);
end
always @(st_state2 or startup_set_pulse2 or DONE ) begin
nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2);
end
always @(st_state3 or startup_set_pulse3 or DONE ) begin
nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3);
end
task nx_st_tsk;
output [2:0] nx_st;
input [2:0] cur_st;
input [1:0] stup_pulse;
input [2:0] done_cycle_in;
begin
if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in))
case (cur_st)
STARTUP_PH0 : if (stup_pulse == 2'b11 )
nx_st = STARTUP_PH1;
else
nx_st = STARTUP_PH0;
STARTUP_PH1 : nx_st = STARTUP_PH2;
STARTUP_PH2 : nx_st = STARTUP_PH3;
STARTUP_PH3 : nx_st = STARTUP_PH4;
STARTUP_PH4 : nx_st = STARTUP_PH5;
STARTUP_PH5 : nx_st = STARTUP_PH6;
STARTUP_PH6 : nx_st = STARTUP_PH7;
STARTUP_PH7 : nx_st = STARTUP_PH0;
endcase
end
endtask
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0) begin
gwe_out <= 4'b0;
gts_out <= 4'b1111;
eos_startup <= 4'b0;
gsr_st_out <= 4'b1111;
done_o <= 4'b0;
end
else begin
if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin
if (DONE !== 0 || done_pin_drv[0] === 1)
done_o[0] <= 1'b1;
else
done_o[0] <= 1'bz;
end
if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin
if (DONE !== 0 || done_pin_drv[1] == 1)
done_o[1] <= 1'b1;
else
done_o[1] <= 1'bz;
end
if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin
if (DONE !== 0 || done_pin_drv[2] == 1)
done_o[2] <= 1'b1;
else
done_o[2] <= 1'bz;
end
if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin
if (DONE !== 0 || done_pin_drv[3] == 1)
done_o[3] <= 1'b1;
else
done_o[3] <= 1'bz;
end
if (st_state0 == gwe_cycle_reg0)
gwe_out[0] <= 1;
if (st_state1 == gwe_cycle_reg1)
gwe_out[1] <= 1;
if (st_state2 == gwe_cycle_reg2)
gwe_out[2] <= 1;
if (st_state3 == gwe_cycle_reg3)
gwe_out[3] <= 1;
if (st_state0 == gts_cycle_reg0 )
gts_out[0] <= 0;
if (st_state1 == gts_cycle_reg1 )
gts_out[1] <= 0;
if (st_state2 == gts_cycle_reg2 )
gts_out[2] <= 0;
if (st_state3 == gts_cycle_reg3 )
gts_out[3] <= 0;
if (st_state0 == STARTUP_PH6 )
gsr_st_out[0] <= 0;
if (st_state1 == STARTUP_PH6 )
gsr_st_out[1] <= 0;
if (st_state2 == STARTUP_PH6 )
gsr_st_out[2] <= 0;
if (st_state3 == STARTUP_PH6 )
gsr_st_out[3] <= 0;
if (st_state0 == STARTUP_PH7 )
eos_startup[0] <= 1;
if (st_state1 == STARTUP_PH7 )
eos_startup[1] <= 1;
if (st_state2 == STARTUP_PH7 )
eos_startup[2] <= 1;
if (st_state3 == STARTUP_PH7 )
eos_startup[3] <= 1;
end
assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0];
assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1];
assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2];
assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3];
assign abort_dis_bi = abort_dis[ib];
always @(posedge cclk_in or negedge rst_intl or
posedge abort_flag_rst or posedge csi_b_in)
if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin
abort_flag[ib] <= 0;
checka_en <= 0;
rdwr_b_in1 <= rdwr_b_in;
end
else begin
if ( abort_dis_bi == 0 && csi_b_in == 0) begin
if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin
abort_flag[ib] <= 1;
if (icap_on == 0)
$display(" Warning : RDWRB changes when CSB low, which causes Configuration abort on SIM_CONFIGE2 instance %m at time %t.", $time);
end
end
else
abort_flag[ib] <= 0;
rdwr_b_in1 <= rdwr_b_in;
checka_en <= 1;
end
always @(posedge abort_flag[ib])
begin
abort_out_en <= 1;
abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in) begin
abort_out_en <= 0;
abort_flag_rst <= 1;
end
@(posedge cclk_in)
abort_flag_rst <= 0;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
task rdbk_byte;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:8] <= 24'b0;
if (rd_dcnt==1)
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
else if (rd_dcnt==2)
outbus[7:0] <= bit_revers8(rdbk_reg[15:8]);
else if (rd_dcnt==3)
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
else if (rd_dcnt==4)
outbus[7:0] <= bit_revers8(rdbk_reg[31:24]);
end
endtask
task rdbk_wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:16] <= 16'b0;
if (rd_dcnt==1)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==2)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==3) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
end
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
outbus[15:8] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
task rdbk_2wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
if (rd_dcnt==1)
outbus <= 32'b0;
else if (rd_dcnt==2)
outbus <= 32'b0;
else if (rd_dcnt==3)
outbus <= 32'b0;
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
outbus[23:16] <= bit_revers8(rdbk_reg[23:16]);
outbus[31:24] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SIM_CONFIGE3.v 0000664 0000000 0000000 00000241135 12327044266 0023275 0 ustar 00root root 0000000 0000000 //////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.5
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Configuration Simulation Model
// /___/ /\ Filename : SIM_CONFIGE3.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 10/31/12 - Initial version
// 09/09/13 - Fixed output IDCODE (CR 727695).
// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079).
// End Revision
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module SIM_CONFIGE3 (
AVAIL,
CSOB,
PRDONE,
PRERROR,
DONE,
CCLK,
CSB,
D,
INITB,
M,
PROGB,
RDWRB
);
output AVAIL;
output CSOB;
output PRDONE;
output PRERROR;
inout DONE;
input CCLK;
input CSB;
inout [31:0] D;
inout INITB;
input [2:0] M;
input PROGB;
input RDWRB;
parameter DEVICE_ID = 32'h0;
parameter ICAP_SUPPORT = "FALSE";
parameter ICAP_WIDTH = "X8";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt";
localparam cfg_Tprog = 250000; // min PROG must be low
localparam cfg_Tpl = 100000; // max program latency us.
localparam STARTUP_PH0 = 3'b000;
localparam STARTUP_PH1 = 3'b001;
localparam STARTUP_PH2 = 3'b010;
localparam STARTUP_PH3 = 3'b011;
localparam STARTUP_PH4 = 3'b100;
localparam STARTUP_PH5 = 3'b101;
localparam STARTUP_PH6 = 3'b110;
localparam STARTUP_PH7 = 3'b111;
// tri0 GSR, GTS, GWE;
wire GSR;
wire GTS;
wire GWE;
wire cclk_in;
wire init_b_in;
wire prog_b_in;
wire rdwr_b_in;
reg rdwr_b_in1;
reg checka_en = 0;
reg init_b_out = 1;
reg [3:0] done_o = 4'b0;
integer frame_data_fd;
integer farn = 0;
integer ib, ib_skp, ci, bi;
reg frame_data_wen = 0;
tri1 p_up;
reg por_b;
wire [2:0] m_in;
wire [31:0] d_in;
wire [31:0] d_out;
wire busy_out;
wire cso_b_out;
wire csi_b_in;
reg csi_b_ins = 1;
wire d_out_en;
wire pll_locked;
reg pll_lockwt;
wire init_b_t;
wire prog_b_t;
wire bus_en;
wire [3:0] desync_flag;
wire [3:0] crc_rst;
reg [3:0] crc_bypass = 0;
reg icap_on = 0;
reg icap_clr = 0;
reg icap_sync = 0;
reg icap_desynch = 0;
reg rd_desynch = 0;
reg rd_desynch_tmp = 0;
reg icap_init_done = 0;
reg icap_init_done_dly = 0;
wire [3:0] desynch_set1;
reg [1:0] icap_bw = 2'b00;
assign DONE = p_up;
assign INITB = p_up;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
assign glbl.PROGB_GLBL = PROGB;
assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1;
buf buf_cso (CSOB, cso_b_out);
buf buf_cclk (cclk_in, CCLK);
buf buf_cs (csi_b_in, CSB);
buf buf_din[31:0] (d_in, D);
bufif1 buf_dout[31:0] (D, d_out, d_out_en);
buf buf_init (init_b_in, INITB);
buf buf_m_0 (m_in[0], M[0]);
buf buf_m_1 (m_in[1], M[1]);
buf buf_m_2 (m_in[2], M[2]);
buf buf_prog (prog_b_in, PROGB);
buf buf_rw (rdwr_b_in, RDWRB);
time prog_pulse_low_edge = 0;
time prog_pulse_low = 0;
reg mode_sample_flag = 0;
reg [3:0] buswid_flag_init = 4'b0;
reg [3:0] buswid_flag = 4'b0;
reg [1:0] buswidth[3:0];
wire [1:0] buswidth_ibtmp;
reg [1:0] buswidth_tmp[3:0];
reg [31:0] pack_in_reg[3:0];
reg [31:0] pack_in_reg_tmp0 = 32'b0;
reg [31:0] pack_in_reg_tmps0 = 32'b0;
reg [31:0] pack_in_reg_tmp = 32'b0;
reg [4:0] reg_addr[3:0];
reg [4:0] reg_addr_tmp;
reg [3:0] new_data_in_flag = 4'b0;
reg [3:0] wr_flag = 4'b0;
reg [3:0] rd_flag = 4'b0;
reg [3:0] cmd_wr_flag = 4'b0;
reg [3:0] cmd_reg_new_flag = 4'b0;
reg [3:0] cmd_rd_flag = 4'b0;
reg [3:0] bus_sync_flag = 4'b0;
reg [3:0] conti_data_flag = 4'b0;
integer wr_cnt[3:0];
integer conti_data_cnt[3:0];
integer rd_data_cnt[3:0];
integer abort_cnt;
reg [2:0] st_state0 = STARTUP_PH0;
reg [2:0] st_state1 = STARTUP_PH0;
reg [2:0] st_state2 = STARTUP_PH0;
reg [2:0] st_state3 = STARTUP_PH0;
reg [2:0] st_state0i = STARTUP_PH0;
reg [2:0] st_state1i = STARTUP_PH0;
reg [2:0] st_state2i = STARTUP_PH0;
reg [2:0] st_state3i = STARTUP_PH0;
reg startup_begin_flag0 = 0;
reg startup_end_flag0 = 0;
reg startup_begin_flag1 = 0;
reg startup_end_flag1 = 0;
reg startup_begin_flag2 = 0;
reg startup_end_flag2 = 0;
reg startup_begin_flag3 = 0;
reg startup_end_flag3 = 0;
reg [3:0] crc_ck = 4'b0;
reg [3:0] crc_ck_en = 4'b1111;
reg [3:0] crc_err_flag = 4'b0;
wire [3:0] crc_err_flag_tot;
reg [3:0] crc_err_flag_reg = 4'b0;
wire [3:0] crc_en;
reg [31:0] crc_curr[3:0];
reg [31:0] crc_curr_tmp;
wire [31:0] crc_curr_cktmp;
reg [31:0] crc_new;
reg [36:0] crc_input;
reg [31:0] rbcrc_curr[3:0];
reg [31:0] rbcrc_new;
reg [36:0] rbcrc_input;
reg [3:0] gwe_out = 4'b0;
reg [3:0] gts_out = 4'b1111;
reg [31:0] d_o = 32'h0;
reg [31:0] outbus = 32'h0;
reg [31:0] outbus_dly = 32'h0;
reg [31:0] outbus_dly1 = 32'h0;
reg busy_o = 0;
reg [31:0] tmp_val1;
reg [31:0] tmp_val2;
reg [31:0] crc_reg[3:0];
reg [31:0] crc_reg_tmp;
wire [31:0] crc_reg_cktmp;
reg [31:0] far_reg[3:0];
reg [31:0] far_addr;
reg [31:0] fdri_reg[3:0];
reg [31:0] fdro_reg[3:0];
reg [4:0] cmd_reg[3:0];
reg [31:0] ctl0_reg[3:0];
reg [31:0] mask_reg[3:0];
wire [31:0] stat_reg[3:0];
wire [31:0] stat_reg_tmp0;
wire [31:0] stat_reg_tmp1;
wire [31:0] stat_reg_tmp2;
wire [31:0] stat_reg_tmp3;
reg [31:0] lout_reg[3:0];
reg [31:0] cor0_reg[3:0];
reg [31:0] cor0_reg_tmp0 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp1 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp2 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp3 = 32'b00000000000000000011111111101100;
reg [31:0] mfwr_reg[3:0];
reg [31:0] cbc_reg[3:0];
reg [31:0] idcode_reg[3:0];
reg [31:0] axss_reg[3:0];
reg [31:0] cor1_reg[3:0];
reg [31:0] cor1_reg_tmp0 = 32'b0;
reg [31:0] cor1_reg_tmp1 = 32'b0;
reg [31:0] cor1_reg_tmp2 = 32'b0;
reg [31:0] cor1_reg_tmp3 = 32'b0;
reg [31:0] csob_reg[3:0];
reg [31:0] wbstar_reg[3:0];
reg [31:0] timer_reg[3:0];
reg [31:0] rbcrc_hw_reg[3:0];
reg [31:0] rbcrc_sw_reg[3:0];
reg [31:0] rbcrc_live_reg[3:0];
reg [31:0] efar_reg[3:0];
reg [31:0] bootsts_reg[3:0];
reg [31:0] ctl1_reg[3:0];
reg [31:0] testmode_reg[3:0];
reg [31:0] memrd_param_reg[3:0];
reg [31:0] dwc_reg[3:0];
reg [31:0] trim_reg[3:0];
reg [31:0] bout_reg[3:0];
reg [31:0] bspi_reg[3:0];
reg [2:0] mode_pin_in = 3'b0;
reg [2:0] mode_reg;
reg [3:0] crc_reset = 4'b0;
reg [3:0] gsr_set = 4'b0;
reg [3:0] gts_usr_b = 4'b111;
reg [3:0] done_pin_drv = 4'b0;
reg [3:0] shutdown_set = 4'b0;
reg [3:0] desynch_set = 4'b0;
reg [2:0] done_cycle_reg0 = 3'b011;
reg [2:0] done_cycle_reg1 = 3'b011;
reg [2:0] done_cycle_reg2 = 3'b011;
reg [2:0] done_cycle_reg3 = 3'b011;
reg [2:0] gts_cycle_reg0 = 3'b101;
reg [2:0] gts_cycle_reg1 = 3'b101;
reg [2:0] gts_cycle_reg2 = 3'b101;
reg [2:0] gts_cycle_reg3 = 3'b101;
reg [2:0] gwe_cycle_reg0 = 3'b100;
reg [2:0] gwe_cycle_reg1 = 3'b100;
reg [2:0] gwe_cycle_reg2 = 3'b100;
reg [2:0] gwe_cycle_reg3 = 3'b100;
reg init_pin;
reg init_rst = 0;
reg [2:0] nx_st_state0 = 3'b0;
reg [2:0] nx_st_state1 = 3'b0;
reg [2:0] nx_st_state2 = 3'b0;
reg [2:0] nx_st_state3 = 3'b0;
reg [3:0] ghigh_b = 4'b0;
reg [3:0] gts_cfg_b = 4'b0;
reg [3:0] eos_startup = 4'b0;
reg [3:0] startup_set = 4'b0;
reg [1:0] startup_set_pulse0 = 2'b0;
reg [1:0] startup_set_pulse1 = 2'b0;
reg [1:0] startup_set_pulse2 = 2'b0;
reg [1:0] startup_set_pulse3 = 2'b0;
reg abort_out_en = 0;
reg [31:0] tmp_dword;
reg [15:0] tmp_word;
reg [7:0] tmp_byte;
reg [3:0] id_error_flag = 4'b0;
wire id_error_flag_t;
reg [3:0] iprog_b = 4'b1111;
wire iprog_b_t;
reg [3:0] i_init_b_cmd = 4'b1111;
wire i_init_b_cmd_t;
reg i_init_b = 0;
reg [7:0] abort_status = 8'b0;
reg [3:0] persist_en = 0;
reg [3:0] rst_sync = 0;
reg [3:0] abort_dis = 0;
reg [2:0] lock_cycle_reg0 = 3'b0;
reg [2:0] lock_cycle_reg1 = 3'b0;
reg [2:0] lock_cycle_reg2 = 3'b0;
reg [2:0] lock_cycle_reg3 = 3'b0;
reg [3:0] rbcrc_no_pin = 4'b0;
reg abort_flag_rst = 0;
reg [3:0] gsr_st_out = 4'b1111;
reg [3:0] gsr_cmd_out = 4'b0;
reg [3:0] gsr_cmd_out_pulse = 4'b0;
reg d_o_en = 0;
wire rst_intl;
wire rw_en_tmp1;
wire [3:0] rw_en;
wire [3:0] gsr_out;
wire [3:0] cfgerr_b_flag;
reg [3:0] abort_flag = 4'b0;
integer downcont_cnt = 0;
reg rst_en = 0;
reg prog_b_a = 1;
reg [3:0] csbo_flag = 4'b0;
reg [3:0] bout_flag = 4'b0;
reg [3:0] bout_flags = 4'b0;
reg [3:0] bout_bf = 4'b0;
reg [3:0] bout_en = 4'b0001;
reg rd_sw_en = 0;
integer csbo_cnt[3:0];
integer bout_cnt[3:0];
integer bout_cnt_tmp;
reg [4:0] rd_reg_addr[3:0];
reg done_release = 0;
triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out;
triand (weak1, strong0) DONE= done_o[0];
assign DONE= (bout_en[1] == 1) ? done_o[1] : p_up;
assign DONE= (bout_en[2] == 1) ? done_o[2] : p_up;
assign DONE= (bout_en[3] == 1) ? done_o[3] : p_up;
reg PRDONE = 0;
reg fdri_rst_prdone_flag = 0;
always @(fdri_rst_prdone_flag)
PRDONE = 1'b0;
always @(desync_flag or eos_startup)
if ((&desync_flag) & (&eos_startup)) begin
PRDONE = 1'b1;
end
assign PRERROR = (|rw_en) & (|crc_err_flag_tot);
initial begin
if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093")
bout_en = 4'b0011;
else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093")
bout_en = 4'b0111;
else if (DEVICE_ID == "036A6093")
bout_en = 4'b1111;
end
initial begin
buswidth_tmp[0] = 2'b00;
buswidth_tmp[1] = 2'b00;
buswidth_tmp[2] = 2'b00;
buswidth_tmp[3] = 2'b00;
pack_in_reg[0] = 32'b0;
pack_in_reg[1] = 32'b0;
pack_in_reg[2] = 32'b0;
pack_in_reg[3] = 32'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
pack_in_reg_tmp = 32'b0;
crc_curr[0] = 32'b0;
crc_curr[1] = 32'b0;
crc_curr[2] = 32'b0;
crc_curr[3] = 32'b0;
rbcrc_curr[0] = 32'b0;
rbcrc_curr[1] = 32'b0;
rbcrc_curr[2] = 32'b0;
rbcrc_curr[3] = 32'b0;
ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
cor0_reg[0] = 32'b00000000000000000011111111101100;
cor0_reg[1] = 32'b00000000000000000011111111101100;
cor0_reg[2] = 32'b00000000000000000011111111101100;
cor0_reg[3] = 32'b00000000000000000011111111101100;
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
done_cycle_reg1 = cor0_reg_tmp0[14:12];
lock_cycle_reg1 = cor0_reg_tmp0[8:6];
done_cycle_reg2 = cor0_reg_tmp0[14:12];
lock_cycle_reg2 = cor0_reg_tmp0[8:6];
done_cycle_reg3 = cor0_reg_tmp0[14:12];
lock_cycle_reg3 = cor0_reg_tmp0[8:6];
cor1_reg[0] = 32'b0;
cor1_reg[1] = 32'b0;
cor1_reg[2] = 32'b0;
cor1_reg[3] = 32'b0;
wbstar_reg[0] = 32'b0;
wbstar_reg[1] = 32'b0;
wbstar_reg[2] = 32'b0;
wbstar_reg[3] = 32'b0;
timer_reg[0] = 32'b0;
timer_reg[1] = 32'b0;
timer_reg[2] = 32'b0;
timer_reg[3] = 32'b0;
bootsts_reg[0] = 32'b0;
bootsts_reg[1] = 32'b0;
bootsts_reg[2] = 32'b0;
bootsts_reg[3] = 32'b0;
ctl1_reg[0] = 32'b0;
ctl1_reg[1] = 32'b0;
ctl1_reg[2] = 32'b0;
ctl1_reg[3] = 32'b0;
testmode_reg[0] = 32'b0;
testmode_reg[1] = 32'b0;
testmode_reg[2] = 32'b0;
testmode_reg[3] = 32'b0;
memrd_param_reg[0] = 32'b0;
memrd_param_reg[1] = 32'b0;
memrd_param_reg[2] = 32'b0;
memrd_param_reg[3] = 32'b0;
dwc_reg[0] = 32'b0;
dwc_reg[1] = 32'b0;
dwc_reg[2] = 32'b0;
dwc_reg[3] = 32'b0;
trim_reg[0] = 32'b0;
trim_reg[1] = 32'b0;
trim_reg[2] = 32'b0;
trim_reg[3] = 32'b0;
bout_reg[0] = 32'b0;
bout_reg[1] = 32'b0;
bout_reg[2] = 32'b0;
bout_reg[3] = 32'b0;
bspi_reg[0] = 32'h000B;
bspi_reg[1] = 32'h000B;
bspi_reg[2] = 32'h000B;
bspi_reg[3] = 32'h000B;
rd_reg_addr[0] = 5'b0;
rd_reg_addr[1] = 5'b0;
rd_reg_addr[2] = 5'b0;
rd_reg_addr[3] = 5'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
bout_cnt[0] = 0;
bout_cnt[1] = 0;
bout_cnt[2] = 0;
bout_cnt[3] = 0;
done_o = 4'b0;
end
initial begin
case (ICAP_SUPPORT)
"FALSE" : icap_on = 0;
"TRUE" : icap_on = 1;
default : icap_on = 0;
endcase
if (DEVICE_ID == 32'h0 && icap_on == 0) begin
$display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIGE3 instance %m is not set.");
end
if (ICAP_SUPPORT == "TRUE") begin
case (ICAP_WIDTH)
"X8" : icap_bw = 2'b01;
"X16" : icap_bw = 2'b10;
"X32" : icap_bw = 2'b11;
default : icap_bw = 2'b01;
endcase
frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w");
if (frame_data_fd != 0) begin
frame_data_wen = 1;
$fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n");
end
end
else begin
icap_bw = 2'b00;
frame_data_wen = 0;
end
icap_sync = 0;
end
assign GSR = gsr_out[0];
assign GTS = gts_out[0];
assign GWE = gwe_out[0];
assign busy_out = busy_o;
assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0];
assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1];
assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2];
assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3];
assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0];
assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1];
assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2];
assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3];
assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0];
assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8];
assign d_out_en = d_o_en;
assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1;
assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111;
always @(posedge cclk_in) begin
outbus_dly <= outbus_dly1;
outbus_dly1 <= outbus;
end
always @(posedge cclk_in or csi_b_in)
if (csi_b_in == 1)
csi_b_ins <= csi_b_in;
else begin
if (cclk_in != 1)
csi_b_ins <= csi_b_in;
else
@(negedge cclk_in)
csi_b_ins <= csi_b_in;
end
always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] )
if (abort_out_en == 1)
d_o_en = 1;
else
d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib];
assign init_b_t = init_b_in & i_init_b_cmd_t;
always @( negedge prog_b_in) begin
rst_en = 0;
rst_en <= #cfg_Tprog 1;
end
assign iprog_b_0 = iprog_b[0];
assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1;
assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1;
assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1;
assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0;
assign i_init_b_cmd_0 = i_init_b_cmd[0];
assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1;
assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1;
assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1;
assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2
& i_init_b_cmd_3;
always @( rst_en or init_rst or prog_b_in or iprog_b_t )
if (icap_on == 0) begin
if (init_rst == 1)
init_b_out <= 0;
else begin
if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0))
init_b_out <= 0;
else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1))
init_b_out <= #(cfg_Tpl) 1;
end
end
assign id_error_flag_t = &id_error_flag;
always @(posedge id_error_flag_t) begin
init_rst <= 1;
init_rst <= #cfg_Tprog 0;
end
always @( rst_en or prog_b_in or prog_pulse_low)
if (rst_en == 1) begin
if (prog_pulse_low==cfg_Tprog) begin
prog_b_a = 0;
prog_b_a <= #500 1;
end
else
prog_b_a = prog_b_in;
end
else
prog_b_a = 1;
initial begin
por_b = 0;
por_b = #400000 1;
end
assign prog_b_t = prog_b_a & iprog_b_t & por_b;
assign rst_intl = (prog_b_t==0 ) ? 0 : 1;
always @( init_b_t or prog_b_t)
if (prog_b_t == 0)
mode_sample_flag <= 0;
else if (init_b_t && mode_sample_flag == 0) begin
if (prog_b_t == 1) begin
mode_pin_in <= m_in;
if (m_in !== 3'b110) begin
mode_sample_flag <= 0;
if ( icap_on == 0)
$display("Error: input M is %h. Only Slave SelectMAP mode M=110 supported on SIM_CONFIGE3 instance %m.", m_in);
end
else
mode_sample_flag <= #1 1;
end
end
always @(posedge init_b_t )
if (prog_b_t != 1) begin
if ($time != 0 && icap_on == 0)
$display("Error: PROGB is not high when INITB goes high on SIM_CONFIGE3 instance %m at time %t.", $time);
end
always @(m_in)
if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0)
$display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIGE3 instance %m at time %t.", $time);
always @(posedge prog_b_in or negedge prog_b_in)
if (prog_b_in == 0)
prog_pulse_low_edge <= $time;
else if (prog_b_in == 1 && $time > 0) begin
prog_pulse_low = $time - prog_pulse_low_edge;
if (prog_pulse_low < cfg_Tprog && icap_on == 0)
$display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIGE3 instance %m at time %t.", cfg_Tprog, $time);
end
assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0;
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0 ) begin
buswid_flag_init <= 4'b0;
buswid_flag <= 4'b0;
buswidth_tmp[0] <= 2'b00;
buswidth_tmp[1] <= 2'b00;
buswidth_tmp[2] <= 2'b00;
buswidth_tmp[3] <= 2'b00;
end
else
if (buswid_flag[ib] == 0) begin
if (bus_en == 1 && rdwr_b_in == 0) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (buswid_flag_init[ib] == 0) begin
if (tmp_byte == 8'hBB)
buswid_flag_init[ib] <= 1;
end
else begin
if (tmp_byte == 8'h11) begin // x8
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b01;
end
else if (tmp_byte == 8'h22) begin // x16
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b10;
end
else if (tmp_byte == 8'h44) begin // x32
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b11;
end
else begin
buswid_flag[ib] <= 0;
buswidth_tmp[ib] <= 2'b00;
buswid_flag_init[ib] <= 0;
if (icap_on == 0)
$display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB on SIM_CONFIGE3 instance %m at time %t.", $time);
else
$display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE3 instance %m at time %t.", $time);
end
end
end
end
assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib];
always @(buswidth_ibtmp)
buswidth[ib] = buswidth_ibtmp;
assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0;
assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0;
assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0;
assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0;
assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0;
assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch;
assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch;
assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch;
assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch;
assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0];
assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1];
assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2];
assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3];
always @(posedge eos_startup[0])
if (icap_on == 1) begin
$fclose(frame_data_fd);
icap_init_done <= 1;
@(posedge cclk_in);
@(posedge cclk_in)
if (icap_init_done_dly == 0)
icap_desynch <= 1;
@(posedge cclk_in);
@(posedge cclk_in) begin
icap_desynch <= 0;
icap_init_done_dly <= 1;
end
@(posedge cclk_in);
@(posedge cclk_in);
@(posedge cclk_in);
end
else begin
icap_clr <= 0;
icap_desynch <= 0;
end
always @(posedge cclk_in or negedge rdwr_b_in)
if (rdwr_b_in == 0)
rd_sw_en <= 0;
else begin
if (csi_b_in == 1 && rdwr_b_in ==1)
rd_sw_en <= 1;
end
assign desync_flag_t = |desync_flag;
always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin
if (desync_flag[ib] == 1) begin
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
if (desync_flag[0] == 1 ) begin
new_data_in_flag[0] = 0;
bus_sync_flag[0] = 0;
wr_cnt[0] = 0;
wr_flag[0] = 0;
rd_flag[0] = 0;
end
if (desync_flag[1] == 1 ) begin
new_data_in_flag[1] = 0;
bus_sync_flag[1] = 0;
wr_cnt[1] = 0;
wr_flag[1] = 0;
rd_flag[1] = 0;
end
if (desync_flag[2] == 1 ) begin
new_data_in_flag[2] = 0;
bus_sync_flag[2] = 0;
wr_cnt[2] = 0;
wr_flag[2] = 0;
rd_flag[2] = 0;
end
if (desync_flag[3] == 1 ) begin
new_data_in_flag[3] = 0;
bus_sync_flag[3] = 0;
wr_cnt[3] = 0;
wr_flag[3] = 0;
rd_flag[3] = 0;
end
if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin
new_data_in_flag = 4'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else begin
if (icap_clr == 1) begin
new_data_in_flag <= 4'b0;
wr_cnt[0] <= 0;
wr_cnt[1] <= 0;
wr_cnt[2] <= 0;
wr_cnt[3] <= 0;
wr_flag <= 4'b0;
rd_flag <= 4'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin
if (rdwr_b_in == 0) begin
wr_flag[ib] <= 1;
rd_flag[ib] <= 0;
if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99
&& pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16];
pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8];
pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
end
end
else begin
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[31:24] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[23:16] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 2;
end
else if (wr_cnt[ib] == 2) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[15:8] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 3;
end
else if (wr_cnt[ib] == 3) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b10) begin
tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])};
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin
wr_cnt[ib] <= 0;
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0];
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0[31:16] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b11 ) begin
tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]),
bit_revers8(d_in[7:0])};
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
if (bus_sync_flag[ib] == 0) begin
if (tmp_dword == 32'hAA995566) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
new_data_in_flag[ib] <= 1;
end
end
end
else begin
wr_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
if (rd_sw_en ==1)
rd_flag[ib] <= 1;
end
end
else begin
wr_flag[ib] <= 0;
rd_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
end
end
end
always @(pack_in_reg_tmps0 or desync_flag or icap_clr)
begin
if (desync_flag[0] == 1 || icap_clr == 1)
pack_in_reg[0] = 32'b0;
if (desync_flag[1] == 1 || icap_clr == 1)
pack_in_reg[1] = 32'b0;
if (desync_flag[2] == 1 || icap_clr == 1)
pack_in_reg[2] = 32'b0;
if (desync_flag[3] == 1 || icap_clr == 1)
pack_in_reg[3] = 32'b0;
if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin
pack_in_reg[0] = pack_in_reg_tmps0;
end
else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0)
pack_in_reg[1] = pack_in_reg_tmps0;
else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0)
pack_in_reg[2] = pack_in_reg_tmps0;
else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0)
pack_in_reg[3] = pack_in_reg_tmps0;
end
task rst_pack_dec;
input ib_d;
begin
conti_data_flag[ib_d] <= 0;
conti_data_cnt[ib_d] <= 0;
cmd_wr_flag[ib_d] <= 0;
cmd_rd_flag[ib_d] <= 0;
id_error_flag[ib_d] <= 0;
crc_curr[ib_d] <= 32'b0;
crc_ck[ib_d] <= 0;
csbo_cnt[ib_d] <= 0;
csbo_flag[ib_d] <= 0;
downcont_cnt <= 0;
rd_data_cnt[ib_d] <= 0;
end
endtask
always @(negedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
else begin
if (icap_clr == 1) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
if (crc_reset[ib] == 1 ) begin
crc_reg[ib] <= 32'b0;
crc_ck[ib] <= 0;
crc_curr[ib] <= 32'b0;
end
if (crc_ck[ib] == 1) begin
crc_curr[ib] <= 32'b0;
crc_ck[ib] <= 0;
end
if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin
bout_flag[0] <= 0;
bout_cnt[0] <= 0;
rst_pack_dec(0);
end
if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin
bout_flag[1] <= 0;
bout_cnt[1] <= 0;
rst_pack_dec(1);
end
if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin
bout_flag[2] <= 0;
bout_cnt[2] <= 0;
rst_pack_dec(2);
end
if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin
bout_flag[3] <= 0;
bout_cnt[3] <= 0;
rst_pack_dec(3);
end
if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0
&& desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin
pack_in_reg_tmp = pack_in_reg[ib];
if (conti_data_flag[ib] == 1 ) begin
reg_addr_tmp = reg_addr[ib];
case (reg_addr_tmp)
5'b00000 : begin
crc_reg[ib] <= pack_in_reg[ib];
crc_reg_tmp <= pack_in_reg[ib];
crc_ck[ib] <= 1;
end
5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]};
// 5'b00010 : fdri_reg[ib] <= pack_in_reg[ib];
5'b00010 : begin
fdri_reg[ib] <= pack_in_reg[ib];
fdri_rst_prdone_flag <= ~fdri_rst_prdone_flag;
end
5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0];
5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]);
5'b00110 : mask_reg[ib] <= pack_in_reg[ib];
5'b01000 : lout_reg[ib] <= pack_in_reg[ib];
5'b01001 : cor0_reg[ib] <= pack_in_reg[ib];
5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib];
5'b01011 : cbc_reg[ib] <= pack_in_reg[ib];
5'b01100 : begin
idcode_reg[ib] <= pack_in_reg[ib];
if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin
id_error_flag[ib] <= 1;
if (icap_on == 0)
$display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIGE3 instance %m at time %t.", pack_in_reg[ib], DEVICE_ID, $time);
else
$display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on ICAPE3 instance %m at time %t.", pack_in_reg[ib], DEVICE_ID, $time);
end
else
id_error_flag[ib] <= 0;
end
5'b01101 : axss_reg[ib] <= pack_in_reg[ib];
5'b01110 : cor1_reg[ib] <= pack_in_reg[ib];
5'b01111 : csob_reg[ib] <= pack_in_reg[ib];
5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib];
5'b10001 : timer_reg[ib] <= pack_in_reg[ib];
5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib];
5'b10111 : testmode_reg[ib] <= pack_in_reg[ib];
5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]);
5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11011 : trim_reg[ib] <= pack_in_reg[ib];
5'b11110 : bout_reg[ib] <= pack_in_reg[ib];
5'b11111 : bspi_reg[ib] <= pack_in_reg[ib];
endcase
if (reg_addr[ib] != 5'b00000)
crc_ck[ib] <= 0;
if (reg_addr_tmp == 5'b00100)
cmd_reg_new_flag[ib] <= 1;
else
cmd_reg_new_flag[ib] <= 0;
if (crc_en[ib] == 1) begin
if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111)
crc_curr[ib] = 32'b0;
else begin
if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14
&& reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin
crc_input = {reg_addr[ib], pack_in_reg_tmp};
crc_curr_tmp = crc_curr[ib];
crc_new = bcc_next(crc_curr_tmp, crc_input);
crc_curr[ib] <= crc_new;
end
end
end
if (conti_data_cnt[ib] <= 1) begin
conti_data_cnt[ib] <= 0;
end
else
conti_data_cnt[ib] <= conti_data_cnt[ib] - 1;
end
else if (conti_data_flag[ib] == 0 ) begin
if ( downcont_cnt >= 1) begin
if (crc_en[ib] == 1) begin
crc_input[36:0] = {5'b00010, pack_in_reg[ib]};
crc_new = bcc_next(crc_curr[ib], crc_input);
crc_curr[ib] <= crc_new;
end
if (ib == 0) begin
if (farn <= 80)
farn <= farn + 1;
else begin
far_addr <= far_addr + 1;
farn <= 0;
end
if (frame_data_wen == 1 && icap_init_done == 0) begin
rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]};
rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input);
rbcrc_curr[ib] <= rbcrc_new;
$fwriteh(frame_data_fd, far_addr);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, pack_in_reg[ib]);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, rbcrc_new);
$fwriteh(frame_data_fd, "\n");
end
end
end
if (pack_in_reg_tmp[31:29] == 3'b010 ) begin
bout_cnt_tmp = bout_cnt[ib];
if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
downcont_cnt <= pack_in_reg_tmp[26:0];
far_addr <= far_reg[ib];
end
else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
bout_flag[ib] <= 1;
bout_cnt[ib] <= pack_in_reg_tmp[26:0];
end
else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
csbo_flag[ib] <= 1;
csbo_cnt[ib] <= pack_in_reg_tmp[26:0];
end
end
else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package
if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[10:0] != 11'b0) begin
cmd_rd_flag[ib] <= 1;
cmd_wr_flag[ib] <= 0;
rd_data_cnt[ib] <= 4;
conti_data_cnt[ib] <= 0;
conti_data_flag[ib] <= 0;
rd_reg_addr[ib] <= pack_in_reg_tmp[17:13];
end
end
else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg
lout_reg[ib] <= pack_in_reg_tmp;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib] <= 5'b0;
end
else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg
bout_reg[ib] <= pack_in_reg_tmp;
bout_flags[ib] <= 1;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib]<= 5'b0;
end
else begin
if (pack_in_reg_tmp[10:0] != 10'b0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 1;
conti_data_cnt[ib] <= pack_in_reg_tmp[10:0];
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
else begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
end
end
else begin
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
end
end
end // if (conti_data_flag == 0 )
if (csbo_cnt[ib] != 0 ) begin
if (csbo_flag[ib] == 1)
csbo_cnt[ib] <= csbo_cnt[ib] - 1;
end
else
csbo_flag[ib] <= 0;
if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin
if (bout_cnt[0] == 1) begin
bout_cnt[0] <= 0;
bout_flag[0] <= 0;
end
else
bout_cnt[0] <= bout_cnt[0] - 1;
end
if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin
if (bout_cnt[1] == 1) begin
bout_cnt[1] <= 0;
bout_flag[1] <= 0;
end
else
bout_cnt[1] <= bout_cnt[1] - 1;
end
if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin
bout_cnt[2] <= bout_cnt[2] - 1;
if (bout_cnt[2] == 1) begin
bout_cnt[2] <= 0;
bout_flag[2] <= 0;
end
else
bout_cnt[2] <= bout_cnt[2] - 1;
end
if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin
if (bout_cnt[3] == 1) begin
bout_cnt[3] <= 0;
bout_flag[3] <= 0;
end
else
bout_cnt[3] <= bout_cnt[3] - 1;
end
if (conti_data_cnt[ib] == 5'b00001 )
conti_data_flag[ib] <= 0;
if (crc_ck[ib] == 1 || icap_init_done == 1)
crc_ck[ib] <= 0;
end
if (rw_en[ib] == 1 && csi_b_ins == 0) begin
if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= 0;
else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin
cmd_rd_flag[ib] <= 0;
end
else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= rd_data_cnt[ib] - 1;
if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1)
downcont_cnt <= downcont_cnt - 1;
end
if (cmd_reg_new_flag[ib] == 1 )
cmd_reg_new_flag[ib] <= 0;
end
always @(bout_flag)
if (bout_flag[3] == 1) begin
ib = 3;
ib_skp = 1;
end
else if (bout_flag[2] == 1) begin
ib = 3;
ib_skp = 0;
end
else if (bout_flag[1] == 1) begin
ib = 2;
ib_skp = 0;
end
else if (bout_flag[0] == 1) begin
ib = 1;
ib_skp = 0;
end
else begin
ib = 0;
ib_skp = 0;
end
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
outbus <= 32'b0;
end
else begin
if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin
case (rd_reg_addr[ib])
5'b00000 : if (buswidth[ib] == 2'b01)
rdbk_byte(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]);
5'b00001 : if (buswidth[ib] == 2'b01)
rdbk_byte(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(far_reg[ib], rd_data_cnt[ib]);
5'b00011 : if (buswidth[ib] == 2'b01)
rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]);
5'b00100 : if (buswidth[ib] == 2'b01)
rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]);
5'b00101 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]);
5'b00110 : if (buswidth[ib] == 2'b01)
rdbk_byte(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]);
5'b00111 : if (buswidth[ib] == 2'b01)
rdbk_byte(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]);
5'b01001 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]);
5'b01100 : if (buswidth[ib] == 2'b01)
rdbk_byte(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]);
5'b01101 : if (buswidth[ib] == 2'b01)
rdbk_byte(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]);
5'b01110 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]);
5'b10000 : if (buswidth[ib] == 2'b01)
rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]);
5'b10001 : if (buswidth[ib] == 2'b01)
rdbk_byte(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]);
5'b10010 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
5'b10011 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
5'b10100 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
5'b10101 : if (buswidth[ib] == 2'b01)
rdbk_byte(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]);
5'b10110 : if (buswidth[ib] == 2'b01)
rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]);
5'b11000 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]);
5'b11001 : if (buswidth[ib] == 2'b01)
rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]);
5'b11010 : if (buswidth[ib] == 2'b01)
rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]);
5'b11011 : if (buswidth[ib] == 2'b01)
rdbk_byte(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]);
5'b11111 : if (buswidth[ib] == 2'b01)
rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]);
endcase
if (ib != 0) begin
if (rd_data_cnt[ib] == 1)
rd_desynch_tmp <= 1;
end
end
else begin
outbus <= 32'b0;
rd_desynch <= rd_desynch_tmp;
rd_desynch_tmp <= 0;
end
end
assign crc_rst[0] = crc_reset[0] | ~rst_intl;
assign crc_rst[1] = crc_reset[1] | ~rst_intl;
assign crc_rst[2] = crc_reset[2] | ~rst_intl;
assign crc_rst[3] = crc_reset[3] | ~rst_intl;
assign crc_curr_cktmp = crc_curr[0];
assign crc_reg_cktmp = crc_reg[0];
always @(posedge cclk_in or posedge crc_rst[0] )
if (crc_rst[0] == 1) begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
else
if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin
if (crc_curr[0] != crc_reg[0])
crc_err_flag[0] <= 1;
else
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 0;
end
else begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[1] )
if (crc_rst[1] == 1) begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
else
if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin
if (crc_curr[1] != crc_reg[1])
crc_err_flag[1] <= 1;
else
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 0;
end
else begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[2] )
if (crc_rst[2] == 1) begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
else
if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin
if (crc_curr[2] != crc_reg[2])
crc_err_flag[2] <= 1;
else
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 0;
end
else begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[3] )
if (crc_rst[3] == 1) begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
else
if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin
if (crc_curr[3] != crc_reg[3])
crc_err_flag[3] <= 1;
else
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 0;
end
else begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0])
if (rst_intl == 0)
crc_err_flag_reg[0] <= 0;
else if (crc_err_flag[0] == 1)
crc_err_flag_reg[0] <= 1;
else
crc_err_flag_reg[0] <= 0;
always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1])
if (rst_intl == 0)
crc_err_flag_reg[1] <= 0;
else if (crc_err_flag[1] == 1)
crc_err_flag_reg[1] <= 1;
else
crc_err_flag_reg[1] <= 0;
always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2])
if (rst_intl == 0)
crc_err_flag_reg[2] <= 0;
else if (crc_err_flag[2] == 1)
crc_err_flag_reg[2] <= 1;
else
crc_err_flag_reg[2] <= 0;
always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3])
if (rst_intl == 0)
crc_err_flag_reg[3] <= 0;
else if (crc_err_flag[3] == 1)
crc_err_flag_reg[3] <= 1;
else
crc_err_flag_reg[3] <= 0;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
startup_set <= 4'b0;
crc_reset <= 4'b0;
gsr_cmd_out <= 4'b0;
shutdown_set <= 4'b0;
desynch_set <= 4'b0;
ghigh_b <= 4'b0;
end
else
for (ci = 0; ci <=3; ci = ci+1) begin
if (cmd_reg_new_flag[ci] == 1) begin
if (cmd_reg[ci] == 5'b00011)
ghigh_b[ci] <= 1;
else if (cmd_reg[ci] == 5'b01000)
ghigh_b[ci] <= 0;
if (cmd_reg[ci] == 5'b00101)
startup_set[ci] <= 1;
else
startup_set[ci] <= 0;
if (cmd_reg[ci] == 5'b00111)
crc_reset[ci] <= 1;
else
crc_reset[ci] <= 0;
if (cmd_reg[ci] == 5'b01010)
gsr_cmd_out[ci] <= 1;
else
gsr_cmd_out[ci] <= 0;
if (cmd_reg[ci] == 5'b01011)
shutdown_set[ci] <= 1;
else
shutdown_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01101)
desynch_set[ci] <= 1;
else
desynch_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01111) begin
iprog_b[ci] <= 0;
i_init_b_cmd[ci] <= 0;
iprog_b[ci] <= #cfg_Tprog 1;
i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1;
end
end
else begin
startup_set[ci] <= 0;
crc_reset[ci] <= 0;
gsr_cmd_out[ci] <= 0;
shutdown_set[ci] <= 0;
desynch_set[ci] <= 0;
end
end
always @(posedge startup_set[0] or posedge desynch_set[0] or negedge rw_en[0] )
if (rw_en[0] == 1)
begin
if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin
if (icap_on == 0)
startup_set_pulse0 <= 2'b01;
else begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
always @(posedge startup_set[1] or posedge desynch_set[1] or negedge rw_en[1] )
if (rw_en[1] == 1)
begin
if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin
if (icap_on == 0)
startup_set_pulse1 <= 2'b01;
else begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
always @(posedge startup_set[2] or posedge desynch_set[2] or negedge rw_en[2])
if (rw_en[2] == 1)
begin
if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin
if (icap_on == 0)
startup_set_pulse2 <= 2'b01;
else begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
always @(posedge startup_set[3] or posedge desynch_set[3] or negedge rw_en[3])
if (rw_en[3] == 1)
begin
if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin
if (icap_on == 0)
startup_set_pulse3 <= 2'b01;
else begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
always @(posedge gsr_cmd_out[0] or negedge rw_en[0])
if (rw_en[0] == 0)
gsr_cmd_out_pulse[0] <= 0;
else
begin
gsr_cmd_out_pulse[0] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[0] <= 0;
end
always @(posedge gsr_cmd_out[1] or negedge rw_en[1])
if (rw_en[1] == 0)
gsr_cmd_out_pulse[1] <= 0;
else
begin
gsr_cmd_out_pulse[1] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[1] <= 0;
end
always @(posedge gsr_cmd_out[2] or negedge rw_en[2])
if (rw_en[2] == 0)
gsr_cmd_out_pulse[2] <= 0;
else
begin
gsr_cmd_out_pulse[2] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[2] <= 0;
end
always @(posedge gsr_cmd_out[3] or negedge rw_en[3])
if (rw_en[3] == 0)
gsr_cmd_out_pulse[3] <= 0;
else
begin
gsr_cmd_out_pulse[3] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[3] <= 0;
end
reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3;
always @(ctl0_reg[0]) begin
ctl0_reg_tmp0 = ctl0_reg[0];
if (ctl0_reg_tmp0[9] == 1)
abort_dis[0] = 1;
else
abort_dis[0] = 0;
if (ctl0_reg_tmp0[3] == 1)
persist_en[0] = 1;
else
persist_en[0] = 0;
if (ctl0_reg_tmp0[0] == 1)
gts_usr_b[0] = 1;
else
gts_usr_b[0] = 0;
end
always @(ctl0_reg[1]) begin
ctl0_reg_tmp1 = ctl0_reg[1];
if (ctl0_reg_tmp1[9] == 1)
abort_dis[1] = 1;
else
abort_dis[1] = 0;
if (ctl0_reg_tmp1[3] == 1)
persist_en[1] = 1;
else
persist_en[1] = 0;
if (ctl0_reg_tmp1[0] == 1)
gts_usr_b[1] = 1;
else
gts_usr_b[1] = 0;
end
always @(ctl0_reg[2]) begin
ctl0_reg_tmp2 = ctl0_reg[2];
if (ctl0_reg_tmp2[9] == 1)
abort_dis[2] = 1;
else
abort_dis[2] = 0;
if (ctl0_reg_tmp2[3] == 1)
persist_en[2] = 1;
else
persist_en[2] = 0;
if (ctl0_reg_tmp0[2] == 1)
gts_usr_b[2] = 1;
else
gts_usr_b[2] = 0;
end
always @(ctl0_reg[3]) begin
ctl0_reg_tmp3 = ctl0_reg[3];
if (ctl0_reg_tmp3[9] == 1)
abort_dis[3] = 1;
else
abort_dis[3] = 0;
if (ctl0_reg_tmp3[3] == 1)
persist_en[3] = 1;
else
persist_en[3] = 0;
if (ctl0_reg_tmp3[0] == 1)
gts_usr_b[3] = 1;
else
gts_usr_b[3] = 0;
end
always @(cor0_reg[0])
begin
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
gts_cycle_reg0 = cor0_reg_tmp0[5:3];
gwe_cycle_reg0 = cor0_reg_tmp0[2:0];
if (cor0_reg_tmp0[24] == 1'b1)
done_pin_drv[0] = 1;
else
done_pin_drv[0] = 0;
if (cor0_reg_tmp0[28] == 1'b1)
crc_bypass[0] = 1;
else
crc_bypass[0] = 0;
end
always @(cor0_reg[1])
begin
cor0_reg_tmp1 = cor0_reg[1];
done_cycle_reg1 = cor0_reg_tmp1[14:12];
lock_cycle_reg1 = cor0_reg_tmp1[8:6];
gts_cycle_reg1 = cor0_reg_tmp1[5:3];
gwe_cycle_reg1 = cor0_reg_tmp1[2:0];
if (cor0_reg_tmp1[24] == 1'b1)
done_pin_drv[1] = 1;
else
done_pin_drv[1] = 0;
if (cor0_reg_tmp1[28] == 1'b1)
crc_bypass[1] = 1;
else
crc_bypass[1] = 0;
end
always @(cor0_reg[2])
begin
cor0_reg_tmp2 = cor0_reg[2];
done_cycle_reg2 = cor0_reg_tmp2[14:12];
lock_cycle_reg2 = cor0_reg_tmp2[8:6];
gts_cycle_reg2 = cor0_reg_tmp2[5:3];
gwe_cycle_reg2 = cor0_reg_tmp2[2:0];
if (cor0_reg_tmp2[24] == 1'b1)
done_pin_drv[2] = 1;
else
done_pin_drv[2] = 0;
if (cor0_reg_tmp2[28] == 1'b1)
crc_bypass[2] = 1;
else
crc_bypass[2] = 0;
end
always @(cor0_reg[3])
begin
cor0_reg_tmp3 = cor0_reg[3];
done_cycle_reg3 = cor0_reg_tmp3[14:12];
lock_cycle_reg3 = cor0_reg_tmp3[8:6];
gts_cycle_reg3 = cor0_reg_tmp3[5:3];
gwe_cycle_reg3 = cor0_reg_tmp3[2:0];
if (cor0_reg_tmp3[24] == 1'b1)
done_pin_drv[3] = 1;
else
done_pin_drv[3] = 0;
if (cor0_reg_tmp3[28] == 1'b1)
crc_bypass[3] = 1;
else
crc_bypass[3] = 0;
end
always @(cor1_reg[0]) begin
cor1_reg_tmp0 = cor1_reg[0];
rbcrc_no_pin[0] = cor1_reg_tmp0[8];
end
always @(cor1_reg[1]) begin
cor1_reg_tmp1 = cor1_reg[1];
rbcrc_no_pin[1] = cor1_reg_tmp1[8];
end
always @(cor1_reg[2]) begin
cor1_reg_tmp2 = cor1_reg[2];
rbcrc_no_pin[2] = cor1_reg_tmp2[8];
end
always @(cor1_reg[3]) begin
cor1_reg_tmp3 = cor1_reg[3];
rbcrc_no_pin[3] = cor1_reg_tmp3[8];
end
assign stat_reg_tmp0[31:27] = 5'b00000;
assign stat_reg_tmp1[31:27] = 5'b00000;
assign stat_reg_tmp2[31:27] = 5'b00000;
assign stat_reg_tmp3[31:27] = 5'b00000;
assign stat_reg_tmp0[24:21] = 4'bxxx0;
assign stat_reg_tmp1[24:21] = 4'bxxx0;
assign stat_reg_tmp2[24:21] = 4'bxxx0;
assign stat_reg_tmp3[24:21] = 4'bxxx0;
assign stat_reg_tmp0[17:16] = 2'b0;
assign stat_reg_tmp1[17:16] = 2'b0;
assign stat_reg_tmp2[17:16] = 2'b0;
assign stat_reg_tmp3[17:16] = 2'b0;
assign stat_reg_tmp0[14] = DONE;
assign stat_reg_tmp1[14] = DONE;
assign stat_reg_tmp2[14] = DONE;
assign stat_reg_tmp3[14] = DONE;
assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0;
assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0;
assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0;
assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0;
assign stat_reg_tmp0[12] = INITB;
assign stat_reg_tmp1[12] = INITB;
assign stat_reg_tmp2[12] = INITB;
assign stat_reg_tmp3[12] = INITB;
assign stat_reg_tmp0[11] = mode_sample_flag;
assign stat_reg_tmp1[11] = mode_sample_flag;
assign stat_reg_tmp2[11] = mode_sample_flag;
assign stat_reg_tmp3[11] = mode_sample_flag;
assign stat_reg_tmp0[10:8] = mode_pin_in;
assign stat_reg_tmp1[10:8] = mode_pin_in;
assign stat_reg_tmp2[10:8] = mode_pin_in;
assign stat_reg_tmp3[10:8] = mode_pin_in;
assign stat_reg_tmp0[3] = 1'b1;
assign stat_reg_tmp1[3] = 1'b1;
assign stat_reg_tmp2[3] = 1'b1;
assign stat_reg_tmp3[3] = 1'b1;
assign stat_reg_tmp0[2] = pll_locked;
assign stat_reg_tmp1[2] = pll_locked;
assign stat_reg_tmp2[2] = pll_locked;
assign stat_reg_tmp3[2] = pll_locked;
assign stat_reg_tmp0[1] = 1'b0;
assign stat_reg_tmp1[1] = 1'b0;
assign stat_reg_tmp2[1] = 1'b0;
assign stat_reg_tmp3[1] = 1'b0;
assign stat_reg_tmp0[26:25] = buswidth[0];
assign stat_reg_tmp0[20:18] = st_state0;
assign stat_reg_tmp0[15] = id_error_flag[0];
assign stat_reg_tmp0[7] = ghigh_b[0];
assign stat_reg_tmp0[6] = gwe_out[0];
assign stat_reg_tmp0[5] = gts_cfg_b[0];
assign stat_reg_tmp0[4] = eos_startup[0];
assign stat_reg_tmp0[0] = crc_err_flag_reg[0];
assign stat_reg_tmp1[26:25] = buswidth[1];
assign stat_reg_tmp1[20:18] = st_state1;
assign stat_reg_tmp1[15] = id_error_flag[1];
assign stat_reg_tmp1[7] = ghigh_b[1];
assign stat_reg_tmp1[6] = gwe_out[1];
assign stat_reg_tmp1[5] = gts_cfg_b[1];
assign stat_reg_tmp1[4] = eos_startup[1];
assign stat_reg_tmp1[0] = crc_err_flag_reg[1];
assign stat_reg_tmp2[26:25] = buswidth[2];
assign stat_reg_tmp2[20:18] = st_state2;
assign stat_reg_tmp2[15] = id_error_flag[2];
assign stat_reg_tmp2[7] = ghigh_b[2];
assign stat_reg_tmp2[6] = gwe_out[2];
assign stat_reg_tmp2[5] = gts_cfg_b[2];
assign stat_reg_tmp2[4] = eos_startup[2];
assign stat_reg_tmp2[0] = crc_err_flag_reg[2];
assign stat_reg_tmp3[26:25] = buswidth[3];
assign stat_reg_tmp3[20:18] = st_state3;
assign stat_reg_tmp3[15] = id_error_flag[3];
assign stat_reg_tmp3[7] = ghigh_b[3];
assign stat_reg_tmp3[6] = gwe_out[3];
assign stat_reg_tmp3[5] = gts_cfg_b[3];
assign stat_reg_tmp3[4] = eos_startup[3];
assign stat_reg_tmp3[0] = crc_err_flag_reg[3];
assign stat_reg[0] = stat_reg_tmp0;
assign stat_reg[1] = stat_reg_tmp1;
assign stat_reg[2] = stat_reg_tmp2;
assign stat_reg[3] = stat_reg_tmp3;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
st_state0 <= STARTUP_PH0;
st_state1 <= STARTUP_PH0;
st_state2 <= STARTUP_PH0;
st_state3 <= STARTUP_PH0;
startup_begin_flag0 <= 0;
startup_begin_flag1 <= 0;
startup_begin_flag2 <= 0;
startup_begin_flag3 <= 0;
startup_end_flag0 <= 0;
startup_end_flag1 <= 0;
startup_end_flag2 <= 0;
startup_end_flag3 <= 0;
end
else begin
st_state0i = st_state0;
cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0,
st_state0i, nx_st_state0,lock_cycle_reg0);
st_state1i = st_state1;
cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1,
st_state1i, nx_st_state1,lock_cycle_reg1);
st_state2i = st_state2;
cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2,
st_state2i, nx_st_state2,lock_cycle_reg2);
st_state3i = st_state3;
cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3,
st_state3i, nx_st_state3,lock_cycle_reg3);
end
task cur_st_tsk;
output stup_bflag;
output stup_eflag;
output [2:0] cst_o;
input [2:0] cst_in;
input [2:0] nst_in;
input [2:0] lock_cycle_in;
begin
if (nst_in == STARTUP_PH1) begin
stup_bflag = 1;
stup_eflag = 0;
end
else if (cst_in == STARTUP_PH7) begin
stup_eflag = 1;
stup_bflag = 0;
end
if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin
cst_o = nst_in;
end
else
cst_o = cst_in;
end
endtask
always @(st_state0 or startup_set_pulse0 or DONE ) begin
nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0);
end
always @(st_state1 or startup_set_pulse1 or DONE ) begin
nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1);
end
always @(st_state2 or startup_set_pulse2 or DONE ) begin
nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2);
end
always @(st_state3 or startup_set_pulse3 or DONE ) begin
nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3);
end
task nx_st_tsk;
output [2:0] nx_st;
input [2:0] cur_st;
input [1:0] stup_pulse;
input [2:0] done_cycle_in;
begin
if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in))
case (cur_st)
STARTUP_PH0 : if (stup_pulse == 2'b11 )
nx_st = STARTUP_PH1;
else
nx_st = STARTUP_PH0;
STARTUP_PH1 : nx_st = STARTUP_PH2;
STARTUP_PH2 : nx_st = STARTUP_PH3;
STARTUP_PH3 : nx_st = STARTUP_PH4;
STARTUP_PH4 : nx_st = STARTUP_PH5;
STARTUP_PH5 : nx_st = STARTUP_PH6;
STARTUP_PH6 : nx_st = STARTUP_PH7;
STARTUP_PH7 : nx_st = STARTUP_PH0;
endcase
end
endtask
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0) begin
gwe_out <= 4'b0;
gts_out <= 4'b1111;
eos_startup <= 4'b0;
gsr_st_out <= 4'b1111;
done_o <= 4'b0;
end
else begin
if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin
if (DONE !== 0 || done_pin_drv[0] === 1)
done_o[0] <= 1'b1;
else
done_o[0] <= 1'bz;
end
if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin
if (DONE !== 0 || done_pin_drv[1] == 1)
done_o[1] <= 1'b1;
else
done_o[1] <= 1'bz;
end
if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin
if (DONE !== 0 || done_pin_drv[2] == 1)
done_o[2] <= 1'b1;
else
done_o[2] <= 1'bz;
end
if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin
if (DONE !== 0 || done_pin_drv[3] == 1)
done_o[3] <= 1'b1;
else
done_o[3] <= 1'bz;
end
if (st_state0 == gwe_cycle_reg0)
gwe_out[0] <= 1;
if (st_state1 == gwe_cycle_reg1)
gwe_out[1] <= 1;
if (st_state2 == gwe_cycle_reg2)
gwe_out[2] <= 1;
if (st_state3 == gwe_cycle_reg3)
gwe_out[3] <= 1;
if (st_state0 == gts_cycle_reg0 )
gts_out[0] <= 0;
if (st_state1 == gts_cycle_reg1 )
gts_out[1] <= 0;
if (st_state2 == gts_cycle_reg2 )
gts_out[2] <= 0;
if (st_state3 == gts_cycle_reg3 )
gts_out[3] <= 0;
if (st_state0 == STARTUP_PH6 )
gsr_st_out[0] <= 0;
if (st_state1 == STARTUP_PH6 )
gsr_st_out[1] <= 0;
if (st_state2 == STARTUP_PH6 )
gsr_st_out[2] <= 0;
if (st_state3 == STARTUP_PH6 )
gsr_st_out[3] <= 0;
if (st_state0 == STARTUP_PH7 )
eos_startup[0] <= 1;
if (st_state1 == STARTUP_PH7 )
eos_startup[1] <= 1;
if (st_state2 == STARTUP_PH7 )
eos_startup[2] <= 1;
if (st_state3 == STARTUP_PH7 )
eos_startup[3] <= 1;
end
assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0];
assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1];
assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2];
assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3];
assign abort_dis_bi = abort_dis[ib];
always @(posedge cclk_in or negedge rst_intl or
posedge abort_flag_rst or posedge csi_b_in)
if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin
abort_flag[ib] <= 0;
checka_en <= 0;
rdwr_b_in1 <= rdwr_b_in;
end
else begin
if ( abort_dis_bi == 0 && csi_b_in == 0) begin
if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin
abort_flag[ib] <= 1;
if (icap_on == 0)
$display(" Warning : RDWRB changes when CSB low, which causes Configuration abort on SIM_CONFIGE3 instance %m at time %t.", $time);
end
end
else
abort_flag[ib] <= 0;
rdwr_b_in1 <= rdwr_b_in;
checka_en <= 1;
end
always @(posedge abort_flag[ib])
begin
abort_out_en <= 1;
abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in) begin
abort_out_en <= 0;
abort_flag_rst <= 1;
end
@(posedge cclk_in)
abort_flag_rst <= 0;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
task rdbk_byte;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:8] <= 24'b0;
if (rd_dcnt==1)
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
else if (rd_dcnt==2)
outbus[7:0] <= bit_revers8(rdbk_reg[15:8]);
else if (rd_dcnt==3)
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
else if (rd_dcnt==4)
outbus[7:0] <= bit_revers8(rdbk_reg[31:24]);
end
endtask
task rdbk_wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:16] <= 16'b0;
if (rd_dcnt==1)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==2)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==3) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
end
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
outbus[15:8] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
task rdbk_2wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
if (rd_dcnt==1)
outbus <= 32'b0;
else if (rd_dcnt==2)
outbus <= 32'b0;
else if (rd_dcnt==3)
outbus <= 32'b0;
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
outbus[23:16] <= bit_revers8(rdbk_reg[23:16]);
outbus[31:24] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SRL16E.v 0000664 0000000 0000000 00000005713 12327044266 0022344 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
// /___/ /\ Filename : SRL16E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRL16E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
reg [15:0] data;
wire [3:0] addr;
wire CLK_dly, D_dly, CE_dly;
wire CLK_in, D_in, CE_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr = {A3, A2, A1, A0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
{data[15:0]} <= #100 {data[14:0], D_in};
assign Q = data[addr];
always @(notifier)
data[0] <= 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly;
assign CE_in = CE_dly;
`ifdef XIL_TIMING
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (negedge CLK, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SRLC16E.v 0000664 0000000 0000000 00000006053 12327044266 0022445 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : SRLC16E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRLC16E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
output Q15,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
reg [15:0] data;
wire [3:0] addr;
wire CLK_dly, D_dly, CE_dly;
wire CLK_in, D_in, CE_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr[3:0] = {A3, A2, A1, A0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
{data[15:0]} <= #100 {data[14:0], D_in};
assign Q = data[addr];
assign Q15 = data[15];
always @(notifier)
data[0] <= 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly;
assign CE_in = CE_dly;
`ifdef XIL_TIMING
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
(CLK => Q15) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (negedge CLK, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SRLC32E.v 0000664 0000000 0000000 00000006100 12327044266 0022434 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 32-Bit Shift Register Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : SRLC32E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/15/05 - Initial version.
// 01/07/06 - Add LOC parameter (CR 222733)
// 01/18/06 - Add timing path for A1, A2, A3, A4 (CR224341).
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRLC32E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
output Q31,
input [4:0] A,
input CE,
input CLK,
input D
);
reg [31:0] data;
wire CLK_dly, CE_dly, D_dly;
wire CLK_in, CE_in, D_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
always @(posedge CLK_in)
if (CE_in == 1'b1)
data[31:0] <= {data[30:0], D_in};
assign Q = data[A];
assign Q31 = data[31];
always @(notifier)
data[0] = 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly ;
assign CE_in = CE_dly ;
`ifdef XIL_TIMING
specify
(A[0] => Q) = (0:0:0, 0:0:0);
(A[1] => Q) = (0:0:0, 0:0:0);
(A[2] => Q) = (0:0:0, 0:0:0);
(A[3] => Q) = (0:0:0, 0:0:0);
(A[4] => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
(CLK => Q31) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$period (negedge CLK, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/STARTUPE2.v 0000664 0000000 0000000 00000013147 12327044266 0022761 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / User Interface to Global Clock, Reset and 3-State Controls
// /___/ /\ Filename : STARTUPE2.v
// \ \ / \ Timestamp : Mon Mar 8 15:49:37 PST 2010
// \___\/\___\
//
// Revision:
// 03/08/10 - Initial version.
// 10/26/10 - CR 573665 -- Added PREQ support.
// 01/26/11 - CR 591438 -- Added SIM_CCLK_FREQ
// 06/16/11 - CR 610112 -- SIM_CCLK_FREQ attribute check fix
// 08/23/11 - CR 608084 -- Passed USRCCLKO to glbl.CCLKO
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 08/23/12 - Fixed GSR (CR 673651).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module STARTUPE2 (
CFGCLK,
CFGMCLK,
EOS,
PREQ,
CLK,
GSR,
GTS,
KEYCLEARB,
PACK,
USRCCLKO,
USRCCLKTS,
USRDONEO,
USRDONETS
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter PROG_USR = "FALSE";
parameter real SIM_CCLK_FREQ = 0.0;
output CFGCLK;
output CFGMCLK;
output EOS;
output PREQ;
input CLK;
input GSR;
input GTS;
input KEYCLEARB;
input PACK;
input USRCCLKO;
input USRCCLKTS;
input USRDONEO;
input USRDONETS;
reg SIM_CCLK_FREQ_BINARY;
reg [2:0] PROG_USR_BINARY;
time CFGMCLK_PERIOD = 20000;
reg cfgmclk_out;
tri0 GSR, GTS;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
wire CFGCLK_OUT;
wire CFGMCLK_OUT;
wire CLK_IN;
wire GSR_IN;
wire GTS_IN;
wire KEYCLEARB_IN;
wire PACK_IN;
wire USRCCLKO_IN;
wire USRCCLKTS_IN;
wire USRDONEO_IN;
wire USRDONETS_IN;
wire CLK_INDELAY;
wire GSR_INDELAY;
wire GTS_INDELAY;
wire KEYCLEARB_INDELAY;
wire PACK_INDELAY;
wire USRCCLKO_INDELAY;
wire USRCCLKTS_INDELAY;
wire USRDONEO_INDELAY;
wire USRDONETS_INDELAY;
wire start_count;
integer edge_count = 0;
reg preq_deassert = 0;
reg PREQ_out = 0;
wire EOS_out;
// Counters and Flags
reg [2:0] edge_count_cclko = 0;
reg [2:0] cclko_wait_count = 3'b010;
reg start_glbl_cclko = 0;
initial begin
case (PROG_USR)
"FALSE" : PROG_USR_BINARY = 3'b000;
"TRUE" : PROG_USR_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute PROG_USR on STARTUPE2 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PROG_USR);
$finish;
end
endcase
if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0))
SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ;
else begin
$display("Attribute Syntax Error : The Attribute SIM_CCLK_FREQ on STARTUPE2 instance %m is set to %f. Legal values for this attribute are 0.0 to 10.0.", SIM_CCLK_FREQ);
$finish;
end
end
//-------------------------------------------------------------------------------
//----------------- Initial -----------------------------------------------------
//-------------------------------------------------------------------------------
initial begin
cfgmclk_out = 0;
forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out;
end
//-------------------------------------------------------------------------------
//-------------------- PREQ -----------------------------------------------------
//-------------------------------------------------------------------------------
assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0;
always @(posedge cfgmclk_out) begin
if(start_count)
edge_count = edge_count + 1;
else
edge_count = 0;
if(edge_count == 35)
preq_deassert <= 1'b1;
else
preq_deassert <= 1'b0;
end
always @(negedge glbl.PROGB_GLBL, posedge preq_deassert)
PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert;
//-------------------------------------------------------------------------------
//-------------------- ERROR MSG ------------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge PACK) begin
if(PREQ_out == 1'b0)
$display("Error : PACK received with no associate PREQ in STARTTUPE2 instance %m.");
end
//-------------------------------------------------------------------------------
//--------------------- EOS -----------------------------------------------------
//-------------------------------------------------------------------------------
assign EOS_out = ~glbl.GSR;
//-------------------------------------------------------------------------------
//-------------------- glbl.CCLKO ---------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge USRCCLKO) begin
if(EOS_out) edge_count_cclko <= edge_count_cclko + 1;
end
always @(edge_count_cclko)
if (edge_count_cclko == cclko_wait_count)
start_glbl_cclko = 1;
//-------------------------------------------------------------------------------
//-------------------- OUTPUT ---------------------------------------------------
//-------------------------------------------------------------------------------
assign CFGMCLK = cfgmclk_out;
assign PREQ = PREQ_out;
assign EOS = EOS_out;
assign glbl.CCLKO_GLBL = start_glbl_cclko ? ~USRCCLKTS? USRCCLKO : 1'b1 : 1'b1;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/STARTUPE3.v 0000664 0000000 0000000 00000011505 12327044266 0022756 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2013 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / / User Interface to Global Clock, Reset and 3-State Controls
// /___/ /\ Filename : STARTUPE3.v
// \ \ / \ Timestamp : Tue Jul 9 16:30:16 PDT 2013
// \___\/\___\
//
// Revision:
// 07/12/13 - Initial version.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module STARTUPE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter PROG_USR = "FALSE",
parameter real SIM_CCLK_FREQ = 0.0
)(
output CFGCLK,
output CFGMCLK,
output [3:0] DI,
output EOS,
output PREQ,
input [3:0] DO,
input [3:0] DTS,
input FCSBO,
input FCSBTS,
input GSR,
input GTS,
input KEYCLEARB,
input PACK,
input USRCCLKO,
input USRCCLKTS,
input USRDONEO,
input USRDONETS
);
reg SIM_CCLK_FREQ_BINARY;
reg [2:0] PROG_USR_BINARY;
time CFGMCLK_PERIOD = 20000;
reg cfgmclk_out;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
wire start_count;
integer edge_count = 0;
reg preq_deassert = 0;
reg PREQ_out = 0;
wire EOS_out;
// Counters and Flags
reg [2:0] edge_count_cclko = 0;
reg [2:0] cclko_wait_count = 3'b010;
reg start_glbl_cclko = 0;
initial begin
case (PROG_USR)
"FALSE" : PROG_USR_BINARY = 3'b000;
"TRUE" : PROG_USR_BINARY = 3'b111;
default : begin
$display("Attribute Syntax Error : The Attribute PROG_USR on STARTUPE3 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PROG_USR);
$finish;
end
endcase
if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0))
SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ;
else begin
$display("Attribute Syntax Error : The Attribute SIM_CCLK_FREQ on STARTUPE3 instance %m is set to %f. Legal values for this attribute are 0.0 to 10.0.", SIM_CCLK_FREQ);
$finish;
end
end
//-------------------------------------------------------------------------------
//----------------- Initial -----------------------------------------------------
//-------------------------------------------------------------------------------
initial begin
cfgmclk_out = 0;
forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out;
end
//-------------------------------------------------------------------------------
//-------------------- PREQ -----------------------------------------------------
//-------------------------------------------------------------------------------
assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0;
always @(posedge cfgmclk_out) begin
if(start_count)
edge_count = edge_count + 1;
else
edge_count = 0;
if(edge_count == 35)
preq_deassert <= 1'b1;
else
preq_deassert <= 1'b0;
end
always @(negedge glbl.PROGB_GLBL, posedge preq_deassert)
PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert;
//-------------------------------------------------------------------------------
//-------------------- ERROR MSG ------------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge PACK) begin
if(PREQ_out == 1'b0)
$display("Error : PACK received with no associate PREQ in STARTTUPE3 instance %m.");
end
//-------------------------------------------------------------------------------
//--------------------- EOS -----------------------------------------------------
//-------------------------------------------------------------------------------
assign EOS_out = ~glbl.GSR;
//-------------------------------------------------------------------------------
//-------------------- glbl.CCLKO ---------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge USRCCLKO) begin
if(EOS_out) edge_count_cclko <= edge_count_cclko + 1;
end
always @(edge_count_cclko)
if (edge_count_cclko == cclko_wait_count)
start_glbl_cclko = 1;
//-------------------------------------------------------------------------------
//-------------------- OUTPUT ---------------------------------------------------
//-------------------------------------------------------------------------------
assign CFGMCLK = cfgmclk_out;
assign PREQ = PREQ_out;
assign EOS = EOS_out;
assign glbl.CCLKO_GLBL = start_glbl_cclko ? ~USRCCLKTS? USRCCLKO : 1'b1 : 1'b1;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/SYSMONE1.v 0000664 0000000 0000000 00000316032 12327044266 0022645 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.6 (P.59)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / System Monitor
// /___/ /\ Filename : SYSMONE1.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 01/31/13 - Initial version.
// 03/19/13 - Fixed fatal width problem (CR 707214).
// - Update MUXADDR width (CR 706758).
// 03/20/13 - Fixed output MSB problem (CR 706163).
// - Remove SCL and SDA ports (CR 707646).
// 04/26/13 - Add invertible pin support (PR 683925).
// 05/01/13 - Fixed DRC for IS_*_INVERTED parameters (CR 715818).
// 05/08/13 - Changed Vuser1-4 to Vuser 0-3 (CR 716783).
// 06/04/13 - Added I2CSCLK and I2CSDA ports (CR 721147).
// 06/19/13 - Fixed CHANNEL output (CR 717955).
// 10/15/13 - Added I2C simulation support (CR 707725).
// 10/28/13 - Removed DRC for event mode timing (CR 736315).
// 11/15/13 - Updated I2C support for in and output instead of inout (CR 742395).
// End Revision
`timescale 1ps / 1ps
`celldefine
module SYSMONE1 #(
parameter [15:0] INIT_40 = 16'h0,
parameter [15:0] INIT_41 = 16'h0,
parameter [15:0] INIT_42 = 16'h0,
parameter [15:0] INIT_43 = 16'h0,
parameter [15:0] INIT_44 = 16'h0,
parameter [15:0] INIT_45 = 16'h0,
parameter [15:0] INIT_46 = 16'h0,
parameter [15:0] INIT_47 = 16'h0,
parameter [15:0] INIT_48 = 16'h0,
parameter [15:0] INIT_49 = 16'h0,
parameter [15:0] INIT_4A = 16'h0,
parameter [15:0] INIT_4B = 16'h0,
parameter [15:0] INIT_4C = 16'h0,
parameter [15:0] INIT_4D = 16'h0,
parameter [15:0] INIT_4E = 16'h0,
parameter [15:0] INIT_4F = 16'h0,
parameter [15:0] INIT_50 = 16'h0,
parameter [15:0] INIT_51 = 16'h0,
parameter [15:0] INIT_52 = 16'h0,
parameter [15:0] INIT_53 = 16'h0,
parameter [15:0] INIT_54 = 16'h0,
parameter [15:0] INIT_55 = 16'h0,
parameter [15:0] INIT_56 = 16'h0,
parameter [15:0] INIT_57 = 16'h0,
parameter [15:0] INIT_58 = 16'h0,
parameter [15:0] INIT_59 = 16'h0,
parameter [15:0] INIT_5A = 16'h0,
parameter [15:0] INIT_5B = 16'h0,
parameter [15:0] INIT_5C = 16'h0,
parameter [15:0] INIT_5D = 16'h0,
parameter [15:0] INIT_5E = 16'h0,
parameter [15:0] INIT_5F = 16'h0,
parameter [15:0] INIT_60 = 16'h0,
parameter [15:0] INIT_61 = 16'h0,
parameter [15:0] INIT_62 = 16'h0,
parameter [15:0] INIT_63 = 16'h0,
parameter [15:0] INIT_64 = 16'h0,
parameter [15:0] INIT_65 = 16'h0,
parameter [15:0] INIT_66 = 16'h0,
parameter [15:0] INIT_67 = 16'h0,
parameter [15:0] INIT_68 = 16'h0,
parameter [15:0] INIT_69 = 16'h0,
parameter [15:0] INIT_6A = 16'h0,
parameter [15:0] INIT_6B = 16'h0,
parameter [15:0] INIT_6C = 16'h0,
parameter [15:0] INIT_6D = 16'h0,
parameter [15:0] INIT_6E = 16'h0,
parameter [15:0] INIT_6F = 16'h0,
parameter [15:0] INIT_70 = 16'h0,
parameter [15:0] INIT_71 = 16'h0,
parameter [15:0] INIT_72 = 16'h0,
parameter [15:0] INIT_73 = 16'h0,
parameter [15:0] INIT_74 = 16'h0,
parameter [15:0] INIT_75 = 16'h0,
parameter [15:0] INIT_76 = 16'h0,
parameter [15:0] INIT_77 = 16'h0,
parameter [15:0] INIT_78 = 16'h0,
parameter [15:0] INIT_79 = 16'h0,
parameter [15:0] INIT_7A = 16'h0,
parameter [15:0] INIT_7B = 16'h0,
parameter [15:0] INIT_7C = 16'h0,
parameter [15:0] INIT_7D = 16'h0,
parameter [15:0] INIT_7E = 16'h0,
parameter [15:0] INIT_7F = 16'h0,
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0,
parameter [0:0] IS_DCLK_INVERTED = 1'b0,
parameter SIM_MONITOR_FILE = "design.txt",
parameter integer SYSMON_VUSER0_BANK = 0,
parameter SYSMON_VUSER0_MONITOR = "NONE",
parameter integer SYSMON_VUSER1_BANK = 0,
parameter SYSMON_VUSER1_MONITOR = "NONE",
parameter integer SYSMON_VUSER2_BANK = 0,
parameter SYSMON_VUSER2_MONITOR = "NONE",
parameter integer SYSMON_VUSER3_BANK = 0,
parameter SYSMON_VUSER3_MONITOR = "NONE"
)(
output [15:0] ALM,
output BUSY,
output [5:0] CHANNEL,
output [15:0] DO,
output DRDY,
output EOC,
output EOS,
output I2C_SCLK_TS,
output I2C_SDA_TS,
output JTAGBUSY,
output JTAGLOCKED,
output JTAGMODIFIED,
output [4:0] MUXADDR,
output OT,
input CONVST,
input CONVSTCLK,
input [7:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input I2C_SCLK,
input I2C_SDA,
input RESET,
input [15:0] VAUXN,
input [15:0] VAUXP,
input VN,
input VP
);
localparam S1_ST = 0,
S6_ST = 1,
S2_ST = 2,
S3_ST = 3,
S5_ST = 5,
S4_ST = 6;
time time_out, prev_time_out;
integer temperature_index = -1, time_index = -1, vccaux_index = -1;
integer vbram_index = -1;
integer vccint_index = -1, vn_index = -1, vp_index = -1;
integer vccpint_index = -1;
integer vccpaux_index = -1;
integer vccpdro_index = -1;
integer vauxp_idx0 = -1, vauxn_idx0 = -1;
integer vauxp_idx1 = -1, vauxn_idx1 = -1;
integer vauxp_idx2 = -1, vauxn_idx2 = -1;
integer vauxp_idx3 = -1, vauxn_idx3 = -1;
integer vauxp_idx4 = -1, vauxn_idx4 = -1;
integer vauxp_idx5 = -1, vauxn_idx5 = -1;
integer vauxp_idx6 = -1, vauxn_idx6 = -1;
integer vauxp_idx7 = -1, vauxn_idx7 = -1;
integer vauxp_idx8 = -1, vauxn_idx8 = -1;
integer vauxp_idx9 = -1, vauxn_idx9 = -1;
integer vauxp_idx10 = -1, vauxn_idx10 = -1;
integer vauxp_idx11 = -1, vauxn_idx11 = -1;
integer vauxp_idx12 = -1, vauxn_idx12 = -1;
integer vauxp_idx13 = -1, vauxn_idx13 = -1;
integer vauxp_idx14 = -1, vauxn_idx14 = -1;
integer vauxp_idx15 = -1, vauxn_idx15 = -1;
integer vuser0_index = -1, vuser1_index = -1;
integer vuser2_index = -1, vuser3_index = -1;
integer char_1, char_2, fs, fd;
integer num_arg, num_val;
integer clk_count, seq_count, seq_count2, seq_count_a;
integer seq_status_avg, acq_count;
integer seq_status_avg2;
integer conv_pj_count [63:0];
integer conv_acc [31:0];
integer conv_result_int;
integer conv_time, conv_count, conv_time_cal, conv_time_cal_1;
integer h, i, j, k, l, m, n, p;
integer file_line;
// string
reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46;
reg [8*600:1] one_line;
reg [8*12:1] label [46:0];
reg [8*12:1] tmp_label;
reg end_of_file;
real tmp_va0, tmp_va1, column_real00, column_real100, column_real101;
real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46;
// array of real numbers
reg [63:0] column_real [46:0];
reg [63:0] chan_val [35:0];
reg [63:0] chan_val_tmp [35:0];
reg [63:0] chan_valn [35:0];
reg [63:0] chan_valn_tmp [35:0];
reg [63:0] mn_in_diff [35:0];
reg [63:0] mn_in2_diff [35:0];
reg [63:0] mn_in_uni [35:0];
reg [63:0] mn_in2_uni [35:0];
reg [63:0] mn_comm_in [35:0];
reg [63:0] mn_comm2_in [35:0];
real chan_val_p_tmp, chan_val_n_tmp;
real mn_mux_in, mn_in_tmp, mn_comm_in_tmp, mn_in_comm;
real tmp_v, tmp_v1;
real adc_temp_result, adc_intpwr_result;
real adc_ext_result;
reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly;
reg soft_reset = 0;
reg en_data_flag;
reg first_cal_chan;
reg seq_en;
reg seq_en_dly;
wire [15:0] flag_reg0, flag_reg1;
reg [15:0] ot_limit_reg = 16'hCA30;
reg [15:0] tmp_otv;
reg [23:0] conv_acc_vec;
reg [15:0] conv_result;
reg [15:0] conv_result_reg, conv_acc_result;
wire [7:0] curr_clkdiv_sel;
reg [15:0] alarm_out_reg;
reg [5:0] curr_chan, curr_chan_lat;
reg [2:0] adc_state, next_state;
reg conv_start, conv_end;
reg eos_en, eos_tmp_en;
reg drdy_out, drdy_out_tmp1, drdy_out_tmp2, drdy_out_tmp3, drdy_out_tmp4;
reg ot_out_reg;
reg [15:0] do_out;
reg [15:0] do_out_rdtmp;
reg [15:0] data_reg [63:0];
reg [15:0] dr_sram [255:64];
reg sysclk, adcclk_tmp;
wire adcclk;
wire sysmone1_en, sysmone12_en;
reg [3:0] curr_seq1_0, curr_seq1_0_lat;
reg [1:0] tmp_seq1_0 = 2'b00;
reg curr_e_c, curr_b_u, curr_acq;
reg ext_mux;
reg seq_count_en;
reg [5:0] acq_chan;
reg [4:0] acq_chan_m;
reg [4:0] ext_mux_chan;
reg acq_b_u;
reg adc_s1_flag, acq_acqsel;
wire acq_e_c;
reg acq_e_c_tmp5, acq_e_c_tmp6;
reg [1:0] curr_pj_set;
reg eoc_en, eoc_en_delay;
reg eoc_out_tmp, eos_out_tmp;
reg eoc_out_tmp1, eos_out_tmp1;
reg eoc_out, eos_out;
reg eoc_out_t;
reg busy_r, busy_r_rst;
reg busy_sync1, busy_sync2;
wire busy_sync_fall, busy_sync_rise;
reg notifier, notifier_do;
reg [5:0] channel_out;
wire [4:0] muxaddr_o;
reg [4:0] muxaddr_out;
reg rst_lock, rst_lock_early, rst_lock_late;
reg sim_file_flag;
reg [7:0] daddr_in_lat;
reg [15:0] init40h_tmp, init41h_tmp, init42h_tmp, init4eh_tmp;
reg [15:0] alarm_out;
reg ot_out;
reg [15:0] curr_seq, curr_seq_m;
wire [15:0] curr_seq2;
reg busy_out, busy_rst, busy_conv, busy_out_tmp, busy_seq_rst;
reg [3:0] seq1_0, seq_bits;
reg ot_en, alarm_update, drp_update, cal_chan_update;
reg [13:0] alarm_en;
reg [4:0] scon_tmp;
wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_chan_reg3;
wire [15:0] seq_acq_reg1, seq_acq_reg2, seq_acq_reg3;
wire [15:0] seq_pj_reg1, seq_pj_reg2, seq_pj_reg3;
wire [15:0] seq_du_reg1, seq_du_reg2, seq_du_reg3;
reg [15:0] cfg_reg1_init;
reg [4:0] seq_curr_i, seq_curr_i2, seq_curr_ia;
integer busy_rst_cnt;
integer si, seq_num, seq_num2;
integer seq_mem [32:0];
integer seq_mem2 [32:0];
wire rst_in, adc_convst;
wire [15:0] cfg_reg0;
wire [15:0] cfg_reg1;
wire [15:0] cfg_reg2;
wire [15:0] cfg_reg3;
wire [15:0] di_in;
wire [7:0] daddr_in;
wire [15:0] tmp_data_reg_out, tmp_dr_sram_out;
wire convst_in_tmp;
reg convst_in;
wire rst_in_not_seq;
wire adcclk_div1;
wire gsr_in;
wire convst_raw_in, convstclk_in, dclk_in, den_in, rst_input, dwe_in;
wire dclk_tmp, convstclk_tmp;
wire DCLK_dly, DEN_dly, DWE_dly;
wire [7:0] DADDR_dly;
wire [15:0] DI_dly;
reg trig_attr_chk = 0;
reg trig_dep_attr_chk = 0;
reg attr_err = 0;
wire i2c_sclk_in, i2c_sda_in;
reg i2c_sda_setup_sync;
reg i2c_sda_out_tmp;
assign i2c_sclk_in = I2C_SCLK;
assign i2c_sda_in = I2C_SDA;
assign I2C_SCLK_TS = i2c_sda_setup_sync;
assign I2C_SDA_TS = i2c_sda_out_tmp;
reg [15:0] INIT_40_reg = INIT_40;
reg [15:0] INIT_41_reg = INIT_41;
reg [15:0] INIT_42_reg = INIT_42;
reg [15:0] INIT_43_reg = INIT_43;
reg [15:0] INIT_44_reg = INIT_44;
reg [15:0] INIT_45_reg = INIT_45;
reg [15:0] INIT_46_reg = INIT_46;
reg [15:0] INIT_47_reg = INIT_47;
reg [15:0] INIT_48_reg = INIT_48;
reg [15:0] INIT_49_reg = INIT_49;
reg [15:0] INIT_4A_reg = INIT_4A;
reg [15:0] INIT_4B_reg = INIT_4B;
reg [15:0] INIT_4C_reg = INIT_4C;
reg [15:0] INIT_4D_reg = INIT_4D;
reg [15:0] INIT_4E_reg = INIT_4E;
reg [15:0] INIT_4F_reg = INIT_4F;
reg [15:0] INIT_50_reg = INIT_50;
reg [15:0] INIT_51_reg = INIT_51;
reg [15:0] INIT_52_reg = INIT_52;
reg [15:0] INIT_53_reg = INIT_53;
reg [15:0] INIT_54_reg = INIT_54;
reg [15:0] INIT_55_reg = INIT_55;
reg [15:0] INIT_56_reg = INIT_56;
reg [15:0] INIT_57_reg = INIT_57;
reg [15:0] INIT_58_reg = INIT_58;
reg [15:0] INIT_59_reg = INIT_59;
reg [15:0] INIT_5A_reg = INIT_5A;
reg [15:0] INIT_5B_reg = INIT_5B;
reg [15:0] INIT_5C_reg = INIT_5C;
reg [15:0] INIT_5D_reg = INIT_5D;
reg [15:0] INIT_5E_reg = INIT_5E;
reg [15:0] INIT_5F_reg = INIT_5F;
reg [15:0] INIT_60_reg = INIT_60;
reg [15:0] INIT_61_reg = INIT_61;
reg [15:0] INIT_62_reg = INIT_62;
reg [15:0] INIT_63_reg = INIT_63;
reg [15:0] INIT_64_reg = INIT_64;
reg [15:0] INIT_65_reg = INIT_65;
reg [15:0] INIT_66_reg = INIT_66;
reg [15:0] INIT_67_reg = INIT_67;
reg [15:0] INIT_68_reg = INIT_68;
reg [15:0] INIT_69_reg = INIT_69;
reg [15:0] INIT_6A_reg = INIT_6A;
reg [15:0] INIT_6B_reg = INIT_6B;
reg [15:0] INIT_6C_reg = INIT_6C;
reg [15:0] INIT_6D_reg = INIT_6D;
reg [15:0] INIT_6E_reg = INIT_6E;
reg [15:0] INIT_6F_reg = INIT_6F;
reg [15:0] INIT_70_reg = INIT_70;
reg [15:0] INIT_71_reg = INIT_71;
reg [15:0] INIT_72_reg = INIT_72;
reg [15:0] INIT_73_reg = INIT_73;
reg [15:0] INIT_74_reg = INIT_74;
reg [15:0] INIT_75_reg = INIT_75;
reg [15:0] INIT_76_reg = INIT_76;
reg [15:0] INIT_77_reg = INIT_77;
reg [15:0] INIT_78_reg = INIT_78;
reg [15:0] INIT_79_reg = INIT_79;
reg [15:0] INIT_7A_reg = INIT_7A;
reg [15:0] INIT_7B_reg = INIT_7B;
reg [15:0] INIT_7C_reg = INIT_7C;
reg [15:0] INIT_7D_reg = INIT_7D;
reg [15:0] INIT_7E_reg = INIT_7E;
reg [15:0] INIT_7F_reg = INIT_7F;
reg IS_CONVSTCLK_INVERTED_reg = IS_CONVSTCLK_INVERTED;
reg IS_DCLK_INVERTED_reg = IS_DCLK_INVERTED;
`ifdef XIL_DR
`include "SYSMONE1_dr.v"
`endif
initial begin
#1 trig_attr_chk = 1;
#2 trig_dep_attr_chk = 1;
end
//CR 675227
integer halt_adc = 0;
reg int_rst;
always @(posedge rst_input)
halt_adc <= 0;
always @(seq1_0) begin
if (halt_adc == 2 && seq1_0 == 4'b0001) begin
halt_adc <= 0;
int_rst <= 1;
@(posedge dclk_in)
int_rst <= 0;
end
end
tri0 GSR = glbl.GSR;
`ifndef XIL_TIMING
assign BUSY = busy_out;
assign DRDY = drdy_out;
assign EOC = eoc_out;
assign EOS = eos_out;
assign OT = ot_out;
assign DO = do_out;
assign CHANNEL = channel_out;
assign MUXADDR = muxaddr_out;
assign ALM = alarm_out;
assign convst_raw_in = CONVST;
assign convstclk_tmp = CONVSTCLK;
assign dclk_tmp = DCLK;
assign den_in = DEN;
assign rst_input = RESET;
assign dwe_in = DWE;
assign di_in = DI;
assign daddr_in = DADDR;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
assign BUSY = busy_out;
assign DRDY = drdy_out;
assign EOC = eoc_out;
assign EOS = eos_out;
assign OT = ot_out;
assign DO = do_out;
assign CHANNEL = channel_out;
assign MUXADDR = muxaddr_out;
assign ALM = alarm_out;
assign convst_raw_in = CONVST;
assign convstclk_tmp = CONVSTCLK;
assign dclk_tmp = DCLK_dly;
assign den_in = DEN_dly;
assign rst_input = RESET;
assign dwe_in = DWE_dly;
assign di_in = DI_dly;
assign daddr_in = DADDR_dly;
`endif // `ifdef XIL_TIMING
assign dclk_in = dclk_tmp ^ IS_DCLK_INVERTED_reg;
assign convstclk_in = convstclk_tmp ^ IS_CONVSTCLK_INVERTED_reg;
assign gsr_in = GSR;
assign convst_in_tmp = (convst_raw_in===1 || convstclk_in===1) ? 1: 0;
assign JTAGLOCKED = 0;
assign JTAGMODIFIED = 0;
assign JTAGBUSY = 0;
always @(posedge convst_in_tmp or negedge convst_in_tmp or posedge rst_in)
if (rst_in == 1 || rst_lock == 1)
convst_in <= 0;
else if (convst_in_tmp == 1)
convst_in <= 1;
else if (convst_in_tmp == 0)
convst_in <= 0;
always @(trig_dep_attr_chk) begin
init40h_tmp = INIT_40_reg;
init41h_tmp = INIT_41_reg;
init42h_tmp = INIT_42_reg;
init4eh_tmp = INIT_4E_reg;
if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[8]==1) && (init40h_tmp[5:0] != 6'b000011) && (init40h_tmp[5:0] < 6'b010000))
$display(" Attribute Syntax warning : The attribute INIT_40 on SYSMONE1 instance %m is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_40_reg);
if ((init41h_tmp[15:12]!=4'b0011) && (init4eh_tmp[10:0]!=11'b0) && (init4eh_tmp[15:12]!=4'b0))
$display(" Attribute Syntax warning : The attribute INIT_4E on SYSMONE1 instance %m is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_4E_reg);
if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[13:12]!=2'b00) && (INIT_48_reg != 16'h0000) && (INIT_49_reg != 16'h0000))
$display(" Attribute Syntax warning : INIT_48 and INIT_49 are %x and %x on SYSMONE1 instance %m. Those attributes must be set to 0000h in single channel mode and averaging enabled.", INIT_48_reg, INIT_49_reg);
if (INIT_45_reg != 16'h0)
$display(" Warning : The attribute INIT_45 on SYSMONE1 instance %m is set to %x. This must be set to 0000h.", INIT_45_reg);
end
always @(trig_attr_chk) begin
dr_sram[8'h40] = INIT_40_reg;
dr_sram[8'h41] = INIT_41_reg;
dr_sram[8'h42] = INIT_42_reg;
dr_sram[8'h43] = INIT_43_reg;
dr_sram[8'h44] = INIT_44_reg;
dr_sram[8'h45] = INIT_45_reg;
dr_sram[8'h46] = INIT_46_reg;
dr_sram[8'h47] = INIT_47_reg;
dr_sram[8'h48] = INIT_48_reg;
dr_sram[8'h49] = INIT_49_reg;
dr_sram[8'h4A] = INIT_4A_reg;
dr_sram[8'h4B] = INIT_4B_reg;
dr_sram[8'h4C] = INIT_4C_reg;
dr_sram[8'h4D] = INIT_4D_reg;
dr_sram[8'h4E] = INIT_4E_reg;
dr_sram[8'h4F] = INIT_4F_reg;
dr_sram[8'h50] = INIT_50_reg;
dr_sram[8'h51] = INIT_51_reg;
dr_sram[8'h52] = INIT_52_reg;
tmp_otv = INIT_53_reg;
if (tmp_otv [3:0] == 4'b0011) begin
dr_sram[8'h53] = INIT_53_reg;
ot_limit_reg = INIT_53_reg;
end
else begin
dr_sram[8'h53] = 16'hCA30;
ot_limit_reg = 16'hCA30;
end
dr_sram[8'h54] = INIT_54_reg;
dr_sram[8'h55] = INIT_55_reg;
dr_sram[8'h56] = INIT_56_reg;
dr_sram[8'h57] = INIT_57_reg;
dr_sram[8'h58] = INIT_58_reg;
dr_sram[8'h59] = INIT_59_reg;
dr_sram[8'h5A] = INIT_5A_reg;
dr_sram[8'h5B] = INIT_5B_reg;
dr_sram[8'h5C] = INIT_5C_reg;
dr_sram[8'h5D] = INIT_5D_reg;
dr_sram[8'h5E] = INIT_5E_reg;
dr_sram[8'h5F] = INIT_5F_reg;
dr_sram[8'h60] = INIT_60_reg;
dr_sram[8'h61] = INIT_61_reg;
dr_sram[8'h62] = INIT_62_reg;
dr_sram[8'h63] = INIT_63_reg;
dr_sram[8'h68] = INIT_68_reg;
dr_sram[8'h69] = INIT_69_reg;
dr_sram[8'h6A] = INIT_6A_reg;
dr_sram[8'h6B] = INIT_6B_reg;
dr_sram[8'h78] = INIT_78_reg;
dr_sram[8'h79] = INIT_79_reg;
if (!((IS_CONVSTCLK_INVERTED_reg == 1'b0) || (IS_CONVSTCLK_INVERTED_reg == 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CONVSTCLK_INVERTED on instance %m is set to %b. Legal values for this attribute are 1'b0 or 1'b1.", IS_CONVSTCLK_INVERTED_reg);
attr_err = 1'b1;
end
if (!((IS_DCLK_INVERTED_reg == 1'b0) || (IS_DCLK_INVERTED_reg == 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_DCLK_INVERTED on instance %m is set to %b. Legal values for this attribute are 1'b0 or 1'b1.", IS_DCLK_INVERTED_reg);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end // always @ (trig_attr_chk)
// read input file
initial begin
char_1 = 0;
char_2 = 0;
time_out = 0;
sim_file_flag = 0;
file_line = -1;
end_of_file = 0;
fd = $fopen(SIM_MONITOR_FILE, "r");
if (fd == 0)
begin
$display(" *** Warning: The analog data file %s for SYSMONE1 instance %m was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.\n", SIM_MONITOR_FILE);
sim_file_flag = 1;
end
if (sim_file_flag == 0) begin
while (end_of_file==0) begin
file_line = file_line + 1;
char_1 = $fgetc (fd);
char_2 = $fgetc (fd);
// if(char_2==`EOFile)
if(char_2== -1)
end_of_file = 1;
else begin
// Ignore Comments
if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
// Getting labels
else if ((char_1 == "T" & char_2 == "I" ) ||
(char_1 == "T" & char_2 == "i" ) ||
(char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s ", label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46);
label[0] = label0;
label[1] = label1;
label[2] = label2;
label[3] = label3;
label[4] = label4;
label[5] = label5;
label[6] = label6;
label[7] = label7;
label[8] = label8;
label[9] = label9;
label[10] = label10;
label[11] = label11;
label[12] = label12;
label[13] = label13;
label[14] = label14;
label[15] = label15;
label[16] = label16;
label[17] = label17;
label[18] = label18;
label[19] = label19;
label[20] = label20;
label[21] = label21;
label[22] = label22;
label[23] = label23;
label[24] = label24;
label[25] = label25;
label[26] = label26;
label[27] = label27;
label[28] = label28;
label[29] = label29;
label[30] = label30;
label[31] = label31;
label[32] = label32;
label[33] = label33;
label[34] = label34;
label[35] = label35;
label[36] = label36;
label[37] = label37;
label[38] = label38;
label[39] = label39;
label[40] = label40;
label[41] = label41;
label[42] = label42;
label[43] = label43;
label[44] = label44;
label[45] = label45;
label[46] = label46;
for (m = 0; m < num_arg; m = m +1) begin
tmp_label = 96'b0;
tmp_label = to_upcase_label(label[m]);
case (tmp_label)
"TEMP" : temperature_index = m;
"TIME" : time_index = m;
"VCCAUX" : vccaux_index = m;
"VCCINT" : vccint_index = m;
"VBRAM" : vbram_index = m;
"VCCPINT" : vccpint_index = m;
"VCCPAUX" : vccpaux_index = m;
"VCCDDRO" : vccpdro_index = m;
"VN" : vn_index = m;
"VAUXN[0]" : vauxn_idx0 = m;
"VAUXN[1]" : vauxn_idx1 = m;
"VAUXN[2]" : vauxn_idx2 = m;
"VAUXN[3]" : vauxn_idx3 = m;
"VAUXN[4]" : vauxn_idx4 = m;
"VAUXN[5]" : vauxn_idx5 = m;
"VAUXN[6]" : vauxn_idx6 = m;
"VAUXN[7]" : vauxn_idx7 = m;
"VAUXN[8]" : vauxn_idx8 = m;
"VAUXN[9]" : vauxn_idx9 = m;
"VAUXN[10]" : vauxn_idx10 = m;
"VAUXN[11]" : vauxn_idx11 = m;
"VAUXN[12]" : vauxn_idx12 = m;
"VAUXN[13]" : vauxn_idx13 = m;
"VAUXN[14]" : vauxn_idx14 = m;
"VAUXN[15]" : vauxn_idx15 = m;
"VP" : vp_index = m;
"VAUXP[0]" : vauxp_idx0 = m;
"VAUXP[1]" : vauxp_idx1 = m;
"VAUXP[2]" : vauxp_idx2 = m;
"VAUXP[3]" : vauxp_idx3 = m;
"VAUXP[4]" : vauxp_idx4 = m;
"VAUXP[5]" : vauxp_idx5 = m;
"VAUXP[6]" : vauxp_idx6 = m;
"VAUXP[7]" : vauxp_idx7 = m;
"VAUXP[8]" : vauxp_idx8 = m;
"VAUXP[9]" : vauxp_idx9 = m;
"VAUXP[10]" : vauxp_idx10 = m;
"VAUXP[11]" : vauxp_idx11 = m;
"VAUXP[12]" : vauxp_idx12 = m;
"VAUXP[13]" : vauxp_idx13 = m;
"VAUXP[14]" : vauxp_idx14 = m;
"VAUXP[15]" : vauxp_idx15 = m;
"VUSER0" : vuser0_index = m;
"VUSER1" : vuser1_index = m;
"VUSER2" : vuser2_index = m;
"VUSER3" : vuser3_index = m;
default : begin
$display("analog Data File Error : The channel name %s is invalid in the input file for SYSMONE1 instance %m.", tmp_label);
infile_format;
end
endcase
end // for (m = 0; m < num_arg; m = m +1)
end
// Getting column values
else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
column_real0 = 0.0;
column_real1 = 0.0;
column_real2 = 0.0;
column_real3 = 0.0;
column_real4 = 0.0;
column_real5 = 0.0;
column_real6 = 0.0;
column_real7 = 0.0;
column_real8 = 0.0;
column_real9 = 0.0;
column_real10 = 0.0;
column_real11 = 0.0;
column_real12 = 0.0;
column_real13 = 0.0;
column_real14 = 0.0;
column_real15 = 0.0;
column_real16 = 0.0;
column_real17 = 0.0;
column_real18 = 0.0;
column_real19 = 0.0;
column_real20 = 0.0;
column_real21 = 0.0;
column_real22 = 0.0;
column_real23 = 0.0;
column_real24 = 0.0;
column_real25 = 0.0;
column_real26 = 0.0;
column_real27 = 0.0;
column_real28 = 0.0;
column_real29 = 0.0;
column_real30 = 0.0;
column_real31 = 0.0;
column_real32 = 0.0;
column_real33 = 0.0;
column_real34 = 0.0;
column_real35 = 0.0;
column_real36 = 0.0;
column_real37 = 0.0;
column_real38 = 0.0;
column_real39 = 0.0;
column_real40 = 0.0;
column_real41 = 0.0;
column_real42 = 0.0;
column_real43 = 0.0;
column_real44 = 0.0;
column_real45 = 0.0;
column_real46 = 0.0;
num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46);
column_real[0] = $realtobits(column_real0);
column_real[1] = $realtobits(column_real1);
column_real[2] = $realtobits(column_real2);
column_real[3] = $realtobits(column_real3);
column_real[4] = $realtobits(column_real4);
column_real[5] = $realtobits(column_real5);
column_real[6] = $realtobits(column_real6);
column_real[7] = $realtobits(column_real7);
column_real[8] = $realtobits(column_real8);
column_real[9] = $realtobits(column_real9);
column_real[10] = $realtobits(column_real10);
column_real[11] = $realtobits(column_real11);
column_real[12] = $realtobits(column_real12);
column_real[13] = $realtobits(column_real13);
column_real[14] = $realtobits(column_real14);
column_real[15] = $realtobits(column_real15);
column_real[16] = $realtobits(column_real16);
column_real[17] = $realtobits(column_real17);
column_real[18] = $realtobits(column_real18);
column_real[19] = $realtobits(column_real19);
column_real[20] = $realtobits(column_real20);
column_real[21] = $realtobits(column_real21);
column_real[22] = $realtobits(column_real22);
column_real[23] = $realtobits(column_real23);
column_real[24] = $realtobits(column_real24);
column_real[25] = $realtobits(column_real25);
column_real[26] = $realtobits(column_real26);
column_real[27] = $realtobits(column_real27);
column_real[28] = $realtobits(column_real28);
column_real[29] = $realtobits(column_real29);
column_real[30] = $realtobits(column_real30);
column_real[31] = $realtobits(column_real31);
column_real[32] = $realtobits(column_real32);
column_real[33] = $realtobits(column_real33);
column_real[34] = $realtobits(column_real34);
column_real[35] = $realtobits(column_real35);
column_real[36] = $realtobits(column_real36);
column_real[37] = $realtobits(column_real37);
column_real[38] = $realtobits(column_real38);
column_real[39] = $realtobits(column_real39);
column_real[40] = $realtobits(column_real40);
column_real[41] = $realtobits(column_real41);
column_real[42] = $realtobits(column_real42);
column_real[43] = $realtobits(column_real43);
column_real[44] = $realtobits(column_real44);
column_real[45] = $realtobits(column_real45);
column_real[46] = $realtobits(column_real46);
chan_val[0] = column_real[temperature_index];
chan_val[1] = column_real[vccint_index];
chan_val[2] = column_real[vccaux_index];
chan_val[3] = column_real[vp_index];
chan_val[6] = column_real[vbram_index];
chan_val[13] = column_real[vccpint_index];
chan_val[14] = column_real[vccpaux_index];
chan_val[15] = column_real[vccpdro_index];
chan_val[16] = column_real[vauxp_idx0];
chan_val[17] = column_real[vauxp_idx1];
chan_val[18] = column_real[vauxp_idx2];
chan_val[19] = column_real[vauxp_idx3];
chan_val[20] = column_real[vauxp_idx4];
chan_val[21] = column_real[vauxp_idx5];
chan_val[22] = column_real[vauxp_idx6];
chan_val[23] = column_real[vauxp_idx7];
chan_val[24] = column_real[vauxp_idx8];
chan_val[25] = column_real[vauxp_idx9];
chan_val[26] = column_real[vauxp_idx10];
chan_val[27] = column_real[vauxp_idx11];
chan_val[28] = column_real[vauxp_idx12];
chan_val[29] = column_real[vauxp_idx13];
chan_val[30] = column_real[vauxp_idx14];
chan_val[31] = column_real[vauxp_idx15];
chan_val[32] = column_real[vuser0_index];
chan_val[33] = column_real[vuser1_index];
chan_val[34] = column_real[vuser2_index];
chan_val[35] = column_real[vuser3_index];
chan_valn[3] = column_real[vn_index];
chan_valn[16] = column_real[vauxn_idx0];
chan_valn[17] = column_real[vauxn_idx1];
chan_valn[18] = column_real[vauxn_idx2];
chan_valn[19] = column_real[vauxn_idx3];
chan_valn[20] = column_real[vauxn_idx4];
chan_valn[21] = column_real[vauxn_idx5];
chan_valn[22] = column_real[vauxn_idx6];
chan_valn[23] = column_real[vauxn_idx7];
chan_valn[24] = column_real[vauxn_idx8];
chan_valn[25] = column_real[vauxn_idx9];
chan_valn[26] = column_real[vauxn_idx10];
chan_valn[27] = column_real[vauxn_idx11];
chan_valn[28] = column_real[vauxn_idx12];
chan_valn[29] = column_real[vauxn_idx13];
chan_valn[30] = column_real[vauxn_idx14];
chan_valn[31] = column_real[vauxn_idx15];
// identify columns
if (time_index != -1) begin
prev_time_out = time_out;
time_out = $bitstoreal(column_real[time_index]);
if (prev_time_out > time_out) begin
$display("analog Data File Error : Time value %f is invalid in the input file for SYSMONE1 instance %m. Time value should increase.", time_out);
infile_format;
end
end
else begin
$display("analog Data File Error : No TIME label is found in the analog data file for SYSMONE1 instance %m.");
infile_format;
$finish;
end
# ((time_out - prev_time_out) * 1000);
for (p = 0; p < 36; p = p + 1) begin
// assign to real before minus - to work around a bug in modelsim
chan_val_tmp[p] = chan_val[p];
chan_valn_tmp[p] = chan_valn[p];
mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]);
mn_in_diff[p] = $realtobits(mn_in_tmp);
mn_in_uni[p] = chan_val[p];
end
// # ((time_out - prev_time_out) * 1000);
end // if (char_1 == "0" | char_1 == "9")
// Ignore any non-comment, label
else begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
end
end // while (end_file == 0)
end // if (sim_file_flag == 0)
end // initial begin
task infile_format;
begin
$display("\n***** SYSMONE1 Simulation analog Data File Format *****\n");
$display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n");
$display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] ..... \n");
$display("TIME must be in first column.\n");
$display("Time value need to be integer in ns scale.\n");
$display("analog value need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n");
$display("Each line including header line can not have extra space after the last character/digit.\n");
$display("Each data line must have same number of columns as the header line.\n");
$display("Comment line start with -- or //\n");
$display("Example:\n");
$display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n");
$display("000 125.6 1.0 0.7 0.4 0.3 0.6\n");
$display("200 25.6 0.8 0.5 0.3 0.8 0.2\n");
end
endtask //task infile_format
function [12*8:1] to_upcase_label;
input [12*8:1] in_label;
reg [8:1] tmp_reg;
begin
for (i=0; i< 12; i=i+1) begin
for (j=1; j<=8; j= j+1)
tmp_reg[j] = in_label[i*8+j];
if ((tmp_reg >96) && (tmp_reg<123))
tmp_reg = tmp_reg -32;
for (j=1; j<=8; j= j+1)
to_upcase_label[i*8+j] = tmp_reg[j];
end
end
endfunction
// end read input file
// Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only
always @( posedge busy_r )
begin
if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin
chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]);
chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]);
if ( chan_val_n_tmp > chan_val_p_tmp)
$display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for SYSMONE1 instance %m at %.3f ns.", acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0)
$display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for SYSMONE1 instance %m at %.3f ns.", acq_chan, chan_val_n_tmp, $time/1000.0);
end
end
reg seq_reset_busy_out = 0;
wire rst_in_out;
always @(posedge dclk_in or posedge rst_in_out)
if (rst_in_out) begin
busy_rst <= 1;
rst_lock <= 1;
rst_lock_early <= 1;
rst_lock_late <= 1;
busy_rst_cnt <= 0;
end
else begin
if (rst_lock == 1) begin
if (busy_rst_cnt < 29) begin
busy_rst_cnt <= busy_rst_cnt + 1;
if ( busy_rst_cnt == 26)
rst_lock_early <= 0;
end
else begin
busy_rst <= 0;
rst_lock = 0;
end
end
if (busy_out == 0)
rst_lock_late <= 0;
end
initial begin
busy_out = 0;
busy_rst = 0;
busy_conv = 0;
busy_seq_rst = 0;
busy_out_tmp = 0;
end
always @(busy_rst or busy_conv or rst_lock)
if (rst_lock)
busy_out = busy_rst;
else
busy_out = busy_conv;
always @(posedge dclk_in or posedge rst_in)
if (rst_in) begin
busy_conv <= 0;
cal_chan_update <= 0;
end
else begin
if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03) begin
busy_conv <= busy_seq_rst;
end
else if (busy_sync_fall)
busy_conv <= 0;
else if (busy_sync_rise)
busy_conv <= 1;
if (conv_count == 21 && curr_chan == 6'b001000)
cal_chan_update <= 1;
else
cal_chan_update <= 0;
end
always @(posedge dclk_in or rst_lock)
if (rst_lock) begin
busy_sync1 <= 0;
busy_sync2 <= 0;
end
else begin
busy_sync1 <= busy_r;
busy_sync2 <= busy_sync1;
end
assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0;
assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0;
always @(negedge busy_out or posedge busy_r)
if (seq_reset_flag == 1 && seq1_0 == 4'b0000 && curr_clkdiv_sel <= 8'h03) begin
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in)
busy_seq_rst <= 1;
end
else if (seq_reset_flag == 1 && seq1_0 != 4'b0000 && curr_clkdiv_sel <= 8'h03) begin
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in)
@(posedge dclk_in)
@(posedge dclk_in)
busy_seq_rst <= 1;
end
else
busy_seq_rst <= 0;
always @(posedge busy_out or posedge rst_in_out or negedge rst_lock_early)
if (rst_in_out)
muxaddr_out <= 5'b0;
else if (rst_lock_early == 0 && rst_lock_late == 1 )
muxaddr_out <= muxaddr_o;
else begin
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
// @(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk)
muxaddr_out <= muxaddr_o;
end
always @(negedge busy_out or posedge busy_out or posedge rst_in_out or posedge cal_chan_update )
if (rst_in_out || rst_lock_late)
channel_out <= 5'b0;
else if (busy_out ==1 && (cal_chan_update == 1) )
channel_out <= 5'b01000;
else if (busy_out == 0) begin
if ((curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0) || sysmone12_en == 1)
channel_out <= curr_chan;
else
channel_out <= 5'b0;
curr_chan_lat <= curr_chan;
end
// START double latch rst_in
reg rst_in1_tmp5;
reg rst_in2_tmp5;
reg rst_in1_tmp6;
reg rst_in2_tmp6;
wire rst_input_t;
wire rst_in2;
initial begin
int_rst = 1;
@(posedge dclk_in)
@(posedge dclk_in)
int_rst <= 0;
end
initial begin
rst_in1_tmp5 = 0;
rst_in2_tmp5 = 0;
rst_in1_tmp6 = 0;
rst_in2_tmp6 = 0;
end
assign #1 rst_input_t = rst_input | int_rst | soft_reset;
always@(posedge adcclk or posedge rst_input_t)
if (rst_input_t) begin
rst_in2_tmp6 <= 1;
rst_in1_tmp6 <= 1;
end
else begin
rst_in2_tmp6 <= rst_in1_tmp6;
rst_in1_tmp6 <= rst_input_t;
end
assign rst_in2 = rst_in2_tmp6;
assign #10 rst_in_not_seq = rst_in2;
assign rst_in = rst_in_not_seq | seq_reset_dly;
assign rst_in_out = rst_in_not_seq | seq_reset_busy_out;
always @(posedge seq_reset) begin
@(posedge dclk_in);
@(posedge dclk_in)
seq_reset_dly <= 1;
@(posedge dclk_in);
@(negedge dclk_in)
seq_reset_busy_out <= 1;
@(posedge dclk_in)
@(posedge dclk_in)
@(posedge dclk_in) begin
seq_reset_dly <= 0;
seq_reset_busy_out <= 0;
end
end
always @(posedge seq_reset_dly or posedge busy_r)
if (seq_reset_dly)
seq_reset_flag <= 1;
else
seq_reset_flag <= 0;
always @(posedge seq_reset_flag or posedge busy_out)
if (seq_reset_flag)
seq_reset_flag_dly <= 1;
else
seq_reset_flag_dly <= 0;
always @(posedge busy_out )
if (seq_reset_flag_dly == 1 && acq_chan == 6'b001000 && seq1_0 == 4'b0000)
first_cal_chan <= 1;
else
first_cal_chan <= 0;
initial begin
conv_time = 18; //minus 3
conv_time_cal_1 = 96;
conv_time_cal = 96;
sysclk = 0;
adcclk_tmp = 0;
seq_count = 1;
seq_count_a = 1;
seq_count2 = 1;
eos_en = 0;
eos_tmp_en = 0;
clk_count = -1;
acq_acqsel = 0;
acq_e_c_tmp6 = 0;
acq_e_c_tmp5 = 0;
eoc_en = 0;
eoc_en_delay = 0;
rst_lock = 0;
rst_lock_early = 0;
alarm_update = 0;
drp_update = 0;
cal_chan_update = 0;
adc_state = S3_ST;
scon_tmp = 5'b0;
busy_r = 0;
busy_r_rst = 0;
busy_sync1 = 0;
busy_sync2 = 0;
conv_count = 0;
conv_end = 0;
seq_status_avg = 0;
seq_status_avg2 = 0;
for (i = 0; i <=20; i = i +1)
begin
conv_pj_count[i] = 0;
conv_acc[j] = 0;
end
adc_s1_flag = 0;
for (k = 0; k <= 31; k = k + 1) begin
data_reg[k] = 16'b0;
end
seq_count_en = 0;
eos_out_tmp = 0;
eoc_out_tmp = 0;
eos_out_tmp1 = 0;
eoc_out_tmp1 = 0;
eos_out = 0;
eoc_out = 0;
eoc_out_t = 0;
curr_pj_set = 2'b0;
curr_e_c = 0;
curr_b_u = 0;
curr_acq = 0;
curr_seq1_0 = 4'b0;
curr_seq1_0_lat = 4'b0;
seq1_0 = 4'b0;
ext_mux = 0;
ext_mux_chan = 5'b0;
daddr_in_lat = 8'b0;
data_reg[32] = 16'b0;
data_reg[33] = 16'b0;
data_reg[34] = 16'b0;
data_reg[35] = 16'b0;
data_reg[36] = 16'b1111111111111111;
data_reg[37] = 16'b1111111111111111;
data_reg[38] = 16'b1111111111111111;
data_reg[39] = 16'b1111111111111111;
data_reg[40] = 16'b0;
data_reg[41] = 16'b0;
data_reg[42] = 16'b0;
data_reg[43] = 16'b0;
data_reg[44] = 16'b1111111111111111;
data_reg[45] = 16'b1111111111111111;
data_reg[46] = 16'b1111111111111111;
data_reg[47] = 16'b1111111111111111;
ot_out_reg = 0;
ot_out = 0;
alarm_out_reg = 16'b0;
alarm_out = 16'b0;
curr_chan = 6'b0;
curr_chan_lat = 6'b0;
busy_out = 0;
busy_out_tmp = 0;
curr_seq = 16'b0;
curr_seq_m = 16'b0;
seq_num = 0;
seq_num2 = 0;
seq_reset_flag_dly = 0;
seq_reset_flag = 0;
seq_reset_dly = 0;
ot_en = 1;
alarm_en = 13'h1fff;
do_out_rdtmp = 16'b0;
acq_chan = 6'b0;
acq_chan_m = 5'b0;
acq_b_u = 0;
conv_result_int = 0;
conv_result = 0;
conv_result_reg = 0;
end
// state machine
always @(posedge adcclk or posedge rst_in or sim_file_flag) begin
//CR 675227
if (!(halt_adc == 2 && seq1_0 == 4'b0011)) begin
if (sim_file_flag == 1'b1)
adc_state <= S1_ST;
else if (rst_in == 1'b1 || rst_lock_early == 1)
adc_state <= S1_ST;
else if (rst_in == 1'b0)
adc_state <= next_state;
end
end
always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin
case (adc_state)
S1_ST : next_state = S2_ST;
S2_ST : if (conv_start)
next_state = S3_ST;
else
next_state = S2_ST;
S3_ST : if (conv_end)
next_state = S5_ST;
else
next_state = S3_ST;
S5_ST : if (curr_seq1_0_lat == 4'b0001)
begin
//CR 675227 if (eos_en)
if (eos_tmp_en)
next_state = S6_ST;
else
next_state = S2_ST;
end
else
next_state = S2_ST;
S6_ST : next_state = S1_ST;
default : next_state = S1_ST;
endcase // case(adc_state)
end
// end state machine
// DRPORT - SRAM
initial begin
drdy_out = 0;
drdy_out_tmp1 = 0;
drdy_out_tmp2 = 0;
drdy_out_tmp3 = 0;
drdy_out_tmp4 = 0;
en_data_flag = 0;
do_out = 16'b0;
seq_reset = 0;
cfg_reg1_init = INIT_41_reg;
seq_en = 0;
seq_en_dly = 0;
seq_en <= #20 (cfg_reg1_init[15:12] != 4'b0011 ) ? 1 : 0;
seq_en <= #150 0;
end
always @(posedge drdy_out_tmp3 or posedge gsr_in)
if (gsr_in == 1)
drdy_out <= 0;
else begin
@(posedge dclk_in)
drdy_out <= 1;
@(posedge dclk_in)
drdy_out <= 0;
end
always @(posedge dclk_in or posedge gsr_in)
if (gsr_in == 1) begin
daddr_in_lat <= 8'b0;
do_out <= 16'b0;
end
else begin
if (den_in == 1'b1) begin
if (drdy_out_tmp1 == 1'b0) begin
drdy_out_tmp1 <= 1'b1;
en_data_flag = 1;
daddr_in_lat <= daddr_in;
end
else begin
if (daddr_in != daddr_in_lat)
$display("Warning : input pin DEN on SYSMONE1 instance %m at time %.3f ns can not continue set to high. Need wait DRDY high and then set DEN high again.", $time/1000.0);
end
end // if (den_in == 1'b1)
else
drdy_out_tmp1 <= 1'b0;
drdy_out_tmp2 <= drdy_out_tmp1;
drdy_out_tmp3 <= drdy_out_tmp2;
if (drdy_out_tmp1 == 1)
en_data_flag = 0;
if (drdy_out_tmp3 == 1)
do_out <= do_out_rdtmp;
if (den_in == 1 && (daddr_in >8'hAD || (daddr_in > 8'hA5 && daddr_in < 8'hA8) || (daddr_in > 8'h85 && daddr_in < 8'hA0) || (daddr_in > 8'h79 && daddr_in < 8'h80) || (daddr_in > 8'h75 && daddr_in < 8'h78) || (daddr_in > 8'h6D && daddr_in < 8'h73) || (daddr_in > 8'h65 && daddr_in < 8'h68) || (daddr_in > 8'h38 && daddr_in < 8'h3C) || (daddr_in > 8'h32 && daddr_in < 8'h38) || daddr_in == 8'h2B || daddr_in == 8'h2F))
$display("Invalid Input Warning : The DADDR %x to SYSMONE1 instance %m at time %.3f ns is accessing an undefined location. The data in this location is invalid.", daddr_in, $time/1000.0);
// write all available daddr addresses
if (dwe_in == 1'b1 && en_data_flag == 1) begin
dr_sram[daddr_in] <= di_in;
if (daddr_in == 8'h03)
soft_reset <= 1;
if ( daddr_in == 8'h53) begin
if (di_in[3:0] == 4'b0011)
ot_limit_reg[15:4] <= di_in[15:4];
end
if ( daddr_in == 8'h42 && (di_in[2:0] !=3'b000))
$display(" Invalid Input Error : The DI bit[2:0] %x at DADDR %x on SYSMONE1 instance %m at %.3f ns is invalid. These must be set to 000.", di_in[2:0], daddr_in, $time/1000.0);
if ( daddr_in >= 8'h73 && daddr_in <= 8'h75 && (di_in[15:0] != 16'h0000))
$display(" Invalid Input Error : The DI value %x at DADDR %x of SYSMONE1 instance %m at %.3f ns is invalid. These must be set to 0000h.", di_in, daddr_in, $time/1000.0);
if ((daddr_in == 8'h40) && ( di_in[5:0] == 6'b000111 || (di_in[5:0] > 6'b001000 && di_in[5:0] < 6'b010000)))
$display("Invalid Input Warning : The DI bit [5:0] at address DADDR %x to SYSMONE1 instance %m at %.3f ns is %h, which is an invalid analog channel.", daddr_in, $time/1000.0, di_in[5:0]);
if (daddr_in == 8'h40) begin
if ((cfg_reg1[15:12]==4'b0011) && (di_in[8]==1) && (di_in[5:0] != 6'b000011) && (di_in[5:0] < 6'b010000))
$display(" Invalid Input warning : The DI value is %x at DADDR %x on SYSMONE1 instance %m at %.3f ns. Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels", di_in, daddr_in, $time/1000.0);
// if ((cfg_reg1[15:12]==4'b0011) && (di_in[9]==1) && (di_in[5:0] != 6'b000011) && (di_in[5:0] < 6'b010000))
// $display(" Invalid Input warning : The DI value is %x at DADDR %x on SYSMONE1 instance %m at %.3f ns. Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels", di_in, daddr_in, $time/1000.0);
if ((cfg_reg1[15:12]==4'b0011) && (di_in[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000) && (seq_chan_reg3 != 16'h0000))
$display(" Invalid Input warning : The Control Regiter 46h, 48h and 49h are %x, %x and %x on SYSMONE1 instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg3, seq_chan_reg1, seq_chan_reg2, $time/1000.0);
end
if (daddr_in == 8'h40 && en_data_flag == 1) begin
if ((di_in[15:12]==4'b0011) && (cfg_reg0[8]==1) && (cfg_reg0[5:0] != 6'b000011) && (cfg_reg0[5:0] < 6'b010000))
$display(" Invalid Input warning : The Control Regiter 40h value is %x on SYSMONE1 instance %m at %.3f ns. Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels", cfg_reg0, $time/1000.0);
// if ((di_in[15:12]==4'b0011) && (cfg_reg0[9]==1) && (cfg_reg0[4:0] != 6'b000011) && (cfg_reg0[5:0] < 6'b010000))
// $display(" Invalid Input warning : The Control Regiter 40h value is %x on SYSMONE1 instance %m at %.3f ns. Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels", cfg_reg0, $time/1000.0);
if ((di_in[15:12]!=4'b0011) && (seq_acq_reg1[10:0]!=11'b0) && (seq_acq_reg1[15:12]!=4'b0))
$display(" Invalid Input warning : The Control Regiter 4Eh value is %x on SYSMONE1 instance %m at %.3f ns. Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels", seq_acq_reg1, $time/1000.0);
if ((di_in[15:12]==4'b0011) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000) && (seq_chan_reg3 != 16'h0000))
$display(" Invalid Input warning : The Control Regiter 46h, 48h and 49h are %x, %x and %x on SYSMONE1 instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg3, seq_chan_reg1, seq_chan_reg2, $time/1000.0);
end
if (daddr_in == 8'h41 && en_data_flag == 1) begin
if (den_in == 1'b1 && dwe_in == 1'b1) begin
if (di_in[15:12] != cfg_reg1[15:12])
seq_reset <= 1'b1;
else
seq_reset <= 1'b0;
if (di_in[15:12] != 4'b0011 )
seq_en <= 1'b1;
else
seq_en <= 1'b0;
end
else begin
seq_reset <= 1'b0;
seq_en <= 1'b0;
end
end
end // dwe ==1
if (seq_en == 1)
seq_en <= 1'b0;
if (seq_reset == 1)
seq_reset <= 1'b0;
if (soft_reset == 1)
soft_reset <= 0;
end // if (gsr == 1)
// DO bus data out
assign tmp_dr_sram_out = ( daddr_in_lat >= 8'h40 && daddr_in_lat <= 8'hAD) ?
dr_sram[daddr_in_lat] : 16'b0;
assign flag_reg0 = {8'b0, alarm_out[6:3], ot_out, alarm_out[2:0]};
assign flag_reg1 = {10'b0, alarm_out[13:8]};
assign tmp_data_reg_out = (daddr_in_lat >= 8'h00 && daddr_in_lat <= 8'h3D) ?
data_reg[daddr_in_lat] : 16'b0;
always @( daddr_in_lat or tmp_data_reg_out or tmp_dr_sram_out or flag_reg0 or flag_reg1 ) begin
if ((daddr_in_lat > 8'hAD || (daddr_in_lat >= 8'h86 && daddr_in_lat < 8'hA0))) begin
do_out_rdtmp = 16'bx;
end
if (daddr_in_lat == 8'h3E)
do_out_rdtmp = flag_reg1;
else if (daddr_in_lat == 8'h3F)
do_out_rdtmp = flag_reg0;
if ((daddr_in_lat >= 8'h00 && daddr_in_lat <= 8'h3D))
do_out_rdtmp = tmp_data_reg_out;
else if (daddr_in_lat >= 8'h40 && daddr_in_lat <= 8'hAD)
do_out_rdtmp = tmp_dr_sram_out;
end
// end DRP RAM
assign cfg_reg0 = dr_sram[8'h40];
assign cfg_reg1 = dr_sram[8'h41];
assign cfg_reg2 = dr_sram[8'h42];
assign cfg_reg3 = dr_sram[8'h43];
assign seq_chan_reg1 = dr_sram[8'h48];
assign seq_chan_reg2 = dr_sram[8'h49];
assign seq_chan_reg3 = dr_sram[8'h46];
assign seq_pj_reg1 = dr_sram[8'h4A];
assign seq_pj_reg2 = dr_sram[8'h4B];
assign seq_pj_reg3 = dr_sram[8'h47];
assign seq_du_reg1 = dr_sram[8'h4C];
assign seq_du_reg2 = dr_sram[8'h4D];
assign seq_du_reg3 = dr_sram[8'h78];
assign seq_acq_reg1 = dr_sram[8'h4E];
assign seq_acq_reg2 = dr_sram[8'h4F];
assign seq_acq_reg3 = dr_sram[8'h79];
always @(cfg_reg1)
seq1_0 = cfg_reg1[15:12];
always @(cfg_reg0) begin
ext_mux = cfg_reg0[11];
ext_mux_chan = cfg_reg0[4:0];
end
always @(posedge drp_update or posedge rst_in)
begin
if (rst_in) begin
@(posedge dclk_in)
@(posedge dclk_in)
seq_bits = seq1_0;
end
else
seq_bits = curr_seq1_0;
if (seq_bits == 4'b0000) begin
alarm_en <= 13'b0;
ot_en <= 1;
end
else begin
ot_en <= ~cfg_reg1[0];
alarm_en[2:0] <= ~cfg_reg1[3:1];
alarm_en[6:3] <= ~cfg_reg1[11:8];
alarm_en[11:8] <= ~cfg_reg3[3:0];
end
end
// end DRPORT - sram
//////////////////////////////////////// I2C start /////////////////////////////////////
reg i2c_sda_in_sync, i2c_sda_in_sync_d1, i2c_sda_in_sync_d2;
reg i2c_sclk_in_sync, i2c_sclk_in_sync_d1, i2c_sclk_in_sync_d2;
reg detect_ack;
integer byte_cnt = 0;
integer bit_cnt = 8;
integer i2c_sda_setup_cnt;
reg [31:0] i2c_data_in = 32'b0;
reg [7:0] i2c_data_in70 = 8'b0;
reg [7:0] i2c_data_in158 = 8'b0;
reg [7:0] i2c_data_in2316 = 8'b0;
reg [7:0] i2c_data_in3124 = 8'b0;
reg [7:0] i2c_sda_out_70_tmp;
reg [7:0] i2c_sda_out_158_tmp;
reg [7:0] i2c_address;
reg i2c_clk = 0;
reg [15:0] data_ff = 16'b0;
reg [7:0] addr_ff = 8'b0;
reg den_ff = 0;
reg dwe_ff = 0;
reg addr_match = 0;
reg new_written_data = 0;
reg i2c_start = 0;
reg i2c_stop = 0;
reg [2:0] i2c_state;
reg [6:0] i2c_addr;
reg [7:0] i2c_header = 8'b0;
reg sclk_falling_sync, sclk_rising_sync;
reg sclk_falling_sync_d3, sclk_falling_sync_d2, sclk_falling_sync_d1;
reg i2c_sda_xmit;
parameter IDLE = 3'b000,
HEADER = 3'b001,
ACK_HEADER = 3'b010,
RCV_DATA = 3'b011,
ACK_DATA = 3'b100,
XMIT_DATA = 3'b101,
WAIT_ACK = 3'b110;
initial forever #10000 i2c_clk = ~i2c_clk; // 50 Mhz oscillator
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input) begin
i2c_sda_in_sync <= 0;
i2c_sda_in_sync_d1 <= 0;
i2c_sda_in_sync_d2 <= 0;
i2c_sclk_in_sync <= 0;
i2c_sclk_in_sync_d1 <= 0;
i2c_sclk_in_sync_d2 <= 0;
end
else begin
i2c_sda_in_sync <= i2c_sda_in;
i2c_sda_in_sync_d1 <= i2c_sda_in_sync;
i2c_sda_in_sync_d2 <= i2c_sda_in_sync_d1;
i2c_sclk_in_sync <= i2c_sclk_in;
i2c_sclk_in_sync_d1 <= i2c_sclk_in_sync;
i2c_sclk_in_sync_d2 <= i2c_sclk_in_sync_d1;
end
end
assign sda_falling = i2c_sda_in_sync_d2 & ~i2c_sda_in_sync_d1;
assign sda_rising = ~i2c_sda_in_sync_d2 & i2c_sda_in_sync_d1;
assign sda_changing = sda_falling | sda_rising;
// detect i2c start
always @(posedge i2c_clk or posedge rst_input) begin
if(rst_input)
i2c_start = 1'b0;
else if (cfg_reg3[7] == 1'b1) begin
if (i2c_state == HEADER)
i2c_start = 1'b0;
else begin
if(i2c_sda_in_sync_d2 && ~i2c_sda_in_sync_d1) begin
if(i2c_sclk_in_sync_d1) begin
i2c_start = 1'b1;
end
else
i2c_start = 1'b0;
end
end
end
end
// detect i2c stop
always @(posedge i2c_clk or posedge rst_input) begin
if(rst_input)
i2c_stop <= 1'b0;
else if (cfg_reg3[7] == 1'b1) begin
if(~i2c_sda_in_sync_d2 & i2c_sda_in_sync_d1) begin
if(i2c_sclk_in_sync_d1)
i2c_stop <= 1'b1;
else
i2c_stop <= 1'b0;
end
end
end
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input) begin
sclk_falling_sync <= 0;
sclk_rising_sync <= 0;
end
else begin
sclk_falling_sync <= i2c_sclk_in_sync_d2 & ~i2c_sclk_in_sync_d1;
sclk_falling_sync_d1 <= sclk_falling_sync;
sclk_falling_sync_d2 <= sclk_falling_sync_d1;
sclk_falling_sync_d3 <= sclk_falling_sync_d2;
sclk_rising_sync <= ~i2c_sclk_in_sync_d2 & i2c_sclk_in_sync_d1;
end
end
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input)
detect_ack <= 0;
else
if (sclk_rising_sync)
detect_ack <= i2c_sda_in_sync_d1; // 0 = ack, 1 nack
end
// I2C slave address mapping
always @(cfg_reg3[15:7] or data_reg[3]) begin
if (cfg_reg3[7] == 1'b1) begin
if (cfg_reg3[15] == 1'b1)
i2c_addr = cfg_reg3[14:8];
else begin
case (data_reg[3][15:12])
4'h0 : i2c_addr = 7'b0110010;
4'h1 : i2c_addr = 7'b0001011;
4'h2 : i2c_addr = 7'b0010011;
4'h3 : i2c_addr = 7'b0011011;
4'h4 : i2c_addr = 7'b0100011;
4'h5 : i2c_addr = 7'b0101011;
4'h6 : i2c_addr = 7'b0110011;
4'h7 : i2c_addr = 7'b0111011;
4'h8 : i2c_addr = 7'b1000011;
4'h9 : i2c_addr = 7'b1001011;
4'ha : i2c_addr = 7'b1010011;
4'hb : i2c_addr = 7'b1011011;
4'hc : i2c_addr = 7'b1100011;
4'hd : i2c_addr = 7'b1101011;
4'he : i2c_addr = 7'b1110011;
4'hf : i2c_addr = 7'b0111010;
endcase
end // else: !if(cfg_reg3[15] == 1'b1)
end // if (cfg_reg3[7] == 1'b1)
end // always @ (cfg_reg3[15:7] or data_reg[3])
always @(posedge i2c_clk or posedge rst_input) begin // I2C FSM
if(rst_input) begin
i2c_state <= IDLE;
end
else if (sclk_falling_sync_d2) begin
case (i2c_state)
IDLE : begin
if(i2c_start)
i2c_state <= HEADER;
end
HEADER : begin
if(bit_cnt == 0)
i2c_state <= ACK_HEADER;
end
ACK_HEADER : begin
if(detect_ack == 1'b0) begin // Ack has been received
if(addr_match) begin // If aas_ff is true then addressed as slave
if(i2c_header[0] == 1'b0) begin // Check i2c_header[0] to determine direction
i2c_state <= RCV_DATA; // Receive Mode
end
else begin
i2c_state <= XMIT_DATA; // Transmit Mode
end
end
else begin
i2c_state <= IDLE;
end
end
end
RCV_DATA : begin
if(i2c_start) begin
i2c_state <= HEADER;
end
else if(bit_cnt == 0) begin
i2c_state <= ACK_DATA;
end
end
XMIT_DATA : begin
if(i2c_start) begin
i2c_state <= HEADER;
end
else if(bit_cnt == 1) begin // after transmitted 8 bit now wait for acknowledge
i2c_state <= WAIT_ACK;
end
end
ACK_DATA : begin
if (detect_ack == 1'b0)
i2c_state <= RCV_DATA;
else // NACK received
i2c_state <= IDLE;
end
WAIT_ACK : begin
if(detect_ack == 1'b0) begin // wait for acknowlege from master 0 ack, 1 nack
i2c_state <= XMIT_DATA;
end
else begin
i2c_state <= IDLE;
end
end
default : begin
i2c_state <= IDLE;
end
endcase
if(i2c_stop) begin
i2c_state <= IDLE;
end
end
end
// bit count from 8 to 1 -> bit 7 to bit 0
always @(posedge i2c_clk or posedge rst_input) begin
if((rst_input) || (i2c_state == IDLE) || (i2c_state == ACK_HEADER) || (i2c_state == ACK_DATA) ||
(i2c_state == WAIT_ACK) || i2c_start) begin
bit_cnt <= 8;
end
else if(((i2c_state == HEADER) && sclk_falling_sync) ||
((i2c_state == RCV_DATA) && sclk_falling_sync) ||
((i2c_state == XMIT_DATA) && sclk_falling_sync_d2)) begin
bit_cnt <= bit_cnt - 1;
end
end // always @ (posedge i2c_clk or posedge rst_input)
// byte count
always @(posedge i2c_clk or posedge rst_input) begin
if((rst_input) || (i2c_state == IDLE) || (i2c_state == ACK_HEADER) || i2c_start) begin
byte_cnt <= 0;
end
else if ((i2c_state == RCV_DATA && sclk_falling_sync_d1 && byte_cnt <= 3 && bit_cnt == 0) ||
(i2c_state == XMIT_DATA && sclk_falling_sync_d1 && byte_cnt <= 1 && bit_cnt == 1)) begin
byte_cnt <= byte_cnt + 1;
end
end
// Getting I2C header
always @(posedge i2c_clk) begin
if (!rst_input)
if (i2c_state == HEADER && sclk_rising_sync && bit_cnt > 0)
i2c_header <= {i2c_header[6:0], i2c_sda_in_sync_d1};
end
// matching I2C slave address from i2c_sda bus
always @(i2c_header[7:1] or i2c_addr) begin
if(i2c_header[7:1] == i2c_addr[6:0])
addr_match = 1'b1;
else
addr_match = 1'b0;
end
// I2C Data recevie
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input) begin
i2c_data_in70 <= 8'b0;
i2c_data_in158 <= 8'b0;
i2c_data_in2316 <= 8'b0;
i2c_data_in3124 <= 8'b0;
end
else begin
if (i2c_state == RCV_DATA && sclk_rising_sync && ~i2c_start && bit_cnt > 0)
if (byte_cnt == 0)
i2c_data_in70 <= {i2c_data_in70[6:0], i2c_sda_in_sync_d1};
else if (byte_cnt == 1)
i2c_data_in158 <= {i2c_data_in158[6:0], i2c_sda_in_sync_d1};
else if (byte_cnt == 2)
i2c_data_in2316 <= {i2c_data_in2316[6:0], i2c_sda_in_sync_d1};
else if (byte_cnt == 3)
i2c_data_in3124 <= {i2c_data_in3124[6:0], i2c_sda_in_sync_d1};
end // else: !if(i2c_stop)
end
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input)
i2c_data_in <= 32'b0;
else
if (bit_cnt == 0 && byte_cnt == 4) begin
i2c_data_in <= {i2c_data_in3124, i2c_data_in2316, i2c_data_in158, i2c_data_in70};
new_written_data = 1;
end
else
new_written_data = 0;
end
// Decode I2C incoming data
always@(posedge i2c_clk or posedge rst_input) begin
if(rst_input) begin
data_ff <= 16'b0;
addr_ff <= 8'b0;
den_ff <= 1'b0;
dwe_ff <= 1'b0;
end
else begin
if(new_written_data) begin
data_ff <= i2c_data_in[15:0];
addr_ff <= i2c_data_in[23:16];
case(i2c_data_in[29:26])
4'b0001: begin
den_ff <= 1'b1;
dwe_ff <= 1'b0;
end
4'b0010: begin
den_ff <= 1'b1;
dwe_ff <= 1'b1;
end
default: begin
den_ff <= 1'b0;
dwe_ff <= 1'b0;
end
endcase
if (den_ff == 1'b1 && dwe_ff == 1'b1) begin // write
if (addr_ff >= 8'h40 && addr_ff <= 8'h79)
dr_sram[addr_ff] <= data_ff;
end
else if (den_ff == 1'b1 && dwe_ff == 1'b0) begin // read
if (addr_ff >= 64) begin
i2c_sda_out_70_tmp <= dr_sram[addr_ff][7:0];
i2c_sda_out_158_tmp <= dr_sram[addr_ff][15:8];
end
else if (addr_ff < 64) begin
i2c_sda_out_70_tmp <= data_reg[addr_ff][7:0];
i2c_sda_out_158_tmp <= data_reg[addr_ff][15:8];
end
end
end
end
end // always@ (posedge i2c_clk or posedge rst_input)
// clock stretching
always @(posedge i2c_clk or posedge rst_input) begin
if(rst_input) begin
i2c_sda_setup_sync <= 1'b1;
end
else begin
if((i2c_sda_in != i2c_sda_in_sync) && ~i2c_sclk_in) begin
i2c_sda_setup_sync <= 1'b0;
end
else if(i2c_sda_setup_cnt == 15) begin // i2c_clk predefined by HW as 15
i2c_sda_setup_sync <= 1'b1;
end
end
end
always @(posedge i2c_clk or sda_changing or rst_input) begin
if (rst_input)
i2c_sda_setup_cnt = 0;
else if (sda_changing)
i2c_sda_setup_cnt = 1;
else if (i2c_sda_setup_sync == 1'b0)
i2c_sda_setup_cnt = i2c_sda_setup_cnt + 1;
end
// I2C Data transmit
always @(posedge i2c_clk) begin
if(i2c_state == XMIT_DATA && sclk_falling_sync_d3 && ~i2c_start) begin // as transmitter
if (den_ff == 1'b1 && dwe_ff == 1'b0) begin // read
if (byte_cnt == 0) begin
i2c_sda_xmit <= i2c_sda_out_70_tmp[7];
i2c_sda_out_70_tmp <= i2c_sda_out_70_tmp << 1;
end
else if (byte_cnt == 1) begin
i2c_sda_xmit <= i2c_sda_out_158_tmp[7];
i2c_sda_out_158_tmp <= i2c_sda_out_158_tmp << 1;
end
end
end
end
// sending sda out
always @(posedge i2c_clk or posedge rst_input) begin
if (rst_input) begin
i2c_sda_out_tmp <= 1'b1;
end
else begin
if ((addr_match && i2c_state == ACK_HEADER) || (i2c_state == ACK_DATA)) // send ACK
i2c_sda_out_tmp <= 1'b0;
else if (i2c_state == XMIT_DATA)
i2c_sda_out_tmp <= i2c_sda_xmit;
else
i2c_sda_out_tmp <= 1'b1;
end
end
/////////////////////////////////////////// I2C end /////////////////////////////////////////
// Clock divider, generate and adcclk
always @(posedge dclk_in)
sysclk <= ~sysclk;
always @(posedge dclk_in)
if (curr_clkdiv_sel > 8'b00000010 ) begin
if (clk_count >= curr_clkdiv_sel - 1)
clk_count = 0;
else
clk_count = clk_count + 1;
if (clk_count > (curr_clkdiv_sel/2) - 1)
adcclk_tmp <= 1;
else
adcclk_tmp <= 0;
end
else
adcclk_tmp <= ~adcclk_tmp;
assign curr_clkdiv_sel = cfg_reg2[15:8];
assign sysmone1_en = (cfg_reg2[5]===1 && cfg_reg2[4]===1) ? 0 : 1;
assign sysmone12_en = (cfg_reg2[5]===1 ) ? 0 : 1;
assign adcclk_div1 = (curr_clkdiv_sel > 8'b00000010) ? 0 : 1;
assign adcclk_r = (adcclk_div1) ? ~sysclk : adcclk_tmp;
assign adcclk = (sysmone1_en) ? adcclk_r : 0;
// end clock divider
// latch configuration registers
wire [15:0] cfg_reg0_seq, cfg_reg0_adc;
reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5;
reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6;
reg [1:0] acq_avg;
assign muxaddr_o = (rst_lock_early) ? 5'b0 : (curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0 || sysmone12_en == 1) ? acq_chan_m : 5'b0;
always @( seq1_0 or adc_s1_flag or curr_seq_m or cfg_reg0_adc or rst_in) begin
if (rst_in == 0) begin
if (seq1_0[3:2] == 2'b11) begin
acq_chan_m = curr_seq_m[4:0];
end
else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin
acq_chan_m = curr_seq_m[4:0];
end
else begin
acq_chan_m = cfg_reg0_adc[4:0];
end
end
end
//CR 675227 always @( seq1_0 or adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin
always @(adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin
if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010 || seq1_0[3:2] == 2'b11) begin
acq_acqsel = curr_seq[8];
end
else if (seq1_0 == 4'b0011) begin
acq_acqsel = cfg_reg0_adc[8];
end
else begin
acq_acqsel = 0;
end
if (rst_in == 0) begin
if (seq1_0[3:2] == 2'b11) begin
acq_avg = 2'b01;
acq_chan = curr_seq[5:0];
acq_b_u = 0;
end
else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin
acq_avg = curr_seq[13:12];
acq_chan = curr_seq[5:0];
acq_b_u = curr_seq[10];
end
else begin
acq_avg = cfg_reg0_adc[13:12];
acq_chan = cfg_reg0_adc[5:0];
acq_b_u = cfg_reg0_adc[10];
//CR 675227
if (seq1_0 == 4'b0001) begin
halt_adc = halt_adc + 1;
if (halt_adc == 2)
dr_sram[8'h41][15:12] = 4'b0011;
end
end
end
end
reg single_chan_conv_end;
reg [3:0] conv_end_reg_read;
reg busy_reg_read;
reg first_after_reset_tmp5;
reg first_after_reset_tmp6;
always@(posedge adcclk or posedge rst_in)
begin
if(rst_in) conv_end_reg_read <= 4'b0;
else conv_end_reg_read <= {conv_end_reg_read[2:0], single_chan_conv_end | conv_end};
end
always@(posedge DCLK or posedge rst_in)
begin
if(rst_in) busy_reg_read <= 1;
else busy_reg_read <= ~conv_end_reg_read[2];
end
// i2c write
assign cfg_reg0_adc = (i2c_stop) ? cfg_reg0 : cfg_reg0_adc_tmp6;
// assign cfg_reg0_adc = cfg_reg0_adc_tmp6;
assign cfg_reg0_seq = cfg_reg0_seq_tmp6;
assign acq_e_c = acq_e_c_tmp6;
always @(negedge busy_out or rst_in)
if(rst_in) begin
cfg_reg0_seq_tmp6 <= 16'b0;
cfg_reg0_adc_tmp6 <= 16'b0;
acq_e_c_tmp6 <= 0;
first_after_reset_tmp6 <= 1;
end
else begin
repeat(3) @(posedge DCLK);
if(first_after_reset_tmp6) begin
first_after_reset_tmp6<=0;
cfg_reg0_adc_tmp6 <= cfg_reg0;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
else begin
cfg_reg0_adc_tmp6 <= cfg_reg0_seq;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
acq_e_c_tmp6 <= cfg_reg0[9];
end
always @(posedge conv_start or posedge busy_r_rst or posedge rst_in)
if (rst_in ==1)
busy_r <= 0;
else if (conv_start && rst_lock == 0)
busy_r <= 1;
else if (busy_r_rst)
busy_r <= 0;
always @(negedge busy_out )
if (adc_s1_flag == 1)
curr_seq1_0 <= 4'b0000;
else
curr_seq1_0 <= seq1_0;
always @(posedge conv_start or rst_in )
if (rst_in == 1) begin
mn_mux_in <= 0.0;
curr_chan <= 6'b0;
end
else begin
if ((acq_chan == 6'b000011) || (acq_chan >= 6'b010000 && acq_chan <= 6'b011111)) begin
if (ext_mux == 1) begin
tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan]);
mn_mux_in <= tmp_v;
end
else begin
tmp_v = $bitstoreal(mn_in_diff[acq_chan]);
mn_mux_in <= tmp_v;
end
end
else
mn_mux_in <= $bitstoreal(mn_in_uni[acq_chan]);
tmp_seq1_0 = curr_seq1_0[3:2];
curr_chan <= acq_chan;
curr_seq1_0_lat <= curr_seq1_0;
if ( acq_chan == 6'b000111 || (acq_chan >= 6'b001001 && acq_chan <= 6'b001111) || acq_chan > 6'b100011)
$display("Invalid Input Warning : The analog channel %x to SYSMONE1 instance %m at %.3f ns is invalid.", acq_chan, $time/1000.0);
if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010 || seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) begin
curr_pj_set <= curr_seq[13:12];
curr_b_u <= curr_seq[10];
curr_e_c <= curr_seq[9];
curr_acq <= curr_seq[8];
end
else begin
curr_pj_set <= acq_avg;
curr_b_u <= acq_b_u;
curr_e_c <= cfg_reg0[9];
curr_acq <= cfg_reg0[8];
end
end // if (rst_in == 0)
// end latch configuration registers
// sequence control
always @(seq_en )
seq_en_dly <= #1 seq_en;
always @(posedge seq_en_dly)
if (seq1_0 == 4'b0001 || seq1_0 == 4'b0010) begin
seq_num = 0;
for (si=0; si<= 15; si=si+1) begin
if (seq_chan_reg1[si] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
for (si=16; si<= 31; si=si+1) begin
if (seq_chan_reg2[si-16] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
for (si=32; si<= 35; si=si+1) begin
if (seq_chan_reg3[si-32] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
end
else if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11) begin
seq_num = 5;
seq_mem[1] = 0;
seq_mem[2] = 8;
seq_mem[3] = 9;
seq_mem[4] = 10;
seq_mem[5] = 14;
end
always @( seq_count or negedge seq_en_dly) begin
seq_curr_i = seq_mem[seq_count];
curr_seq = 16'b0;
if (seq_curr_i >= 0 && seq_curr_i <= 15) begin
curr_seq [2:0] = seq_curr_i[2:0];
curr_seq [4:3] = 2'b01;
curr_seq [8] = seq_acq_reg1[seq_curr_i];
curr_seq [10] = seq_du_reg1[seq_curr_i];
if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11)
curr_seq [13:12] = 2'b01;
else if (seq_pj_reg1[seq_curr_i] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
if (seq_curr_i >= 0 && seq_curr_i <=7)
curr_seq [4:3] = 2'b01;
else
curr_seq [4:3] = 2'b00;
end
else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin
curr_seq [4:0] = seq_curr_i;
curr_seq [8] = seq_acq_reg2[seq_curr_i - 16];
curr_seq [10] = seq_du_reg2[seq_curr_i - 16];
if (seq_pj_reg2[seq_curr_i - 16] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
end // if (seq_curr_i >= 16 && seq_curr_i <= 31)
else if (seq_curr_i > 31 && seq_curr_i <= 35) begin
curr_seq [5:0] = seq_curr_i;
curr_seq [8] = seq_acq_reg3[seq_curr_i - 32];
curr_seq [10] = seq_du_reg3[seq_curr_i - 32];
if (seq_pj_reg3[seq_curr_i - 32] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
end
end
always @( seq_count_a or negedge seq_en_dly) begin
seq_curr_ia = seq_mem[seq_count_a];
curr_seq_m = 16'b0;
if (seq_curr_ia >= 0 && seq_curr_ia <= 15) begin
curr_seq_m [2:0] = seq_curr_ia[2:0];
curr_seq_m [4:3] = 2'b01;
curr_seq_m [8] = seq_acq_reg1[seq_curr_ia];
curr_seq_m [10] = seq_du_reg1[seq_curr_ia];
if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11)
curr_seq_m [13:12] = 2'b01;
else if (seq_pj_reg1[seq_curr_ia] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
if (seq_curr_ia >= 0 && seq_curr_ia <=7)
curr_seq_m [4:3] = 2'b01;
else
curr_seq_m [4:3] = 2'b00;
end
else if (seq_curr_ia >= 16 && seq_curr_ia <= 31) begin
curr_seq_m [4:0] = seq_curr_ia;
curr_seq_m [8] = seq_acq_reg2[seq_curr_ia - 16];
curr_seq_m [10] = seq_du_reg2[seq_curr_ia - 16];
if (seq_pj_reg2[seq_curr_ia - 16] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
end
else if (seq_curr_ia > 31 && seq_curr_ia <= 35) begin
curr_seq_m [5:0] = seq_curr_ia;
curr_seq_m [8] = seq_acq_reg3[seq_curr_ia - 32];
curr_seq_m [10] = seq_du_reg3[seq_curr_ia - 32];
if (seq_pj_reg3[seq_curr_ia - 32] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
end
end // always @ ( seq_count_a or negedge seq_en_dly)
always @(posedge busy_out or posedge rst_in )
if (rst_in == 1 || rst_lock == 1 ) begin
seq_count_a <= 1;
end
else begin
if ( curr_seq1_0_lat == 4'b0011 )
seq_count_a <= 1;
else begin
if (seq_count_a >= 32 || seq_count_a >= seq_num)
seq_count_a <= 1;
else
seq_count_a <= seq_count_a +1;
end
end
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1 ) begin
seq_count <= 1;
seq_count2 <= 1;
eos_en <= 0;
end
else begin
if ((seq_count == seq_num ) && (adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && rst_lock == 0)
eos_tmp_en <= 1;
else
eos_tmp_en <= 0;
if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk
eos_en <= 1;
else
eos_en <= 0;
if (eos_tmp_en == 1 || curr_seq1_0_lat == 4'b0011 )
seq_count <= 1;
else if (seq_count_en == 1) begin
if (seq_count >= 32)
seq_count <= 1;
else
seq_count <= seq_count +1;
end
end // else: !if(rst_in == 1)
// end sequence control
// Acquisition
reg first_acq;
reg shorten_acq;
wire busy_out_dly;
assign #10 busy_out_dly = busy_out;
always @(adc_state or posedge rst_in or first_acq)
begin
if(rst_in) shorten_acq = 0;
else if(busy_out_dly==0 && adc_state==S2_ST && first_acq==1)
shorten_acq = 1;
else
shorten_acq = 0;
end
always @(posedge adcclk or posedge rst_in)
// if (rst_in == 1) begin
if (rst_in == 1 || rst_lock == 1) begin
acq_count <= 1;
first_acq <=1;
end
else begin
if (adc_state == S2_ST && rst_lock == 0 && (acq_e_c==0)) begin
first_acq <= 0;
if (acq_acqsel == 1) begin
if (acq_count <= 11)
acq_count <= acq_count + 1 + shorten_acq;
end
else begin
if (acq_count <= 4)
acq_count <= acq_count + 1 + shorten_acq;
end // else: !if(acq_acqsel == 1)
if (next_state == S3_ST)
if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4))
$display ("Warning: Acquisition time is not long enough for SYSMONE1 instance %m at time %t.", $time);
end // if (adc_state == S2_ST)
else
acq_count <= (first_acq) ? 1 : 0;
end // if (rst_in == 0)
// continuous mode
reg conv_start_cont;
wire reset_conv_start;
wire conv_start_sel;
always @(adc_state or acq_acqsel or acq_count)
if (adc_state == S2_ST) begin
if (rst_lock == 0) begin
if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03))
&& ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) )
conv_start_cont = 1;
else
conv_start_cont = 0;
end
end // if (adc_state == S2_ST)
else
conv_start_cont = 0;
assign conv_start_sel = (acq_e_c) ? convst_in : conv_start_cont;
assign reset_conv_start = rst_in | (conv_count==2);
always@(posedge conv_start_sel or posedge reset_conv_start)
begin
if(reset_conv_start) conv_start <= 0;
else conv_start <= 1;
end
// end acquisition
// Conversion
always @(adc_state or next_state or curr_chan or mn_mux_in or curr_b_u) begin
if ((adc_state == S3_ST && next_state == S5_ST) || adc_state == S5_ST) begin
if (curr_chan == 0) begin // temperature conversion
adc_temp_result = (mn_mux_in + 273.15) * 0.001984226*65536;
if (adc_temp_result >= 65535.0)
conv_result_int = 65535;
else if (adc_temp_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_temp_result);
if (adc_temp_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 1 || curr_chan == 2 || curr_chan ==6 ||
curr_chan == 13 || curr_chan == 14 || curr_chan == 15 ||
(curr_chan >= 32 && curr_chan <= 35)) begin // internal power conversion
adc_intpwr_result = mn_mux_in * 65536.0 / 3.0;
if (adc_intpwr_result >= 65535.0)
conv_result_int = 65535;
else if (adc_intpwr_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_intpwr_result);
if (adc_intpwr_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin
adc_ext_result = (mn_mux_in) * 65536.0;
if (curr_b_u == 1) begin
if (adc_ext_result > 32767.0)
conv_result_int = 32767;
else if (adc_ext_result < -32768.0)
conv_result_int = -32768;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else begin
if (adc_ext_result > 65535.0)
conv_result_int = 65535;
else if (adc_ext_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
end
else begin
conv_result_int = 0;
end
end
conv_result = conv_result_int;
end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u)
reg busy_r_rst_done;
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
conv_count <= 6;
conv_end <= 0;
seq_status_avg <= 0;
busy_r_rst <= 0;
busy_r_rst_done <= 0;
for (i = 0; i <=31; i = i +1) begin
conv_pj_count[i] <= 0; // array of integer
end
single_chan_conv_end <= 0;
end
else begin
if(adc_state == S2_ST)
begin
if(busy_r_rst_done == 0) busy_r_rst <= 1;
else busy_r_rst <= 0;
busy_r_rst_done <= 1;
end
if (adc_state == S2_ST && conv_start == 1) begin
conv_count <= 0;
conv_end <= 0;
end
else if (adc_state == S3_ST ) begin
busy_r_rst_done <= 0;
conv_count = conv_count + 1;
if ((curr_chan != 5'b01000 ) && (conv_count == conv_time ) ||
(curr_chan == 5'b01000 ) && (conv_count == conv_time_cal_1 ) && (first_cal_chan==1)
|| (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal) && (first_cal_chan == 0))
conv_end <= 1;
else
conv_end <= 0;
end
else begin
conv_end <= 0;
conv_count <= 0;
end
// jmcgrath - to model the behaviour correctly when a cal chanel is being converted
// an signal to signify the conversion has ended must be produced - this is for single channel mode
single_chan_conv_end <= 0;
if( (conv_count == conv_time) || (conv_count == 44))
single_chan_conv_end <= 1;
if (adc_state == S3_ST && next_state == S5_ST && rst_lock == 0) begin
case (curr_pj_set)
2'b00 : begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
end
2'b01 : if (conv_pj_count[curr_chan] == 15) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
2'b10 : if (conv_pj_count[curr_chan] == 63) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
2'b11 : if (conv_pj_count[curr_chan] == 255) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
default : eoc_en <= 0;
endcase // case(curr_pj_set)
end // if (adc_state == S3_ST && next_state == S5_ST)
else begin
eoc_en <= 0;
end
if (adc_state == S5_ST) begin
conv_result_reg <= conv_result;
end
end // if (rst_in == 0)
// end conversion
// average
always @(adc_state or conv_acc[curr_chan])
if (adc_state == S5_ST )
// no signed or unsigned differences for bit vector conv_acc_vec
conv_acc_vec = conv_acc[curr_chan];
else
conv_acc_vec = 24'b00000000000000000000;
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
for (j = 0; j <= 31; j = j + 1) begin
conv_acc[j] <= 0;
end
conv_acc_result <= 16'b0000000000000000;
end
else begin
if (adc_state == S3_ST && next_state == S5_ST) begin
if (curr_pj_set != 2'b00 && rst_lock != 1)
conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int;
else
conv_acc[curr_chan] <= 0;
end // if (adc_state == S3_ST && next_state == S5_ST)
else if (eoc_en == 1) begin
case (curr_pj_set)
2'b00 : conv_acc_result <= 16'b0000000000000000;
2'b01 : conv_acc_result <= conv_acc_vec[19:4];
2'b10 : conv_acc_result <= conv_acc_vec[21:6];
2'b11 : conv_acc_result <= conv_acc_vec[23:8];
endcase
conv_acc[curr_chan] <= 0;
end
end // if (rst_in == 0)
// end average
// single sequence
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1)
adc_s1_flag <= 0;
else
if (adc_state == S6_ST)
adc_s1_flag <= 1;
// end state
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
seq_count_en <= 0;
eos_out_tmp <= 0;
eoc_out_tmp <= 0;
end
else begin
if ((adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && (rst_lock == 0))
seq_count_en <= 1;
else
seq_count_en <= 0;
if (rst_lock == 0) begin
eos_out_tmp <= eos_en;
eoc_en_delay <= eoc_en;
eoc_out_tmp <= eoc_en_delay;
end
else begin
eos_out_tmp <= 0;
eoc_en_delay <= 0;
eoc_out_tmp <= 0;
end
end
always @(eoc_out)
eoc_out_t <= #1 eoc_out;
always @(posedge eoc_out_t or posedge rst_in_not_seq)
if (rst_in_not_seq == 1) begin
for (k = 32; k <= 39; k = k + 1)
if (k >= 36)
data_reg[k] <= 16'b1111111111111111;
else
data_reg[k] <= 16'b0000000000000000;
for (k = 40; k <= 42; k = k + 1)
data_reg[k] <= 16'b0000000000000000;
for (k = 44; k <= 46; k = k + 1)
data_reg[k] <= 16'b1111111111111111;
end
else
if ( rst_lock == 0) begin
if (eoc_out == 1) begin
if ((curr_chan_lat >= 0 && curr_chan_lat <= 3) || (curr_chan_lat == 6) ||
(curr_chan_lat >= 13 && curr_chan_lat <= 31)) begin
if (curr_pj_set == 2'b00)
data_reg[curr_chan_lat] <= conv_result_reg;
else
data_reg[curr_chan_lat] <= conv_acc_result;
end
else if (curr_chan_lat >= 32 && curr_chan_lat <= 35) begin
if (curr_pj_set == 2'b00)
dr_sram[curr_chan_lat + 96] <= conv_result_reg;
else
dr_sram[curr_chan_lat + 96] <= conv_acc_result;
end
if (curr_chan_lat == 4)
data_reg[curr_chan_lat] <= 16'hD555;
if (curr_chan_lat == 5)
data_reg[curr_chan_lat] <= 16'h0000;
if (curr_chan_lat == 0 || curr_chan_lat == 1 || curr_chan_lat == 2) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_result_reg;
if (conv_result_reg < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_acc_result;
if (conv_acc_result < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_acc_result;
end
end
if (curr_chan_lat == 6) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[35])
data_reg[35] <= conv_result_reg;
if (conv_result_reg < data_reg[39])
data_reg[39] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[35])
data_reg[35] <= conv_acc_result;
if (conv_acc_result < data_reg[39])
data_reg[39] <= conv_acc_result;
end
end
if (curr_chan_lat == 13) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < data_reg[40])
data_reg[40] <= conv_result_reg;
if (conv_result_reg > data_reg[44])
data_reg[44] <= conv_result_reg;
end
else begin
if (conv_acc_result < data_reg[40])
data_reg[40] <= conv_acc_result;
if (conv_acc_result > data_reg[44])
data_reg[44] <= conv_acc_result;
end
end
if (curr_chan_lat == 14) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < data_reg[41])
data_reg[41] <= conv_result_reg;
if (conv_result_reg > data_reg[45])
data_reg[45] <= conv_result_reg;
end
else begin
if (conv_acc_result < data_reg[41])
data_reg[41] <= conv_acc_result;
if (conv_acc_result > data_reg[45])
data_reg[45] <= conv_acc_result;
end
end
if (curr_chan_lat == 15) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < data_reg[42])
data_reg[42] <= conv_result_reg;
if (conv_result_reg > data_reg[46])
data_reg[46] <= conv_result_reg;
end
else begin
if (conv_acc_result < data_reg[42])
data_reg[42] <= conv_acc_result;
if (conv_acc_result > data_reg[46])
data_reg[46] <= conv_acc_result;
end
end
if (curr_chan_lat == 32) begin //Vuser0
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < dr_sram[168])
dr_sram[168] <= conv_result_reg;
if (conv_result_reg > dr_sram[160])
data_reg[160] <= conv_result_reg;
end
else begin
if (conv_acc_result < dr_sram[168])
dr_sram[168] <= conv_acc_result;
if (conv_acc_result > dr_sram[160])
dr_sram[160] <= conv_acc_result;
end
end
if (curr_chan_lat == 33) begin //Vuser1
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < dr_sram[169])
dr_sram[169] <= conv_result_reg;
if (conv_result_reg > dr_sram[161])
data_reg[161] <= conv_result_reg;
end
else begin
if (conv_acc_result < dr_sram[169])
dr_sram[169] <= conv_acc_result;
if (conv_acc_result > dr_sram[161])
dr_sram[161] <= conv_acc_result;
end
end
if (curr_chan_lat == 34) begin //Vuser2
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < dr_sram[170])
dr_sram[170] <= conv_result_reg;
if (conv_result_reg > dr_sram[162])
data_reg[162] <= conv_result_reg;
end
else begin
if (conv_acc_result < dr_sram[170])
dr_sram[170] <= conv_acc_result;
if (conv_acc_result > dr_sram[162])
dr_sram[162] <= conv_acc_result;
end
end
if (curr_chan_lat == 35) begin //Vuser3
if (curr_pj_set == 2'b00) begin
if (conv_result_reg < dr_sram[171])
dr_sram[171] <= conv_result_reg;
if (conv_result_reg > dr_sram[163])
data_reg[163] <= conv_result_reg;
end
else begin
if (conv_acc_result < dr_sram[171])
dr_sram[171] <= conv_acc_result;
if (conv_acc_result > dr_sram[163])
dr_sram[163] <= conv_acc_result;
end
end
end // if (eoc_out == 1)
end // if ( rst_lock == 0)
reg [15:0] data_written;
always @(negedge busy_r or posedge rst_in_not_seq)
if (rst_in_not_seq)
data_written <= 16'b0;
else begin
if (curr_pj_set == 2'b00)
data_written <= conv_result_reg;
else
data_written <= conv_acc_result;
end
reg [4:0] op_count=15;
reg busy_out_sync;
wire busy_out_low_edge;
// eos and eoc
always @( posedge eoc_out_tmp or posedge eoc_out or posedge rst_in)
if (rst_in ==1)
eoc_out_tmp1 <= 0;
else if ( eoc_out ==1)
eoc_out_tmp1 <= 0;
else if ( eoc_out_tmp == 1) begin
if (curr_chan != 5'b01000 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0)))
eoc_out_tmp1 <= 1;
else
eoc_out_tmp1 <= 0;
end
always @( posedge eos_out_tmp or posedge eos_out or posedge rst_in)
if (rst_in ==1)
eos_out_tmp1 <= 0;
else if ( eos_out ==1)
eos_out_tmp1 <= 0;
else if ( eos_out_tmp == 1 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0)))
eos_out_tmp1 <= 1;
assign busy_out_low_edge = (busy_out==0 && busy_out_sync==1) ? 1 : 0;
always @( posedge dclk_in or posedge rst_in)
begin
if (rst_in) begin
op_count <= 15;
busy_out_sync <= 0;
end
drp_update <= 0;
alarm_update <= 0;
eoc_out <= 0;
eos_out <= 0;
if(rst_in==0)
begin
busy_out_sync <= busy_out;
if(op_count==3)
drp_update <= 1;
if(op_count==5 && eoc_out_tmp1==1)
alarm_update <=1;
if(op_count== 16)
eoc_out <= eoc_out_tmp1;
if(op_count==16)
eos_out <= eos_out_tmp1;
if (busy_out_low_edge==1 )
op_count <= 0;
else if(op_count < 22)
op_count <= op_count +1;
end
end
// end eos and eoc
// alarm
always @( posedge alarm_update or posedge rst_in_not_seq )
if (rst_in_not_seq == 1) begin
ot_out_reg <= 0;
alarm_out_reg <= 8'b0;
end
else
if (rst_lock == 0) begin
if (curr_chan_lat == 0) begin
if (data_written >= ot_limit_reg)
ot_out_reg <= 1;
else if (data_written < dr_sram[8'h57])
ot_out_reg <= 0;
if (data_written > dr_sram[8'h50])
alarm_out_reg[0] <= 1;
else if (data_written < dr_sram[8'h54])
alarm_out_reg[0] <= 0;
end
if (curr_chan_lat == 1) begin
if (data_written > dr_sram[8'h51] || data_written < dr_sram[8'h55])
alarm_out_reg[1] <= 1;
else
alarm_out_reg[1] <= 0;
end
if (curr_chan_lat == 2) begin
if (data_written > dr_sram[8'h52] || data_written < dr_sram[8'h56])
alarm_out_reg[2] <= 1;
else
alarm_out_reg[2] <= 0;
end
if (curr_chan_lat == 6) begin
if (data_written > dr_sram[8'h58] || data_written < dr_sram[8'h5C])
alarm_out_reg[3] <= 1;
else
alarm_out_reg[3] <= 0;
end
if (curr_chan_lat == 5'b01101) begin
if (data_written > dr_sram[8'h59] || data_written < dr_sram[8'h5D])
alarm_out_reg[4] <= 1;
else
alarm_out_reg[4] <= 0;
end
if (curr_chan_lat == 5'b01110) begin
if (data_written > dr_sram[8'h5A] || data_written < dr_sram[8'h5E])
alarm_out_reg[5] <= 1;
else
alarm_out_reg[5] <= 0;
end
if (curr_chan_lat == 5'b01111) begin
if (data_written > dr_sram[8'h5B] || data_written < dr_sram[8'h5F])
alarm_out_reg[6] <= 1;
else
alarm_out_reg[6] <= 0;
end
if (curr_chan_lat == 32) begin
if (data_written > dr_sram[8'h60] || data_written < dr_sram[8'h68])
alarm_out_reg[8] <= 1;
else
alarm_out_reg[8] <= 0;
end
if (curr_chan_lat == 33) begin
if (data_written > dr_sram[8'h61] || data_written < dr_sram[8'h69])
alarm_out_reg[9] <= 1;
else
alarm_out_reg[9] <= 0;
end
if (curr_chan_lat == 34) begin
if (data_written > dr_sram[8'h62] || data_written < dr_sram[8'h6A])
alarm_out_reg[10] <= 1;
else
alarm_out_reg[10] <= 0;
end
if (curr_chan_lat == 35) begin
if (data_written > dr_sram[8'h63] || data_written < dr_sram[8'h6B])
alarm_out_reg[11] <= 1;
else
alarm_out_reg[11] <= 0;
end
end // always
always @(ot_out_reg or ot_en or alarm_out_reg or alarm_en)
begin
ot_out = ot_out_reg & ot_en;
alarm_out[6:0] = alarm_out_reg[6:0] & alarm_en[6:0];
alarm_out[11:8] = alarm_out_reg[11:8] & alarm_en[11:8];
alarm_out[7] = |alarm_out[6:0];
alarm_out[15] = |alarm_out[14:8];
end
// end alarm
//*** Timing_Checks_Start_here
always @(notifier) begin
alarm_out_reg = 16'bx;
ot_out = 1'bx;
busy_out = 1'bx;
eoc_out = 1'bx;
eos_out = 1'bx;
curr_chan = 5'bx;
drdy_out = 1'bx;
do_out = 16'bx;
end
always @(notifier_do) begin
drdy_out = 1'bx;
do_out = 16'bx;
end
specify
(DCLK => ALM) = (100:100:100, 100:100:100);
(DCLK => BUSY) = (100:100:100, 100:100:100);
(DCLK => CHANNEL) = (100:100:100, 100:100:100);
(DCLK => DO) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => EOC) = (100:100:100, 100:100:100);
(DCLK => EOS) = (100:100:100, 100:100:100);
(DCLK => JTAGBUSY) = (100:100:100, 100:100:100);
(DCLK => JTAGLOCKED) = (100:100:100, 100:100:100);
(DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100);
(DCLK => MUXADDR) = (100:100:100, 100:100:100);
(DCLK => OT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CONVST, 0:0:0, notifier);
$period (posedge CONVSTCLK, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (posedge DCLK, negedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (posedge DCLK, negedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (posedge DCLK, negedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (posedge DCLK, posedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (posedge DCLK, posedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (posedge DCLK, posedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (posedge DCLK, posedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (negedge DCLK, negedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (negedge DCLK, negedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (negedge DCLK, negedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (negedge DCLK, negedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (negedge DCLK, posedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (negedge DCLK, posedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (negedge DCLK, posedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (negedge DCLK, posedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/TX_BITSLICE.v 0000664 0000000 0000000 00000041063 12327044266 0023237 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : TX_BITSLICE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module TX_BITSLICE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter OUTPUT_PHASE_90 = "FALSE",
parameter PRE_EMPHASIS = "OFF",
parameter real REFCLK_FREQUENCY = 300.0,
parameter TBYTE_CTL = "TBYTE_IN",
parameter UPDATE_MODE = "ASYNC"
)(
output [29:0] BIT_CTRL_OUT,
output [8:0] CNTVALUEOUT,
output O,
output T_OUT,
input [26:0] BIT_CTRL_IN,
input CE,
input CLK,
input [8:0] CNTVALUEIN,
input [7:0] D,
input EN_VTC,
input INC,
input LOAD,
input RST,
input RST_DLY,
input T,
input TBYTE_IN
);
// define constants
localparam MODULE_NAME = "TX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT;
localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE;
localparam [10:0] DELAY_VALUE_REG = DELAY_VALUE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [40:1] OUTPUT_PHASE_90_REG = OUTPUT_PHASE_90;
localparam [24:1] PRE_EMPHASIS_REG = PRE_EMPHASIS;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL;
localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE;
`endif
localparam [0:0] DC_ADJ_EN_REG = 1'b0;
localparam [2:0] FDLY_REG = 3'b000;
localparam [2:0] FDLY_RES_REG = 3'b000;
reg [63:0] REFCLK_FREQUENCY_INT = REFCLK_FREQUENCY * 1000;
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_CLK_INVERTED_BIN;
wire IS_RST_DLY_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "TX_BITSLICE_dr.v"
`endif
wire O_out;
wire T_OUT_out;
wire [29:0] BIT_CTRL_OUT_out;
wire [8:0] CNTVALUEOUT_out;
wire O_delay;
wire T_OUT_delay;
wire [29:0] BIT_CTRL_OUT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CE_in;
wire CLK_in;
wire EN_VTC_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire INC_in;
wire LOAD_in;
wire OFD_CE_in;
wire RST_DLY_in;
wire RST_in;
wire RX_CE_in;
wire RX_CLK_in;
wire RX_DATAIN1_in;
wire RX_EN_VTC_in;
wire RX_INC_in;
wire RX_LOAD_in;
wire RX_RESET_in;
wire RX_RST_in;
wire TBYTE_IN_in;
wire T_in;
wire [26:0] BIT_CTRL_IN_in;
wire [7:0] D_in;
wire [8:0] CNTVALUEIN_in;
wire [8:0] RX_CNTVALUEIN_in;
wire CE_delay;
wire CLK_delay;
wire EN_VTC_delay;
wire INC_delay;
wire LOAD_delay;
wire RST_DLY_delay;
wire RST_delay;
wire TBYTE_IN_delay;
wire T_delay;
wire [26:0] BIT_CTRL_IN_delay;
wire [7:0] D_delay;
wire [8:0] CNTVALUEIN_delay;
wire OSERDES_Q_out;
wire BITSLICE_WRITE_Q_out;
wire ODELAY_DATAIN0_out;
wire ODELAY_DATAOUT_out;
assign #(out_delay) BIT_CTRL_OUT = BIT_CTRL_OUT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) T_OUT = T_OUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) BIT_CTRL_IN_delay = BIT_CTRL_IN;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) D_delay = D;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_delay = LOAD;
assign #(in_delay) RST_DLY_delay = RST_DLY;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) TBYTE_IN_delay = TBYTE_IN;
assign #(in_delay) T_delay = T;
assign BIT_CTRL_OUT_delay = BIT_CTRL_OUT_out;
assign CNTVALUEOUT_delay = CNTVALUEOUT_out;
assign O_delay = O_out;
assign T_OUT_delay = T_OUT_out;
assign BIT_CTRL_IN_in = BIT_CTRL_IN_delay;
assign CE_in = CE_delay;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign D_in = D_delay;
assign EN_VTC_in = EN_VTC_delay;
assign INC_in = INC_delay;
assign LOAD_in = LOAD_delay;
assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign TBYTE_IN_in = TBYTE_IN_delay;
assign T_in = T_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 2) &&
(DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((DELAY_FORMAT_REG != "TIME") &&
(DELAY_FORMAT_REG != "COUNT")) begin
$display("Attribute Syntax Error : The attribute DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((DELAY_TYPE_REG != "FIXED") &&
(DELAY_TYPE_REG != "VARIABLE") &&
(DELAY_TYPE_REG != "VAR_LOAD")) begin
$display("Attribute Syntax Error : The attribute DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((INIT_REG < 1'b0) || (INIT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG < 1'b0) || (IS_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_DLY_INVERTED_REG < 1'b0) || (IS_RST_DLY_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_DLY_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((OUTPUT_PHASE_90_REG != "FALSE") &&
(OUTPUT_PHASE_90_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute OUTPUT_PHASE_90 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((PRE_EMPHASIS_REG != "OFF") &&
(PRE_EMPHASIS_REG != "ON")) begin
$display("Attribute Syntax Error : The attribute PRE_EMPHASIS on %s instance %m is set to %s. Legal values for this attribute are OFF or ON.", MODULE_NAME, PRE_EMPHASIS_REG);
attr_err = 1'b1;
end
if ((TBYTE_CTL_REG != "TBYTE_IN") &&
(TBYTE_CTL_REG != "T")) begin
$display("Attribute Syntax Error : The attribute TBYTE_CTL on %s instance %m is set to %s. Legal values for this attribute are TBYTE_IN or T.", MODULE_NAME, TBYTE_CTL_REG);
attr_err = 1'b1;
end
if ((UPDATE_MODE_REG != "ASYNC") &&
(UPDATE_MODE_REG != "MANUAL") &&
(UPDATE_MODE_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
if (REFCLK_FREQUENCY_REG >= 300.0 && REFCLK_FREQUENCY_REG <= 1333.0) begin // float
REFCLK_FREQUENCY_INT <= REFCLK_FREQUENCY_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign RX_CLK_in = 1'b1; // tie off
assign FIFO_RD_CLK_in = 1'b0; // tie off
assign FIFO_RD_EN_in = 1'b0; // tie off
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX_CE_in = 1'b0; // tie off
assign RX_CNTVALUEIN_in = 9'b000000000; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign RX_EN_VTC_in = 1'b0; // tie off
assign RX_INC_in = 1'b0; // tie off
assign RX_LOAD_in = 1'b0; // tie off
assign RX_RESET_in = 1'b1; // tie off
assign RX_RST_in = 1'b1; // tie off
SIP_TX_BITSLICE SIP_TX_BITSLICE_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.FDLY (FDLY_REG),
.FDLY_RES (FDLY_RES_REG),
.INIT (INIT_REG),
.OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG),
.PRE_EMPHASIS (PRE_EMPHASIS_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_INT),
.TBYTE_CTL (TBYTE_CTL_REG),
.UPDATE_MODE (UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.BIT_CTRL_OUT (BIT_CTRL_OUT_out),
.CNTVALUEOUT (CNTVALUEOUT_out),
.O (O_out),
.T_OUT (T_OUT_out),
.BIT_CTRL_IN (BIT_CTRL_IN_in),
.CE (CE_in),
.CLK (CLK_in),
.CNTVALUEIN (CNTVALUEIN_in),
.D (D_in),
.EN_VTC (EN_VTC_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.INC (INC_in),
.LOAD (LOAD_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RESET (RX_RESET_in),
.RX_RST (RX_RST_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.SIM_OSERDES_Q(OSERDES_Q_out),
.SIM_BITSLICE_WRITE_Q(BITSLICE_WRITE_Q_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
specify
(BIT_CTRL_IN *> O) = (0:0:0, 0:0:0);
(BIT_CTRL_IN *> T_OUT) = (0:0:0, 0:0:0);
(D *> O) = (0:0:0, 0:0:0);
(D *> T_OUT) = (0:0:0, 0:0:0);
(TBYTE_IN => T_OUT) = (0:0:0, 0:0:0);
(negedge RST => (O +: 0)) = (0:0:0, 0:0:0);
(posedge RST => (O +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge BIT_CTRL_IN[0], 0:0:0, notifier);
$period (negedge BIT_CTRL_IN[25], 0:0:0, notifier);
$period (negedge BIT_CTRL_IN[26], 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$period (posedge BIT_CTRL_IN[0], 0:0:0, notifier);
$period (posedge BIT_CTRL_IN[25], 0:0:0, notifier);
$period (posedge BIT_CTRL_IN[26], 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem ( negedge RST, negedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( negedge RST, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( negedge RST_DLY, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( negedge RST_DLY, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, BIT_CTRL_IN_delay);
$recrem ( negedge RST_DLY, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( posedge RST, negedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( posedge RST, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_delay, BIT_CTRL_IN_delay);
$recrem ( posedge RST_DLY, negedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$recrem ( posedge RST_DLY, posedge BIT_CTRL_IN, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, BIT_CTRL_IN_delay);
$recrem ( posedge RST_DLY, posedge CLK, 0:0:0, 0:0:0, notifier,,, RST_DLY_delay, CLK_delay);
$setuphold (negedge BIT_CTRL_IN, negedge D, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, D_delay);
$setuphold (negedge BIT_CTRL_IN, posedge D, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, D_delay);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, negedge D, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, D_delay);
$setuphold (posedge BIT_CTRL_IN, negedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, negedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, posedge D, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, D_delay);
$setuphold (posedge BIT_CTRL_IN, posedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, posedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$width (negedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/TX_BITSLICE_TRI.v 0000664 0000000 0000000 00000030617 12327044266 0023760 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : TX_BITSLICE_TRI.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module TX_BITSLICE_TRI #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter OUTPUT_PHASE_90 = "FALSE",
parameter real REFCLK_FREQUENCY = 300.0,
parameter UPDATE_MODE = "ASYNC"
)(
output [10:0] BIT_CTRL_OUT,
output [8:0] CNTVALUEOUT,
output TRI_OUT,
input [34:0] BIT_CTRL_IN,
input CE,
input CLK,
input [8:0] CNTVALUEIN,
input EN_VTC,
input INC,
input LOAD,
input RST,
input RST_DLY
);
// define constants
localparam MODULE_NAME = "TX_BITSLICE_TRI";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT;
localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE;
localparam [10:0] DELAY_VALUE_REG = DELAY_VALUE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [40:1] OUTPUT_PHASE_90_REG = OUTPUT_PHASE_90;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE;
`endif
localparam [0:0] DC_ADJ_EN_REG = 1'b0;
localparam [2:0] FDLY_REG = 3'b000;
localparam [2:0] FDLY_RES_REG = 3'b000;
reg [63:0] REFCLK_FREQUENCY_INT = REFCLK_FREQUENCY * 1000;
localparam [64:1] TBYTE_CTL_REG = "TBYTE_IN";
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_CLK_INVERTED_BIN;
wire IS_RST_DLY_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "TX_BITSLICE_TRI_dr.v"
`endif
wire CDATAOUT_out;
wire TRI_OUT_out;
wire T_OUT_out;
wire [10:0] BIT_CTRL_OUT_out;
wire [8:0] CNTVALUEOUT_out;
wire TRI_OUT_delay;
wire [10:0] BIT_CTRL_OUT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CDATAIN0_in;
wire CDATAIN1_in;
wire CE_in;
wire CLK_in;
wire EN_VTC_in;
wire INC_in;
wire LOAD_in;
wire OFD_CE_in;
wire RST_DLY_in;
wire RST_in;
wire [34:0] BIT_CTRL_IN_in;
wire [8:0] CNTVALUEIN_in;
wire CE_delay;
wire CLK_delay;
wire EN_VTC_delay;
wire INC_delay;
wire LOAD_delay;
wire RST_DLY_delay;
wire RST_delay;
wire [34:0] BIT_CTRL_IN_delay;
wire [8:0] CNTVALUEIN_delay;
assign #(out_delay) BIT_CTRL_OUT = BIT_CTRL_OUT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) TRI_OUT = TRI_OUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) BIT_CTRL_IN_delay = BIT_CTRL_IN;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_delay = LOAD;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) RST_DLY_delay = RST_DLY;
assign #(in_delay) RST_delay = RST;
assign BIT_CTRL_OUT_delay = BIT_CTRL_OUT_out;
assign CNTVALUEOUT_delay = CNTVALUEOUT_out;
assign TRI_OUT_delay = TRI_OUT_out;
assign BIT_CTRL_IN_in = BIT_CTRL_IN_delay;
assign CE_in = CE_delay;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign EN_VTC_in = EN_VTC_delay;
assign INC_in = INC_delay;
assign LOAD_in = LOAD_delay;
assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 2) &&
(DATA_WIDTH_REG != 4)) begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 2 to 8.", MODULE_NAME, DATA_WIDTH_REG, 8);
attr_err = 1'b1;
end
if ((DELAY_FORMAT_REG != "TIME") &&
(DELAY_FORMAT_REG != "COUNT")) begin
$display("Attribute Syntax Error : The attribute DELAY_FORMAT on %s instance %m is set to %s. Legal values for this attribute are TIME or COUNT.", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((DELAY_TYPE_REG != "FIXED") &&
(DELAY_TYPE_REG != "VARIABLE") &&
(DELAY_TYPE_REG != "VAR_LOAD")) begin
$display("Attribute Syntax Error : The attribute DELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD.", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)) begin
$display("Attribute Syntax Error : The attribute DELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0 to 1250.", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((INIT_REG < 1'b0) || (INIT_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((IS_CLK_INVERTED_REG < 1'b0) || (IS_CLK_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLK_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_DLY_INVERTED_REG < 1'b0) || (IS_RST_DLY_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_DLY_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_RST_INVERTED_REG < 1'b0) || (IS_RST_INVERTED_REG > 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((OUTPUT_PHASE_90_REG != "FALSE") &&
(OUTPUT_PHASE_90_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute OUTPUT_PHASE_90 on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((UPDATE_MODE_REG != "ASYNC") &&
(UPDATE_MODE_REG != "MANUAL") &&
(UPDATE_MODE_REG != "SYNC")) begin
$display("Attribute Syntax Error : The attribute UPDATE_MODE on %s instance %m is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC.", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
if (REFCLK_FREQUENCY_REG >= 300.0 && REFCLK_FREQUENCY_REG <= 1333.0) begin // float
REFCLK_FREQUENCY_INT <= REFCLK_FREQUENCY_REG * 1000;
end
else begin
$display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on %s instance %m is set to %f. Legal values for this attribute are 300.0 to 1333.0.", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CDATAIN0_in = 1'b1; // tie off
assign CDATAIN1_in = 1'b1; // tie off
assign OFD_CE_in = 1'b0; // tie off
SIP_TX_BITSLICE_TRI SIP_TX_BITSLICE_TRI_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.FDLY (FDLY_REG),
.FDLY_RES (FDLY_RES_REG),
.INIT (INIT_REG),
.OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_INT),
.TBYTE_CTL (TBYTE_CTL_REG),
.UPDATE_MODE (UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.BIT_CTRL_OUT (BIT_CTRL_OUT_out),
.CDATAOUT (CDATAOUT_out),
.CNTVALUEOUT (CNTVALUEOUT_out),
.TRI_OUT (TRI_OUT_out),
.T_OUT (T_OUT_out),
.BIT_CTRL_IN (BIT_CTRL_IN_in),
.CDATAIN0 (CDATAIN0_in),
.CDATAIN1 (CDATAIN1_in),
.CE (CE_in),
.CLK (CLK_in),
.CNTVALUEIN (CNTVALUEIN_in),
.EN_VTC (EN_VTC_in),
.INC (INC_in),
.LOAD (LOAD_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.GSR (glblGSR)
);
specify
(BIT_CTRL_IN *> TRI_OUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge BIT_CTRL_IN, 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$period (posedge BIT_CTRL_IN, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, negedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, negedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CE, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CE_delay);
$setuphold (posedge BIT_CTRL_IN, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, CNTVALUEIN_delay);
$setuphold (posedge BIT_CTRL_IN, posedge INC, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, INC_delay);
$setuphold (posedge BIT_CTRL_IN, posedge LOAD, 0:0:0, 0:0:0, notifier,,, BIT_CTRL_IN_delay, LOAD_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN, 0:0:0, 0:0:0, notifier,,, CLK_delay, CNTVALUEIN_delay);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier,,, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier,,, CLK_delay, LOAD_delay);
$width (negedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge BIT_CTRL_IN, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/USR_ACCESSE2.v 0000664 0000000 0000000 00000001736 12327044266 0023312 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/USR_ACCESSE2.v,v 1.1 2010/05/27 18:53:42 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : USR_ACCESSE2.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module USR_ACCESSE2 (
CFGCLK,
DATA,
DATAVALID
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CFGCLK;
output DATAVALID;
output [31:0] DATA;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/VCC.v 0000664 0000000 0000000 00000002025 12327044266 0022034 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/VCC.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / VCC Connection
// /___/ /\ Filename : VCC.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module VCC(P);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output P;
assign P = 1'b1;
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/XADC.v 0000664 0000000 0000000 00000312575 12327044266 0022156 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.77)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / System Monitor
// /___/ /\ Filename : XADC.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 12/09/09 - Initial version.
// 05/24/10 - Correctly write result to data_reg for ADC2 (CR561364)
// 08/02/10 - Not generate eoc_out2 when ADC2 not used (CR568374)
// 09/09/10 - Change to bus timing
// 10/15/10 - use 273.15 for temperature calculation (CR579001)
// 10/22/10 - Add BUSY to EOS to 18 DCLK instead of 11 (CR579591)
// Extend calibration cycle to 4 conversions (CR580176)
// 11/11/10 - Match hardware (CR580660 580663 580598)
// 11/16/10 - Set seq_num=5 for sequence mode 0000 (CR579051)
// 11/29/10 - Using curr_chan_lat for data_reg update due to extend of
// eoc (CR581758)
// 12/01/10 - Set analog data to fixed channel for external mux and
// simultaneous sampling mode. (CR580598)
// 12/09/10 - Remove check for clock divider (CR586253)
// 03/03/11 - Add VCCPINT VCCPAUX VCCDDRO channel and SIM_DEVICE attibute
// (CR593005)
// 03/03/11 - disable timing check when RESET=1 (CR594618)
// 03/22/11 - use INIT_53 for ot upper limit (CR602195)
// 03/28/11 - Set data_reg range to 47:0 (CR603247)
// 03/29/11 - Set column_real range to 42:0 (CR602520)
// 08/26/11 - Change ot_limit_reg to CA3h(125 C) (CR623029)
// Allow tmp_dr_sram_out out when address 58h (CR623028)
// 09/13/11 - Add ZYNQ to SIM_DEVICE (CR624910)
// Add curr_seq2_tmps for simultaneous mode (CR621932)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/05/12 - Fixed specify block to handle X's (CR 654692).
// 09/26/12 - Removed DRC for event-driven/continuous sampling mode (CR 680075).
// 10/08/12 - Fixed single pass sequence mode (CR 675227).
// 01/18/13 - Added DRP monitor (CR 695630).
// 07/26/13 - Added invertible pins support (CR 715417).
// 08/29/13 - Updated undefined address location (CR 719013).
// 10/28/13 - Removed DRC for event mode timing (CR 736315).
// End Revision
`timescale 1ps / 1ps
`celldefine
module XADC (
ALM,
BUSY,
CHANNEL,
DO,
DRDY,
EOC,
EOS,
JTAGBUSY,
JTAGLOCKED,
JTAGMODIFIED,
MUXADDR,
OT,
CONVST,
CONVSTCLK,
DADDR,
DCLK,
DEN,
DI,
DWE,
RESET,
VAUXN,
VAUXP,
VN,
VP
);
output BUSY;
output DRDY;
output EOC;
output EOS;
output JTAGBUSY;
output JTAGLOCKED;
output JTAGMODIFIED;
output OT;
output [15:0] DO;
output [7:0] ALM;
output [4:0] CHANNEL;
output [4:0] MUXADDR;
input CONVST;
input CONVSTCLK;
input DCLK;
input DEN;
input DWE;
input RESET;
input VN;
input VP;
input [15:0] DI;
input [15:0] VAUXN;
input [15:0] VAUXP;
input [6:0] DADDR;
parameter [15:0] INIT_40 = 16'h0;
parameter [15:0] INIT_41 = 16'h0;
parameter [15:0] INIT_42 = 16'h0800;
parameter [15:0] INIT_43 = 16'h0;
parameter [15:0] INIT_44 = 16'h0;
parameter [15:0] INIT_45 = 16'h0;
parameter [15:0] INIT_46 = 16'h0;
parameter [15:0] INIT_47 = 16'h0;
parameter [15:0] INIT_48 = 16'h0;
parameter [15:0] INIT_49 = 16'h0;
parameter [15:0] INIT_4A = 16'h0;
parameter [15:0] INIT_4B = 16'h0;
parameter [15:0] INIT_4C = 16'h0;
parameter [15:0] INIT_4D = 16'h0;
parameter [15:0] INIT_4E = 16'h0;
parameter [15:0] INIT_4F = 16'h0;
parameter [15:0] INIT_50 = 16'h0;
parameter [15:0] INIT_51 = 16'h0;
parameter [15:0] INIT_52 = 16'h0;
parameter [15:0] INIT_53 = 16'h0;
parameter [15:0] INIT_54 = 16'h0;
parameter [15:0] INIT_55 = 16'h0;
parameter [15:0] INIT_56 = 16'h0;
parameter [15:0] INIT_57 = 16'h0;
parameter [15:0] INIT_58 = 16'h0;
parameter [15:0] INIT_59 = 16'h0;
parameter [15:0] INIT_5A = 16'h0;
parameter [15:0] INIT_5B = 16'h0;
parameter [15:0] INIT_5C = 16'h0;
parameter [15:0] INIT_5D = 16'h0;
parameter [15:0] INIT_5E = 16'h0;
parameter [15:0] INIT_5F = 16'h0;
parameter IS_CONVSTCLK_INVERTED = 1'b0;
parameter IS_DCLK_INVERTED = 1'b0;
parameter SIM_DEVICE = "7SERIES";
parameter SIM_MONITOR_FILE = "design.txt";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
localparam S1_ST = 0,
S6_ST = 1,
S2_ST = 2,
S3_ST = 3,
S5_ST = 5,
S4_ST = 6;
time time_out, prev_time_out;
integer temperature_index = -1, time_index = -1, vccaux_index = -1;
integer vbram_index = -1;
integer vccint_index = -1, vn_index = -1, vp_index = -1;
integer vccpint_index = -1;
integer vccpaux_index = -1;
integer vccpdro_index = -1;
integer vauxp_idx0 = -1, vauxn_idx0 = -1;
integer vauxp_idx1 = -1, vauxn_idx1 = -1;
integer vauxp_idx2 = -1, vauxn_idx2 = -1;
integer vauxp_idx3 = -1, vauxn_idx3 = -1;
integer vauxp_idx4 = -1, vauxn_idx4 = -1;
integer vauxp_idx5 = -1, vauxn_idx5 = -1;
integer vauxp_idx6 = -1, vauxn_idx6 = -1;
integer vauxp_idx7 = -1, vauxn_idx7 = -1;
integer vauxp_idx8 = -1, vauxn_idx8 = -1;
integer vauxp_idx9 = -1, vauxn_idx9 = -1;
integer vauxp_idx10 = -1, vauxn_idx10 = -1;
integer vauxp_idx11 = -1, vauxn_idx11 = -1;
integer vauxp_idx12 = -1, vauxn_idx12 = -1;
integer vauxp_idx13 = -1, vauxn_idx13 = -1;
integer vauxp_idx14 = -1, vauxn_idx14 = -1;
integer vauxp_idx15 = -1, vauxn_idx15 = -1;
integer char_1, char_2, fs, fd;
integer num_arg, num_val;
integer clk_count, seq_count, seq_count2, seq_count_a;
integer seq_status_avg, acq_count;
integer seq_status_avg2;
integer conv_pj_count [31:0];
integer conv_pj_count2 [31:0];
integer conv_acc [31:0];
integer conv_acc2 [31:0];
integer conv_result_int;
integer conv_result_int2;
integer conv_time, conv_count, conv_time_cal, conv_time_cal_1;
integer h, i, j, k, l, m, n, p;
integer file_line;
// string
reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42;
reg [8*600:1] one_line;
reg [8*12:1] label [43:0];
reg [8*12:1] tmp_label;
reg end_of_file;
real tmp_va0, tmp_va1, column_real00, column_real100, column_real101;
real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42;
// array of real numbers
// real column_real [39:0];
// reg [63:0] column_real [39:0];
reg [63:0] column_real [42:0];
reg [63:0] chan_val [31:0];
reg [63:0] chan_val_tmp [31:0];
reg [63:0] chan_valn [31:0];
reg [63:0] chan_valn_tmp [31:0];
reg [63:0] mn_in_diff [31:0];
reg [63:0] mn_in2_diff [31:0];
reg [63:0] mn_in_uni [31:0];
reg [63:0] mn_in2_uni [31:0];
reg [63:0] mn_comm_in [31:0];
reg [63:0] mn_comm2_in [31:0];
real chan_val_p_tmp, chan_val_n_tmp;
real mn_mux_in, mn_in_tmp, mn_comm_in_tmp, mn_in_comm;
real mn_mux_in2;
real tmp_v, tmp_v1;
real adc_temp_result, adc_intpwr_result;
real adc_temp_result2, adc_intpwr_result2;
real adc_ext_result;
real adc_ext_result2;
reg simd_f;
reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly;
reg soft_reset = 0;
reg en_data_flag;
reg first_cal_chan;
reg seq_en;
reg seq_en_dly;
wire [15:0] status_reg;
reg [15:0] ot_limit_reg = 16'hCA30;
reg [15:0] tmp_otv;
// reg [15:0] ot_sf_limit_low_reg = 16'hAE40;
reg [23:0] conv_acc_vec;
reg [23:0] conv_acc_vec2;
reg [15:0] conv_result2;
reg [15:0] conv_result;
reg [15:0] conv_result_reg, conv_acc_result;
reg [15:0] conv_result_reg2, conv_acc_result2;
wire [7:0] curr_clkdiv_sel;
reg [7:0] alarm_out_reg;
reg [4:0] curr_chan, curr_chan_lat;
reg [4:0] curr_chan2, curr_chan_lat2;
reg [2:0] adc_state, next_state;
reg conv_start, conv_end;
reg eos_en, eos_tmp_en;
reg drdy_out, drdy_out_tmp1, drdy_out_tmp2, drdy_out_tmp3, drdy_out_tmp4;
reg ot_out_reg;
reg [15:0] do_out;
reg [15:0] do_out_rdtmp;
reg [15:0] data_reg [47:0];
reg [15:0] dr_sram [127:64];
reg sysclk, adcclk_tmp;
wire adcclk;
wire xadc_en, xadc2_en;
reg [3:0] curr_seq1_0, curr_seq1_0_lat;
reg [1:0] tmp_seq1_0 = 2'b00;
reg curr_e_c, curr_b_u, curr_acq;
reg ext_mux;
reg curr_e_c2, curr_b_u2, curr_acq2;
reg seq_count_en;
reg [4:0] acq_chan, acq_chan2, acq_chan_m;
reg [4:0] ext_mux_chan, ext_mux_chan2;
reg acq_b_u, acq_b_u2;
reg adc_s1_flag, acq_acqsel;
wire acq_e_c;
reg acq_e_c_tmp5, acq_e_c_tmp6;
reg [1:0] curr_pj_set;
reg [1:0] curr_pj_set2;
reg eoc_en, eoc_en_delay;
reg eoc_en2, eoc_en_delay2;
reg eoc_out_tmp, eos_out_tmp;
reg eoc_out_tmp2;
reg eoc_out_tmp1, eos_out_tmp1;
reg eoc_out_tmp21;
reg eoc_out, eos_out;
reg eoc_out2, eoc_out_t;
reg busy_r, busy_r_rst;
reg busy_sync1, busy_sync2;
wire busy_sync_fall, busy_sync_rise;
reg notifier, notifier_do;
reg [4:0] channel_out;
wire [4:0] muxaddr_o;
reg [4:0] muxaddr_out;
reg rst_lock, rst_lock_early, rst_lock_late;
reg sim_file_flag;
reg [6:0] daddr_in_lat;
reg [15:0] init40h_tmp, init41h_tmp, init42h_tmp, init4eh_tmp;
reg [7:0] alarm_out;
reg ot_out;
reg [15:0] curr_seq, curr_seq_m;
reg [15:0] curr_seq2_tmp, curr_seq2_tmps;
wire [15:0] curr_seq2;
reg busy_out, busy_rst, busy_conv, busy_out_tmp, busy_seq_rst;
reg [3:0] seq1_0, seq_bits;
reg ot_en, alarm_update, drp_update, cal_chan_update;
reg [6:0] alarm_en;
reg [4:0] scon_tmp;
wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_acq_reg1, seq_acq_reg2;
wire [15:0] seq_pj_reg1, seq_pj_reg2, seq_du_reg1, seq_du_reg2;
reg [15:0] cfg_reg1_init;
reg [4:0] seq_curr_i, seq_curr_i2, seq_curr_ia;
integer busy_rst_cnt;
integer si, seq_num, seq_num2;
integer seq_mem [32:0];
integer seq_mem2 [32:0];
wire rst_in, adc_convst;
wire [15:0] cfg_reg0;
wire [15:0] cfg_reg1;
wire [15:0] cfg_reg2;
wire [15:0] di_in;
wire [6:0] daddr_in;
wire [15:0] tmp_data_reg_out, tmp_dr_sram_out;
wire convst_in_tmp;
reg convst_in;
wire rst_in_not_seq;
wire adcclk_div1;
wire gsr_in;
wire convst_raw_in, convstclk_in, dclk_in, den_in, rst_input, dwe_in;
wire DCLK_dly, DEN_dly, DWE_dly;
wire [6:0] DADDR_dly;
wire [15:0] DI_dly;
wire dclk_inv, convstclk_inv;
reg attr_err = 1'b0;
//drp monitor
reg den_r1 = 1'b0;
reg den_r2 = 1'b0;
reg dwe_r1 = 1'b0;
reg dwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge dclk_in)
begin
// pipeline the DEN and DWE
den_r1 <= den_in;
dwe_r1 <= dwe_in;
den_r2 <= den_r1;
dwe_r2 <= dwe_r1;
// Check - if DEN or DWE is more than 1 DCLK
if ((den_r1 == 1'b1) && (den_r2 == 1'b1))
begin
$display("DRC Error : DEN is high for more than 1 DCLK on %m instance");
$finish;
end
if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1))
begin
$display("DRC Error : DWE is high for more than 1 DCLK on %m instance");
$finish;
end
//After the 1st DEN pulse, check the DEN and DRDY.
case (sfsm)
FSM_IDLE:
begin
if(den_in == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DEN, 4 cases can happen
// DEN DRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(den_in === 1'b1 && drdy_out === 1'b0)
begin
$display("DRC Error : DEN is enabled before DRDY returns on %m instance");
$finish;
end
//Add the check for another DWE pulse
if ((dwe_in === 1'b1) && (den_in === 1'b0))
begin
$display("DRC Error : DWE is enabled before DRDY returns on %m instance");
$finish;
end
if ((drdy_out === 1'b1) && (den_in === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((drdy_out === 1'b1)&& (den_in === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge DCLK)
//end drp monitor
//CR 675227
integer halt_adc = 0;
reg int_rst;
always @(posedge rst_input)
halt_adc <= 0;
always @(seq1_0) begin
if (halt_adc == 2 && seq1_0 == 4'b0001) begin
halt_adc <= 0;
int_rst <= 1;
@(posedge dclk_in)
int_rst <= 0;
end
end
tri0 GSR = glbl.GSR;
`ifndef XIL_TIMING
assign BUSY = busy_out;
assign DRDY = drdy_out;
assign EOC = eoc_out;
assign EOS = eos_out;
assign OT = ot_out;
assign DO = do_out;
assign CHANNEL = channel_out;
assign MUXADDR = muxaddr_out;
assign ALM = alarm_out;
assign convst_raw_in = CONVST;
assign convstclk_inv = CONVSTCLK;
assign dclk_inv = DCLK;
assign den_in = DEN;
assign rst_input = RESET;
assign dwe_in = DWE;
assign di_in = DI;
assign daddr_in = DADDR;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
assign BUSY = busy_out;
assign DRDY = drdy_out;
assign EOC = eoc_out;
assign EOS = eos_out;
assign OT = ot_out;
assign DO = do_out;
assign CHANNEL = channel_out;
assign MUXADDR = muxaddr_out;
assign ALM = alarm_out;
assign convst_raw_in = CONVST;
assign convstclk_inv = CONVSTCLK;
assign dclk_inv = DCLK_dly;
assign den_in = DEN_dly;
assign rst_input = RESET;
assign dwe_in = DWE_dly;
assign di_in = DI_dly;
assign daddr_in = DADDR_dly;
`endif // `ifdef XIL_TIMING
assign convstclk_in = convstclk_inv ^ IS_CONVSTCLK_INVERTED;
assign dclk_in = dclk_inv ^ IS_DCLK_INVERTED;
assign gsr_in = GSR;
assign convst_in_tmp = (convst_raw_in===1 || convstclk_in===1) ? 1: 0;
assign JTAGLOCKED = 0;
assign JTAGMODIFIED = 0;
assign JTAGBUSY = 0;
always @(posedge convst_in_tmp or negedge convst_in_tmp or posedge rst_in)
if (rst_in == 1 || rst_lock == 1)
convst_in <= 0;
else if (convst_in_tmp == 1)
convst_in <= 1;
else if (convst_in_tmp == 0)
convst_in <= 0;
initial begin
case (SIM_DEVICE)
"7SERIES" : simd_f = 0;
"ZYNQ" : simd_f = 1;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on XADC instance %m is set to %s. Legal values for this attribute are 7SERIES, or ZYNQ.", SIM_DEVICE);
$finish;
end
endcase
init40h_tmp = INIT_40;
init41h_tmp = INIT_41;
init42h_tmp = INIT_42;
init4eh_tmp = INIT_4E;
if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[8]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000))
$display(" Attribute Syntax warning : The attribute INIT_40 on XADC instance %m is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_40);
if ((init41h_tmp[15:12]!=4'b0011) && (init4eh_tmp[10:0]!=11'b0) && (init4eh_tmp[15:12]!=4'b0))
$display(" Attribute Syntax warning : The attribute INIT_4E on XADC instance %m is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_4E);
// if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[9]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000))
// $display(" Attribute Syntax warning : The attribute INIT_40 on XADC instance %m is set to %x. Bit[9] of this attribute must be set to 0. Event mode timing can only be used with external channels, and only in single channel mode.", INIT_40);
if ((init41h_tmp[15:12]==4'b0011) && (init40h_tmp[13:12]!=2'b00) && (INIT_48 != 16'h0000) && (INIT_49 != 16'h0000))
$display(" Attribute Syntax warning : INIT_48 and INIT_49 are %x and %x on XADC instance %m. Those attributes must be set to 0000h in single channel mode and averaging enabled.", INIT_48, INIT_49);
if (init42h_tmp[1:0] != 2'b00)
$display(" Attribute Syntax Error : The attribute INIT_42 on XADC instance %m is set to %x. Bit[1:0] of this attribute must be set to 0h.", INIT_42);
// if (init42h_tmp[15:8] < 8'b00000010) begin
// $display(" Attribute Syntax Error : The attribute INIT_42 on XADC instance %m is set to %x. Bit[15:8] of this attribute is the ADC Clock divider and must be equal or greater than 2. ", INIT_42);
// $finish;
// end
if (INIT_43 != 16'h0)
$display(" Warning : The attribute INIT_43 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_43);
if (INIT_44 != 16'h0)
$display(" Warning : The attribute INIT_44 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_44);
if (INIT_45 != 16'h0)
$display(" Warning : The attribute INIT_45 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_45);
if (INIT_46 != 16'h0)
$display(" Warning : The attribute INIT_46 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_46);
if (INIT_47 != 16'h0)
$display(" Warning : The attribute INIT_47 on XADC instance %m is set to %x. This must be set to 0000h.", INIT_47);
if (!((IS_CONVSTCLK_INVERTED >= 1'b0) && (IS_CONVSTCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_CONVSTCLK_INVERTED on XADC instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CONVSTCLK_INVERTED);
attr_err = 1'b1;
end
if (!((IS_DCLK_INVERTED >= 1'b0) && (IS_DCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_DCLK_INVERTED on XADC instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_DCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
initial begin
dr_sram[7'h40] = INIT_40;
dr_sram[7'h41] = INIT_41;
dr_sram[7'h42] = INIT_42;
dr_sram[7'h43] = INIT_43;
dr_sram[7'h44] = INIT_44;
dr_sram[7'h45] = INIT_45;
dr_sram[7'h46] = INIT_46;
dr_sram[7'h47] = INIT_47;
dr_sram[7'h48] = INIT_48;
dr_sram[7'h49] = INIT_49;
dr_sram[7'h4A] = INIT_4A;
dr_sram[7'h4B] = INIT_4B;
dr_sram[7'h4C] = INIT_4C;
dr_sram[7'h4D] = INIT_4D;
dr_sram[7'h4E] = INIT_4E;
dr_sram[7'h4F] = INIT_4F;
dr_sram[7'h50] = INIT_50;
dr_sram[7'h51] = INIT_51;
dr_sram[7'h52] = INIT_52;
tmp_otv = INIT_53;
if (tmp_otv [3:0] == 4'b0011) begin
dr_sram[7'h53] = INIT_53;
ot_limit_reg = INIT_53;
end
else begin
dr_sram[7'h53] = 16'hCA30;
ot_limit_reg = 16'hCA30;
end
dr_sram[7'h54] = INIT_54;
dr_sram[7'h55] = INIT_55;
dr_sram[7'h56] = INIT_56;
dr_sram[7'h57] = INIT_57;
dr_sram[7'h58] = INIT_58;
dr_sram[7'h59] = INIT_59;
dr_sram[7'h5A] = INIT_5A;
dr_sram[7'h5B] = INIT_5B;
dr_sram[7'h5C] = INIT_5C;
dr_sram[7'h5D] = INIT_5D;
dr_sram[7'h5E] = INIT_5E;
dr_sram[7'h5F] = INIT_5F;
end // initial begin
// read input file
initial begin
char_1 = 0;
char_2 = 0;
time_out = 0;
sim_file_flag = 0;
file_line = -1;
end_of_file = 0;
fd = $fopen(SIM_MONITOR_FILE, "r");
if (fd == 0)
begin
$display(" *** Warning: The analog data file %s for XADC instance %m was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.\n", SIM_MONITOR_FILE);
sim_file_flag = 1;
end
if (sim_file_flag == 0) begin
while (end_of_file==0) begin
file_line = file_line + 1;
char_1 = $fgetc (fd);
char_2 = $fgetc (fd);
// if(char_2==`EOFile)
if(char_2== -1)
end_of_file = 1;
else begin
// Ignore Comments
if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
// Getting labels
else if ((char_1 == "T" & char_2 == "I" ) ||
(char_1 == "T" & char_2 == "i" ) ||
(char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s", label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42);
label[0] = label0;
label[1] = label1;
label[2] = label2;
label[3] = label3;
label[4] = label4;
label[5] = label5;
label[6] = label6;
label[7] = label7;
label[8] = label8;
label[9] = label9;
label[10] = label10;
label[11] = label11;
label[12] = label12;
label[13] = label13;
label[14] = label14;
label[15] = label15;
label[16] = label16;
label[17] = label17;
label[18] = label18;
label[19] = label19;
label[20] = label20;
label[21] = label21;
label[22] = label22;
label[23] = label23;
label[24] = label24;
label[25] = label25;
label[26] = label26;
label[27] = label27;
label[28] = label28;
label[29] = label29;
label[30] = label30;
label[31] = label31;
label[32] = label32;
label[33] = label33;
label[34] = label34;
label[35] = label35;
label[36] = label36;
label[37] = label37;
label[38] = label38;
label[39] = label39;
label[40] = label40;
label[41] = label41;
label[42] = label42;
for (m = 0; m < num_arg; m = m +1) begin
tmp_label = 96'b0;
tmp_label = to_upcase_label(label[m]);
case (tmp_label)
"TEMP" : temperature_index = m;
"TIME" : time_index = m;
"VCCAUX" : vccaux_index = m;
"VCCINT" : vccint_index = m;
"VBRAM" : vbram_index = m;
"VCCPINT" : vccpint_index = m;
"VCCPAUX" : vccpaux_index = m;
"VCCDDRO" : vccpdro_index = m;
"VN" : vn_index = m;
"VAUXN[0]" : vauxn_idx0 = m;
"VAUXN[1]" : vauxn_idx1 = m;
"VAUXN[2]" : vauxn_idx2 = m;
"VAUXN[3]" : vauxn_idx3 = m;
"VAUXN[4]" : vauxn_idx4 = m;
"VAUXN[5]" : vauxn_idx5 = m;
"VAUXN[6]" : vauxn_idx6 = m;
"VAUXN[7]" : vauxn_idx7 = m;
"VAUXN[8]" : vauxn_idx8 = m;
"VAUXN[9]" : vauxn_idx9 = m;
"VAUXN[10]" : vauxn_idx10 = m;
"VAUXN[11]" : vauxn_idx11 = m;
"VAUXN[12]" : vauxn_idx12 = m;
"VAUXN[13]" : vauxn_idx13 = m;
"VAUXN[14]" : vauxn_idx14 = m;
"VAUXN[15]" : vauxn_idx15 = m;
"VP" : vp_index = m;
"VAUXP[0]" : vauxp_idx0 = m;
"VAUXP[1]" : vauxp_idx1 = m;
"VAUXP[2]" : vauxp_idx2 = m;
"VAUXP[3]" : vauxp_idx3 = m;
"VAUXP[4]" : vauxp_idx4 = m;
"VAUXP[5]" : vauxp_idx5 = m;
"VAUXP[6]" : vauxp_idx6 = m;
"VAUXP[7]" : vauxp_idx7 = m;
"VAUXP[8]" : vauxp_idx8 = m;
"VAUXP[9]" : vauxp_idx9 = m;
"VAUXP[10]" : vauxp_idx10 = m;
"VAUXP[11]" : vauxp_idx11 = m;
"VAUXP[12]" : vauxp_idx12 = m;
"VAUXP[13]" : vauxp_idx13 = m;
"VAUXP[14]" : vauxp_idx14 = m;
"VAUXP[15]" : vauxp_idx15 = m;
default : begin
$display("analog Data File Error : The channel name %s is invalid in the input file for XADC instance %m.", tmp_label);
infile_format;
end
endcase
end // for (m = 0; m < num_arg; m = m +1)
end
// Getting column values
else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
column_real0 = 0.0;
column_real1 = 0.0;
column_real2 = 0.0;
column_real3 = 0.0;
column_real4 = 0.0;
column_real5 = 0.0;
column_real6 = 0.0;
column_real7 = 0.0;
column_real8 = 0.0;
column_real9 = 0.0;
column_real10 = 0.0;
column_real11 = 0.0;
column_real12 = 0.0;
column_real13 = 0.0;
column_real14 = 0.0;
column_real15 = 0.0;
column_real16 = 0.0;
column_real17 = 0.0;
column_real18 = 0.0;
column_real19 = 0.0;
column_real20 = 0.0;
column_real21 = 0.0;
column_real22 = 0.0;
column_real23 = 0.0;
column_real24 = 0.0;
column_real25 = 0.0;
column_real26 = 0.0;
column_real27 = 0.0;
column_real28 = 0.0;
column_real29 = 0.0;
column_real30 = 0.0;
column_real31 = 0.0;
column_real32 = 0.0;
column_real33 = 0.0;
column_real34 = 0.0;
column_real35 = 0.0;
column_real36 = 0.0;
column_real37 = 0.0;
column_real38 = 0.0;
column_real39 = 0.0;
column_real40 = 0.0;
column_real41 = 0.0;
column_real42 = 0.0;
num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42);
column_real[0] = $realtobits(column_real0);
column_real[1] = $realtobits(column_real1);
column_real[2] = $realtobits(column_real2);
column_real[3] = $realtobits(column_real3);
column_real[4] = $realtobits(column_real4);
column_real[5] = $realtobits(column_real5);
column_real[6] = $realtobits(column_real6);
column_real[7] = $realtobits(column_real7);
column_real[8] = $realtobits(column_real8);
column_real[9] = $realtobits(column_real9);
column_real[10] = $realtobits(column_real10);
column_real[11] = $realtobits(column_real11);
column_real[12] = $realtobits(column_real12);
column_real[13] = $realtobits(column_real13);
column_real[14] = $realtobits(column_real14);
column_real[15] = $realtobits(column_real15);
column_real[16] = $realtobits(column_real16);
column_real[17] = $realtobits(column_real17);
column_real[18] = $realtobits(column_real18);
column_real[19] = $realtobits(column_real19);
column_real[20] = $realtobits(column_real20);
column_real[21] = $realtobits(column_real21);
column_real[22] = $realtobits(column_real22);
column_real[23] = $realtobits(column_real23);
column_real[24] = $realtobits(column_real24);
column_real[25] = $realtobits(column_real25);
column_real[26] = $realtobits(column_real26);
column_real[27] = $realtobits(column_real27);
column_real[28] = $realtobits(column_real28);
column_real[29] = $realtobits(column_real29);
column_real[30] = $realtobits(column_real30);
column_real[31] = $realtobits(column_real31);
column_real[32] = $realtobits(column_real32);
column_real[33] = $realtobits(column_real33);
column_real[34] = $realtobits(column_real34);
column_real[35] = $realtobits(column_real35);
column_real[36] = $realtobits(column_real36);
column_real[37] = $realtobits(column_real37);
column_real[38] = $realtobits(column_real38);
column_real[39] = $realtobits(column_real39);
column_real[40] = $realtobits(column_real40);
column_real[41] = $realtobits(column_real41);
column_real[42] = $realtobits(column_real42);
chan_val[0] = column_real[temperature_index];
chan_val[1] = column_real[vccint_index];
chan_val[2] = column_real[vccaux_index];
chan_val[3] = column_real[vp_index];
chan_val[6] = column_real[vbram_index];
chan_val[13] = column_real[vccpint_index];
chan_val[14] = column_real[vccpaux_index];
chan_val[15] = column_real[vccpdro_index];
chan_val[16] = column_real[vauxp_idx0];
chan_val[17] = column_real[vauxp_idx1];
chan_val[18] = column_real[vauxp_idx2];
chan_val[19] = column_real[vauxp_idx3];
chan_val[20] = column_real[vauxp_idx4];
chan_val[21] = column_real[vauxp_idx5];
chan_val[22] = column_real[vauxp_idx6];
chan_val[23] = column_real[vauxp_idx7];
chan_val[24] = column_real[vauxp_idx8];
chan_val[25] = column_real[vauxp_idx9];
chan_val[26] = column_real[vauxp_idx10];
chan_val[27] = column_real[vauxp_idx11];
chan_val[28] = column_real[vauxp_idx12];
chan_val[29] = column_real[vauxp_idx13];
chan_val[30] = column_real[vauxp_idx14];
chan_val[31] = column_real[vauxp_idx15];
chan_valn[3] = column_real[vn_index];
chan_valn[16] = column_real[vauxn_idx0];
chan_valn[17] = column_real[vauxn_idx1];
chan_valn[18] = column_real[vauxn_idx2];
chan_valn[19] = column_real[vauxn_idx3];
chan_valn[20] = column_real[vauxn_idx4];
chan_valn[21] = column_real[vauxn_idx5];
chan_valn[22] = column_real[vauxn_idx6];
chan_valn[23] = column_real[vauxn_idx7];
chan_valn[24] = column_real[vauxn_idx8];
chan_valn[25] = column_real[vauxn_idx9];
chan_valn[26] = column_real[vauxn_idx10];
chan_valn[27] = column_real[vauxn_idx11];
chan_valn[28] = column_real[vauxn_idx12];
chan_valn[29] = column_real[vauxn_idx13];
chan_valn[30] = column_real[vauxn_idx14];
chan_valn[31] = column_real[vauxn_idx15];
// identify columns
if (time_index != -1) begin
prev_time_out = time_out;
time_out = $bitstoreal(column_real[time_index]);
if (prev_time_out > time_out) begin
$display("analog Data File Error : Time value %f is invalid in the input file for XADC instance %m. Time value should increase.", time_out);
infile_format;
end
end
else begin
$display("analog Data File Error : No TIME label is found in the analog data file for XADC instance %m.");
infile_format;
$finish;
end
# ((time_out - prev_time_out) * 1000);
for (p = 0; p < 32; p = p + 1) begin
// assign to real before minus - to work around a bug in modelsim
chan_val_tmp[p] = chan_val[p];
chan_valn_tmp[p] = chan_valn[p];
mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]);
mn_in_diff[p] = $realtobits(mn_in_tmp);
mn_in_uni[p] = chan_val[p];
end
// # ((time_out - prev_time_out) * 1000);
end // if (char_1 == "0" | char_1 == "9")
// Ignore any non-comment, label
else begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
end
end // while (end_file == 0)
end // if (sim_file_flag == 0)
end // initial begin
task infile_format;
begin
$display("\n***** XADC Simulation analog Data File Format *****\n");
$display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n");
$display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] ..... \n");
$display("TIME must be in first column.\n");
$display("Time value need to be integer in ns scale.\n");
$display("analog value need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n");
$display("Each line including header line can not have extra space after the last character/digit.\n");
$display("Each data line must have same number of columns as the header line.\n");
$display("Comment line start with -- or //\n");
$display("Example:\n");
$display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n");
$display("000 125.6 1.0 0.7 0.4 0.3 0.6\n");
$display("200 25.6 0.8 0.5 0.3 0.8 0.2\n");
end
endtask //task infile_format
function [12*8:1] to_upcase_label;
input [12*8:1] in_label;
reg [8:1] tmp_reg;
begin
for (i=0; i< 12; i=i+1) begin
for (j=1; j<=8; j= j+1)
tmp_reg[j] = in_label[i*8+j];
if ((tmp_reg >96) && (tmp_reg<123))
tmp_reg = tmp_reg -32;
for (j=1; j<=8; j= j+1)
to_upcase_label[i*8+j] = tmp_reg[j];
end
end
endfunction
// end read input file
// Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only
always @( posedge busy_r )
begin
if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin
chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]);
chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]);
if ( chan_val_n_tmp > chan_val_p_tmp)
$display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0)
$display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan, chan_val_n_tmp, $time/1000.0);
end
if ((seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b10) && acq_b_u == 0 && rst_in == 0 && ((acq_chan2 == 3) || (acq_chan2 >= 16 && acq_chan2 <= 31))) begin
chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan2]);
chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan2]);
if ( chan_val_n_tmp > chan_val_p_tmp)
$display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan2, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0)
$display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for XADC instance %m at %.3f ns.", acq_chan2, chan_val_n_tmp, $time/1000.0);
end
end
reg seq_reset_busy_out = 0;
wire rst_in_out;
always @(posedge dclk_in or posedge rst_in_out)
if (rst_in_out) begin
busy_rst <= 1;
rst_lock <= 1;
rst_lock_early <= 1;
rst_lock_late <= 1;
busy_rst_cnt <= 0;
end
else begin
if (rst_lock == 1) begin
if (busy_rst_cnt < 29) begin
busy_rst_cnt <= busy_rst_cnt + 1;
if ( busy_rst_cnt == 26)
rst_lock_early <= 0;
end
else begin
busy_rst <= 0;
rst_lock = 0;
end
end
if (busy_out == 0)
rst_lock_late <= 0;
end
initial begin
busy_out = 0;
busy_rst = 0;
busy_conv = 0;
busy_seq_rst = 0;
busy_out_tmp = 0;
end
always @(busy_rst or busy_conv or rst_lock)
if (rst_lock)
busy_out = busy_rst;
else
busy_out = busy_conv;
always @(posedge dclk_in or posedge rst_in)
if (rst_in) begin
busy_conv <= 0;
cal_chan_update <= 0;
end
else begin
if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03) begin
busy_conv <= busy_seq_rst;
end
else if (busy_sync_fall)
busy_conv <= 0;
else if (busy_sync_rise)
busy_conv <= 1;
if (conv_count == 21 && curr_chan == 5'b01000)
cal_chan_update <= 1;
else
cal_chan_update <= 0;
end
always @(posedge dclk_in or rst_lock)
if (rst_lock) begin
busy_sync1 <= 0;
busy_sync2 <= 0;
end
else begin
busy_sync1 <= busy_r;
busy_sync2 <= busy_sync1;
end
assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0;
assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0;
always @(negedge busy_out or posedge busy_r)
if (seq_reset_flag == 1 && seq1_0 == 4'b0000 && curr_clkdiv_sel <= 8'h03) begin
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in)
busy_seq_rst <= 1;
end
else if (seq_reset_flag == 1 && seq1_0 != 4'b0000 && curr_clkdiv_sel <= 8'h03) begin
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in);
@(posedge dclk_in)
@(posedge dclk_in)
@(posedge dclk_in)
busy_seq_rst <= 1;
end
else
busy_seq_rst <= 0;
always @(posedge busy_out or posedge rst_in_out or negedge rst_lock_early)
if (rst_in_out)
muxaddr_out <= 5'b0;
else if (rst_lock_early == 0 && rst_lock_late == 1 )
muxaddr_out <= muxaddr_o;
else begin
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
// @(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk);
@(posedge adcclk)
muxaddr_out <= muxaddr_o;
end
always @(negedge busy_out or posedge busy_out or posedge rst_in_out or posedge cal_chan_update )
if (rst_in_out || rst_lock_late)
channel_out <= 5'b0;
else if (busy_out ==1 && (cal_chan_update == 1) )
channel_out <= 5'b01000;
else if (busy_out == 0) begin
if (curr_seq1_0_lat[3:2] != 2'b10 && xadc2_en == 0 || xadc2_en == 1)
channel_out <= curr_chan;
else
channel_out <= 5'b0;
curr_chan_lat <= curr_chan;
curr_chan_lat2 <= curr_chan2;
end
// START double latch rst_in
reg rst_in1_tmp5;
reg rst_in2_tmp5;
reg rst_in1_tmp6;
reg rst_in2_tmp6;
wire rst_input_t;
wire rst_in2;
initial begin
int_rst = 1;
@(posedge dclk_in)
@(posedge dclk_in)
int_rst <= 0;
end
initial begin
rst_in1_tmp5 = 0;
rst_in2_tmp5 = 0;
rst_in1_tmp6 = 0;
rst_in2_tmp6 = 0;
end
assign #1 rst_input_t = rst_input | int_rst | soft_reset;
always@(posedge adcclk or posedge rst_input_t)
if (rst_input_t) begin
rst_in2_tmp6 <= 1;
rst_in1_tmp6 <= 1;
end
else begin
rst_in2_tmp6 <= rst_in1_tmp6;
rst_in1_tmp6 <= rst_input_t;
end
assign rst_in2 = rst_in2_tmp6;
assign #10 rst_in_not_seq = rst_in2;
assign rst_in = rst_in_not_seq | seq_reset_dly;
assign rst_in_out = rst_in_not_seq | seq_reset_busy_out;
always @(posedge seq_reset) begin
@(posedge dclk_in);
@(posedge dclk_in)
seq_reset_dly <= 1;
@(posedge dclk_in);
@(negedge dclk_in)
seq_reset_busy_out <= 1;
@(posedge dclk_in)
@(posedge dclk_in)
@(posedge dclk_in) begin
seq_reset_dly <= 0;
seq_reset_busy_out <= 0;
end
end
always @(posedge seq_reset_dly or posedge busy_r)
if (seq_reset_dly)
seq_reset_flag <= 1;
else
seq_reset_flag <= 0;
always @(posedge seq_reset_flag or posedge busy_out)
if (seq_reset_flag)
seq_reset_flag_dly <= 1;
else
seq_reset_flag_dly <= 0;
always @(posedge busy_out )
if (seq_reset_flag_dly == 1 && acq_chan == 5'b01000 && seq1_0 == 4'b0000)
first_cal_chan <= 1;
else
first_cal_chan <= 0;
initial begin
conv_time = 18; //minus 3
// conv_time_cal_1 = 70;
// conv_time_cal = 70;
conv_time_cal_1 = 96;
conv_time_cal = 96;
sysclk = 0;
adcclk_tmp = 0;
seq_count = 1;
seq_count_a = 1;
seq_count2 = 1;
eos_en = 0;
eos_tmp_en = 0;
clk_count = -1;
acq_acqsel = 0;
acq_e_c_tmp6 = 0;
acq_e_c_tmp5 = 0;
eoc_en2 = 0;
eoc_en = 0;
eoc_en_delay = 0;
eoc_en_delay2 = 0;
rst_lock = 0;
rst_lock_early = 0;
alarm_update = 0;
drp_update = 0;
cal_chan_update = 0;
adc_state = S3_ST;
scon_tmp = 5'b0;
busy_r = 0;
busy_r_rst = 0;
busy_sync1 = 0;
busy_sync2 = 0;
conv_count = 0;
conv_end = 0;
seq_status_avg = 0;
seq_status_avg2 = 0;
for (i = 0; i <=20; i = i +1)
begin
conv_pj_count2[i] = 0;
conv_acc2[j] = 0;
conv_pj_count[i] = 0;
conv_acc[j] = 0;
end
adc_s1_flag = 0;
for (k = 0; k <= 31; k = k + 1) begin
data_reg[k] = 16'b0;
end
seq_count_en = 0;
eos_out_tmp = 0;
eoc_out_tmp = 0;
eoc_out_tmp2 = 0;
eos_out_tmp1 = 0;
eoc_out_tmp1 = 0;
eoc_out_tmp21 = 0;
eos_out = 0;
eoc_out = 0;
eoc_out_t = 0;
eoc_out2 = 0;
curr_pj_set = 2'b0;
curr_pj_set2 = 2'b0;
curr_e_c = 0;
curr_b_u = 0;
curr_acq = 0;
curr_e_c2 = 0;
curr_b_u2 = 0;
curr_acq2 = 0;
curr_seq1_0 = 4'b0;
curr_seq1_0_lat = 4'b0;
seq1_0 = 4'b0;
ext_mux = 0;
ext_mux_chan = 5'b0;
ext_mux_chan2 = 5'b0;
daddr_in_lat = 7'b0;
data_reg[8] = 16'b0;
data_reg[9] = 16'b0;
data_reg[10] = 16'b0;
data_reg[32] = 16'b0;
data_reg[33] = 16'b0;
data_reg[34] = 16'b0;
data_reg[35] = 16'b0;
data_reg[36] = 16'b1111111111111111;
data_reg[37] = 16'b1111111111111111;
data_reg[38] = 16'b1111111111111111;
data_reg[39] = 16'b1111111111111111;
data_reg[40] = 16'b0;
data_reg[41] = 16'b0;
data_reg[42] = 16'b0;
data_reg[43] = 16'b0;
data_reg[44] = 16'b1111111111111111;
data_reg[45] = 16'b1111111111111111;
data_reg[46] = 16'b1111111111111111;
data_reg[47] = 16'b1111111111111111;
data_reg[48] = 16'b0;
data_reg[49] = 16'b0;
data_reg[50] = 16'b0;
ot_out_reg = 0;
ot_out = 0;
alarm_out_reg = 7'b0;
alarm_out = 7'b0;
curr_chan = 5'b0;
curr_chan_lat = 5'b0;
curr_chan2 = 5'b0;
curr_chan_lat2 = 5'b0;
busy_out = 0;
busy_out_tmp = 0;
curr_seq = 16'b0;
curr_seq_m = 16'b0;
curr_seq2_tmp = 16'b0;
curr_seq2_tmps = 16'b0;
seq_num = 0;
seq_num2 = 0;
seq_reset_flag_dly = 0;
seq_reset_flag = 0;
seq_reset_dly = 0;
ot_en = 1;
alarm_en = 7'b1111111;
do_out_rdtmp = 16'b0;
acq_chan = 5'b0;
acq_chan_m = 5'b0;
acq_chan2 = 5'b0;
acq_b_u = 0;
acq_b_u2 = 0;
conv_result_int = 0;
conv_result = 0;
conv_result_reg = 0;
conv_result_int2 = 0;
conv_result2 = 0;
conv_result_reg2 = 0;
end
// state machine
always @(posedge adcclk or posedge rst_in or sim_file_flag) begin
//CR 675227
if (!(halt_adc == 2 && seq1_0 == 4'b0011)) begin
if (sim_file_flag == 1'b1)
adc_state <= S1_ST;
else if (rst_in == 1'b1 || rst_lock_early == 1)
adc_state <= S1_ST;
else if (rst_in == 1'b0)
adc_state <= next_state;
end
end
always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin
case (adc_state)
S1_ST : next_state = S2_ST;
S2_ST : if (conv_start)
next_state = S3_ST;
else
next_state = S2_ST;
S3_ST : if (conv_end)
next_state = S5_ST;
else
next_state = S3_ST;
S5_ST : if (curr_seq1_0_lat == 4'b0001)
begin
//CR 675227 if (eos_en)
if (eos_tmp_en)
next_state = S6_ST;
else
next_state = S2_ST;
end
else
next_state = S2_ST;
S6_ST : next_state = S1_ST;
default : next_state = S1_ST;
endcase // case(adc_state)
end
// end state machine
// DRPORT - SRAM
initial begin
drdy_out = 0;
drdy_out_tmp1 = 0;
drdy_out_tmp2 = 0;
drdy_out_tmp3 = 0;
drdy_out_tmp4 = 0;
en_data_flag = 0;
do_out = 16'b0;
seq_reset = 0;
cfg_reg1_init = INIT_41;
seq_en = 0;
seq_en_dly = 0;
seq_en <= #20 (cfg_reg1_init[15:12] != 4'b0011 ) ? 1 : 0;
seq_en <= #150 0;
end
always @(posedge drdy_out_tmp3 or posedge gsr_in)
if (gsr_in == 1)
drdy_out <= 0;
else begin
@(posedge dclk_in)
drdy_out <= 1;
@(posedge dclk_in)
drdy_out <= 0;
end
always @(posedge dclk_in or posedge gsr_in)
if (gsr_in == 1) begin
daddr_in_lat <= 7'b0;
do_out <= 16'b0;
end
else begin
if (den_in == 1'b1) begin
if (drdy_out_tmp1 == 1'b0) begin
drdy_out_tmp1 <= 1'b1;
en_data_flag = 1;
daddr_in_lat <= daddr_in;
end
else begin
if (daddr_in != daddr_in_lat)
$display("Warning : input pin DEN on XADC instance %m at time %.3f ns can not continue set to high. Need wait DRDY high and then set DEN high again.", $time/1000.0);
end
end
else
drdy_out_tmp1 <= 1'b0;
drdy_out_tmp2 <= drdy_out_tmp1;
drdy_out_tmp3 <= drdy_out_tmp2;
if (drdy_out_tmp1 == 1)
en_data_flag = 0;
if (drdy_out_tmp3 == 1)
do_out <= do_out_rdtmp;
if (den_in == 1 && (daddr_in >7'h5F || (daddr_in >= 7'h33 && daddr_in < 7'h3F)))
$display("Invalid Input Warning : The DADDR %x to XADC instance %m at time %.3f ns is accessing an undefined location. The data in this location is invalid.", daddr_in, $time/1000.0);
// write all available daddr addresses
if (dwe_in == 1'b1 && en_data_flag == 1) begin
dr_sram[daddr_in] <= di_in;
if (daddr_in == 7'h03)
soft_reset <= 1;
if ( daddr_in == 7'h53) begin
if (di_in[3:0] == 4'b0011)
ot_limit_reg[15:4] <= di_in[15:4];
end
if ( daddr_in == 7'h42 && (di_in[2:0] !=3'b000))
$display(" Invalid Input Error : The DI bit[2:0] %x at DADDR %x on XADC instance %m at %.3f ns is invalid. These must be set to 000.", di_in[2:0], daddr_in, $time/1000.0);
if ( daddr_in >= 7'h43 && daddr_in <= 7'h47 && (di_in[15:0] != 16'h0000))
$display(" Invalid Input Error : The DI value %x at DADDR %x of XADC instance %m at %.3f ns is invalid. These must be set to 0000h.", di_in, daddr_in, $time/1000.0);
if ((daddr_in == 7'h40) && ( di_in[4:0] == 5'b00111
|| (di_in[4:0] >= 5'b01001 && di_in[4:0] <= 5'b01100)))
$display("Invalid Input Warning : The DI bit4:0] at address DADDR %x to XADC instance %m at %.3f ns is %h, which is invalid analog channel.", daddr_in, $time/1000.0, di_in[4:0]);
if (daddr_in == 7'h40) begin
if ((cfg_reg1[15:12]==4'b0011) && (di_in[8]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000))
$display(" Invalid Input warning : The DI value is %x at DADDR %x on XADC instance %m at %.3f ns. Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels", di_in, daddr_in, $time/1000.0);
// if ((cfg_reg1[15:12]==4'b0011) && (di_in[9]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000))
// $display(" Invalid Input warning : The DI value is %x at DADDR %x on XADC instance %m at %.3f ns. Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels", di_in, daddr_in, $time/1000.0);
if ((cfg_reg1[15:12]==4'b0011) && (di_in[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000))
$display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on XADC instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0);
end
if (daddr_in == 7'h41 && en_data_flag == 1) begin
if ((di_in[15:12]==4'b0011) && (cfg_reg0[8]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000))
$display(" Invalid Input warning : The Control Regiter 40h value is %x on XADC instance %m at %.3f ns. Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels", cfg_reg0, $time/1000.0);
// if ((di_in[15:12]==4'b0011) && (cfg_reg0[9]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000))
// $display(" Invalid Input warning : The Control Regiter 40h value is %x on XADC instance %m at %.3f ns. Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels", cfg_reg0, $time/1000.0);
if ((di_in[15:12]!=4'b0011) && (seq_acq_reg1[10:0]!=11'b0) && (seq_acq_reg1[15:12]!=4'b0))
$display(" Invalid Input warning : The Control Regiter 4Eh value is %x on XADC instance %m at %.3f ns. Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels", seq_acq_reg1, $time/1000.0);
if ((di_in[15:12]==4'b0011) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000))
$display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on XADC instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0);
end
if (daddr_in == 7'h41 && en_data_flag == 1) begin
if (den_in == 1'b1 && dwe_in == 1'b1) begin
if (di_in[15:12] != cfg_reg1[15:12])
seq_reset <= 1'b1;
else
seq_reset <= 1'b0;
if (di_in[15:12] != 4'b0011 )
seq_en <= 1'b1;
else
seq_en <= 1'b0;
end
else begin
seq_reset <= 1'b0;
seq_en <= 1'b0;
end
end
// else begin
// seq_reset <= 0;
// seq_en <= 0;
// end // if (daddr_in == 7'h41)
end // dwe ==1
if (seq_en == 1)
seq_en <= 1'b0;
if (seq_reset == 1)
seq_reset <= 1'b0;
if (soft_reset == 1)
soft_reset <= 0;
end // if (gsr == 1)
// DO bus data out
assign tmp_dr_sram_out = ( daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h5F) ?
dr_sram[daddr_in_lat] : 16'b0;
assign status_reg = {8'b0, alarm_out[6:3], ot_out, alarm_out[2:0]};
assign tmp_data_reg_out = (daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h2E) ?
data_reg[daddr_in_lat] : 16'b0;
always @( daddr_in_lat or tmp_data_reg_out or tmp_dr_sram_out or status_reg ) begin
if ((daddr_in_lat >7'h5F || (daddr_in_lat >= 7'h2F && daddr_in_lat < 7'h3F))) begin
do_out_rdtmp = 16'bx;
end
if (daddr_in_lat == 7'h3F) begin
do_out_rdtmp = status_reg;
end
if ((daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h2E))
do_out_rdtmp = tmp_data_reg_out;
else if (daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h5F)
do_out_rdtmp = tmp_dr_sram_out;
end
// end DRP RAM
assign cfg_reg0 = dr_sram[7'h40];
assign cfg_reg1 = dr_sram[7'h41];
assign cfg_reg2 = dr_sram[7'h42];
assign seq_chan_reg1 = dr_sram[7'h48];
assign seq_chan_reg2 = dr_sram[7'h49];
assign seq_pj_reg1 = dr_sram[7'h4A];
assign seq_pj_reg2 = dr_sram[7'h4B];
assign seq_du_reg1 = dr_sram[7'h4C];
assign seq_du_reg2 = dr_sram[7'h4D];
assign seq_acq_reg1 = dr_sram[7'h4E];
assign seq_acq_reg2 = dr_sram[7'h4F];
always @(cfg_reg1)
seq1_0 = cfg_reg1[15:12];
always @(cfg_reg0) begin
ext_mux = cfg_reg0[11];
ext_mux_chan = cfg_reg0[4:0];
ext_mux_chan2 = {2'b11, cfg_reg0[2:0]};
end
always @(posedge drp_update or posedge rst_in)
begin
if (rst_in) begin
@(posedge dclk_in)
@(posedge dclk_in)
seq_bits = seq1_0;
end
else
seq_bits = curr_seq1_0;
if (seq_bits == 4'b0000) begin
alarm_en <= 8'b0;
ot_en <= 1;
end
else begin
ot_en <= ~cfg_reg1[0];
alarm_en[2:0] <= ~cfg_reg1[3:1];
alarm_en[6:3] <= ~cfg_reg1[11:8];
end
end
// end DRPORT - sram
// Clock divider, generate and adcclk
always @(posedge dclk_in)
sysclk <= ~sysclk;
always @(posedge dclk_in)
if (curr_clkdiv_sel > 8'b00000010 ) begin
if (clk_count >= curr_clkdiv_sel - 1)
clk_count = 0;
else
clk_count = clk_count + 1;
if (clk_count > (curr_clkdiv_sel/2) - 1)
adcclk_tmp <= 1;
else
adcclk_tmp <= 0;
end
else
adcclk_tmp <= ~adcclk_tmp;
assign curr_clkdiv_sel = cfg_reg2[15:8];
assign xadc_en = (cfg_reg2[5]===1 && cfg_reg2[4]===1) ? 0 : 1;
assign xadc2_en = (cfg_reg2[5]===1 ) ? 0 : 1;
assign adcclk_div1 = (curr_clkdiv_sel > 8'b00000010) ? 0 : 1;
assign adcclk_r = (adcclk_div1) ? ~sysclk : adcclk_tmp;
assign adcclk = (xadc_en) ? adcclk_r : 0;
// end clock divider
// latch configuration registers
wire [15:0] cfg_reg0_seq, cfg_reg0_adc;
reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5;
reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6;
reg [1:0] acq_avg, acq_avg2;
assign muxaddr_o = (rst_lock_early) ? 5'b0 : (curr_seq1_0_lat[3:2] != 2'b10 && xadc2_en == 0 || xadc2_en == 1) ? acq_chan_m : 5'b0;
always @( seq1_0 or adc_s1_flag or curr_seq_m or cfg_reg0_adc or rst_in) begin
if (rst_in == 0) begin
if (seq1_0[3:2] == 2'b01) begin
acq_chan_m = curr_seq_m[4:0];
end
else if (seq1_0[3:2] == 2'b10) begin
acq_chan_m = curr_seq_m[4:0];
end
else if (seq1_0[3:2] == 2'b11) begin
acq_chan_m = curr_seq_m[4:0];
end
else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin
acq_chan_m = curr_seq_m[4:0];
end
else begin
acq_chan_m = cfg_reg0_adc[4:0];
end
end
end
//CR 675227 always @( seq1_0 or adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin
always @(adc_s1_flag or curr_seq or curr_seq2 or cfg_reg0_adc or rst_in) begin
if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010
|| seq1_0[3:2] == 2'b10 || seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b11) begin
acq_acqsel = curr_seq[8];
end
else if (seq1_0 == 4'b0011) begin
acq_acqsel = cfg_reg0_adc[8];
end
else begin
acq_acqsel = 0;
end
if (rst_in == 0) begin
if (seq1_0[3:2] == 2'b01) begin
acq_avg = curr_seq[13:12];
acq_chan = curr_seq[4:0];
acq_b_u = curr_seq[10];
acq_avg2 = curr_seq2[13:12];
acq_chan2 = curr_seq[4:0] + 8;
acq_b_u2 = curr_seq2[10];
end
else if (seq1_0[3:2] == 2'b10) begin
acq_avg = curr_seq[13:12];
acq_chan = curr_seq[4:0];
acq_b_u = curr_seq[10];
acq_avg2 = 2'b01;
acq_chan2 = curr_seq2[4:0];
acq_b_u2 = 0;
end
else if (seq1_0[3:2] == 2'b11) begin
acq_avg = 2'b01;
acq_chan = curr_seq[4:0];
acq_b_u = 0;
end
else if (seq1_0 != 4'b0011 && adc_s1_flag == 0) begin
acq_avg = curr_seq[13:12];
acq_chan = curr_seq[4:0];
acq_b_u = curr_seq[10];
end
else begin
acq_avg = cfg_reg0_adc[13:12];
acq_chan = cfg_reg0_adc[4:0];
acq_b_u = cfg_reg0_adc[10];
//CR 675227
if (seq1_0 == 4'b0001) begin
halt_adc = halt_adc + 1;
if (halt_adc == 2)
dr_sram[7'h41][15:12] = 4'b0011;
end
end
end
end
reg single_chan_conv_end;
reg [3:0] conv_end_reg_read;
reg busy_reg_read;
reg first_after_reset_tmp5;
reg first_after_reset_tmp6;
always@(posedge adcclk or posedge rst_in)
begin
if(rst_in) conv_end_reg_read <= 4'b0;
else conv_end_reg_read <= {conv_end_reg_read[2:0], single_chan_conv_end | conv_end};
end
always@(posedge DCLK or posedge rst_in)
begin
if(rst_in) busy_reg_read <= 1;
else busy_reg_read <= ~conv_end_reg_read[2];
end
assign cfg_reg0_adc = cfg_reg0_adc_tmp6;
assign cfg_reg0_seq = cfg_reg0_seq_tmp6;
assign acq_e_c = acq_e_c_tmp6;
always @(negedge busy_out or rst_in)
if(rst_in) begin
cfg_reg0_seq_tmp6 <= 16'b0;
cfg_reg0_adc_tmp6 <= 16'b0;
acq_e_c_tmp6 <= 0;
first_after_reset_tmp6 <= 1;
end
else begin
repeat(3) @(posedge DCLK);
if(first_after_reset_tmp6) begin
first_after_reset_tmp6<=0;
cfg_reg0_adc_tmp6 <= cfg_reg0;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
else begin
cfg_reg0_adc_tmp6 <= cfg_reg0_seq;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
acq_e_c_tmp6 <= cfg_reg0[9];
end
always @(posedge conv_start or posedge busy_r_rst or posedge rst_in)
if (rst_in ==1)
busy_r <= 0;
else if (conv_start && rst_lock == 0)
busy_r <= 1;
else if (busy_r_rst)
busy_r <= 0;
always @(negedge busy_out )
if (adc_s1_flag == 1)
curr_seq1_0 <= 4'b0000;
else
curr_seq1_0 <= seq1_0;
// always @(posedge conv_start or posedge rst_in )
always @(posedge conv_start or rst_in )
if (rst_in == 1) begin
mn_mux_in <= 0.0;
mn_mux_in2 <= 0.0;
curr_chan <= 5'b0;
curr_chan2 <= 5'b0;
end
else begin
if ((acq_chan == 5'b00011) || (acq_chan >= 5'b10000 && acq_chan <= 5'b11111)) begin
if (ext_mux == 1) begin
tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan]);
mn_mux_in <= tmp_v;
end
else begin
tmp_v = $bitstoreal(mn_in_diff[acq_chan]);
mn_mux_in <= tmp_v;
end
end
else
mn_mux_in <= $bitstoreal(mn_in_uni[acq_chan]);
tmp_seq1_0 = curr_seq1_0[3:2];
if (tmp_seq1_0 == 2'b01 || tmp_seq1_0 == 2'b10) begin
if ((acq_chan2 == 5'b00011) || (acq_chan2 >= 5'b10000 && acq_chan2 <= 5'b11111)) begin
if (ext_mux == 1) begin
tmp_v1 = $bitstoreal(mn_in_diff[ext_mux_chan2]);
mn_mux_in2 <= tmp_v1;
end
else begin
tmp_v1 = $bitstoreal(mn_in_diff[acq_chan2]);
mn_mux_in2 <= tmp_v1;
end
end
else
mn_mux_in2 <= $bitstoreal(mn_in_uni[acq_chan2]);
end
curr_chan <= acq_chan;
curr_chan2 <= acq_chan2;
curr_seq1_0_lat <= curr_seq1_0;
if ( acq_chan == 5'b00111 || (acq_chan >= 5'b01010 && acq_chan <= 5'b01100))
$display("Invalid Input Warning : The analog channel %x to XADC instance %m at %.3f ns is invalid.", acq_chan, $time/1000.0);
if ((seq1_0 == 4'b0001 && adc_s1_flag == 0) || seq1_0 == 4'b0010 || seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b01 || seq1_0[3:2] == 2'b10 || seq1_0[3:2] == 2'b11) begin
curr_pj_set <= curr_seq[13:12];
curr_b_u <= curr_seq[10];
curr_e_c <= curr_seq[9];
curr_acq <= curr_seq[8];
curr_pj_set2 <= curr_seq2[13:12];
curr_b_u2<= curr_seq2[10];
curr_e_c2 <= curr_seq2[9];
curr_acq2 <= curr_seq2[8];
end
else begin
curr_pj_set <= acq_avg;
curr_b_u <= acq_b_u;
curr_e_c <= cfg_reg0[9];
curr_acq <= cfg_reg0[8];
end
end // if (rst_in == 0)
// end latch configuration registers
// sequence control
always @(seq_en )
seq_en_dly <= #1 seq_en;
always @(posedge seq_en_dly)
if (seq1_0 == 4'b0001 || seq1_0 == 4'b0010) begin
seq_num = 0;
for (si=0; si<= 15; si=si+1) begin
if (seq_chan_reg1[si] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
for (si=16; si<= 31; si=si+1) begin
if (seq_chan_reg2[si-16] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
end
else if (seq1_0[3:2] == 2'b01) begin
seq_num = 0;
for (si=0; si<= 15; si=si+1) begin
if (seq_chan_reg1[si] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
for (si=16; si<= 23; si=si+1) begin
if (seq_chan_reg2[si-16] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
end
else if (seq1_0[3:2] == 2'b10) begin
seq_num = 0;
if (seq_chan_reg1[11] == 1) begin
seq_num = 1;
seq_mem[1] = 11;
end
for (si=16; si<= 31; si=si+1) begin
if (seq_chan_reg2[si-16] ==1) begin
seq_num = seq_num + 1;
seq_mem[seq_num] = si;
end
end
if (simd_f == 0) begin
seq_num2 = 5;
seq_mem2[1] = 0;
seq_mem2[2] = 8;
seq_mem2[3] = 9;
seq_mem2[4] = 10;
seq_mem2[5] = 14;
end
else if (simd_f == 1) begin
seq_num2 = 8;
seq_mem2[1] = 0;
seq_mem2[2] = 5;
seq_mem2[3] = 6;
seq_mem2[4] = 7;
seq_mem2[5] = 8;
seq_mem2[6] = 9;
seq_mem2[7] = 10;
seq_mem2[8] = 14;
end
end
else if (seq1_0 == 4'b0000) begin
if (simd_f == 0) begin
seq_num = 5;
seq_mem[1] = 0;
seq_mem[2] = 8;
seq_mem[3] = 9;
seq_mem[4] = 10;
seq_mem[5] = 14;
end
else if (simd_f == 1) begin
seq_num = 8;
seq_mem[1] = 0;
seq_mem[2] = 5;
seq_mem[3] = 6;
seq_mem[4] = 7;
seq_mem[5] = 8;
seq_mem[6] = 9;
seq_mem[7] = 10;
seq_mem[8] = 14;
end
end
else if (seq1_0[3:2] == 2'b11) begin
if (simd_f == 0) begin
seq_num = 5;
seq_mem[1] = 0;
seq_mem[2] = 8;
seq_mem[3] = 9;
seq_mem[4] = 10;
seq_mem[5] = 14;
end
else if (simd_f == 1) begin
seq_num = 8;
seq_mem[1] = 0;
seq_mem[2] = 5;
seq_mem[3] = 6;
seq_mem[4] = 7;
seq_mem[5] = 8;
seq_mem[6] = 9;
seq_mem[7] = 10;
seq_mem[8] = 14;
end
end
always @( seq_count or negedge seq_en_dly) begin
seq_curr_i = seq_mem[seq_count];
curr_seq = 16'b0;
if (seq_curr_i >= 0 && seq_curr_i <= 15) begin
curr_seq [2:0] = seq_curr_i[2:0];
curr_seq [4:3] = 2'b01;
curr_seq [8] = seq_acq_reg1[seq_curr_i];
curr_seq [10] = seq_du_reg1[seq_curr_i];
if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11)
curr_seq [13:12] = 2'b01;
else if (seq_pj_reg1[seq_curr_i] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
if (seq_curr_i >= 0 && seq_curr_i <=7)
curr_seq [4:3] = 2'b01;
else
curr_seq [4:3] = 2'b00;
end
else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin
curr_seq [4:0] = seq_curr_i;
curr_seq [8] = seq_acq_reg2[seq_curr_i - 16];
curr_seq [10] = seq_du_reg2[seq_curr_i - 16];
if (seq_pj_reg2[seq_curr_i - 16] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
if (seq_curr_i < 24) begin
curr_seq2_tmps[4:0] = seq_curr_i + 8;
curr_seq2_tmps[8] = seq_acq_reg2[seq_curr_i - 8];
curr_seq2_tmps[10] = seq_du_reg2[seq_curr_i - 8];
if (seq_pj_reg2[seq_curr_i - 8] == 1)
curr_seq2_tmps[13:12] = cfg_reg0[13:12];
else
curr_seq2_tmps [13:12] = 2'b00;
end
end
end
assign curr_seq2 = (tmp_seq1_0 == 2'b01) ? curr_seq2_tmps : curr_seq2_tmp;
always @( seq_count_a or negedge seq_en_dly) begin
seq_curr_ia = seq_mem[seq_count_a];
curr_seq_m = 16'b0;
if (seq_curr_ia >= 0 && seq_curr_ia <= 15) begin
curr_seq_m [2:0] = seq_curr_ia[2:0];
curr_seq_m [4:3] = 2'b01;
curr_seq_m [8] = seq_acq_reg1[seq_curr_ia];
curr_seq_m [10] = seq_du_reg1[seq_curr_ia];
if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11)
curr_seq_m [13:12] = 2'b01;
else if (seq_pj_reg1[seq_curr_ia] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
if (seq_curr_ia >= 0 && seq_curr_ia <=7)
curr_seq_m [4:3] = 2'b01;
else
curr_seq_m [4:3] = 2'b00;
end
else if (seq_curr_ia >= 16 && seq_curr_ia <= 31) begin
curr_seq_m [4:0] = seq_curr_ia;
curr_seq_m [8] = seq_acq_reg2[seq_curr_ia - 16];
curr_seq_m [10] = seq_du_reg2[seq_curr_ia - 16];
if (seq_pj_reg2[seq_curr_ia - 16] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
end
end
always @( seq_count2 or negedge seq_en_dly) begin
seq_curr_i2 = seq_mem2[seq_count2];
curr_seq2_tmp = 16'b0;
if (seq_curr_i2 >= 0 && seq_curr_i2 <= 15) begin
curr_seq2_tmp [2:0] = seq_curr_i2[2:0];
curr_seq2_tmp [4:3] = 2'b01;
curr_seq2_tmp [8] = seq_acq_reg1[seq_curr_i2];
curr_seq2_tmp [9] = 0;
curr_seq2_tmp [10] = seq_du_reg1[seq_curr_i2];
if ( seq1_0[3:2] == 2'b10)
curr_seq2_tmp [13:12] = 2'b01;
else
curr_seq2_tmp [13:12] = 2'b00;
if (seq_curr_i2 >= 0 && seq_curr_i2 <=7)
curr_seq2_tmp [4:3] = 2'b01;
else
curr_seq2_tmp [4:3] = 2'b00;
end
else if (seq_curr_i2 >= 16 && seq_curr_i2 <= 31) begin
curr_seq2_tmp [4:0] = seq_curr_i2;
curr_seq2_tmp [8] = seq_acq_reg2[seq_curr_i2 - 16];
curr_seq2_tmp [10] = seq_du_reg2[seq_curr_i2 - 16];
if (seq_pj_reg2[seq_curr_i2 - 16] == 1)
curr_seq2_tmp [13:12] = cfg_reg0[13:12];
else
curr_seq2_tmp [13:12] = 2'b00;
end
end
always @(posedge busy_out or posedge rst_in )
if (rst_in == 1 || rst_lock == 1 ) begin
seq_count_a <= 1;
end
else begin
if ( curr_seq1_0_lat == 4'b0011 )
seq_count_a <= 1;
else begin
if (seq_count_a >= 32 || seq_count_a >= seq_num)
seq_count_a <= 1;
else
seq_count_a <= seq_count_a +1;
end
end
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1 ) begin
seq_count <= 1;
seq_count2 <= 1;
eos_en <= 0;
end
else begin
if (curr_seq1_0_lat[3:2] == 2'b10) begin
if ((seq_count2 >= seq_num2 ) && (adc_state == S5_ST) )
seq_count2 <= 1;
else if (seq_count_en == 1)
seq_count2 <= seq_count2 + 1;
end
if ((seq_count == seq_num ) && (adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && rst_lock == 0)
eos_tmp_en <= 1;
else
eos_tmp_en <= 0;
if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk
eos_en <= 1;
else
eos_en <= 0;
if (eos_tmp_en == 1 || curr_seq1_0_lat == 4'b0011 )
seq_count <= 1;
else if (seq_count_en == 1) begin
if (seq_count >= 32)
seq_count <= 1;
else
seq_count <= seq_count +1;
end
end // else: !if(rst_in == 1)
// end sequence control
// Acquisition
reg first_acq;
reg shorten_acq;
wire busy_out_dly;
assign #10 busy_out_dly = busy_out;
always @(adc_state or posedge rst_in or first_acq)
begin
if(rst_in) shorten_acq = 0;
else if(busy_out_dly==0 && adc_state==S2_ST && first_acq==1)
shorten_acq = 1;
else
shorten_acq = 0;
end
always @(posedge adcclk or posedge rst_in)
// if (rst_in == 1) begin
if (rst_in == 1 || rst_lock == 1) begin
acq_count <= 1;
first_acq <=1;
end
else begin
if (adc_state == S2_ST && rst_lock == 0 && (acq_e_c==0)) begin
first_acq <= 0;
if (acq_acqsel == 1) begin
if (acq_count <= 11)
acq_count <= acq_count + 1 + shorten_acq;
end
else begin
if (acq_count <= 4)
acq_count <= acq_count + 1 + shorten_acq;
end // else: !if(acq_acqsel == 1)
if (next_state == S3_ST)
if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4))
$display ("Warning: Acquisition time is not long enough for XADC instance %m at time %t.", $time);
end // if (adc_state == S2_ST)
else
acq_count <= (first_acq) ? 1 : 0;
end // if (rst_in == 0)
// continuous mode
reg conv_start_cont;
wire reset_conv_start;
wire conv_start_sel;
always @(adc_state or acq_acqsel or acq_count)
if (adc_state == S2_ST) begin
if (rst_lock == 0) begin
if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03))
&& ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) )
conv_start_cont = 1;
else
conv_start_cont = 0;
end
end // if (adc_state == S2_ST)
else
conv_start_cont = 0;
assign conv_start_sel = (acq_e_c) ? convst_in : conv_start_cont;
assign reset_conv_start = rst_in | (conv_count==2);
always@(posedge conv_start_sel or posedge reset_conv_start)
begin
if(reset_conv_start) conv_start <= 0;
else conv_start <= 1;
end
// end acquisition
// Conversion
always @(adc_state or next_state or curr_chan or mn_mux_in or curr_b_u) begin
if ((adc_state == S3_ST && next_state == S5_ST) || adc_state == S5_ST) begin
if (curr_chan == 0) begin // temperature conversion
adc_temp_result = (mn_mux_in + 273.15) * 0.001984226*65536;
if (adc_temp_result >= 65535.0)
conv_result_int = 65535;
else if (adc_temp_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_temp_result);
if (adc_temp_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 1 || curr_chan == 2 || curr_chan ==6 ||
curr_chan == 13 || curr_chan == 14 || curr_chan == 15) begin // internal power conversion
adc_intpwr_result = mn_mux_in * 65536.0 / 3.0;
if (adc_intpwr_result >= 65535.0)
conv_result_int = 65535;
else if (adc_intpwr_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_intpwr_result);
if (adc_intpwr_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin
adc_ext_result = (mn_mux_in) * 65536.0;
if (curr_b_u == 1) begin
if (adc_ext_result > 32767.0)
conv_result_int = 32767;
else if (adc_ext_result < -32768.0)
conv_result_int = -32768;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else begin
if (adc_ext_result > 65535.0)
conv_result_int = 65535;
else if (adc_ext_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
end
else begin
conv_result_int = 0;
end
end
conv_result = conv_result_int;
end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u)
always @(adc_state or next_state or curr_chan2 or mn_mux_in2 or curr_b_u2) begin
if ((adc_state == S3_ST && next_state == S5_ST) || adc_state == S5_ST) begin
if (curr_chan2 == 0) begin // temperature conversion
adc_temp_result2 = (mn_mux_in2 + 273.15) * 0.001984226*65536;
if (adc_temp_result2 >= 65535.0)
conv_result_int2 = 65535;
else if (adc_temp_result2 < 0.0)
conv_result_int2 = 0;
else begin
conv_result_int2 = $rtoi(adc_temp_result2);
if (adc_temp_result2 - conv_result_int2 > 0.9999)
conv_result_int2 = conv_result_int2 + 1;
end
end
else if (curr_chan2 == 1 || curr_chan2 == 2 || curr_chan2 == 6
|| curr_chan2 == 13 || curr_chan2 == 14 || curr_chan2 == 15) begin // internal power conversion
adc_intpwr_result2 = mn_mux_in2 * 65536.0 / 3.0;
if (adc_intpwr_result2 >= 65535.0)
conv_result_int2 = 65535;
else if (adc_intpwr_result2 < 0.0)
conv_result_int2 = 0;
else begin
conv_result_int2 = $rtoi(adc_intpwr_result2);
if (adc_intpwr_result2 - conv_result_int2 > 0.9999)
conv_result_int2 = conv_result_int2 + 1;
end
end
else if (curr_chan2 == 3 || (curr_chan2 >=16 && curr_chan2 <= 31)) begin
adc_ext_result2 = (mn_mux_in2) * 65536.0;
if (curr_b_u2 == 1) begin
if (adc_ext_result2 > 32767.0)
conv_result_int2 = 32767;
else if (adc_ext_result2 < -32768.0)
conv_result_int2 = -32768;
else begin
conv_result_int2 = $rtoi(adc_ext_result2);
if (adc_ext_result2 - conv_result_int2 > 0.9999)
conv_result_int2 = conv_result_int2 + 1;
end
end
else begin
if (adc_ext_result2 > 65535.0)
conv_result_int2 = 65535;
else if (adc_ext_result2 < 0.0)
conv_result_int2 = 0;
else begin
conv_result_int2 = $rtoi(adc_ext_result2);
if (adc_ext_result2 - conv_result_int2 > 0.9999)
conv_result_int2 = conv_result_int2 + 1;
end
end
end
else begin
conv_result_int2 = 0;
end
end
conv_result2 = conv_result_int2;
end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u)
reg busy_r_rst_done;
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
conv_count <= 6;
conv_end <= 0;
seq_status_avg <= 0;
busy_r_rst <= 0;
busy_r_rst_done <= 0;
for (i = 0; i <=31; i = i +1) begin
conv_pj_count[i] <= 0; // array of integer
conv_pj_count2[i] <= 0; // array of integer
end
single_chan_conv_end <= 0;
end
else begin
if(adc_state == S2_ST)
begin
if(busy_r_rst_done == 0) busy_r_rst <= 1;
else busy_r_rst <= 0;
busy_r_rst_done <= 1;
end
if (adc_state == S2_ST && conv_start == 1) begin
conv_count <= 0;
conv_end <= 0;
end
else if (adc_state == S3_ST ) begin
busy_r_rst_done <= 0;
conv_count = conv_count + 1;
if ((curr_chan != 5'b01000 ) && (conv_count == conv_time ) ||
(curr_chan == 5'b01000 ) && (conv_count == conv_time_cal_1 ) && (first_cal_chan==1)
|| (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal) && (first_cal_chan == 0))
conv_end <= 1;
else
conv_end <= 0;
end
else begin
conv_end <= 0;
conv_count <= 0;
end
// jmcgrath - to model the behaviour correctly when a cal chanel is being converted
// an signal to signify the conversion has ended must be produced - this is for single channel mode
single_chan_conv_end <= 0;
if( (conv_count == conv_time) || (conv_count == 44))
single_chan_conv_end <= 1;
if (adc_state == S3_ST && next_state == S5_ST && rst_lock == 0) begin
case (curr_pj_set)
2'b00 : begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
end
2'b01 : if (conv_pj_count[curr_chan] == 15) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
2'b10 : if (conv_pj_count[curr_chan] == 63) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
2'b11 : if (conv_pj_count[curr_chan] == 255) begin
eoc_en <= 1;
conv_pj_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_pj_count[curr_chan] == 0)
seq_status_avg <= seq_status_avg + 1;
conv_pj_count[curr_chan] <= conv_pj_count[curr_chan] + 1;
end
default : eoc_en <= 0;
endcase // case(curr_pj_set)
case (curr_pj_set2)
2'b00 : begin
eoc_en2 <= 1;
conv_pj_count2[curr_chan2] <= 0;
end
2'b01 : if (conv_pj_count2[curr_chan2] == 15) begin
eoc_en2 <= 1;
conv_pj_count2[curr_chan2] <= 0;
seq_status_avg2 <= seq_status_avg2 - 1;
end
else begin
eoc_en2 <= 0;
if (conv_pj_count2[curr_chan2] == 0)
seq_status_avg2 <= seq_status_avg2 + 1;
conv_pj_count2[curr_chan2] <= conv_pj_count2[curr_chan2] + 1;
end
2'b10 : if (conv_pj_count2[curr_chan2] == 63) begin
eoc_en2 <= 1;
conv_pj_count2[curr_chan2] <= 0;
seq_status_avg2 <= seq_status_avg2 - 1;
end
else begin
eoc_en2 <= 0;
if (conv_pj_count2[curr_chan2] == 0)
seq_status_avg2 <= seq_status_avg2 + 1;
conv_pj_count[curr_chan2] <= conv_pj_count[curr_chan2] + 1;
end
2'b11 : if (conv_pj_count2[curr_chan2] == 255) begin
eoc_en2 <= 1;
conv_pj_count2[curr_chan2] <= 0;
seq_status_avg2 <= seq_status_avg2 - 1;
end
else begin
eoc_en2 <= 0;
if (conv_pj_count2[curr_chan2] == 0)
seq_status_avg2 <= seq_status_avg2 + 1;
conv_pj_count2[curr_chan2] <= conv_pj_count2[curr_chan2] + 1;
end
default : eoc_en2 <= 0;
endcase // case(curr_pj_set)
end // if (adc_state == S3_ST && next_state == S5_ST)
else begin
eoc_en <= 0;
eoc_en2 <= 0;
end
if (adc_state == S5_ST) begin
conv_result_reg <= conv_result;
conv_result_reg2 <= conv_result2;
end
end // if (rst_in == 0)
// end conversion
// average
always @(adc_state or conv_acc[curr_chan])
if (adc_state == S5_ST )
// no signed or unsigned differences for bit vector conv_acc_vec
conv_acc_vec = conv_acc[curr_chan];
else
conv_acc_vec = 24'b00000000000000000000;
always @(adc_state or conv_acc2[curr_chan2])
if (adc_state == S5_ST )
// no signed or unsigned differences for bit vector conv_acc_vec
conv_acc_vec2 = conv_acc2[curr_chan2];
else
conv_acc_vec2 = 24'b00000000000000000000;
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
for (j = 0; j <= 31; j = j + 1) begin
conv_acc[j] <= 0;
conv_acc2[j] <= 0;
end
conv_acc_result <= 16'b0000000000000000;
conv_acc_result2 <= 16'b0000000000000000;
end
else begin
if (adc_state == S3_ST && next_state == S5_ST) begin
if (curr_pj_set != 2'b00 && rst_lock != 1)
conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int;
else
conv_acc[curr_chan] <= 0;
if (curr_pj_set2 != 2'b00 && rst_lock != 1)
conv_acc2[curr_chan2] <= conv_acc2[curr_chan2] + conv_result_int2;
else
conv_acc2[curr_chan2] <= 0;
end
else if (eoc_en == 1) begin
case (curr_pj_set)
2'b00 : conv_acc_result <= 16'b0000000000000000;
2'b01 : conv_acc_result <= conv_acc_vec[19:4];
2'b10 : conv_acc_result <= conv_acc_vec[21:6];
2'b11 : conv_acc_result <= conv_acc_vec[23:8];
endcase
conv_acc[curr_chan] <= 0;
end
else if (eoc_en2 == 1 ) begin
case (curr_pj_set2)
2'b00 : conv_acc_result2 <= 16'b0000000000000000;
2'b01 : conv_acc_result2 <= conv_acc_vec2[19:4];
2'b10 : conv_acc_result2 <= conv_acc_vec2[21:6];
2'b11 : conv_acc_result2 <= conv_acc_vec2[23:8];
endcase
conv_acc2[curr_chan2] <= 0;
end
end // if (rst_in == 0)
// end average
// single sequence
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1)
adc_s1_flag <= 0;
else
if (adc_state == S6_ST)
adc_s1_flag <= 1;
// end state
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
seq_count_en <= 0;
eos_out_tmp <= 0;
eoc_out_tmp <= 0;
eoc_out_tmp2 <= 0;
end
else begin
if ((adc_state == S3_ST && next_state == S5_ST) && (curr_seq1_0_lat != 4'b0011) && (rst_lock == 0))
seq_count_en <= 1;
else
seq_count_en <= 0;
if (rst_lock == 0) begin
eos_out_tmp <= eos_en;
eoc_en_delay <= eoc_en;
eoc_out_tmp <= eoc_en_delay;
if (curr_seq1_0_lat[3:2] != 2'b00) begin
eoc_en_delay2 <= eoc_en2;
eoc_out_tmp2 <= eoc_en_delay2;
end
end
else begin
eos_out_tmp <= 0;
eoc_en_delay <= 0;
eoc_out_tmp <= 0;
eoc_en_delay2 <= 0;
eoc_out_tmp2 <= 0;
end
end
// assign eoc_out_t = eoc_out | eoc_out2;
always @(eoc_out or eoc_out2)
eoc_out_t <= #1 (eoc_out | eoc_out2);
always @(posedge eoc_out_t or posedge rst_in_not_seq)
if (rst_in_not_seq == 1) begin
for (k = 32; k <= 39; k = k + 1)
if (k >= 36)
data_reg[k] <= 16'b1111111111111111;
else
data_reg[k] <= 16'b0000000000000000;
for (k = 40; k <= 42; k = k + 1)
data_reg[k] <= 16'b0000000000000000;
for (k = 44; k <= 46; k = k + 1)
data_reg[k] <= 16'b1111111111111111;
end
else
if ( rst_lock == 0) begin
if (eoc_out == 1) begin
if ((curr_chan_lat >= 0 && curr_chan_lat <= 3) || (curr_chan_lat == 6) ||
(curr_chan_lat >= 13 && curr_chan_lat <= 31)) begin
if (curr_pj_set == 2'b00)
data_reg[curr_chan_lat] <= conv_result_reg;
else
data_reg[curr_chan_lat] <= conv_acc_result;
end
if (curr_chan_lat == 4)
data_reg[curr_chan_lat] <= 16'hD555;
if (curr_chan_lat == 5)
data_reg[curr_chan_lat] <= 16'h0000;
if (curr_chan_lat == 0 || curr_chan_lat == 1 || curr_chan_lat == 2) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_result_reg;
if (conv_result_reg < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_acc_result;
if (conv_acc_result < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_acc_result;
end
end
if (curr_chan_lat == 6) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[35])
data_reg[35] <= conv_result_reg;
if (conv_result_reg < data_reg[39])
data_reg[39] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[35])
data_reg[35] <= conv_acc_result;
if (conv_acc_result < data_reg[39])
data_reg[39] <= conv_acc_result;
end
end
if (curr_chan_lat == 5'b01101) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[40])
data_reg[40] <= conv_result_reg;
if (conv_result_reg < data_reg[44])
data_reg[44] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[40])
data_reg[40] <= conv_acc_result;
if (conv_acc_result < data_reg[44])
data_reg[44] <= conv_acc_result;
end
end
if (curr_chan_lat == 5'b01110) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[41])
data_reg[41] <= conv_result_reg;
if (conv_result_reg < data_reg[45])
data_reg[45] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[41])
data_reg[41] <= conv_acc_result;
if (conv_acc_result < data_reg[45])
data_reg[45] <= conv_acc_result;
end
end
if (curr_chan_lat == 5'b01111) begin
if (curr_pj_set == 2'b00) begin
if (conv_result_reg > data_reg[42])
data_reg[42] <= conv_result_reg;
if (conv_result_reg < data_reg[46])
data_reg[46] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[42])
data_reg[42] <= conv_acc_result;
if (conv_acc_result < data_reg[46])
data_reg[46] <= conv_acc_result;
end
end
end
if (eoc_out2 == 1) begin
if ((curr_chan_lat2 >= 0 && curr_chan_lat2 <= 3) || (curr_chan_lat2 == 6) ||
(curr_chan_lat2 >= 13 && curr_chan_lat2 <= 31)) begin
if (curr_pj_set2 == 2'b00)
data_reg[curr_chan_lat2] <= conv_result_reg2;
else
data_reg[curr_chan_lat2] <= conv_acc_result2;
end
if (curr_chan_lat2 == 4)
data_reg[curr_chan_lat2] <= 16'hD555;
if (curr_chan_lat2 == 5)
data_reg[curr_chan_lat2] <= 16'h0000;
if (curr_chan_lat2 == 0 || curr_chan_lat2 == 1 || curr_chan_lat2 == 2) begin
if (curr_pj_set2 == 2'b00) begin
if (conv_result_reg2 > data_reg[32 + curr_chan_lat2])
data_reg[32 + curr_chan_lat2] <= conv_result_reg2;
if (conv_result_reg2 < data_reg[36 + curr_chan_lat2])
data_reg[36 + curr_chan_lat2] <= conv_result_reg2;
end
else begin
if (conv_acc_result2 > data_reg[32 + curr_chan_lat2])
data_reg[32 + curr_chan_lat2] <= conv_acc_result2;
if (conv_acc_result2 < data_reg[36 + curr_chan_lat2])
data_reg[36 + curr_chan_lat2] <= conv_acc_result2;
end
end
if (curr_chan_lat2 == 6) begin
if (curr_pj_set2 == 2'b00) begin
if (conv_result_reg2 > data_reg[35])
data_reg[35] <= conv_result_reg2;
if (conv_result_reg2 < data_reg[39])
data_reg[39] <= conv_result_reg2;
end
else begin
if (conv_acc_result2 > data_reg[35])
data_reg[35] <= conv_acc_result2;
if (conv_acc_result2 < data_reg[39])
data_reg[39] <= conv_acc_result2;
end
end
if (curr_chan_lat2 == 5'b01101) begin
if (curr_pj_set2 == 2'b00) begin
if (conv_result_reg2 > data_reg[40])
data_reg[40] <= conv_result_reg2;
if (conv_result_reg2 < data_reg[44])
data_reg[44] <= conv_result_reg2;
end
else begin
if (conv_acc_result2 > data_reg[40])
data_reg[40] <= conv_acc_result2;
if (conv_acc_result2 < data_reg[44])
data_reg[44] <= conv_acc_result2;
end
end
if (curr_chan_lat2 == 5'b01110) begin
if (curr_pj_set2 == 2'b00) begin
if (conv_result_reg2 > data_reg[41])
data_reg[41] <= conv_result_reg2;
if (conv_result_reg2 < data_reg[45])
data_reg[45] <= conv_result_reg2;
end
else begin
if (conv_acc_result2 > data_reg[41])
data_reg[41] <= conv_acc_result2;
if (conv_acc_result2 < data_reg[45])
data_reg[45] <= conv_acc_result2;
end
end
if (curr_chan_lat2 == 5'b01111) begin
if (curr_pj_set2 == 2'b00) begin
if (conv_result_reg2 > data_reg[42])
data_reg[42] <= conv_result_reg2;
if (conv_result_reg2 < data_reg[46])
data_reg[46] <= conv_result_reg2;
end
else begin
if (conv_acc_result2 > data_reg[42])
data_reg[42] <= conv_acc_result2;
if (conv_acc_result2 < data_reg[46])
data_reg[46] <= conv_acc_result2;
end
end
end
end
reg [15:0] data_written;
always @(negedge busy_r or posedge rst_in_not_seq)
if (rst_in_not_seq)
data_written <= 16'b0;
else begin
if (curr_seq1_0[3:2] != 2'b10) begin
if (curr_pj_set == 2'b00)
data_written <= conv_result_reg;
else
data_written <= conv_acc_result;
end
else begin
if (curr_pj_set2 == 2'b00)
data_written <= conv_result_reg2;
else
data_written <= conv_acc_result2;
end
end
reg [4:0] op_count=15;
reg busy_out_sync;
wire busy_out_low_edge;
// eos and eoc
always @( posedge eoc_out_tmp or posedge eoc_out or posedge rst_in)
if (rst_in ==1)
eoc_out_tmp1 <= 0;
else if ( eoc_out ==1)
eoc_out_tmp1 <= 0;
else if ( eoc_out_tmp == 1) begin
if (curr_chan != 5'b01000 && ( xadc2_en == 1 || (curr_seq1_0[3:2] != 2'b10 && xadc2_en == 0)))
eoc_out_tmp1 <= 1;
else
eoc_out_tmp1 <= 0;
end
always @( posedge eoc_out_tmp2 or posedge eoc_out2 or posedge rst_in)
if (rst_in ==1)
eoc_out_tmp21 <= 0;
else if ( eoc_out2 ==1)
eoc_out_tmp21 <= 0;
else if ( eoc_out_tmp2 == 1) begin
if (curr_chan2 != 5'b01000 && ( xadc2_en == 1 || (curr_seq1_0[3:2] == 2'b10 && xadc2_en == 0)))
eoc_out_tmp21 <= 1;
else
eoc_out_tmp21 <= 0;
end
always @( posedge eos_out_tmp or posedge eos_out or posedge rst_in)
if (rst_in ==1)
eos_out_tmp1 <= 0;
else if ( eos_out ==1)
eos_out_tmp1 <= 0;
else if ( eos_out_tmp == 1 && ( xadc2_en == 1 || (curr_seq1_0[3:2] != 2'b10 && xadc2_en == 0)))
eos_out_tmp1 <= 1;
assign busy_out_low_edge = (busy_out==0 && busy_out_sync==1) ? 1 : 0;
always @( posedge dclk_in or posedge rst_in)
begin
if (rst_in) begin
op_count <= 15;
busy_out_sync <= 0;
end
drp_update <= 0;
alarm_update <= 0;
eoc_out <= 0;
eoc_out2 <= 0;
eos_out <= 0;
if(rst_in==0)
begin
busy_out_sync <= busy_out;
if(op_count==3) drp_update <= 1;
if(op_count==5 && (eoc_out_tmp1==1 || eoc_out_tmp21 == 1))
alarm_update <=1;
// if(op_count==9 ) begin
if(op_count== 16 ) begin
eoc_out <= eoc_out_tmp1;
eoc_out2 <= eoc_out_tmp21;
end
// if(op_count==9) eos_out <= eos_out_tmp1;
if(op_count==16) eos_out <= eos_out_tmp1;
if (busy_out_low_edge==1 )
op_count <= 0;
else if(op_count < 22) op_count <= op_count +1;
end
end
// end eos and eoc
// alarm
always @( posedge alarm_update or posedge rst_in_not_seq )
if (rst_in_not_seq == 1) begin
ot_out_reg <= 0;
alarm_out_reg <= 8'b0;
end
else
if (rst_lock == 0) begin
if (curr_chan_lat == 0) begin
if (data_written >= ot_limit_reg)
ot_out_reg <= 1;
else if (data_written < dr_sram[7'h57])
ot_out_reg <= 0;
if (data_written > dr_sram[7'h50])
alarm_out_reg[0] <= 1;
else if (data_written < dr_sram[7'h54])
alarm_out_reg[0] <= 0;
end
if (curr_chan_lat == 1) begin
if (data_written > dr_sram[7'h51] || data_written < dr_sram[7'h55])
alarm_out_reg[1] <= 1;
else
alarm_out_reg[1] <= 0;
end
if (curr_chan_lat == 2) begin
if (data_written > dr_sram[7'h52] || data_written < dr_sram[7'h56])
alarm_out_reg[2] <= 1;
else
alarm_out_reg[2] <= 0;
end
if (curr_chan_lat == 6) begin
if (data_written > dr_sram[7'h58] || data_written < dr_sram[7'h5C])
alarm_out_reg[3] <= 1;
else
alarm_out_reg[3] <= 0;
end
if (curr_chan_lat == 5'b01101) begin
if (data_written > dr_sram[7'h59] || data_written < dr_sram[7'h5D]) alarm_out_reg[4] <= 1;
else
alarm_out_reg[4] <= 0;
end
if (curr_chan_lat == 5'b01110) begin
if (data_written > dr_sram[7'h5A] || data_written < dr_sram[7'h5E]) alarm_out_reg[5] <= 1;
else
alarm_out_reg[5] <= 0;
end
if (curr_chan_lat == 5'b01111) begin
if (data_written > dr_sram[7'h5B] || data_written < dr_sram[7'h5F]) alarm_out_reg[6] <= 1;
else
alarm_out_reg[6] <= 0;
end
end // always
always @(ot_out_reg or ot_en or alarm_out_reg or alarm_en)
begin
ot_out = ot_out_reg & ot_en;
alarm_out[6:0] = alarm_out_reg[6:0] & alarm_en[6:0];
alarm_out[7] = |alarm_out[6:0];
end
// end alarm
//*** Timing_Checks_Start_here
always @(notifier) begin
alarm_out_reg = 7'bx;
ot_out = 1'bx;
busy_out = 1'bx;
eoc_out = 1'bx;
eos_out = 1'bx;
curr_chan = 5'bx;
drdy_out = 1'bx;
do_out = 16'bx;
end
always @(notifier_do) begin
drdy_out = 1'bx;
do_out = 16'bx;
end
specify
(DCLK => ALM) = (100:100:100, 100:100:100);
(DCLK => BUSY) = (100:100:100, 100:100:100);
(DCLK => CHANNEL) = (100:100:100, 100:100:100);
(DCLK => DO) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => EOC) = (100:100:100, 100:100:100);
(DCLK => EOS) = (100:100:100, 100:100:100);
(DCLK => JTAGBUSY) = (100:100:100, 100:100:100);
(DCLK => JTAGLOCKED) = (100:100:100, 100:100:100);
(DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100);
(DCLK => MUXADDR) = (100:100:100, 100:100:100);
(DCLK => OT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CONVST, 0:0:0, notifier);
$period (posedge CONVSTCLK, 0:0:0, notifier);
$period (negedge CONVSTCLK, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (posedge DCLK, negedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (posedge DCLK, negedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (posedge DCLK, negedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (posedge DCLK, posedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (posedge DCLK, posedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (posedge DCLK, posedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (posedge DCLK, posedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (negedge DCLK, negedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (negedge DCLK, negedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (negedge DCLK, negedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (negedge DCLK, negedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
$setuphold (negedge DCLK, posedge DADDR &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DADDR_dly);
$setuphold (negedge DCLK, posedge DEN &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DEN_dly);
$setuphold (negedge DCLK, posedge DI &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DI_dly);
$setuphold (negedge DCLK, posedge DWE &&& (rst_input === 0), 0:0:0, 0:0:0, notifier_do,,,DCLK_dly,DWE_dly);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/XORCY.v 0000664 0000000 0000000 00000002271 12327044266 0022330 0 ustar 00root root 0000000 0000000 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / XOR for Carry Logic with General Output
// /___/ /\ Filename : XORCY.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module XORCY (O, CI, LI);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input CI, LI;
xor X1 (O, CI, LI);
`ifdef XIL_TIMING
specify
(CI => O) = (0:0:0, 0:0:0);
(LI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
x393-313a1564d4ffd6f3b3abdc79dd9ce5b34773f8de/unisims/ZHOLD_DELAY.v 0000664 0000000 0000000 00000015734 12327044266 0023232 0 ustar 00root root 0000000 0000000 ///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx TEST ONLY Library Component
// / / Delay Element.
// /___/ /\ Filename : ZHOLD_DELAY.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/14/10 - Initial version.
// 05/12/11 - 609212 -- fix for ncsim
// 07/11/11 - 616630 -- Change/Combine attributes
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/10/12 - 659430 - remove GSR ref, ANSI ports, mti simprim error (add #1)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ZHOLD_DELAY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif // ifdef XIL_TIMING
parameter [0:0] IS_DLYIN_INVERTED = 1'b0,
parameter ZHOLD_FABRIC = "DEFAULT", // {"DEFAULT", "0", .... "31"}
parameter ZHOLD_IFF = "DEFAULT" // {"DEFAULT", "0", .... "31"}
) (
output DLYFABRIC,
output DLYIFF,
input DLYIN
);
localparam MODULE_NAME = "ZHOLD_DELAY";
//------------------- constants ------------------------------------
localparam MAX_IFF_DELAY_COUNT = 31;
localparam MIN_IFF_DELAY_COUNT = 0;
localparam MAX_IDELAY_COUNT = 31;
localparam MIN_IDELAY_COUNT = 0;
`ifndef XIL_TIMING
real TAP_DELAY = 200.0;
`endif // ifndef XIL_TIMING
integer idelay_count=0;
integer iff_idelay_count=0;
// inputs
wire dlyin_in;
`ifndef XIL_TIMING
// outputs
reg tap_out_fabric = 0;
reg tap_out_iff = 0;
`endif // ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
`ifdef XIL_TIMING
assign #1 DLYFABRIC = dlyin_in;
assign #1 DLYIFF = dlyin_in;
`else // ifdef XIL_TIMING
assign DLYFABRIC = tap_out_fabric;
assign DLYIFF = tap_out_iff;
`endif // ifdef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign dlyin_in = IS_DLYIN_INVERTED ^ DLYIN;
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- ZHOLD_FABRIC check
case (ZHOLD_FABRIC)
"DEFAULT" : idelay_count = 0;
"0" : idelay_count = 0;
"1" : idelay_count = 1;
"2" : idelay_count = 2;
"3" : idelay_count = 3;
"4" : idelay_count = 4;
"5" : idelay_count = 5;
"6" : idelay_count = 6;
"7" : idelay_count = 7;
"8" : idelay_count = 8;
"9" : idelay_count = 9;
"10" : idelay_count = 10;
"11" : idelay_count = 11;
"12" : idelay_count = 12;
"13" : idelay_count = 13;
"14" : idelay_count = 14;
"15" : idelay_count = 15;
"16" : idelay_count = 16;
"17" : idelay_count = 17;
"18" : idelay_count = 18;
"19" : idelay_count = 19;
"20" : idelay_count = 20;
"21" : idelay_count = 21;
"22" : idelay_count = 22;
"23" : idelay_count = 23;
"24" : idelay_count = 24;
"25" : idelay_count = 25;
"26" : idelay_count = 26;
"27" : idelay_count = 27;
"28" : idelay_count = 28;
"29" : idelay_count = 29;
"30" : idelay_count = 30;
"31" : idelay_count = 31;
default : begin
$display("Attribute Syntax Error : The attribute ZHOLD_FABRIC on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\" ..... \"31\"",MODULE_NAME,ZHOLD_FABRIC);
$finish;
end
endcase
//-------- ZHOLD_IFF check
case (ZHOLD_IFF)
"DEFAULT" : iff_idelay_count = 0;
"0" : iff_idelay_count = 0;
"1" : iff_idelay_count = 1;
"2" : iff_idelay_count = 2;
"3" : iff_idelay_count = 3;
"4" : iff_idelay_count = 4;
"5" : iff_idelay_count = 5;
"6" : iff_idelay_count = 6;
"7" : iff_idelay_count = 7;
"8" : iff_idelay_count = 8;
"9" : iff_idelay_count = 9;
"10" : iff_idelay_count = 10;
"11" : iff_idelay_count = 11;
"12" : iff_idelay_count = 12;
"13" : iff_idelay_count = 13;
"14" : iff_idelay_count = 14;
"15" : iff_idelay_count = 15;
"16" : iff_idelay_count = 16;
"17" : iff_idelay_count = 17;
"18" : iff_idelay_count = 18;
"19" : iff_idelay_count = 19;
"20" : iff_idelay_count = 20;
"21" : iff_idelay_count = 21;
"22" : iff_idelay_count = 22;
"23" : iff_idelay_count = 23;
"24" : iff_idelay_count = 24;
"25" : iff_idelay_count = 25;
"26" : iff_idelay_count = 26;
"27" : iff_idelay_count = 27;
"28" : iff_idelay_count = 28;
"29" : iff_idelay_count = 29;
"30" : iff_idelay_count = 30;
"31" : iff_idelay_count = 31;
default : begin
$display("Attribute Syntax Error : The attribute ZHOLD_IFF on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\"...\"31\"",MODULE_NAME,ZHOLD_IFF);
$finish;
end
endcase
end // initial begin
`ifndef XIL_TIMING
always@(dlyin_in) begin
tap_out_fabric <= #(TAP_DELAY*idelay_count) dlyin_in;
tap_out_iff <= #(TAP_DELAY*iff_idelay_count) dlyin_in;
end // end always
`endif // ifndef XIL_TIMING
specify
`ifdef XIL_TIMING
( DLYIN => DLYFABRIC) = (0:0:0, 0:0:0);
( DLYIN => DLYIFF) = (0:0:0, 0:0:0);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // ZHOLD_DELAY
`endcelldefine