pax_global_header 0000666 0000000 0000000 00000000064 12327746175 0014530 g ustar 00root root 0000000 0000000 52 comment=023b001574dd9f79be652f091f4761ea273a1a37
x393-023b001574dd9f79be652f091f4761ea273a1a37/ 0000775 0000000 0000000 00000000000 12327746175 0017011 5 ustar 00root root 0000000 0000000 x393-023b001574dd9f79be652f091f4761ea273a1a37/.gitignore 0000664 0000000 0000000 00000000011 12327746175 0020771 0 ustar 00root root 0000000 0000000 /unisims
x393-023b001574dd9f79be652f091f4761ea273a1a37/.project 0000664 0000000 0000000 00000002575 12327746175 0020471 0 ustar 00root root 0000000 0000000
eddr3
com.elphel.vdt.veditor.simulateBuilder
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com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder
0
com.elphel.vdt.veditor.simulateBuilder.00000000Default.command
echo 'No Build Configuration Specified'
com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable
true
com.elphel.vdt.veditor.simulateBuilder.00000000Default.name
Default
com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser
com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder
com.elphel.vdt.veditor.HdlNature
x393-023b001574dd9f79be652f091f4761ea273a1a37/.settings/ 0000775 0000000 0000000 00000000000 12327746175 0020727 5 ustar 00root root 0000000 0000000 x393-023b001574dd9f79be652f091f4761ea273a1a37/.settings/com.elphel.vdt.prefs 0000664 0000000 0000000 00000000227 12327746175 0024613 0 ustar 00root root 0000000 0000000 com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
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eclipse.preferences.version=1
x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/ 0000775 0000000 0000000 00000000000 12327746175 0017611 5 ustar 00root root 0000000 0000000 x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/ 0000775 0000000 0000000 00000000000 12327746175 0020562 5 ustar 00root root 0000000 0000000 x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/idelay_ctrl.v 0000664 0000000 0000000 00000002410 12327746175 0023241 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_ctrl
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYCTRL wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_ctrl.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_ctrl
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY"
) (
input refclk,
input rst,
output rdy
);
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYCTRL idelay_ctrl_i(
.RDY(rdy),
.REFCLK(refclk),
.RST(rst));
endmodule
x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/idelay_fine_pipe.v 0000664 0000000 0000000 00000005025 12327746175 0024240 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: idelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: IDELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* idelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module idelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_DATAIN_INVERTED(1'b0),
.IS_IDATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
idelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.DATAIN(1'b0),
.IDATAIN(data_in),
.IFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/iserdes_mem.v 0000664 0000000 0000000 00000013651 12327746175 0023253 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: iserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: ISERDESE2/ISERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* iserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* iserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module iserdes_mem(
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
input oclk_div, // oclk divided by 2, front aligned
input rst, // reset
input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
input ddly, // serial input from idelay
output [3:0] dout
);
parameter IOBDELAY = "IFD"; // "NONE", "IBUF", "IFD", "BOTH"
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIVP (), // used with phasers, source-sync
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OCLKB (!oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
ISERDESE1 #(
.DATA_RATE ("DDR"),
.DATA_WIDTH (4),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("MEMORY"),
.NUM_CE (1),
.IOBDELAY (IOBDELAY),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0)
)
iserdes_i
(
.O (),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iclk),
.CLKB (!iclk),
.CLKDIV (oclk_div),
.DDLY (ddly),
.D (d_direct), // direct connection to IOB bypassing idelay
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OCLK (oclk),
.OFB (),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
`endif
endmodule
x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/odelay_fine_pipe.v 0000664 0000000 0000000 00000004763 12327746175 0024256 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: odelay_fine_pipe
* Date:2014-04-25
* Author: Andrey Filippov
* Description: ODELAYE2_FINEDELAY wrapper with fine control pipelined
*
* Copyright (c) 2014 Elphel, Inc.
* idelay_fine_pipe.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* odelay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
module odelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter integer DELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
) (
input clk,
input rst,
input set,
input ld,
input [7:0] delay,
input data_in,
output data_out
);
reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
always @ (posedge clk or posedge rst) begin
if (rst) fdly_pre <= DELAY_VALUE[2:0];
else if (ld) fdly_pre <= delay[2:0];
if (rst) fdly <= DELAY_VALUE[2:0];
else if (set) fdly <= fdly_pre;
end
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
#(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
.FINEDELAY("ADD_DLY"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.ODELAY_TYPE("VAR_LOAD_PIPE"),
.ODELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_ODATAIN_INVERTED(1'b0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
)
odelay2_finedelay_i(
.CNTVALUEOUT(),
.DATAOUT(data_out),
.C(clk),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(delay[7:3]),
.CLKIN(1'b0),
.ODATAIN(data_in),
.OFDLY(fdly),
.INC(1'b0),
.LD(set),
.LDPIPEEN(ld),
.REGRST(rst)
);
endmodule
x393-023b001574dd9f79be652f091f4761ea273a1a37/phy/wrap/oserdes_mem.v 0000664 0000000 0000000 00000013661 12327746175 0023262 0 ustar 00root root 0000000 0000000 /*******************************************************************************
* Module: oserdes_mem
* Date:2014-04-26
* Author: Andrey Filippov
* Description: OSERDESE2/OSERDESE1 wrapper to use for DDR3 memory w/o phasers
*
* Copyright (c) 2014 Elphel, Inc.
* oserdes_mem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oserdes_mem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*******************************************************************************/
`timescale 1ns/1ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module oserdes_mem(
input clk, // serial output clock
input clk_div, // oclk divided by 2, front aligned
input rst, // reset
input [3:0] din, // parallel data in
input [3:0] tin, // parallel tri-state in
output dout_dly, // data out to be connected to odelay input
output dout_iob, // data out to be connected directly to the output buffer
output tout_dly, // tristate out to be connected to odelay input
output tout_iob // tristate out to be connected directly to the tristate control of the output buffer
);
/*
Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
go directly. Luckily the active time for DQ/DQS may be extended (there is at least 1 full clock period
between READ and WRITE DQS active (more for DQ), so extending write preamble and postabmble by 1/2 period
seems to be OK.
*/
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 (din[2]),
.D4 (din[3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 (tin[2]),
.T4 (tin[3]),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN ()
);
`else // Simulating, use Virtex 6 module that does not have encrypted functionality
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.DDR3_DATA (1), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3"
.ODELAY_USED (0), // 1 available only for MEMORY_DDR3
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4)
) oserdes_i (
.OFB (dout_dly),
.OQ (dout_iob),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TFB (tout_dly),
.TQ (tout_iob),
.CLK (clk),
.CLKDIV (clk_div),
.D1 (din[0]),
.D2 (din[1]),
.D3 (din[2]),
.D4 (din[3]),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (rst),
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T3 (tin[2]),
.T4 (tin[3]),
.TCE (1'b1),
// not in OSERDES2E:
.WC (1'b0),
.OCBEXTEND (),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.ODV (1'b0)
);
`endif
endmodule