Cloned code from NC353 camera to be updated for NC393, current ISE and VDT....

Cloned code from NC353 camera to be updated for NC393, current ISE and VDT. Initial bitfile is operation.

.gitignore

+unisims
+vivado_*
+syntax_*
+simulation/*
+simulation_data/*
+quartus_logs/ *
+www/*
+constraints/*
+ise_*
+attic/*
+hardware_tests/*
+IVERILOG_INCLUDE.v
+*DEBUG_VDT*
+*.kate-swp
+*.old
+*.new
+*.bad
+*.pyc
+*.pickle
+*.tmp
+debug/*
+html/*
+man/*
+.project
+.pydevproject
+#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
+workingSet.psf
+*.fst
+cocotb/Makefile
+cocotb/sim_build
+cocotb/results.xml
+*.directory
+/html.tar.gz

.settings/com.elphel.vdt.FPGA_project.prefs

+FPGA_project_@_ImplementationTopFile=x359.v
+FPGA_project_@_SimulationTopFile=x359.tf
+FPGA_project_@_SimulationTopModule=testbench359
+FPGA_project_@_part=xc3s1200eft256-4
+com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->
+com.elphel.store.version.FPGA_project=1.0
+eclipse.preferences.version=1

.settings/com.elphel.vdt.prefs

+com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
+com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
+eclipse.preferences.version=1

Makefile

+include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+OWN = -o root -g root
+
+DOCUMENTROOT = $(prefix)/usr/html
+TESTSCRIPTS = $(DOCUMENTROOT)/359
+INCLUDES =     $(prefix)/usr/html/includes
+INSTDOCS =  0644
+
+PHPSCRIPTS= test_scripts/10359_controls.html \
+	    test_scripts/10359_mem_test.php \
+	    test_scripts/10359_modes.php \
+            test_scripts/phases_adjust.php \
+            test_scripts/reg_read.php \
+            test_scripts/reg_write.php \
+            test_scripts/sensors_init.php \
+
+all:
+install:
+	$(INSTALL) $(OWN) -d $(DOCUMENTROOT)
+	$(INSTALL) $(OWN) -d $(TESTSCRIPTS)
+#install files
+	$(INSTALL) $(OWN) -m $(INSTDOCS) $(PHPSCRIPTS)  $(TESTSCRIPTS)

channel_rd.v

+/*
+*! -----------------------------------------------------------------------------**
+*! FILE NAME  : channel_rd.v
+*! DESCRIPTION: channel for read from sdram
+*! Copyright (C) 2008 Elphel, Inc.
+*! -----------------------------------------------------------------------------**
+*!  This program is free software: you can redistribute it and/or modify
+*!  it under the terms of the GNU General Public License as published by
+*!  the Free Software Foundation, either version 3 of the License, or
+*!  (at your option) any later version.
+*!
+*!  This program is distributed in the hope that it will be useful,
+*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*!  GNU General Public License for more details.
+*!
+*!  You should have received a copy of the GNU General Public License
+*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*! -----------------------------------------------------------------------------**
+*!
+*! $Log: channel_rd.v,v $
+*! Revision 1.4  2010/05/14 18:48:35  dzhimiev
+*! 1. added hacts shifts for buffered channels
+*! 2. set fixed SDRAM spaces
+*!
+*! Revision 1.1  2009/06/11 17:39:00  dzhimiev
+*! new initial version
+*! 1. simulation and board test availability
+*!
+*! Revision 1.1  2008/12/08 09:09:03  dzhimiev
+*! 0. based on channel0.v (theora)
+*! 1. set up of the data path for the transform
+*! 2. 2 read and 2 write channels
+*! 3. in snapshot mode - 3 frames output sequence -
+*!   1st - direct
+*!   2nd - stored 'direct' from the 1st buffer
+*!   3rd - stored '1st buffer' from the 2nd buffer
+*!
+*/
+`timescale 1 ns / 1 ps
+
+module channel_rd   (
+	clk,	 // SDRAM clock (negedge)
+	enrq,	    // enable channel requests (does not reset if 0)
+   fsa,      // [11:0] frame start address (12 MSBs of SDRAM row address)
+   // Using the same values for channels 0..2
+	init,     // resets channel
+	x_max,
+	x_shift,
+	nx_max,
+	y_max,
+	y_shift,
+	ny_max,
+	fill_order,
+	// arbiter interface
+	start,
+	start2,
+	rq,       // request - want at least one access
+	rq_urgent,// need 3 or 4 accesses
+	sddi,     //[31:0]
+	rq_busy,
+	//SDRAM controller inteface (mcontr_line_rd)
+	predrun,
+	sa,       //[16:0]
+	len,      // access length
+	// external interface (compressor)
+	obre,     // output read enable, advance address
+	ch1a,
+	obdat,    // [15:0] output dtata
+	next_line, // advance to the next scan line (and next block RAM page if needed)
+	ao
+);
+						 
+  input         clk;
+  input         enrq;
+  input  [11:0] fsa;
+  input         init;
+  input  [ 11:0] ch1a;
+
+  input         start;
+  input         start2;
+  input         rq_busy;
+  output        rq;
+  output        rq_urgent;
+
+  input [7:0]   x_max;
+  input [7:0]   x_shift;
+  input [7:0]   nx_max;
+  input [13:0]   y_max;
+  input [7:0]   y_shift;
+  input [7:0]   ny_max;
+  input fill_order;
+
+  input  [31:0] sddi;     // data from SDRAM
+  input         predrun;
+  output [21:0] sa;
+  output  [4:0] len;
+  input        obre;      // output read enable
+  output[15:0] obdat;     // [15:0] output dtata
+  input        next_line;
+	output [10:0] ao;
+
+  wire         predrun;
+
+	reg         we;
+   reg         done;
+	reg	[10:0]	a=0;
+
+	reg   [2:0] rq_cnt=0;
+   wire        init0;
+   reg         init_pclk; 
+   wire        page_used0;
+   reg         page_used;
+	reg         rq;
+   reg         rq_urgent;
+   reg   [1:0] obpage;
+   reg   [7:0] obaddr;
+   wire        next_opage;
+   reg         cs,cs0;
+
+   reg [21:0] sa=0; 
+   reg   [7:0] obre_cnt=0;
+   reg   [4:0] len;
+
+//	parameter x_max=7;
+//	parameter x_shift=8;
+//	parameter nx_max=17;
+//	parameter y_max=4;
+//	parameter y_shift=4;
+//	parameter ny_max=9;
+
+	reg [6:0]  x=0, nx=0;
+	reg [12:0] y=0, ny=0;
+	reg [7:0] ny_cnt=0;
+	reg [7:0] nx_cnt=0;
+	reg [1:0] bank=0;
+
+   assign      next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
+
+	always @ (negedge clk) init_pclk <= init;
+
+	always @ (negedge clk) page_used <= !init_pclk && next_opage;
+  
+  always @ (negedge clk) begin
+    if      (init_pclk | next_opage)  obre_cnt[7:0] <= 0;
+    else if (obre)                    obre_cnt[7:0] <= obre_cnt[7:0] + 1;
+  end
+
+  //wire switch_order=0;
+
+  always @ (negedge clk) begin
+  
+   if      (init)              rq_cnt <= 0;
+   else if (start2) 
+		if (rq_busy)             rq_cnt <= rq_cnt + 1;
+		else                     rq_cnt <= rq_cnt;
+	else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;  
+  
+   if (init) begin
+	  sa[21:0]<= {fsa[11:0],10'b0};
+     nx <= 0;
+     nx_cnt <= 0;
+     ny <= 0;
+     ny_cnt <= 0; 
+     {y[11:0],bank[1:0]} <= 0;
+   end
+   else if (start) 
+		begin
+		
+//				if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
+//					{y[11:0],bank[1:0]} <= 0;
+//					if (nx_cnt==nx_max) begin
+//						nx <= 0;
+//						nx_cnt <= 0;
+//					end   							
+//					else begin
+//					  nx <= nx + x_shift;
+//					  nx_cnt <= nx_cnt + 1;
+//					end  
+//				end	
+//				else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
+
+			if (nx_cnt==nx_max) begin
+				nx <= 0;
+				nx_cnt <= 0;
+				if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
+				else                                  {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;	
+			end   							
+			else begin
+				nx <= nx + x_shift;
+				nx_cnt <= nx_cnt + 1;
+			end
+				
+
+			//sa[21:10]<= ny[11:0] + y[11:0];
+			sa[21] <= sa[21];
+			//sa[20:10]<= ny[10:0] + y[10:0];
+			sa[20:10]<= {sa[20],y[9:0]};
+			sa[9:2]  <= {1'b0,nx[6:0]};
+			sa[1:0]  <= bank[1:0];
+		end
+   len[4:0] <= x_max; 
+
+   rq        <= enrq & (start2 | (rq & !start));
+   rq_urgent <= enrq & start2 & (rq_cnt==3);
+
+  end
+	
+	assign ao[10:0]=a[10:0];
+	
+	always @ (negedge clk) begin
+	  we <= predrun;
+	  done <= we & !predrun;
+
+	  if (init)        a[10:0] <= 11'b0;
+	  else if (we)     a[10:0] <= a[10:0] + 1;
+	  //if (init)        a[9:0] <= 10'b0;
+	  //else if (we)     a[9:0] <= a[9:0] + 1;    
+
+		 //if      (init) a[8:7] <= 2'h0;
+     //else if (done) a[8:7] <= a[8:7] + 1;
+	end	
+	
+	reg [11:10] ch1a_d=0;
+	
+	always @ (negedge clk) begin
+		ch1a_d[11:10] <= ch1a[11:10];
+	end
+	
+	wire [15:0] obdat_0;
+	RAMB16_S18_S36 i_buf_0 (
+		.DOA(obdat_0[15:0]),    // Port A 16-bit Data Output   - compressor side
+		.ADDRA(ch1a[9:0]),
+		.CLKA(!clk),          // Port A Clock
+		.DIA(16'b0),          // Port A 16-bit Data Input
+		.DIPA(2'b0),          // Port A 2-bit parity Input
+		.ENA(obre & !ch1a[11] & !ch1a[10]),           // Port A RAM Enable Input
+		.SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+		.WEA(1'b0),           // Port A Write Enable Input
+	
+		.ADDRB(a[8:0]),       // Port B 9-bit Address Input
+		.CLKB(!clk),         // Port B Clock
+		.DIB(sddi[31:0]),     // Port B 32-bit Data Input
+		.DIPB(4'b0),          // Port-B 4-bit parity Input
+		.ENB(we & !a[10] & !a[9]),             // PortB RAM Enable Input
+		.SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+		.WEB(1'b1)            // Port B Write Enable Input
+	);
+
+	wire [15:0] obdat_1;
+	RAMB16_S18_S36 i_buf_1 (
+		.DOA(obdat_1[15:0]),    // Port A 16-bit Data Output   - compressor side
+		.ADDRA(ch1a[9:0]),
+		.CLKA(!clk),          // Port A Clock
+		.DIA(16'b0),          // Port A 16-bit Data Input
+		.DIPA(2'b0),          // Port A 2-bit parity Input
+		.ENA(obre & !ch1a[11] & ch1a[10]),           // Port A RAM Enable Input
+		.SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+		.WEA(1'b0),           // Port A Write Enable Input
+	
+		.ADDRB(a[8:0]),       // Port B 9-bit Address Input
+		.CLKB(!clk),         // Port B Clock
+		.DIB(sddi[31:0]),     // Port B 32-bit Data Input
+		.DIPB(4'b0),          // Port-B 4-bit parity Input
+		.ENB(we & !a[10] & a[9]),             // PortB RAM Enable Input
+		.SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+		.WEB(1'b1)            // Port B Write Enable Input
+	);
+	
+	wire [15:0] obdat_2;
+	RAMB16_S18_S36 i_buf_2 (
+		.DOA(obdat_2[15:0]),    // Port A 16-bit Data Output   - compressor side
+		.ADDRA(ch1a[9:0]),
+		.CLKA(!clk),          // Port A Clock
+		.DIA(16'b0),          // Port A 16-bit Data Input
+		.DIPA(2'b0),          // Port A 2-bit parity Input
+		.ENA(obre & ch1a[11] & !ch1a[10]),           // Port A RAM Enable Input
+		.SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+		.WEA(1'b0),           // Port A Write Enable Input
+	
+		.ADDRB(a[8:0]),       // Port B 9-bit Address Input
+		.CLKB(!clk),         // Port B Clock
+		.DIB(sddi[31:0]),     // Port B 32-bit Data Input
+		.DIPB(4'b0),          // Port-B 4-bit parity Input
+		.ENB(we & a[10] & !a[9]),             // PortB RAM Enable Input
+		.SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+		.WEB(1'b1)            // Port B Write Enable Input
+	);
+
+	wire [15:0] obdat_3;
+	RAMB16_S18_S36 i_buf_3 (
+		.DOA(obdat_3[15:0]),    // Port A 16-bit Data Output   - compressor side
+		.ADDRA(ch1a[9:0]),
+		.CLKA(!clk),          // Port A Clock
+		.DIA(16'b0),          // Port A 16-bit Data Input
+		.DIPA(2'b0),          // Port A 2-bit parity Input
+		.ENA(obre & ch1a[11] & ch1a[10]),           // Port A RAM Enable Input
+		.SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+		.WEA(1'b0),           // Port A Write Enable Input
+	
+		.ADDRB(a[8:0]),       // Port B 9-bit Address Input
+		.CLKB(!clk),         // Port B Clock
+		.DIB(sddi[31:0]),     // Port B 32-bit Data Input
+		.DIPB(4'b0),          // Port-B 4-bit parity Input
+		.ENB(we & a[10] & a[9]),             // PortB RAM Enable Input
+		.SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+		.WEB(1'b1)            // Port B Write Enable Input
+	);	
+
+assign obdat=ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
+
+endmodule
+

channel_rd_short.v

+/*
+*! -----------------------------------------------------------------------------**
+*! FILE NAME  : channel_rd_short.v
+*! DESCRIPTION: channel for read from sdram
+*! Copyright (C) 2008 Elphel, Inc.
+*! -----------------------------------------------------------------------------**
+*!  This program is free software: you can redistribute it and/or modify
+*!  it under the terms of the GNU General Public License as published by
+*!  the Free Software Foundation, either version 3 of the License, or
+*!  (at your option) any later version.
+*!
+*!  This program is distributed in the hope that it will be useful,
+*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*!  GNU General Public License for more details.
+*!
+*!  You should have received a copy of the GNU General Public License
+*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*! -----------------------------------------------------------------------------**
+*!
+*! $Log: channel_rd_short.v,v $
+*! Revision 1.4  2010/05/14 18:48:35  dzhimiev
+*! 1. added hacts shifts for buffered channels
+*! 2. set fixed SDRAM spaces
+*!
+*/
+`timescale 1 ns / 1 ps
+
+module channel_rd_short   (
+	clk,	 // SDRAM clock (negedge)
+	enrq,	    // enable channel requests (does not reset if 0)
+   fsa,      // [11:0] frame start address (12 MSBs of SDRAM row address)
+   // Using the same values for channels 0..2
+	init,     // resets channel
+	x_max,
+	x_shift,
+	nx_max,
+	y_max,
+	y_shift,
+	ny_max,
+	fill_order,
+	// arbiter interface
+	start,
+	start2,
+	rq,       // request - want at least one access
+	rq_urgent,// need 3 or 4 accesses
+	sddi,     //[31:0]
+	rq_busy,
+	//SDRAM controller inteface (mcontr_line_rd)
+	predrun,
+	sa,       //[16:0]
+	len,      // access length
+	// external interface (compressor)
+	obre,     // output read enable, advance address
+	ch1a,
+	obdat,    // [15:0] output dtata
+	next_line, // advance to the next scan line (and next block RAM page if needed)
+	ao
+);
+						 
+  input         clk;
+  input         enrq;
+  input  [11:0] fsa;
+  input         init;
+  input  [ 11:0] ch1a;
+
+  input         start;
+  input         start2;
+  input         rq_busy;
+  output        rq;
+  output        rq_urgent;
+
+  input [7:0]   x_max;
+  input [7:0]   x_shift;
+  input [7:0]   nx_max;
+  input [13:0]   y_max;
+  input [7:0]   y_shift;
+  input [7:0]   ny_max;
+  input fill_order;
+
+  input  [31:0] sddi;     // data from SDRAM
+  input         predrun;
+  output [21:0] sa;
+  output  [4:0] len;
+  input        obre;      // output read enable
+  output[15:0] obdat;     // [15:0] output dtata
+  input        next_line;
+	output [10:0] ao;
+
+  wire         predrun;
+
+	reg         we;
+   reg         done;
+	reg	[10:0]	a=0;
+
+	reg   [2:0] rq_cnt=0;
+   wire        init0;
+   reg         init_pclk; 
+   wire        page_used0;
+   reg         page_used;
+	reg         rq;
+   reg         rq_urgent;
+   reg   [1:0] obpage;
+   reg   [7:0] obaddr;
+   wire        next_opage;
+   reg         cs,cs0;
+
+   reg [21:0] sa=0; 
+   reg   [7:0] obre_cnt=0;
+   reg   [4:0] len;
+
+//	parameter x_max=7;
+//	parameter x_shift=8;
+//	parameter nx_max=17;
+//	parameter y_max=4;
+//	parameter y_shift=4;
+//	parameter ny_max=9;
+
+	reg [6:0]  x=0, nx=0;
+	reg [12:0] y=0, ny=0;
+	reg [7:0] ny_cnt=0;
+	reg [7:0] nx_cnt=0;
+	reg [1:0] bank=0;
+
+   assign      next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
+
+	always @ (negedge clk) init_pclk <= init;
+
+	always @ (negedge clk) page_used <= !init_pclk && next_opage;
+  
+  always @ (negedge clk) begin
+    if      (init_pclk | next_opage)  obre_cnt[7:0] <= 0;
+    else if (obre)                    obre_cnt[7:0] <= obre_cnt[7:0] + 1;
+  end
+
+  //wire switch_order=0;
+
+  always @ (negedge clk) begin
+  
+   if      (init)              rq_cnt <= 0;
+   else if (start2) 
+		if (rq_busy)             rq_cnt <= rq_cnt + 1;
+		else                     rq_cnt <= rq_cnt;
+	else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;  
+  
+   if (init) begin
+	  sa[21:0]<= {fsa[11:0],10'b0};
+     nx <= 0;
+     nx_cnt <= 0;
+     ny <= 0;
+     ny_cnt <= 0; 
+     {y[11:0],bank[1:0]} <= 0;
+   end
+   else if (start) 
+		begin
+		
+//				if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
+//					{y[11:0],bank[1:0]} <= 0;
+//					if (nx_cnt==nx_max) begin
+//						nx <= 0;
+//						nx_cnt <= 0;
+//					end   							
+//					else begin
+//					  nx <= nx + x_shift;
+//					  nx_cnt <= nx_cnt + 1;
+//					end  
+//				end	
+//				else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
+
+			if (nx_cnt==nx_max) begin
+				nx <= 0;
+				nx_cnt <= 0;
+				if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
+				else                                  {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;	
+			end   							
+			else begin
+				nx <= nx + x_shift;
+				nx_cnt <= nx_cnt + 1;
+			end
+				
+
+			//sa[21:10]<= ny[11:0] + y[11:0];
+			sa[21] <= sa[21];
+			//sa[20:10]<= ny[10:0] + y[10:0];
+			sa[20:10]<= {sa[20],y[9:0]};
+			sa[9:2]  <= {1'b0,nx[6:0]};
+			sa[1:0]  <= bank[1:0];
+		end
+   len[4:0] <= x_max; 
+
+   rq        <= enrq & (start2 | (rq & !start));
+   rq_urgent <= enrq & start2 & (rq_cnt==3);
+
+  end
+	
+	assign ao[10:0]=a[10:0];
+	
+	always @ (negedge clk) begin
+	  we <= predrun;
+	  done <= we & !predrun;
+
+	  if (init)        a[10:0] <= 11'b0;
+	  else if (we)     a[10:0] <= a[10:0] + 1;
+	  //if (init)        a[9:0] <= 10'b0;
+	  //else if (we)     a[9:0] <= a[9:0] + 1;    
+
+		 //if      (init) a[8:7] <= 2'h0;
+     //else if (done) a[8:7] <= a[8:7] + 1;
+	end	
+	
+	reg [11:10] ch1a_d=0;
+	
+	always @ (negedge clk) begin
+		ch1a_d[11:10] <= ch1a[11:10];
+	end
+	
+	wire [15:0] obdat_0;
+	RAMB16_S18_S36 i_buf_0 (
+		.DOA(obdat_0[15:0]),    // Port A 16-bit Data Output   - compressor side
+		.ADDRA(ch1a[9:0]),
+		.CLKA(!clk),          // Port A Clock
+		.DIA(16'b0),          // Port A 16-bit Data Input
+		.DIPA(2'b0),          // Port A 2-bit parity Input
+		.ENA(1),           // Port A RAM Enable Input
+		.SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+		.WEA(1'b0),           // Port A Write Enable Input
+	
+		.ADDRB(a[8:0]),       // Port B 9-bit Address Input
+		.CLKB(!clk),         // Port B Clock
+		.DIB(sddi[31:0]),     // Port B 32-bit Data Input
+		.DIPB(4'b0),          // Port-B 4-bit parity Input
+		.ENB(1),             // PortB RAM Enable Input
+		.SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+		.WEB(we)            // Port B Write Enable Input
+	);
+
+	wire [15:0] obdat_1;	
+	wire [15:0] obdat_2;
+	wire [15:0] obdat_3;
+
+assign obdat=obdat_0;//ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
+
+endmodule

channel_wr.v

+/*
+*! -----------------------------------------------------------------------------**
+*! FILE NAME  : channel_wr.v
+*! DESCRIPTION: channel for write to sdram
+*! Copyright (C) 2008 Elphel, Inc.
+*! -----------------------------------------------------------------------------**
+*!  This program is free software: you can redistribute it and/or modify
+*!  it under the terms of the GNU General Public License as published by
+*!  the Free Software Foundation, either version 3 of the License, or
+*!  (at your option) any later version.
+*!
+*!  This program is distributed in the hope that it will be useful,
+*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*!  GNU General Public License for more details.
+*!
+*!  You should have received a copy of the GNU General Public License
+*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*! -----------------------------------------------------------------------------**
+*!
+*! $Log: channel_wr.v,v $
+*! Revision 1.5  2010/05/14 18:48:35  dzhimiev
+*! 1. added hacts shifts for buffered channels
+*! 2. set fixed SDRAM spaces
+*!
+*! Revision 1.1  2009/06/11 17:39:00  dzhimiev
+*! new initial version
+*! 1. simulation and board test availability
+*!
+*! Revision 1.1  2008/12/08 09:09:35  dzhimiev
+*! 0. based on channel0.v (theora)
+*! 1. set up of the data path for the transform
+*! 2. 2 read and 2 write channels
+*! 3. in snapshot mode - 3 frames output sequence -
+*!   1st - direct
+*!   2nd - stored 'direct' from the 1st buffer
+*!   3rd - stored '1st buffer' from the 2nd buffer
+*!
+*/
+
+`timescale 1 ns / 1 ps
+
+module channel_wr(
+  clk,	  // SDRAM clock (negedge)
+  enrq,	  // enable channel requests (does not reset if 0)
+  fsa,     // [11:0] frame start address (12 MSBs of SDRAM row address)
+// Using the same values for channels 0..2?
+  init,    // resets channel
+  x_max,
+  x_shift,
+  nx_max,
+  y_max,
+  y_shift,
+  ny_max,	
+  fill_order,
+// arbiter interface
+  start,
+  rq,       // request - want at least one access
+  rq_urgent,// need 3 or 4 accesses
+//SDRAM controller inteface (mcontr_line_wr)
+  sddo,     //[31:0]
+  predrun,
+  sa,       //[16:0]
+  len,      // access length
+// external interface (compressor)
+  ibwe,  // input data write enable, advance address
+  ch0a,
+  ibdat, // [15:0] input data (1 or 2 pixels)
+  next_line // advance to the next scan line (and next block RAM page if needed)
+);
+
+  input         clk;
+  input         enrq;
+  input  [11:0] fsa;
+  input         init;
+
+  input         start;
+  output        rq;
+  output        rq_urgent;
+
+  output [31:0] sddo;     //[31:0] - data to SDRAM
+  input         predrun;
+  output [21:0] sa;
+  output  [4:0] len;
+
+  input        ibwe;
+  input [10:0] ch0a;
+  input [15:0] ibdat;
+  input        next_line;
+	
+	input [7:0]   x_max;
+	input [7:0]   x_shift;
+	input [7:0]   nx_max;
+	input [13:0]   y_max;
+	input [7:0]   y_shift;
+	input [7:0]   ny_max;	
+	input         fill_order;
+  
+  wire         next_line;
+  wire         predrun;
+
+	reg         re;
+   reg         done;
+	reg	[9:0]	a;
+
+   reg   [4:0] full_pages_in_buffer;
+   wire        init0;
+   reg         init_pclk; 
+   wire        page_prepared0;
+   reg         page_prepared;
+
+   reg         rq=0;
+	 //wire         rq;
+   reg         rq_urgent;
+	
+   reg  [21:0] sa=0; 
+   reg   [7:0] ibwe_cnt=0;
+   reg   [4:0] len;
+
+   wire  [10:0] ch0a;
+	
+//	parameter x_max=7;
+//	parameter x_shift=8;
+//	parameter nx_max=17;
+//	parameter y_max=4;
+//	parameter y_shift=4;
+//	parameter ny_max=9;
+
+	reg [ 6:0] x=0, nx=0;
+	reg [12:0] y=0, ny=0;
+	reg [ 7:0] ny_cnt=0;
+	reg [ 7:0] nx_cnt=0;
+	reg [1:0] bank=0;
+	wire next_ipage;
+	
+  always @ (posedge clk) 
+	if (init) init_pclk <= 1;
+	else      init_pclk <= 0;
+
+  always @ (negedge clk) 
+		if (!init_pclk & next_ipage) page_prepared <= 1;
+		else                         page_prepared <= 0;
+  
+  always @ (posedge clk) begin
+    if      (init_pclk | next_ipage)  ibwe_cnt[7:0] <= 0;
+    else if (ibwe)                    ibwe_cnt[7:0] <= ibwe_cnt[7:0] + 1;
+  end
+
+  //assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'hff) & ibwe));
+	//assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'h7f) & ibwe));
+	assign next_ipage=0;//((ibwe_cnt[5:0]==63) & ibwe);
+
+  always @ (negedge clk) begin
+   if      (init)       
+		full_pages_in_buffer <= 5'h0;
+	else if (next_line & start) 
+		full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0];
+   else if (next_line)  
+		full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] +1;
+   else if (start)  
+	   if (full_pages_in_buffer[4:0]!=0) 
+			full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] -1;
+ 
+   if (init) begin
+     sa[21:0]<= {fsa[11:0],10'b0};
+     nx <= 0;
+     nx_cnt <= 0;
+     ny <= 0;
+     ny_cnt <= 0; 
+	  {y[11:0],bank[1:0]} <= 0;
+   end
+	else if (start) 
+		begin
+		
+//				if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
+//					{y[11:0],bank[1:0]} <= 0;
+//					if (nx_cnt==nx_max) begin
+//						nx <= 0;
+//						nx_cnt <= 0;
+//					end   							
+//					else begin
+//					  nx <= nx + x_shift;
+//					  nx_cnt <= nx_cnt + 1;
+//					end  
+//				end	
+//				else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
+
+			if (nx_cnt==nx_max) begin
+				nx <= 0;
+				nx_cnt <= 0;
+				if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
+				else                                  {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;	
+			end   							
+			else begin
+				nx <= nx + x_shift;
+				nx_cnt <= nx_cnt + 1;
+			end
+				
+
+			//sa[21:10]<= ny[11:0] + y[11:0];
+			sa[21] <= sa[21];
+			//sa[20:10]<= ny[10:0] + y[10:0];
+			sa[20:10]<= {sa[20],y[9:0]};
+			sa[9:2]  <= {1'b0,nx[6:0]};
+			sa[1:0]  <= bank[1:0];
+			
+		end
+   len[4:0] <= x_max; 
+	 
+	 if (!start)
+		rq <= ((next_line|rq) & enrq & !init);//|(rq & !start);
+	 else
+	//	rq <= 0;
+		rq <= enrq & (full_pages_in_buffer[4:0] != 1);
+	 
+   rq_urgent <= enrq & (full_pages_in_buffer[3] | (full_pages_in_buffer[3:0]==7)); //>=3
+
+  end
+
+//assign rq=next_line&enrq&!init;
+
+	always @ (negedge clk) begin
+	  re <= predrun;
+	  done <= re & !predrun;
+
+	  if (init) a[9:0] <= 10'b0;
+	  else if (re)     a[9:0] <= a[9:0] + 1;
+     //if      (init) a[8:7] <= 2'h0;
+     //else if (done) a[8:7] <= a[8:7] + 1;
+	end
+
+   reg a_d=0;
+
+	always @ (negedge clk) begin
+	  a_d <= a[9];
+	end
+	
+	wire [31:0] sddo_0;	
+    RAMB16_S18_S36 i_buf_0 (
+      .DOA(),               // Port A 16-bit Data Output   - compressor side
+      .DOPA(),              // Port A 2-bit Parity Output
+		.ADDRA(ch0a[9:0]),
+      .CLKA(clk),          // Port A Clock
+      .DIA(ibdat[15:0]),    // Port A 16-bit Data Input
+      .DIPA(2'b0),          // Port A 2-bit parity Input
+      .ENA(ibwe & !ch0a[10]),           // Port A RAM Enable Input
+      .SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+      .WEA(1'b1),           // Port A Write Enable Input
+
+      .DOB(sddo_0[31:0]),     // Port B 32-bit Data Output  - SDRAM side
+      .DOPB(),              // Port B 4-bit Parity Output
+      .ADDRB(a[8:0]),       // Port B 9-bit Address Input
+      .CLKB(!clk),          // Port B Clock
+      .DIB(32'h0),          // Port B 32-bit Data Input
+      .DIPB(4'b0),          // Port-B 4-bit parity Input
+      .ENB(re & !a[9]),             // PortB RAM Enable Input
+      .SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+      .WEB(1'b0)            // Port B Write Enable Input
+   );
+
+	wire [31:0] sddo_1;
+    RAMB16_S18_S36 i_buf_1 (
+      .DOA(),               // Port A 16-bit Data Output   - compressor side
+      .DOPA(),              // Port A 2-bit Parity Output
+		.ADDRA(ch0a[9:0]),
+      .CLKA(clk),          // Port A Clock
+      .DIA(ibdat[15:0]),    // Port A 16-bit Data Input
+      .DIPA(2'b0),          // Port A 2-bit parity Input
+      .ENA(ibwe & ch0a[10]),           // Port A RAM Enable Input
+      .SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+      .WEA(1'b1),           // Port A Write Enable Input
+
+      .DOB(sddo_1[31:0]),     // Port B 32-bit Data Output  - SDRAM side
+      .DOPB(),              // Port B 4-bit Parity Output
+      .ADDRB(a[8:0]),       // Port B 9-bit Address Input
+      .CLKB(!clk),          // Port B Clock
+      .DIB(32'h0),          // Port B 32-bit Data Input
+      .DIPB(4'b0),          // Port-B 4-bit parity Input
+      .ENB(re & a[9]),             // PortB RAM Enable Input
+      .SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+      .WEB(1'b0)            // Port B Write Enable Input
+   );
+
+assign sddo[31:0]=a_d?sddo_1[31:0]:sddo_0[31:0];
+
+endmodule
+

dcm_phase.v

+/*
+** -----------------------------------------------------------------------------**
+** dcm_phase.v
+**
+** Copyright (C) 2002 Elphel, Inc
+**
+** -----------------------------------------------------------------------------**
+**  This file is part of X353
+**  X333 is free software - hardware description language (HDL) code.
+** 
+**  This program is free software: you can redistribute it and/or modify
+**  it under the terms of the GNU General Public License as published by
+**  the Free Software Foundation, either version 3 of the License, or
+**  (at your option) any later version.
+**
+**  This program is distributed in the hope that it will be useful,
+**  but WITHOUT ANY WARRANTY; without even the implied warranty of
+**  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+**  GNU General Public License for more details.
+**
+**  You should have received a copy of the GNU General Public License
+**  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+** -----------------------------------------------------------------------------**
+**
+** $Log: dcm_phase.v,v $
+** Revision 1.2  2010/05/14 18:48:35  dzhimiev
+** 1. added hacts shifts for buffered channels
+** 2. set fixed SDRAM spaces
+**
+*/
+
+`timescale 1 ns / 1 ps
+
+module dcm_phase (
+	cclk,   	   // command clock for shift
+	wcmd,   	   // decoded address - enables wclk
+   cmd,    	   // CPU write data [3:0]
+	        	   //  0 - nop, just reset status data
+	        	   //  1 - increase phase shift
+	        	   //  2 - decrease phase shift
+	        	   //  3 - reset phase shift to default (preprogrammed in FPGA configuration)
+	        	   //  4 - incr pahse90
+	        	   //  8 - decrease phase90											
+	        	   //  c - reset phase90
+	iclk,   	   // DCM input clock
+	clk_fb,     // feed back clock
+	clk0,       // global output clock, phase 0
+	clk90,      // global output clock, phase 90
+	clk180,     // global output clock, phase 180							
+	clk270,     // global output clock, phase 270
+	
+	dcm_phase,   // current DCM phase (small steps)
+	dcm_phase_90,// current DCM quarter (90 degrees steps)
+	dcm_done,    // DCM command done
+	dcm_status,  // DCM status (bit 1 - dcm clkin stopped)
+	dcm_locked   // DCM "Locked" pin
+);
+							
+  parameter NO_SHIFT90=0; //wanted to choose between clk0 BUFGs
+							
+	input         cclk;
+   input         wcmd;
+   input  [ 3:0] cmd;
+   input         iclk;
+   input         clk_fb;	
+	
+	output clk0;
+	output clk90;
+	output clk180;
+	output clk270;	
+	
+   output [8:0]  dcm_phase;
+   output [1:0]  dcm_phase_90;
+	output dcm_done;
+	output [7:0] dcm_status;
+	output dcm_locked;
+
+  reg       dcm_rst=0;
+  wire      dcm_rst_cmd;
+  reg [2:0] dcm_drst=0;  
+  reg [2:0] dcm_reset_done=0;
+  wire dcm_done_dcm;
+  
+  reg dcm_en=0;
+  reg dcm_incdec=0;
+  reg [8:0] phase_reg=0;
+  reg [1:0] phase90_reg=0;
+  
+  reg dcm_done=0;
+  
+  assign dcm_phase[8:0] = phase_reg[8:0];
+  assign dcm_phase_90[1:0] = NO_SHIFT90? 0 : phase90_reg[1:0];
+
+  FD i_dcm_rst_cmd(.Q(dcm_rst_cmd), .D((wcmd && (cmd[1:0] == 2'b11)) || (dcm_rst_cmd && !dcm_drst[2])), .C(cclk));
+  
+  // shift commands are synchronous to the command clock
+  always @ (posedge cclk) begin
+    dcm_reset_done[2:0] <= {dcm_reset_done[1] & ~dcm_reset_done[0], dcm_reset_done[0], dcm_rst}; // sync to cclkl end of dcm reset
+    dcm_en     <= wcmd && (cmd[1]!=cmd[0]);
+    dcm_incdec <= wcmd && cmd[0]; 
+
+    if (wcmd) begin
+      if      (cmd[0] && cmd[1]) phase_reg[8:0] <= 9'h0;
+      else if (cmd[0])           phase_reg[8:0] <= phase_reg[8:0] +1;
+      else if (cmd[1])           phase_reg[8:0] <= phase_reg[8:0] -1;
+    end	 
+	 
+    if (wcmd) begin
+      if      (cmd[2] && cmd[3]) phase90_reg[1:0] <= 2'h0;
+      else if (cmd[2])           phase90_reg[1:0] <= phase90_reg[1:0] +1;
+      else if (cmd[3])           phase90_reg[1:0] <= phase90_reg[1:0] -1;
+    end
+  end
+
+  // dcm_rst is synchronous to incoming clock
+  always @ (posedge iclk) begin
+    dcm_drst[2:0] <= dcm_drst[2]? 3'b0:{dcm_drst[1], dcm_drst[0], dcm_rst_cmd};
+    dcm_rst    <= dcm_drst[0]  || dcm_drst[1]   || dcm_drst[2] ;
+  end
+// make dcm_done behave as dcm_ready
+  always @ (posedge cclk)
+     if (wcmd && |cmd[2:0])                      dcm_done <= 0;
+     else if (dcm_done_dcm || dcm_reset_done[2]) dcm_done <= 1;
+
+/// DCM to compensate sensor delays. Adjustment for data phase - both fine and 90-degrees, hact/vact - 90-degree steps relative to data
+
+  DCM_SP #(
+      .CLKIN_DIVIDE_BY_2("FALSE"),     // TRUE/FALSE to enable CLKIN divide by two feature
+      .CLKIN_PERIOD(10.0),            //96Hz
+      .CLKOUT_PHASE_SHIFT("VARIABLE"),// Specify phase shift of NONE, FIXED or VARIABLE
+      .CLK_FEEDBACK("1X"),            // Specify clock feedback of NONE, 1X or 2X
+      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                            //   an integer from 0 to 15
+      .DLL_FREQUENCY_MODE("LOW"),     // HIGH or LOW frequency mode for DLL
+      .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
+      .PHASE_SHIFT(0),                // Amount of fixed phase shift from -255 to 255
+      .STARTUP_WAIT("FALSE")          // Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   ) i_dcm_sensor(
+    .CLKIN    (iclk),
+    .CLKFB    (clk_fb),
+    .RST      (dcm_rst),
+    .PSEN     (dcm_en),
+    .PSINCDEC (dcm_incdec),
+    .PSCLK    (cclk),
+    .DSSEN    (1'b0),
+    .CLK0     (pre_clk0),
+    .CLK90    (pre_clk90),   // adjust tap
+    .CLK180   (pre_clk180), // adjust tap
+    .CLK270   (pre_clk270),
+    .CLKDV    (),
+    .CLK2X    (),
+    .CLK2X180 (),
+    .CLKFX    (),
+    .CLKFX180 (),
+    .STATUS   (dcm_status[7:0]),
+    .LOCKED   (dcm_locked),
+    .PSDONE   (dcm_done_dcm)
+);
+
+	wire pre_clk = phase90_reg[1]? (phase90_reg[0]? pre_clk270:pre_clk180) : (phase90_reg[0]? pre_clk90:pre_clk0);
+
+	BUFG i_clk0a   (.I(NO_SHIFT90?pre_clk0:pre_clk),   .O(clk0));
+//	BUFG i_clk0b   (.I(pre_clk),   .O(clk0));
+		
+	BUFG i_clk90  (.I(pre_clk90),  .O(clk90));
+	BUFG i_clk180 (.I(pre_clk180), .O(clk180));
+	BUFG i_clk270 (.I(pre_clk270), .O(clk270));
+
+endmodule

ddr_parameters.v

+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
+    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.4; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.4; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.5; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`define sg75Z                       //              Timing Parameters for -75Z (CL = 2)
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.5; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+//    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRC              =  63.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    20.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`endif
+`endif
+`endif
+
+    // Size Parameters based on Part Width
+
+`ifdef x4
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used
+`else
+`ifdef x8
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
+`else
+`define x16
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
+`endif
+`endif
+
+    parameter full_mem_bits    = 25;//2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+//    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 25;//14;                   // Set this parameter to control how many unique addresses are used
+
+    parameter no_halt          =       1; // If set to 1, the model won't halt on command sequence/major errors
+    parameter Debug            =       1; // Turn on debug message

glbl.v

+// $Header: /cvsroot/elphel/elphel353-8.0/fpga/x359/glbl.v,v 1.4 2010/05/14 18:48:35 dzhimiev Exp $
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+    wire GSR;
+    wire GTS;
+    wire PRLD;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule

macros353.v

+/*
+** -----------------------------------------------------------------------------**
+** macros353.v
+**
+** I/O pads related circuitry
+**
+** Copyright (C) 2002 Elphel, Inc
+**
+** -----------------------------------------------------------------------------**
+**  This file is part of X353
+**  X353 is free software - hardware description language (HDL) code.
+** 
+**  This program is free software: you can redistribute it and/or modify
+**  it under the terms of the GNU General Public License as published by
+**  the Free Software Foundation, either version 3 of the License, or
+**  (at your option) any later version.
+**
+**  This program is distributed in the hope that it will be useful,
+**  but WITHOUT ANY WARRANTY; without even the implied warranty of
+**  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+**  GNU General Public License for more details.
+**
+**  You should have received a copy of the GNU General Public License
+**  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+** -----------------------------------------------------------------------------**
+**
+*/
+// just make more convenient A[3:0] instead of 4 one-bit inputs
+`timescale 1 ns / 1 ps
+
+module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
+parameter DATA_WIDTH=16;
+parameter DATA_DEPTH=4;
+parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    input	 [DATA_WIDTH-1:0]	D;
+    input				WE,clk;
+    input	 [DATA_DEPTH-1:0]	AW;
+    input	 [DATA_DEPTH-1:0]	AR;
+    output [DATA_WIDTH-1:0]	QW;
+    output [DATA_WIDTH-1:0]	QR;
+    reg	 [DATA_WIDTH-1:0]	ram [0:DATA_2DEPTH];
+    always @ (posedge clk) if (WE) ram[AW] <= D; 
+    assign	QW= ram[AW];
+    assign	QR= ram[AR];
+endmodule
+
+module MSRL16_1 (Q, A, CLK, D);
+    output Q;
+    input  [3:0] A;
+    input  CLK, D;
+    SRL16_1 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
+endmodule
+
+/*
+module MSRLC16E_1 (Q, Q15, A, CLK, CE, D);
+    output Q,Q15;
+    input  [3:0] A;
+    input  CLK,CE, D;
+    SRLC16E_1 i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
+endmodule
+*/
+
+module MSRL16 (Q, A, CLK, D);
+    output Q;
+    input  [3:0] A;
+    input  CLK, D;
+    SRL16 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
+endmodule
+
+module MSRLC16E (Q, Q15, A, CLK, CE, D);
+    output Q,Q15;
+    input  [3:0] A;
+    input  CLK,CE, D;
+    SRLC16E i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
+endmodule
+
+module MSRLC16E_1 (Q, Q15, A, CLK, CE, D);
+    output Q,Q15;
+    input  [3:0] A;
+    input  CLK,CE, D;
+    SRLC16E_1 i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
+endmodule
+/*
+module RAM32X12D_1 (DPO,SPO,A,D,DPRA,WCLK,WE);
+       input   [4:0] A;    // Port A address[4:0] input bit
+       input   [4:0] DPRA; // Port B address[4:0] input bit
+       input  [11:0] D;    // Port A data input [11:0]
+       input         WCLK; // Port A clock (negedge write)
+       input         WE;   // Port A write enable input
+       output [11:0] DPO;  // Port A 12-bit data output
+       output [11:0] SPO;  // Port B 12-bit data output
+   RAM32X1D_1 i0 (.DPO(DPO[ 0]),.SPO(SPO[ 0]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 0]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i1 (.DPO(DPO[ 1]),.SPO(SPO[ 1]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 1]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i2 (.DPO(DPO[ 2]),.SPO(SPO[ 2]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 2]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i3 (.DPO(DPO[ 3]),.SPO(SPO[ 3]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 3]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i4 (.DPO(DPO[ 4]),.SPO(SPO[ 4]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 4]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i5 (.DPO(DPO[ 5]),.SPO(SPO[ 5]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 5]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i6 (.DPO(DPO[ 6]),.SPO(SPO[ 6]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 6]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i7 (.DPO(DPO[ 7]),.SPO(SPO[ 7]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 7]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i8 (.DPO(DPO[ 8]),.SPO(SPO[ 8]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 8]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i9 (.DPO(DPO[ 9]),.SPO(SPO[ 9]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 9]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i10(.DPO(DPO[10]),.SPO(SPO[10]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[10]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+   RAM32X1D_1 i11(.DPO(DPO[11]),.SPO(SPO[11]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[11]),
+                  .DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
+endmodule
+*/
+
+
+
+module RAM16XnnD (D,WE,CLK,AW,AR,QW,QR);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				WE,CLK;
+	input	 [ 3:0]	AW;
+	input	 [ 3:0]	AR;
+	output [w-1:0]	QW;
+	output [w-1:0]	QR;
+ 	reg	 [w-1:0]	ram [0:15];
+	always @ (posedge CLK) if (WE) ram[AW] <= D; 
+	assign	QW= ram[AW];
+	assign	QR= ram[AR];
+endmodule
+
+module RAM16XnnD_1 (D,WE,CLK,AW,AR,QW,QR);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				WE,CLK;
+	input	 [ 3:0]	AW;
+	input	 [ 3:0]	AR;
+	output [w-1:0]	QW;
+	output [w-1:0]	QR;
+ 	reg	 [w-1:0]	ram [0:15];
+	always @ (negedge CLK) if (WE) ram[AW] <= D; 
+	assign	QW= ram[AW];
+	assign	QR= ram[AR];
+endmodule
+
+module RAM32XnnD   (D,WE,CLK,AW,AR,QW,QR);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				WE,CLK;
+	input	 [ 4:0]	AW;
+	input	 [ 4:0]	AR;
+	output [w-1:0]	QW;
+	output [w-1:0]	QR;
+ 	reg	 [w-1:0]	ram [0:31];
+	always @ (posedge CLK) if (WE) ram[AW] <= D; 
+	assign	QW= ram[AW];
+	assign	QR= ram[AR];
+endmodule
+
+module RAM32XnnD_1 (D,WE,CLK,AW,AR,QW,QR);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				WE,CLK;
+	input	 [ 4:0]	AW;
+	input	 [ 4:0]	AR;
+	output [w-1:0]	QW;
+	output [w-1:0]	QR;
+ 	reg	 [w-1:0]	ram [0:31];
+	always @ (negedge CLK) if (WE) ram[AW] <= D; 
+	assign	QW= ram[AW];
+	assign	QR= ram[AR];
+endmodule
+
+
+module SRPL	 (D,SDO,SDI,CLK,EN,LD);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				EN,CLK, LD, SDI;
+	output         SDO;
+ 	reg	 [w-1:0]	r;
+	always @ (posedge CLK)
+	  if      (LD) r <= D;
+	  else if (EN)	r <= {SDI,r[w-1:1]};
+	assign SDO=r[0];
+endmodule
+
+module SRPL_1	 (D,SDO,SDI,CLK,EN,LD);
+   parameter w=16;
+	input	 [w-1:0]	D;
+	input				EN,CLK, LD, SDI;
+	output         SDO;
+ 	reg	 [w-1:0]	r;
+	always @ (negedge CLK)
+	  if      (LD) r <= D;
+	  else if (EN)	r <= {SDI,r[w-1:1]};
+	assign SDO=r[0];
+endmodule