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Commit 1727b764 authored by Andrey Filippov's avatar Andrey Filippov
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Cloned code from NC353 camera to be updated for NC393, current ISE and VDT.... 

Cloned code from NC353 camera to be updated for NC393, current ISE and VDT. Initial bitfile is operation.
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.gitignore 0 → 100644
View file @ 1727b764
unisims
vivado_*
syntax_*
simulation/*
simulation_data/*
quartus_logs/ *
www/*
constraints/*
ise_*
attic/*
hardware_tests/*
IVERILOG_INCLUDE.v
*DEBUG_VDT*
*.kate-swp
*.old
*.new
*.bad
*.pyc
*.pickle
*.tmp
debug/*
html/*
man/*
.project
.pydevproject
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
workingSet.psf
*.fst
cocotb/Makefile
cocotb/sim_build
cocotb/results.xml
*.directory
/html.tar.gz
.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 1727b764
FPGA_project_@_ImplementationTopFile=x359.v
FPGA_project_@_SimulationTopFile=x359.tf
FPGA_project_@_SimulationTopModule=testbench359
FPGA_project_@_part=xc3s1200eft256-4
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 1727b764
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
Makefile 0 → 100644
View file @ 1727b764
include $(AXIS_TOP_DIR)/tools/build/Rules.axis
OWN = -o root -g root
DOCUMENTROOT = $(prefix)/usr/html
TESTSCRIPTS = $(DOCUMENTROOT)/359
INCLUDES = $(prefix)/usr/html/includes
INSTDOCS = 0644
PHPSCRIPTS= test_scripts/10359_controls.html \
test_scripts/10359_mem_test.php \
test_scripts/10359_modes.php \
test_scripts/phases_adjust.php \
test_scripts/reg_read.php \
test_scripts/reg_write.php \
test_scripts/sensors_init.php \
all:
install:
$(INSTALL) $(OWN) -d $(DOCUMENTROOT)
$(INSTALL) $(OWN) -d $(TESTSCRIPTS)
#install files
$(INSTALL) $(OWN) -m $(INSTDOCS) $(PHPSCRIPTS) $(TESTSCRIPTS)
channel_rd.v 0 → 100644
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_rd.v
*! DESCRIPTION: channel for read from sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_rd.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:09:03 dzhimiev
*! 0. based on channel0.v (theora)
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
`timescale 1 ns / 1 ps
module channel_rd (
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
start2,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
sddi, //[31:0]
rq_busy,
//SDRAM controller inteface (mcontr_line_rd)
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
obre, // output read enable, advance address
ch1a,
obdat, // [15:0] output dtata
next_line, // advance to the next scan line (and next block RAM page if needed)
ao
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input [ 11:0] ch1a;
input start;
input start2;
input rq_busy;
output rq;
output rq_urgent;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
input [31:0] sddi; // data from SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input obre; // output read enable
output[15:0] obdat; // [15:0] output dtata
input next_line;
output [10:0] ao;
wire predrun;
reg we;
reg done;
reg [10:0] a=0;
reg [2:0] rq_cnt=0;
wire init0;
reg init_pclk;
wire page_used0;
reg page_used;
reg rq;
reg rq_urgent;
reg [1:0] obpage;
reg [7:0] obaddr;
wire next_opage;
reg cs,cs0;
reg [21:0] sa=0;
reg [7:0] obre_cnt=0;
reg [4:0] len;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [7:0] ny_cnt=0;
reg [7:0] nx_cnt=0;
reg [1:0] bank=0;
assign next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
always @ (negedge clk) init_pclk <= init;
always @ (negedge clk) page_used <= !init_pclk && next_opage;
always @ (negedge clk) begin
if (init_pclk | next_opage) obre_cnt[7:0] <= 0;
else if (obre) obre_cnt[7:0] <= obre_cnt[7:0] + 1;
end
//wire switch_order=0;
always @ (negedge clk) begin
if (init) rq_cnt <= 0;
else if (start2)
if (rq_busy) rq_cnt <= rq_cnt + 1;
else rq_cnt <= rq_cnt;
else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
rq <= enrq & (start2 | (rq & !start));
rq_urgent <= enrq & start2 & (rq_cnt==3);
end
assign ao[10:0]=a[10:0];
always @ (negedge clk) begin
we <= predrun;
done <= we & !predrun;
if (init) a[10:0] <= 11'b0;
else if (we) a[10:0] <= a[10:0] + 1;
//if (init) a[9:0] <= 10'b0;
//else if (we) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg [11:10] ch1a_d=0;
always @ (negedge clk) begin
ch1a_d[11:10] <= ch1a[11:10];
end
wire [15:0] obdat_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(obdat_0[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & !ch1a[11] & !ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & !a[10] & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_1;
RAMB16_S18_S36 i_buf_1 (
.DOA(obdat_1[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & !ch1a[11] & ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & !a[10] & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_2;
RAMB16_S18_S36 i_buf_2 (
.DOA(obdat_2[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & ch1a[11] & !ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & a[10] & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_3;
RAMB16_S18_S36 i_buf_3 (
.DOA(obdat_3[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & ch1a[11] & ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & a[10] & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
assign obdat=ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
endmodule
channel_rd_short.v 0 → 100644
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_rd_short.v
*! DESCRIPTION: channel for read from sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_rd_short.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*/
`timescale 1 ns / 1 ps
module channel_rd_short (
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
start2,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
sddi, //[31:0]
rq_busy,
//SDRAM controller inteface (mcontr_line_rd)
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
obre, // output read enable, advance address
ch1a,
obdat, // [15:0] output dtata
next_line, // advance to the next scan line (and next block RAM page if needed)
ao
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input [ 11:0] ch1a;
input start;
input start2;
input rq_busy;
output rq;
output rq_urgent;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
input [31:0] sddi; // data from SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input obre; // output read enable
output[15:0] obdat; // [15:0] output dtata
input next_line;
output [10:0] ao;
wire predrun;
reg we;
reg done;
reg [10:0] a=0;
reg [2:0] rq_cnt=0;
wire init0;
reg init_pclk;
wire page_used0;
reg page_used;
reg rq;
reg rq_urgent;
reg [1:0] obpage;
reg [7:0] obaddr;
wire next_opage;
reg cs,cs0;
reg [21:0] sa=0;
reg [7:0] obre_cnt=0;
reg [4:0] len;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [7:0] ny_cnt=0;
reg [7:0] nx_cnt=0;
reg [1:0] bank=0;
assign next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
always @ (negedge clk) init_pclk <= init;
always @ (negedge clk) page_used <= !init_pclk && next_opage;
always @ (negedge clk) begin
if (init_pclk | next_opage) obre_cnt[7:0] <= 0;
else if (obre) obre_cnt[7:0] <= obre_cnt[7:0] + 1;
end
//wire switch_order=0;
always @ (negedge clk) begin
if (init) rq_cnt <= 0;
else if (start2)
if (rq_busy) rq_cnt <= rq_cnt + 1;
else rq_cnt <= rq_cnt;
else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
rq <= enrq & (start2 | (rq & !start));
rq_urgent <= enrq & start2 & (rq_cnt==3);
end
assign ao[10:0]=a[10:0];
always @ (negedge clk) begin
we <= predrun;
done <= we & !predrun;
if (init) a[10:0] <= 11'b0;
else if (we) a[10:0] <= a[10:0] + 1;
//if (init) a[9:0] <= 10'b0;
//else if (we) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg [11:10] ch1a_d=0;
always @ (negedge clk) begin
ch1a_d[11:10] <= ch1a[11:10];
end
wire [15:0] obdat_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(obdat_0[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(we) // Port B Write Enable Input
);
wire [15:0] obdat_1;
wire [15:0] obdat_2;
wire [15:0] obdat_3;
assign obdat=obdat_0;//ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
endmodule
channel_wr.v 0 → 100644
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_wr.v
*! DESCRIPTION: channel for write to sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_wr.v,v $
*! Revision 1.5 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:09:35 dzhimiev
*! 0. based on channel0.v (theora)
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
`timescale 1 ns / 1 ps
module channel_wr(
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2?
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
//SDRAM controller inteface (mcontr_line_wr)
sddo, //[31:0]
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
ibwe, // input data write enable, advance address
ch0a,
ibdat, // [15:0] input data (1 or 2 pixels)
next_line // advance to the next scan line (and next block RAM page if needed)
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input start;
output rq;
output rq_urgent;
output [31:0] sddo; //[31:0] - data to SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input ibwe;
input [10:0] ch0a;
input [15:0] ibdat;
input next_line;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
wire next_line;
wire predrun;
reg re;
reg done;
reg [9:0] a;
reg [4:0] full_pages_in_buffer;
wire init0;
reg init_pclk;
wire page_prepared0;
reg page_prepared;
reg rq=0;
//wire rq;
reg rq_urgent;
reg [21:0] sa=0;
reg [7:0] ibwe_cnt=0;
reg [4:0] len;
wire [10:0] ch0a;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [ 6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [ 7:0] ny_cnt=0;
reg [ 7:0] nx_cnt=0;
reg [1:0] bank=0;
wire next_ipage;
always @ (posedge clk)
if (init) init_pclk <= 1;
else init_pclk <= 0;
always @ (negedge clk)
if (!init_pclk & next_ipage) page_prepared <= 1;
else page_prepared <= 0;
always @ (posedge clk) begin
if (init_pclk | next_ipage) ibwe_cnt[7:0] <= 0;
else if (ibwe) ibwe_cnt[7:0] <= ibwe_cnt[7:0] + 1;
end
//assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'hff) & ibwe));
//assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'h7f) & ibwe));
assign next_ipage=0;//((ibwe_cnt[5:0]==63) & ibwe);
always @ (negedge clk) begin
if (init)
full_pages_in_buffer <= 5'h0;
else if (next_line & start)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0];
else if (next_line)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] +1;
else if (start)
if (full_pages_in_buffer[4:0]!=0)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] -1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
if (!start)
rq <= ((next_line|rq) & enrq & !init);//|(rq & !start);
else
// rq <= 0;
rq <= enrq & (full_pages_in_buffer[4:0] != 1);
rq_urgent <= enrq & (full_pages_in_buffer[3] | (full_pages_in_buffer[3:0]==7)); //>=3
end
//assign rq=next_line&enrq&!init;
always @ (negedge clk) begin
re <= predrun;
done <= re & !predrun;
if (init) a[9:0] <= 10'b0;
else if (re) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg a_d=0;
always @ (negedge clk) begin
a_d <= a[9];
end
wire [31:0] sddo_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(), // Port A 16-bit Data Output - compressor side
.DOPA(), // Port A 2-bit Parity Output
.ADDRA(ch0a[9:0]),
.CLKA(clk), // Port A Clock
.DIA(ibdat[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(ibwe & !ch0a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(sddo_0[31:0]), // Port B 32-bit Data Output - SDRAM side
.DOPB(), // Port B 4-bit Parity Output
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(32'h0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(re & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
wire [31:0] sddo_1;
RAMB16_S18_S36 i_buf_1 (
.DOA(), // Port A 16-bit Data Output - compressor side
.DOPA(), // Port A 2-bit Parity Output
.ADDRA(ch0a[9:0]),
.CLKA(clk), // Port A Clock
.DIA(ibdat[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(ibwe & ch0a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(sddo_1[31:0]), // Port B 32-bit Data Output - SDRAM side
.DOPB(), // Port B 4-bit Parity Output
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(32'h0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(re & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
assign sddo[31:0]=a_d?sddo_1[31:0]:sddo_0[31:0];
endmodule
clkios353.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** clkios353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002-2006 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
** $Log: clkios353.v,v $
** Revision 1.5 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
** Revision 1.1 2009/06/11 17:39:00 dzhimiev
** new initial version
** 1. simulation and board test availability
**
** Revision 1.1 2008/12/08 09:07:57 dzhimiev
** 1. set up of the data path for the transform
** 2. 2 read and 2 write channels
** 3. in snapshot mode - 3 frames output sequence -
** 1st - direct
** 2nd - stored 'direct' from the 1st buffer
** 3rd - stored '1st buffer' from the 2nd buffer
**
** Revision 1.1 2008/04/23 01:55:49 dzhimiev
** 1. added x359 files to src lists
** 2. x359 read/write DDR
** 3. x359 3 channels mux directly to out
** 4. x359 one channel through DDR and another directly frames switching at out
**
*/
// Some placement constraints are in this file
`timescale 1 ns / 1 ps
module dcm333(
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
sdcl_fb,
xclk, // 60MHz for compressor
phsel, // additional phase control for SDRAM CLK
dcm_rst, // reset DCM phase
dcm_incdec, // variable phase control to adjust SDCLK so read DQS is aligned with sclk90/sclk270
dcm_en,
dcm_clk,
dcm_done,
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input sclk;
output xclk;
output SDCLK, SDNCLK;
input [1:0] phsel;
input sdcl_fb;
input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done;
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire isdclk0, isdclk90, isdclk180, isdclk270;
wire ixclk;
wire gsdclk; //used only for the feedback
wire isdclk;
reg dcm_done;
wire dcm_done_dcm; // single-cycle
assign isdclk=phsel[1]? (phsel[0]?isdclk270:isdclk180):(phsel[0]?isdclk90:isdclk0);
FD i_ixclk (.C(sclk), .D(!ixclk), .Q(ixclk));
BUFG i_xclk (.I(ixclk), .O(xclk));
// second - adjustable DCM. Will be adjusted so read DQS (dependent on SDCLK) will be aligned with sclk90/270
// maybe will need some delay as there is DLL in SDRAM and responce may be slow.
DCM i_dcm2(
.CLKIN (sclk),
// .CLKFB (gsdclk), // initial
.CLKFB (isdclk90),
// .CLKFB (sdcl_fb),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (dcm_clk),.DSSEN (1'b0),
.CLK0 (isdclk0),
.CLK90 (isdclk90),
.CLK180 (isdclk180),
.CLK270 (isdclk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE (dcm_done_dcm));
// s-ynthesis attribute loc of i_dcm2 is "DCM_X1Y1"
// synthesis attribute CLK_FEEDBACK of i_dcm2 is "1X"
// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm2 is "FALSE"
// synthesis attribute CLKIN_PERIOD of i_dcm2 is 8.33333
// synthesis attribute CLKOUT_PHASE_SHIFT of i_dcm2 is "VARIABLE"
// synthesis attribute DESKEW_ADJUST of i_dcm2 is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DLL_FREQUENCY_MODE of i_dcm2 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm2 is "TRUE"
// put here default phase shift ....
// synthesis attribute PHASE_SHIFT of i_dcm2 is 0
// synthesis translate_off
// defparam i_dcm2.CLK_FEEDBACK="1X";
// defparam i_dcm2.CLKIN_DIVIDE_BY_2="FALSE";
// defparam i_dcm2.CLKIN_PERIOD=8.33333;
// defparam i_dcm2.CLKOUT_PHASE_SHIFT="VARIABLE";
// defparam i_dcm2.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
// defparam i_dcm2.DLL_FREQUENCY_MODE="LOW";
// defparam i_dcm2.DUTY_CYCLE_CORRECTION="TRUE";
// defparam i_dcm2.PHASE_SHIFT=0;
// synthesis translate_on
BUFG i_gsdclk (.I(isdclk90), .O(gsdclk));
OBUFDS i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
// OBUFDS i_SDCLK (.O(SDNCLK),.OB(SDCLK),.I(!isdclk));
// make dcm_done behave as dcm_ready
always @ (posedge dcm_clk or posedge dcm_rst)
if (dcm_rst) dcm_done <= 1'b1;
else if (dcm_en) dcm_done <=1'b0;
else if (dcm_done_dcm) dcm_done <=1'b1;
endmodule
module clockios353(
CLK0, // input clock pad - 120MHz
sclk0, // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge)
/*sclk90,*/ // global clock, 120MHz, phase=90 (strobe data write to sdram)
sclk180, // global clock, 120MHz, phase=180 (just to generate DQS :-( )
sclk270, // global clock, 120MHz, phase=270 (strobe data write to sdram)
iclk0, //before BUFG
dcmrst, //reset dcm
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input CLK0;
output sclk0,/*sclk90,*/sclk270,sclk180;
output iclk0;
input dcmrst; //reset dcm
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire iclk0;
wire isclk0, /*isclk90,*/ isclk270, isclk180;
BUFG i_iclk0 (.I(CLK0), .O(iclk0));
// DCM - just 4 phases out
DCM i_dcm1(
.CLKIN (iclk0),
.CLKFB (sclk0),
.RST (dcmrst), .PSEN (1'b0),.PSINCDEC (1'b0), .PSCLK (1'b0),.DSSEN (1'b0),
.CLK0 (isclk0),
.CLK90 (/*isclk90*/),
.CLK180 (isclk180),
.CLK270 (isclk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE ());
// s- ynthesis attribute loc of i_dcm1 is "DCM_X0Y0"
// synthesis attribute CLK_FEEDBACK of i_dcm1 is "1X"
// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm1 is "FALSE"
// synthesis attribute CLKIN_PERIOD of i_dcm1 is 8.33333
// synthesis attribute DESKEW_ADJUST of i_dcm1 is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DLL_FREQUENCY_MODE of i_dcm1 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm1 is "TRUE"
// synthesis translate_off
defparam i_dcm1.CLK_FEEDBACK="1X";
defparam i_dcm1.CLKIN_DIVIDE_BY_2="FALSE";
defparam i_dcm1.CLKIN_PERIOD=8.33333;
defparam i_dcm1.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
defparam i_dcm1.DLL_FREQUENCY_MODE="LOW";
defparam i_dcm1.DUTY_CYCLE_CORRECTION="TRUE";
// synthesis translate_on
BUFG i_sclk0 (.I(isclk0),. O(sclk0));
// s-ynthesis attribute loc of i_sclk0 is "BUFGMUX0"
/* BUFG i_sclk90 (.I(isclk90), .O(sclk90)); */
// s-ynthesis attribute loc of i_sclk90 is "BUFGMUX1"
BUFG i_sclk180(.I(isclk180),.O(sclk180));
// s-ynthesis attribute loc of i_sclk180 is "BUFGMUX2"
BUFG i_sclk270(.I(isclk270),.O(sclk270));
// s-ynthesis attribute loc of i_sclk270 is "BUFGMUX3"
endmodule
/*
module clock_pclk( clk0, // global clock (phase =0)
CLK1, // external input clock
pclk, // global clock, sensor pixel rate
clk_en, // enable clock output to sensor
pclk_src,// [3:0] - source fror the pclk
dclk); // clock output to sensor (sync to pclk)
input CLK1,clk0,clk_en;
input [3:0] pclk_src;
output pclk,dclk;
wire ipclk,dclk,pclk;
reg clk_en_r;
IBUF i_iclk1 (.I(CLK1), .O(iclk1));
// and global clock (divided by 1, 1.5,2,...,8)
pclk_cntrl i_pclk_cntrl(.ext_clk(iclk1), // external clock, may be stopped (will wait for up to 16 clk periods?)
.clk(clk0), // always running global clock
.div(pclk_src[3:0]), // 0: q=ext_clk
// 1: q=clk - temporary made clk/1.5 - not to fry MI1300
// 2: q=clk/1.5
//...0'hf: q=clk/8
.q(ipclk)); // output clock
always @ (posedge pclk) clk_en_r<=clk_en;
assign dclk=!clk_en_r || !ipclk;
BUFG i_pclk (.I(ipclk), .O(pclk));
endmodule
// switches between external clock (no divisor)
// and global clock (divided by 1, 1.5,2,...,8)
module pclk_cntrl(ext_clk, // external clock, may be stopped (will wait for up to 16 clk periods?)
clk, // always running global clock
div, // 0: q=ext_clk
// 1: q=clk - temporary made clk/1.5 - not to fry MI1300
// 2: q=clk/1.5
//...0'hf: q=clk/8
q); // output clock
input ext_clk;
input clk;
input [3:0] div;
output q;
reg ena;
reg enb;
// reg clksel;
wire [3:0] div_p;
wire blank;
wire copy_div,blank_off;
wire a_on, a_off0, b_on, b_off;
reg [3:0] da0; // from a_start to a_on
reg [3:0] da1; // from a_on to a_off
reg [3:0] db0; // from a_start to a_on
reg [3:0] db1; // from a_on to a_off
reg a_start;
reg b_start;
reg a_off;
reg a_singleon; // a stays on for 1 cycle;
reg use_b;
wire a,b,ab;
FDE i_div_p0 (.C(clk),.CE(copy_div),.D(div[0]),.Q(div_p[0]));
FDE i_div_p1 (.C(clk),.CE(copy_div),.D(div[1]),.Q(div_p[1]));
FDE i_div_p2 (.C(clk),.CE(copy_div),.D(div[2]),.Q(div_p[2]));
FDE i_div_p3 (.C(clk),.CE(copy_div),.D(div[3]),.Q(div_p[3]));
always @ (posedge enb or posedge ext_clk) begin
if (enb) ena <=1'b0;
else ena <= (div[3:0]==4'b0);
end
always @ (posedge clk) begin
enb <= (div_p[3:0]!=4'b0);
a_off <= a_singleon?a_on:a_off0;
a_start <= blank_off || (!blank && (a_singleon?a_on:a_off0));
end
always @ (negedge clk) begin
b_start <= a_start;
use_b <= (div_p[3:0]!=4'h0) && (div_p[1:0]!=2'h3);
end
FD i_blank (.C(clk),.D((div[3:0] != div_p[3:0]) || (blank && !blank_off)),.Q(blank)); // add always blank if (div==0)? no!
SRL16 i_copy_div (.Q(copy_div),.D((div[3:0] != div_p[3:0]) && !blank), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=max (16)
SRL16 i_blank_off(.Q(blank_off),.D(copy_div), .CLK(clk), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0)); // 2
SRL16 i_a_on (.Q(a_on), .D(a_start), .CLK(clk), .A0(da0[0]), .A1(da0[1]), .A2(da0[2]), .A3(da0[3]));
SRL16 i_a_off0(.Q(a_off0),.D(a_on), .CLK(clk), .A0(da1[0]), .A1(da1[1]), .A2(da1[2]), .A3(da1[3]));
SRL16_1 i_b_on (.Q(b_on), .D(b_start), .CLK(clk), .A0(db0[0]), .A1(db0[1]), .A2(db0[2]), .A3(db0[3]));
SRL16_1 i_b_off (.Q(b_off), .D(b_on), .CLK(clk), .A0(db1[0]), .A1(db1[1]), .A2(db1[2]), .A3(db1[3]));
FD i_a (.C(clk),.D(enb && (a_on || (a && !a_off))),.Q(a));
FD_1 i_b (.C(clk),.D(use_b && (b_on || (b && !b_off))),.Q(b));
assign ab= ~(a ^ b);
assign q= (!ena || ext_clk) && (!enb || ab);
always @ (posedge clk) case (div_p[3:0])
4'h0: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end // any, not used
// 4'h1: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b1; end
4'h1: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)
4'h2: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end
4'h3: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b1; end
4'h4: begin da0<=4'h3; da1<=4'h0; a_singleon<=1'b1; end
4'h5: begin da0<=4'h2; da1<=4'h1; a_singleon<=1'b0; end
4'h6: begin da0<=4'h1; da1<=4'h3; a_singleon<=1'b0; end
4'h7: begin da0<=4'h1; da1<=4'h0; a_singleon<=1'b0; end
4'h8: begin da0<=4'h6; da1<=4'h0; a_singleon<=1'b0; end
4'h9: begin da0<=4'h4; da1<=4'h3; a_singleon<=1'b0; end
4'ha: begin da0<=4'h2; da1<=4'h6; a_singleon<=1'b0; end
4'hb: begin da0<=4'h2; da1<=4'h1; a_singleon<=1'b0; end
4'hc: begin da0<=4'h9; da1<=4'h1; a_singleon<=1'b0; end
4'hd: begin da0<=4'h6; da1<=4'h5; a_singleon<=1'b0; end
4'he: begin da0<=4'h3; da1<=4'h9; a_singleon<=1'b0; end
4'hf: begin da0<=4'h3; da1<=4'h2; a_singleon<=1'b0; end
endcase
always @ (negedge clk) case (div_p[3:0])
4'h0: begin db0<=4'h0; db1<=4'h0; end
// 4'h1: begin db0<=4'h1; db1<=4'h0; end
4'h1: begin db0<=4'h0; db1<=4'h0; end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)
4'h2: begin db0<=4'h0; db1<=4'h0; end
4'h3: begin db0<=4'h0; db1<=4'h0; end
4'h4: begin db0<=4'h0; db1<=4'h0; end
4'h5: begin db0<=4'h0; db1<=4'h2; end
4'h6: begin db0<=4'h2; db1<=4'h1; end
4'h7: begin db0<=4'h0; db1<=4'h0; end
4'h8: begin db0<=4'h1; db1<=4'h1; end
4'h9: begin db0<=4'h1; db1<=4'h4; end
4'ha: begin db0<=4'h4; db1<=4'h2; end
4'hb: begin db0<=4'h0; db1<=4'h0; end
4'hc: begin db0<=4'h2; db1<=4'h2; end
4'hd: begin db0<=4'h2; db1<=4'h6; end
4'he: begin db0<=4'h6; db1<=4'h3; end
4'hf: begin db0<=4'h0; db1<=4'h0; end
endcase
endmodule
*/
dcm_phase.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** dcm_phase.v
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
** $Log: dcm_phase.v,v $
** Revision 1.2 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
*/
`timescale 1 ns / 1 ps
module dcm_phase (
cclk, // command clock for shift
wcmd, // decoded address - enables wclk
cmd, // CPU write data [3:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// 4 - incr pahse90
// 8 - decrease phase90
// c - reset phase90
iclk, // DCM input clock
clk_fb, // feed back clock
clk0, // global output clock, phase 0
clk90, // global output clock, phase 90
clk180, // global output clock, phase 180
clk270, // global output clock, phase 270
dcm_phase, // current DCM phase (small steps)
dcm_phase_90,// current DCM quarter (90 degrees steps)
dcm_done, // DCM command done
dcm_status, // DCM status (bit 1 - dcm clkin stopped)
dcm_locked // DCM "Locked" pin
);
parameter NO_SHIFT90=0; //wanted to choose between clk0 BUFGs
input cclk;
input wcmd;
input [ 3:0] cmd;
input iclk;
input clk_fb;
output clk0;
output clk90;
output clk180;
output clk270;
output [8:0] dcm_phase;
output [1:0] dcm_phase_90;
output dcm_done;
output [7:0] dcm_status;
output dcm_locked;
reg dcm_rst=0;
wire dcm_rst_cmd;
reg [2:0] dcm_drst=0;
reg [2:0] dcm_reset_done=0;
wire dcm_done_dcm;
reg dcm_en=0;
reg dcm_incdec=0;
reg [8:0] phase_reg=0;
reg [1:0] phase90_reg=0;
reg dcm_done=0;
assign dcm_phase[8:0] = phase_reg[8:0];
assign dcm_phase_90[1:0] = NO_SHIFT90? 0 : phase90_reg[1:0];
FD i_dcm_rst_cmd(.Q(dcm_rst_cmd), .D((wcmd && (cmd[1:0] == 2'b11)) || (dcm_rst_cmd && !dcm_drst[2])), .C(cclk));
// shift commands are synchronous to the command clock
always @ (posedge cclk) begin
dcm_reset_done[2:0] <= {dcm_reset_done[1] & ~dcm_reset_done[0], dcm_reset_done[0], dcm_rst}; // sync to cclkl end of dcm reset
dcm_en <= wcmd && (cmd[1]!=cmd[0]);
dcm_incdec <= wcmd && cmd[0];
if (wcmd) begin
if (cmd[0] && cmd[1]) phase_reg[8:0] <= 9'h0;
else if (cmd[0]) phase_reg[8:0] <= phase_reg[8:0] +1;
else if (cmd[1]) phase_reg[8:0] <= phase_reg[8:0] -1;
end
if (wcmd) begin
if (cmd[2] && cmd[3]) phase90_reg[1:0] <= 2'h0;
else if (cmd[2]) phase90_reg[1:0] <= phase90_reg[1:0] +1;
else if (cmd[3]) phase90_reg[1:0] <= phase90_reg[1:0] -1;
end
end
// dcm_rst is synchronous to incoming clock
always @ (posedge iclk) begin
dcm_drst[2:0] <= dcm_drst[2]? 3'b0:{dcm_drst[1], dcm_drst[0], dcm_rst_cmd};
dcm_rst <= dcm_drst[0] || dcm_drst[1] || dcm_drst[2] ;
end
// make dcm_done behave as dcm_ready
always @ (posedge cclk)
if (wcmd && |cmd[2:0]) dcm_done <= 0;
else if (dcm_done_dcm || dcm_reset_done[2]) dcm_done <= 1;
/// DCM to compensate sensor delays. Adjustment for data phase - both fine and 90-degrees, hact/vact - 90-degree steps relative to data
DCM_SP #(
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), //96Hz
.CLKOUT_PHASE_SHIFT("VARIABLE"),// Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) i_dcm_sensor(
.CLKIN (iclk),
.CLKFB (clk_fb),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (cclk),
.DSSEN (1'b0),
.CLK0 (pre_clk0),
.CLK90 (pre_clk90), // adjust tap
.CLK180 (pre_clk180), // adjust tap
.CLK270 (pre_clk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (dcm_status[7:0]),
.LOCKED (dcm_locked),
.PSDONE (dcm_done_dcm)
);
wire pre_clk = phase90_reg[1]? (phase90_reg[0]? pre_clk270:pre_clk180) : (phase90_reg[0]? pre_clk90:pre_clk0);
BUFG i_clk0a (.I(NO_SHIFT90?pre_clk0:pre_clk), .O(clk0));
// BUFG i_clk0b (.I(pre_clk), .O(clk0));
BUFG i_clk90 (.I(pre_clk90), .O(clk90));
BUFG i_clk180 (.I(pre_clk180), .O(clk180));
BUFG i_clk270 (.I(pre_clk270), .O(clk270));
endmodule
ddr.v 0 → 100644
View file @ 1727b764
/****************************************************************************************
*
* File Name: ddr.v
* Version: 5.7
* Model: BUS Functional
*
* Dependencies: ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate)
*
* Limitation: - Doesn't check for 8K-cycle refresh.
* - Doesn't check power-down entry/exit
* - Doesn't check self-refresh entry/exit.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 2.1 SPH 03/19/2002 - Second Release
* - Fix tWR and several incompatability
* between different simulators
* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
* - Added tDQSH and tDQSL timing checks.
* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
* - Changed Dq_buf size to [15:0]
* 5.0 JMK 06/16/2004 - Added read to write checking.
* - Added read with precharge truncation to write checking.
* - Added associative memory array to reduce memory consumption.
* - Added checking for required DQS edges during write.
* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
* - Fixed wdqs_valid window.
* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
* - Added tRFC checking during Load Mode and Precharge.
* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
* JMK 02/11/2005 - Changed the display format for numbers to hex.
* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
* - Renamed parameters file with .vh extension.
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1 ns / 1 ps
module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
`include "ddr_parameters.v"
// Port Declarations
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
input [ADDR_BITS - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [DM_BITS - 1 : 0] Dm;
// Internal Wires (fixed width)
wire [15 : 0] Dq_in;
wire [1 : 0] Dqs_in;
wire [1 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [15 : 0] dq_rise;
reg [1 : 0] dm_rise;
reg [15 : 0] dq_fall;
reg [1 : 0] dm_fall;
reg [3 : 0] dm_pair;
reg [15 : 0] Dq_buf;
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
reg Dqs_int;
// Dqs buffer
reg [DQS_BITS - 1 : 0] Dqs_out;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out;
// Read pipeline variables
reg Read_cmnd [0 : 6];
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg Write_cmnd [0 : 3];
reg [1 : 0] Write_bank [0 : 3];
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
// Auto precharge variables
reg Read_precharge [0 : 3];
reg Write_precharge [0 : 3];
integer Count_precharge [0 : 3];
// Manual precharge variables
reg A10_precharge [0 : 6];
reg [1 : 0] Bank_precharge [0 : 6];
reg Cmnd_precharge [0 : 6];
// Burst terminate variables
reg Cmnd_bst [0 : 6];
// Memory Banks
`ifdef FULL_MEM
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<full_mem_bits)-1];
`else
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<part_mem_bits)-1];
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
reg [part_mem_bits : 0] mem_used;
initial mem_used = 0;
`endif
// Dqs edge checking
integer i;
reg [1:0] expect_pos_dqs;
reg [1:0] expect_neg_dqs;
// Burst counter
reg [COL_BITS - 1 : 0] Burst_counter;
// Precharge variables
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
// Activate variables
reg Act_b0, Act_b1, Act_b2, Act_b3;
// Data IO variables
reg Data_in_enable;
reg Data_out_enable;
// Internal address mux variables
reg [1 : 0] Prev_bank;
reg [1 : 0] Bank_addr;
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
reg [ADDR_BITS - 1 : 0] Rows_addr;
reg [ADDR_BITS - 1 : 0] B0_row_addr;
reg [ADDR_BITS - 1 : 0] B1_row_addr;
reg [ADDR_BITS - 1 : 0] B2_row_addr;
reg [ADDR_BITS - 1 : 0] B3_row_addr;
// DLL Reset variable
reg DLL_enable;
reg DLL_reset;
reg DLL_done;
integer DLL_count;
integer aref_count;
integer Prech_count;
reg power_up_done;
// Write DQS for tDSS, tDSH, tDQSH, tDQSL checks
wire wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[0] & ~Ba[1];
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
reg [3:0] read_precharge_truncation;
// CAS Latency Decode
wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
// DQS Buffer
assign Dqs = Dqs_out;
// DQ Buffer
assign Dq = Dq_out;
// Debug message
//wire Debug = 1'b1;
// Timing Check
time MRD_chk;
time RFC_chk;
time RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
time WR_chk0, WR_chk1, WR_chk2, WR_chk3;
initial begin
CkeZ = 1'b0;
Sys_clk = 1'b0;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
Dqs_int = 1'b0;
Dqs_out = {DQS_BITS{1'bz}};
Dq_out = {DQ_BITS{1'bz}};
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
DLL_enable = 1'b0;
DLL_reset = 1'b0;
DLL_done = 1'b0;
DLL_count = 0;
aref_count = 0;
Prech_count = 0;
power_up_done = 0;
MRD_chk = 0;
RFC_chk = 0;
RRD_chk = 0;
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;
{RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
{WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
$timeformat (-9, 3, " ns", 12);
end
// System Clock
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
always @(Cke) begin
if (Cke === 1'b1) begin
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
$display ("%m: at time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $time);
$display ("%m: when the Clock Enable is brought High.");
end
end
end
// Check the initialization sequence
initial begin
@ (posedge Cke) begin
$display("Expecting initialization. oleg");
@ (posedge DLL_enable) begin
aref_count = 0;
@ (posedge DLL_reset) begin
@ (Prech_count) begin
if (aref_count >= 2) begin
if (Debug) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end else begin
aref_count = 0;
@ (aref_count >= 2) begin
if (Debug) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end
end
end
end
end
end
end
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
mem_array[addr] = data;
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i === mem_used) begin
if (i === (1<<part_mem_bits)) begin
$display ("At time %t ERROR: Memory overflow.\n Write to Address %x with Data %x will be lost.\n You must increase the part_mem_bits parameter or define FULL_MEM.", $time, addr, data);
end else begin
mem_used = mem_used + 1;
addr_array[i] = addr;
end
end
mem_array[i] = data;
`endif
end
endtask
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
data = mem_array[addr];
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i <= mem_used) begin
data = mem_array[i];
end
`endif
end
endtask
// Burst Decode
task Burst_Decode;
begin
// Advance Burst Counter
if (Burst_counter < burst_length) begin
Burst_counter = Burst_counter + 1;
end
// Burst Type
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
Cols_temp = Cols_addr + 1;
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
end
// Burst Length
if (burst_length === 2) begin
Cols_addr [0] = Cols_temp [0];
end else if (burst_length === 4) begin
Cols_addr [1 : 0] = Cols_temp [1 : 0];
end else if (burst_length === 8) begin
Cols_addr [2 : 0] = Cols_temp [2 : 0];
end else begin
Cols_addr = Cols_temp;
end
// Data Counter
if (Burst_counter >= burst_length) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
read_precharge_truncation = 4'h0;
end
end
endtask
// Manual Precharge Pipeline
task Manual_Precharge_Pipeline;
begin
// A10 Precharge Pipeline
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = A10_precharge[4];
A10_precharge[4] = A10_precharge[5];
A10_precharge[5] = A10_precharge[6];
A10_precharge[6] = 1'b0;
// Bank Precharge Pipeline
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = Bank_precharge[4];
Bank_precharge[4] = Bank_precharge[5];
Bank_precharge[5] = Bank_precharge[6];
Bank_precharge[6] = 2'b0;
// Command Precharge Pipeline
Cmnd_precharge[0] = Cmnd_precharge[1];
Cmnd_precharge[1] = Cmnd_precharge[2];
Cmnd_precharge[2] = Cmnd_precharge[3];
Cmnd_precharge[3] = Cmnd_precharge[4];
Cmnd_precharge[4] = Cmnd_precharge[5];
Cmnd_precharge[5] = Cmnd_precharge[6];
Cmnd_precharge[6] = 1'b0;
// Terminate a Read if same bank or all banks
if (Cmnd_precharge[0] === 1'b1) begin
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
if (Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
read_precharge_truncation = 4'hF;
end
end
end
end
endtask
// Burst Terminate Pipeline
task Burst_Terminate_Pipeline;
begin
// Command Precharge Pipeline
Cmnd_bst[0] = Cmnd_bst[1];
Cmnd_bst[1] = Cmnd_bst[2];
Cmnd_bst[2] = Cmnd_bst[3];
Cmnd_bst[3] = Cmnd_bst[4];
Cmnd_bst[4] = Cmnd_bst[5];
Cmnd_bst[5] = Cmnd_bst[6];
Cmnd_bst[6] = 1'b0;
// Terminate a Read regardless of banks
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// read command pipeline
Read_cmnd [0] = Read_cmnd [1];
Read_cmnd [1] = Read_cmnd [2];
Read_cmnd [2] = Read_cmnd [3];
Read_cmnd [3] = Read_cmnd [4];
Read_cmnd [4] = Read_cmnd [5];
Read_cmnd [5] = Read_cmnd [6];
Read_cmnd [6] = 1'b0;
// read bank pipeline
Read_bank [0] = Read_bank [1];
Read_bank [1] = Read_bank [2];
Read_bank [2] = Read_bank [3];
Read_bank [3] = Read_bank [4];
Read_bank [4] = Read_bank [5];
Read_bank [5] = Read_bank [6];
Read_bank [6] = 2'b0;
// read column pipeline
Read_cols [0] = Read_cols [1];
Read_cols [1] = Read_cols [2];
Read_cols [2] = Read_cols [3];
Read_cols [3] = Read_cols [4];
Read_cols [4] = Read_cols [5];
Read_cols [5] = Read_cols [6];
Read_cols [6] = 0;
// Initialize Read command
if (Read_cmnd [0] === 1'b1) begin
Data_out_enable = 1'b1;
Bank_addr = Read_bank [0];
Cols_addr = Read_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Bank Address", $time);
endcase
end
// Toggle Dqs during Read command
if (Data_out_enable === 1'b1) begin
Dqs_int = 1'b0;
if (Dqs_out === {DQS_BITS{1'b0}}) begin
Dqs_out = {DQS_BITS{1'b1}};
end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
Dqs_out = {DQS_BITS{1'b0}};
end else begin
Dqs_out = {DQS_BITS{1'b0}};
end
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
Dqs_out = {DQS_BITS{1'bz}};
end
// Initialize dqs for Read command
if (Read_cmnd [2] === 1'b1) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_out = {DQS_BITS{1'b0}};
end
end
// Read latch
if (Data_out_enable === 1'b1) begin
// output data
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
if (Debug) begin
$display ("At time %t READ : Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
end
end else begin
Dq_out = {DQ_BITS{1'bz}};
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Write command pipeline
Write_cmnd [0] = Write_cmnd [1];
Write_cmnd [1] = Write_cmnd [2];
Write_cmnd [2] = Write_cmnd [3];
Write_cmnd [3] = 1'b0;
// Write command pipeline
Write_bank [0] = Write_bank [1];
Write_bank [1] = Write_bank [2];
Write_bank [2] = Write_bank [3];
Write_bank [3] = 2'b0;
// Write column pipeline
Write_cols [0] = Write_cols [1];
Write_cols [1] = Write_cols [2];
Write_cols [2] = Write_cols [3];
Write_cols [3] = {COL_BITS{1'b0}};
// Initialize Write command
if (Write_cmnd [0] === 1'b1) begin
Data_in_enable = 1'b1;
Bank_addr = Write_bank [0];
Cols_addr = Write_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Row Address", $time);
endcase
end
// Write data
if (Data_in_enable === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
if (~&dm_fall) begin
if (Debug) begin
$display ("At time %t WRITE: Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
if (~&dm_rise) begin
if (Debug) begin
$display ("At time %t WRITE: Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $time;
2'd1 : WR_chk1 = $time;
2'd2 : WR_chk2 = $time;
2'd3 : WR_chk3 = $time;
default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
endcase
// tWTR check
if (Read_enable === 1'b1) begin
$display ("At time %t ERROR: tWTR violation during Read", $time);
end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. BL/2 cycles after command
if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Read_precharge[0] = 1'b0;
end
end
if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Read_precharge[1] = 1'b0;
end
end
if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Read_precharge[2] = 1'b0;
end
end
if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Read_precharge[3] = 1'b0;
end
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Write_precharge[0] = 1'b0;
end
end
if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Write_precharge[1] = 1'b0;
end
end
if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Write_precharge[2] = 1'b0;
end
end
if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Write_precharge[3] = 1'b0;
end
end
end
endtask
// DLL Counter
task DLL_Counter;
begin
if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
DLL_count = DLL_count + 1;
if (DLL_count >= 200) begin
DLL_done = 1'b1;
end
end
end
endtask
// Control Logic
task Control_Logic;
begin
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t AREF : Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
end
// LMR/EMR to Auto Refresh
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
if (!no_halt) $stop (0);
end else begin
aref_count = aref_count + 1;
RFC_chk = $time;
end
end
// Extended Mode Register
if (Ext_mode_enable === 1'b1) begin
if (Debug) begin
$display ("At time %t EMR : Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
if (!no_halt) $stop (0);
end else begin
if (Addr[0] === 1'b0) begin
DLL_enable = 1'b1;
if (Debug) begin
$display ("At time %t EMR : Enable DLL", $time);
end
end else begin
DLL_enable = 1'b0;
if (Debug) begin
$display ("At time %t EMR : Disable DLL", $time);
end
end
MRD_chk = $time;
end
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (Debug) begin
$display ("At time %t LMR : Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
end else begin
// Register Mode
Mode_reg = Addr;
// DLL Reset
if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
DLL_reset = 1'b1;
DLL_done = 1'b0;
DLL_count = 0;
end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
$display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
$display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("At time %t LMR : Burst Length = 2", $time);
3'b010 : $display ("At time %t LMR : Burst Length = 4", $time);
3'b011 : $display ("At time %t LMR : Burst Length = 8", $time);
default : $display ("At time %t ERROR: Burst Length not supported", $time);
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("At time %t LMR : CAS Latency = 2", $time);
3'b110 : $display ("At time %t LMR : CAS Latency = 2.5", $time);
3'b011 : $display ("At time %t LMR : CAS Latency = 3", $time);
default : $display ("At time %t ERROR: CAS Latency not supported", $time);
endcase
// Record current tMRD time
MRD_chk = $time;
end
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
end
// Display Debug Message
if (Debug) begin
$display ("At time %t ACT : Bank = %x, Row = %x", $time, Ba, Addr);
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
end
// LMR/EMR to Activate
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
end
// AutoRefresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
if (!no_halt) $stop (0);
end else begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk0 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk0 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $time;
RCD_chk0 = $time;
RAS_chk0 = $time;
RAP_chk0 = $time;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk1 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk1 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $time;
RCD_chk1 = $time;
RAS_chk1 = $time;
RAP_chk1 = $time;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk2 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk2 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $time;
RCD_chk2 = $time;
RAS_chk2 = $time;
RAP_chk2 = $time;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk3 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk3 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $time;
RCD_chk3 = $time;
RAS_chk3 = $time;
RAP_chk3 = $time;
end
// Record variable for checking violation
RRD_chk = $time;
Prev_bank = Ba;
read_precharge_truncation[Ba] = 1'b0;
end
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
end
// LMR/EMR to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Precharge", $time);
end
// AutoRefresh to Precharge
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Precharge", $time);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge Bank
if ($time - RAS_chk0 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk0 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk1 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk2 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk3 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Prech_count is to make sure we have met part of the initialization sequence
Prech_count = Prech_count + 1;
// Pipeline for READ
A10_precharge [cas_latency_x2] = Addr[10];
Bank_precharge[cas_latency_x2] = Ba;
Cmnd_precharge[cas_latency_x2] = 1'b1;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t BST : Burst Terminate",$time);
end
if (Data_in_enable === 1'b1) begin
// Illegal to burst terminate a Write
$display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
if (!no_halt) $stop (0);
end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
// Illegal to burst terminate a Read with Auto Precharge
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
end else begin
// Burst Terminate Command Pipeline for Read
Cmnd_bst[cas_latency_x2] = 1'b1;
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
end
// Check for DLL reset before Read
if (DLL_reset === 1 && DLL_done === 0) begin
$display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
end
// Display Debug Message
if (Debug) begin
$display ("At time %t READ : Bank = %x, Col = %x", $time, Ba, {Addr [11], Addr [9 : 0]});
end
// Terminate a Write
if (Data_in_enable === 1'b1) begin
Data_in_enable = 1'b0;
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Read", $time);
end
// Activate to Read with Auto Precharge
if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
$display ("At time %t ERROR: tRAP violation during Read", $time);
end
// Interrupt a Read with Auto Precharge (same bank only)
if (Read_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Read_precharge [Ba]= 1'b0;
end
end
// Activate to Read
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Read", $time);
if (!no_halt) $stop (0);
end else begin
// CAS Latency pipeline
Read_cmnd[cas_latency_x2] = 1'b1;
Read_bank[cas_latency_x2] = Ba;
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
if (!no_halt) $stop (0);
end
// display debug message
if (Debug) begin
$display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Activate to Write
if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Write to Bank %x", $time, Ba);
end
// Read to Write
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
if (Data_out_enable || read_precharge_truncation) begin
$display("At time %t ERROR: Read to Write violation", $time);
end
end
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Write_precharge [Ba]= 1'b0;
end
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Write", $time);
if (!no_halt) $stop (0);
end else begin
// Pipeline for Write
Write_cmnd [3] = 1'b1;
Write_bank [3] = Ba;
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
end
endtask
task check_neg_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_neg_dqs[i]) begin
$display ("At time %t ERROR: Negative DQS[%1d] transition required.", $time, i);
end
expect_neg_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
task check_pos_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_pos_dqs[i]) begin
$display ("At time %t ERROR: Positive DQS[%1d] transition required.", $time, i);
end
expect_pos_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
// Main Logic
always @ (posedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_neg_dqs;
Auto_Precharge_Calculation;
DLL_Counter;
Control_Logic;
end
always @ (negedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_pos_dqs;
end
// Dqs Receiver
always @ (posedge Dqs_in[0]) begin
// Latch data at posedge Dqs
dq_rise[7 : 0] = Dq_in[7 : 0];
dm_rise[0] = Dm_in[0];
expect_pos_dqs[0] = 0;
end
always @ (posedge Dqs_in[1]) begin
// Latch data at posedge Dqs
dq_rise[15 : 8] = Dq_in[15 : 8];
dm_rise[1] = Dm_in [1];
expect_pos_dqs[1] = 0;
end
always @ (negedge Dqs_in[0]) begin
// Latch data at negedge Dqs
dq_fall[7 : 0] = Dq_in[7 : 0];
dm_fall[0] = Dm_in[0];
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
expect_neg_dqs[0] = 0;
end
always @ (negedge Dqs_in[1]) begin
// Latch data at negedge Dqs
dq_fall[15: 8] = Dq_in[15 : 8];
dm_fall[1] = Dm_in[1];
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
expect_neg_dqs[1] = 0;
end
specify
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5B // specparams for -5B (CL = 3)
specparam tDSS = 1.0; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.0; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.600; // tIH ns Input Hold Time
specparam tIS = 0.600; // tIS ns Input Setup Time
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else
`ifdef sg6 // specparams for -6 (CL = 2.5)
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else
`ifdef sg75E // specparams for -75E (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else
`define sg75Z // specparams for -75Z (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`endif
`endif
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
$setuphold(posedge Clk, Cke, tIS, tIH);
$setuphold(posedge Clk, Cs_n, tIS, tIH);
$setuphold(posedge Clk, Cas_n, tIS, tIH);
$setuphold(posedge Clk, Ras_n, tIS, tIH);
$setuphold(posedge Clk, We_n, tIS, tIH);
$setuphold(posedge Clk, Addr, tIS, tIH);
$setuphold(posedge Clk, Ba, tIS, tIH);
// $setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH);
endspecify
endmodule
ddr_parameters.v 0 → 100644
View file @ 1727b764
/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5B // Timing Parameters for -5B (CL = 3)
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.4; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`else
`ifdef sg6 // Timing Parameters for -6 (CL = 2.5)
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.4; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`else
`ifdef sg75E // Timing Parameters for -75E (CL = 2)
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.5; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`else
`define sg75Z // Timing Parameters for -75Z (CL = 2)
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.5; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
// parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRC = 63.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
parameter tRP = 20.0; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`endif
`endif
// Size Parameters based on Part Width
`ifdef x4
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 12; // Set this parameter to control how many Column bits are used
`else
`ifdef x8
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
`else
`define x16
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
`endif
`endif
parameter full_mem_bits = 25;//2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
// parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
parameter part_mem_bits = 25;//14; // Set this parameter to control how many unique addresses are used
parameter no_halt = 1; // If set to 1, the model won't halt on command sequence/major errors
parameter Debug = 1; // Turn on debug message
glbl.v 0 → 100644
View file @ 1727b764
// $Header: /cvsroot/elphel/elphel353-8.0/fpga/x359/glbl.v,v 1.4 2010/05/14 18:48:35 dzhimiev Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
i2csbr.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** i2csbr.v
**
** Slave 2-wire serial device and a passthrough bridge
**
** Active pullup of SDA line
**
** Copyright (C) 2007 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of x347
** X347 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
** $Log: i2csbr.v,v $
** Revision 1.4 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
** Revision 1.1 2009/06/11 17:39:00 dzhimiev
** new initial version
** 1. simulation and board test availability
**
** Revision 1.1 2008/12/08 09:07:57 dzhimiev
** 1. set up of the data path for the transform
** 2. 2 read and 2 write channels
** 3. in snapshot mode - 3 frames output sequence -
** 1st - direct
** 2nd - stored 'direct' from the 1st buffer
** 3rd - stored '1st buffer' from the 2nd buffer
**
** Revision 1.1.1.1 2007/08/17 11:52:28 elphel
** This is a fresh tree based on elphel353-2.10
**
** Revision 1.6 2007/08/17 11:52:28 spectr_rain
** switch to GPL3 license
**
** Revision 1.5 2007/07/20 09:48:14 spectr_rain
** *** empty log message ***
**
** Revision 1.1 2007/04/04 04:21:25 elphel
** added 10359 fpga files
**
**
*/
`timescale 1 ns / 1 ps
module i2csbr (clk, // global clock (30-150MHz?)
slave_en, // enable slave bus (may be disabled while fast/non-standard communications with master)
scl, // SCL from master
scl_en, // enable sclk output to external slave device
scls, // SCL to external slave device
sdami, // SDA from master input
sdamo, // SDA to master output
sdamen, // SDA to master output enable
sdasi, // SDA from external slave input
sdaso, // SDA to external slave output
sdasen, // SDA to external slave output enable
sr, // 16-bit shift register output (skipped ACKN)
slava_ackn, // will ackn. (using 7 MSBs from sr)
wra_stb, // single-cycle strobe when sr contains register+slave address to read/write
wra_ackn, // acknowledge address (active high input)
wrd_stb, // single-cycle strobe when sr[7:0] contains byte to write (st[16:9] may have previous/MS byte)
wrd_ackn, // acknowledge for the byte/word written
rd_req, // request read byte (ackn from master), strobe after SCL goes high
rdat, // 8-bit data to send to master
rd_stb, // rdat is updated
start, // start strobe (just in case)
stop); // stop strobe (some commands will be triggered now (i.e. connecting/disconnecting bridge to external slave)
input clk;
input slave_en, scl,sdami, sdasi;
output scl_en, scls, sdamo, sdamen, sdaso, sdasen;
output [15:0] sr;
input slava_ackn;
output wra_stb;
input wra_ackn;
output wrd_stb;
input wrd_ackn;
output rd_req;
input [ 7:0] rdat;
input rd_stb;
output start;
output stop;
reg [2:0] sclr; // registered scl
reg [2:0] sdamr; // registered sdami
reg [2:0] sdasr; // registered sdasi
reg sclf; // filtered scl
reg sdamf; // filtered sdami
reg sdasf; // filtered sdasi
reg sclp; // previous scl
reg sdamp; // previous sdami
reg sdasp; // previous sdasi
reg start, start_d, stop;
wire i2c_active;
reg i2c_active_d; //delayed by 1 clock;
reg [15:0] sr;
reg [3:0] bcntr;
reg this_sa; // selected this slave
reg this_ackn; // acknowledge slave_a/address/write_data
// reg wr; // i2c write mode, register address/data, including trailing ACKN bit
// i2c if active can be reading slave address, wra, wrd or rd
// next registers (state of i2c) change on the rising edge of 9-th SCL
reg wrs; // i2c write slave address - including trailing ACKN bit
reg wra; // i2c write register address including trailing ACKN bit
reg wrd; // i2c write data including trailing ACKN bit
reg rd; // i2c read mode including trailing ACKN bit
// these registers switch on the falling edge of SCL delaying wrs, wra, wrd,rd by the duration of SCL=1
reg wrs_d, wra_d, wrd_d, rd_d, wr_d; // wr_d= wrs_d | wra_d | wrd_d
reg acknw; // acknowledge window (from falling SCL to falling SCL)
reg wra_stb;
reg wrd_stb;
reg rd_req;
wire rd_stb;
reg [7:0] rd_sr; // shift register for read data
wire scl_rise= sclf & ~sclp;
wire scl_fall=~sclf & sclp;
reg slave_en_sync; //slave_en synchronized to i2c bus activity (will not turn on/off in the middle of the i2c active cycle
// reg scl_en;
wire sdamo;
wire sdamen;
wire sdaso;
wire sdasen;
wire scl_en;
wire scls;
wire int_slave_do;
wire from_master; // SDA from master
wire from_int; // SDA - from internal slave
wire from_ext; // SDA - from externa slave
// assign from_master= acknw? rd_d: wr_d;
assign from_master= acknw? rd_d: ~rd_d;
assign from_int= this_sa & (acknw? wr_d: rd_d);
assign from_ext= slave_en_sync & ~this_sa & (acknw? wr_d: rd_d);
assign int_slave_do=acknw ? ~this_ackn : rd_sr[7] ;
// can use any of the 2 below (always enable or use sclf)
assign scls= sclf | ~slave_en_sync;
assign scl_en= slave_en_sync;
// let external slave see what internal is sending to the master
assign sdaso= from_master ? sdamf : int_slave_do ;
assign sdasen=slave_en_sync &
~from_ext &
(~sdaso | ~sclp); // active pullup while SCL=0, open-drain when SCL=1 (using sclp so active enabling will not lead the state
assign sdamo = from_int ? int_slave_do : (from_ext ? sdasf:1'b1);
assign sdamen = ~from_master & (~sdamo | ~sclp) ;
// using FD instance to make sure it will be reset at startup both in simulation and hardware
FD i_i2c_active (.Q(i2c_active),.C(clk),.D(start || (i2c_active && !stop)));
always @ (posedge clk) begin
sclr[2:0] <= {scl,sclr[2:1]};
sdamr[2:0] <= {sdami,sdamr[2:1]};
sdasr[2:0] <= {sdasi,sdasr[2:1]};
sclf <= sclf? (sclr [1:0] != 2'h0) : (sclr [1:0] == 2'h3);
sdamf <= sdamf? (sdamr[1:0] != 2'h0) : (sdamr[1:0] == 2'h3);
sdasf <= sdasf? (sdasr[1:0] != 2'h0) : (sdasr[1:0] == 2'h3);
sclp <= sclf;
sdamp <= sdamf;
sdasp <= sdasf;
start <= sclp & sclf & sdamp & ~sdamf; // if sda and scl switch at the same time - no start/stop will be generated
stop <= sclp & sclf & ~sdamp & sdamf;
start_d <= start;
if (scl_rise && !bcntr[3]) sr[15:0] <={sr[14:0],sdamf};
if (!i2c_active || start ) bcntr[3:0] <= 4'h0;
else if (scl_rise) bcntr[3:0] <= bcntr[3]? 4'h0 : (bcntr[3:0]+1);
i2c_active_d <= i2c_active;
if (start || start_d) wrs <= 1'b1;
else if (!i2c_active ||
(scl_rise && bcntr[3])) wrs <= 1'b0;
if (!i2c_active) this_sa <= 1'b0;
else if (scl_fall && bcntr[3] && wrs) this_sa <= slava_ackn;
if (!i2c_active || start) wra <= 1'b0;
else if (scl_rise && bcntr[3] ) wra <= ~sr[0] & wrs & (this_sa | ~sdasf); // one of the slaves should respond
if (!i2c_active || start) rd <= 1'b0;
else if (scl_rise && bcntr[3]) rd <= rd ? (~sdamf): (sr[0] & wrs & (this_sa | ~sdasf)) ;
if (!i2c_active || start) wrd <= 1'b0;
else if (scl_rise && bcntr[3] ) wrd <= this_sa? ((wra | wrd) & this_ackn):(~sdasf & (wra | wrd));
if (scl_fall) this_ackn <= bcntr[3] & ((wrs & slava_ackn) |
(wra & (this_sa & wra_ackn)) |
(wrd & (this_sa & wrd_ackn)));
if (!i2c_active) wrs_d <= 1'b0;
else if (scl_fall) wrs_d <= wrs;
if (!i2c_active) wra_d <= 1'b0;
else if (scl_fall) wra_d <= wra;
if (!i2c_active) wrd_d <= 1'b0;
else if (scl_fall) wrd_d <= wrd;
if (!i2c_active) wr_d <= 1'b0;
else if (scl_fall) wr_d <= wrs | wra | wrd;
if (!i2c_active) rd_d <= 1'b0;
else if (scl_fall) rd_d <= rd;
if (!i2c_active) acknw <= 1'b0;
else if (scl_fall) acknw <= bcntr[3];
wra_stb <= this_sa && scl_rise && bcntr[3] && wra; // last cycle of wra - beginning of SCL pulse after ACKN
wrd_stb <= this_sa && scl_rise && bcntr[3] && wrd; // last cycle(s) of wrd - beginning of SCL pulse after ACKN
if (rd_stb) rd_sr[7:0] <= rdat[7:0];
else if (scl_fall && |bcntr[2:0]) rd_sr[7:0] <= {rd_sr[6:0], 1'b0};
rd_req <= this_sa && scl_rise && bcntr[3] && (rd ? (!sdamf): (wrs && sr[0]));
// make sure slave_en_sync does not turn on/off in the middle of i2c activity
if (!i2c_active) slave_en_sync <= slave_en;
end
endmodule
ioports353.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** ioports353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002-2008 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
`timescale 1 ns / 1 ps
module dmapads (dreq0,dack0,idreq0,idack0,dreq1,dack1,idreq1,idack1);
output dreq0,dreq1;
input dack0,dack1;
input idreq0,idreq1;
output idack0,idack1;
OBUF i_dreq0 (.I(idreq0), .O(dreq0));
IBUF i_dack0 (.I(dack0), .O(idack0));
OBUF i_dreq1 (.I(idreq1), .O(dreq1));
IBUF i_dack1 (.I(dack1), .O(idack1));
endmodule
module i2cpads (sda,scl,sda_o,sda_i,sda_en,scl_o,scl_i,scl_en);
inout sda;
inout scl;
input sda_o;
input sda_en;
output sda_i;
input scl_o;
input scl_en;
output scl_i;
IOBUF i_sda0 (.I(sda_o), .T(!sda_en), .O(sda_i), .IO(sda));
IOBUF i_scl0 (.I(scl_o), .T(!scl_en), .O(scl_i), .IO(scl));
endmodule
module sysinterface(clk,
drv_bus, // drive system bus (to write to system memory)
d, // 32 bit D[31:0] data pads
oe, // OE pad
ce, // CE pad (zero wait states)
ce1, // CE1 pad (EW=1)
we, // WE pad
a, // 13 bit A[12:0] pads
iod, // internal 32-bit data out (FPGA->CPU) bus
// as of v. 03533016 idi[31:16] is valid with da_*, twr_* and one cycle after,
// idi[15:0] is multiplexed: withda_*, twr_*it has di[15:0], next cycle = di[31:16]
idi, // internal 32-bit data in, synchronous to clk
ia, // internal 8-bit address bus (fast - directly from I/O pads)
as, // internal 8-bit address bus (synchronized to clk)
am, // multiplexed addr - switching between ia and as
wnr, // write/not read, sync with clk
da_ctl, // WE to control 32-bit register (1 loc)
da_dmamode, // select writing to dma_cntr/dma_raw (1 loc)
da_sensormode, // select writing to sensorpix (1 loc)
da_virttrig, // write virtual trigger threshold
da_sensortrig, // sensor control: bit0 continuous, bit1 - external, bit2 - enable
da_sensortrig_lines,// write number of lines to be transferred in a frame (or aftre trigger)
da_dswe, // select reading/writing to mcontr (16 locations)
da_init_ch3, // write to init cnhannel 3 (will reset address r/w)
da_next_ch3, // advance to the next channel3 page, reset address
da_mem, // read/write to SDRAM buffer, autoincrement address
// in read mode - needs CE1 to autoincrement!
da_hist, // 0x40..0x43 write/read histogram related data/registers
// 40 - {top, left}
// 41 - {height-1, width-1}
// 42 - hist. data start address (will also read pointed word to output word
// 43 - read histogram (with CE1 to autoincrement)
da_pre_hist, // wire - ahead of da_hist
da_rtc, // 44 - write microseconds (actual write will happen after writing seconds)
// 45 - write seconds
// 46 - write correction (16 bit, signed
// 47 - nop, just latch the output 32+20 bits to read to CPU). Maybe nop (or 2 writes) are needed between read.
da_timestamp, // 48 - write timesatmp mode (0 - off, 1 - normal frames, 1 photo-finish)
da_sens_dc, // write clock divisor for sensor DCDC converter
da_interrupts, // interrupt control 0x1c..0x1f
da_compressor, // 0x0c - 0x0f - will be farther decoded in the compressor module
da_dcm, // tune SDRAM clock
da_saturation, // write color saturation vaues (currently 10 bits
da_framesync_dly,
da_io_pins, // write i/o pins control (for 6 pins to connector J2) - 0x70
da_pio_dmafifo, // increment address of the DMA FIFO(S) (PIO mode should be enabled in the desired channel)
da_xjtag, // write to external (sensor board) JTAG
da_extsync, // control of external sync module 0x78 - 0x7b
da_i2c, // i2c_writeonly control (0x50 - 0x5f)
da_irq_smart, // single IRQ control (0x1a)
ta, // [10:0] table address - will be valid at twr_xx and one cycle beforfe (@ negedge clk)
twr_quant, // write enable to quantization table (@negedge clk - addr and data valid this cycle and one before)
twr_huff, // write enable to huffman table (@negedge clk - addr and data valid this cycle and one before)
twr_gamma, // write enable to "gamma" table (@negedge clk - addr and data valid this cycle and one before)
twr_focus, // write enable to "focus" table (@negedge clk - addr and data valid this cycle and one before)
dcmrst, // (emergency)async DCM reset Seems SE hangs if the frequency changed on the fly
// goe //global clock- OE
ioe // OE after IBUF
);
input clk;
input drv_bus;
inout [31:0] d;
input oe;
input ce;
input ce1;
input we;
inout [12:0] a;
input [31:0] iod;
output [31:0] idi;
output [7:0] ia;
output [7:0] as; // output clock-synchronous address
output [7:0] am;
output wnr;
output [11:0] ta;
output twr_quant;
output twr_huff;
output twr_gamma;
output twr_focus;
output da_ctl; // WE to control 32-bit register (1 loc)
output da_dmamode; // select writing to dma_cntr/dma_raw (1 loc)
output da_sensormode; // select writing to sensorpix (1 loc)
output da_virttrig; // write virtual trigger threshold
output da_sensortrig; // sensor control: bit0 continuous, bit1 - external, bit2 - enable
output da_sensortrig_lines; // write number of lines to be transferred in a frame (or aftre trigger)
output da_dswe; // select reading/writing to mcontr (16 locations)
output da_init_ch3; // write to init cnhannel 3 (will reset address r/w)
output da_next_ch3; // advance to the next channel3 page, reset address
output da_mem; // read/write to SDRAM buffer, autoincrement address
// in read mode - needs CE1 to autoincrement!
output da_sens_dc; // write clock divisor for sensor DCDC converter
output da_interrupts; // interrupt mask
output da_compressor; // 0x0c - 0x0f - will be farther decoded in the compressor module
output da_dcm; // tune SDRAM clock
output da_saturation; // write color saturation vaues (currently 10 bits
output da_hist; // write/read histogram related data/registers
output da_pre_hist;
output da_framesync_dly;
output da_io_pins; // write i/o pins control (for 6 pins to connector J2) - 0x70
output da_rtc;
output da_timestamp; // 48 - write timesatmp mode (0 - off, 1 - normal frames, 1 photo-finish)
output dcmrst; // async
output da_pio_dmafifo; // increment address of the DMA FIFO(S) (PIO mode should be enabled in the desired channel)
output da_xjtag; // write to external (sensor board) JTAG
output da_extsync; // control of external sync module 0x78 - 0x7b
output da_i2c; // i2c_writeonly control (0x50 - 0x5f)
output da_irq_smart; // single IRQ control (0x1a)
// output goe;
output ioe;
reg dcmrst;
wire cwr;
wire iwe;
reg [31:0] idi;
wire t;
wire ioe;
wire ice;
wire ice1;
wire irnw;
reg [ 7:0] a0; // sampled at posedge of oe/wr
wire [ 7:0] ial; // sampled at posedge of oe/wr
reg wnr0, wnr;
wire [31:0] id0;
reg [ 7:0] as; // output clock-synchronous address
reg da_ctl0, da_ctl; // WE to control 32-bit register (1 loc)
reg da_dmamode0, da_dmamode; // select writing to dma_cntr/dma_raw (1 loc)
reg da_sensormode0, da_sensormode; // select writing to sensorpix (1 loc)
reg da_virttrig0, da_virttrig; // write virtual trigger threshold
reg da_sensortrig0, da_sensortrig; // sensor control: bit0 continuous, bit1 - external, bit2 - enable
reg da_sensortrig_lines0,da_sensortrig_lines; // write number of lines to be transferred in a frame (or aftre trigger)
reg da_dswe0, da_dswe; // select reading/writing to mcontr (16 locations)
reg da_init_ch30, da_init_ch3; // write to init cnhannel 3 (will reset address r/w)
reg da_next_ch30, da_next_ch3; // advance to the next channel3 page, reset address
reg da_mem0, da_mem; // read/write to SDRAM buffer, autoincrement address
reg da_sens_dc0, da_sens_dc; // write clock divisor for sensor DCDC converter
reg da_interrupts0, da_interrupts; // interrupt mask
reg da_compressor0, da_compressor; // 0x0c - 0x0f - will be farther decoded in the compressor module
reg da_dcm0, da_dcm; // tune SDRAM clock phase
reg da_table_a0, da_table_a; // write table address (internal)
reg da_saturation0, da_saturation; // write color saturation values
reg da_hist0, da_hist; // write/read histogram related data/registers
reg da_framesync_dly0, da_framesync_dly;
reg da_io_pins0, da_io_pins; // write i/o pins control (for 6 pins to connector J2) - 0x70
reg da_rtc0, da_rtc;
reg da_timestamp0, da_timestamp;
reg da_pio_dmafifo0, da_pio_dmafifo; // increment address of the DMA FIFO(S) (PIO mode should be enabled in the desired channel)
reg da_xjtag0, da_xjtag; // write to external (sensor board) JTAG
reg da_extsync0, da_extsync; // control of external sync module 0x78 - 0x7b
reg da_i2c0, da_i2c; // i2c_writeonly control (0x50 - 0x5f)
reg da_irq_smart0, da_irq_smart; // single IRQ control (0x1a)
reg twr0, twr; // write table data (address will be incremented 1 cycle after
// reg inc_ta;
reg [11:0] pre_ta; // one cycle ahead of ta
reg [11:0] ta; // table address. valid with twr_* and 1 cycle after
reg twr_quant;
reg twr_huff;
reg twr_gamma;
reg twr_focus;
wire [7:0] am;
reg wra; // to select source of as - for 2 cycles during sync write will use as, else - ia;
// inter-clock synchronization
wire sync0, sync1, sync2, sync3;
wire da_pre_hist;
assign am[7:0]=wra?as[7:0]:ia[7:0];
assign da_pre_hist = sync2 && da_hist0;
IBUF i_oe (.I(oe), .O(ioe ));
IBUF i_ce (.I(ce), .O(ice ));
IBUF i_ce1 (.I(ce1), .O(ice1));
ipadql i_we (.g(cwr),.q(iwe),.qr(irnw),.d(we));
// negative pulse - with CE (zero w.s.) - only with WE, with CE1 (EW=1) - both WE and OE
BUFG i_cwr (.I((ice | iwe) & (ice1 | (iwe & ioe))), .O(cwr));
wire [12:0] ao=13'b0;
bpadql i_a0 (.g(cwr),.q(ia[ 0]),.qr(ial[ 0]),.io(a[ 0]),.t(!drv_bus),.d(ao[ 0]));
bpadql i_a1 (.g(cwr),.q(ia[ 1]),.qr(ial[ 1]),.io(a[ 1]),.t(!drv_bus),.d(ao[ 1]));
bpadql i_a2 (.g(cwr),.q(ia[ 2]),.qr(ial[ 2]),.io(a[ 2]),.t(!drv_bus),.d(ao[ 2]));
bpadql i_a3 (.g(cwr),.q(ia[ 3]),.qr(ial[ 3]),.io(a[ 3]),.t(!drv_bus),.d(ao[ 3]));
bpadql i_a4 (.g(cwr),.q(ia[ 4]),.qr(ial[ 4]),.io(a[ 4]),.t(!drv_bus),.d(ao[ 4]));
bpadql i_a5 (.g(cwr),.q(ia[ 5]),.qr(ial[ 5]),.io(a[ 5]),.t(!drv_bus),.d(ao[ 5]));
bpadql i_a6 (.g(cwr),.q(ia[ 6]),.qr(ial[ 6]),.io(a[ 6]),.t(!drv_bus),.d(ao[ 6]));
bpadql i_a7 (.g(cwr),.q(ia[ 7]),.qr(ial[ 7]),.io(a[ 7]),.t(!drv_bus),.d(ao[ 7]));
bpadql i_a8 (.g(cwr),.q(), .qr(), .io(a[ 8]),.t(!drv_bus),.d(ao[ 8]));
bpadql i_a9 (.g(cwr),.q(), .qr(), .io(a[ 9]),.t(!drv_bus),.d(ao[ 9]));
bpadql i_a10(.g(cwr),.q(), .qr(), .io(a[10]),.t(!drv_bus),.d(ao[10]));
bpadql i_a11(.g(cwr),.q(), .qr(), .io(a[11]),.t(!drv_bus),.d(ao[11]));
bpadql i_a12(.g(cwr),.q(), .qr(), .io(a[12]),.t(!drv_bus),.d(ao[12]));
// these signals will be valid after the end of the CPU r/w cycle
always @ (posedge cwr) begin
a0[7:0]<=ial[7:0]; // may want to change to just ia if ia will be late enough;
wnr0 <=~irnw;
da_ctl0 <= (ial[7:0]==8'h00); // 0x00 WE to control 32-bit register (1 loc)
da_dmamode0 <= (ial[7:0]==8'h01); // 0x01 select writing to dma_cntr/dma_raw (1 loc)
da_sensormode0 <= (ial[7:0]==8'h02); // 0x02 select writing to sensorpix (1 loc)
da_virttrig0 <= (ial[7:0]==8'h03); // 0x03 write virtual trigger threshold
da_sensortrig0 <= (ial[7:0]==8'h04); // 0x04 select writing to sensorpix (1 loc)
da_sensortrig_lines0<= (ial[7:0]==8'h05); // 0x05 write number of lines to be transferred in a frame (or aftre trigger)
da_dswe0 <= (ial[7:4]==4'h2 ); // 0x2x select reading/writing to mcontr (16 locations)
da_init_ch30 <= (ial[7:0]==8'h2c); // 0x2c write to init cnhannel 3 (will reset address r/w)
da_next_ch30 <= (ial[7:0]==8'h2f); // 0x2f advance to the next channel3 page, reset address
da_mem0 <= (ial[7:0]==8'h30); // 0x30 read/write to SDRAM buffer, autoincrement address
da_sens_dc0 <= (ial[7:0]==8'h07); // 0x07 write to sensor DCDC converter frequency divider
// da_interrupts0 <= (ial[7:0]==8'h06); // interrupt mask
//assign dcmrst=!iwe && !ice &&(ia[7:0]==8'h1b);//0x1b async signal to restart DCMs
dcmrst <= ~irnw && (ial[7:0]==8'h1b); // 0x1b async signal to restart DCMs
da_interrupts0 <= (ial[7:2]==6'h07); // 0x1c..0x1f interrup control
da_compressor0 <= (ial[7:1]==7'h06); // 0x0c..0x0d - will be farther decoded in the compressor module
da_table_a0 <= (ial[7:0]==8'h0e); // 0x0e - write tables address
twr0 <= (ial[7:0]==8'h0f); // 0x0f - write tables data
da_dcm0 <= (ial[7:0]==8'h08); // 0x08 tune SDRAM clock phase
da_saturation0 <= (ial[7:0]==8'h09); // 0x09 write color saturation values
da_hist0 <= (ial[7:2]==6'h10); // 0x40..0x43write/read histogram related data/registers
da_framesync_dly0 <= (ial[7:0]==8'h0a); // 0x0a write frame sync interrupt delay (in scan lines)
da_io_pins0 <= (ial[7:0]==8'h70); // 0x70 write i/o pins control (for 6 pins to connector J2) - 0x70
da_rtc0 <= (ial[7:2]==6'h11); // 0x44..0x47
da_timestamp0 <= (ial[7:0]==8'h48); // 0x48 write timestamp mode
da_pio_dmafifo0 <= irnw && (ial[7:4]==4'h0); // 0x0..0x0f, read
da_xjtag0 <= (ial[7:0]==8'h74); // write to external (sensor board) JTAG
da_extsync0 <= (ial[7:2]==6'h1e); // control of external sync module 0x78 - 0x7b
da_i2c0 <= (ial[7:4]==4'h5); // control of external sync module 0x50 - 0x5f
da_irq_smart0 <= (ial[7:0]==8'h1a); // single IRQ control (0x1a)
//da_rtc
end
// assign dcmrst=!iwe && !ice && (ia[7:0]==8'h1b); //0x1b async signal to restart DCMs
// inter-clock synchronization
FDCE i_sync0 (.Q(sync0),.C(cwr),.CE(1'b1),.CLR(sync2),.D(1'b1));
FD_1 i_sync1 (.Q(sync1),.C(clk),.D(sync0 && ! sync1));
FD i_sync2 (.Q(sync2),.C(clk),.D(sync1));
FD_1 i_sync3 (.Q(sync3),.C(clk),.D(sync2));
always @ (negedge clk) if (!sync3) begin // could use sync2, but let's leave room for duplication of sync3
as[7:0] <= a0[7:0];
wnr <= wnr0;
// idi[31:0] <= id0[31:0];
wra <= sync2 && wnr0;
end
always @ (negedge clk) begin
idi[31:0] <= sync3?{idi[31:16],idi[31:16]}:id0[31:0];
da_ctl <= sync2 && da_ctl0;
da_dmamode <= sync2 && da_dmamode0;
da_sensormode <= sync2 && da_sensormode0;
da_virttrig <= sync2 && da_virttrig0;
da_sensortrig <= sync2 && da_sensortrig0;
da_sensortrig_lines<= sync2 && da_sensortrig_lines0;
da_dswe <= sync2 && da_dswe0;
da_init_ch3 <= sync2 && da_init_ch30;
da_next_ch3 <= sync2 && da_next_ch30;
da_mem <= sync2 && da_mem0;
da_sens_dc <= sync2 && da_sens_dc0;
da_interrupts <= sync2 && da_interrupts0;
da_compressor <= sync2 && da_compressor0;
da_dcm <= sync2 && da_dcm0;
da_saturation <= sync2 && da_saturation0;
twr <= sync2 && twr0;
da_table_a <= sync2 && da_table_a0;
da_framesync_dly <= sync2 && da_framesync_dly0;
da_io_pins <= sync2 && da_io_pins0;
if (da_table_a) pre_ta[11:0]<= idi[11:0];
else if (twr) pre_ta[11:0]<= pre_ta[11:0]+1;
ta[11:0] <= pre_ta[11:0];
twr_quant <= sync2 && twr0 && (pre_ta[11: 9] ==3'h0);
twr_huff <= sync2 && twr0 && (pre_ta[11: 9] ==3'h1);
twr_gamma <= sync2 && twr0 && (pre_ta[11:10] ==2'h1); // 3'h2..3'h3
twr_focus <= sync2 && twr0 && (pre_ta[11:10] ==2'h2); // 3'h4..3'h5
da_hist <= sync2 && da_hist0;
da_rtc <= sync2 && da_rtc0;
da_timestamp <= sync2 && da_timestamp0;
da_pio_dmafifo <= sync2 && da_pio_dmafifo0;
da_xjtag <= sync2 && da_xjtag0;
da_extsync <= sync2 && da_extsync0;
da_i2c <= sync2 && da_i2c0;
da_irq_smart <= sync2 && da_irq_smart0;
end
// assign t= ((ice & ice1) | ioe) & iinta;
// assign t= ioe?iinta:(iinta & ice & ice1);
// MUXF6 i_dataouten ( .I0(iinta & ice & ice1), .I1(iinta), .S(ioe), .O(t));
// LUT4 i_dataouten ( .I0(iinta), .I1(ice1), .I2(ice), .I3(ioe), .O(t));
LUT4 i_dataouten ( .I0(1'b1), .I1(ice1), .I2(ice), .I3(ioe), .O(t));
//synthesis translate_off
defparam i_dataouten.INIT = 16'hAA80;
//synthesis translate_on
//synthesis attribute INIT of i_dataouten is "AA80"
dpads32 i_dmapads32(.c(cwr),.t(t),.d(iod[31:0]),.q(id0[31:0]),.dq(d[31:0]));
endmodule
module dpads32(c,t,d,q,dq);
input c,t;
input [31:0] d;
output [31:0] q;
inout [31:0] dq;
wire t0, t1;
// synthesis attribute KEEP_HIERARCHY of i_t0 is true
// synthesis attribute KEEP_HIERARCHY of i_t1 is true
BUF i_t0 (.I(t), .O(t0));
BUF i_t1 (.I(t), .O(t1));
dio1 i_d0 (.c(c),.t(t0),.d(d[ 0]),.q(q[ 0]),.dq(dq[ 0]));
dio1 i_d1 (.c(c),.t(t0),.d(d[ 1]),.q(q[ 1]),.dq(dq[ 1]));
dio1 i_d2 (.c(c),.t(t0),.d(d[ 2]),.q(q[ 2]),.dq(dq[ 2]));
dio1 i_d3 (.c(c),.t(t0),.d(d[ 3]),.q(q[ 3]),.dq(dq[ 3]));
dio1 i_d4 (.c(c),.t(t0),.d(d[ 4]),.q(q[ 4]),.dq(dq[ 4]));
dio1 i_d5 (.c(c),.t(t0),.d(d[ 5]),.q(q[ 5]),.dq(dq[ 5]));
dio1 i_d6 (.c(c),.t(t0),.d(d[ 6]),.q(q[ 6]),.dq(dq[ 6]));
dio1 i_d7 (.c(c),.t(t0),.d(d[ 7]),.q(q[ 7]),.dq(dq[ 7]));
dio1 i_d8 (.c(c),.t(t0),.d(d[ 8]),.q(q[ 8]),.dq(dq[ 8]));
dio1 i_d9 (.c(c),.t(t0),.d(d[ 9]),.q(q[ 9]),.dq(dq[ 9]));
dio1 i_d10 (.c(c),.t(t1),.d(d[10]),.q(q[10]),.dq(dq[10]));
dio1 i_d11 (.c(c),.t(t1),.d(d[11]),.q(q[11]),.dq(dq[11]));
dio1 i_d12 (.c(c),.t(t1),.d(d[12]),.q(q[12]),.dq(dq[12]));
dio1 i_d13 (.c(c),.t(t1),.d(d[13]),.q(q[13]),.dq(dq[13]));
dio1 i_d14 (.c(c),.t(t1),.d(d[14]),.q(q[14]),.dq(dq[14]));
dio1 i_d15 (.c(c),.t(t1),.d(d[15]),.q(q[15]),.dq(dq[15]));
dio1 i_d16 (.c(c),.t(t1),.d(d[16]),.q(q[16]),.dq(dq[16]));
dio1 i_d17 (.c(c),.t(t0),.d(d[17]),.q(q[17]),.dq(dq[17]));
dio1 i_d18 (.c(c),.t(t1),.d(d[18]),.q(q[18]),.dq(dq[18]));
dio1 i_d19 (.c(c),.t(t1),.d(d[19]),.q(q[19]),.dq(dq[19]));
dio1 i_d20 (.c(c),.t(t1),.d(d[20]),.q(q[20]),.dq(dq[20]));
dio1 i_d21 (.c(c),.t(t1),.d(d[21]),.q(q[21]),.dq(dq[21]));
dio1 i_d22 (.c(c),.t(t0),.d(d[22]),.q(q[22]),.dq(dq[22]));
dio1 i_d23 (.c(c),.t(t1),.d(d[23]),.q(q[23]),.dq(dq[23]));
dio1 i_d24 (.c(c),.t(t0),.d(d[24]),.q(q[24]),.dq(dq[24]));
dio1 i_d25 (.c(c),.t(t1),.d(d[25]),.q(q[25]),.dq(dq[25]));
dio1 i_d26 (.c(c),.t(t0),.d(d[26]),.q(q[26]),.dq(dq[26]));
dio1 i_d27 (.c(c),.t(t0),.d(d[27]),.q(q[27]),.dq(dq[27]));
dio1 i_d28 (.c(c),.t(t0),.d(d[28]),.q(q[28]),.dq(dq[28]));
dio1 i_d29 (.c(c),.t(t0),.d(d[29]),.q(q[29]),.dq(dq[29]));
dio1 i_d30 (.c(c),.t(t1),.d(d[30]),.q(q[30]),.dq(dq[30]));
dio1 i_d31 (.c(c),.t(t1),.d(d[31]),.q(q[31]),.dq(dq[31]));
endmodule
module sddrio16(c0,/*c90,*/c270,d,t,q,dq); //added an extra FF for the t signal
input c0,/*c90,*/c270;
input [31:0] d;
input t;
output [31:0] q;
inout [15:0] dq;
wire [31:0] q;
sddrio0 i_dq0 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[16],d[ 0]}),.t(t),.q({q[16],q[ 0]}),.dq(dq[ 0]));
sddrio0 i_dq1 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[17],d[ 1]}),.t(t),.q({q[17],q[ 1]}),.dq(dq[ 1]));
sddrio0 i_dq2 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[18],d[ 2]}),.t(t),.q({q[18],q[ 2]}),.dq(dq[ 2]));
sddrio0 i_dq3 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[19],d[ 3]}),.t(t),.q({q[19],q[ 3]}),.dq(dq[ 3]));
sddrio0 i_dq4 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[20],d[ 4]}),.t(t),.q({q[20],q[ 4]}),.dq(dq[ 4]));
sddrio0 i_dq5 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[21],d[ 5]}),.t(t),.q({q[21],q[ 5]}),.dq(dq[ 5]));
sddrio0 i_dq6 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[22],d[ 6]}),.t(t),.q({q[22],q[ 6]}),.dq(dq[ 6]));
sddrio0 i_dq7 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[23],d[ 7]}),.t(t),.q({q[23],q[ 7]}),.dq(dq[ 7]));
sddrio0 i_dq8 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[24],d[ 8]}),.t(t),.q({q[24],q[ 8]}),.dq(dq[ 8]));
sddrio0 i_dq9 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[25],d[ 9]}),.t(t),.q({q[25],q[ 9]}),.dq(dq[ 9]));
sddrio0 i_dq10 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[26],d[10]}),.t(t),.q({q[26],q[10]}),.dq(dq[10]));
sddrio0 i_dq11 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[27],d[11]}),.t(t),.q({q[27],q[11]}),.dq(dq[11]));
sddrio0 i_dq12 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[28],d[12]}),.t(t),.q({q[28],q[12]}),.dq(dq[12]));
sddrio0 i_dq13 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[29],d[13]}),.t(t),.q({q[29],q[13]}),.dq(dq[13]));
sddrio0 i_dq14 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[30],d[14]}),.t(t),.q({q[30],q[14]}),.dq(dq[14]));
sddrio0 i_dq15 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[31],d[15]}),.t(t),.q({q[31],q[15]}),.dq(dq[15]));
// synthesis attribute KEEP_HIERARCHY of i_dq0 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq1 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq2 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq3 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq4 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq5 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq6 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq7 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq8 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq9 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq10 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq11 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq12 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq13 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq14 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_dq15 is "TRUE"
endmodule
// Made for CL=2.5
// all data to write is expected to be sync to posedge of c0 - phase=0,
// data to sdram is clocked at c270 (LSW) and c90 (MSW)
// MSB will be delayed by half-cycle internally
// tristate will be clocked at rising edge of c270
// All data read will be also sync to rising edge of c0 (LSB will be delayed internally)
module sddrio0(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 falling edge is before rising, gets LSB
input c0,/*c90,*/c270;
input [1:0] d;
input t;
output [1:0] q;
inout dq;
wire dr,t0,t1,tr,qp,q00,d1d;
wire [1:0] d0;
FD i_d00 (.C(c0), .D(d[0]), .Q(d0[0])); //regular FF, not IOB
FD i_d01 (.C(c0), .D(d[1]), .Q(d0[1])); //regular FF, not IOB
FD i_d1d (.C(c270),.D(d0[1]),.Q(d1d)); //regular FF, not IOB
FD_1 i_q0 (.C(c0),.D(q00),.Q(q[0])); //regular FF, not IOB
IOBUF i_dq (.I(dr), .T(tr),.O(qp), .IO(dq));
FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(!c270),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FD_1 i_t0 (.C(c0), .D(t), .Q(t0));
FD i_t1 (.C(c0), .D(t0), .Q(t1));
FD i_tr (.C(c270), .D(t1), .Q(tr));
IDDR2 i_qq(.Q0(q00),.Q1(q[1]),.C0(c0),.C1(!c0),.CE(1'b1), .D(qp), .R(1'b0), .S(1'b0) );
// synthesis translate_off
defparam i_t0.INIT = 1'b1;
defparam i_t1.INIT = 1'b1;
defparam i_tr.INIT = 1'b1;
// synthesis translate_on
// synthesis attribute INIT of i_t0 is "1"
// synthesis attribute INIT of i_t1 is "1"
// synthesis attribute INIT of i_tr is "1"
// synthesis attribute IOB of i_dr is "TRUE"
// synthesis attribute IOB of i_tr is "TRUE"
// synthesis attribute NODELAY of i_dq is "TRUE"
endmodule
module dqs2 (c0,/*c90,*/c270,
t, // 1.5 cycles before cmd "write" sent out to the SDRAM, sync to sclk180
UDQS, // UDQS I/O pin
LDQS, // LDQS I/O pin
udqsr90, // data from SDRAM interface pin UDQS strobed at rising sclk90
ldqsr90, // data from SDRAM interface pin LDQS strobed at rising sclk90
udqsr270, // data from SDRAM interface pin UDQS strobed at rising sclk270
ldqsr270 // data from SDRAM interface pin UDQS strobed at rising sclk270
);
input c0,/*c90,*/c270,t;
inout UDQS, LDQS;
output udqsr90,ldqsr90,udqsr270,ldqsr270;
wire t0,t1,t2,tr;
FD_1 i_t0 (.C(c0),.D(t),.Q(t0));
FD i_t1 (.C(c0),.D(t0),.Q(t1));
FD i_t2 (.C(c270),.D(t0),.Q(t2));
// FDDRCPE i_tr (.Q(tr),.C0(c0),.C1(c270),.D0(t),.D1(t | t0),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
// FDDRCPE i_tr (.Q(tr),.C0(c0),.C1(c270),.D0(t0),.D1(t0 | t1),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
// assign tr= t1 || t2; // ************** try this later if delays will be too high ***********************
assign tr= t1;
dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
// synthesis translate_off
defparam i_t0.INIT = 1'b1;
defparam i_t1.INIT = 1'b1;
defparam i_t2.INIT = 1'b1;
// synthesis translate_on
// synthesis attribute INIT of i_t0 is "1"
// synthesis attribute INIT of i_t1 is "1"
// synthesis attribute INIT of i_t2 is "1"
// synthesis attribute KEEP_HIERARCHY of i_t0 is "TRUE"
// synthesis attribute KEEP_HIERARCHY of i_tr is "TRUE"
endmodule
module dqs2_0(c0,/*c90,*/c270,t,q,dq);
input c0,/*c90,*/c270;
input t;
output [1:0] q;
inout dq;
wire qp;
wire virtc0; // sync to c0
IOBUF i_dq (.I(virtc0), .T(t),.O(qp), .IO(dq));
// reset DQS when tristated
FDDRCPE i_dr (.Q(virtc0),.C0(c0),.C1(!c0),.D0(1'b1),.D1(1'b0),.CE(1'b1),.CLR(t),.PRE(1'b0));
// as in IFDDRCPE.v
// FDCPE i_q0 (.C(c90), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
FDCPE_1 i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
defparam i_q0.INIT = 1'b0;
FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1]));
// defparam i_q1.INIT = 1'b0;
// synthesis attribute IOB of i_q0 is "TRUE"
// synthesis attribute IOB of i_q1 is "TRUE"
// synthesis attribute FAST of i_dq is "TRUE"
// synthesis attribute NODELAY of i_dq is "TRUE"
endmodule
//both bits are strobed at rising c270
module sddrdm(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270;
input [1:0] d;
inout dq;
sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq));
// synthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule
module sddrdm0(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270;
input [1:0] d;
output dq;
wire dr,d1d;
wire [1:0] d0;
OBUF i_dq (.I(dr), .O(dq));
// FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(c90),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(!c270),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FD i_d00(.C(c0),.D(d[0]),.Q(d0[0])); //regular FF, not IOB
FD i_d01(.C(c0),.D(d[1]),.Q(d0[1])); //regular FF, not IOB
FD i_d1d(.C(c270),.D(d0[1]),.Q(d1d)); //regular FF, not IOB
// synthesis attribute IOB of i_dr is "TRUE"
// synthesis attribute NODELAY of i_dq is "TRUE"
endmodule
// SDRAM address and ras/cas/we
module sdo15_2(c,d,q); // inputs at rising edge, resyncs to falling edge, all go high at reset
input c;
input [14:0] d;
output [14:0] q;
sdo1_2 i_q0 (.c(c),.d(d[ 0]),.q(q[ 0]));
sdo1_2 i_q1 (.c(c),.d(d[ 1]),.q(q[ 1]));
sdo1_2 i_q2 (.c(c),.d(d[ 2]),.q(q[ 2]));
sdo1_2 i_q3 (.c(c),.d(d[ 3]),.q(q[ 3]));
sdo1_2 i_q4 (.c(c),.d(d[ 4]),.q(q[ 4]));
sdo1_2 i_q5 (.c(c),.d(d[ 5]),.q(q[ 5]));
sdo1_2 i_q6 (.c(c),.d(d[ 6]),.q(q[ 6]));
sdo1_2 i_q7 (.c(c),.d(d[ 7]),.q(q[ 7]));
sdo1_2 i_q8 (.c(c),.d(d[ 8]),.q(q[ 8]));
sdo1_2 i_q9 (.c(c),.d(d[ 9]),.q(q[ 9]));
sdo1_2 i_q10 (.c(c),.d(d[10]),.q(q[10]));
sdo1_2 i_q11 (.c(c),.d(d[11]),.q(q[11]));
sdo1_2 i_q12 (.c(c),.d(d[12]),.q(q[12]));
sdo1_2 i_q13 (.c(c),.d(d[13]),.q(q[13]));
sdo1_2 i_q14 (.c(c),.d(d[14]),.q(q[14]));
endmodule
module sdo1_2(c,d,q); // input at rising edge, resyncs to falling
input c;
input d;
output q;
sdo0_2 i_q (.c(c),.d(d),.q(q));
// synthesis attribute KEEP_HIERARCHY of i_q is "TRUE"
endmodule
module sdo0_2(c,d,q); // input at rising edge, resyncs to falling, initializes to "1"
input c;
input d;
output q;
wire d0, dr;
OBUF i_q (.I(dr), .O(q));
FD i_d0 (.C(c), .D(d), .Q(d0));
//FD_1 i_dr (.C(c), .D(d), .Q(dr));
FD_1 i_dr (.C(c), .D(d0), .Q(dr));
//synthesis translate_off
defparam i_dr.INIT = 1'b1;
//synthesis translate_on
//synthesis attribute INIT of i_dr is "1"
// synthesis attribute IOB of i_dr is "TRUE"
//synthesis attribute INIT of i_d0 is "1"
endmodule
module ipadql(g,q,qr,d); //
input g;
output q;
output qr;
input d;
ipadql0 i_q (.g(g),.q(q),.qr(qr),.d(d));
// synthesis attribute KEEP_HIERARCHY of i_q is "TRUE"
endmodule
module ipadql0(g,q,qr,d);
input g;
output q;
output qr;
input d;
IBUF i_q (.I(d), .O(q));
LD i_qr (.G(g), .D(q), .Q(qr));
// synthesis attribute IOB of i_qr is "TRUE"
// synthesis attribute NODELAY of i_q is "TRUE"
endmodule
module bpadql(g,q,qr,io,t,d); //
input g;
output q;
output qr;
inout io;
input t;
input d;
bpadql0 i_q (.g(g),.q(q),.qr(qr),.io(io),.t(t),.d(d));
// synthesis attribute KEEP_HIERARCHY of i_q is "TRUE"
endmodule
module bpadql0(g,q,qr,io,t,d);
input g;
output q;
output qr;
inout io;
input t;
input d;
IOBUF i_q (.I(d), .T(t),.O(q), .IO(io));
LD i_qr (.G(g), .D(q), .Q(qr));
// synthesis attribute IOB of i_qr is "TRUE"
// synthesis attribute NODELAY of i_q is "TRUE"
endmodule
module dio1(c,t,d,q,dq);
input c;
input t;
input d;
output q;
inout dq;
dio0 i_dq (.c(c),.t(t),.d(d),.q(q),.dq(dq));
// synthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule
module dio0(c,t,d,q,dq);
input c;
input t;
input d;
output q;
inout dq;
wire q0;
IOBUF i_dq (.I(d), .T(t),.O(q0), .IO(dq));
FD i_q (.C(c), .D(q0), .Q(q));
// synthesis attribute IOB of i_q is "TRUE"
// synthesis attribute NODELAY of i_dq is "TRUE"
endmodule
macros353.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** macros353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// just make more convenient A[3:0] instead of 4 one-bit inputs
`timescale 1 ns / 1 ps
module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
parameter DATA_WIDTH=16;
parameter DATA_DEPTH=4;
parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
input [DATA_WIDTH-1:0] D;
input WE,clk;
input [DATA_DEPTH-1:0] AW;
input [DATA_DEPTH-1:0] AR;
output [DATA_WIDTH-1:0] QW;
output [DATA_WIDTH-1:0] QR;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
always @ (posedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module MSRL16_1 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
SRL16_1 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
endmodule
/*
module MSRLC16E_1 (Q, Q15, A, CLK, CE, D);
output Q,Q15;
input [3:0] A;
input CLK,CE, D;
SRLC16E_1 i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
endmodule
*/
module MSRL16 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
SRL16 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
endmodule
module MSRLC16E (Q, Q15, A, CLK, CE, D);
output Q,Q15;
input [3:0] A;
input CLK,CE, D;
SRLC16E i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
endmodule
module MSRLC16E_1 (Q, Q15, A, CLK, CE, D);
output Q,Q15;
input [3:0] A;
input CLK,CE, D;
SRLC16E_1 i_q(.Q(Q),.Q15(Q15), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .CE(CE), .D(D));
endmodule
/*
module RAM32X12D_1 (DPO,SPO,A,D,DPRA,WCLK,WE);
input [4:0] A; // Port A address[4:0] input bit
input [4:0] DPRA; // Port B address[4:0] input bit
input [11:0] D; // Port A data input [11:0]
input WCLK; // Port A clock (negedge write)
input WE; // Port A write enable input
output [11:0] DPO; // Port A 12-bit data output
output [11:0] SPO; // Port B 12-bit data output
RAM32X1D_1 i0 (.DPO(DPO[ 0]),.SPO(SPO[ 0]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 0]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i1 (.DPO(DPO[ 1]),.SPO(SPO[ 1]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 1]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i2 (.DPO(DPO[ 2]),.SPO(SPO[ 2]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 2]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i3 (.DPO(DPO[ 3]),.SPO(SPO[ 3]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 3]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i4 (.DPO(DPO[ 4]),.SPO(SPO[ 4]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 4]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i5 (.DPO(DPO[ 5]),.SPO(SPO[ 5]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 5]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i6 (.DPO(DPO[ 6]),.SPO(SPO[ 6]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 6]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i7 (.DPO(DPO[ 7]),.SPO(SPO[ 7]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 7]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i8 (.DPO(DPO[ 8]),.SPO(SPO[ 8]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 8]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i9 (.DPO(DPO[ 9]),.SPO(SPO[ 9]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[ 9]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i10(.DPO(DPO[10]),.SPO(SPO[10]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[10]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
RAM32X1D_1 i11(.DPO(DPO[11]),.SPO(SPO[11]),.A0(A[0]),.A1(A[1]),.A2(A[2]),.A3(A[3]),.A4(A[4]),.D(D[11]),
.DPRA0(DPRA[0]),.DPRA1(DPRA[1]),.DPRA2(DPRA[2]),.DPRA3(DPRA[3]),.DPRA4(DPRA[4]),.WCLK(WCLK),.WE(WE));
endmodule
*/
module RAM16XnnD (D,WE,CLK,AW,AR,QW,QR);
parameter w=16;
input [w-1:0] D;
input WE,CLK;
input [ 3:0] AW;
input [ 3:0] AR;
output [w-1:0] QW;
output [w-1:0] QR;
reg [w-1:0] ram [0:15];
always @ (posedge CLK) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module RAM16XnnD_1 (D,WE,CLK,AW,AR,QW,QR);
parameter w=16;
input [w-1:0] D;
input WE,CLK;
input [ 3:0] AW;
input [ 3:0] AR;
output [w-1:0] QW;
output [w-1:0] QR;
reg [w-1:0] ram [0:15];
always @ (negedge CLK) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module RAM32XnnD (D,WE,CLK,AW,AR,QW,QR);
parameter w=16;
input [w-1:0] D;
input WE,CLK;
input [ 4:0] AW;
input [ 4:0] AR;
output [w-1:0] QW;
output [w-1:0] QR;
reg [w-1:0] ram [0:31];
always @ (posedge CLK) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module RAM32XnnD_1 (D,WE,CLK,AW,AR,QW,QR);
parameter w=16;
input [w-1:0] D;
input WE,CLK;
input [ 4:0] AW;
input [ 4:0] AR;
output [w-1:0] QW;
output [w-1:0] QR;
reg [w-1:0] ram [0:31];
always @ (negedge CLK) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module SRPL (D,SDO,SDI,CLK,EN,LD);
parameter w=16;
input [w-1:0] D;
input EN,CLK, LD, SDI;
output SDO;
reg [w-1:0] r;
always @ (posedge CLK)
if (LD) r <= D;
else if (EN) r <= {SDI,r[w-1:1]};
assign SDO=r[0];
endmodule
module SRPL_1 (D,SDO,SDI,CLK,EN,LD);
parameter w=16;
input [w-1:0] D;
input EN,CLK, LD, SDI;
output SDO;
reg [w-1:0] r;
always @ (negedge CLK)
if (LD) r <= D;
else if (EN) r <= {SDI,r[w-1:1]};
assign SDO=r[0];
endmodule
mcontr359.v 0 → 100755
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : mcontr359.v
*! DESCRIPTION: memory controller block
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: mcontr359.v,v $
*! Revision 1.8 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:11:54 dzhimiev
*! 0. based on theora's mcontr_8chn.v, mcontr_line512_wr.v, mcontr_line512_rd.v
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
/*
To improve timing all SDRAM conrol signals will be generated 2 cycles ahead of the outputs.
will be registered twice - first where the signals from several controllers will come together,
second - in the I/O FFs
mwr will write parameters, initialize running variables. These variables will be also updated after
being used.
There will be 3 types of write operations:
1 - intensity - write two 32-bit words (for each index) into the same page (open page once)
2 - intensity - write two 32-bit words (for each index) into different pages - different banks, make overlap
3 - color. Write two 32-bit words - each in it's own page
Two types of read operations (may be truncated between planes/frames)
1 - intensity
2 - color
*/
`timescale 1 ns / 1 ps
module mcontr( clk0, // system clock, mostly negedge (maybe add more clocks for ground bounce reducing?)
rst,
mwr, // @negedge clk0 - write parameters, - valid with ma[2:0]
ma, // [2:0] - specifies register to use:
// 0 - command register, bit19 - ch3 read_block, bit 18 - next block, [17:16] - SDRAM enable/refresh, [15:14] - channel7, ...
// 1 - SDRAM manual commands [17:0]
// 2 - {ny[9:0], 6'b0, nx[9:0]}
// 3 - snb_msbs[9:0], nst[9:0], nsty[4:0], nstx[4:0]
// 4 - channel0 start address [11:0]
// 5 - channel1 start address [11:0]
// 6 - channel2 start address {sync,[11:0]}
// 7 - channel3 start address {write,4'b0,[15:0]}
piorw, // PIO data (channel 3 R/W)
wnr, // write/not read - used with piorw (channel direction - separately - bit of data)
mdi, // [31:0] data valid with mwr - CPU data to write parameters (and also - channel3)
mdo, // [31:0] channel 3 data to cpu
rq_busy, // [8:0] per channel - rq | busy
nstx, // [4:0] (number of SUPERTILES (128x64 pix) in a row) -1
nsty, // [4:0] (number of SUPERTILES (128x64 pix) rows in a frame) -1
nst, // [9:0] (number of SUPERTILES (128x64 pix) in a frame) -1
// interface to SDRAM (through extra registers
pre2cmd, // {ras,cas,we} - should be all ones when not in use (2 cycles ahead of I/O pads)
pre2sda, //[12:0] address to SDRAM - 2 cycles ahead of I/O pads
pre2sdb, //[ 1:0] bank to SDRAM - 2 cycles ahead of I/O pads
sddo, //[31:0] - 1 cycle ahead of "write" command on I/O pads
sddi, //[31:0] -
drive_sd2, // enable data to SDRAM (2 cycles ahead)
drive_dq2, // enable DQ outputs (one extra for FF in output buffer)
dmask2, // now both the same (even number of words written)
dqs_re, // enable read from DQS i/o-s for phase adjustments (latency 2 from the SDRAM RD command)
// Channel 0 : read/write of SDRAM data
ch0_a,
ch0_ibwe, // input data write enable, advance address
ch0_ibdat, // [15:0] input data (1 or 2 pixels)
ch0_next_line, // advance to the next scan line (and next block RAM page if needed)
ch0_last_line,
ch0_a_out,
ch0_fill_order,
// Channel 1 : read/write of SDRAM data
ch1_a,
ch1_obre, // output read enable, advance address
ch1_obdat, // [15:0] output dtata
ch1_next_line, // advance to the next scan line (and next block RAM page if needed)
ch1_weo,
ch1_start,
ch1_a_out,
ch1_fill_order,
// Channel 2 : read/write of SDRAM data
ch2_a,
ch2_ibwe, // input data write enable, advance address
ch2_ibdat, // [15:0] input data (1 or 2 pixels)
ch2_next_line, // advance to the next scan line (and next block RAM page if needed)
ch2_last_line,
ch2_a_out,
ch2_fill_order,
// Channel 3 : read/write of SDRAM data
ch3_a,
ch3_obre, // output read enable, advance address
ch3_obdat, // [15:0] output dtata
ch3_next_line, // advance to the next scan line (and next block RAM page if needed)
ch3_weo,
ch3_start,
ch3_a_out,
ch3_fill_order,
// Channel 4 : read/write of SDRAM data
ch4_a,
ch4_ibwe, // input data write enable, advance address
ch4_ibdat, // [15:0] input data (1 or 2 pixels)
ch4_next_line, // advance to the next scan line (and next block RAM page if needed)
ch4_last_line,
ch4_a_out,
ch4_fill_order,
// Channel 5 : read/write of SDRAM data
ch5_a,
ch5_obre, // output read enable, advance address
ch5_obdat, // [15:0] output dtata
ch5_next_line, // advance to the next scan line (and next block RAM page if needed)
ch5_weo,
ch5_start,
ch5_a_out,
ch5_fill_order,
// Others :
en_refresh, // to see if SDRAM controller is programmed
tok_frame_num_wr,// debug - LSB of last frame written by compressor_one
init_out,
ao
);
input clk0;
input rst;
input mwr; // @negedge clk0 - write parameters, - valid with ma[2:0]
input [ 4:0] ma; // [2:0] - specifies register to use:
// 0 - command register, bit19 - ch3 read_block, bit 18 - next block, [17:16] - SDRAM enable/refresh, [15:14] - channel7, ...
// 1 - SDRAM manual commands [17:0]
// 2 - ny[9:0], nx[9:0]
// 3 - snb_msbs[9:0], nst[9:0], nsty[4:0], nstx[4:0]
// 4 - channel0 start address [11:0]
// 5 - channel1 start address [11:0]
// 6 - channel2 start address {sync,[11:0]}
// 7 - channel3 start address {read_ahead,write,[15:0]}
input piorw; // PIO data (channel 3 R/W)
input wnr; // write/not read - used with piorw (channel direction - separately - bit of data)
input [31:0] mdi; // [31:0] data valid with mwr - CPU data to write parameters (and also - channel3)
output [31:0] mdo; // [31:0] channel 3 data to cpu
output [8:0] rq_busy; // request or busy - per channel
output [ 4:0] nstx;
output [ 4:0] nsty;
output [ 9:0] nst;
// interface to SDRAM (through extra registers
output [ 2:0] pre2cmd; // {ras,cas,we} - should be all ones when not in use (2 cycles ahead of I/O pads)
output [12:0] pre2sda; //[12:0] address to SDRAM - 2 cycles ahead of I/O pads
output [ 1:0] pre2sdb; //[ 1:0] bank to SDRAM - 2 cycles ahead of I/O pads
output [31:0] sddo; //[31:0] - 1 cycle ahead of "write" command on I/O pads
input [31:0] sddi; //[31:0] -
output drive_sd2; // enable data to SDRAM (2 cycles ahead)
output drive_dq2; // enable DQ outputs (one extra for FF in output buffer)
output dmask2; // [1:0] - now both the same (even number of words written)
output dqs_re; // enable read from DQS i/o-s for phase adjustments (latency 2 from the SDRAM RD command)
// output inuse2; // SDRAM is used by this module (sync to pre2cmd, etc)
// Channel 0
input [10:0] ch0_a;
input ch0_ibwe; // input data write enable, advance address
input [15:0] ch0_ibdat; // [15:0] input data (1 or 2 pixels)
input ch0_next_line; // advance to the next scan line (and next block RAM page if needed)
input ch0_last_line;
output [21:0] ch0_a_out;
input ch0_fill_order;
// Channel 1
input [11:0] ch1_a;
input ch1_obre; // output read enable, advance address
output [15:0] ch1_obdat; // [15:0] output dtata
input ch1_next_line; // advance to the next scan line (and next block RAM page if needed)
output ch1_weo;
input ch1_start;
output [21:0] ch1_a_out;
input ch1_fill_order;
// Channel 2
input [10:0] ch2_a;
input ch2_ibwe; // input data write enable, advance address
input [15:0] ch2_ibdat; // [15:0] input data (1 or 2 pixels)
input ch2_next_line; // advance to the next scan line (and next block RAM page if needed)
input ch2_last_line;
output [21:0] ch2_a_out;
input ch2_fill_order;
// Channel 3
input [11:0] ch3_a;
input ch3_obre; // output read enable, advance address
output [15:0] ch3_obdat; // [15:0] output dtata
input ch3_next_line; // advance to the next scan line (and next block RAM page if needed)
output ch3_weo;
input ch3_start;
output [21:0] ch3_a_out;
input ch3_fill_order;
// Channel 4
input [10:0] ch4_a;
input ch4_ibwe; // input data write enable, advance address
input [15:0] ch4_ibdat; // [15:0] input data (1 or 2 pixels)
input ch4_next_line; // advance to the next scan line (and next block RAM page if needed)
input ch4_last_line;
output [21:0] ch4_a_out;
input ch4_fill_order;
// Channel 5
input [11:0] ch5_a;
input ch5_obre; // output read enable, advance address
output [15:0] ch5_obdat; // [15:0] output dtata
input ch5_next_line; // advance to the next scan line (and next block RAM page if needed)
output ch5_weo;
input ch5_start;
output [21:0] ch5_a_out;
input ch5_fill_order;
output en_refresh;
output tok_frame_num_wr;
output [10:0] ao;
output [8:0] init_out;
wire ch0_next_line;
wire ch0_next_line_clone=ch0_next_line;
wire [ 8:0] init_chn;
wire [ 8:0] enrq_chn;
wire en_refresh;
wire ch3_next_block;
wire ch3_read_block;
wire [ 9:0] snb_msbs;
wire [ 4:0] nstx;
wire [ 4:0] nsty;
wire [ 9:0] nst;
wire [ 9:0] ntile_x;
wire [ 9:0] ntile_y;
wire [11:0] ch0_sa;
wire [11:0] ch1_sa;
wire [11:0] ch2_sa;
wire [15:0] ch3_sa;
wire ch2_sync;
wire ch3_wnr;
wire [10:0] ch0_a;
wire [11:0] ch1_a;
wire [14:0] ch0_line_number;
wire [ 8:0] start_chn;
wire [ 8:0] channel; // 1-hot current channel (may switch before drun?)
wire [ 8:0] rq_chn; // not all bits used
wire [ 8:0] rq_urgent_chn; // not all bits used
assign rq_urgent_chn[7:6]=0;
wire [21:0] chn0_sa;
wire [ 4:0] chn0_len;
wire [21:0] chn1_sa;
wire [ 4:0] chn1_len;
wire [21:0] chn2_sa;
wire [ 4:0] chn2_len;
wire [21:0] chn3_sa;
wire [ 4:0] chn3_len;
wire [21:0] chn4_sa;
wire [ 4:0] chn4_len;
wire [21:0] chn5_sa;
wire [ 4:0] chn5_len;
wire ch3_wnr_current;
wire ch3_read_ahead;
wire start_lnwr, start_lnrd;
wire pre3refr;
wire predrun_lnwr, predrun_lnrd, predrun_t20x20;// predrun_wpf, predrun_rpf, predrun_tw, predrun_tr;
wire prenext_lnwr, prenext_lnrd, prenext_t20x20, prenext_wpf, prenext_rpf, prenext_tw, prenext_tr, prenext_refr;
wire prenext;
wire pre3act_lnwr, pre3act_lnrd, pre3act_t20x20, pre3act_wpf, pre3act_rpf, pre3act_tw, pre3act_tr;
wire pre3pre_lnwr, pre3pre_lnrd, pre3pre_t20x20, pre3pre_wpf, pre3pre_rpf, pre3pre_tw, pre3pre_tr;
wire pre3wr_lnwr, pre3wr_wpf, pre3wr_tw;
wire drive_sd3_lnwr, drive_sd3_wpf, drive_sd3_tw;
wire drive_dq3_lnwr, drive_dq3_wpf, drive_dq3_tw;
wire dmask3_lnwr, dmask3_wpf, dmask3_tw;
wire pre3rd_lnrd, pre3rd_t20x20, pre3rd_rpf, pre3rd_tr;
wire dqs_re3_lnrd, dqs_re3_t20x20, dqs_re3_rpf, dqs_re3_tr;
wire inuse3_lnwr, inuse3_lnrd, inuse3_t20x20, inuse3_wpf, inuse3_rpf, inuse3_tw, inuse3_tr, inuse3_refr;
wire [12:0] pre3sda_lnwr;
wire [12:0] pre3sda_lnrd;
wire [12:0] pre3sda_t20x20;
wire [12:0] pre3sda_wpf;
wire [12:0] pre3sda_rpf;
wire [12:0] pre3sda_tw;
wire [12:0] pre3sda_tr;
wire [ 1:0] pre3sdb_lnwr;
wire [ 1:0] pre3sdb_lnrd;
wire [ 1:0] pre3sdb_t20x20;
wire [ 1:0] pre3sdb_wpf;
wire [ 1:0] pre3sdb_rpf;
wire [ 1:0] pre3sdb_tw;
wire [ 1:0] pre3sdb_tr;
wire [31:0] sddo_chn0;
wire [31:0] sddo_chn2;
wire [31:0] sddo_chn4;
wire [31:0] sddo_wpf;
wire [31:0] sddo_tw;
wire used_4_sb; // used group of 4 superblocks from Block RAM buffer (may be overwritten)
wire tok_rd_dav;
wire [ 9:0] obadr;
wire [15:0] obdat;
wire obre;
wire [10:0] ibadr;
wire [ 7:0] ibdat;
wire ibwe;
wire [15:0] compr_tk_data;
wire compr_tk_data_we;
wire pre3act;
wire pre3rd;
wire pre3wr;
wire pre3pre;
reg next;
//reg inuse2;
reg [12:0] pre2sda;
reg [ 1:0] pre2sdb;
reg [31:0] sddo;
reg drive_sd2;
reg drive_dq2;
reg dmask2;
reg dqs_re;
wire [ 2:0] pre2cmd;
wire [17:0] mancmd;
wire [ 5:0] sddo_sel;
wire init_lnwr;
wire init_lnrd;
wire tok_frame_written;
assign en_refresh=enrq_chn[8];
reg tok_frame_num_wr;
wire tok_frame_writtens;
wire [7:0] ch0_x_max;
wire [7:0] ch0_x_shift;
wire [7:0] ch0_nx_max;
wire [13:0] ch0_y_max;
wire [7:0] ch0_y_shift;
wire [7:0] ch0_ny_max;
wire [7:0] ch1_x_max;
wire [7:0] ch1_x_shift;
wire [7:0] ch1_nx_max;
wire [13:0] ch1_y_max;
wire [7:0] ch1_y_shift;
wire [7:0] ch1_ny_max;
wire [21:0] ch0_a_out=chn0_sa;
wire [21:0] ch1_a_out=chn1_sa;
wire [21:0] ch2_a_out=chn2_sa;
wire [21:0] ch3_a_out=chn3_sa;
reg sddo_chn0_block=0;
always @ (negedge clk0) begin
if (ch0_last_line) sddo_chn0_block <= 0;//1;
else if (ch0_next_line) sddo_chn0_block <= 0;
end
reg sddo_chn2_block=0;
always @ (negedge clk0) begin
if (ch2_last_line) sddo_chn2_block <= 0;//1;
else if (ch2_next_line) sddo_chn2_block <= 0;
end
always @ (negedge clk0) begin
if (init_chn[6]) tok_frame_num_wr <= 1'h0;
else if (tok_frame_written) tok_frame_num_wr <= tok_frame_num_wr + 1;
end
assign init_lnwr= (init_chn[0] & init_chn[2] & init_chn[4])|(init_chn[0] & channel[0])|(init_chn[2] & channel[2])|(init_chn[4] & channel[4]);
assign init_lnrd= (init_chn[1] & init_chn[3] & init_chn[5])|(init_chn[1] & channel[1])|(init_chn[3] & channel[3])|(init_chn[5] & channel[5]);
assign prenext = (!init_lnwr && prenext_lnwr) || (!init_lnrd && prenext_lnrd) ||
prenext_refr;
assign pre3act = pre3act_lnwr | pre3act_lnrd;
assign pre3rd = pre3rd_lnrd;
assign pre3wr = pre3wr_lnwr;
assign pre3pre = pre3pre_lnwr | pre3pre_lnrd;
//assign rq_chn[2]= 1'b0;
//assign rq_chn[3]= 1'b0;
//assign rq_chn[4]= 1'b0;
//assign rq_chn[5]= 1'b0;
assign rq_chn[6]= 1'b0;
assign rq_chn[7]= 1'b0;
//assign rq_urgent_chn[3]= 1'b0;
//assign rq_urgent_chn[2]= 1'b0;
always @ (negedge clk0) begin
next <= prenext;
pre2sda[12:0] <= ({13{~inuse3_lnwr }} | pre3sda_lnwr[12:0]) &
({13{~inuse3_lnrd }} | pre3sda_lnrd[12:0]) & mancmd[12:0];
pre2sdb[1:0] <= ({ 2{~inuse3_lnwr }} | pre3sdb_lnwr [1:0] ) &
({ 2{~inuse3_lnrd }} | pre3sdb_lnrd [1:0] ) & mancmd[14:13];
case (sddo_sel)
6'h01: sddo[31:0] <= (sddo_chn0_block)?32'hffffffff:sddo_chn0[31:0];
6'h02: sddo[31:0] <= (sddo_chn0_block)?32'hffffffff:sddo_chn0[31:0];
6'h03: sddo[31:0] <= (sddo_chn2_block)?32'hffffffff:sddo_chn2[31:0];
6'h04: sddo[31:0] <= (sddo_chn2_block)?32'hffffffff:sddo_chn2[31:0]; //token write
6'h10: sddo[31:0] <= (sddo_chn2_block)?32'hffffffff:sddo_chn4[31:0];
6'h20: sddo[31:0] <= (sddo_chn2_block)?32'hffffffff:sddo_chn4[31:0]; //token write
endcase
drive_sd2 <= (inuse3_lnwr && drive_sd3_lnwr);
drive_dq2 <= (inuse3_lnwr && drive_dq3_lnwr);
dmask2 <= (inuse3_lnwr && dmask3_lnwr);
// inuse is too early for dqs_re (3 cycles?)
// dqs_re <= (inuse3_lnrd && dqs_re3_lnrd) || (inuse3_tr && dqs_re3_tr) || (inuse3_rpf && dqs_re3_rpf) || (inuse3_rpf && dqs_re3_t20x20);
dqs_re <= dqs_re3_lnrd;
end
// Use FF for cas, ras, we for correct simulation
FD_1 i_pre2cmd_0 (.D( ~(pre3wr | pre3pre ) & mancmd[15]), .C(clk0),.Q(pre2cmd[0])); //WE
FD_1 i_pre2cmd_1 (.D( ~(pre3rd | pre3wr | pre3refr) & mancmd[16]), .C(clk0),.Q(pre2cmd[1])); //CAS
FD_1 i_pre2cmd_2 (.D( ~(pre3act | pre3pre | pre3refr) & mancmd[17]), .C(clk0),.Q(pre2cmd[2])); //RAS
//synthesis translate_off
defparam i_pre2cmd_0.INIT = 1'b1;
defparam i_pre2cmd_1.INIT = 1'b1;
defparam i_pre2cmd_2.INIT = 1'b1;
//synthesis translate_on
//synthesis attribute INIT of i_pre2cmd_0 is "1"
//synthesis attribute INIT of i_pre2cmd_1 is "1"
//synthesis attribute INIT of i_pre2cmd_2 is "1"
mcontr_cmd i_mcontr_cmd(.clk0(clk0), // system clock, mostly negedge (maybe add more clocks for ground bounce reducing?)0
.mwr(mwr), // @negedge clk0 - write parameters, single-cycle - valid with ma[2:0] - early , mdi valid at mwr and next cycle
.ma(ma[4:0]), // [2:0] - specifies register to use:
// 0 - command register, bit19 - ch3 read_block, bit 18 - next block, [17:16] - refresh, [15:14] - channel7, ...
// 1 - SDRAM manual commands [17:0]
// 2 - ny[9:0] (d[25:16], nx[9:0] (d[9:0])
// 3 - snb_msbs[9:0], nst[9:0], nsty[4:0], nstx[4:0]
// 4 - channel0 start address [11:0]
// 5 - channel1 start address [11:0]
// 6 - channel2 start address {sync,4'b0,[11:0]}
// 7 - channel3 start address {readahead,write,[15:0]}
.mdi(mdi[31:0]), // [31:0] data valid with mwr - CPU data to write parameters (and also - channel3)
.init_chn(init_chn[8:0]), // [8:0] init channels
.enrq_chn(enrq_chn[8:0]), // [8:0] enable channels to access SDRAM ( 0 - pause, will not abort SDRAM r/w in progress)
.ch3_next_block(ch3_next_block),
.ch3_read_block(ch3_read_block),
.ch3_read_ahead(ch3_read_ahead), // if set, ch3 in read mode will try to read 4 pages ahead without additional requests
.snb_msbs(snb_msbs[9:0]), // 10 MSBs of the start block address of the SDRAM dedicated to the token buffer
//.nstx(nstx[4:0]), // (number of SUPERTILES (128x64 pix) block in a row) -1
//.nsty(nsty[4:0]), // (number of SUPERTILES (128x64 pix) rows in a frame) -1
//.nst(nst[9:0]), // (number of SUPERTILES (128x64 pix) in a frame) -1
//.ntile_x(ntile_x[9:0]), // [9:0] (number of overlapping 20x20 tiles in a scan line) - 1
//.ntile_y(ntile_y[9:0]), // [9:0] (number of overlapping 20x20 tiles in a column) - 1
.ch0_x_max(ch0_x_max),
.ch0_x_shift(ch0_x_shift),
.ch0_nx_max(ch0_nx_max),
.ch0_y_max(ch0_y_max),
.ch0_y_shift(ch0_y_shift),
.ch0_ny_max(ch0_ny_max),
.ch1_x_max(ch1_x_max),
.ch1_x_shift(ch1_x_shift),
.ch1_nx_max(ch1_nx_max),
.ch1_y_max(ch1_y_max),
.ch1_y_shift(ch1_y_shift),
.ch1_ny_max(ch1_ny_max),
.ch0_sa(ch0_sa[11:0]), // [11:0] 12 MSBs of the channel0 start address
.ch1_sa(ch1_sa[11:0]), // [11:0] 12 MSBs of the channel0 start address
.ch2_sa(ch2_sa[11:0]), // [11:0] 12 MSBs of the channel0 start address
.ch3_sa(ch3_sa[15:0]), // [15:0] 16 MSBs of the channel0 start address
.ch2_sync(ch2_sync), // If "1" - channel 2 will wait for data from channel 0, "0" - run independently
.ch3_wnr(ch3_wnr), // channel3 (CPU PIO) write/not read mode
.mancmd(mancmd) // [17:0]
);
wire [8:0] init_out=init_chn[8:0];
mcontr_arbiter i_mcontr_arbiter(.clk0(clk0), // system clock, mostly negedge (maybe add more clocks for ground bounce reducing?)
.ch3_wnr(0), // channel3 mode: 1 - write, 0 - read
.init_chn(init_chn[8:0]), // [8:0] - reset busy for selected channels
.rq(rq_chn[8:0]), // [8:0] - low priority request from channels (0..5), 8 - refresh
.rq_urgent(rq_urgent_chn[8:0]), // [7:0] - high priority request from channels (0..2, 4..7)
.next(next), // - 7 cycles ahead of the next start (8- refresh)
.start(start_chn[8:0]), // [8:0] - one-hot start channels
.start_lnwr(start_lnwr), // start writing line (ch0 and possibly ch3)
.start_lnrd(start_lnrd), // start reading line (ch1 and possibly ch3)
.channel(channel[8:0]), // [8:0] - one-hot channel select - starts 1 cycle ahead of start (drun can last longer)
.sddo_sel(sddo_sel[5:0]), // [1:0] - 0 - chn0, 1 - chn3, 2 - chn4, 3 - chn6
.rq_busy(rq_busy[8:0]) // [8:0] per channel - rq | busy
);
mcontr_refresh i_mcontr_refresh(.clk0(clk0),
.enrq(enrq_chn[8]),
.init(init_chn[8]),
.start(start_chn[8]),
.rq(rq_chn[8]),
.rq_urgent(rq_urgent_chn[8]),
.prenext(prenext_refr),
// interface to SDRAM (through extra registers
.pre3refr(pre3refr), // precharge command (3 ahead)
.inuse3(inuse3_refr) // SDRAm in use by this channel (sync with pre3***
);
reg [5:0] sddo_sel_d=0;
reg [5:0] sddo_sel_dd=0;
always @(negedge clk0)
begin
sddo_sel_d[5:0] <= sddo_sel[5:0];
sddo_sel_dd[5:0] <= sddo_sel_d[5:0];
end
channel_wr i_channel0 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[0]), // enable channel requests (does not reset if 0)
//.fsa(ch0_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h000),
// Using the same values for channels 0..2
.init(init_chn[0]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch0_fill_order),
// arbiter interface
.start(start_chn[0]),
.rq(rq_chn[0]), // request - want at least one access
.rq_urgent(rq_urgent_chn[0]), // need 3 or 4 accesses
//SDRAM controller inteface (mcontr_line512_wr)
.sddo(sddo_chn0[31:0]), //[31:0]
.predrun(predrun_lnwr & sddo_sel[0]),
.sa(chn0_sa[21:0]), //[16:0]
.len(chn0_len[4:0]), // access length (0 - full block, 1 - 10x16 bits, 2 - 18*16 bits,... (m16 bit will be 0 for this channel)
// external interface (compressor)
.ibwe(ch0_ibwe), // input data write enable, advance address
.ch0a(ch0_a[10:0]),
.ibdat(ch0_ibdat[15:0]), // [15:0] input data (1 or 2 pixels)
//.next_line(0)
.next_line(ch0_next_line)
);
channel_rd i_channel1 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[1]), // enable channel requests (does not reset if 0)
//.fsa(ch1_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h000),
.start2(ch1_start),
// Using the same values for channels 0..2
.init(init_chn[1]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch1_fill_order),
// arbiter interface
.start(start_chn[1] & !init_chn[1]),
.rq(rq_chn[1]), // request - want at least one access
.rq_urgent(rq_urgent_chn[1]), // need 3 or 4 accesses
.sddi(sddi[31:0]), //[31:0]
.rq_busy(rq_busy[1]),
//SDRAM controller inteface (mcontr_line512_rd)
.predrun(predrun_lnrd & sddo_sel_dd[1]),// & sddo_sel[1]),
.sa(chn1_sa[21:0]), //[16:0]
.len(chn1_len[4:0]), // access length (0 - full block, 1 - 12x16 bits, 2 - 20*16 bits,... (m16 bit will be set for this channel)
// external interface (compressor)
.obre(ch1_obre), // output read enable, advance address
.ch1a(ch1_a[11:0]),
.obdat(ch1_obdat[15:0]), // [15:0] output dtata
.next_line(ch1_next_line), // advance to the next scan line (and next block RAM page if needed)
.ao(ao)
);
assign ch1_weo=predrun_lnrd & sddo_sel_dd[1];
/////////////
/////////////
channel_wr i_channel2 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[2]), // enable channel requests (does not reset if 0)
//.fsa(ch0_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h400),
// Using the same values for channels 0..2
.init(init_chn[2]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch2_fill_order),
// arbiter interface
.start(start_chn[2]),
.rq(rq_chn[2]), // request - want at least one access
.rq_urgent(rq_urgent_chn[2]), // need 3 or 4 accesses
//SDRAM controller inteface (mcontr_line512_wr)
.sddo(sddo_chn2[31:0]), //[31:0]
.predrun(predrun_lnwr & sddo_sel[2]),
.sa(chn2_sa[21:0]), //[16:0]
.len(chn2_len[4:0]), // access length (0 - full block, 1 - 10x16 bits, 2 - 18*16 bits,... (m16 bit will be 0 for this channel)
// external interface (compressor)
.ibwe(ch2_ibwe), // input data write enable, advance address
.ch0a(ch2_a[10:0]),
.ibdat(ch2_ibdat[15:0]), // [15:0] input data (1 or 2 pixels)
//.next_line(0)
.next_line(ch2_next_line)
);
/////////////
/////////////
channel_rd i_channel3 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[3]), // enable channel requests (does not reset if 0)
//.fsa(ch3_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h400),
//.fsa(12'h000), //for testing equal frames
.start2(ch3_start),
// Using the same values for channels 0..2
.init(init_chn[3]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch3_fill_order),
// arbiter interface
.start(start_chn[3] & !init_chn[3]),
.rq(rq_chn[3]), // request - want at least one access
.rq_urgent(rq_urgent_chn[3]), // need 3 or 4 accesses
.sddi(sddi[31:0]), //[31:0]
.rq_busy(rq_busy[3]),
//SDRAM controller inteface (mcontr_line512_rd)
.predrun(predrun_lnrd & sddo_sel_dd[3]),
.sa(chn3_sa[21:0]), //[16:0]
.len(chn3_len[4:0]), // access length (0 - full block, 1 - 12x16 bits, 2 - 20*16 bits,... (m16 bit will be set for this channel)
// external interface (compressor)
.obre(ch3_obre), // output read enable, advance address
.ch1a(ch3_a[11:0]),
.obdat(ch3_obdat[15:0]), // [15:0] output dtata
.next_line(ch3_next_line), // advance to the next scan line (and next block RAM page if needed)
.ao()
);
assign ch3_weo=predrun_lnrd & sddo_sel_dd[3];
/////////////
/////////////
channel_wr i_channel4 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[4]), // enable channel requests (does not reset if 0)
//.fsa(ch0_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h000),
// Using the same values for channels 0..2
.init(init_chn[4]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch4_fill_order),
// arbiter interface
.start(start_chn[4]),
.rq(rq_chn[4]), // request - want at least one access
.rq_urgent(rq_urgent_chn[4]), // need 3 or 4 accesses
//SDRAM controller inteface (mcontr_line512_wr)
.sddo(sddo_chn4[31:0]), //[31:0]
.predrun(predrun_lnwr & sddo_sel[4]),
.sa(chn4_sa[21:0]), //[16:0]
.len(chn4_len[4:0]), // access length (0 - full block, 1 - 10x16 bits, 2 - 18*16 bits,... (m16 bit will be 0 for this channel)
// external interface (compressor)
.ibwe(ch4_ibwe), // input data write enable, advance address
.ch0a(ch4_a[10:0]),
.ibdat(ch4_ibdat[15:0]), // [15:0] input data (1 or 2 pixels)
//.next_line(0)
.next_line(ch4_next_line)
);
/////////////
/////////////
channel_rd_short i_channel5 (.clk(clk0), // SDRAM clock (negedge)
.enrq(enrq_chn[5]), // enable channel requests (does not reset if 0)
//.fsa(ch3_sa[11:0]), // [11:0] frame start address (12 MSBs of SDRAM row address)
.fsa(12'h000),
//.fsa(12'h000), //for testing equal frames
.start2(ch5_start),
// Using the same values for channels 0..2
.init(init_chn[5]|rst), // resets channel
// .x_max(ch0_x_max),
// .x_shift(ch0_x_shift),
// .nx_max(ch0_nx_max),
// .y_max(ch0_y_max),
// .y_shift(ch0_y_shift),
// .ny_max(ch0_ny_max),
.x_max (8'h0f),
.x_shift(8'h02),
.nx_max (8'h0f),
.y_max (16'h1fff),
.y_shift(8'h10),
.ny_max (8'hff ),
.fill_order(ch5_fill_order),
// arbiter interface
.start(start_chn[5] & !init_chn[5]),
.rq(rq_chn[5]), // request - want at least one access
.rq_urgent(rq_urgent_chn[5]), // need 3 or 4 accesses
.sddi(sddi[31:0]), //[31:0]
.rq_busy(rq_busy[5]),
//SDRAM controller inteface (mcontr_line512_rd)
.predrun(predrun_lnrd & sddo_sel_dd[5]),
.sa(chn5_sa[21:0]), //[16:0]
.len(chn5_len[4:0]), // access length (0 - full block, 1 - 12x16 bits, 2 - 20*16 bits,... (m16 bit will be set for this channel)
// external interface (compressor)
.obre(ch5_obre), // output read enable, advance address
.ch1a(ch5_a[11:0]),
.obdat(ch5_obdat[15:0]), // [15:0] output dtata
.next_line(ch5_next_line), // advance to the next scan line (and next block RAM page if needed)
.ao()
);
assign ch5_weo=predrun_lnrd & sddo_sel_dd[5];
mcontr_line_wr i_mcontr_line_wr (.mclk0(clk0), // system clock, mostly negedge
// .en(!(init_chn[0] && init_chn[3])), // need to reset both channels to reset this module
.en(!init_lnwr), // need to reset both channels to reset this module
// interface to the output block RAM (x16). Will probably include 12->16 bit conversion here
.predrun(predrun_lnwr), //
// interface to SDRAM arbiter
.start(start_lnwr), // start atomic writing to SDRAM operation (5 cycles ahead of RAS command on the pads)
.sa(channel[4]?chn4_sa[21:0]:(channel[2]?chn2_sa[21:0]:chn0_sa[21:0])), // [16:0] - 13 MSBs ->RA, 4 LSBs - row in a chunk
.len(chn0_len[4:0]), // [ 4:0] - number of 32-byte groups to write, 0 - all 256bytes, for other values - (len*32+8) bytes
.prenext(prenext_lnwr), // 8 cycles ahead of possible next start_*?
// interface to SDRAM (through extra registers
.pre3pre(pre3pre_lnwr), // precharge command (3 ahead)
.pre3wr(pre3wr_lnwr), // read command (3 ahead)
.pre3act(pre3act_lnwr), // activate command (3ahead)
.pre3sda(pre3sda_lnwr[12:0]), //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
.pre3sdb(pre3sdb_lnwr[1:0]), //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
.drive_sd3(drive_sd3_lnwr), // enable data to SDRAM (2 cycles ahead)
.drive_dq3(drive_dq3_lnwr), // enable DQ outputs (one extra for FF in output buffer)
.dmask3(dmask3_lnwr), // write mask - 1 bit as even number of words written (32-bit pairs)
.inuse3(inuse3_lnwr) // SDRAm in use by this channel (sync with pre3***
);
mcontr_line_rd i_mcontr_line_rd (.mclk0(clk0), // system clock, mostly negedge
// .en(!(init_chn[1] && init_chn[3])),
.en(!init_lnrd),
// interface to the output block RAM (x16). Will probably include 12->16 bit conversion here
.predrun(predrun_lnrd), //
// interface to SDRAM arbiter
.start(start_lnrd), // start atomic reading from SDRAM operation (5 cycles ahead of RAS command on the pads)
.sa(channel[5]?chn5_sa[21:0]:(channel[3]?chn3_sa[21:0]:chn1_sa[21:0])), // [16:0] - 13 MSBs ->RA, 4 LSBs - row in a chunk
.len(chn1_len[4:0]), // [ 4:0] - number of 32-byte groups to read, 0 - all 256bytes, for other values - (len*32+8) bytes
//.m16(channel[3]), // 16-bit mode (read 2, not 1 extra 32-bit words for partial blocks)
.prenext(prenext_lnrd), // 8 cycles ahead of possible next start_*?
// interface to SDRAM (through extra registers
.pre3pre(pre3pre_lnrd), // precharge command (3 ahead)
.pre3rd(pre3rd_lnrd), // read command (3 ahead)
.pre3act(pre3act_lnrd), // activate command (3ahead)
.pre3sda(pre3sda_lnrd[12:0]), //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
.pre3sdb(pre3sdb_lnrd[1:0]), //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
.dqs_re3(dqs_re3_lnrd), // enable read from DQS i/o-s for phase adjustments (1 ahead of the final)
.inuse3(inuse3_lnrd) // SDRAm in use by this channel (sync with pre3***
);
endmodule
mcontr_arbiter.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** mcontr_arbiter.v
**
** Performs arbitration of SDRAM accesses between 8 channels and refresh.
** some channels have 2 levels of request priority (rq and rq_urgent)
**
** Copyright 2002-2004 Andrey Filippov
**
** -----------------------------------------------------------------------------**
** This file is part of X333
**
** X333 is free software - hardware description language (HDL) code; you can
** redistribute it and/or modify it under the terms of the GNU General Public License
** as published by the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** X333 is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with X333; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
** -----------------------------------------------------------------------------**
**
*/
`timescale 1 ns / 1 ps
// add some status outputs
module mcontr_arbiter(clk0, // system clock, mostly negedge (maybe add more clocks for ground bounce reducing?)
ch3_wnr, // channel3 mode: 1 - write, 0 - read
init_chn, // [8:0] - reset busy for selected channels
rq, // [8:0] - low priority request from channels (0..5), 8 - refresh
rq_urgent, // [8:0] - high priority request from channels (0..2, 4..7)
// prenext, // - 8 cycles ahead of the next start (8- refresh)
next, // - 7 cycles ahead of the next start (8- refresh)
start, // [8:0] - one-hot start channels
start_lnwr, // start writing line (ch0 and possibly ch3)
start_lnrd, // start reading line (ch1 and possibly ch3)
channel, // [8:0] - one-hot channel select - starts 1 cycle ahead of start (drun can last longer)
sddo_sel, // [1:0] - 0 - chn0, 1 - chn3, 2 - chn4, 3 - chn6
rq_busy // [8:0] per channel - rq | busy
);
input clk0;
input ch3_wnr;
input [8:0] init_chn;
input [8:0] rq;
input [8:0] rq_urgent;
// input prenext;
input next;
output [8:0] start;
output start_lnwr;
output start_lnrd;
output [8:0] channel;
output [5:0] sddo_sel;
output [8:0] rq_busy;
reg [8:0] start=0;
reg [8:0] channel=0;
wire [8:0] prechannel;
reg prestart=0;
reg pre2start=0;
reg [8:0] busy=0;
reg [2:0] cntr=0;
// wire want=|(rq[8:0] & (~init_chn[8:0])) || |(rq_urgent[8:0]& (~init_chn[8:0]));
reg want=0;
wire can= (busy[8:0] == 9'h0);
reg [17:0] frosen_rq=0;
reg start_lnwr=0;
reg start_lnrd=0;
reg [5:0] sddo_sel=0;
wire sddo_sel_stb;
assign rq_busy[8:0] = rq[8:0] | busy[8:0];
wire no_urgent=(frosen_rq[8:0]==9'h0);
assign prechannel[0] = no_urgent?(frosen_rq[ 9 ] == 1'h1 ):(frosen_rq[ 0 ] == 1'h1 );
assign prechannel[1] = no_urgent?(frosen_rq[10:9] == 2'h2 ):(frosen_rq[ 1:0] == 2'h2 );
assign prechannel[2] = no_urgent?(frosen_rq[11:9] == 3'h4 ):(frosen_rq[ 2:0] == 3'h4 );
assign prechannel[3] = no_urgent?(frosen_rq[12:9] == 4'h8 ):(frosen_rq[ 3:0] == 4'h8 );
assign prechannel[4] = no_urgent?(frosen_rq[13:9] == 5'h10 ):(frosen_rq[ 4:0] == 5'h10);
assign prechannel[5] = no_urgent?(frosen_rq[14:9] == 6'h20 ):(frosen_rq[ 5:0] == 6'h20);
assign prechannel[6] = no_urgent?(frosen_rq[15:9] == 7'h40 ):(frosen_rq[ 6:0] == 7'h40);
assign prechannel[7] = no_urgent?(frosen_rq[16:9] == 8'h80 ):(frosen_rq[ 7:0] == 8'h80);
assign prechannel[8] = no_urgent?(frosen_rq[17:9] == 9'h100):(frosen_rq[ 8:0] == 9'h100);
MSRL16_1 i_sddo_sel_stb (.Q(sddo_sel_stb), .A(4'h2), .CLK(clk0), .D(prestart));
always @ (negedge clk0) begin
// busy[8:0] <= ~init_chn[8:0] & (prestart?prechannel[8:0]:(prenext? 9'h0 : busy[8:0]));
busy[8:0] <= ~init_chn[8:0] & (prestart?prechannel[8:0]:(next? 9'h0 : busy[8:0]));
want<=|(rq[8:0] & (~init_chn[8:0])) || |(rq_urgent[8:0]& (~init_chn[8:0]));
if (pre2start) channel[8:0] <= prechannel[8:0];
start[8:0] <= prestart?prechannel[8:0]:9'h0;
start_lnwr <= prestart && (prechannel[0] | prechannel[2] | prechannel[4] | (prechannel[3] && ch3_wnr));
start_lnrd <= prestart && (prechannel[1] | prechannel[5] | (prechannel[3] && !ch3_wnr));
// if (!(want && can)) cntr[2:0] <= 3'h3;
if (!(want && can)) cntr[2:0] <= 3'h2;
else if (cntr[2:0]!=3'h7) cntr[2:0] <= cntr[2:0] -1;
pre2start <= (cntr[2:0] == 3'h0);
prestart <= pre2start;
if (!(want && can)) frosen_rq[17:0] <= {(rq[8:0] & (~init_chn[8:0])), (rq_urgent[8:0] & (~init_chn[8:0]))};
if (sddo_sel_stb) sddo_sel[5:0] <= channel[5:0];
end
endmodule
mcontr_cmd.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** mcontr_cmd.v
**
** decodes CPU writes to mcontr registers
** Copyright 2004 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X333
**
** X333 is free software - hardware description language (HDL) code; you can
** redistribute it and/or modify it under the terms of the GNU General Public License
** as published by the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** X333 is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with X333; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
** -----------------------------------------------------------------------------**
**
*/
`timescale 1 ns / 1 ps
// add some status outputs
module mcontr_cmd( clk0, // system clock, mostly negedge (maybe add more clocks for ground bounce reducing?)0
mwr, // @negedge clk0 - write parameters, single-cycle - valid with ma[2:0] - early , mdi valid at mwr and next cycle
ma, // [2:0] - specifies register to use:
// 0 - command register, bit19 - ch3 read_block, bit 18 - next block, [17:16] - refresh, [15:14] - channel7, ...
// 1 - SDRAM manual commands [17:0]
// 2 - ny[9:0] (d[25:16], nx[9:0] (d[9:0])
// 3 - snb_msbs[9:0], nst[9:0], nsty[4:0], nstx[4:0]
// 4 - channel0 start address [11:0]
// 5 - channel1 start address [11:0]
// 6 - channel2 start address {sync,4'b0,[11:0]}
// 7 - channel3 start address {readahead,write,[15:0]}
mdi, // [31:0] data valid with mwr - CPU data to write parameters (and also - channel3)
//
init_chn, // [8:0] init channels (8 - refresh)
enrq_chn, // [8:0] enable channels to access SDRAM ( 0 - pause, will not abort SDRAM r/w in progress)
// en_refresh,
ch3_next_block,
ch3_read_block,
ch3_read_ahead, // if set, ch3 in read mode will try to read 4 pages ahead without additional requests
snb_msbs, // 10 MSBs of the start block address of the SDRAM dedicated to the token buffer
//nstx, // (number of SUPERTILES (128x64 pix) block in a row) -1
//nsty, // (number of SUPERTILES (128x64 pix) rows in a frame) -1
nst, // (number of SUPERTILES (128x64 pix) in a frame) -1
//ntile_x, // [9:0] (number of overlapping 20x20 tiles in a scan line) - 1
//ntile_y, // [9:0] (number of overlapping 20x20 tiles in a column) - 1
ch0_x_max,
ch0_x_shift,
ch0_nx_max,
ch0_y_max,
ch0_y_shift,
ch0_ny_max,
ch1_x_max,
ch1_x_shift,
ch1_nx_max,
ch1_y_max,
ch1_y_shift,
ch1_ny_max,
ch0_sa, // [11:0] 12 MSBs of the channel0 start address
ch1_sa, // [11:0] 12 MSBs of the channel0 start address
ch2_sa, // [11:0] 12 MSBs of the channel0 start address
ch3_sa, // [15:0] 16 MSBs of the channel0 start address
ch2_sync, // If "1" - channel 2 will wait for data from channel 0, "0" - run independently
ch3_wnr, // channel3 (CPU PIO) write/not read mode
mancmd // [17:0]
);
input clk0;
input mwr;
input [4:0] ma;
input [31:0] mdi;
output [8:0] init_chn;
output [8:0] enrq_chn;
// output en_refresh;
output ch3_next_block;
output ch3_read_block;
output ch3_read_ahead;
output [9:0] snb_msbs; // 10 MSBs of the start block address of the SDRAM dedicated to the token buffer
//output [4:0] nstx; // (number of SUPERTILES (128x64 pix) block in a row) -1
//output [4:0] nsty; // (number of SUPERTILES (128x64 pix) rows in a frame) -1
output [9:0] nst; // (number of SUPERTILES (128x64 pix) in a frame) -1
//output [9:0] ntile_x; // [9:0] (number of overlapping 20x20 tiles in a scan line) - 1
//output [9:0] ntile_y; // [9:0] (number of overlapping 20x20 tiles in a column) - 1
output [11:0] ch0_sa; // [11:0] 12 MSBs of the channel0 start address
output [11:0] ch1_sa; // [11:0] 12 MSBs of the channel0 start address
output [11:0] ch2_sa; // [11:0] 12 MSBs of the channel0 start address
output [15:0] ch3_sa; // [15:0] 16 MSBs of the channel0 start address
output ch2_sync; // If "1" - channel 2 will wait for data from channel 0, "0" - run independently
output ch3_wnr; // channel3 (CPU PIO) write/not read mode
output [17:0] mancmd;
output [7:0] ch0_x_max;
output [7:0] ch0_x_shift;
output [7:0] ch0_nx_max;
output [13:0] ch0_y_max;
output [7:0] ch0_y_shift;
output [7:0] ch0_ny_max;
output [7:0] ch1_x_max;
output [7:0] ch1_x_shift;
output [7:0] ch1_nx_max;
output [13:0] ch1_y_max;
output [7:0] ch1_y_shift;
output [7:0] ch1_ny_max;
// reg en_refresh;
reg ch3_next_block;
reg ch3_read_block;
reg [9:0] snb_msbs; // 10 MSBs of the start block address of the SDRAM dedicated to the token buffer
//reg [4:0] nstx; // (number of SUPERTILES (128x64 pix) block in a row) -1
//reg [4:0] nsty; // (number of SUPERTILES (128x64 pix) rows in a frame) -1
reg [9:0] nst; // (number of SUPERTILES (128x64 pix) in a frame) -1
//reg [9:0] ntile_x; // [9:0] (number of overlapping 20x20 tiles in a scan line) - 1
//reg [9:0] ntile_y; // [9:0] (number of overlapping 20x20 tiles in a column) - 1
reg [11:0] ch0_sa; // [11:0] 12 MSBs of the channel0 start address
reg [11:0] ch1_sa; // [11:0] 12 MSBs of the channel0 start address
reg [11:0] ch2_sa; // [11:0] 12 MSBs of the channel0 start address
reg [15:0] ch3_sa; // [15:0] 16 MSBs of the channel0 start address
reg ch2_sync; // If "1" - channel 2 will wait for data from channel 0, "0" - run independently
reg ch3_wnr; // channel3 (CPU PIO) write/not read mode
reg [17:0] mancmd;
reg [8:0] ninit_chn;
reg ch3_read_ahead;
wire [8:0] init_chn=~ninit_chn[8:0]; // so will be initialized to all "1"-s on POR
reg [8:0] enrq_chn;
/**/
reg mwr_cmd;
reg mancmd_stb;
reg mwr_nxny;
reg mwr_tkpars;
reg mwr_ch0;
reg mwr_ch1;
reg mwr_ch2;
reg mwr_ch3;
reg mwr_ch0x, mwr_ch0y;
reg mwr_ch1x, mwr_ch1y;
reg [7:0] ch0_x_max=7;
reg [7:0] ch0_x_shift=1; //was8
reg [7:0] ch0_nx_max=15; //was3
reg [13:0] ch0_y_max=3;
reg [7:0] ch0_y_shift=4;
reg [7:0] ch0_ny_max=9;
reg [7:0] ch1_x_max=7;
reg [7:0] ch1_x_shift=1; //was8
reg [7:0] ch1_nx_max=15; //was3
reg [13:0] ch1_y_max=3;
reg [7:0] ch1_y_shift=4;
reg [7:0] ch1_ny_max=9;
/**/
/*
wire mwr_cmd;
wire mancmd_stb;
wire mwr_nxny;
wire mwr_tkpars;
wire mwr_ch0;
wire mwr_ch1;
wire mwr_ch2;
wire mwr_ch3;
assign mwr_cmd = mwr && (ma[2:0]==3'h0);
assign mancmd_stb = mwr && (ma[2:0]==3'h1);
assign mwr_nxny = mwr && (ma[2:0]==3'h2);
assign mwr_tkpars = mwr && (ma[2:0]==3'h3);
assign mwr_ch0 = mwr && (ma[2:0]==3'h4);
assign mwr_ch1 = mwr && (ma[2:0]==3'h5);
assign mwr_ch2 = mwr && (ma[2:0]==3'h6);
assign mwr_ch3 = mwr && (ma[2:0]==3'h7);
*/
always @ (negedge clk0) begin
/**/
mwr_cmd <= mwr && (ma[4:0]==5'h0);
mancmd_stb <= mwr && (ma[4:0]==5'h1);
mwr_nxny <= mwr && (ma[4:0]==5'h2);
mwr_tkpars <= mwr && (ma[4:0]==5'h3);
mwr_ch0 <= mwr && (ma[4:0]==5'h4);
mwr_ch1 <= mwr && (ma[4:0]==5'h5);
mwr_ch2 <= mwr && (ma[4:0]==5'h6);
mwr_ch3 <= mwr && (ma[4:0]==5'h7);
mwr_ch0x <= mwr & (ma[4:0]==5'h0c);
mwr_ch1x <= mwr & (ma[4:0]==5'h0d);
mwr_ch0y <= mwr & (ma[4:0]==5'h0e);
mwr_ch1y <= mwr & (ma[4:0]==5'h0f);
/**/
mancmd[17:0] <= mancmd_stb?mdi[17:0]:18'h3ffff;
if (mwr_cmd) begin
ninit_chn[8:0]<={(mdi[17] | ~mdi[16]),
(mdi[15] | ~mdi[14]),(mdi[13] | ~mdi[12]),(mdi[11] | ~mdi[10]),(mdi[ 9] | ~mdi[ 8]),
(mdi[ 7] | ~mdi[ 6]),(mdi[ 5] | ~mdi[ 4]),(mdi[ 3] | ~mdi[ 2]),(mdi[ 1] | ~mdi[ 0])} & (ninit_chn[8:0] |
{mdi[17],mdi[15],mdi[13],mdi[11],mdi[9],mdi[7],mdi[5],mdi[3],mdi[1]} );
enrq_chn[8:0] <= (~{mdi[16],mdi[14],mdi[12],mdi[10],mdi[8],mdi[6],mdi[4],mdi[2],mdi[0]}) &
({mdi[17],mdi[15],mdi[13],mdi[11],mdi[9],mdi[7],mdi[5],mdi[3],mdi[1]} | enrq_chn[8:0]);
end
ch3_next_block <= mwr_cmd && mdi[18];
ch3_read_block <= mwr_cmd && mdi[19];
// if (mwr_nxny) begin
// ntile_x[9:0] <= mdi[9:0];
// ntile_y[9:0] <= mdi[25:16];
// end
if (mwr_tkpars) begin
snb_msbs[9:0]<= mdi[29:20];
nst[9:0] <= mdi[19:10];
//nsty[4:0] <= mdi[9:5];
//nstx[4:0] <= mdi[4:0];
end
if (mwr_ch0) ch0_sa[11:0] <= mdi[11:0];
if (mwr_ch1) ch1_sa[11:0] <= mdi[11:0];
if (mwr_ch2) begin
ch2_sa[11:0] <= mdi[11:0];
ch2_sync <= mdi[16];
end
if (mwr_ch3) begin
ch3_sa[15:0] <= mdi[15:0];
ch3_wnr <= mdi[16];
ch3_read_ahead <= mdi[17];
end
if (mwr_ch0x) begin
ch0_x_max <= mdi[7:0];
ch0_x_shift <= mdi[15:8];
ch0_nx_max <= mdi[23:16];
end
if (mwr_ch0y) begin
ch0_y_max <= mdi[29:16];
ch0_y_shift <= mdi[15:8];
ch0_ny_max <= mdi[7:0];
end
if (mwr_ch1x) begin
ch1_x_max <= mdi[7:0];
ch1_x_shift <= mdi[15:8];
ch1_nx_max <= mdi[23:16];
end
if (mwr_ch1y) begin
ch1_y_max <= mdi[29:16];
ch1_y_shift <= mdi[15:8];
ch1_ny_max <= mdi[7:0];
end
end
endmodule
mcontr_line_rd.v 0 → 100644
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : mcontr_line_rd.v
*! DESCRIPTION: read sequence to sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: mcontr_line_rd.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:11:54 dzhimiev
*! 0. based on theora's mcontr_8chn.v, mcontr_line512_wr.v, mcontr_line512_rd.v
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
/*
will open both pages (if 2 are needed) at once, read as needed and precharge all banks in the end
*/
// need to take care of banks when switching from plane to plane in the same access.
`timescale 1 ns / 1 ps
module mcontr_line_rd (mclk0, // system clock, mostly negedge
en,
// interface to the output block RAM (x16). Will probably include 12->16 bit conversion here
predrun, //
// interface to SDRAM arbiter
start, // start atomic reading from SDRAM operation (5 cycles ahead of RAS command on the pads)
sa, // [16:0] - 13 MSBs ->RA, 4 LSBs - row in a chunk
len, // [ 4:0] - number of 32-byte groups to read, 0 - all 256bytes, for other values - (len*32+8) bytes
//m16, // 16-bit mode (read 2, not 1 extra 32-bit words for partial blocks)
prenext, // 8 cycles ahead of possible next start_*?
// interface to SDRAM (through extra registers
pre3pre, // precharge command (3 ahead)
pre3rd, // read command (3 ahead)
pre3act, // activate command (3ahead)
pre3sda, //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
pre3sdb, //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
// sddi, //[31:0] - data from SDRAM
dqs_re3, // enable read from DQS i/o-s for phase adjustments (1 ahead of the final)
inuse3 // SDRAm in use by this channel (sync with pre3***
);
input mclk0;
input en;
output predrun;
input start;
input [21:0] sa;
input [ 4:0] len;
//input m16;
output prenext;
// interface to SDRAM (through extra registers
output pre3pre; // precharge command (3 ahead)
output pre3rd; // read command (3 ahead)
output pre3act; // activate command (3ahead)
output [12:0] pre3sda; //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
output [1:0] pre3sdb; //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
// input [31:0] sddi; //[31:0] - data from SDRAM
output dqs_re3; // enable read from DQS i/o-s for phase adjustments (1 ahead of the final)
output inuse3; // SDRAm in use by this channel (sync with pre3***
//
reg pre3act;
reg pre3pre;
reg pre3rd;
reg [12:0] pre3sda;
reg [ 1:0] pre3sdb;
reg inuse3;
reg predrun;
reg prenext;
reg dqs_re3;
wire predrun_on;
wire predrun_off;
wire dqs_re3_on;
wire dqs_re3_off;
reg pre4act1; // before first of 2 activate pulses
reg pre5act2;
reg pre4act2;
reg pre4rd;
reg pre4rd1;
reg pre4rd_else;
wire pre6rd;
reg pre5rd;
reg pre4pre;
reg pre4pre1,pre4pre2,pre4pre3;
reg [ 5:0] left;
// reg [ 3:0] row;
//reg [ 1:0] row;
reg fullpage;
//reg m16_r;
//reg pre4pre_no_m16;
wire [ 3:0] next_ca=pre3sda[6:3]+1;
MSRL16_1 i_pre6rd (.Q(pre6rd), .A(4'h1), .CLK(mclk0), .D(en && pre4rd && (left[5:0]!=0)));
MSRL16_1 i_predrun_on (.Q(predrun_on), .A(4'h7), .CLK(mclk0), .D(pre4act2));
MSRL16_1 i_predrun_off (.Q(predrun_off), .A(4'h6), .CLK(mclk0), .D(pre4pre3));
// MSRL16_1 i_dqs_re3_on (.Q(dqs_re3_on), .A(4'h5), .CLK(mclk0), .D(pre4act2));
// MSRL16_1 i_dqs_re3_off (.Q(dqs_re3_off),.A(4'h4), .CLK(mclk0), .D(pre4pre));
MSRL16_1 i_dqs_re3_on (.Q(dqs_re3_on), .A(4'h4), .CLK(mclk0), .D(pre4act2));
MSRL16_1 i_dqs_re3_off (.Q(dqs_re3_off),.A(4'h3), .CLK(mclk0), .D(pre4pre3));
always @ (negedge mclk0) begin
pre4act1 <= start;
pre5act2 <= pre4act1;
pre4act2 <= pre5act2; // not alway will generate "activate" command
//pre3act <= pre4act1 || (pre4act2 && (left[5] || left[4]));
pre3act <= pre4act1 | pre4act2;
pre4rd1 <= pre4act2;
pre5rd <= pre6rd;
// if (pre4act1) row[3:0] <= sa[3:0];
// if (pre4act1) row[1:0] <= sa[1:0];
if (pre5act2) fullpage <= left[5];
//if (pre5act2) m16_r <= m16 && !left[5];
pre4rd <= pre4act2 || (pre5rd && (!fullpage || (left[5:0]!=0)));
pre4rd_else <= (pre5rd && (!fullpage || (left[5:0]!=0)));
// pre4pre <= (left[5:0]==0) && (fullpage?pre5rd:pre4rd);
//pre4pre_no_m16 <= (left[5:0]==0) && (fullpage?pre5rd:pre4rd);
//pre4pre <= m16_r? pre4pre_no_m16:((left[5:0]==0) && (fullpage?pre5rd:pre4rd)); // extra delay for 16-bit mode (FPN)
pre4pre <= (left[5:0]==0) & (fullpage?pre5rd:pre4rd);
if (pre4act1) pre3sda[12:0] <= sa[21:9];
else if (pre4act2) pre3sda[12:0] <= pre3sda[12:0]+1;
else if (pre4rd1) pre3sda[12:0] <= {1'b0,sa[8:2],5'h0};
else if (pre4rd_else)
if (left[3:0]==len[4:1]) pre3sda[12:0] <= {1'b0,sa[8:2],5'h0};
else pre3sda[12:0] <= {pre3sda[12:3]+10'b1,3'h0};
else if (pre4pre) pre3sda[12:0] <= {pre3sda[12:11],1'b1,pre3sda[9:0]}; //set A10, others - don't care
if (pre4act1) pre3sdb[0] <= sa[0];
if (pre4act1) pre3sdb[1] <= sa[0] ^ sa[1];
else if (pre4act2 | pre4rd1 | (pre4rd_else & (left[3:0]==len[4:1]))) pre3sdb[1] <= ~pre3sdb[1];
if (pre4act1) left[5:0] <= {~(|len[4:0]), len[4:0]};
else if (pre4rd) left[5:0] <= left[5:0] - 1;
predrun <= en && !predrun_off && (predrun_on || predrun);
dqs_re3 <= en && !dqs_re3_off && (dqs_re3_on || dqs_re3);
inuse3 <= en && !pre3pre && (inuse3 || pre4act1);
// prenext <= (left[5:0]==6'h1) && (fullpage? pre6rd:(pre5rd || pre4act2));
//prenext <= (left[5:0]==6'h0) && (fullpage? pre6rd:(m16_r?(pre4rd || pre4act2):(pre5rd || pre4act2)));
prenext <= (left[5:0]==6'h0) && (fullpage? pre6rd:(pre5rd | pre4act2));
pre4pre1 <= pre4pre;
pre4pre2 <= pre4pre1;
pre4pre3 <= pre4pre2;
pre3pre <= pre4pre3;
pre3rd <= pre4rd;
end
endmodule
mcontr_line_wr.v 0 → 100644
View file @ 1727b764
/*
*! -----------------------------------------------------------------------------**
*! FILE NAME : mcontr_line_wr.v
*! DESCRIPTION: write sequence to sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: mcontr_line_wr.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:11:54 dzhimiev
*! 0. based on theora's mcontr_8chn.v, mcontr_line512_wr.v, mcontr_line512_rd.v
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
`timescale 1 ns / 1 ps
// need to take care of banks when switching from plane to plane in the same access.
module mcontr_line_wr (mclk0, // system clock, mostly negedge
en,
// interface to the output block RAM (x16). Will probably include 12->16 bit conversion here
predrun, //
// interface to SDRAM arbiter
start, // start atomic writing to SDRAM operation (5 cycles ahead of RAS command on the pads)
sa, // [16:0] - 13 MSBs ->RA, 4 LSBs - row in a chunk
len, // [ 4:0] - number of 32-byte groups to write, 0 - all 256bytes, for other values - (len*32+8) bytes
prenext, // 8 cycles ahead of possible next start_*?
// interface to SDRAM (through extra registers
pre3pre, // precharge command (3 ahead)
pre3wr, // read command (3 ahead)
pre3act, // activate command (3ahead)
pre3sda, //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
pre3sdb, //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
drive_sd3, // enable data to SDRAM (2 cycles ahead)
drive_dq3, // enable DQ outputs (one extra for FF in output buffer)
dmask3, // write mask - 1 bit as even number of words written (32-bit pairs)
inuse3 // SDRAM in use by this channel (sync with pre3***
);
input mclk0;
input en;
output predrun;
input start;
input [21:0] sa;
input [ 4:0] len;
output prenext;
// interface to SDRAM (through extra registers
output pre3pre; // precharge command (3 ahead)
output pre3wr; // write command (3 ahead)
output pre3act; // activate command (3ahead)
output [12:0] pre3sda; //[12:0] address to SDRAM - 3 cycles ahead of I/O pads
output [1:0] pre3sdb; //[ 1:0] bank to SDRAM - 3 cycles ahead of I/O pads
output drive_sd3; // enable data to SDRAM (2 cycles ahead)
output drive_dq3; // enable DQ outputs (one extra for FF in output buffer)
output dmask3; // write mask - 1 bit as even number of words written (32-bit pairs)
output inuse3; // SDRAm in use by this channel (sync with pre3***
reg pre3act;
reg pre3pre;
reg pre3wr;
reg [12:0] pre3sda;
reg [ 1:0] pre3sdb;
reg inuse3;
reg predrun;
reg drun;
wire predrun_off;
reg preprenext;
reg drive_sd3; // enable data to SDRAM (2 cycles ahead)
reg drive_dq3; // enable DQ outputs (one extra for FF in output buffer)
reg dmask3; // write mask - 1 bit as even number of words written (32-bit pairs)
wire drive_sd3_off;
reg drive_dq3_off;
reg pre4act1; // before first of 2 activate pulses
reg pre5act2;
reg pre4act2;
reg pre4wr;
reg pre4wr1;
reg pre4wr_else;
wire pre6wr;
reg pre5wr;
reg pre4pre;
reg [ 5:0] left;
reg fullpage;
reg pre4pre1,pre4pre2;
wire prenext;
assign prenext=predrun_off;
MSRL16_1 i_pre6wr (.Q(pre6wr), .A(4'h1), .CLK(mclk0), .D(en & pre4wr & (left[5:0]!=0)));
MSRL16_1 i_predrun_off (.Q(predrun_off), .A(4'h2), .CLK(mclk0), .D(preprenext));
MSRL16_1 i_drive_sd3_off (.Q(drive_sd3_off), .A(4'h2), .CLK(mclk0), .D(predrun_off));
always @ (negedge mclk0) begin
pre4act1 <= start;
pre5act2 <= pre4act1;
pre4act2 <= pre5act2; // not alway will generate "activate" command
pre3act <= pre4act1 | pre4act2;
pre4wr1 <= pre4act2;
pre5wr <= pre6wr;
if (pre5act2) fullpage <= left[5];
pre4wr <= pre4act2 || (pre5wr && (!fullpage || (left[5:0]!=0)));
pre4wr_else <= (pre5wr && (!fullpage || (left[5:0]!=0)));
drive_dq3_off <= fullpage?drive_sd3_off:pre4pre;
pre4pre <= drive_sd3_off;
if (pre4act1) pre3sda[12:0] <= sa[21:9]; // row 1
else if (pre4act2) pre3sda[12:0] <= pre3sda[12:0]+1; // row 2
else if (pre4wr1) pre3sda[12:0] <= {1'b0,sa[8:2],5'h0};
else if (pre4wr_else)
if (left[3:0]==len[4:1]) pre3sda[12:0] <= {1'b0,sa[8:2],5'h0};
else pre3sda[12:0] <= {pre3sda[12:3]+10'b1,3'h0};
else if (pre4pre2) pre3sda[12:0] <= {pre3sda[12:11],1'b1,pre3sda[9:0]}; //set A10, others - don't care
if (pre4act1) pre3sdb[0] <= sa[0];
if (pre4act1) pre3sdb[1] <= sa[0] ^ sa[1];
else if (pre4act2 | pre4wr1 | (pre4wr_else & (left[3:0]==len[4:1]))) pre3sdb[1] <= ~pre3sdb[1];
if (pre4act1) left[5:0] <= {~(|len[4:0]), len[4:0]};
else if (pre4wr) left[5:0] <= left[5:0] - 1;
predrun <= en & !predrun_off & (predrun | pre4act2);
drive_sd3 <= en & (!drive_sd3_off) & (drive_sd3 | pre4wr1);
drive_dq3 <= en & (!drive_dq3_off) & (drive_dq3 | pre4wr1);
inuse3 <= en & !pre3pre && (inuse3 | pre4act1);
drun <= predrun;
preprenext <= (left[5:0]==0) & (fullpage?pre6wr:pre5wr);
//predrun_off<= prenext;
dmask3 <= ~drun;
pre4pre1 <= pre4pre;
pre4pre2 <= pre4pre1;
pre3pre <= pre4pre2;
pre3wr <= pre4wr;
end
endmodule
mcontr_refresh.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** mcontr_refresh.v
**
** SDRAM refresh controller
** average interval (by datasheet) 7.8125usec,
** maximal interval - 9*7.8125usec (because of future DLL at AR cycles only)
**
** Copyright 2002-2004 Andrey Filippov
**
** -----------------------------------------------------------------------------**
** This file is part of X333
**
** X333 is free software - hardware description language (HDL) code; you can
** redistribute it and/or modify it under the terms of the GNU General Public License
** as published by the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** X333 is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with X333; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
** -----------------------------------------------------------------------------**
**
*/
`timescale 1 ns / 1 ps
// add some status outputs
module mcontr_refresh (clk0,
enrq,
init,
start,
rq,
rq_urgent,
prenext,
// interface to SDRAM (through extra registers
pre3refr, // precharge command (3 ahead)
inuse3 // SDRAm in use by this channel (sync with pre3***
);
input clk0;
input enrq;
input init;
input start;
output rq;
output rq_urgent;
output prenext;
output pre3refr;
output inuse3;
parameter REFRESHPERIOD=11'h3d0;
reg pre4refr;
reg pre3refr;
reg prenext;
wire inuse3=pre3refr;
reg [12:0] nRefrDue;
reg [10:0] rcntr;
reg [ 2:0] ucntr;
reg rtim;
reg rq;
reg rq_urgent;
always @ (negedge clk0) begin
pre4refr <= start;
pre3refr <= pre4refr;
prenext <= pre3refr;
if (init) ucntr[2:0] <=4'h0;
else if ((ucntr[2:0]!=3'h7) && rtim && !start) ucntr[2:0] <= ucntr[2:0]+1;
else if ((ucntr[2:0]!=3'h0) && start) ucntr[2:0] <= ucntr[2:0]-1;
if (init) nRefrDue <= {1'b1,12'b0};
else if ( start && !rtim) nRefrDue <= nRefrDue - 1;
else if (!start && rtim) nRefrDue <= nRefrDue + 1;
if (init | rtim) rcntr[10:0] <= REFRESHPERIOD;
else rcntr[10:0] <= rcntr[10:0]-1;
rtim <= !nRefrDue[12] && !(|rcntr[10:0]); // nRefrDue[12] to "saturate" number of refr. cycles due to 4096
rq <= !init && enrq && |nRefrDue[12:0];
rq_urgent <= !init && enrq && (nRefrDue[12] || (ucntr[2:0]==3'h7) || (rq_urgent && (ucntr[2:0]!=3'h0)));
end
endmodule
sdram_phase.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** sdram_phase.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X333
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
** $Log: sdram_phase.v,v $
** Revision 1.5 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
** Revision 1.1 2009/06/11 17:39:00 dzhimiev
** new initial version
** 1. simulation and board test availability
**
** Revision 1.1 2008/12/08 09:07:57 dzhimiev
** 1. set up of the data path for the transform
** 2. 2 read and 2 write channels
** 3. in snapshot mode - 3 frames output sequence -
** 1st - direct
** 2nd - stored 'direct' from the 1st buffer
** 3rd - stored '1st buffer' from the 2nd buffer
**
** Revision 1.1 2008/04/23 01:55:49 dzhimiev
** 1. added x359 files to src lists
** 2. x359 read/write DDR
** 3. x359 3 channels mux directly to out
** 4. x359 one channel through DDR and another directly frames switching at out
**
*/
// assumed CL=2.5
`timescale 1 ns / 1 ps
module sdram_phase (// wclk, // global CPU WE pulse
clk,
pre_wcmd, // decoded address - enables wclk
wd, // CPU write data [1:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
ph_err, // [1:0] 0 - no data (SDRAM reads) since last change (wclk*wcmd)
// 1 - clock is too late
// 2 - clock is too early
// 3 - OK (some measurements show too late, some - too early)
sclk0, // global clock, phase 0
/* sclk90, // global clock, phase 0 */
sclk270, // global clock, phase 0
enrd180, // read enable, latency 2 from the command, sync with sclk falling edge
udqsr90, // data from SDRAM interface pin UDQS strobed at rising sclk90
ldqsr90, // data from SDRAM interface pin LDQS strobed at rising sclk90
udqsr270, // data from SDRAM interface pin UDQS strobed at rising sclk270
ldqsr270, // data from SDRAM interface pin UDQS strobed at rising sclk270
dcm_rst, // set DCM phase to default
dcm_clk, // clock for changing DCM phase (now == sclk0)
dcm_en, // enable inc/dec of the DCM phase
dcm_incdec, // 0 - increment, 1 - decrement DCM phase
phase90sel // add phase 0 - 0, 1 - 90, 2 - 180, 3 - 270
);
input clk;
input pre_wcmd;
input [ 3:0] wd;
output [ 1:0] ph_err;
input sclk0, /*sclk90, */sclk270;
input enrd180;
input udqsr90, udqsr270, ldqsr90, ldqsr270;
output dcm_rst, dcm_clk, dcm_en, dcm_incdec;
output [ 1:0] phase90sel;
// reg wcmd;
wire wcmd = pre_wcmd;
reg [ 1:0] phase90sel=2'b0;
reg dcm_rst;
reg [1:0] dcm_drst;
reg dcm_en;
reg dcm_incdec;
reg enrd0, enrd180_d,enrd90,enrd270;
reg waslate90, waslate270, wasearly90, wasearly270;
// generate control pulses from CPU command
always @ (negedge clk) begin
// wcmd <=pre_wcmd;
dcm_drst[1:0] <= {dcm_drst[0], (wcmd && (wd[1:0] == 2'b11))};
dcm_rst <= (wcmd && (wd[1:0] == 2'b11)) || dcm_drst[0] || dcm_drst[1] ;
dcm_en <= wcmd && (wd[1]!=wd[0]);
dcm_incdec <= wcmd && wd[0];
if (wcmd && wd[2] && wd[3]) phase90sel[1:0] <= 2'h0;
else if (wcmd && wd[2]) phase90sel[1:0] <= phase90sel[1:0] +1;
else if (wcmd && wd[3]) phase90sel[1:0] <= phase90sel[1:0] -1;
end
// DCM control outputs (use automatic adjustment later?)
// assign dcm_clk=sclk0;
assign dcm_clk=!clk;//!sclk0; // DCM is triggered by posedge
// generate phase error signals
always @ (posedge sclk0) enrd0 <= enrd180;
always @ (negedge sclk0) enrd180_d <= enrd180;
// always @ (posedge sclk90) enrd90 <= enrd180_d;
always @ (negedge sclk270) enrd90 <= enrd180_d;
always @ (posedge sclk270) enrd270 <= enrd0;
// always @ (posedge sclk90 or posedge wcmd)
always @ (negedge sclk270 or posedge wcmd)
if (wcmd) begin
waslate90 <= 1'b0;
wasearly90 <= 1'b0;
end else begin
waslate90 <= waslate90 || (enrd90 && ( udqsr90 || ldqsr90));
wasearly90 <= wasearly90 || (enrd90 && (!udqsr90 || !ldqsr90));
end
always @ (posedge sclk270 or posedge wcmd)
if (wcmd) begin
waslate270 <= 1'b0;
wasearly270 <= 1'b0;
end else begin
waslate270 <= waslate270 || (enrd270 && (!udqsr270 || !ldqsr270));
wasearly270 <= wasearly270 || (enrd270 && ( udqsr270 || ldqsr270));
end
assign ph_err[1:0]= {(wasearly90 || wasearly270), (waslate90 || waslate270)};
endmodule
sensor.dat 0 → 100644
View file @ 1727b764
253 165 0ee 067 238 3cb 2c1 096 1af 25b 137 3c2 183 3d6 2e0 179 2e0 179 08e 284 0ea 09a 1a3 3fc 357 1d7 165 355 275 204 147 370 147 370 03f 2ad 2ba 050 314 1f6 283 109 1af 0d4 2e0 20a 167 27e 167 27e 056 3e4 29c 20f 1a8 2c8 265 256 2e8 1c5 236 18b 253 165
292 1dc 227 22f 084 1fc 0f2 3b6 333 122 2e5 0ab 0ed 32d 020 3eb 020 3eb 005 292 166 13a 187 305 220 1d1 07a 10b 077 292 3e2 2d4 3e2 2d4 145 30f 336 1ef 0fa 3f8 160 1c7 37a 367 34a 05f 3ac 3e3 3ac 3e3 23a 2ac 0e9 33d 1e0 2d4 026 367 0b9 146 0d9 238 292 1dc
1d7 2aa 2b6 3df 160 1a4 345 0da 375 15a 34b 055 35b 39e 398 31f 398 31f 33e 341 043 1e1 3e1 314 09e 252 302 14c 01e 259 059 20b 059 20b 119 0ef 184 343 04b 023 28b 141 015 071 39a 12b 011 24d 011 24d 099 3eb 017 0ef 317 04a 06e 08c 358 347 141 1ba 1d7 2aa
1fa 374 313 03b 3f0 309 3da 0ce 27d 395 29d 052 189 2a8 1bd 2e5 1bd 2e5 2da 2e3 203 2b5 328 3f1 1eb 2c1 0bb 316 1e4 39b 0d7 3c3 0d7 3c3 343 1e5 044 216 294 0fa 0eb 373 184 018 0c8 134 13a 306 13a 306 0a1 047 1a7 052 0b3 02a 2b3 011 1cd 0db 1a8 11a 1fa 374
126 324 049 20c 220 18b 119 2c7 376 3fd 369 3e4 0f8 1f0 32a 0d1 32a 0d1 08f 039 2a4 2e6 059 314 068 39c 12d 0b5 02b 359 1df 3e0 1df 3e0 0c6 0d1 125 287 007 055 3bd 052 2ec 3d4 1b7 1fb 02c 264 02c 264 142 2d8 099 391 2b8 2cf 0a9 083 17b 2c5 10f 378 126 324
05b 2b8 358 253 0f2 22a 000 3c5 360 392 2ad 00a 2a7 274 0e1 1e1 0e1 1e1 15c 044 326 374 072 17b 117 1e4 157 329 3f3 295 070 361 070 361 2a1 2b1 127 194 1a3 335 000 0de 14d 0a6 368 07e 1e7 168 1e7 168 37c 09e 1eb 3ae 227 138 350 2e2 362 203 078 1d2 05b 2b8
09a 331 141 20e 165 1e6 191 0c7 33c 354 16b 1c6 398 136 3e0 317 3e0 317 243 005 089 15f 075 027 0f6 29a 23b 372 23d 24e 189 348 189 348 1d6 087 14a 03e 068 29b 2b4 216 1a7 38c 2d9 1be 36b 110 36b 110 04f 299 29e 1a8 3fe 067 3a8 02d 082 397 0e1 129 09a 331
2e1 190 302 23e 078 1be 2ca 2cf 008 043 0a1 217 0ca 334 129 171 129 171 042 07a 3cd 1a7 161 018 107 2bc 0d8 290 007 384 22c 094 22c 094 364 352 28f 386 156 385 0d8 0fc 0fa 187 10b 2bb 1b8 25d 1b8 25d 0bb 1c9 3b3 27e 13e 15b 2b1 166 1db 07f 34c 27d 2e1 190
031 2d3 19c 3e3 32d 2b4 0ac 2dc 2c5 360 151 1fc 33d 170 1ba 1f1 1ba 1f1 05b 2a4 1f2 14c 035 24e 248 34c 22d 183 252 336 358 045 358 045 04b 011 1f4 06a 16d 2f5 36e 28f 046 397 2ff 075 1ce 24f 1ce 24f 1c0 32d 228 332 2e7 113 16b 38c 06e 1bd 0b8 2cf 031 2d3
18a 3fb 210 3fd 283 1c7 038 1ee 073 1a9 079 277 3f1 0e8 295 196 295 196 38c 384 3f7 14e 1f3 3c9 1bb 148 33c 14b 21e 266 20d 35a 20d 35a 18b 3c6 07a 3ec 1ad 1e9 375 3ce 08b 2bc 1b3 3ec 0ad 1e6 0ad 1e6 05e 3c7 2ff 0c2 1f9 091 0d6 39f 139 04f 224 31d 18a 3fb
3ed 208 15c 38c 37a 3f7 26c 105 213 01f 31a 087 3e6 29e 0b8 15f 0b8 15f 2d7 018 2de 2ae 399 18a 05e 1b2 104 2e8 06b 213 34a 2d5 34a 2d5 023 36f 321 30a 316 162 1ed 1bb 2c9 3f7 228 220 355 222 355 222 196 096 336 030 374 0d4 1f2 29f 13d 136 092 068 3ed 208
058 1fb 081 390 311 244 049 121 0a3 3c2 235 12c 01b 390 125 24e 125 24e 33a 161 3a6 26a 229 08f 333 188 084 35a 239 33d 011 3b5 011 3b5 115 00e 2ea 2c5 2a7 261 3d5 155 3ff 046 15f 011 2c6 003 2c6 003 266 29a 3cf 27b 058 2db 1bf 18c 17a 173 100 3b0 058 1fb
3cc 0d2 080 109 24a 1ae 2d0 342 124 192 2c8 165 192 0c0 0da 161 0da 161 1b7 060 34f 183 2a2 1d9 338 1cc 2be 3a1 088 2e3 161 2fa 161 2fa 160 2a2 0d3 01e 162 1e4 22f 39b 12f 0aa 056 2bf 000 089 000 089 3cf 2d3 1c8 0a2 1a5 3a8 13d 166 2f0 204 070 1f6 3cc 0d2
349 38e 257 0f7 224 335 2ff 068 097 290 1d5 234 14a 32c 0d9 39a 0d9 39a 34d 213 2d9 0f9 203 268 16f 37c 0b1 0bd 058 207 03a 1a4 03a 1a4 204 02a 1dd 013 046 0ed 1fa 18f 358 223 00e 32a 003 0b4 003 0b4 2d1 241 223 3a7 05c 03a 16c 32d 29f 3eb 3e1 038 349 38e
3d0 330 307 05a 39e 3d9 1d7 193 3fa 3ba 05a 098 043 3d6 220 1f7 220 1f7 0fb 37b 344 1cc 14e 33c 2d6 399 35c 3ae 2a9 1a8 19b 0b2 19b 0b2 001 1a8 308 3a5 053 07a 036 030 37a 1b2 188 252 3cf 184 3cf 184 06c 1e4 1de 089 17b 190 34c 3e1 188 026 052 377 3d0 330
25f 0b6 390 033 3ba 09a 059 3c3 04e 211 359 191 37d 3bc 1b1 17a 1b1 17a 3c3 199 190 0fc 182 155 06f 324 3c1 174 07b 2c6 286 126 286 126 056 01a 154 3d5 289 18c 1e3 07d 295 055 1c2 137 064 3f9 064 3f9 1a0 2bb 1fb 047 203 0ac 3dd 082 0a9 3b7 2c5 0b3 25f 0b6
3d0 330 307 05a 39e 3d9 1d7 193 3fa 3ba 05a 098 043 3d6 220 1f7 220 1f7 0fb 37b 344 1cc 14e 33c 2d6 399 35c 3ae 2a9 1a8 19b 0b2 19b 0b2 001 1a8 308 3a5 053 07a 036 030 37a 1b2 188 252 3cf 184 3cf 184 06c 1e4 1de 089 17b 190 34c 3e1 188 026 052 377 3d0 330
25f 0b6 390 033 3ba 09a 059 3c3 04e 211 359 191 37d 3bc 1b1 17a 1b1 17a 3c3 199 190 0fc 182 155 06f 324 3c1 174 07b 2c6 286 126 286 126 056 01a 154 3d5 289 18c 1e3 07d 295 055 1c2 137 064 3f9 064 3f9 1a0 2bb 1fb 047 203 0ac 3dd 082 0a9 3b7 2c5 0b3 25f 0b6
043 2a7 242 079 1d3 18a 3d3 270 0f1 225 12a 1f9 0b0 0de 018 0df 018 0df 0af 22f 1ba 2bb 192 13f 05e 051 145 1c4 0f8 10d 07c 0e0 07c 0e0 16e 330 0ff 211 020 3e2 18f 175 3bc 0bc 0f7 254 0d9 336 0d9 336 0d2 281 296 2b1 211 29d 3b6 3f3 162 066 022 256 043 2a7
0f6 1c1 030 025 273 0bf 2f8 2b4 309 330 00c 345 2ee 3b8 2cd 2f6 2cd 2f6 1db 120 18a 15f 36a 26c 0bb 390 28e 0de 2ce 21f 18b 0e7 18b 0e7 128 377 1cf 2b4 0fa 108 300 276 0bb 1b4 235 22d 292 23f 292 23f 26a 22d 236 3e4 23d 2cc 10b 248 368 34b 099 186 0f6 1c1
0b2 3c0 2f6 146 2b4 111 2c7 0fd 312 268 068 027 26d 2d0 0ca 331 0ca 331 11f 1c7 03b 360 32b 1de 248 33b 28f 3cd 125 1ad 323 354 323 354 03a 1b2 0c0 0f5 0fd 0b4 0e1 225 1b3 2c0 335 2c3 214 3ed 214 3ed 09b 00e 338 0f3 2d2 1c1 212 18a 2a6 284 011 3b4 0b2 3c0
077 1a5 395 0dc 395 380 03e 24b 20d 0cd 33c 19e 02d 324 311 292 311 292 37d 122 2cd 1be 1d4 095 207 053 24a 391 0fd 0b9 244 126 244 126 3a6 2e3 2d3 1d2 129 3e4 034 181 3a4 0e1 0f5 116 05f 140 05f 140 065 123 29a 2e0 0d0 07b 3c9 2b9 01d 313 389 1de 077 1a5
146 06e 30e 3e7 218 10c 05e 39e 0f8 35f 18a 0aa 12d 1b6 2a0 217 2a0 217 1f4 032 240 179 067 392 0f6 3d9 2be 12a 356 042 3ed 35d 3ed 35d 06b 009 106 24c 27e 399 1f8 189 38e 117 076 226 273 338 273 338 2c8 26e 15e 2aa 138 3f9 331 2d5 0cd 1f6 003 105 146 06e
01d 11c 25f 367 33c 2b5 028 1f6 0d4 31f 050 24a 26f 384 079 2c2 079 2c2 183 3f8 394 391 3e2 3d3 017 2cb 0eb 198 130 148 120 2f8 120 2f8 389 223 05a 364 1fc 0d4 32d 33f 271 063 2b9 2f3 150 2d5 150 2d5 0c4 0ee 082 150 108 13d 14a 2dd 1b6 02f 27d 229 01d 11c
1fd 0af 289 05c 000 17a 09a 253 2a1 10b 08f 380 0f2 190 19a 192 19a 192 32c 172 3c9 106 147 259 068 22b 1d0 1db 38b 0ca 2dc 0f9 2dc 0f9 200 233 1cf 218 0a3 093 0d2 3a2 14d 3c3 0bc 07d 1f6 117 1f6 117 359 1a3 108 3d4 141 146 314 3d3 3d8 2bc 3f9 24b 1fd 0af
3e6 028 08c 3c7 166 25d 2b5 1b5 360 224 348 14b 1b6 0d8 304 386 304 386 3ed 1a1 3df 2d9 195 024 2eb 2f7 26f 2f3 367 3ca 221 25f 221 25f 0cf 137 265 36a 372 3d8 3e9 3b1 121 038 380 3c4 165 2fe 165 2fe 387 18d 3ee 334 2e3 113 18f 2b6 034 29f 176 269 3e6 028
2d8 085 169 2a6 06d 25d 37a 11c 00f 36a 179 0aa 1bb 25e 1b8 1a0 1b8 1a0 0c8 186 0d6 208 1cb 234 09e 231 3c7 1e0 1c4 347 3ee 02a 3ee 02a 0f8 031 31d 058 36b 3a1 171 06e 2ef 2c2 006 1c8 09d 18a 09d 18a 24e 1ac 236 072 2ee 1a6 1bb 086 3c8 0d6 3f3 384 2d8 085
3d4 2c7 21e 1fa 215 27a 3e7 188 1af 1dd 024 29f 201 320 2b4 0de 2b4 0de 2bb 21f 3ae 394 2eb 189 283 0d7 2d7 3a2 3a2 041 145 35a 145 35a 37a 020 0f5 1e3 18d 0ef 26a 2d8 3b6 061 34c 389 09e 1bb 09e 1bb 0ae 300 0de 08d 262 3fe 098 243 395 263 072 29c 3d4 2c7
3d8 3ef 3ac 2c3 35d 3b4 0fe 3f8 141 27d 047 029 387 020 2fa 242 2fa 242 2c8 06d 167 07d 1f4 323 199 3eb 0a1 139 201 3b7 325 0ee 325 0ee 155 203 0ee 10c 2d8 0c3 3d4 3ee 076 216 253 207 268 091 268 091 3a7 288 0e8 084 23f 11a 326 0ed 09b 044 3f1 0b2 3d8 3ef
3e5 0fb 314 201 147 30b 3bd 16e 3c3 24b 2e4 248 34f 25c 388 2ca 388 2ca 1ed 171 301 1c3 3e5 003 2df 06b 224 3a5 1e1 2ab 28d 1e8 28d 1e8 389 2dc 008 2d1 04c 01b 2ae 0b2 22f 0df 21c 242 2fb 30c 2fb 30c 03a 146 352 159 385 1fc 265 184 3da 37a 372 2c4 3e5 0fb
0fb 2ec 154 0b4 0d2 17f 125 2e9 236 245 0f9 1fb 258 2d6 160 378 160 378 12c 229 17c 066 1c0 127 357 358 05f 3e6 043 21c 07f 347 07f 347 315 3a9 343 034 2e9 3f9 3fa 223 1e1 1bd 3a5 13a 357 22c 357 22c 365 039 11d 00b 334 3a3 355 108 252 106 3f3 1d3 0fb 2ec
01b 2c2 36d 3dc 2fd 010 237 169 19a 36c 387 044 1a2 28c 180 14a 180 14a 183 396 1d8 166 083 390 3ff 1b3 054 2fc 225 30a 1fa 20b 1fa 20b 0fb 16c 3a0 233 3af 15b 0b7 141 08c 1b0 3ef 3ef 07c 2f1 07c 2f1 229 061 34a 199 24d 30e 2f6 079 104 1e6 276 2df 01b 2c2
0fb 2ec 154 0b4 0d2 17f 125 2e9 236 245 0f9 1fb 258 2d6 160 378 160 378 12c 229 17c 066 1c0 127 357 358 05f 3e6 043 21c 07f 347 07f 347 315 3a9 343 034 2e9 3f9 3fa 223 1e1 1bd 3a5 13a 357 22c 357 22c 365 039 11d 00b 334 3a3 355 108 252 106 3f3 1d3 0fb 2ec
01b 2c2 36d 3dc 2fd 010 237 169 19a 36c 387 044 1a2 28c 180 14a 180 14a 183 396 1d8 166 083 390 3ff 1b3 054 2fc 225 30a 1fa 20b 1fa 20b 0fb 16c 3a0 233 3af 15b 0b7 141 08c 1b0 3ef 3ef 07c 2f1 07c 2f1 229 061 34a 199 24d 30e 2f6 079 104 1e6 276 2df 01b 2c2
3ae 3a3 2cf 212 347 270 161 107 36d 3f0 009 09c 305 31e 198 3a0 198 3a0 320 21c 031 095 044 069 11f 350 088 33b 2d1 0c1 1a0 0b4 1a0 0b4 2c3 272 17a 1df 0f6 0a0 193 2a8 063 208 354 07c 2a1 11f 2a1 11f 20b 216 215 173 20b 1ef 3ff 05a 06d 286 004 3f2 3ae 3a3
0f2 10e 24c 10e 1f6 375 316 19b 095 3cb 27b 339 153 1c8 0dc 006 0dc 006 1dc 05e 211 109 0ac 1e7 08b 15f 161 3a5 0b7 1a3 33f 30c 33f 30c 00c 208 05b 052 060 217 214 279 0f2 04f 0a3 025 0ea 278 0ea 278 133 112 3c6 076 0c7 26f 064 17f 202 2ba 08a 2f2 0f2 10e
13e 15d 2a3 180 047 197 174 034 3af 1d3 267 16b 0e2 0b0 36a 292 36a 292 2b0 054 2d2 0da 2fc 1a9 129 3da 0f2 3e4 31e 101 167 3c9 167 3c9 0af 394 15c 063 2f3 212 306 0f8 17a 2ab 1b2 08b 0fc 276 0fc 276 0f4 243 2d7 355 3ec 1b4 07a 391 0d1 344 012 0f0 13e 15d
193 191 0d2 066 339 1d6 17c 1d2 1b9 308 0cb 031 2b2 0d5 240 043 240 043 29e 2ff 374 108 036 0b0 3f7 3c3 03d 0f8 306 3dd 117 3ea 117 3ea 1ab 015 17e 310 1af 192 168 324 2fb 21d 382 2ae 3d7 219 3d7 219 24e 2a9 04a 312 07a 0bd 141 390 1d8 122 39b 2ea 193 191
2f1 2aa 1da 2c1 3cb 132 02c 375 3b4 06a 2a8 08d 3c3 336 260 218 260 218 2a4 160 0f7 293 159 3fc 1f7 218 041 3e1 16f 336 351 071 351 071 000 08a 1c1 15b 194 198 23c 1fc 274 3a3 314 38e 27b 261 27b 261 241 344 11d 0ac 371 08c 3b9 27c 218 156 024 1e1 2f1 2aa
259 1a9 2bc 191 2ff 0ab 286 21c 2a1 2fa 0ff 37e 115 0d5 0c8 113 0c8 113 3c4 075 05b 27b 364 08d 027 3da 1fd 19f 359 00c 114 25d 114 25d 0ae 1f5 325 042 3a2 322 281 282 0e7 03e 166 02b 1e8 04e 1e8 04e 1cd 114 252 122 1d1 220 0e2 155 291 0de 2af 2d5 259 1a9
0c9 38c 076 1d6 1d4 140 188 2c9 37e 3b6 0ce 204 3a7 2b0 27a 232 27a 232 2fc 140 2a0 1c0 359 363 389 20a 273 332 1c4 35e 360 2ae 360 2ae 0b4 154 2ab 0c6 0d8 332 337 1b5 353 0ee 379 185 31e 0e0 31e 0e0 1f2 119 0e7 176 09b 278 1bc 11a 043 0bc 03a 2c7 0c9 38c
342 154 009 090 14a 3f3 233 27b 34c 39f 317 11e 07b 1c9 074 277 074 277 14e 0bf 0c6 163 236 17f 11b 1a6 2a2 19a 1b0 22e 334 264 334 264 114 3a9 151 3e8 238 2c6 15e 094 2b8 2b4 24e 09c 31d 117 31d 117 3b0 052 1dd 2a7 0cd 296 347 2cd 02e 1ee 1c7 2b5 342 154
2c4 002 276 2bf 260 1c3 188 232 30b 3b5 0d8 1ce 090 31e 3b8 2e0 3b8 2e0 3b9 3f3 3cd 262 0fd 3df 1df 3b0 389 1d7 01d 17b 192 27e 192 27e 2cd 1f3 018 2a6 0c1 2e0 1f5 021 016 28e 2e3 270 2e5 1f3 2e5 1f3 007 3c1 235 1b4 368 379 283 36d 353 176 054 3a0 2c4 002
050 094 0bb 163 218 3b0 085 2ee 3bc 0f8 313 113 0e6 3b1 144 06f 144 06f 33c 3dd 0b5 1be 0ad 384 2d3 126 22a 0e9 20c 245 379 3fe 379 3fe 2df 131 000 201 173 07e 1fe 15b 06d 17d 239 001 376 074 376 074 3f7 065 2ed 39f 16c 220 070 3fa 2b0 052 0e3 288 050 094
0e4 00b 3d9 17c 171 2ba 02b 1af 25d 069 2c6 3ec 27d 080 21a 022 21a 022 0d9 17b 07e 077 245 16e 0f9 30a 384 3d0 07b 18b 1e9 3e3 1e9 3e3 24a 265 209 2fa 14e 0a1 278 142 0bd 081 151 24f 1d0 19a 1d0 19a 080 33e 107 166 3d9 38d 20e 174 346 384 073 06e 0e4 00b
181 367 0d0 00a 16a 3e1 17b 375 3ef 306 0f2 35b 255 28d 338 2fb 338 2fb 18e 1ce 028 38d 2c7 29d 14f 25a 096 38c 06b 04f 1e1 32d 1e1 32d 20d 28d 334 28f 152 04a 063 0d5 206 09a 129 25a 2f3 265 2f3 265 2a2 14c 181 00b 3af 0bf 05d 0db 215 00a 003 250 181 367
327 3a9 0a1 20e 305 025 173 140 172 1d0 298 05f 16d 2d6 1a0 1f8 1a0 1f8 25d 1d7 0b3 000 332 011 0d7 018 262 11d 2dc 390 063 2db 063 2db 32a 2ab 07f 1c2 27f 077 0be 116 148 2c9 2c2 122 3df 3d5 3df 3d5 35d 38f 15d 08d 1ee 2b5 05d 32f 01d 2e5 095 12f 327 3a9
2d7 1cf 04a 086 341 086 114 010 3e7 1c7 0b6 3f8 0c7 25d 250 21b 250 21b 044 294 31f 2d0 085 2cb 08f 142 1e7 183 0ce 04e 26e 3ef 26e 3ef 2a0 3be 2eb 191 1d4 22a 08b 304 383 00c 31d 3a7 194 2ea 194 2ea 3b1 307 199 3eb 396 271 30e 170 25e 116 327 20b 2d7 1cf
327 3a9 0a1 20e 305 025 173 140 172 1d0 298 05f 16d 2d6 1a0 1f8 1a0 1f8 25d 1d7 0b3 000 332 011 0d7 018 262 11d 2dc 390 063 2db 063 2db 32a 2ab 07f 1c2 27f 077 0be 116 148 2c9 2c2 122 3df 3d5 3df 3d5 35d 38f 15d 08d 1ee 2b5 05d 32f 01d 2e5 095 12f 327 3a9
2d7 1cf 04a 086 341 086 114 010 3e7 1c7 0b6 3f8 0c7 25d 250 21b 250 21b 044 294 31f 2d0 085 2cb 08f 142 1e7 183 0ce 04e 26e 3ef 26e 3ef 2a0 3be 2eb 191 1d4 22a 08b 304 383 00c 31d 3a7 194 2ea 194 2ea 3b1 307 199 3eb 396 271 30e 170 25e 116 327 20b 2d7 1cf
01a 1a0 05c 0ac 1ba 056 3ef 09d 2e9 2bb 3e7 040 25b 25e 018 360 018 360 291 30a 3a9 36f 3f6 094 2df 34f 0cb 1b3 1aa 175 3c4 189 3c4 189 117 2b3 2f6 2ad 2cc 25f 297 0db 20a 054 2b2 3a4 169 007 169 007 044 2ac 295 135 305 242 147 1c1 078 1a5 0e5 28e 01a 1a0
1ed 15a 169 2f8 27a 32b 034 181 322 166 1ea 02d 0b9 0d9 3ec 217 3ec 217 2dc 09b 399 1b3 2ee 261 15b 02e 133 36d 3a0 227 1f3 230 1f3 230 3f1 19a 3e6 2f0 0c6 025 228 37c 229 3eb 010 31d 042 3b0 042 3b0 0fc 0f8 255 208 051 312 0bc 1b6 19d 32a 17c 15e 1ed 15a
2ca 3f9 350 2b9 2da 31d 122 06a 14b 23e 165 3ae 057 390 30a 2f3 30a 2f3 141 3e2 26a 354 3ce 273 109 179 055 0fc 217 155 0aa 13d 0aa 13d 224 276 2f7 0d1 1e9 071 22a 0cb 240 397 12f 353 0e4 1fe 0e4 1fe 24d 179 376 2b7 206 2a6 3e2 298 3fb 103 113 32c 2ca 3f9
3af 27e 30f 0ef 3dc 12c 3ba 258 265 243 35a 3c5 237 385 270 2f3 270 2f3 2bf 1dd 11c 152 398 1ca 2e8 032 330 360 20f 001 0eb 3af 0eb 3af 0b0 246 129 14e 335 041 39d 1c7 351 058 310 146 04f 3f1 04f 3f1 137 12f 2f9 044 124 200 3b9 167 092 032 0ac 0f6 3af 27e
19d 1e7 1a7 29a 27f 258 0fa 04b 371 275 0c7 171 358 1b6 320 319 320 319 055 38d 0af 0ad 34a 167 3f7 157 2c3 399 088 32a 3b5 286 3b5 286 095 20c 37c 169 1aa 096 381 36f 25b 32e 2b1 1f6 383 289 383 289 2ba 119 1dc 3ae 2ab 21f 141 323 063 1b5 145 3bd 19d 1e7
194 335 018 0ba 3c2 3a1 1e3 343 16d 3d5 2ae 1b1 0ba 325 218 063 218 063 305 1f3 222 265 3e6 248 138 1e9 010 2a7 283 3d0 208 2c2 208 2c2 2d2 2c6 2f1 220 247 271 2d5 2c5 05e 11a 113 263 380 2c6 380 2c6 3d6 239 121 1f4 39b 002 17a 0cc 06c 28e 3e0 081 194 335
095 369 363 050 0a7 207 376 040 15a 361 20d 187 35d 0d0 05a 3d3 05a 3d3 3cd 20d 277 37b 26b 16e 3a9 2e9 016 18a 0fe 2f2 0e3 162 0e3 162 069 176 086 074 20e 2d0 29b 0c8 25a 31a 337 38d 146 1a8 146 1a8 18b 18e 1c6 018 0f4 0ab 164 362 1ae 3bb 17c 043 095 369
39e 381 086 25a 22d 289 2b1 042 038 21a 3e5 1f2 041 3b9 2e4 267 2e4 267 3af 0dc 2ad 0ed 3d8 3d9 04c 155 3d4 142 0fa 192 148 368 148 368 259 31b 13c 166 1fe 2b5 3d2 278 14f 22f 21b 274 1d5 02f 1d5 02f 0d9 018 0cd 319 3b6 119 1ff 3e4 129 23e 318 001 39e 381
3b0 07e 082 3d9 154 229 095 049 308 100 137 3f2 065 0de 2b8 121 2b8 121 3a9 361 3c4 3bc 12f 289 01f 22f 04c 2cf 377 0af 036 1d3 036 1d3 1a2 0b4 213 1f4 317 31e 37a 0d4 23d 359 2c0 018 22d 35b 22d 35b 2c0 2d7 334 3f6 0e2 24b 04b 354 3dd 315 1b6 0bc 3b0 07e
1cb 360 058 1cd 31b 1e6 223 155 2c8 113 301 086 0cb 141 0d4 0ff 0d4 0ff 0bd 29a 2bc 0e8 36f 27e 024 275 27d 331 175 149 2ad 1a3 2ad 1a3 344 343 00b 320 259 10d 292 0de 224 399 227 179 34e 02c 34e 02c 040 2cb 1fd 3b1 176 143 148 2b1 2cb 342 254 374 1cb 360
2f0 128 106 136 084 2c0 059 066 079 354 245 0b0 272 1e0 23a 303 23a 303 3e9 388 095 171 397 0b9 159 329 367 368 3f4 060 1ac 3d7 1ac 3d7 03e 3c6 025 1e8 0c4 180 21c 395 204 3ed 14e 397 238 3a2 238 3a2 259 0f4 226 349 273 300 1f6 2fb 2f1 3c3 1f4 12a 2f0 128
01d 2d4 38d 314 28e 1b7 039 27c 11b 0c1 001 16f 25a 3bd 3e8 02b 3e8 02b 22f 32c 24f 257 2a9 238 0c0 149 009 074 3f4 2f3 235 171 235 171 192 33f 35f 34d 358 178 317 1f8 2dd 156 136 372 3eb 2bd 3eb 2bd 20b 251 0b1 3bd 0d9 081 355 132 150 19a 194 2dc 01d 2d4
253 165 0ee 067 238 3cb 2c1 096 1af 25b 137 3c2 183 3d6 2e0 179 2e0 179 08e 284 0ea 09a 1a3 3fc 357 1d7 165 355 275 204 147 370 147 370 03f 2ad 2ba 050 314 1f6 283 109 1af 0d4 2e0 20a 167 27e 167 27e 056 3e4 29c 20f 1a8 2c8 265 256 2e8 1c5 236 18b 253 165
292 1dc 227 22f 084 1fc 0f2 3b6 333 122 2e5 0ab 0ed 32d 020 3eb 020 3eb 005 292 166 13a 187 305 220 1d1 07a 10b 077 292 3e2 2d4 3e2 2d4 145 30f 336 1ef 0fa 3f8 160 1c7 37a 367 34a 05f 3ac 3e3 3ac 3e3 23a 2ac 0e9 33d 1e0 2d4 026 367 0b9 146 0d9 238 292 1dc
sensor12bits.v 0 → 100644
View file @ 1727b764
module sensor12bits (MCLK, // Master clock
MRST, // Master Reset - active low
ARO, // Array read Out.
ARST, // Array Reset. Active low
OE, // output enable active low
SCL, // I2C clock
SDA, // I2C data
OFST, // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
D, // [11:0] data output
DCLK, // Data output clock
BPF, // Black Pixel Flag
HACT, // Horizontal Active
VACT, // Vertical Active
VACT1);
input MCLK, // Master clock
MRST, // Master Reset - active low
ARO, // Array read Out.
ARST, // Array Reset. Active low
OE, // output enable active low
SCL; // I2C clock
inout SDA; // I2C data
input OFST; // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
output [11:0] D; // data output
output DCLK, // Data output clock
BPF, // Black Pixel Flag
HACT, // Horizontal Active
VACT, // Vertical Active
VACT1; // 1-clock VACT
parameter ramp = 1; // 1 - ramp, 0 - random
parameter lline = 192; // 1664;// line duration in clocks
parameter ncols = 66; //58; //56; // 129; //128; //1288;
parameter nrows = 18; // 16; // 1032;
parameter nrowb = 1; // number of "blank rows" from vact to 1-st hact
parameter nrowa = 1; // number of "blank rows" from last hact to end of vact
parameter nAV = 24; //240; // clocks from ARO to VACT (actually from en_dclkd)
parameter nbpf = 20; //16; // bpf length
parameter ngp1 = 8; // bpf to hact
parameter nVLO = 1; // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
parameter tMD = 4; //
parameter tDDO = 2; // some confusion here - let's assume that it is from DCLK to Data out
parameter tDDO1= 5;
parameter s_stop= 0;
parameter s_preVACT= 1;
parameter s_firstline=2;
parameter s_BPF= 3;
parameter s_preHACT= 4;
parameter s_HACT= 5;
parameter s_afterHACT=6;
parameter s_lastline= 7;
parameter s_frame_done=8;
parameter t_preVACT= nAV; // 240
parameter t_firstline=nrowb*lline+1; // 1664
parameter t_BPF= nbpf; // 16
parameter t_preHACT= ngp1; // 8
parameter t_HACT= ncols; // 1288
parameter t_afterHACT=lline-nbpf-ngp1-ncols; // 352
parameter t_lastline= nrowa*lline+1; // 1664
reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
// $readmemh("sensor.dat",sensor_data);
reg c; // internal data out clock
//reg [9:0] id; // internal pixel data (sync do DCLK)
//wire [9:0] nxt_d; // will be calculated later - next pixel data
reg stopped;
wire #1 stoppedd=stopped;
reg ibpf, ihact, ivact, ivact1;
reg arst1; //
reg [11:0] col; // current row
reg [11:0] row; // current column;
reg [3:0] state;
reg [15:0] cntr;
wire [11:0] cold;
wire [11:0] rowd;
wire [3:0] stated;
wire [15:0] cntrd;
wire NMRST=!MRST;
parameter new_bayer=0; // 0 - old (16x16), 1 - new (18x18)
wire [5:0] row_index=row[5:0]-new_bayer;
wire [5:0] col_index=col[5:0]-new_bayer;
// random
integer seed;
integer r;
reg c_rand;
reg [11:0] d_rand;
assign #1 cold= col;
assign #1 rowd= row;
assign #1 stated= state;
assign #1 cntrd= cntr;
//assign #tDDO D = OE? {10{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[9:0] + row[9:0]):(d_rand)): 10'b0); // just test pattern
//assign #tDDO D = OE? {10{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[9:0] + row[9:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 10'b0); // just test pattern
//assign #tDDO D = OE? {12{1'bz}}: ((ihact || ibpf)? ((ramp)?(col[11:0] + row[11:0]):(sensor_data[{row_index[5:0],col_index[5:0]}])): 12'b0); // just test pattern
wire [11:0] strange_value=sensor_data[{row_index[5:0],col_index[5:0]}];
assign #tDDO D = OE? {12{1'bz}}: ((ihact || ibpf)? ((ramp)?({row[11:8],8'h0} + col[11:0]):(strange_value)): 12'b0); // just test pattern
//assign #tDDO BPF = ibpf;
//assign #tDDO HACT= ihact;
//assign #tDDO VACT= ivact;
assign #tDDO1 BPF = ibpf;
assign #tDDO1 HACT= ihact;
assign #tDDO1 VACT= ivact;
assign #tDDO1 VACT1= ivact && !ivact1;
assign DCLK= c;
initial begin
//parameter ramp = 1; // 0 - ramp, 1 - random
//parameter lline = 192; // 1664;// line duration in clocks
//parameter ncols = 58; //56; // 129; //128; //1288;
//parameter nrows = 16; // 1032;
$display ("sensor parameters");
$display (" -- ramp = %d (0 - random, 1 - ramp)",ramp);
$display (" -- lline = %d (line duration in clocks)",lline);
$display (" -- ncols = %d (numer of clocks in HACT)",ncols);
$display (" -- nrows = %d (number of rows)",nrows);
$display (" -- t_afterHACT = %d ",t_afterHACT);
$display (" -- t_preHACT = %d ",t_preHACT);
$display (" -- new_bayer = %d ",new_bayer);
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
$readmemh("sensor.dat",sensor_data);
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
arst1= 0;
seed= 1;
d_rand= 0;
// row=0;
// col=0;
end
always @ (NMRST) begin
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
arst1=0;
// row=0;
// col=0;
end
always begin
@ (posedge MCLK) begin
#tMD c = !stoppedd;
end
@ (negedge MCLK) begin
#tMD c = 1'b0;
end
end
always @ (posedge MCLK) begin
#1 stopped= !arst1 || (stoppedd && !ARO) ;
#1 arst1=ARST;
end
always @ (posedge c) ivact1 = ivact;
always @ (posedge stoppedd or posedge c) begin
if (stoppedd) begin
{ibpf,ihact,ivact}=0;
row=0;
col=0;
// id=0;
state=0;
cntr=0;
end else if (|cntrd != 0) begin
#1 cntr=cntrd-1;
if (BPF || HACT) col=cold+1;
end else begin
case (stated)
s_stop: begin
cntr= t_preVACT-1;
state= s_preVACT;
end
s_preVACT: begin
ivact= 1'b1;
cntr= t_firstline-1;
state= s_firstline;
end
s_firstline: begin
ibpf= 1'b1;
col= 0;
row= 0;
cntr= t_BPF-1;
state= s_BPF;
end
s_BPF: begin
ibpf= 1'b0;
cntr= t_preHACT-1;
state= s_preHACT;
end
s_preHACT: begin
ihact= 1'b1;
col= 0;
cntr= t_HACT-1;
state= s_HACT;
end
s_HACT: begin
ihact= 1'b0;
row= rowd+1;
cntr= t_afterHACT-1;
state= s_afterHACT;
end
s_afterHACT:
if (rowd == nrows) begin
cntr= t_lastline-1;
state= s_lastline;
end else begin
ibpf= 1'b1;
col= 0;
cntr= t_BPF-1;
state= s_BPF;
end
s_lastline: begin
ivact= 1'b0;
state= s_frame_done;
cntr=nVLO;
end
s_frame_done: if (OFST) begin
ivact= 1'b1;
cntr= t_firstline-1;
state= s_firstline;
end
endcase
end
// random data
seed=$random(seed);
r=(seed & 'h7fff);
r=(r * r) >> 20; // 10 bits
c_rand=seed>>16; // sign
d_rand=c_rand?(D+(((1023-d_rand)*r)>>10)):(d_rand-((d_rand*r)>>10));
end
endmodule
sensor_phase359.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** sensor_phase353.v
**
** Phase conpensating for the sesnor data (separate for data and hact/vact)
**
** Copyright (C) 2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module sensor_phase353 (cclk, // command clock (posedge, invert on input if needed)
wcmd, // write command
cmd, // CPU write data [5:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
// 10 - increase hact/vact phase
// 20 - decrease hact/vact phase
// 30 - reset hact/vact phase
HACT, // sensor HACT I/O pin (input), used to reset FIFO
VACT, // sensor VACT I/O pin (input)
DI, // sensor D[DATA_WIDTH-1:0] i/o pins (input), strobed @posedge gclk_idata and en_idata
debug, // 2-bit debug mode input
hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
hact_regen, // 0 - use hact from sensor, 1 - regenerate using hact_lengh
mode_12bits,// input, 1 - enable 12/14 bit mode, 0 - 10 bit mode
mode_14bits,// input, 1 - enable 14 bit mode, 0 - 12/10 bit mode
mode_alt, // enable alternative vact/hact input (sync to data)
sync_alt, // alternative HACT/VACT input pad (10347) (VACT - 1 clock, HACT >1)
iclk, // DCM input clock (GCLK)
sclk, // global FIFO output clock (posedge)
shact, // hact - sync to sclk
svact, // vact - sync to sclk (single cycle)
fvact,
sdo, // data output[DATA_WIDTH-1:0], sync to sclk
clkout,
dcm_done, // DCM command done
status, // dcm status (bit 1 - dcm clkin stopped)
locked); // DCM locked
/*in UCF
NET "i_sensorpads/i_sensor_phase/gclk_idata" TNM_NET = "TNM_GCLK_IDATA";
NET "i_sensorpads/i_sensor_phase/en_idata" TNM_NET = "TNM_EN_IDATA";
TIMESPEC "TS_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_GCLK_IDATA" TIG;
TIMESPEC "TS_GCLK_IDATA_PCLK" = FROM "TNM_GCLK_IDATA" TO "TNM_PCLK" TIG;
TIMESPEC "TS_DOUBLECYC_IDATA" = FROM "TNM_EN_IDATA" TO "TNM_EN_IDATA" "TS_CLK1";
NET "i_sensorpads/i_sensor_phase/phase_hact_sel_sync*" TIG;
NET "i_sensorpads/i_sensor_phase/mode_alt_sync" TIG;
NET "i_sensorpads/i_sensor_phase/mode_12bits_sync" TIG;
NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG;
NET "hact_length*" TIG;
*/
parameter IS_SIMUL=0;
//synthesis translate_off
parameter IS_SIMUL=1;
//synthesis translate_on
input cclk; // command clock (posedge, invert on input if needed)
input wcmd; // write command
input [5:0] cmd; // CPU write data [5:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
// 10 - increase hact/vact phase
// 20 - decrease hact/vact phase
// 30 - reset hact/vact phase
input HACT; // sensor HACT I/O pin (input), used to reset FIFO
input VACT; // sensor VACT I/O pin (input)
input [11:0] DI; // sensor D11:0], after IBUF (IOBUF)
input [1:0] debug; // 2-bit debug mode input, connect to 2'b0 if not needed
input [13:0] hact_length;// [13:0] WOI width (to overwrite sensor HACT duration)
input hact_regen; // 0 - use hact from sensor, 1 - regenerate using hact_lengh
input mode_12bits;// input, 1 - enable 12/14 bit mode, 0 - 10 bit mode, use 1'b1 in 10359
input mode_14bits;// input, 1 - enable 14 bit mode, 0 - 12/10 bit mode, use 1'b0 in 10359
input mode_alt; // enable alternative vact/hact input (sync to data), use 1'b0 in 10359
input sync_alt; // alternative HACT/VACT input pad (10347) (VACT - 1 clock, HACT >1)
input iclk; // global sensor input clock (posedge) - the clock that goes to all 3 sensors
input sclk; // global FIFO output clock (posedge)
output shact; // hact - sync to sclk
output svact; // vact - sync to sclk
output fvact; // vact fall
output [13:0] sdo; // data output[DATA_WIDTH-1:0], sync to sclk (Use {pxdo[11:0],unused[1:0]} in 10359
output clkout;
output dcm_done; // DCM command done
output [7:0] status; // DCM command done
output locked; // DCM locked
wire dcm_rst_cmd;
reg [2:0] dcm_drst=0;
reg dcm_en=0;
reg dcm_incdec=0;
reg dcm_done=0;
wire dcm_done_dcm; // single-cycle
reg dcm_rst=0;
reg [2:0] dcm_reset_done=0;
reg [1:0] phase90sel=0;
reg [2:0] phase_hact_sel=0;
wire locked;
wire dcm_out0,dcm2x,dcm2x180;
wire gclk_idata;
reg en_idata=0;
wire pre_pre_en_idata, pre_pre_en_idata90;
reg pre_en_idata=0;
reg inv_gclk_idata=0;
reg inv_en_idata=0;
wire [7:0] status;
// reg reset_fifo_in_cntr; // only for simulation;
wire reset_fifo_in_cntr; // only for simulation;
FD i_dcm_rst_cmd(.Q(dcm_rst_cmd), .D((wcmd && (cmd[1:0] == 2'b11)) || (dcm_rst_cmd && !dcm_drst[2])), .C(cclk)) ;
always @ (posedge cclk) begin
dcm_reset_done[2:0] <= {dcm_reset_done[1] & ~dcm_reset_done[0], dcm_reset_done[0], dcm_rst}; // sync to cclkl end of dcm reset
dcm_en <= wcmd && (cmd[1]!=cmd[0]);
dcm_incdec <= wcmd && cmd[0];
if (wcmd) begin
if (cmd[2] && cmd[3]) phase90sel[1:0] <= 2'h0;
else if (cmd[2]) phase90sel[1:0] <= phase90sel[1:0] +1;
else if (cmd[3]) phase90sel[1:0] <= phase90sel[1:0] -1;
end
if (wcmd) begin
if (cmd[4] && cmd[5]) phase_hact_sel[2:0] <= 3'h0;
else if (cmd[4]) phase_hact_sel[2:0] <= phase_hact_sel[2:0] +1;
else if (cmd[5]) phase_hact_sel[2:0] <= phase_hact_sel[2:0] -1;
end
// if (wcmd) reset_fifo_in_cntr <= IS_SIMUL && (cmd[5:0]==6'h3f);
end
always @ (posedge iclk) begin
dcm_drst[2:0] <= dcm_drst[2]? 3'b0:{dcm_drst[1], dcm_drst[0], dcm_rst_cmd};
dcm_rst <= dcm_drst[0] || dcm_drst[1] || dcm_drst[2] ;
end
// make dcm_done behave as dcm_ready
always @ (posedge cclk)
if (wcmd && |cmd[2:0]) dcm_done <=1'b0;
else if (dcm_done_dcm || dcm_reset_done[2]) dcm_done <=1'b1;
/// DCM to compensate sensor delays. Adjustment for data phase - both fine and 90-degrees, hact/vact - 90-degree steps relative to data
always @ (posedge gclk_idata) begin
inv_gclk_idata <= phase90sel[0]; /// TODO: check polarities. Make them TIG?
inv_en_idata <= phase90sel[1]; /// TODO: check polarities. Make them TIG?
pre_en_idata <=inv_gclk_idata?pre_pre_en_idata90:pre_pre_en_idata; /// adjust tap
en_idata <= pre_en_idata ^ inv_en_idata;
end
BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata));
DCM_SP #(
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), //96Hz
.CLKOUT_PHASE_SHIFT("VARIABLE"),// Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) i_dcm_sensor(
.CLKIN (iclk),
.CLKFB (dcm_out0),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (cclk),
.DSSEN (1'b0),
.CLK0 (dcm_out0),
.CLK90 (pre_pre_en_idata), // adjust tap
.CLK180 (pre_pre_en_idata90), // adjust tap
.CLK270 (),
.CLKDV (),
.CLK2X (dcm2x),
.CLK2X180 (dcm2x180),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE (dcm_done_dcm));
// Preventing skipping VACT/HACT after DCM reset (disabling update of the fifo output address:
reg [1:0] dcm_in_locked=0; // syncing to sclk
reg [3:0] dcm_locked_cntr=0; // counter that extends !locked to the fifo size
reg dcm_fifo_locked=0; // safe to reset fifo output address
always @ (posedge sclk) begin
dcm_in_locked[1:0] <= {dcm_in_locked[0],locked};
if (!dcm_in_locked[1]) dcm_fifo_locked <= 1'b0;
else if (dcm_locked_cntr[3:0]==4'h0) dcm_fifo_locked <= 1'b1;
if (!dcm_in_locked[1]) dcm_locked_cntr[3:0] <= 4'hf;
else if (!dcm_fifo_locked) dcm_locked_cntr[3:0] <= dcm_locked_cntr[3:0]-1;
end
// reg [11:0] idi;
wire [11:0] idi;
reg [13:0] idi14=0;
wire hact_q0, vact_q0;
// wire hact_q1,vact_q1;
reg hact_q1=0,vact_q1=0;
wire sync_alt_d0;
reg [2:1] sync_alt_d=0;
reg [3:0] hact_q1_d=0;
reg [3:0] hact_q0_d=0;
reg [3:0] vact_q1_d=0;
reg [3:0] vact_q0_d=0;
reg hact_vd=0; // variable delay, each clock cycle
reg vact_vd=0; // variable delay, each clock cycle
reg hact_selected=0; // selected between normal and alt hact
reg vact_selected=0; // selected between normal and alt vact
reg [1:0] hact_selected_d=0;
reg hact_selected_2_cycles=0;
reg [1:0] vact_selected_d=0;
reg vact_selected_2_cycles=0;
wire alt_hact;
wire alt_vact;
reg [2:0] phase_hact_sel_sync=0;
reg mode_alt_sync=0;
reg mode_12bits_sync=0;
reg mode_14bits_sync=0;
reg svact=0,shact=0;
reg fvact=0;
reg [13:0] sdo=0;
wire[13:0] pre_sdo;
wire pre_shact;
wire pre_svact; ///nominally 2-cycle long output from FIFO (can be 1 or 3 long)
reg pre_svact_d=0;
wire ihact,ivact;
reg [13:0] hact_count=0;
reg pre_shact_d=0;
reg [13:0] hact_length_sync=0;
reg hact_regen_sync=0; // sync to output
reg hact_regen_isync=0; // sync to gclk_idata
reg hact_count_zero=0;
assign alt_hact=sync_alt_d[1] && (sync_alt_d0 || sync_alt_d[2]); /// already controlled by mode_alt
assign alt_vact=sync_alt_d[1] && !sync_alt_d0 && !sync_alt_d[2]; /// already controlled by mode_alt
//synthesis translate_off
wire vact_or_hact= VACT || HACT;
reg sim_rst=0;
always @ (negedge glbl.GSR or posedge vact_or_hact) begin
if (vact_or_hact) sim_rst <= 1'b0;
else sim_rst <= 1'b1;
end
assign reset_fifo_in_cntr=glbl.GSR || sim_rst;
//synthesis translate_on
wire ihact00,ivact00;
/// some are double cycle
IBUF i_hact (.I(HACT), .O(ihact));
IBUF i_vact (.I(VACT), .O(ivact));
always @ (posedge gclk_idata) begin
hact_q1 <= ihact00;
vact_q1 <= ivact00;
hact_q0_d[3:0]<={hact_q0_d[2:0],hact_q0};
hact_q1_d[3:0]<={hact_q1_d[2:0],hact_q1};
vact_q0_d[3:0]<={vact_q0_d[2:0],vact_q0};
vact_q1_d[3:0]<={vact_q1_d[2:0],vact_q1};
end
always @ (posedge gclk_idata) if (en_idata) begin
// HACT delay -3..+4 90-degree steps, positive hact arrives later than data
{vact_vd,hact_vd} <= phase_hact_sel_sync[2]?
(phase_hact_sel_sync[1]?
(phase_hact_sel_sync[0]?{vact_q1_d[2],hact_q1_d[2]}:{vact_q0_d[3],hact_q0_d[3]}):
(phase_hact_sel_sync[0]?{vact_q1_d[3],hact_q1_d[3]}:{vact_q0_d[0],hact_q0_d[0]})):
(phase_hact_sel_sync[1]?
(phase_hact_sel_sync[0]?{vact_q1_d[0],hact_q1_d[0]}:{vact_q0_d[1],hact_q0_d[1]}):
(phase_hact_sel_sync[0]?{vact_q1_d[1],hact_q1_d[1]}:{vact_q0_d[2],hact_q0_d[2]}));
end
IDDR2 i_ihact (.Q0(hact_q0),.Q1(ihact00),.C0(gclk_idata),.C1(!gclk_idata),.CE(1'b1), .D(ihact), .R(1'b0), .S(1'b0) );
IDDR2 i_ivact (.Q0(vact_q0),.Q1(ivact00),.C0(gclk_idata),.C1(!gclk_idata),.CE(1'b1), .D(ivact), .R(1'b0), .S(1'b0) );
// FD i_hact_q1 (.C(gclk_idata), .D(ihact00), .Q(hact_q1));
// FD i_vact_q1 (.C(gclk_idata), .D(ivact00), .Q(vact_q1));
FDCE i_sync_alt_d0 (.Q(sync_alt_d0), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(sync_alt));
FDCE i_idi_0 (.Q(idi[ 0]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 0]));
FDCE i_idi_1 (.Q(idi[ 1]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 1]));
FDCE i_idi_2 (.Q(idi[ 2]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 2]));
FDCE i_idi_3 (.Q(idi[ 3]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 3]));
FDCE i_idi_4 (.Q(idi[ 4]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 4]));
FDCE i_idi_5 (.Q(idi[ 5]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 5]));
FDCE i_idi_6 (.Q(idi[ 6]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 6]));
FDCE i_idi_7 (.Q(idi[ 7]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 7]));
FDCE i_idi_8 (.Q(idi[ 8]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 8]));
FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9]));
FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10]));
FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11]));
// synthesis attribute IOB of i_sync_alt_d0 is "TRUE"
// synthesis attribute IOB of i_idi_0 is "TRUE"
// synthesis attribute IOB of i_idi_1 is "TRUE"
// synthesis attribute IOB of i_idi_2 is "TRUE"
// synthesis attribute IOB of i_idi_3 is "TRUE"
// synthesis attribute IOB of i_idi_4 is "TRUE"
// synthesis attribute IOB of i_idi_5 is "TRUE"
// synthesis attribute IOB of i_idi_6 is "TRUE"
// synthesis attribute IOB of i_idi_7 is "TRUE"
// synthesis attribute IOB of i_idi_8 is "TRUE"
// synthesis attribute IOB of i_idi_9 is "TRUE"
// synthesis attribute IOB of i_idi_10 is "TRUE"
// synthesis attribute IOB of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_sync_alt_d0 is "TRUE"
// synthesis attribute NODELAY of i_idi_0 is "TRUE"
// synthesis attribute NODELAY of i_idi_1 is "TRUE"
// synthesis attribute NODELAY of i_idi_2 is "TRUE"
// synthesis attribute NODELAY of i_idi_3 is "TRUE"
// synthesis attribute NODELAY of i_idi_4 is "TRUE"
// synthesis attribute NODELAY of i_idi_5 is "TRUE"
// synthesis attribute NODELAY of i_idi_6 is "TRUE"
// synthesis attribute NODELAY of i_idi_7 is "TRUE"
// synthesis attribute NODELAY of i_idi_8 is "TRUE"
// synthesis attribute NODELAY of i_idi_9 is "TRUE"
// synthesis attribute NODELAY of i_idi_10 is "TRUE"
// synthesis attribute NODELAY of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_ihact is "TRUE"
// synthesis attribute NODELAY of i_ivact is "TRUE"
reg [1:0] shact_zero=0; // shact was zero (inactive), sync to gclk_data
always @ (posedge gclk_idata) if (en_idata) begin
idi14[13:4] <= idi[11:2];
idi14[ 3:2] <= (mode_12bits_sync || mode_14bits_sync)? idi[1:0]:2'h0;
idi14[ 1:0] <= mode_14bits_sync? {vact_q0_d[0],hact_q0_d[0]}:2'h0;
sync_alt_d[2:1]<={sync_alt_d[1], sync_alt_d0 & mode_alt_sync}; ///sync_alt_d[0] - IOB
phase_hact_sel_sync[2:0] <= phase_hact_sel[2:0];
mode_14bits_sync <= mode_14bits;
mode_12bits_sync <= mode_12bits;
// hact_regen_isync <= hact_regen;
// only update hact_regen_isync when HACT (both input and output from fifo) are inactive (to prevent short lines)
if ((!hact_q0_d[0]) && shact_zero[1]) hact_regen_isync <= hact_regen;
//shact_zero[1]
//hact_q0_d[3:0]
mode_alt_sync <= mode_alt;
hact_selected <= mode_alt_sync? alt_hact : hact_vd;
vact_selected <= mode_alt_sync? alt_vact : vact_vd;
///if (hact_regen_isync==0) will copy hact to hact_selected_2_cycles
hact_selected_d[1:0]<={hact_selected_d[0], hact_selected && hact_regen_isync };
hact_selected_2_cycles <= (hact_selected && !hact_selected_d[0]) ||
(hact_selected_d[0] && !hact_selected_d[1]);
vact_selected_d[1:0]<={vact_selected_d[0],vact_selected};
vact_selected_2_cycles <= (vact_selected && !vact_selected_d[0]) ||
(vact_selected_d[0] && !vact_selected_d[1]);
//vact_selected_2_cycles <= vact_selected; //(debug[0] || !hact_selected && !hact_selected_d[0] && !hact_selected_d[1]) && ((vact_selected && !vact_selected_d[0]) || (vact_selected_d[0] && !vact_selected_d[1]));
end
//phase_hact_sel==3'h0 - delay by 2 cycles from data
reg [3:0] fifo_data_in_addr=0;
reg [3:0] fifo_hact_in_addr=0;
reg [3:0] fifo_data_in_addr_saved=0;
reg ihact_rst_in=0;
wire reset_rq;
reg rq=0;
reg reset_out_fifo=0;
reg [2:0] pre_reset_out_fifo=0;
assign reset_rq= reset_out_fifo || (IS_SIMUL && reset_fifo_in_cntr) ;
//glbl.GSR
always @ (posedge gclk_idata) if (en_idata) begin
/// input FIFO counter is only reset for the simulation
if (IS_SIMUL && reset_fifo_in_cntr) fifo_data_in_addr[3:0] <= 4'h0;
else fifo_data_in_addr[3:0] <= fifo_data_in_addr[3:0] + 1;
// if (IS_SIMUL && reset_fifo_in_cntr) fifo_hact_in_addr[3:0] <= 4'he;
// else fifo_hact_in_addr[3:0] <= fifo_data_in_addr[3:0] - 1; // 1 behind data
if (IS_SIMUL && reset_fifo_in_cntr) fifo_hact_in_addr[3:0] <= 4'hd;
else fifo_hact_in_addr[3:0] <= fifo_data_in_addr[3:0] - 2; // 3 behind data
// if (ihact_rst_in) fifo_data_in_addr_saved[3:0] <= fifo_data_in_addr[3:0] - 4'h5; // save FIFO in address for transferring to FIFO out address later
if (ihact_rst_in) fifo_data_in_addr_saved[3:0] <= fifo_data_in_addr[3:0] - 4'h6; // save FIFO in address for transferring to FIFO out address later
end
always @ (posedge gclk_idata or posedge reset_rq) begin
if (reset_rq) rq <= 1'b0;
else if (ihact_rst_in && en_idata) rq <= 1'b1;
end
reg [3:0] fifo_out_addr=0;
always @ (posedge sclk) begin
pre_reset_out_fifo[2:0]<={pre_reset_out_fifo[1:0], rq};
reset_out_fifo<=pre_reset_out_fifo[1] && ! pre_reset_out_fifo[2];
if (reset_out_fifo && dcm_fifo_locked) fifo_out_addr[3:0] <= fifo_data_in_addr_saved[3:0];
else fifo_out_addr[3:0] <= fifo_out_addr[3:0]+1;
end
reg rq_back=0;
reg reset_out_fifo_back=0;
reg [2:0] pre_reset_out_fifo_back=0;
wire reset_rq_back;
assign reset_rq_back= reset_out_fifo_back || (IS_SIMUL && reset_fifo_in_cntr) ;
always @ (posedge sclk or posedge reset_rq_back) begin
if (reset_rq_back) rq_back <= 1'b0;
else if ( reset_out_fifo) rq_back <= 1'b1;
end
reg wait_reset_back=0;
always @ (posedge gclk_idata) if (en_idata) begin
shact_zero[1:0]<={shact_zero[0], ~shact}; // dual sync
pre_reset_out_fifo_back[2:0]<={pre_reset_out_fifo_back[1:0], rq_back};
reset_out_fifo_back<=pre_reset_out_fifo_back[1] && ! pre_reset_out_fifo_back[2];
wait_reset_back <= !(IS_SIMUL && reset_fifo_in_cntr) && !hact_selected && shact_zero[1] && (ihact_rst_in || (wait_reset_back && !reset_out_fifo_back));
ihact_rst_in <= (IS_SIMUL && reset_fifo_in_cntr) || (!hact_selected && shact_zero[1] && !wait_reset_back && !ihact_rst_in);
end
//FIFO 16 deep, 2 wide (vact, hact)
wire pre_svact_outfifo;
myRAM_WxD_D #( .DATA_WIDTH(2),.DATA_DEPTH(4))
i_fifo_hact_vact(.D({vact_selected_2_cycles,hact_selected_2_cycles}),
.WE(en_idata),
.clk(gclk_idata),
.AW(fifo_hact_in_addr[3:0]),
.AR(fifo_out_addr[3:0]),
.QW(),
.QR({pre_svact_outfifo,pre_shact}));
//FIFO 16 deep, 14 wide (data)
myRAM_WxD_D #( .DATA_WIDTH(14),.DATA_DEPTH(4))
i_fifo_data_vact(.D(idi14[13:0]),
.WE(en_idata),
.clk(gclk_idata),
.AW(fifo_data_in_addr[3:0]),
.AR(fifo_out_addr[3:0]),
.QW(),
.QR(pre_sdo[13:0]));
reg vact_bypass=0;
assign pre_svact=debug[1]?vact_bypass:pre_svact_outfifo;
always @ (posedge sclk) begin
vact_bypass<=vact_selected_2_cycles;
hact_length_sync[13:0] <= hact_length[13:0];
hact_regen_sync <= hact_regen_isync;
pre_shact_d <= pre_shact;
if (IS_SIMUL && reset_fifo_in_cntr) shact <= 1'b0;
else if (pre_shact && !pre_shact_d) shact <= 1'b1;
else if (hact_regen_sync?hact_count_zero:(!pre_shact)) shact <= 1'b0;
if (!shact) hact_count[13:0] <= hact_length_sync[13:0];
else hact_count[13:0] <= hact_count[13:0]-1;
hact_count_zero <= (hact_count[13:0]== 14'h2); // now starts from total number, not number-1
sdo[13:0] <= pre_sdo[13:0];
// shact <= pre_shact;
pre_svact_d <= pre_svact;
svact <= pre_svact && ! pre_svact_d;
end
reg vact_sel_d=0;
reg vact_sel_dd=0;
always @ (posedge sclk) begin
vact_sel_d <= vact_selected;
vact_sel_dd <= vact_sel_d;
fvact <= !vact_sel_d && vact_sel_dd;
end
assign clkout = gclk_idata;
endmodule
sensor_phase359_sim.sh 0 → 100755
View file @ 1727b764
#!/bin/sh
UNISIMS="../unisims"
rm -vf motors.lxt
echo "Using UNISIM library $UNISIMS"
time iverilog -Dlegacy_model -gno-specify -v -o sensor_phase359_test -sglbl -stestbench \
-y$UNISIMS \
sensor_phase359_tb.v \
sensor_phase359.v \
glbl.v \
|| { echo "iverilog failed"; exit 1; }
time vvp -v sensor_phase359_test -lxt2 || { echo "vvp failed"; exit 1; }
gtkwave sensor_phase359.lxt sensor_phase359.sav &
exit 0
sensor_phase359_tb.v 0 → 100644
View file @ 1727b764
`timescale 1ns/1ps
/*
* It is just a placeholder for a real testbench. Made from 333, not everything updated
*/
module testbench();
parameter CCLK_PER = 6.25;// 160MHz
parameter ICLK_PER = 10.45;// 96MHz
parameter SCLK_PER_SLOW= 10.0;// 96+MHz
parameter SCLK_PER_FAST= 10.9;// 96-MHz
parameter SKIP_CYCLES=3;
parameter SENSOR_D_DLY=3;
parameter SENSOR_H_DLY=8;
parameter DCM_STEP=5; // number of DCM phase shifts per line
reg CCLK;
reg WCMD;
reg [5:0] CMD;
reg preHACT;
reg preVACT;
reg [11:0] preDI;
reg ICLK;
reg SCLK;
wire SHACT;
wire SVACT;
wire [11:0] SDO;
wire DCM_DONE;
wire [7:0] STATUS;
wire LOCKED;
wire ICLKD;
wire HACT;
wire VACT;
wire [11:0] DI;
assign #(SENSOR_H_DLY) HACT= preHACT;
assign #(SENSOR_H_DLY) VACT= preVACT;
assign #(SENSOR_D_DLY) DI[11:0]= preHACT?preDI[11:0]:12'bx;
wire CLOCK_SEL;
reg [5:0] FRAME;
integer pix, line;
parameter npix=100;
parameter nlines=10;
parameter vb=4;
parameter hb0=10;
parameter hb1=10;
assign CLOCK_SEL=FRAME[5];
sensor_phase359 i_sensor_phase359(
.cclk(CCLK), // command clock (posedge, invert on input if needed)
.wcmd(WCMD), // write command
.cmd(CMD[5:0]), // CPU write data [5:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
// 10 - increase hact/vact phase
// 20 - decrease hact/vact phase
// 30 - reset hact/vact phase
.HACT(HACT), // sensor HACT I/O pin (input), used to reset FIFO
.VACT(VACT), // sensor VACT I/O pin (input)
.DI(DI[11:0]), // sensor D[11:0] i/o pins (input)
.iclk(ICLK), // global sensor input clock (posedge) - the clock that goes to all 3 sensors
.sclk(SCLK), // global FIFO output clock (posedge)
.shact(SHACT), // hact - sync to sclk
.svact(SVACT), // vact - sync to sclk
.sdo(SDO[11:0]), // data output[11:0], sync to sclk
.dcm_done(DCM_DONE), // DCM command done
.status(STATUS[7:0]), // dcm status (bit 1 - dcm clkin stopped)
.locked(LOCKED)); // DCM locked
//reg [3:0] fifo_data_in_addr;
//reg [3:0] fifo_hact_in_addr;
//reg [3:0] fifo_out_addr;
wire [3:0] fifo_d_diff=i_sensor_phase359.fifo_data_in_addr[3:0]-i_sensor_phase359.fifo_out_addr[3:0];
wire [3:0] fifo_h_diff=i_sensor_phase359.fifo_hact_in_addr[3:0]-i_sensor_phase359.fifo_out_addr[3:0];
initial begin
$dumpfile("sensor_phase359.lxt");
$dumpvars(0,testbench);
CCLK<=0;
ICLK<=0;
SCLK<=0;
wait (~glbl.GSR);
// sclk<=1;
$display ("reset done at %t",$time);
write_cmd(6'h3f);
#1200000;
$finish;
end
// always #(CLK_PER/2) if (~glbl.GSR) sclk <= ~sclk;
initial begin
FRAME=0;
forever begin
wait (VACT);
wait (!VACT);
// write_cmd(6'h8);
write_cmd(6'hb); // rotate clock phases by 90 degrees, reset DCM phase
if (FRAME[1:0]==0) write_cmd(6'h20); // shift clock phase hact,vact vs data by 90 degrees
#10;
FRAME=FRAME+1;
end
end
always @ (posedge HACT) begin /// hoping task at VACT end is already over - could be conflicts - combine in the same thread?
repeat (DCM_STEP) begin
write_cmd(FRAME[0]?6'h1:6'h2);
end
end
//DCM_STEP
initial begin
SCLK <= 1'b0;
forever begin
#((CLOCK_SEL?SCLK_PER_SLOW:SCLK_PER_FAST)/2);
SCLK <= 1'b1;
#((CLOCK_SEL?SCLK_PER_SLOW:SCLK_PER_FAST)/2);
SCLK <= 1'b0;
end
end
always #(CCLK_PER/2) CCLK <= ~CCLK;
always #(ICLK_PER/2) ICLK <= ~ICLK;
// always #(SCLK_PER/2) SCLK <= ~SCLK;
/*
always @ (negedge VACT) begin
write_cmd(6'h20);
end
*/
initial begin
line=0;
pix=0;
preDI=0;
forever begin
for (line=0; line < (nlines+vb); line=line+1) begin
preVACT<=(line>=vb)?1'b1:1'b0;
for (pix=0;pix<(npix+hb0+hb1); pix=pix+1) begin
if ((line>=vb) && (pix>=hb0) && (pix<(hb0+npix))) begin
preHACT<=1'b1;
preDI<=preDI+1;
end else begin
preHACT<=1'b0;
end
wait (~ICLK);wait (ICLK);
end
end
end
end
task write_cmd;
input [5:0] d;
integer i;
begin
wait(~CCLK);wait(CCLK);
#1;
CMD=d;
WCMD=1;
wait(~CCLK);wait(CCLK);
#1;
CMD='bx;
WCMD=0;
wait (DCM_DONE);
for (i=0; i<SKIP_CYCLES;i=i+1) begin
wait(~CCLK);wait(CCLK);
end
end
endtask
endmodule
sensor_phase359_vact.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** sensor_phase353.v
**
** Phase conpensating for the sesnor data (separate for data and hact/vact)
**
** Copyright (C) 2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module sensor_phase353_vact (cclk, // command clock (posedge, invert on input if needed)
wcmd, // write command
cmd, // CPU write data [5:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
// 10 - increase hact/vact phase
// 20 - decrease hact/vact phase
// 30 - reset hact/vact phase
HACT, // sensor HACT I/O pin (input), used to reset FIFO
VACT, // sensor VACT I/O pin (input)
DI, // sensor D[DATA_WIDTH-1:0] i/o pins (input), strobed @posedge gclk_idata and en_idata
debug, // 2-bit debug mode input
hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
hact_regen, // 0 - use hact from sensor, 1 - regenerate using hact_lengh
mode_12bits,// input, 1 - enable 12/14 bit mode, 0 - 10 bit mode
mode_14bits,// input, 1 - enable 14 bit mode, 0 - 12/10 bit mode
mode_alt, // enable alternative vact/hact input (sync to data)
sync_alt, // alternative HACT/VACT input pad (10347) (VACT - 1 clock, HACT >1)
iclk, // DCM input clock (GCLK)
sclk, // global FIFO output clock (posedge)
shact, // hact - sync to sclk
svact, // vact - sync to sclk (single cycle)
fvact, // vact fall
sdo, // data output[DATA_WIDTH-1:0], sync to sclk
clkout,
dcm_done, // DCM command done
status, // dcm status (bit 1 - dcm clkin stopped)
locked); // DCM locked
/*in UCF
NET "i_sensorpads/i_sensor_phase/gclk_idata" TNM_NET = "TNM_GCLK_IDATA";
NET "i_sensorpads/i_sensor_phase/en_idata" TNM_NET = "TNM_EN_IDATA";
TIMESPEC "TS_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_GCLK_IDATA" TIG;
TIMESPEC "TS_GCLK_IDATA_PCLK" = FROM "TNM_GCLK_IDATA" TO "TNM_PCLK" TIG;
TIMESPEC "TS_DOUBLECYC_IDATA" = FROM "TNM_EN_IDATA" TO "TNM_EN_IDATA" "TS_CLK1";
NET "i_sensorpads/i_sensor_phase/phase_hact_sel_sync*" TIG;
NET "i_sensorpads/i_sensor_phase/mode_alt_sync" TIG;
NET "i_sensorpads/i_sensor_phase/mode_12bits_sync" TIG;
NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG;
NET "hact_length*" TIG;
*/
parameter IS_SIMUL=0;
//synthesis translate_off
parameter IS_SIMUL=1;
//synthesis translate_on
input cclk; // command clock (posedge, invert on input if needed)
input wcmd; // write command
input [5:0] cmd; // CPU write data [5:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
// 10 - increase hact/vact phase
// 20 - decrease hact/vact phase
// 30 - reset hact/vact phase
input HACT; // sensor HACT I/O pin (input), used to reset FIFO
input VACT; // sensor VACT I/O pin (input)
input [11:0] DI; // sensor D11:0], after IBUF (IOBUF)
input [1:0] debug; // 2-bit debug mode input, connect to 2'b0 if not needed
input [13:0] hact_length;// [13:0] WOI width (to overwrite sensor HACT duration)
input hact_regen; // 0 - use hact from sensor, 1 - regenerate using hact_lengh
input mode_12bits;// input, 1 - enable 12/14 bit mode, 0 - 10 bit mode, use 1'b1 in 10359
input mode_14bits;// input, 1 - enable 14 bit mode, 0 - 12/10 bit mode, use 1'b0 in 10359
input mode_alt; // enable alternative vact/hact input (sync to data), use 1'b0 in 10359
input sync_alt; // alternative HACT/VACT input pad (10347) (VACT - 1 clock, HACT >1)
input iclk; // global sensor input clock (posedge) - the clock that goes to all 3 sensors
input sclk; // global FIFO output clock (posedge)
output shact; // hact - sync to sclk
output svact; // vact - sync to sclk
output fvact; // vact - sync to sclk
output [13:0] sdo; // data output[DATA_WIDTH-1:0], sync to sclk (Use {pxdo[11:0],unused[1:0]} in 10359
output clkout;
output dcm_done; // DCM command done
output [7:0] status; // DCM command done
output locked; // DCM locked
wire dcm_rst_cmd;
reg [2:0] dcm_drst=0;
reg dcm_en=0;
reg dcm_incdec=0;
reg dcm_done=0;
wire dcm_done_dcm; // single-cycle
reg dcm_rst=0;
reg [2:0] dcm_reset_done=0;
reg [1:0] phase90sel=0;
reg [2:0] phase_hact_sel=0;
wire locked;
wire dcm_out0,dcm2x,dcm2x180;
wire gclk_idata;
reg en_idata=0;
wire pre_pre_en_idata, pre_pre_en_idata90;
reg pre_en_idata=0;
reg inv_gclk_idata=0;
reg inv_en_idata=0;
wire [7:0] status;
// reg reset_fifo_in_cntr; // only for simulation;
wire reset_fifo_in_cntr; // only for simulation;
FD i_dcm_rst_cmd(.Q(dcm_rst_cmd), .D((wcmd && (cmd[1:0] == 2'b11)) || (dcm_rst_cmd && !dcm_drst[2])), .C(cclk)) ;
always @ (posedge cclk) begin
dcm_reset_done[2:0] <= {dcm_reset_done[1] & ~dcm_reset_done[0], dcm_reset_done[0], dcm_rst}; // sync to cclkl end of dcm reset
dcm_en <= wcmd && (cmd[1]!=cmd[0]);
dcm_incdec <= wcmd && cmd[0];
if (wcmd) begin
if (cmd[2] && cmd[3]) phase90sel[1:0] <= 2'h0;
else if (cmd[2]) phase90sel[1:0] <= phase90sel[1:0] +1;
else if (cmd[3]) phase90sel[1:0] <= phase90sel[1:0] -1;
end
if (wcmd) begin
if (cmd[4] && cmd[5]) phase_hact_sel[2:0] <= 3'h0;
else if (cmd[4]) phase_hact_sel[2:0] <= phase_hact_sel[2:0] +1;
else if (cmd[5]) phase_hact_sel[2:0] <= phase_hact_sel[2:0] -1;
end
// if (wcmd) reset_fifo_in_cntr <= IS_SIMUL && (cmd[5:0]==6'h3f);
end
always @ (posedge iclk) begin
dcm_drst[2:0] <= dcm_drst[2]? 3'b0:{dcm_drst[1], dcm_drst[0], dcm_rst_cmd};
dcm_rst <= dcm_drst[0] || dcm_drst[1] || dcm_drst[2] ;
end
// make dcm_done behave as dcm_ready
always @ (posedge cclk)
if (wcmd && |cmd[2:0]) dcm_done <=1'b0;
else if (dcm_done_dcm || dcm_reset_done[2]) dcm_done <=1'b1;
/// DCM to compensate sensor delays. Adjustment for data phase - both fine and 90-degrees, hact/vact - 90-degree steps relative to data
always @ (posedge gclk_idata) begin
inv_gclk_idata <= phase90sel[0]; /// TODO: check polarities. Make them TIG?
inv_en_idata <= phase90sel[1]; /// TODO: check polarities. Make them TIG?
pre_en_idata <=inv_gclk_idata?pre_pre_en_idata90:pre_pre_en_idata; /// adjust tap
en_idata <= pre_en_idata ^ inv_en_idata;
end
BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata));
DCM_SP #(
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), //96Hz
.CLKOUT_PHASE_SHIFT("VARIABLE"),// Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) i_dcm_sensor(
.CLKIN (iclk),
.CLKFB (dcm_out0),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (cclk),
.DSSEN (1'b0),
.CLK0 (dcm_out0),
.CLK90 (pre_pre_en_idata), // adjust tap
.CLK180 (pre_pre_en_idata90), // adjust tap
.CLK270 (),
.CLKDV (),
.CLK2X (dcm2x),
.CLK2X180 (dcm2x180),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE (dcm_done_dcm));
// Preventing skipping VACT/HACT after DCM reset (disabling update of the fifo output address:
reg [1:0] dcm_in_locked=0; // syncing to sclk
reg [3:0] dcm_locked_cntr=0; // counter that extends !locked to the fifo size
reg dcm_fifo_locked=0; // safe to reset fifo output address
always @ (posedge sclk) begin
dcm_in_locked[1:0] <= {dcm_in_locked[0],locked};
if (!dcm_in_locked[1]) dcm_fifo_locked <= 1'b0;
else if (dcm_locked_cntr[3:0]==4'h0) dcm_fifo_locked <= 1'b1;
if (!dcm_in_locked[1]) dcm_locked_cntr[3:0] <= 4'hf;
else if (!dcm_fifo_locked) dcm_locked_cntr[3:0] <= dcm_locked_cntr[3:0]-1;
end
// reg [11:0] idi;
wire [11:0] idi;
reg [13:0] idi14=0;
wire hact_q0, vact_q0;
// wire hact_q1,vact_q1;
reg hact_q1=0,vact_q1=0;
wire sync_alt_d0;
reg [2:1] sync_alt_d=0;
reg [3:0] hact_q1_d=0;
reg [3:0] hact_q0_d=0;
reg [3:0] vact_q1_d=0;
reg [3:0] vact_q0_d=0;
reg hact_vd=0; // variable delay, each clock cycle
reg vact_vd=0; // variable delay, each clock cycle
reg hact_selected=0; // selected between normal and alt hact
reg vact_selected=0; // selected between normal and alt vact
reg [1:0] hact_selected_d=0;
reg hact_selected_2_cycles=0;
reg [1:0] vact_selected_d=0;
reg vact_selected_2_cycles=0;
wire alt_hact;
wire alt_vact;
reg [2:0] phase_hact_sel_sync=0;
reg mode_alt_sync=0;
reg mode_12bits_sync=0;
reg mode_14bits_sync=0;
reg svact=0,shact=0;
reg fvact=0;
reg [13:0] sdo=0;
wire[13:0] pre_sdo;
wire pre_shact;
wire pre_svact; ///nominally 2-cycle long output from FIFO (can be 1 or 3 long)
reg pre_svact_d=0;
wire ihact,ivact;
reg [13:0] hact_count=0;
reg pre_shact_d=0;
reg [13:0] hact_length_sync=0;
reg hact_regen_sync=0; // sync to output
reg hact_regen_isync=0; // sync to gclk_idata
reg hact_count_zero=0;
assign alt_hact=sync_alt_d[1] && (sync_alt_d0 || sync_alt_d[2]); /// already controlled by mode_alt
assign alt_vact=sync_alt_d[1] && !sync_alt_d0 && !sync_alt_d[2]; /// already controlled by mode_alt
//synthesis translate_off
wire vact_or_hact= VACT || HACT;
reg sim_rst=0;
always @ (negedge glbl.GSR or posedge vact_or_hact) begin
if (vact_or_hact) sim_rst <= 1'b0;
else sim_rst <= 1'b1;
end
assign reset_fifo_in_cntr=glbl.GSR || sim_rst;
//synthesis translate_on
wire ihact00,ivact00;
/// some are double cycle
IBUF i_hact (.I(HACT), .O(ihact));
IBUF i_vact (.I(VACT), .O(ivact));
always @ (posedge gclk_idata) begin
hact_q1 <= ihact00;
vact_q1 <= ivact00;
hact_q0_d[3:0]<={hact_q0_d[2:0],hact_q0};
hact_q1_d[3:0]<={hact_q1_d[2:0],hact_q1};
vact_q0_d[3:0]<={vact_q0_d[2:0],vact_q0};
vact_q1_d[3:0]<={vact_q1_d[2:0],vact_q1};
end
always @ (posedge gclk_idata) if (en_idata) begin
// HACT delay -3..+4 90-degree steps, positive hact arrives later than data
{vact_vd,hact_vd} <= phase_hact_sel_sync[2]?
(phase_hact_sel_sync[1]?
(phase_hact_sel_sync[0]?{vact_q1_d[2],hact_q1_d[2]}:{vact_q0_d[3],hact_q0_d[3]}):
(phase_hact_sel_sync[0]?{vact_q1_d[3],hact_q1_d[3]}:{vact_q0_d[0],hact_q0_d[0]})):
(phase_hact_sel_sync[1]?
(phase_hact_sel_sync[0]?{vact_q1_d[0],hact_q1_d[0]}:{vact_q0_d[1],hact_q0_d[1]}):
(phase_hact_sel_sync[0]?{vact_q1_d[1],hact_q1_d[1]}:{vact_q0_d[2],hact_q0_d[2]}));
end
IDDR2 i_ihact (.Q0(hact_q0),.Q1(ihact00),.C0(gclk_idata),.C1(!gclk_idata),.CE(1'b1), .D(ihact), .R(1'b0), .S(1'b0) );
FD i_ivact (.Q(vact_q0),.C(gclk_idata), .D(ivact) );
assign ivact00=vact_q0;
// FD i_hact_q1 (.C(gclk_idata), .D(ihact00), .Q(hact_q1));
// FD i_vact_q1 (.C(gclk_idata), .D(ivact00), .Q(vact_q1));
FDCE i_sync_alt_d0 (.Q(sync_alt_d0), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(sync_alt));
FDCE i_idi_0 (.Q(idi[ 0]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 0]));
FDCE i_idi_1 (.Q(idi[ 1]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 1]));
FDCE i_idi_2 (.Q(idi[ 2]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 2]));
FDCE i_idi_3 (.Q(idi[ 3]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 3]));
FDCE i_idi_4 (.Q(idi[ 4]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 4]));
FDCE i_idi_5 (.Q(idi[ 5]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 5]));
FDCE i_idi_6 (.Q(idi[ 6]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 6]));
FDCE i_idi_7 (.Q(idi[ 7]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 7]));
FDCE i_idi_8 (.Q(idi[ 8]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 8]));
FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9]));
FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10]));
FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11]));
// synthesis attribute IOB of i_sync_alt_d0 is "TRUE"
// synthesis attribute IOB of i_idi_0 is "TRUE"
// synthesis attribute IOB of i_idi_1 is "TRUE"
// synthesis attribute IOB of i_idi_2 is "TRUE"
// synthesis attribute IOB of i_idi_3 is "TRUE"
// synthesis attribute IOB of i_idi_4 is "TRUE"
// synthesis attribute IOB of i_idi_5 is "TRUE"
// synthesis attribute IOB of i_idi_6 is "TRUE"
// synthesis attribute IOB of i_idi_7 is "TRUE"
// synthesis attribute IOB of i_idi_8 is "TRUE"
// synthesis attribute IOB of i_idi_9 is "TRUE"
// synthesis attribute IOB of i_idi_10 is "TRUE"
// synthesis attribute IOB of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_sync_alt_d0 is "TRUE"
// synthesis attribute NODELAY of i_idi_0 is "TRUE"
// synthesis attribute NODELAY of i_idi_1 is "TRUE"
// synthesis attribute NODELAY of i_idi_2 is "TRUE"
// synthesis attribute NODELAY of i_idi_3 is "TRUE"
// synthesis attribute NODELAY of i_idi_4 is "TRUE"
// synthesis attribute NODELAY of i_idi_5 is "TRUE"
// synthesis attribute NODELAY of i_idi_6 is "TRUE"
// synthesis attribute NODELAY of i_idi_7 is "TRUE"
// synthesis attribute NODELAY of i_idi_8 is "TRUE"
// synthesis attribute NODELAY of i_idi_9 is "TRUE"
// synthesis attribute NODELAY of i_idi_10 is "TRUE"
// synthesis attribute NODELAY of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_ihact is "TRUE"
// synthesis attribute NODELAY of i_ivact is "TRUE"
reg [1:0] shact_zero=0; // shact was zero (inactive), sync to gclk_data
always @ (posedge gclk_idata) if (en_idata) begin
idi14[13:4] <= idi[11:2];
idi14[ 3:2] <= (mode_12bits_sync || mode_14bits_sync)? idi[1:0]:2'h0;
idi14[ 1:0] <= mode_14bits_sync? {vact_q0_d[0],hact_q0_d[0]}:2'h0;
sync_alt_d[2:1]<={sync_alt_d[1], sync_alt_d0 & mode_alt_sync}; ///sync_alt_d[0] - IOB
phase_hact_sel_sync[2:0] <= phase_hact_sel[2:0];
mode_14bits_sync <= mode_14bits;
mode_12bits_sync <= mode_12bits;
// hact_regen_isync <= hact_regen;
// only update hact_regen_isync when HACT (both input and output from fifo) are inactive (to prevent short lines)
if ((!hact_q0_d[0]) && shact_zero[1]) hact_regen_isync <= hact_regen;
//shact_zero[1]
//hact_q0_d[3:0]
mode_alt_sync <= mode_alt;
hact_selected <= mode_alt_sync? alt_hact : hact_vd;
vact_selected <= mode_alt_sync? alt_vact : vact_vd;
///if (hact_regen_isync==0) will copy hact to hact_selected_2_cycles
hact_selected_d[1:0]<={hact_selected_d[0], hact_selected && hact_regen_isync };
hact_selected_2_cycles <= (hact_selected && !hact_selected_d[0]) ||
(hact_selected_d[0] && !hact_selected_d[1]);
vact_selected_d[1:0]<={vact_selected_d[0],vact_selected};
vact_selected_2_cycles <= (vact_selected && !vact_selected_d[0]) ||
(vact_selected_d[0] && !vact_selected_d[1]);
//vact_selected_2_cycles <= vact_selected;//(debug[0] || !hact_selected && !hact_selected_d[0] && !hact_selected_d[1]) && ((vact_selected && !vact_selected_d[0]) || (vact_selected_d[0] && !vact_selected_d[1]));
end
//phase_hact_sel==3'h0 - delay by 2 cycles from data
reg [3:0] fifo_data_in_addr=0;
reg [3:0] fifo_hact_in_addr=0;
reg [3:0] fifo_data_in_addr_saved=0;
reg ihact_rst_in=0;
wire reset_rq;
reg rq=0;
reg reset_out_fifo=0;
reg [2:0] pre_reset_out_fifo=0;
assign reset_rq= reset_out_fifo || (IS_SIMUL && reset_fifo_in_cntr) ;
//glbl.GSR
always @ (posedge gclk_idata) if (en_idata) begin
/// input FIFO counter is only reset for the simulation
if (IS_SIMUL && reset_fifo_in_cntr) fifo_data_in_addr[3:0] <= 4'h0;
else fifo_data_in_addr[3:0] <= fifo_data_in_addr[3:0] + 1;
// if (IS_SIMUL && reset_fifo_in_cntr) fifo_hact_in_addr[3:0] <= 4'he;
// else fifo_hact_in_addr[3:0] <= fifo_data_in_addr[3:0] - 1; // 1 behind data
if (IS_SIMUL && reset_fifo_in_cntr) fifo_hact_in_addr[3:0] <= 4'hd;
else fifo_hact_in_addr[3:0] <= fifo_data_in_addr[3:0] - 2; // 3 behind data
// if (ihact_rst_in) fifo_data_in_addr_saved[3:0] <= fifo_data_in_addr[3:0] - 4'h5; // save FIFO in address for transferring to FIFO out address later
if (ihact_rst_in) fifo_data_in_addr_saved[3:0] <= fifo_data_in_addr[3:0] - 4'h6; // save FIFO in address for transferring to FIFO out address later
end
always @ (posedge gclk_idata or posedge reset_rq) begin
if (reset_rq) rq <= 1'b0;
else if (ihact_rst_in && en_idata) rq <= 1'b1;
end
reg [3:0] fifo_out_addr=0;
always @ (posedge sclk) begin
pre_reset_out_fifo[2:0]<={pre_reset_out_fifo[1:0], rq};
reset_out_fifo<=pre_reset_out_fifo[1] && ! pre_reset_out_fifo[2];
if (reset_out_fifo && dcm_fifo_locked) fifo_out_addr[3:0] <= fifo_data_in_addr_saved[3:0];
else fifo_out_addr[3:0] <= fifo_out_addr[3:0]+1;
end
reg rq_back=0;
reg reset_out_fifo_back=0;
reg [2:0] pre_reset_out_fifo_back=0;
wire reset_rq_back;
assign reset_rq_back= reset_out_fifo_back || (IS_SIMUL && reset_fifo_in_cntr) ;
always @ (posedge sclk or posedge reset_rq_back) begin
if (reset_rq_back) rq_back <= 1'b0;
else if ( reset_out_fifo) rq_back <= 1'b1;
end
reg wait_reset_back=0;
always @ (posedge gclk_idata) if (en_idata) begin
shact_zero[1:0]<={shact_zero[0], ~shact}; // dual sync
pre_reset_out_fifo_back[2:0]<={pre_reset_out_fifo_back[1:0], rq_back};
reset_out_fifo_back<=pre_reset_out_fifo_back[1] && ! pre_reset_out_fifo_back[2];
wait_reset_back <= !(IS_SIMUL && reset_fifo_in_cntr) && !hact_selected && shact_zero[1] && (ihact_rst_in || (wait_reset_back && !reset_out_fifo_back));
ihact_rst_in <= (IS_SIMUL && reset_fifo_in_cntr) || (!hact_selected && shact_zero[1] && !wait_reset_back && !ihact_rst_in);
end
//FIFO 16 deep, 2 wide (vact, hact)
wire pre_svact_outfifo;
myRAM_WxD_D #( .DATA_WIDTH(2),.DATA_DEPTH(4))
i_fifo_hact_vact(.D({vact_selected_2_cycles,hact_selected_2_cycles}),
.WE(en_idata),
.clk(gclk_idata),
.AW(fifo_hact_in_addr[3:0]),
.AR(fifo_out_addr[3:0]),
.QW(),
.QR({pre_svact_outfifo,pre_shact}));
//FIFO 16 deep, 14 wide (data)
myRAM_WxD_D #( .DATA_WIDTH(14),.DATA_DEPTH(4))
i_fifo_data_vact(.D(idi14[13:0]),
.WE(en_idata),
.clk(gclk_idata),
.AW(fifo_data_in_addr[3:0]),
.AR(fifo_out_addr[3:0]),
.QW(),
.QR(pre_sdo[13:0]));
reg vact_bypass=0;
assign pre_svact=debug[1]?vact_bypass:pre_svact_outfifo;
always @ (posedge sclk) begin
vact_bypass<=vact_selected_2_cycles;
hact_length_sync[13:0] <= hact_length[13:0];
hact_regen_sync <= hact_regen_isync;
pre_shact_d <= pre_shact;
if (IS_SIMUL && reset_fifo_in_cntr) shact <= 1'b0;
else if (pre_shact && !pre_shact_d) shact <= 1'b1;
else if (hact_regen_sync?hact_count_zero:(!pre_shact)) shact <= 1'b0;
if (!shact) hact_count[13:0] <= hact_length_sync[13:0];
else hact_count[13:0] <= hact_count[13:0]-1;
hact_count_zero <= (hact_count[13:0]== 14'h2); // now starts from total number, not number-1
sdo[13:0] <= pre_sdo[13:0];
// shact <= pre_shact;
pre_svact_d <= pre_svact;
// svact <= pre_svact_d;
svact <= pre_svact && ! pre_svact_d;
end
reg vact_sel_d=0;
reg vact_sel_dd=0;
always @ (posedge sclk) begin
vact_sel_d <= vact_selected;
vact_sel_dd <= vact_sel_d;
fvact <= !vact_sel_d && vact_sel_dd;
end
assign clkout= gclk_idata;
endmodule
sync_frames.v 0 → 100644
View file @ 1727b764
/*
** -----------------------------------------------------------------------------**
** sync_frames.v
**
** Copyright (C) 2002-2010 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module sync_frames(clk, /// @posedge
trig, /// active low, always low in free running mode
vacts, /// [2:0] vacts (single cycle) from each of 3 channels
enchn, /// [2:0] enabled channels
first, /// vacts from the first sesnor (valid in trigger mode only)
sync); /// single cycle (@posedge clk), one cycle dealy from vacts.
input clk;
input trig;
input [2:0] vacts;
input [2:0] enchn;
output first;
output [2:0] sync;
reg trig_d, trigs;
reg [2:0] wait_vacts=0;
reg wait_first=0,wait_first_d=0;
reg [2:0] sync=0;
assign first= wait_first_d & ~wait_first;
always @ (posedge clk) begin
trig_d <=trig;
trigs <= trig_d && !trig;
// wait_vacts[2:0] <= trigs?3'b111:(wait_vacts[2:0] & ~vacts[2:0] & enchn[2:0]);
wait_vacts[2:0] <= {3{trigs}} | (wait_vacts[2:0] & ~vacts[2:0] & enchn[2:0]);
// wait_first <= trigs?1'b1: (wait_first & ~|(vacts[2:0] & enchn[2:0]));
wait_first <= trigs | (wait_first & ~|(vacts[2:0] & enchn[2:0]));
wait_first_d <= wait_first;
sync[2:0] <= enchn[2:0] & ({3{first}} | (vacts[2:0] & ~wait_vacts[2:0]));
end
endmodule
test_scripts/10359_controls.html 0 → 100644
View file @ 1727b764
<html>
<!--
/*!*******************************************************************************
*! FILE NAME : 10359_controls.html
*! DESCRIPTION: 10359 UI
*! Copyright (C) 2009 Elphel, Inc
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: 10359_controls.html,v $
*! Revision 1.10 2010/05/13 17:20:18 dzhimiev
*! 1. for 10359 revA, should be compatible with rev0
*! 2. new command system
*! 3. recoded for Eyesis
*!
<<<<<<< 10359_controls.html
<<<<<<< 10359_controls.html
=======
*! Revision 1.4 2009/11/06 19:05:04 dzhimiev
*! SDRAM phase shift
=======
*! Revision 1.8 2010/01/04 05:32:27 dzhimiev
*! 1. added scale factor - for combined mode mostly, scale factor is set avoiding camvc
*!
*! Revision 1.7 2009/12/14 23:02:15 oneartplease
*! turned header into <h1>
*!
*! Revision 1.6 2009/12/04 03:40:15 dzhimiev
*! 1. removed frame size setting - replaced with getting it from the sensor
*!
*! Revision 1.5 2009/12/02 04:44:25 dzhimiev
*! 1. added and option for combining alternating frames into one
*! 2. changed some names for convenience
>>>>>>> 1.8
*!
>>>>>>> 1.4
*!
*/
-->
<head><title>359 controls page </title></head>
<body>
<h1>10359 board controls</h1><br>
<table border="0" bgcolor="#EFEFEF">
<td>
<table>
<tr border="0" cellpadding="0" bgcolor="#D7F7D7">
<td>
Use sensors (J2,J3,J4)
</td>
<td>
<input type="checkbox" id="j2_on" readonly checked>
<input type="checkbox" id="j3_on" checked>
<input type="checkbox" id="j4_on" >
</td>
</tr>
<tr border="0" cellpadding="0" bgcolor="#C7F7C7">
<td>
Switch to channel :
<input title="reg_35" style="width:30px;text-align:right" type="text" id="reg_35" value="7"/>
</td>
<td>
<input type="button" id="btn_switch" value="apply" onClick="brd359_channel_switch('reg_35');" style="width:60px"/>
</td>
</tr>
<tr border="0" cellpadding="0" bgcolor="#D7F7D7">
<td>
Sensor test mode ON/OFF
</td>
<td>
<input type="button" id="btn_toggle_test" value="toggle" onClick="brd359_toggle_test_mode();" style="width:60px"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
</table>
<table>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Number of phase steps:&nbsp&nbsp
<input title="N_phase_steps" style="width:35px;text-align:right" type="text" id="N_phase_steps" value="5" />
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
SCLK0 phase
</td>
<td>
<input type="button" id="btn_sclk0_phase_plus" value="+" onClick="brd359_phase_shift(0,1);" style="width:30px"/>
<input title="sclk0_phase" style="width:35px;text-align:right" type="text" id="sclk0_phase" value="0" readonly/>
<input type="button" id="btn_sclk0_phase_minus" value="-" onClick="brd359_phase_shift(0,2);" style="width:30px"/>
</td>
<td>&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_sclk0_clk_plus" value="<" onClick="brd359_phase_shift(0,4);" style="width:30px"/>
<input title="sclk0_quarter" style="width:35px;text-align:right" type="text" id="sclk0_quarter" value="0" readonly align=left/>
<input type="button" id="btn_sclk0_clk_minus" value=">" onClick="brd359_phase_shift(0,8);" style="width:30px"/>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Channel 0 phase
</td>
<td>
<input type="button" id="btn_ch0_phase_plus" value="+" onClick="brd359_phase_shift(1,1);" style="width:30px"/>
<input title="ch0_phase" style="width:35px;text-align:right" type="text" id="ch0_phase" value="0" readonly align=right/>
<input type="button" id="btn_ch0_phase_minus" value="-" onClick="brd359_phase_shift(1,2);" style="width:30px"/>
</td>
<td>&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_ch0_clk_plus" value="<" onClick="brd359_phase_shift(1,4);" style="width:30px"/>
<input title="ch0_quarter" style="width:35px;text-align:right" type="text" id="ch0_quarter" value="0" readonly align=left/>
<input type="button" id="btn_ch0_clk_minus" value=">" onClick="brd359_phase_shift(1,8);" style="width:30px"/>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
Channel 1 phase
</td>
<td>
<input type="button" id="btn_ch1_phase_plus" value="+" onClick="brd359_phase_shift(2,1);" style="width:30px"/>
<input title="ch1_phase" style="width:35px;text-align:right" type="text" id="ch1_phase" value="0" readonly/>
<input type="button" id="btn_ch1_phase_minus" value="-" onClick="brd359_phase_shift(2,2);" style="width:30px"/>
</td>
<td>&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_ch1_clk_plus" value="<" onClick="brd359_phase_shift(2,4);" style="width:30px"/>
<input title="ch1_quarter" style="width:35px;text-align:right" type="text" id="ch1_quarter" value="0" readonly align=left/>
<input type="button" id="btn_ch1_clk_minus" value=">" onClick="brd359_phase_shift(2,8);" style="width:30px"/>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Channel 2 phase
</td>
<td>
<input type="button" id="btn_ch2_phase_plus" value="+" onClick="brd359_phase_shift(3,1);" style="width:30px"/>
<input title="ch2_phase" style="width:35px;text-align:right" type="text" id="ch2_phase" value="0" readonly/>
<input type="button" id="btn_ch2_phase_minus" value="-" onClick="brd359_phase_shift(3,2);" style="width:30px"/>
</td>
<td>&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_ch2_clk_plus" value="<" onClick="brd359_phase_shift(3,4);" style="width:30px"/>
<input title="ch2_quarter" style="width:35px;text-align:right" type="text" id="ch2_quarter" value="0" readonly align=left/>
<input type="button" id="btn_ch2_clk_minus" value=">" onClick="brd359_phase_shift(3,8);" style="width:30px"/>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td align=right>
<input type="button" id="btn_auto_phases" value="Auto adjust" onClick="brd359_auto_phases();"/>
<input type="button" id="btn_save_phases" value="Save" onClick="brd359_save_phases();"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
</table>
<table>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
SDRAM clock&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_sdram_clk_plus" value="<" onClick="brd359_sdram_clk_shift(4,4);" style="width:30px"/>
<input title="sdram_clk" style="width:55px;text-align:right" type="text" id="sdram_clk" value="sclk0" readonly align=left/>
<input type="button" id="btn_sdram_clk_minus" value=">" onClick="brd359_sdram_clk_shift(4,8);" style="width:30px"/>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Clock phase&nbsp&nbsp&nbsp&nbsp
</td>
<td>
<input type="button" id="btn_sdram_clk_phase_plus" value="+" onClick="brd359_phase_shift(4,1);" style="width:30px"/>
<input title="ch3_phase" style="width:55px;text-align:right" type="text" id="ch3_phase" value="0" readonly align=right/>
<input type="button" id="btn_sdram_clk_phase_minus" value="-" onClick="brd359_phase_shift(4,2);" style="width:30px"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
</table>
<table>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
Combine into one frame
</td>
<td align=center>
<input type="checkbox" id="combine_into_one_frame" checked>
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Scale factor
</td>
<td>
<input title="scale_factor" style="width:50px;text-align:right" type="text" id="scale_factor" value="1" />
</td>
</tr>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
Alternation mode with buffering:
</td>
<td>
<input type="button" style="width:50px" id="btn_alt_buf_mode" value="start" onClick="brd359_alt_buf_mode();"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
Alternation mode:
</td>
<td>
<input type="button" style="width:50px" id="btn_alt_mode" value="start" onClick="brd359_alt_mode();"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
<tr border="0" cellpadding="2" bgcolor="#C7F7C7">
<td>
<input type="button" style="width:150px" id="btn_stereo_mode" value="Stereo mode" onClick="brd359_stereo_mode();"/>
</td>
</tr>
<tr><td>&nbsp</td></tr>
</table>
<table id="rq_table" border="0" cellpadding="2" bgcolor="#C7F7C7">
<tr>
<td>
Request line
</td>
</tr>
<tr>
<td>
<input title="status_reg" style="width:350px" type="text" id="status_reg" value="" readonly/>&nbsp
</td>
</tr>
</table>
</td>
<td valign="top">
<table>
<tr border="0" cellpadding="2" bgcolor="#D7F7D7">
<td>
<input type="button" id="btn_read_regs" value="read registers" onClick="brd359_read_regs();"/>
</td>
</tr>
<tr><td>
<table>
<tr>
<td>
Firmware Version:
</td>
<td>
<input title="firmware_version" style="width:80px" type="text" id="reg_00" value="" readonly/>
</td>
</tr>
<tr>
<td>
Current Channel:
</td>
<td>
<input title="reg_0x01" style="width:80px" type="text" id="reg_01" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x02:
</td>
<td>
<input title="reg_0x02" style="width:80px" type="text" id="reg_02" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x03h(pclk):
</td>
<td>
<input title="reg_0x03h" style="width:80px" type="text" id="reg_03h" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x03l(sclk0):
</td>
<td>
<input title="reg_0x03l" style="width:80px" type="text" id="reg_03l" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x05:
</td>
<td>
<input title="reg_0x05" style="width:80px" type="text" id="reg_05" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x06:
</td>
<td>
<input title="reg_0x06" style="width:80px" type="text" id="reg_06" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x07:
</td>
<td>
<input title="reg_0x07" style="width:80px" type="text" id="reg_07" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x20:
</td>
<td>
<input title="reg_0x20" style="width:80px" type="text" id="reg_20" value="" readonly/>
</td>
</tr>
<tr>
<td>
Reg 0x44:
</td>
<td>
<input title="reg_0x44" style="width:80px" type="text" id="reg_44" value="" readonly/>
</td>
</tr>
</td>
</tr>
</table>
</td></tr>
<tr><td>&nbsp</td></tr>
</table>
</td>
</table>
<!-- status -->
<script language="javascript"><!--
brd359_init_field_values();
function brd359_init_field_values(){
document.getElementById("reg_35").value = 7;
document.getElementById("N_phase_steps").value = 5;
document.getElementById("sclk0_phase").value = 0;
document.getElementById("ch0_phase").value = 0;
document.getElementById("ch1_phase").value = 0;
document.getElementById("ch2_phase").value = 0;
//sdram phase
document.getElementById("ch3_phase").value = 0;
document.getElementById("scale_factor").value = 1;
document.getElementById("scale_factor").title = "Valid resolutions in CAMVC for combined mode: f=1 - any; f=2 - 1296x1920; f=3 - 864x1280; f=4 - 640x960; f=5 - 512x768;";
document.getElementById("status_reg").value = null;
document.getElementById("reg_00").value = null;
document.getElementById("reg_01").value = null;
document.getElementById("reg_02").value = null;
document.getElementById("reg_03h").value = null;
document.getElementById("reg_03l").value = null;
document.getElementById("reg_05").value = null;
document.getElementById("reg_06").value = null;
document.getElementById("reg_07").value = null;
document.getElementById("reg_20").value = null;
document.getElementById("reg_44").value = null;
}
function brd359_channel_switch(_id) {
chn = document.getElementById(_id).value;
request = "./reg_write.php?adr=0x806&data=" + chn;
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_standard_response(request);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
var toggle_test_mode=false;
function brd359_toggle_test_mode() {
if (toggle_test_mode) {
toggle_test_mode=false;
request = "./reg_write.php?adr=0x48a0&data=0x00";
}else{
toggle_test_mode=true;
request = "./reg_write.php?adr=0x48a0&data=0x41";
}
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_standard_response(request);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_sdram_clk_shift(_dcm,_ps) {
request = "./phases_adjust.php?dcm="+ _dcm + "&n=1&phase_shift=" + _ps;
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_sdram_clk_shift_response(request,_dcm,_ps);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_sdram_clk_shift_response(_rq,_chn,_ps) {
pre_current_phase=document.getElementById("sdram_clk").value;
current_phase = pre_current_phase.substring(4,8); // 8 is just to be sure
document.getElementById("status_reg").value = _rq;//"ch"+ +_chn +"_phase";
if (_ps==8) current_phase = +current_phase - 90;
else current_phase = +current_phase + 90;
if (current_phase == -90) current_phase = 270;
if (current_phase == 360) current_phase = 0;
document.getElementById("sdram_clk").value = "sclk" + current_phase;
}
function brd359_phase_shift(_dcm,_ps) {
if (_ps<4) n = document.getElementById("N_phase_steps").value;
else n = 1;
request = "./phases_adjust.php?dcm="+ _dcm + "&n=" + n + "&phase_shift=" + _ps;
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_phase_shift_response(request,_dcm,_ps,n);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_phase_shift_response(_rq,_chn,_ps,_n) {
if (_chn==0) field="sclk0";
else field="ch"+ (+_chn-1);
if (_ps<4) field=field+"_phase";
else field=field+"_quarter";
current_phase=document.getElementById(field).value;
document.getElementById("status_reg").value = _rq;//"ch"+ +_chn +"_phase";
if (_ps==2) document.getElementById(field).value = +current_phase - +_n;
else if (_ps==1) document.getElementById(field).value = +current_phase + +_n;
else if (_ps==4) {
if (current_phase==3) document.getElementById(field).value = 0;
else document.getElementById(field).value = +current_phase + +_n;
}
else if (_ps==8) {
if (current_phase==0) document.getElementById(field).value = 3;
else document.getElementById(field).value = +current_phase - +_n;
}
}
function brd359_auto_phases() {
request = "./../test/test_inner_10359.php";
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_auto_phases_response;//brd359_auto_phases_response();
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_auto_phases_response() {
if(this.readyState == 1){
document.getElementById('status_reg').value="Working...";
//document.getElementById('rq_table').setAttribute('bgcolor','#FFD700');
}
if(this.readyState == 4) {
if(this.status != 200) {
alert("failed to start");
return;
}
//document.getElementById("status_reg2").value = _rq;
//xml = this.responseXML.getElementsByTagName("registers_read")[0];
//document.getElementById('rq_table').setAttribute('bgcolor','#C7F7C7');
document.getElementById('status_reg').value = "./../test/test_inner_10359.php";
}
}
function brd359_save_phases() {
sclk0_00= document.getElementById('sclk0_phase').value;
sclk0_90= document.getElementById('sclk0_quarter').value;
ch0_00= document.getElementById('ch0_phase').value;
ch0_90= document.getElementById('ch0_quarter').value;
ch1_00= document.getElementById('ch1_phase').value;
ch1_90= document.getElementById('ch1_quarter').value;
ch2_00= document.getElementById('ch2_phase').value;
ch2_90= document.getElementById('ch2_quarter').value;
request = "./../test/test_inner_10359.php?save&dcm0_90="+sclk0_90+"&dcm0="+sclk0_00+"&dcm1_90="+ch0_90+"&dcm1="+ch0_00+"&dcm2_90="+ch1_90+"&dcm2="+ch1_00+"&dcm3_90="+ch2_90+"&dcm3="+ch2_00;
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_save_phases_response;
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_save_phases_response() {
if(this.readyState == 1){
document.getElementById('status_reg').value="Working...";
//document.getElementById('rq_table').setAttribute('bgcolor','#FFD700');
}
if(this.readyState == 4) {
if(this.status != 200) {
alert("failed to start");
return;
}
//document.getElementById("status_reg2").value = _rq;
//xml = this.responseXML.getElementsByTagName("registers_read")[0];
//document.getElementById('rq_table').setAttribute('bgcolor','#C7F7C7');
document.getElementById('status_reg').value = "./../test/test_inner_10359.php";
}
}
function brd359_alt_mode() {
if (document.getElementById('btn_alt_mode').value=="start") {
if (document.getElementById('j3_on').checked) {
request = "./reg_write.php?adr=0x806&data=0x27";
} else if (document.getElementById('j4_on').checked) {
request = "./reg_write.php?adr=0x806&data=0x67";
} else {
alert("An extra sensor needs to be checked");
return;
}
document.getElementById('btn_alt_mode').value = "stop";
} else {
request = "./reg_write.php?adr=0x806&data=0x7";
document.getElementById('btn_alt_mode').value = "start";
}
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_standard_response(request);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_alt_buf_mode() {
if (document.getElementById('btn_alt_buf_mode').value=="start") {
if (document.getElementById('combine_into_one_frame').checked) {
_scale_factor=document.getElementById("scale_factor").value;
if (document.getElementById('j3_on').checked) {
request = "./10359_modes.php?mode=0&channel=2&combined&scale_factor=" + _scale_factor;
} else if (document.getElementById('j4_on').checked) {
request = "./10359_modes.php?mode=0&channel=4&combined&scale_factor=" + _scale_factor;
} else {
alert("An extra sensor needs to be checked");
return;
}
} else {
if (document.getElementById('j3_on').checked) {
request = "./10359_modes.php?mode=0&channel=2";
} else if (document.getElementById('j4_on').checked) {
request = "./10359_modes.php?mode=0&channel=4";
} else {
alert("An extra sensor needs to be checked");
return;
}
}
document.getElementById('btn_alt_buf_mode').value="stop";
document.getElementById('btn_alt_mode').value="start";
document.getElementById('combine_into_one_frame').disabled=true;
document.getElementById('btn_alt_mode').disabled=true;
document.getElementById('scale_factor').disabled=true;
} else {
if (document.getElementById('combine_into_one_frame').checked) {
_scale_factor=document.getElementById("scale_factor").value;
request = "./10359_modes.php?mode=0&combined&stop&scale_factor=" + _scale_factor;
} else {
request = "./10359_modes.php?mode=0&stop";
}
document.getElementById('btn_alt_buf_mode').value="start";
document.getElementById('combine_into_one_frame').disabled=false;
document.getElementById('btn_alt_mode').disabled=false;
document.getElementById('scale_factor').disabled=false;
}
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_standard_response(request);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_stereo_mode() {
if (document.getElementById('j3_on').checked) {
request = "./10359_modes.php?mode=1&channel=2";
} else if (document.getElementById('j4_on').checked) {
request = "./10359_modes.php?mode=1&channel=4";
} else {
alert("An extra sensor needs to be checked");
return;
}
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_standard_response(request);
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_read_regs() {
request = "./reg_read.php";
if(window.XMLHttpRequest) {
brd359_xml = new XMLHttpRequest();
brd359_xml.onreadystatechange = brd359_read_regs_response;
brd359_xml.open("GET", request, true);
brd359_xml.send(null);
} else {
alert("not Firefox?");
return;
}
}
function brd359_read_regs_response() {
if(this.readyState == 1){
document.getElementById('status_reg').value="Working...";
}
if(this.readyState == 4) {
if(this.status != 200) {
alert("failed to start");
return;
}
//document.getElementById("status_reg2").value = _rq;
xml = this.responseXML.getElementsByTagName("registers_read")[0];
version = xml.getElementsByTagName("reg_00")[0].textContent;
document.getElementById('reg_00').value = version;
_data= xml.getElementsByTagName("reg_01")[0].textContent;
document.getElementById('reg_01').value = _data;
document.getElementById('reg_35').value = _data;
_data= xml.getElementsByTagName("reg_02")[0].textContent;
document.getElementById('reg_02').value = _data;
_data= xml.getElementsByTagName("reg_03_h")[0].textContent;
document.getElementById('reg_03h').value = _data;
_data= xml.getElementsByTagName("reg_03_l")[0].textContent;
document.getElementById('reg_03l').value = _data;
_data= xml.getElementsByTagName("reg_05")[0].textContent;
document.getElementById('reg_05').value = _data;
_data= xml.getElementsByTagName("reg_06")[0].textContent;
document.getElementById('reg_06').value = _data;
_data= xml.getElementsByTagName("reg_07")[0].textContent;
document.getElementById('reg_07').value = _data;
_data= xml.getElementsByTagName("reg_20")[0].textContent;
document.getElementById('reg_20').value = _data;
_data= xml.getElementsByTagName("reg_44")[0].textContent;
document.getElementById('reg_44').value = _data;
dcm0_phase = xml.getElementsByTagName("reg_47")[0].textContent;
dcm0_phase_ = parseInt(dcm0_phase,16);
dcm0_phase_00 = dcm0_phase_ & 0x3ff;
dcm0_phase_90 = dcm0_phase_ >> 16;
if (dcm0_phase_00 >256) {
document.getElementById('sclk0_phase').value = dcm0_phase_00-512;
}else{
document.getElementById('sclk0_phase').value = dcm0_phase_00;
}
document.getElementById('sclk0_quarter').value = dcm0_phase_90;
dcm4_phase = xml.getElementsByTagName("reg_60")[0].textContent;
dcm4_phase_h= parseInt(dcm4_phase,16);
dcm4_phase_l= parseInt(dcm4_phase,16) & 0x3ff;
dcm4_phase_h = dcm4_phase_h >> 16;
document.getElementById('sdram_clk').value = "sclk" + (dcm4_phase_h*90);
if (dcm4_phase_l>256) {
document.getElementById('ch3_phase').value = dcm4_phase_l-512;
}else{
document.getElementById('ch3_phase').value = dcm4_phase_l;
}
dcm1_phase = xml.getElementsByTagName("reg_61")[0].textContent;
dcm1_phase_ = parseInt(dcm1_phase,16);
dcm1_phase_00 = dcm1_phase_ & 0x3ff;
dcm1_phase_90 = dcm1_phase_ >> 16;
if (dcm1_phase_00 >256) {
document.getElementById('ch0_phase').value = dcm1_phase_00-512;
}else{
document.getElementById('ch0_phase').value = dcm1_phase_00;
}
document.getElementById('ch0_quarter').value = dcm1_phase_90;
dcm2_phase = xml.getElementsByTagName("reg_62")[0].textContent;
dcm2_phase_ = parseInt(dcm2_phase,16);
dcm2_phase_00 = dcm2_phase_ & 0x3ff;
dcm2_phase_90 = dcm2_phase_ >> 16;
if (dcm2_phase_00 >256) {
document.getElementById('ch1_phase').value = dcm2_phase_00-512;
}else{
document.getElementById('ch1_phase').value = dcm2_phase_00;
}
document.getElementById('ch1_quarter').value = dcm2_phase_90;
dcm3_phase = xml.getElementsByTagName("reg_63")[0].textContent;
dcm3_phase_ = parseInt(dcm3_phase,16);
dcm3_phase_00 = dcm3_phase_ & 0x3ff;
dcm3_phase_90 = dcm3_phase_ >> 16;
if (dcm3_phase_00 >256) {
document.getElementById('ch2_phase').value = dcm3_phase_00-512;
}else{
document.getElementById('ch2_phase').value = dcm3_phase_00;
}
document.getElementById('ch2_quarter').value = dcm3_phase_90;
document.getElementById('status_reg').value = "./reg_read.php";
}
}
function brd359_standard_response(_rq) {
document.getElementById("status_reg").value = _rq;
}
//-->
</script>
</body>
</html>
test_scripts/10359_mem_test.php 0 → 100644
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : 10359_mem_test.php
*! DESCRIPTION: tests SDRAM and other memory
*! Copyright (C) 2009 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: 10359_mem_test.php,v $
*! Revision 1.1 2009/11/06 20:11:57 dzhimiev
*! new memory test
*!
*!
*/
require 'i2c.inc';
function receive_i2c_4($a) {
$i2c = fopen('/dev/xi2c16','r');
fseek ($i2c, 4, SEEK_END);
fseek ($i2c, 2*$a);
$data = fread($i2c, 4);
fclose($i2c);
if (strlen($data)<4) return -1;
$v=unpack('N*',$data);
return $v[1];
}
function send_i2c_4($a,$d) { //$a<0 - use raw read/write
$i2c=fopen('/dev/xi2c16','w');
fseek ($i2c,2*$a);
$res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
//printf("0x%02x%02x%02x%02x ",(floor($d/(256*256*256))),(($d - 256*256*256*floor($d/(256*256*256)))/(256*256)),(($d - 256*256*floor($d/(256*256)))/256),($d - 256*floor($d/(256))));
fclose($i2c);
return $res;
}
function ddr_page_write($shift) {
//fill a buffer
$j=0;
for ($i=0;$i<512;$i++) {
send_i2c_4(0x0802,0x1234);
printf("%04x ",0x1234);
if ($j==31) { $j=0; printf("\n");}
else $j++;
}
for ($i=0;$i<512;$i++) {
send_i2c_4(0x0802,$i+$shift);
printf("%04x ",$i+$shift);
if ($j==31) { $j=0; printf("\n");}
else $j++;
}
//write page, data does not matter
for ($i=0;$i<8;$i++) {
send_i2c_4(0x0803,0x0001);
}
printf("\n");
}
function ddr_page_read($color) {
$j=0;
//read page, data does not matter
for ($i=0;$i<8;$i++) {
send_i2c_4(0x0804,0x0001);
//sleep(1);
}
printf("<font color=#%06x>",$color);
$adr=0x0802;
for ($i=0;$i<1024;$i++) {
$data=receive_i2c_4($adr);
printf("%04x ",$data);
if ($j==31) { $j=0; printf("\n");}
else $j++;
}
printf("\n</font>\n");
}
$adr=0x0860;
$datax=5;
$nopars=false;
$raw=0;
$phase_shift=0;
$channel=2;
$lines1=1940;
$pixes1=2595;
$lines2=1940;
$pixes2=2595;
$delay=0x00ffffff;
$sphase=0x00000007;
$ch1_ch2_delay=115;
printf("<pre><TITLE>SDRAM test</TITLE>");
// initialization
send_i2c_4(0x0841,0x00017fff);
send_i2c_4(0x0841,0x00002002);
send_i2c_4(0x0841,0x00000163);
send_i2c_4(0x0841,0x00008000);
send_i2c_4(0x0841,0x00008000);
send_i2c_4(0x0841,0x00017fff);
send_i2c_4(0x0840,0x00010000);
send_i2c_4(0x0841,0x00005555);
send_i2c_4(0x0841,0x00020000);
send_i2c_4(0x0842,0x0007000f);
send_i2c_4(0x084c,0x000f020f);//send_i2c_4($width,$bus,0x084c,0x0008181f,$raw=0);
send_i2c_4(0x0854,0x1fff10ff);
send_i2c_4(0x084d,0x000f020f);//send_i2c_4($width,$bus,0x084d,0x0008181f,$raw=0);
send_i2c_4(0x0855,0x1fff10ff);
// unknown commands
send_i2c_4(0x0843,0x1c000c21);
send_i2c_4(0x0840,0x00005555);
send_i2c_4(0x0844,0x00000000);
send_i2c_4(0x0845,0x00000000);
send_i2c_4(0x0846,0x00010000);
send_i2c_4(0x0847,0x00010000);
send_i2c_4(0x0840,0x0000aaaa);
printf("SDRAM initialization sequence passed, channels programmed\n\n");
//send_i2c_4(0x0847,0x00000000);
//send_i2c_4(0x0847,0x00000001);
send_i2c_4(0x0805,0x00000001);
send_i2c_4(0x0805,0x00000000);
$adr=0x0800;
$data=receive_i2c_4($adr);
printf("Firmware Version <font size=\"6\">0x%08x</font>\n\n",$data);
printf("Page sent:\n");
for($i=0;$i<1;$i++) {
ddr_page_write(128*$i); // ddr_page_write writes 1024 words to a buffer and then transfer it with 16 writes to SDRAM
}
printf("Page received:\n");
for($i=0;$i<1;$i++) {
//sleep(1);
ddr_page_read(0x00007F+16*$i);
}
printf("</pre>");
?>
test_scripts/10359_modes.php 0 → 100755
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : 10359_modes.php
*! DESCRIPTION: switches between modes
*! Copyright (C) 2009 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: 10359_modes.php,v $
*! Revision 1.6 2010/05/13 17:20:18 dzhimiev
*! 1. for 10359 revA, should be compatible with rev0
*! 2. new command system
*! 3. recoded for Eyesis
*!
*! Revision 1.4 2010/01/04 05:32:27 dzhimiev
*! 1. added scale factor - for combined mode mostly, scale factor is set avoiding camvc
*!
*! Revision 1.3 2009/12/04 03:40:15 dzhimiev
*! 1. removed frame size setting - replaced with getting it from the sensor
*!
*! Revision 1.2 2009/12/02 04:45:10 dzhimiev
*! 1. added combining into one frame for alternating channels
*!
*!
*/
require 'i2c.inc';
function receive_i2c_4($width,$bus,$a,$raw=0) {
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'r');
fseek ($i2c, 4, SEEK_END);
fseek ($i2c, $w*$a);
$data = fread($i2c, 2*$w);
fclose($i2c);
if (strlen($data)<2*$w) return -1;
$v=unpack(($w==1)?'C*':'N*',$data);
//print_r($v);
//printf("0x%x\n",$v[1]);
return $v[1];
} // end of receive_i2c()
function send_i2c_4($width,$bus,$a,$d,$raw=0) { //$a<0 - use raw read/write
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'w');
fseek ($i2c, $w*$a) ;
if ($w==1) $res=fwrite($i2c, chr ($d));
else $res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
fclose($i2c);
return $res;
} // end of send_i2c()
function res_update($name, $result, $description) {
global $res_rpt;
if($result != "")
$res_rpt.="<${name} result=\"${result}\">".$description."</${name}>\n";
else
$res_rpt.="<${name}>".$description."</${name}>\n";
}
function _finish($res) {
global $res_rpt;
res_update("finish", $res, "");
$res_rpt.="</script>\n";
$res_xml=$res_rpt;
header("Content-Type: text/xml");
header("Content-Length: ".strlen($res_xml)."\n");
header("Pragma: no-cache\n");
printf("%s", $res_xml);
flush();
exit(0);
}
$width=16;
$bus=0;
$raw=0;
$pixes=2592;
$lines=1940;
$second_channel=2;
$mode=0;
$mode_start=true;
$combined=false;
$scale_factor=1;
$res_rpt="<?xml version='1.0' standalone='yes'?>\n<script name=\"modes control\">\n";
foreach($_GET as $key=>$value) {
switch($key) {
case "x" : $camvc_pixes = $value+0; break;
case "y" : $camvc_lines = $value+0; break;
case "mode" : $mode=$value+0; break;
case "channel" : $second_channel=$value+0; break;
case "start" : $mode_start=true; break;
case "stop" : $mode_start=false; break;
case "combined" : $combined=true; break;
case "scale_factor" : $scale_factor=$value+0; break;
}
}
// alternation mode with buffering
if ($mode==0) {
// switch to broadcast channel to program all the sensors at once
$adr=0x0806;
//printf("<h3>Set channel to broadcast</h3>");
res_update("step_01", "ok", "set channel to broadcast");
//send_i2c_4($width,$bus,$adr,0x7,$raw=0);
i2c_send(16, 0, $adr, 0x7, 0);
// sleep(1);
$some_x=i2c_receive(16,0,0x4804,0);
res_update("step_01a", "ok", "got x-size from the sensor:${some_x}");
$some_y=i2c_receive(16,0,0x4803,0);
res_update("step_01b", "ok", "got y-size from the sensor:${some_y}");
if ($mode_start) {
$camvc_pixes=$some_x-3;
$camvc_lines=$some_y-3;
//disable all
//printf("<h3>disable 10359 input/output</h3>");
res_update("step_02", "ok", "disable 10359 input/output");
$adr=0x808;
//send_i2c_4($width,$bus,$adr,0x2,$raw=0);
i2c_send(16, 0, $adr, 0x2, 0);
//sleep(1);
// reset regs
//printf("<h3>regs reset</h3>");
res_update("step_03", "ok", "regs reset");
$adr=0x0808;
//send_i2c_4($width,$bus,$adr,0x3,$raw=0);
//send_i2c_4($width,$bus,$adr,0x2,$raw=0);
i2c_send(16, 0, $adr, 0x3, 0);
i2c_send(16, 0, $adr, 0x2, 0);
if ($combined) {
$pixes_to_10359=$camvc_pixes+4;
$lines_to_10359=$camvc_lines/2+2;
$pixes_to_sensor=$scale_factor*$camvc_pixes+4*$scale_factor;
$lines_to_sensor=$scale_factor*$camvc_lines/2+2*$scale_factor;
} else {
$pixes_to_10359=$camvc_pixes+4;
$lines_to_10359=$camvc_lines+4;
$pixes_to_sensor=$camvc_pixes+4;
$lines_to_sensor=$camvc_lines+4;
}
//program mcontr
$adr=0x0837; //to_change
send_i2c_4($width,$bus,$adr,(0x10000*$lines_to_10359)+$pixes_to_10359,$raw=0);
//printf("\nSet ch0 frame resolution to <font size=\"6\">$camvc_pixes"."x$camvc_lines</font>\n");
res_update("step_04", "ok", "Set ch0 frame resolution to ".$pixes_to_10359."x".$lines_to_10359);
$adr=0x083c; //to_change
send_i2c_4($width,$bus,$adr,(0x10000*$lines_to_10359)+$pixes_to_10359,$raw=0);
//printf("\nSet ch1 frame resolution to <font size=\"6\">$camvc_pixes"."x$camvc_lines</font>\n");
res_update("step_05", "ok", "Set ch1 frame resolution to ".$pixes_to_10359."x".$lines_to_10359);
send_i2c_4($width,$bus,0x0840,0x00015555,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00017fff,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00002002,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00000163,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00008000,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00008000,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00017fff,$raw=0);
send_i2c_4($width,$bus,0x0840,0x00010000,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00005555,$raw=0);
send_i2c_4($width,$bus,0x0841,0x00020000,$raw=0);
send_i2c_4($width,$bus,0x0842,0x0007000f,$raw=0);
send_i2c_4($width,$bus,0x084c,0x000f020f,$raw=0);//send_i2c_4($width,$bus,0x084c,0x0008181f,$raw=0);
send_i2c_4($width,$bus,0x0854,0x1fff10ff,$raw=0);
send_i2c_4($width,$bus,0x084d,0x000f020f,$raw=0);//send_i2c_4($width,$bus,0x084d,0x0008181f,$raw=0);
send_i2c_4($width,$bus,0x0855,0x1fff10ff,$raw=0);
send_i2c_4($width,$bus,0x0843,0x1c000c21,$raw=0);
send_i2c_4($width,$bus,0x0840,0x00005555,$raw=0);
send_i2c_4($width,$bus,0x0844,0x00000000,$raw=0);
send_i2c_4($width,$bus,0x0845,0x00000000,$raw=0);
send_i2c_4($width,$bus,0x0846,0x00010000,$raw=0);
send_i2c_4($width,$bus,0x0847,0x00010000,$raw=0);
send_i2c_4($width,$bus,0x0840,0x0000aaaa,$raw=0);
// reset to regs
$adr=0x0808;
//printf("<h3>control reset</h3>");
res_update("step_06", "ok", "control reset");
//send_i2c_4($width,$bus,$adr,0x3,$raw=0);
//send_i2c_4($width,$bus,$adr,0x2,$raw=0);
i2c_send(16, 0, $adr, 0x3, 0);
i2c_send(16, 0, $adr, 0x2, 0);
// sleep(2);
// program sensors
$pixes_hex=dechex($pixes_to_sensor-1);
exec("fpcf -i2cw16 4804 ${pixes_hex}");
//printf("<h3>Sensors programmed Reg: 0x4803 Data: 0x${lines_hex}</h3>");
res_update("step_07", "ok", "Sensors programmed Reg: 0x4804 Data: ${pixes_to_sensor}");
$lines_hex=dechex($lines_to_sensor-1);
exec("fpcf -i2cw16 4803 ${lines_hex}");
//printf("<h3>Sensors programmed Reg: 0x4803 Data: 0x${lines_hex}</h3>");
res_update("step_07", "ok", "Sensors programmed Reg: 0x4803 Data: ${lines_to_sensor}");
$sf=$scale_factor-1;
exec("fpcf -i2cw16 4802 c");
exec("fpcf -i2cw16 4823 ${sf}");
exec("fpcf -i2cw16 4822 ${sf}");
// some useless commands
send_i2c_4($width,$bus,0x0847,0x00000000,$raw=0);
send_i2c_4($width,$bus,0x0847,0x00000001,$raw=0);
// combine mode on
//printf("<h3>Go</h3>");
res_update("step_08", "ok", "mode started");
$adr=0x0808;
//send_i2c_4($width,$bus,$adr,0x00,$raw=0);
i2c_send(16, 0, $adr, 0x00, 0);
if ($second_channel==4) {
if ($combined) send_i2c_4($width,$bus,$adr,0x0c,$raw=0);
else send_i2c_4($width,$bus,$adr,0x1c,$raw=0);
}else{
if ($combined) send_i2c_4($width,$bus,$adr,0x04,$raw=0);
else send_i2c_4($width,$bus,$adr,0x14,$raw=0);
}
} else {
$camvc_pixes=$some_x;
$camvc_lines=$some_y;
res_update("step_03", "ok", "disable output");
$adr=0x0808;
//send_i2c_4($width,$bus,$adr,0x06,$raw=0);
i2c_send(16, 0, $adr, 0x6, 0);
sleep(1);
res_update("step_04", "ok", "keep disable + reset");
$adr=0x0808;
//send_i2c_4($width,$bus,$adr,0x03,$raw=0);
i2c_send(16, 0, $adr, 0x3, 0);
if ($combined) {
$pixes=($camvc_pixes+1)/$scale_factor;
$lines=2*($camvc_lines+1)/$scale_factor;
//reprogram sensor
$pixes_hex=dechex($pixes-1);
exec("fpcf -i2cw16 4804 ${pixes_hex}");
$lines_hex=dechex($lines-1);
exec("fpcf -i2cw16 4803 ${lines_hex}");
exec("fpcf -i2cw16 4823 0");
exec("fpcf -i2cw16 4822 0");
//printf("<h3>Sensors vertical resolution is reprogrammed back - Reg: 0x4803 Data: 0x${lines_hex}</h3>");
res_update("step_05", "ok", "sensors vertical resolution is set back - Reg: 0x4803 Data: 0x${lines_hex}");
sleep(1);
}
res_update("step_06", "ok", "enable 10359 input/output");
$adr=0x0808;
//send_i2c_4($width,$bus,$adr,0x0,$raw=0);
i2c_send(16, 0, $adr, 0x0, 0);
}
}
_finish("ok");
//printf("</pre>");
?>
test_scripts/phases_adjust.php 0 → 100644
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : phases_adjust.php
*! DESCRIPTION: phase shifting for 10359 DCMs
*! Copyright (C) 2008 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: phases_adjust.php,v $
*! Revision 1.4 2010/05/13 17:20:18 dzhimiev
*! 1. for 10359 revA, should be compatible with rev0
*! 2. new command system
*! 3. recoded for Eyesis
*!
*! Revision 1.1 2009/02/13 09:53:10 dzhimiev
*! 1. removed old scripts
*! 2. added new with registers reading and writing, phase shifting and programming other sensors of 10359
*!
*! Revision 1.1 2008/06/23 08:11:58 dzhimiev
*! 1. added more scripts for 10359 board
*!
*! Revision 1.2 2008/06/16 07:43:58 dzhimiev
*! mcontr address range changed from 0x0820-0x082F to 0x0840-0x085F (for making extra channels)
*!
*! Revision 1.2 2008/02/13 00:30:01 elphel
*! Added system time synchronization with "CMOS" clock
*!
*! Revision 1.1 2008/02/12 21:53:20 elphel
*! Modified I2c to support multiple buses, added raw access (no address registers) and per-slave protection bitmasks
*!
*!
*/
require 'i2c.inc';
function receive_i2c_4($width,$bus,$a,$raw=0) {
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'r');
fseek ($i2c, 4, SEEK_END);
fseek ($i2c, $w*$a);
$data = fread($i2c, 2*$w);
fclose($i2c);
if (strlen($data)<2*$w) return -1;
$v=unpack(($w==1)?'C*':'N*',$data);
//print_r($v);
//printf("0x%x\n",$v[1]);
return $v[1];
} // end of receive_i2c()
function send_i2c_4($width,$bus,$a,$d,$raw=0) { //$a<0 - use raw read/write
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'w');
fseek ($i2c, $w*$a) ;
if ($w==1) $res=fwrite($i2c, chr ($d));
else $res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
//printf("Sending passage ");
//printf("0x%02x%02x%02x%02x ",(floor($d/(256*256*256))),(($d - 256*256*256*floor($d/(256*256*256)))/(256*256)),(($d - 256*256*floor($d/(256*256)))/256),($d - 256*floor($d/(256))));
//printf("\n");
fclose($i2c);
return $res;
} // end of send_i2c()
function dcm_reset($width,$bus,$raw=0){
printf("<font size=\"4\">Resetting DCMs</font>\n");
printf("sent 0x%04x ",0x0810); send_i2c_4($width,$bus,0x0810,0xffffffff,$raw=0);
printf("\nsent 0x%04x ",0x0810); send_i2c_4($width,$bus,0x0810,0x00000000,$raw=0);
printf("\n\n");
}
$width=16;
$bus=0;
$raw=0;
$phase_shift=0;
$dcm_addr=0;
$n=1;
$sphase=0x7;
printf("<pre><title>Phases adjust</title>");
foreach($_GET as $key=>$value) {
switch($key) {
case "rst" : $dcm_rst=$value+0; break;
case "dcm" : $dcm_addr=$value+0; break;
case "phase_shift" : $phase_shift=$value+0; break;
case "n" : $n=$value+0; break;
case "sphase" : $sphase=$value+0; break;
}
}
if ($dcm_rst==1) {
dcm_reset($width,$bus,$raw=0);
}
switch($dcm_addr) {
case 0 : $adr=0x0801; break; // sclk0
case 4 : $adr=0x0802; break; // SDRAM
case 1 : $adr=0x0803; break; // sensor1
case 2 : $adr=0x0804; break; // sensor2
case 3 : $adr=0x0805; break; // sensor3
default : $adr=5;
}
if ($dcm_addr<>5){
for($i=0;$i<$n;$i++){
//send_i2c_4($width,$bus,$adr,$phase_shift,$raw=0);
i2c_send(16, 0, $adr, $phase_shift, 0);
usleep(1);
}
printf("DCM %d, number of shifts applied: <font size=\"6\">%d</font>\n",$dcm_addr,$n);
}
//$adr=0x083a;
//send_i2c_4($width,$bus,$adr,$sphase,$raw=0);
if (($sphase & 0x1)==0x1) printf("S1. Vact/Hact - sclk0 FALLING edge, PXD - sclk0 FALLING edge\n");
else printf("S1. Vact/Hact - sclk0 RISING edge, PXD - sclk0 FALLING edge\n");
if (($sphase & 0x2)==0x2) printf("S2. Vact/Hact - sclk0 FALLING edge, PXD - sclk0 FALLING edge\n");
else printf("S2. Vact/Hact - sclk0 RISING edge, PXD - sclk0 FALLING edge\n");
if (($sphase & 0x4)==0x4) printf("S3. Vact/Hact - sclk0 FALLING edge, PXD - sclk0 FALLING edge\n");
else printf("S3. Vact/Hact - sclk0 RISING edge, PXD - sclk0 FALLING edge\n");
$adr=0x0861;
$data=receive_i2c_4($width,$bus,$adr,$raw=0);
printf("read 0x%04x : DCM1 phase step number is <font size=\"6\">0x%08x</font>\n",$adr,$data);
$adr=0x0862;
$data=receive_i2c_4($width,$bus,$adr,$raw=0);
printf("read 0x%04x : DCM_S2 phase step number is <font size=\"6\">0x%08x</font>\n",$adr,$data);
$adr=0x0863;
$data=receive_i2c_4($width,$bus,$adr,$raw=0);
printf("read 0x%04x : DCM_S3 phase step number is <font size=\"6\">0x%08x</font>\n",$adr,$data);
printf("</pre>");
?>
test_scripts/reg_read.php 0 → 100644
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : reg_read.php
*! DESCRIPTION: reads some control and test registers of 10359 board
*! Copyright (C) 2008 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: reg_read.php,v $
*! Revision 1.4 2010/05/13 17:20:18 dzhimiev
*! 1. for 10359 revA, should be compatible with rev0
*! 2. new command system
*! 3. recoded for Eyesis
*!
*! Revision 1.2 2009/08/24 19:07:09 dzhimiev
*! 1. correct xml output
*!
*! Revision 1.1 2009/02/13 09:53:10 dzhimiev
*! 1. removed old scripts
*! 2. added new with registers reading and writing, phase shifting and programming other sensors of 10359
*!
*! Revision 1.1 2008/04/23 01:55:50 dzhimiev
*! 1. added x359 files to src lists
*! 2. x359 read/write DDR
*! 3. x359 3 channels mux directly to out
*! 4. x359 one channel through DDR and another directly frames switching at out
*!
*/
require 'i2c.inc';
function receive_i2c_4($width,$bus,$a,$raw=0) {
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'r');
fseek ($i2c, 4, SEEK_END);
fseek ($i2c, $w*$a);
$data = fread($i2c, 2*$w);
fclose($i2c);
if (strlen($data)<2*$w) return -1;
$v=unpack(($w==1)?'C*':'N*',$data);
//print_r($v);
//printf("0x%x\n",$v[1]);
return $v[1];
} // end of receive_i2c()
function send_i2c_4($width,$bus,$a,$d,$raw=0) { //$a<0 - use raw read/write
$w=($width==16)?2:1;
$i2c_fn='/dev/xi2c'.($raw?'raw':(($w==2)?'16':'8')).(($bus==0)?'':'_aux');
$i2c = fopen($i2c_fn, 'w');
fseek ($i2c, $w*$a) ;
if ($w==1) $res=fwrite($i2c, chr ($d));
else $res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
//printf("Sending passage ");
printf("0x%02x%02x%02x%02x ",(floor($d/(256*256*256))),(($d - 256*256*256*floor($d/(256*256*256)))/(256*256)),(($d - 256*256*floor($d/(256*256)))/256),($d - 256*floor($d/(256))));
//printf("\n");
fclose($i2c);
return $res;
} // end of send_i2c()
$res_xml = "<?xml version='1.0' standalone='yes'?>\n<registers_read>\n";
//$res_xml = "<Registers_read>\n";
$adr=0x0800;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_00>".dechex($data)."</reg_00>\n";//firmware version
$adr=0x0801;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_01>".dechex($data)."</reg_01>\n";//correlation status
$adr=0x0802;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_02>".dechex($data)."</reg_02>\n";
$adr=0x0803;
$data_l=receive_i2c_4(16,0,$adr,0);
$data_h=i2c_receive(16,0,$adr,0);
$res_xml .= "<reg_03_h>".dechex($data_h)."</reg_03_h>\n";
$res_xml .= "<reg_03_l>".dechex($data_l-0x10000*(floor($data_l/0x10000)))."</reg_03_l>\n";
$adr=0x0805;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_05>".dechex($data)."</reg_05>\n";
$adr=0x0806;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_06>".dechex($data)."</reg_06>\n";
$adr=0x0807;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_07>".dechex($data)."</reg_07>\n";
$adr=0x0820;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_20>".dechex($data)."</reg_20>\n";
$adr=0x0844;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_44>".dechex($data)."</reg_44>\n";
$adr=0x0845;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_45>".dechex($data)."</reg_45>\n";
$adr=0x0846;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_46>".dechex($data)."</reg_46>\n";
//sclk0
$adr=0x0847;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_47>".dechex($data)."</reg_47>\n";
//ch0 clk
$adr=0x0860;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_60>".dechex($data)."</reg_60>\n";
// ch1 clk
$adr=0x0861;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_61>".dechex($data)."</reg_61>\n";
// ch2 clk
$adr=0x0862;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_62>".dechex($data)."</reg_62>\n";
$adr=0x0863;
$data=receive_i2c_4(16,0,$adr,0);
$res_xml .= "<reg_63>".dechex($data)."</reg_63>\n";
$res_xml .= "</registers_read>\n";
header("Content-Type: text/xml");
header("Content-Length: ".strlen($res_xml)."\n");
header("Pragma: no-cache\n");
printf("%s", $res_xml);
flush();
?>
test_scripts/reg_write.php 0 → 100644
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : reg_write.php
*! DESCRIPTION: writes data to 10359 registers, addresses start with 0x800
*! Copyright (C) 2008 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: reg_write.php,v $
*! Revision 1.3 2010/05/13 17:20:18 dzhimiev
*! 1. for 10359 revA, should be compatible with rev0
*! 2. new command system
*! 3. recoded for Eyesis
*!
*! Revision 1.1 2009/02/13 09:53:10 dzhimiev
*! 1. removed old scripts
*! 2. added new with registers reading and writing, phase shifting and programming other sensors of 10359
*!
*! Revision 1.1 2008/06/23 08:11:58 dzhimiev
*! 1. added more scripts for 10359 board
*!
*! Revision 1.2 2008/06/16 07:43:58 dzhimiev
*! mcontr address range changed from 0x0820-0x082F to 0x0840-0x085F (for making extra channels)
*!
*! Revision 1.1 2008/04/23 01:55:50 dzhimiev
*! 1. added x359 files to src lists
*! 2. x359 read/write DDR
*! 3. x359 3 channels mux directly to out
*! 4. x359 one channel through DDR and another directly frames switching at out
*!
*/
require 'i2c.inc';
function send_i2c_4($a,$d) {
$i2c = fopen('/dev/xi2c16', 'w');
fseek ($i2c, 2*$a) ;
if ($w==1) $res=fwrite($i2c, chr ($d));
else $res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
fclose($i2c);
return $res;
}
$adr=0x0000;
$data=0x0000;
$width=16;
printf("<pre>");
foreach($_GET as $key=>$value) {
switch($key) {
case "adr" : $adr=$value+0; break;
case "data" : $data=$value+0; break;
case "width" : $width=$value+0; break;
}
}
if ($width==32) {
send_i2c_4($adr,$data);
}else{
i2c_send(16, 0, $adr, $data, 0);
}
switch($adr) {
case 0x806 : printf("\nSet channel to <font size=\"6\">$data</font>\n"); break;
default : printf("Wrote \nAddress: 0x%04x\nData : 0x%08x\n",$adr,$data);
}
printf("</pre>");
?>
test_scripts/sensors_init.php 0 → 100644
View file @ 1727b764
<?php
/*!***************************************************************************
*! FILE NAME : sensors_init.php
*! DESCRIPTION: reads parameters from the sensor 1 and writes to other sensors
*! Copyright (C) 2008 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*! $Log: sensors_init.php,v $
*! Revision 1.4 2009/02/26 14:02:39 dzhimiev
*! 1. added a pause after channel switching - it appears to be more stable
*!
*! Revision 1.4 2008/06/23 08:11:58 dzhimiev
*! 1. added more scripts for 10359 board
*!
*! Revision 1.2 2008/05/22 22:57:54 dzhimiev
*! + 0x0800 - current channel number register
*! + DCMs independent phase adjustment
*! useful scripts
*!
*! Revision 1.2 2008/05/01 20:32:29 dzhimiev
*! reads each sensor registers after configuration
*!
*! Revision 1.1 2008/04/23 01:55:49 dzhimiev
*! 1. added x359 files to src lists
*! 2. x359 read/write DDR
*! 3. x359 3 channels mux directly to out
*! 4. x359 one channel through DDR and another directly frames switching at out
*!
*/
require 'i2c.inc';
function apply_def_settings($pass) {
$DEF_QUALITY = 96;
$DEF_WOI_WIDTH = 10000;
$DEF_WOI_HEIGHT = 10000;
// sample gamma == 1.0
$DEF_GAMMA = 6554624;
$DEF_COLOR = 2; // color mode - "color, YCbCr 4:2:0, 3x3 pixels"
// copy predefined settings with autocampars.php
$conf_xml = simplexml_load_file("/etc/autocampars.xml");
foreach($conf_xml->paramSets->children() as $paramSet) {
$numSet = (integer)$paramSet->attributes()->number;
if($numSet == 0) {
if($pass == 1 || $pass == 2 || $pass == 0) {
$paramSet->QUALITY = $DEF_QUALITY;
$paramSet->WOI_WIDTH = $DEF_WOI_WIDTH;
$paramSet->WOI_HEIGHT = $DEF_WOI_HEIGHT;
$paramSet->GTAB_R = $DEF_GTAB_R;
$paramSet->GTAB_G = $DEF_GTAB_G;
$paramSet->GTAB_B = $DEF_GTAB_B;
$paramSet->GTAB_GB = $DEF_GTAB_GB;
$paramSet->SENSOR_RUN = 2;
$paramSet->COMPRESSOR_RUN = 2;
$paramSet->GAINR = 0x20000;
$paramSet->GAING = 0x20000;
$paramSet->GAINB = 0x20000;
$paramSet->GAINGB = 0x20000;
$paramSet->RSCALE = 0x10000;
$paramSet->GSCALE = 0x10000;
$paramSet->BSCALE = 0x10000;
$paramSet->DGAINR = 32768;
$paramSet->DGAING = 32768;
$paramSet->DGAINGB = 32768;
$paramSet->DGAINB = 32768;
$paramSet->COLOR = 1;
$paramSet->AUTOEXP_ON = 0;
$paramSet->GAIN_MIN = 0x10000;
$paramSet->GAIN_MAX = 0x10000;
$paramSet->ANA_GAIN_ENABLE = 0;
// daemons
$paramSet->DAEMON_EN = 0;
$paramSet->DAEMON_EN_AUTOEXPOSURE = 0;
$paramSet->DAEMON_EN_STREAMER = 0;
$paramSet->DAEMON_EN_CCAMFTP = 0;
$paramSet->DAEMON_EN_CAMOGM = 0;
$paramSet->DAEMON_EN_AUTOCAMPARS = 0;
}
if($pass == 0) { // for SDRAM test
$paramSet->SENSOR_RUN = 0;
$paramSet->COMPRESSOR_RUN = 0;
}
}
}
$z = $conf_xml->asXml();
$f = fopen('/tmp/cd359_def.xml', 'w+');
fwrite($f, $z);
fclose($f);
exec('wget http://127.0.0.1/autocampars.php?load=/tmp/cd359_def.xml');
}
function sensor_init($init_pars){
for ($i=0;$i<256;$i++){
i2c_send(16,0,0x4800+$i,$init_pars[$i],0);
$readout=i2c_receive(16,0,0x4800+$i,0);
printf("%04x ",$readout);
if($j==15){
$j=0; printf("\n");
}else{
$j++;
}
}
printf("\n");
}
function dcm_reset(){
printf("sent 0x%04x \n",0x0810); send_i2c_4(0x0810,0xffffffff);
printf("sent 0x%04x \n",0x0810); send_i2c_4(0x0810,0x00000000);
}
function send_i2c_4($a,$d) {
$i2c = fopen('/dev/xi2c16','w');
fseek ($i2c, 2*$a) ;
$res=fwrite($i2c, chr (floor($d/(256*256*256))).chr (($d - 256*256*256*floor($d/(256*256*256)))/(256*256)).chr (($d - 256*256*floor($d/(256*256)))/256).chr ($d - 256*floor($d/(256))) );
fclose($i2c);
return $res;
} // end of send_i2c()
printf("<pre>\n");
//! Start with reset (normally not needed, just to make sure we have a clean start, not relying on previous programming)
// everything was already set but autocampars.php at boot
// set new parameters
send_i2c_4(0x0835,0x00000001); printf("\nReading parameters from sensor <font size=\"6\">1</font>\n");
exec("fpcf -i2cw16 48a0 0041");
sleep(1);
apply_def_settings(0);
sleep(2);
apply_def_settings(1);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
sleep(3);
apply_def_settings(2);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
// read sensor parameters
for ($i=0;$i<256;$i++){
$init_pars3[$i]=i2c_receive(16,0,0x4800+$i,0);
printf("%04x ",$init_pars3[$i]);
if($j==15){
$j=0; printf("\n");
}else{
$j++;
}
}
send_i2c_4(0x0835,0x00000002); printf("\nInitializing sensor <font size=\"6\">2</font>\n");
sensor_init($init_pars3);
exec("fpcf -i2cw16 48a0 0041");
sleep(1);
apply_def_settings(0);
sleep(2);
apply_def_settings(1);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
sleep(3);
apply_def_settings(2);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
send_i2c_4(0x0835,0x00000004); printf("\nInitializing sensor <font size=\"6\">3</font>\n");
sensor_init($init_pars3);
exec("fpcf -i2cw16 48a0 0041");
sleep(1);
apply_def_settings(0);
sleep(2);
apply_def_settings(1);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
sleep(3);
apply_def_settings(2);
for($i = 0; $i < 6; $i++) exec('wget http://127.0.0.1:8081/noexif/next/wait/img -O /dev/null');
send_i2c_4(0x0835,0x00000001); printf("\nSwitch back to sensor <font size=\"6\">1</font>\n");
printf("</pre>\n");
?>
x359.bit 0 → 100644
View file @ 1727b764
File added
x359.par 0 → 100644
View file @ 1727b764
Release 10.1.03 par K.39 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
inspiron:: Tue Jan 17 14:09:36 2012
par -w -intstyle ise -ol std -t 2 x359_map.ncd x359.ncd x359.pcf
Constraints file: x359.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment /opt/Xilinx/10.1/ISE.
"x359" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
WARNING:Timing:3223 - Timing constraint TS_PX_CHDL = MAXDELAY FROM TIMEGRP "TNM_PX" TO TIMEGRP "TG_CHDL" 8 ns; ignored
during timing analysis.
INFO:Timing:3377 - Intersecting Constraints found and resolved. For more information see the TSI report.
Device speed data version: "PRODUCTION 1.27 2008-01-09".
WARNING:Par:426 - The cost table specified for par "-t 2" is different from map "-t 1". Par will use the map cost table.
Design Summary Report:
Number of External IOBs 134 out of 190 70%
Number of External Input IOBs 52
Number of External Input DIFFMIs 1
Number of LOCed External Input DIFFMIs 1 out of 1 100%
Number of External Input DIFFSIs 1
Number of LOCed External Input DIFFSIs 1 out of 1 100%
Number of External Input IBUFs 50
Number of LOCed External Input IBUFs 49 out of 50 98%
Number of External Output IOBs 60
Number of External Output DIFFMs 1
Number of LOCed External Output DIFFMs 1 out of 1 100%
Number of External Output DIFFSs 1
Number of LOCed External Output DIFFSs 1 out of 1 100%
Number of External Output IOBs 58
Number of LOCed External Output IOBs 58 out of 58 100%
Number of External Bidir IOBs 22
Number of External Bidir IOBs 22
Number of LOCed External Bidir IOBs 22 out of 22 100%
Number of BUFGMUXs 8 out of 24 33%
Number of LOCed BUFGMUXs 1 out of 8 12%
Number of DCMs 5 out of 8 62%
Number of RAMB16s 16 out of 28 57%
Number of Slices 3262 out of 8672 37%
Number of SLICEMs 49 out of 4336 1%
Overall effort level (-ol): Standard
Router effort level (-rl): Standard
Starting initial Timing Analysis. REAL time: 19 secs
Finished initial Timing Analysis. REAL time: 19 secs
Starting Router
Phase 1: 18754 unrouted; REAL time: 25 secs
Phase 2: 15689 unrouted; REAL time: 26 secs
Phase 3: 4011 unrouted; REAL time: 30 secs
Phase 4: 4011 unrouted; (24143) REAL time: 30 secs
Phase 5: 4022 unrouted; (208) REAL time: 34 secs
Phase 6: 4023 unrouted; (0) REAL time: 36 secs
Phase 7: 0 unrouted; (0) REAL time: 42 secs
Phase 8: 0 unrouted; (0) REAL time: 46 secs
Phase 9: 0 unrouted; (0) REAL time: 49 secs
WARNING:Route - CLK Net:new_clk0 is being routed on general routing resources. Please consider using a dedicated
clocking routing resource. For more information on clock routing resources, see the target architecture's user guide.
Total REAL time to Router completion: 52 secs
Total CPU time to Router completion: 50 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
WARNING:ParHelpers:79 -
The following Clock signals are not routed on the dedicated
global clock routing resources. This will usually result in
longer delays and higher skew for the clock load pins. This could
be the result of incorrect clock placement, more than 8 clocks
feeding logic in a single quadrant of the device, or incorrect
logic partitioning into the quadrant(s). Check the timing report
to verify the delay and skew for this net
Net Name: pclk
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sp0_clk | BUFGMUX_X3Y6| No | 89 | 0.167 | 0.289 |
+---------------------+--------------+------+------+------------+-------------+
| sclk0 | BUFGMUX_X2Y0| No | 2048 | 0.209 | 0.378 |
+---------------------+--------------+------+------+------------+-------------+
| i_sp2/clkout | BUFGMUX_X1Y11| No | 90 | 0.089 | 0.313 |
+---------------------+--------------+------+------+------------+-------------+
| i_sp1/clkout | BUFGMUX_X3Y5| No | 89 | 0.132 | 0.289 |
+---------------------+--------------+------+------+------------+-------------+
| sclk270 | BUFGMUX_X2Y1| No | 53 | 0.118 | 0.373 |
+---------------------+--------------+------+------+------------+-------------+
| sensor_clock | BUFGMUX_X2Y10|Yes | 35 | 0.201 | 0.372 |
+---------------------+--------------+------+------+------------+-------------+
| iaro | BUFGMUX_X1Y0| No | 2 | 0.068 | 0.254 |
+---------------------+--------------+------+------+------------+-------------+
| pclk | Local| | 285 | 0.341 | 0.514 |
+---------------------+--------------+------+------+------------+-------------+
| new_clk1 | Local| | 8 | 0.067 | 1.548 |
+---------------------+--------------+------+------+------------+-------------+
| new_clk0 | Local| | 9 | 0.778 | 3.020 |
+---------------------+--------------+------+------+------------+-------------+
| new_clk2 | Local| | 4 | 0.004 | 1.493 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
Number of Timing Constraints that were not applied: 52
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk0_1 = PERIOD TIMEGR | SETUP | 0.013ns| 9.474ns| 0| 0
P "i_dcm_359_1_pre_clk0_1" TS_DCLK | HOLD | 0.763ns| | 0| 0
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x180_3 = PERIOD TIMEGRP "i_s | SETUP | 0.080ns| 4.590ns| 0| 0
p1_dcm2x180_3" TS_DCLK / 2 PHASE | HOLD | 0.987ns| | 0| 0
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x180_3 = PERIOD TIMEGRP "i_s | SETUP | 0.084ns| 4.666ns| 0| 0
p2_dcm2x180_3" TS_DCLK / 2 PHASE | HOLD | 0.988ns| | 0| 0
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_I2C_RA_DAs = MAXDELAY FROM TIMEGRP "TG | SETUP | 0.105ns| 8.895ns| 0| 0
_I2C_REG_ADDR" TO TIMEGRP "TNM_DAs" 9 | | | | |
ns | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x180_3 = PERIOD TIMEGRP "i_s | SETUP | 0.166ns| 4.584ns| 0| 0
p0_dcm2x180_3" TS_DCLK / 2 PHASE | HOLD | 1.080ns| | 0| 0
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_DCLK = PERIOD TIMEGRP "TNM_DCLK" 9.5 n | SETUP | 0.658ns| 8.827ns| 0| 0
s HIGH 50% | HOLD | 0.955ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_CHDL_DIR = MAXDELAY FROM TIMEGRP "TG_C | SETUP | 0.813ns| 5.887ns| 0| 0
HDL" TO TIMEGRP "TG_DIR" 6.7 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_I2C_CT_DAs = MAXDELAY FROM TIMEGRP "TG | SETUP | 0.826ns| 8.174ns| 0| 0
_I2C_CNT" TO TIMEGRP "TNM_DAs" 9 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_SC = PERIOD TIMEGRP "SENSOR_CLK" 8.5 n | SETUP | 0.851ns| 6.798ns| 0| 0
s HIGH 50% | HOLD | 0.968ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_CHMUX_DIR = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 1.784ns| 4.916ns| 0| 0
CHMUX" TO TIMEGRP "TG_DIR" 6.7 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk270_1 = PERIOD TIME | SETUP | 1.851ns| 5.798ns| 0| 0
GRP "i_dcm_359_1_pre_clk270_1" TS | HOLD | 5.788ns| | 0| 0
_DCLK PHASE 7.125 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_ihact_ihact = MAXDELAY FROM TIMEGRP "T | SETUP | 2.447ns| 5.553ns| 0| 0
G_ihact" TO TIMEGRP "TG_ihact" 8 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_SENSOR_CLOCK_TO_PADS_DCM = MAXDELAY FR | MAXDELAY| 3.171ns| 1.829ns| 0| 0
OM TIMEGRP "TP_SENSOR_CLOCK_SOURCE" | | | | |
TO TIMEGRP "SENSOR_CLK" 5 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_PXDR_SDP = MAXDELAY FROM TIMEGRP "TG_P | MAXDELAY| 3.244ns| 4.756ns| 0| 0
XDR" TO TIMEGRP "TG_SENSOR_DATA_PADS" | | | | |
8 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_ALL_FOSUM = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 3.682ns| 5.818ns| 0| 0
ALL_FFS" TO TIMEGRP "TG_FOSUM" TS | | | | |
_SCLK0 | | | | |
------------------------------------------------------------------------------------------------------
TS_ivact_ivact = MAXDELAY FROM TIMEGRP "T | SETUP | 3.842ns| 4.158ns| 0| 0
G_ivact" TO TIMEGRP "TG_ivact" 8 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_SP1_DOUBLECYC_IDATA = MAXDELAY FROM TI | SETUP | 5.078ns| 4.422ns| 0| 0
MEGRP "TNM_SP1_EN_IDATA" TO TIMEGRP | | | | |
"TNM_SP1_EN_IDATA" TS_DCLK | | | | |
------------------------------------------------------------------------------------------------------
TS_FOSUM_ALL = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 5.298ns| 4.202ns| 0| 0
FOSUM" TO TIMEGRP "TG_ALL_FFS" TS | | | | |
_SCLK0 | | | | |
------------------------------------------------------------------------------------------------------
TS_DOUBLECYC_IDATA0 = MAXDELAY FROM TIMEG | SETUP | 5.369ns| 4.131ns| 0| 0
RP "TNM_EN_IDATA0" TO TIMEGRP "TN | | | | |
M_EN_IDATA0" TS_SCLK0 | | | | |
------------------------------------------------------------------------------------------------------
TS_SP2_DOUBLECYC_IDATA = MAXDELAY FROM TI | SETUP | 5.413ns| 4.087ns| 0| 0
MEGRP "TNM_SP2_EN_IDATA" TO TIMEGRP | | | | |
"TNM_SP2_EN_IDATA" TS_DCLK | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x_2 = PERIOD TIMEGRP "i_sp0_ | N/A | N/A| N/A| N/A| N/A
dcm2x_2" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x180_2 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p0_dcm2x180_2" TS_DCLK / 2 PHASE | | | | |
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata_2 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp2_pre_pre_en_idata_2" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata90_2 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp2_pre_pre_en_idata90_2" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x_2 = PERIOD TIMEGRP "i_sp2_ | N/A | N/A| N/A| N/A| N/A
dcm2x_2" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x180_2 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p2_dcm2x180_2" TS_DCLK / 2 PHASE | | | | |
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata_2 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp1_pre_pre_en_idata_2" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata90_2 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp0_pre_pre_en_idata90_2" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata90_0 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp1_pre_pre_en_idata90_0" | | | | |
TS_DCLK PHASE 4.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata_2 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp0_pre_pre_en_idata_2" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk270_0 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_dcm_359_1_pre_clk270_0" TS | | | | |
_DCLK PHASE 7.125 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk0_0 = PERIOD TIMEGR | N/A | N/A| N/A| N/A| N/A
P "i_dcm_359_1_pre_clk0_0" TS_DCLK | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x180_0 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p1_dcm2x180_0" TS_DCLK / 2 PHASE 2.25 | | | | |
ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x_0 = PERIOD TIMEGRP "i_sp1_ | N/A | N/A| N/A| N/A| N/A
dcm2x_0" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata90_2 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp1_pre_pre_en_idata90_2" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x_2 = PERIOD TIMEGRP "i_sp1_ | N/A | N/A| N/A| N/A| N/A
dcm2x_2" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x180_2 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p1_dcm2x180_2" TS_DCLK / 2 PHASE | | | | |
2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata_3 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp2_pre_pre_en_idata_3" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata90_3 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp2_pre_pre_en_idata90_3" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x_3 = PERIOD TIMEGRP "i_sp2_ | N/A | N/A| N/A| N/A| N/A
dcm2x_3" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
PATH "TS_SP0_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 12.825ns| N/A| 0
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata_3 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp1_pre_pre_en_idata_3" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata90_3 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp1_pre_pre_en_idata90_3" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x_3 = PERIOD TIMEGRP "i_sp1_ | N/A | N/A| N/A| N/A| N/A
dcm2x_3" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
PATH "TS_SP0_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 3.177ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP0_SCLK0_GCLK_IDATA_path" TIG | SETUP | N/A| 3.969ns| N/A| 0
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata_3 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp0_pre_pre_en_idata_3" TS | | | | |
_DCLK PHASE 2.375 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata90_3 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp0_pre_pre_en_idata90_3" | | | | |
TS_DCLK PHASE 4.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x_3 = PERIOD TIMEGRP "i_sp0_ | N/A | N/A| N/A| N/A| N/A
dcm2x_3" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
PATH "TS_SP1_SCLK0_GCLK_IDATA_path" TIG | MAXDELAY| N/A| 4.644ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP1_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 3.344ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP1_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 11.474ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP2_SCLK0_GCLK_IDATA_path" TIG | MAXDELAY| N/A| 2.786ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP2_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 2.780ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_SP2_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 11.397ns| N/A| 0
------------------------------------------------------------------------------------------------------
TS_SCLK0 = PERIOD TIMEGRP "TNM_SCLK0" TS_ | N/A | N/A| N/A| N/A| N/A
DCLK HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_PX_CHDL = MAXDELAY FROM TIMEGRP "TNM_P | N/A | N/A| N/A| N/A| N/A
X" TO TIMEGRP "TG_CHDL" 8 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_SP0_DOUBLECYC_IDATA = MAXDELAY FROM TI | N/A | N/A| N/A| N/A| N/A
MEGRP "TNM_SP0_EN_IDATA" TO TIMEGRP | | | | |
"TNM_SP0_EN_IDATA" TS_DCLK | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata_1 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp0_pre_pre_en_idata_1" TS_SC | | | | |
PHASE 1.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata90_1 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp0_pre_pre_en_idata90_1" | | | | |
TS_SC PHASE 3 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x_1 = PERIOD TIMEGRP "i_sp0_ | N/A | N/A| N/A| N/A| N/A
dcm2x_1" TS_SC / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x180_1 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p0_dcm2x180_1" TS_SC / 2 PHASE 1.5 ns | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata_1 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp2_pre_pre_en_idata_1" TS_SC | | | | |
PHASE 1.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata90_1 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp2_pre_pre_en_idata90_1" | | | | |
TS_SC PHASE 3 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x_1 = PERIOD TIMEGRP "i_sp2_ | N/A | N/A| N/A| N/A| N/A
dcm2x_1" TS_SC / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x180_1 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p2_dcm2x180_1" TS_SC / 2 PHASE 1.5 ns | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata_1 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp1_pre_pre_en_idata_1" TS_SC | | | | |
PHASE 1.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata90_1 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp1_pre_pre_en_idata90_1" | | | | |
TS_SC PHASE 3 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x_1 = PERIOD TIMEGRP "i_sp1_ | N/A | N/A| N/A| N/A| N/A
dcm2x_1" TS_SC / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_dcm2x180_1 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p1_dcm2x180_1" TS_SC / 2 PHASE 1.5 ns | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk0 = PERIOD TIMEGRP | N/A | N/A| N/A| N/A| N/A
"i_dcm_359_1_pre_clk0" TS_DCLK HIGH | | | | |
50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_dcm_359_1_pre_clk270 = PERIOD TIMEGR | N/A | N/A| N/A| N/A| N/A
P "i_dcm_359_1_pre_clk270" TS_DCLK | | | | |
PHASE 6.75 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata_0 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp0_pre_pre_en_idata_0" TS | | | | |
_DCLK PHASE 2.25 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_pre_pre_en_idata90_0 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp0_pre_pre_en_idata90_0" | | | | |
TS_DCLK PHASE 4.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x_0 = PERIOD TIMEGRP "i_sp0_ | N/A | N/A| N/A| N/A| N/A
dcm2x_0" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp0_dcm2x180_0 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p0_dcm2x180_0" TS_DCLK / 2 PHASE 2.25 | | | | |
ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata_0 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp2_pre_pre_en_idata_0" TS | | | | |
_DCLK PHASE 2.25 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_pre_pre_en_idata90_0 = PERIOD TI | N/A | N/A| N/A| N/A| N/A
MEGRP "i_sp2_pre_pre_en_idata90_0" | | | | |
TS_DCLK PHASE 4.5 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x_0 = PERIOD TIMEGRP "i_sp2_ | N/A | N/A| N/A| N/A| N/A
dcm2x_0" TS_DCLK / 2 HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp2_dcm2x180_0 = PERIOD TIMEGRP "i_s | N/A | N/A| N/A| N/A| N/A
p2_dcm2x180_0" TS_DCLK / 2 PHASE 2.25 | | | | |
ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_i_sp1_pre_pre_en_idata_0 = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
GRP "i_sp1_pre_pre_en_idata_0" TS | | | | |
_DCLK PHASE 2.25 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_DCLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DCLK | 9.500ns| 8.827ns| 9.474ns| 0| 0| 2636| 52248|
| TS_SP0_DOUBLECYC_IDATA | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_SP1_DOUBLECYC_IDATA | 9.500ns| 4.422ns| N/A| 0| 0| 213| 0|
| TS_SP2_DOUBLECYC_IDATA | 9.500ns| 4.087ns| N/A| 0| 0| 213| 0|
| TS_SCLK0 | 9.500ns| N/A| 5.818ns| 0| 0| 0| 701|
| TS_DOUBLECYC_IDATA0 | 9.500ns| 4.131ns| N/A| 0| 0| 213| 0|
| TS_ALL_FOSUM | 9.500ns| 5.818ns| N/A| 0| 0| 222| 0|
| TS_FOSUM_ALL | 9.500ns| 4.202ns| N/A| 0| 0| 266| 0|
| TS_i_dcm_359_1_pre_clk0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_dcm_359_1_pre_clk270 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata90_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x180_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata90_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x180_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata90_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x180_0 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_dcm_359_1_pre_clk0_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_dcm_359_1_pre_clk270_0 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata90_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x180_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata90_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x180_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata90_2 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x180_2 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata90_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x_3 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x180_3 | 4.750ns| 4.666ns| N/A| 0| 0| 112| 0|
| TS_i_sp1_pre_pre_en_idata_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata90_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x_3 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x180_3 | 4.750ns| 4.590ns| N/A| 0| 0| 112| 0|
| TS_i_dcm_359_1_pre_clk0_1 | 9.500ns| 9.474ns| N/A| 0| 0| 50685| 0|
| TS_i_dcm_359_1_pre_clk270_1 | 9.500ns| 5.798ns| N/A| 0| 0| 70| 0|
| TS_i_sp0_pre_pre_en_idata_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata90_3 | 9.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x_3 | 4.750ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x180_3 | 4.750ns| 4.584ns| N/A| 0| 0| 142| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_SC
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SC | 8.500ns| 6.798ns| N/A| 0| 0| 36| 0|
| TS_i_sp0_pre_pre_en_idata_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_pre_pre_en_idata90_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp0_dcm2x180_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_pre_pre_en_idata90_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp2_dcm2x180_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_pre_pre_en_idata90_1 | 8.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
| TS_i_sp1_dcm2x180_1 | 4.250ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 54 secs
Total CPU time to PAR completion: 52 secs
Peak Memory Usage: 219 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 4
Number of info messages: 2
Writing design to file x359.ncd
PAR done!
x359.sav 0 → 100644
View file @ 1727b764
[timestart] 0
[size] 1298 774
[pos] 245 60
*-31.392126 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x359_tf.
[treeopen] x359_tf.i_x359.
@200
-Sensor 1
@28
x359_tf.i_x359.PX_DCLK1
x359_tf.i_x359.PX_ARO1
x359_tf.i_x359.PX_ARST1
x359_tf.i_x359.PX_MRST1
x359_tf.i_x359.PX_VACT1
x359_tf.i_x359.PX_HACT1
@22
x359_tf.i_x359.PXD1[11:0]
@200
-
-Memory
@28
x359_tf.i_x359.SDWE
x359_tf.i_x359.SDCAS
x359_tf.i_x359.SDRAS
@22
x359_tf.i_x359.SDD[15:0]
x359_tf.i_x359.sddi_r[31:0]
x359_tf.i_x359.sddo_p[31:0]
@200
-
-System Clock
@28
x359_tf.i_x359.sclk0
[pattern_trace] 1
[pattern_trace] 0
x359.syr 0 → 100644
View file @ 1727b764
This source diff could not be displayed because it is too large. You can view the blob instead.
x359.tf 0 → 100755
View file @ 1727b764
/*!***************************************************************************
*! FILE NAME : x359.tf
*! DESCRIPTION: testbench
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!
*! $Log: x359.tf,v $
*! Revision 1.3 2010/05/13 03:34:46 elphel
*! 10359 updates for composite frames
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:07:57 dzhimiev
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*! Revision 1.2 2008/04/24 17:45:55 dzhimiev
*! did't close the header comment
*!
*! Revision 1.1 2008/04/23 01:55:49 dzhimiev
*! 1. added x359 files to src lists
*! 2. x359 read/write DDR
*! 3. x359 3 channels mux directly to out
*! 4. x359 one channel through DDR and another directly frames switching at out
*!
*/
`timescale 1 ns / 1 ps
module x359_tf;
parameter DCLK_PER = 50; //20MHz
parameter I2C_PER = 1000;
parameter PIXELS_IN_LINE = 1296;
parameter LINES_IN_FRAME = 4;
// Inputs
reg SDNCLK_FB;
reg SDCLK_FB;
reg DCLK;
reg MRST;
reg ARO;
reg ARST;
wire PX_BPF1;
wire PX_HACT1;
wire PX_VACT1;
wire PX_BPF2;
wire PX_HACT2;
wire PX_VACT2;
wire PX_BPF3;
wire PX_HACT3;
wire PX_VACT3;
// Outputs
wire RUN;
wire SDCLKE;
wire SDCLK;
wire SDNCLK;
wire SDLDM;
wire SDUDM;
wire SDWE;
wire SDCAS;
wire SDRAS;
wire [14:0] SDA;
wire [9:0] PXD;
wire BPF;
wire HACT;
wire VACT;
wire PX_DCLK1;
wire PX_MRST1;
wire PX_ARO1;
wire PX_ARST1;
wire PX_DCLK2;
wire PX_MRST2;
wire PX_ARO2;
wire PX_ARST2;
wire PX_DCLK3;
wire PX_MRST3;
wire PX_ARO3;
wire PX_ARST3;
// Bidirs
wire [15:0] SDD;
wire UDQS;
wire LDQS;
wire SCL0;
wire SDA0;
wire CNVSYNC;
wire CNVCLK;
wire [11:0] PXD1;
wire PX_SCL1;
wire PX_SDA1;
wire SENSPGM1;
wire [11:0] PXD2;
wire PX_SCL2;
wire PX_SDA2;
wire SENSPGM2;
wire [11:0] PXD3;
wire PX_SCL3;
wire PX_SDA3;
wire SENSPGM3;
wire ALWAYS0;
// test registers/wires
reg I2C_CLK;
reg HOST_SDA;
reg HOST_SCL;
reg HOST_SDA_EN;
reg HOST_SCL_EN;
assign SDA0= HOST_SDA_EN ? HOST_SDA : 'bz;
assign SCL0= HOST_SCL_EN ? HOST_SCL : 'bz;
// param
//defparam i_x359.i_dcm_359_2.i_dcm2.PHASE_SHIFT=7;
// Instantiate the Unit Under Test (UUT)
x359 i_x359 (
.RUN(RUN),
.SDCLKE(SDCLKE),
.SDNCLK_FB(SDNCLK_FB),
.SDCLK(SDCLK),
.SDNCLK(SDNCLK),
.SDCLK_FB(SDCLK_FB),
.SDLDM(SDLDM),
.SDUDM(SDUDM),
.SDWE(SDWE),
.SDCAS(SDCAS),
.SDRAS(SDRAS),
.SDA(SDA),
.SDD(SDD),
.UDQS(UDQS),
.LDQS(LDQS),
.PXD(PXD),
.DCLK(DCLK),
.BPF(BPF),
.HACT(HACT),
.VACT(VACT),
.MRST(MRST),
.ARO(ARO),
.ARST(ARST),
.SCL0(SCL0),
.SDA0(SDA0),
.CNVSYNC(CNVSYNC),
.CNVCLK(CNVCLK),
.PXD1(PXD1),
//.PXD1({5'b0,PXD1[6:0]}),
.PX_DCLK1(PX_DCLK1),
.PX_BPF1(PX_BPF1),
.PX_HACT1(PX_HACT1),
.PX_VACT1(PX_VACT1),
.PX_MRST1(PX_MRST1),
.PX_ARO1(PX_ARO1),
.PX_ARST1(PX_ARST1),
.PX_SCL1(PX_SCL1),
.PX_SDA1(PX_SDA1),
.SENSPGM1(SENSPGM1),
.PXD2(PXD2),
//.PXD2({5'b0,PXD2[6:0]}),
.PX_DCLK2(PX_DCLK2),
.PX_BPF2(PX_BPF2),
.PX_HACT2(PX_HACT2),
.PX_VACT2(PX_VACT2),
.PX_MRST2(PX_MRST2),
.PX_ARO2(PX_ARO2),
.PX_ARST2(PX_ARST2),
.PX_SCL2(PX_SCL2),
.PX_SDA2(PX_SDA2),
.SENSPGM2(SENSPGM2),
.PXD3(PXD3),
//.PXD3(),
.PX_DCLK3(PX_DCLK3),
.PX_BPF3(PX_BPF3),
.PX_HACT3(PX_HACT3),
.PX_VACT3(PX_VACT3),
.PX_MRST3(PX_MRST3),
.PX_ARO3(PX_ARO3),
.PX_ARST3(PX_ARST3),
.PX_SCL3(PX_SCL3),
.PX_SDA3(PX_SDA3),
.SENSPGM3(SENSPGM3),
.ALWAYS0(ALWAYS0)
);
reg a;
reg [2:0] fib=0;
initial begin
fib=0; a=(fib[2] || & fib[1:0]); #100;
fib=1; a=(fib[2] || & fib[1:0]); #100;
fib=2; a=(fib[2] || & fib[1:0]); #100;
fib=3; a=(fib[2] || & fib[1:0]); #100;
fib=4; a=(fib[2] || & fib[1:0]); #100;
fib=5; a=(fib[2] || & fib[1:0]); #100;
fib=6; a=(fib[2] || & fib[1:0]); #100;
fib=7; a=(fib[2] || & fib[1:0]); #100;
end
// Instance of Micron MT48LC8M16LFFF8
// cheating - no such actual signal :-(
reg SDCKE;
initial begin
SDCKE=0;
#1000;
SDCKE=1;
end
wire SDCLK_D;
wire SDNCLK_D;
assign #(2) SDCLK_D=SDCLK;
assign #(2) SDNCLK_D=SDNCLK;
integer k=0;
integer s0=0;
integer s1=0;
reg [7:0] corr_status=0;
//`define sg5B;
ddr i_mt46v16m16fg (.Dq(SDD[15:0]),
.Dqs({UDQS,LDQS}),
.Addr(SDA[12:0]),
.Ba(SDA[14:13]),
.Clk(SDCLK_D),
.Clk_n(SDNCLK_D),
// .Cke(1'b1),
// .Cke(SDCKE),
.Cke(SDCLKE),
.Cs_n(1'b0),
.Ras_n(SDRAS),
.Cas_n(SDCAS),
.We_n(SDWE),
.Dm({SDUDM,SDLDM})
);
initial begin
// Initialize Inputs
SDNCLK_FB = 0;
SDCLK_FB = 0;
DCLK = 0;
MRST = 0;
ARO = 0;
ARST = 0;
//PX_BPF1 = 0;
//PX_HACT1 = 0;
//PX_VACT1 = 0;
//PX_BPF2 = 0;
//PX_HACT2 = 0;
//PX_VACT2 = 0;
//PX_BPF3 = 0;
//PX_HACT3 = 0;
//PX_VACT3 = 0;
// Wait 100 ns for global reset to finish
#100;
MRST = 1;
ARO = 1;
ARST = 1;
// Add stimulus here
end
always #(DCLK_PER/2) DCLK = ~DCLK;
always #(I2C_PER/2) I2C_CLK = ~I2C_CLK;
// parameter DCLK_PER = 50 //20MHz
// parameter I2C_PER = 1000;
initial begin
$dumpfile("x359_sim.lxt");
$dumpvars(0,x359_tf);
DCLK = 0;
I2C_CLK = 0;
// test registers/wires
I2C_CLK =0;
HOST_SDA=1;
HOST_SCL=1;
HOST_SDA_EN=0;
HOST_SCL_EN=0;
//#1000;
// global set/reset for simulation
glbl.GSR_int = 1'b1;
glbl.GTS_int = 1'b1;
#2000;
glbl.GSR_int = 1'b0;
#20;
glbl.GTS_int = 1'b0;
#50;
#10000;
i2c_start; i2c_send_2_bytes('hbaa0); i2c_send_4_bytes('h00410000); i2c_stop; #10000;
// direct frame sizes
i2c_start; i2c_send_2_bytes('h100a); i2c_send_2_bytes(PIXELS_IN_LINE); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h100b); i2c_send_2_bytes(LINES_IN_FRAME); i2c_stop; #10000;
// frequency rotate 90 for ddr correct work
i2c_start; i2c_send_2_bytes('h1002); i2c_send_2_bytes('h0004); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1009); i2c_send_2_bytes('h0003); i2c_stop; #10000; // rst
//i2c_start; i2c_send_2_bytes('h1009); i2c_send_2_bytes('h0002); i2c_stop; #10000; // disable output
i2c_start; i2c_send_2_bytes('h9001); i2c_send_2_bytes('h0002); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h9402); i2c_send_2_bytes('h0003); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1001); i2c_send_2_bytes('h0001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h9803); i2c_send_2_bytes('h0004); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h9c04); i2c_send_2_bytes('h0005); i2c_stop; #10000;
#10000;
i2c_start;
i2c_sendbyte ('h10);
i2c_sendbyte ('h02);
i2c_restart;
i2c_sendbyte ('h11);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (0);
i2c_stop;
#100000;
i2c_start;
i2c_sendbyte ('h90);
i2c_sendbyte ('h00);
i2c_restart;
i2c_sendbyte ('h00);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (0);
i2c_stop;
#100000;
i2c_start;
i2c_sendbyte ('h94);
i2c_sendbyte ('h00);
i2c_restart;
i2c_sendbyte ('h00);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (0);
i2c_stop;
// ch0_N frame dimensions
//i2c_start; i2c_send_2_bytes('h1037); i2c_send_4_bytes(LINES_IN_FRAME*32'h10000+PIXELS_IN_LINE); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1013); i2c_send_2_bytes(PIXELS_IN_LINE); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1014); i2c_send_2_bytes(LINES_IN_FRAME); i2c_stop; #10000;
// ch2_N frame dimensions
//i2c_start; i2c_send_2_bytes('h103c); i2c_send_4_bytes(LINES_IN_FRAME*32'h10000+PIXELS_IN_LINE); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1023); i2c_send_2_bytes(PIXELS_IN_LINE); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1024); i2c_send_2_bytes(LINES_IN_FRAME); i2c_stop; #10000;
// i2c_start; i2c_send_2_bytes('h103b); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
// set little delay for simulation
i2c_start; i2c_send_2_bytes('h1038); i2c_send_4_bytes('h00000000); i2c_stop; #10000;
// switch channel to 0x21
i2c_start; i2c_send_2_bytes('h1006); i2c_send_4_bytes('h00390039); i2c_stop; #10000;
// DDR initialization sequence
// init all the channels?
i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0001); i2c_stop;
i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h5555); i2c_stop;
#10000;
// DDR initialization sequence
//PRE : Addr[10] = 1, Bank = 11
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0001); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h7fff); i2c_stop;
//Extended mode register - Enable DLL
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0000); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h2002); i2c_stop;
//Load Mode Register - Burst Length - 8, CAS latency - 2.5
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0000); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h0163); i2c_stop;
//Refresh
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0000); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h8000); i2c_stop;
//Refresh
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0000); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h8000); i2c_stop;
//PRE : Addr[10] = 1, Bank = 11
i2c_start; i2c_send_2_bytes('h1051); i2c_send_2_bytes('h0001); i2c_stop;
i2c_start; i2c_send_2_bytes('h1041); i2c_send_2_bytes('h7fff); i2c_stop;
#10000;
// i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0001); i2c_stop;
// i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h0000); i2c_stop;
//
// i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0000); i2c_stop;
// i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h5555); i2c_stop;
// unappply init and enable all the 6 channels
i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0002); i2c_stop;
i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('haaaa); i2c_stop;
#10000;
////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
//// ddr test
//repeat(8) begin
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('h2211); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('h4433); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('h6655); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('h8877); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('haa99); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('hccbb); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('heedd); i2c_stop; #10000;
//i2c_start; i2c_send_2_bytes('h1070); i2c_send_2_bytes('h00ff); i2c_stop; #10000;
//end
//
//i2c_start; i2c_send_2_bytes('h1063); i2c_send_2_bytes('h0001); i2c_stop; #10000; // write page to SDRAM
//
//i2c_start; i2c_send_2_bytes('h1064); i2c_send_2_bytes('h0001); i2c_stop; #10000; // read page from SDRAM
//
//repeat(10) begin
//i2c_start;
//i2c_sendbyte ('h10);
//i2c_sendbyte ('h70);
//i2c_restart;
//i2c_sendbyte ('h11);
//i2c_readbyte (1);
//i2c_readbyte (0);
//i2c_stop;
//#10000;
//
//i2c_start;
//i2c_sendbyte ('h10);
//i2c_sendbyte ('h10);
//i2c_restart;
//i2c_sendbyte ('h11);
//i2c_readbyte (1);
//i2c_readbyte (0);
//i2c_stop;
//#10000;
//
//end
//#10000;
//
// i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0001); i2c_stop;
// i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h5555); i2c_stop;
//
// i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0002); i2c_stop;
// i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h0a00); i2c_stop;
//
//#100000;
//
//$finish;
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
i2c_start; i2c_send_2_bytes('h1052); i2c_send_2_bytes('h0007); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1042); i2c_send_2_bytes('h000f); i2c_stop; #10000;
//// i2c_start; i2c_send_2_bytes('h104c); i2c_send_4_bytes('h00010107); i2c_stop; #10000;
//// i2c_start; i2c_send_2_bytes('h1054); i2c_send_4_bytes('h0019100c); i2c_stop; #10000;
//// i2c_start; i2c_send_2_bytes('h104d); i2c_send_4_bytes('h00010107); i2c_stop; #10000;
//// i2c_start; i2c_send_2_bytes('h1055); i2c_send_4_bytes('h0019100c); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h105c); i2c_send_2_bytes('h000f); i2c_stop; #10000; //was 'h001f0107
i2c_start; i2c_send_2_bytes('h104c); i2c_send_2_bytes('h020f); i2c_stop; #10000; //was 'h001f0107
i2c_start; i2c_send_2_bytes('h105e); i2c_send_2_bytes('h1fff); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h104e); i2c_send_2_bytes('h10ff); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h105d); i2c_send_2_bytes('h000f); i2c_stop; #10000; //was 'h001f0107
i2c_start; i2c_send_2_bytes('h104d); i2c_send_2_bytes('h020f); i2c_stop; #10000; //was 'h001f0107
i2c_start; i2c_send_2_bytes('h105f); i2c_send_2_bytes('h1fff); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h104f); i2c_send_2_bytes('h10ff); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1053); i2c_send_2_bytes('h1c00); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1043); i2c_send_2_bytes('h0c21); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('h5555); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1054); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1044); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1055); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1045); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1056); i2c_send_2_bytes('h0001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1046); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1057); i2c_send_2_bytes('h0001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1047); i2c_send_2_bytes('h0000); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1050); i2c_send_2_bytes('h0002); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1040); i2c_send_2_bytes('haaaa); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1009); i2c_send_2_bytes('h0003); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1009); i2c_send_2_bytes('h0002); i2c_stop; #10000;
// switch to alternation mode with buffering
//i2c_start; i2c_send_2_bytes('h1035); i2c_send_4_bytes('h00000007); i2c_stop; #100000;
i2c_start; i2c_send_2_bytes('h1015); i2c_send_2_bytes('h0100); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1016); i2c_send_2_bytes('h0001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1025); i2c_send_2_bytes('h0080); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1026); i2c_send_2_bytes('h0001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1009); i2c_send_2_bytes('h0004); i2c_stop; #10000;
//frame enable
//i2c_start; i2c_send_2_bytes('h1005); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
#8000000;
$finish;
// test!!!
// i2c_start; i2c_send_2_bytes('h1047); i2c_send_4_bytes('h00000000); i2c_stop; #10000;
// i2c_start; i2c_send_2_bytes('h1047); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
i2c_start; i2c_send_2_bytes('h1003); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
// ddr shit
repeat(1) begin
i2c_start; i2c_send_2_bytes('h1002); i2c_send_4_bytes('h00002222); i2c_stop; #10000;
end
i2c_start; i2c_send_2_bytes('h1003); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
// now read what was written from channel 0
i2c_start; i2c_send_2_bytes('h1004); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
// now read what was written from channel 0
i2c_start; i2c_send_2_bytes('h1004); i2c_send_4_bytes('h00000001); i2c_stop; #10000;
i2c_start;
i2c_sendbyte ('h10);
i2c_sendbyte ('h02);
i2c_restart;
i2c_sendbyte ('h11);
repeat(14) begin
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
end
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (0);
i2c_stop;
#10000;
i2c_start;
i2c_sendbyte ('h10);
i2c_sendbyte ('h02);
i2c_restart;
i2c_sendbyte ('h11);
repeat(14) begin
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
end
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (1);
i2c_readbyte (0);
i2c_stop;
#10000;
$finish;
end
reg PX_MRST1_D=0;
reg PX_ARST1_D=0;
initial begin
#100000;
PX_MRST1_D = PX_MRST1;
PX_ARST1_D = PX_ARST1;
end
sensor12bits #(.ncols(PIXELS_IN_LINE),.nrows(LINES_IN_FRAME),.t_afterHACT(100),.nVLO(7000))
i_sensor12bits1(.MCLK(PX_DCLK1), // Master clock
//.MRST(PX_MRST1_D), // Master Reset - active low
.MRST(PX_MRST1), // Master Reset - active low
.ARO (PX_ARO1), // Array read Out.
//.ARST(PX_ARST1_D), // Array Reset. Active low
.ARST(PX_ARST1), // Array Reset. Active low
.OE (1'b0), // output enable active low
.SCL (PX_SCL1), // I2C clock
.SDA (PX_SDA1), // I2C data
.OFST(1'b1), // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
.D (PXD1[11:0]),// [9:0] data output
.DCLK(), // Data output clock
.BPF (PX_BPF1), // Black Pixel Flag
.HACT(PX_HACT1), // Horizontal Active
.VACT(PX_VACT1) // Vertical Active
);
sensor12bits #(.ncols(PIXELS_IN_LINE),.nrows(LINES_IN_FRAME),.t_afterHACT(100),.nVLO(7000))
i_sensor12bits2(.MCLK(PX_DCLK2), // Master clock
.MRST(PX_MRST2), // Master Reset - active low
.ARO (PX_ARO2), // Array read Out.
.ARST(PX_ARST2), // Array Reset. Active low
.OE (1'b0), // output enable active low
.SCL (PX_SCL2), // I2C clock
.SDA (PX_SDA2), // I2C data
.OFST(1'b1), // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
.D (PXD2[11:0]),// [9:0] data output
.DCLK(), // Data output clock
.BPF (PX_BPF2), // Black Pixel Flag
.HACT(PX_HACT2), // Horizontal Active
.VACT(PX_VACT2) // Vertical Active
);
sensor12bits #(.ncols(PIXELS_IN_LINE),.nrows(LINES_IN_FRAME),.t_afterHACT(100),.nVLO(7000))
i_sensor12bits3(.MCLK(PX_DCLK3), // Master clock
.MRST(PX_MRST3), // Master Reset - active low
.ARO (PX_ARO3), // Array read Out.
.ARST(PX_ARST3), // Array Reset. Active low
.OE (1'b0), // output enable active low
.SCL (PX_SCL3), // I2C clock
.SDA (PX_SDA3), // I2C data
.OFST(1'b1), // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
.D (PXD3[11:0]),// [9:0] data output
.DCLK(), // Data output clock
.BPF (PX_BPF3), // Black Pixel Flag
.HACT(PX_HACT3), // Horizontal Active
.VACT(PX_VACT3) // Vertical Active
);
parameter I2CDLY = 10;
task i2c_start; // SCL is supposed to be 1, SDA - released
begin
$display ("i2c START at %t", $time);
HOST_SDA=1;
HOST_SCL=1;
HOST_SDA_EN=0;
HOST_SCL_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SDA_EN=1;
HOST_SDA=0;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
endtask
task i2c_stop; // SCL is supposed to be 0, SDA - any
begin
$display ("i2c STOP at %t", $time);
HOST_SCL=0;
HOST_SCL_EN=1;
wait (~I2C_CLK);wait (I2C_CLK); // wait for bus turnover (it was likely reading ACKN)
HOST_SDA=0;
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SDA=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SDA_EN=0;
end
endtask
task i2c_restart; // SCL is supposed to be 0, SDA - any
begin
$display ("i2c RESTART at %t", $time);
HOST_SCL=0;
HOST_SCL_EN=1;
wait (~I2C_CLK);wait (I2C_CLK); // wait for bus turnover (it was likely reading ACKN)
HOST_SDA=1;
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=1;
HOST_SDA_EN=0;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SDA=0;
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
endtask
task i2c_sendbyte; // SCL is supposed to be 0, SDA - any
input [7:0] b;
reg ackn;
integer i;
begin
$display ("i2c send (%x) at %t", b,$time);
HOST_SCL=0;
HOST_SCL_EN=1;
wait (~I2C_CLK);wait (I2C_CLK); // wait for bus turnover (it was reading ACKN)
for (i=7;i>=0;i=i-1) begin
// # (I2CDLY);
HOST_SDA=b[i];
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=1;
if (HOST_SDA) begin
HOST_SDA_EN=0;
end
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
HOST_SDA_EN=0; // float for acknowledge
wait (~I2C_CLK);wait (I2C_CLK);
ackn=SDA0;
#1;
$display ("i2c acknowledge (%x)", ackn);
HOST_SCL=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
endtask
task i2c_readbyte; // SCL is supposed to be 0, SDA - any (more)
input more;
reg [7:0] d;
integer i;
begin
$display ("i2c read (more=%x) at %t", more, $time);
HOST_SCL=0;
HOST_SCL_EN=1;
HOST_SDA_EN=0;
for (i=7;i>=0;i=i-1) begin
wait (~I2C_CLK);wait (I2C_CLK);
d[i]=SDA0;
#1;
HOST_SCL=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
// # (I2CDLY);
wait (~I2C_CLK);wait (I2C_CLK); // wait for bus turnover (it was reading)
HOST_SDA=~more;
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=1;
if (HOST_SDA) begin
HOST_SDA_EN=0;
end
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
$display ("i2c read returned %x", d);
end
endtask
task i2c_readbyte2; // SCL is supposed to be 0, SDA - any (more)
input more;
output [7:0] d;
reg [7:0] d;
integer i;
begin
$display ("i2c read (more=%x) at %t", more, $time);
HOST_SCL=0;
HOST_SCL_EN=1;
HOST_SDA_EN=0;
for (i=7;i>=0;i=i-1) begin
wait (~I2C_CLK);wait (I2C_CLK);
d[i]=SDA0;
#1;
HOST_SCL=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
end
// # (I2CDLY);
wait (~I2C_CLK);wait (I2C_CLK); // wait for bus turnover (it was reading)
HOST_SDA=~more;
HOST_SDA_EN=1;
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=1;
if (HOST_SDA) begin
HOST_SDA_EN=0;
end
wait (~I2C_CLK);wait (I2C_CLK);
HOST_SCL=0;
$display ("i2c read returned %x", d);
end
endtask
task i2c_send_4_bytes;
input [31:0] di;
begin
i2c_sendbyte(di[31:24]);
i2c_sendbyte(di[23:16]);
i2c_sendbyte(di[15:8]);
i2c_sendbyte(di[7:0]);
end
endtask
task i2c_send_2_bytes;
input [15:0] di;
begin
i2c_sendbyte(di[15:8]);
i2c_sendbyte(di[7:0]);
end
endtask
endmodule
x359.ucf 0 → 100644
View file @ 1727b764
NET "RUN" LOC = "C2" | IOSTANDARD = "LVCMOS25";
NET "SDLDM" LOC = "M8" | IOSTANDARD = "SSTL2_I";
NET "SDUDM" LOC = "T8" | IOSTANDARD = "SSTL2_I" ;
NET "SDWE" LOC = "M7" | IOSTANDARD = "SSTL2_I" ;
NET "SDCAS" LOC = "N7" | IOSTANDARD = "SSTL2_I" ;
NET "SDRAS" LOC = "M6" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<0>" LOC = "P1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<1>" LOC = "K3" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<2>" LOC = "M1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<3>" LOC = "K2" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<4>" LOC = "T4" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<5>" LOC = "M4" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<6>" LOC = "T5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<7>" LOC = "P5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<8>" LOC = "N5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<9>" LOC = "R6" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<10>" LOC = "N1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<11>" LOC = "P6" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<12>" LOC = "P7" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<13>" LOC = "P2" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<14>" LOC = "L4" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<0>" LOC = "R14" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<1>" LOC = "T12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<2>" LOC = "N12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<3>" LOC = "N10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<4>" LOC = "R11" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<5>" LOC = "N9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<6>" LOC = "M9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<7>" LOC = "L8" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<8>" LOC = "P9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<9>" LOC = "P10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<10>" LOC = "M10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<11>" LOC = "P11" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<12>" LOC = "P12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<13>" LOC = "R13" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<14>" LOC = "T13" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<15>" LOC = "P14" | IOSTANDARD = "SSTL2_I" ;
NET "UDQS" LOC = "P8" | IOSTANDARD = "SSTL2_I" ;
NET "LDQS" LOC = "N8" | IOSTANDARD = "SSTL2_I" ;
NET "PXD<0>" LOC = "G3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<1>" LOC = "H5" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<2>" LOC = "G2" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<3>" LOC = "H4" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<4>" LOC = "J3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<5>" LOC = "J2" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<6>" LOC = "J4" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<7>" LOC = "J1" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<8>" LOC = "K1" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "PXD<9>" LOC = "L3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "DCLK" LOC = "E4" | IOSTANDARD = "LVCMOS25" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "BPF" LOC = "F4" | IOSTANDARD = "LVCMOS25";
NET "HACT" LOC = "E3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "VACT" LOC = "G4" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "MRST" LOC = "K5" | IOSTANDARD = "LVCMOS25";
NET "ARO" LOC = "N2" | IOSTANDARD = "LVCMOS25";
NET "ARST" LOC = "L5" | IOSTANDARD = "LVCMOS25";
NET "SCL0" LOC = "H6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "SDA0" LOC = "J5" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "CNVSYNC" LOC = "B1" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
NET "CNVCLK" LOC = "B2" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4;
#----------
NET "PXD1<0>" LOC = "R16" | IOSTANDARD = "LVCMOS25";
NET "PXD1<1>" LOC = "R15" | IOSTANDARD = "LVCMOS25";
NET "PXD1<2>" LOC = "F13" | IOSTANDARD = "LVCMOS25";
NET "PXD1<3>" LOC = "F12" | IOSTANDARD = "LVCMOS25";
NET "PXD1<4>" LOC = "G13" | IOSTANDARD = "LVCMOS25";
NET "PXD1<5>" LOC = "H12" | IOSTANDARD = "LVCMOS25";
NET "PXD1<6>" LOC = "H11" | IOSTANDARD = "LVCMOS25";
NET "PXD1<7>" LOC = "J14" | IOSTANDARD = "LVCMOS25";
NET "PXD1<8>" LOC = "J13" | IOSTANDARD = "LVCMOS25";
NET "PXD1<9>" LOC = "K14" | IOSTANDARD = "LVCMOS25";
NET "PXD1<10>" LOC = "K12" | IOSTANDARD = "LVCMOS25";
NET "PXD1<11>" LOC = "K13" | IOSTANDARD = "LVCMOS25";
NET "PX_DCLK1" LOC = "D14" | IOSTANDARD = "LVCMOS25";
NET "PX_BPF1" LOC = "E11" | IOSTANDARD = "LVCMOS25";
NET "PX_HACT1" LOC = "D15" | IOSTANDARD = "LVCMOS25";
NET "PX_VACT1" LOC = "E13" | IOSTANDARD = "LVCMOS25";
NET "PX_MRST1" LOC = "N15" | IOSTANDARD = "LVCMOS25";
NET "PX_ARO1" LOC = "P15" | IOSTANDARD = "LVCMOS25";
NET "PX_ARST1" LOC = "N14" | IOSTANDARD = "LVCMOS25";
NET "PX_SCL1" LOC = "L13" | IOSTANDARD = "LVCMOS25";
NET "PX_SDA1" LOC = "L12" | IOSTANDARD = "LVCMOS25";
NET "SENSPGM1" LOC = "P16" | IOSTANDARD = "LVCMOS25";
#----------
NET "PXD2<0>" LOC = "M16" | IOSTANDARD = "LVCMOS25";
NET "PXD2<1>" LOC = "N16" | IOSTANDARD = "LVCMOS25";
NET "PXD2<2>" LOC = "B14" | IOSTANDARD = "LVCMOS25";
NET "PXD2<3>" LOC = "C16" | IOSTANDARD = "LVCMOS25";
NET "PXD2<4>" LOC = "C15" | IOSTANDARD = "LVCMOS25";
NET "PXD2<5>" LOC = "E16" | IOSTANDARD = "LVCMOS25";
NET "PXD2<6>" LOC = "F15" | IOSTANDARD = "LVCMOS25";
NET "PXD2<7>" LOC = "F14" | IOSTANDARD = "LVCMOS25";
NET "PXD2<8>" LOC = "G16" | IOSTANDARD = "LVCMOS25";
NET "PXD2<9>" LOC = "G15" | IOSTANDARD = "LVCMOS25";
NET "PXD2<10>" LOC = "G14" | IOSTANDARD = "LVCMOS25";
NET "PXD2<11>" LOC = "H15" | IOSTANDARD = "LVCMOS25";
NET "PX_DCLK2" LOC = "A14" | IOSTANDARD = "LVCMOS25";
NET "PX_BPF2" LOC = "A12" | IOSTANDARD = "LVCMOS25";
NET "PX_HACT2" LOC = "A13" | IOSTANDARD = "LVCMOS25";
NET "PX_VACT2" LOC = "B13" | IOSTANDARD = "LVCMOS25";
NET "PX_MRST2" LOC = "K16" | IOSTANDARD = "LVCMOS25";
NET "PX_ARO2" LOC = "L15" | IOSTANDARD = "LVCMOS25";
NET "PX_ARST2" LOC = "K15" | IOSTANDARD = "LVCMOS25";
NET "PX_SCL2" LOC = "H14" | IOSTANDARD = "LVCMOS25";
NET "PX_SDA2" LOC = "J16" | IOSTANDARD = "LVCMOS25";
NET "SENSPGM2" LOC = "L14" | IOSTANDARD = "LVCMOS25";
#----------
NET "PXD3<0>" LOC = "E10" | IOSTANDARD = "LVCMOS25";
NET "PXD3<1>" LOC = "F9" | IOSTANDARD = "LVCMOS25";
NET "PXD3<2>" LOC = "D7" | IOSTANDARD = "LVCMOS25";
NET "PXD3<3>" LOC = "C7" | IOSTANDARD = "LVCMOS25";
NET "PXD3<4>" LOC = "A7" | IOSTANDARD = "LVCMOS25";
NET "PXD3<5>" LOC = "B7" | IOSTANDARD = "LVCMOS25";
NET "PXD3<6>" LOC = "E8" | IOSTANDARD = "LVCMOS25";
NET "PXD3<7>" LOC = "C8" | IOSTANDARD = "LVCMOS25";
NET "PXD3<8>" LOC = "D8" | IOSTANDARD = "LVCMOS25";
NET "PXD3<9>" LOC = "A9" | IOSTANDARD = "LVCMOS25";
NET "PXD3<10>" LOC = "D9" | IOSTANDARD = "LVCMOS25";
NET "PXD3<11>" LOC = "E9" | IOSTANDARD = "LVCMOS25";
NET "PX_DCLK3" LOC = "A5" | IOSTANDARD = "LVCMOS25";
NET "PX_BPF3" LOC = "A4" | IOSTANDARD = "LVCMOS25";
NET "PX_HACT3" LOC = "C6" | IOSTANDARD = "LVCMOS25";
NET "PX_VACT3" LOC = "B6" | IOSTANDARD = "LVCMOS25";
NET "PX_MRST3" LOC = "C11" | IOSTANDARD = "LVCMOS25";
NET "PX_ARO3" LOC = "D10" | IOSTANDARD = "LVCMOS25";
NET "PX_ARST3" LOC = "B11" | IOSTANDARD = "LVCMOS25";
NET "PX_SCL3" LOC = "A10" | IOSTANDARD = "LVCMOS25";
NET "PX_SDA3" LOC = "B10" | IOSTANDARD = "LVCMOS25";
NET "SENSPGM3" LOC = "F8" | IOSTANDARD = "LVCMOS25";
#----------
NET "AUXSCL" LOC = "C4" | IOSTANDARD = "LVCMOS25";
NET "AUXSDA" LOC = "B4" | IOSTANDARD = "LVCMOS25";
NET "CLK2" LOC = "C9";
NET "CLK1" LOC = "B8";
NET "CLK0" LOC = "A8" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "SDCLK" LOC = "R2" | IOSTANDARD = DIFF_SSTL2_I;
NET "SDCLK_FB" LOC = "R3" | IOSTANDARD = DIFF_SSTL2_I;
NET "SDNCLK" LOC = "R1" | IOSTANDARD = DIFF_SSTL2_I;
NET "SDNCLK_FB" LOC = "T3" | IOSTANDARD = DIFF_SSTL2_I;
NET "SDCLKE" LOC = "N6" | IOSTANDARD = "SSTL2_I";
NET "sclk0" TNM_NET = "TNM_SCLK0";
NET "pclk" TNM_NET = "TNM_PCLK";
NET "DCLK" TNM_NET = "TNM_DCLK";
#NET "*gclk_hact" TNM_NET = "GCLK_HACT";
#NET "*gclk_data" TNM_NET = "GCLK_DATA";
TIMESPEC "TS_DCLK" = PERIOD "TNM_DCLK" 9.5 ns HIGH 50 %;
NET "i2c_rdat_*" TIG;
NET "sp0_clk" TNM_NET = "TNM_SP0_GCLK_IDATA";
NET "i_sp0/en_idata" TNM_NET = "TNM_SP0_EN_IDATA";
TIMESPEC "TS_SP0_SCLK0_GCLK_IDATA" = FROM "TNM_SCLK0" TO "TNM_SP0_GCLK_IDATA" TIG;
TIMESPEC "TS_SP0_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP0_GCLK_IDATA" TIG;
TIMESPEC "TS_SP0_GCLK_IDATA_PCLK" = FROM "TNM_SP0_GCLK_IDATA" TO "TNM_SCLK0" TIG;
TIMESPEC "TS_SP0_DOUBLECYC_IDATA" = FROM "TNM_SP0_EN_IDATA" TO "TNM_SP0_EN_IDATA" "TS_DCLK";
#uncomment for older ISE WebPack (e.g., 10.3)
NET "i_sp1/clkout" TNM_NET = "TNM_SP1_GCLK_IDATA";
#####NET "i_sp1/gclk_idata" TNM_NET = "TNM_SP1_GCLK_IDATA";
NET "i_sp1/en_idata" TNM_NET = "TNM_SP1_EN_IDATA";
TIMESPEC "TS_SP1_SCLK0_GCLK_IDATA" = FROM "TNM_SCLK0" TO "TNM_SP1_GCLK_IDATA" TIG;
TIMESPEC "TS_SP1_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP1_GCLK_IDATA" TIG;
TIMESPEC "TS_SP1_GCLK_IDATA_PCLK" = FROM "TNM_SP1_GCLK_IDATA" TO "TNM_SCLK0" TIG;
TIMESPEC "TS_SP1_DOUBLECYC_IDATA" = FROM "TNM_SP1_EN_IDATA" TO "TNM_SP1_EN_IDATA" "TS_DCLK";
#uncomment for older ISE WebPack (e.g., 10.3)
NET "i_sp2/clkout" TNM_NET = "TNM_SP2_GCLK_IDATA";
#####NET "i_sp2/gclk_idata" TNM_NET = "TNM_SP2_GCLK_IDATA";
NET "i_sp2/en_idata" TNM_NET = "TNM_SP2_EN_IDATA";
TIMESPEC "TS_SP2_SCLK0_GCLK_IDATA" = FROM "TNM_SCLK0" TO "TNM_SP2_GCLK_IDATA" TIG;
TIMESPEC "TS_SP2_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP2_GCLK_IDATA" TIG;
TIMESPEC "TS_SP2_GCLK_IDATA_PCLK" = FROM "TNM_SP2_GCLK_IDATA" TO "TNM_SCLK0" TIG;
TIMESPEC "TS_SP2_DOUBLECYC_IDATA" = FROM "TNM_SP2_EN_IDATA" TO "TNM_SP2_EN_IDATA" "TS_DCLK";
TIMESPEC "TS_SCLK0" = PERIOD "TNM_SCLK0" "TS_DCLK";
NET "sensor_clock" TNM = "SENSOR_CLK";
TIMESPEC "TS_SC" = PERIOD "SENSOR_CLK" 8.5 ns HIGH 50%;
# next 3 are probably not needed now when we use ODDR2. Problem before was that GCLK could not be
# routed directly to OBUF and sesnor_clock used side DCM and local eires - even to DCM inputs.
# Using ODDR2 on teh output (constant values on D-inputs) allow GCLK to be routed to the IOB
INST "BUFGMUX_inst" LOC = "BUFGMUX_X2Y10"; #Somewhere on top
INST "BUFGMUX_inst" TPSYNC="TP_SENSOR_CLOCK_SOURCE";
TIMESPEC "TS_SENSOR_CLOCK_TO_PADS_DCM" = FROM "TP_SENSOR_CLOCK_SOURCE" TO "SENSOR_CLK" 5ns;
# new above
#TIMESPEC "TS_PCLK" = PERIOD "pclk" 9.0 ns HIGH 50 %;
#TIMESPEC "TS_CLK0" = PERIOD "CLK0" 6.0 ns HIGH 50 %;
#TIMESPEC "TS_CLK2" = PERIOD "CLK2" "TS_CLK0";
#TIMESPEC "TS_CLK1" = PERIOD "CLK1" "TS_CLK0";
NET "i_sp0/en_idata" TNM_NET = "TNM_EN_IDATA0";
NET "i_sp1/en_idata" TNM_NET = "TNM_EN_IDATA1";
NET "i_sp2/en_idata" TNM_NET = "TNM_EN_IDATA2";
TIMESPEC "TS_DOUBLECYC_IDATA0" = FROM "TNM_EN_IDATA0" TO "TNM_EN_IDATA0" "TS_SCLK0";
TIMESPEC "TS_DOUBLECYC_IDATA1" = FROM "TNM_EN_IDATA1" TO "TNM_EN_IDATA1" "TS_SCLK1";
TIMESPEC "TS_DOUBLECYC_IDATA2" = FROM "TNM_EN_IDATA2" TO "TNM_EN_IDATA2" "TS_SCLK2";
TIMEGRP "ALLPADS"= pads("*");
NET "SDA0*" TNM_NET = "SDA0";
# timing constraints for registers
TIMEGRP "TG_CHMUX"= ffs("chn_mux*");
TIMEGRP "TG_CHDL"= ffs("*_dl*");
NET "PXD*" TNM = TNM_PXD;
NET "PX_*" TNM = TNM_PX;
TIMEGRP "TG_DIR"= ffs("*_direct*");
#TIMESPEC TS_PXD_CHDL = FROM TNM_PXD TO TG_CHDL 8 ns;
TIMESPEC TS_PX_CHDL = FROM TNM_PX TO TG_CHDL 8 ns;
TIMESPEC TS_CHMUX_DIR = FROM TG_CHMUX TO TG_DIR 6.700 ns;
TIMESPEC TS_CHDL_DIR = FROM TG_CHDL TO TG_DIR 6.700 ns;
TIMEGRP "TG_ch0"= ffs("i_mcontr/i_channel0/*");
TIMEGRP "TG_enSDRAM"= ffs("i_mcontr/*");
TIMEGRP "TG_SDDO_REG"= ffs("i_mcontr/sddo*");
TIMEGRP "TG_PRE2_REG"= ffs("i_mcontr/pre2*");
NET "da_*" TNM= TNM_DAs;
TIMEGRP "TG_I2C_REG_ADDR"= ffs("i2c_reg_addr*");
TIMEGRP "TG_I2C_CNT"= ffs("i2c_cnt*");
TIMESPEC TS_I2C_RA_DAs = FROM TG_I2C_REG_ADDR TO TNM_DAs 9 ns;
TIMESPEC TS_I2C_CT_DAs = FROM TG_I2C_CNT TO TNM_DAs 9 ns;
# timing constraints for channel counters
TIMEGRP "TG_PRE4ACT1" = ffs("*pre4act1");
TIMEGRP "TG_PRE4ACT2" = ffs("*pre4act2");
TIMEGRP "TG_PRE3SDA" = ffs("*pre3sda*");
# new freedom
TIMEGRP "TG_ALL_SYNC"= FFS RAMS;
#new cheat
TIMEGRP "TG_ihact" = ffs("*ihact*");
TIMESPEC TS_ihact_ihact = FROM TG_ihact TO TG_ihact 8 ns;
TIMEGRP "TG_ivact" = ffs("*ivact*");
TIMESPEC TS_ivact_ivact = FROM TG_ivact TO TG_ivact 8 ns;
# sensors data constraints
TIMEGRP "TG_ALL_FFS" = ffs("*");
NET "*" TNM= TNM_ALL_NETS;
NET "PXD*" TNM= TNM_PXD_NETS;
TIMEGRP "TG_SENSOR_DATA_PADS"= pads("PXD*");
TIMEGRP "TG_SP_IDI" = ffs("*idi*");
#TIMESPEC TS_SDP_SP_IDI = FROM TG_SENSOR_DATA_PADS TO TG_ALL_FFS 6 ns;
#TIMESPEC TS_SDP_ALLNETS_IDI = FROM TNM_ALL_NETS TO TG_SP_IDI 6 ns;
#TIMEGRP "TG_SP0_IDI" = ffs("i_sp0/idi*");
#TIMEGRP "TG_SP1_IDI" = ffs("i_sp1/idi*");
#TIMEGRP "TG_SP2_IDI" = ffs("i_sp2/idi*");
#
#TIMESPEC TS_PXDNETS_SP0_IDI = FROM TNM_PXD_NETS TO TG_SP0_IDI 6 ns;
#TIMESPEC TS_PXDNETS_SP1_IDI = FROM TNM_PXD_NETS TO TG_SP1_IDI 6 ns;
#TIMESPEC TS_PXDNETS_SP2_IDI = FROM TNM_PXD_NETS TO TG_SP2_IDI 6 ns;
#TIMEGRP "TG_HACT_PADS"= pads("HACT*");
#TIMEGRP "TG_SP_HACT" = ffs("*ihact*");
#
#NET "PX_HACT*" TNM= TNM_HACT_NET;
#
#TIMEGRP "TG_SP0_HACT" = ffs("i_sp0/ihact*");
#TIMEGRP "TG_SP1_HACT" = ffs("i_sp1/ihact*");
#TIMEGRP "TG_SP2_HACT" = ffs("i_sp2/ihact*");
#
#TIMESPEC TS_HACTNET_SP0_HACT = FROM TNM_HACT_NET TO TG_SP0_HACT 6 ns;
#TIMESPEC TS_HACTNET_SP1_HACT = FROM TNM_HACT_NET TO TG_SP1_HACT 6 ns;
#TIMESPEC TS_HACTNET_SP2_HACT = FROM TNM_HACT_NET TO TG_SP2_HACT 6 ns;
TIMEGRP "TG_PXDR" = ffs("pxdr*");
TIMESPEC TS_PXDR_SDP = FROM TG_PXDR TO TG_SENSOR_DATA_PADS 8 ns;
# resync blocks constraints
NET "pclk" TNM_NET = "TNM_PCLK";
#NET "i_sp0/gclk_idata" TNM_NET = "TNM_SP0_GCLK_IDATA";
#NET "i_sp0/en_idata" TNM_NET = "TNM_SP0_EN_IDATA";
#
#TIMESPEC "TS_SP0_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP0_GCLK_IDATA" TIG;
#TIMESPEC "TS_SP0_GCLK_IDATA_PCLK" = FROM "TNM_SP0_GCLK_IDATA" TO "TNM_PCLK" TIG;
#TIMESPEC "TS_SP0_DOUBLECYC_IDATA" = FROM "TNM_SP0_EN_IDATA" TO "TNM_SP0_EN_IDATA" "TS_SCLK0";
#NET "i_sp1/gclk_idata" TNM_NET = "TNM_SP1_GCLK_IDATA";
#NET "i_sp1/en_idata" TNM_NET = "TNM_SP1_EN_IDATA";
#
#TIMESPEC "TS_SP1_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP1_GCLK_IDATA" TIG;
#TIMESPEC "TS_SP1_GCLK_IDATA_PCLK" = FROM "TNM_SP1_GCLK_IDATA" TO "TNM_PCLK" TIG;
#TIMESPEC "TS_SP1_DOUBLECYC_IDATA" = FROM "TNM_SP1_EN_IDATA" TO "TNM_SP1_EN_IDATA" "TS_SCLK0";
#NET "i_sp2/gclk_idata" TNM_NET = "TNM_SP2_GCLK_IDATA";
#NET "i_sp2/en_idata" TNM_NET = "TNM_SP2_EN_IDATA";
#TIMESPEC "TS_SP2_PCLK_GCLK_IDATA" = FROM "TNM_PCLK" TO "TNM_SP2_GCLK_IDATA" TIG;
#TIMESPEC "TS_SP2_GCLK_IDATA_PCLK" = FROM "TNM_SP2_GCLK_IDATA" TO "TNM_PCLK" TIG;
#TIMESPEC "TS_SP2_DOUBLECYC_IDATA" = FROM "TNM_SP2_EN_IDATA" TO "TNM_SP2_EN_IDATA" "TS_SCLK0";
NET "i_sp*/phase_hact_sel_sync*" TIG;
NET "ARO" CLOCK_DEDICATED_ROUTE = FALSE;
# my new constraints
#TIMEGRP "TG_FISUM" = ffs("fisum*");
TIMEGRP "TG_FOSUM" = ffs("fosum*");
#
#TIMESPEC "TS_ALL_FISUM" = FROM TG_ALL_FFS TO TG_FISUM TS_SCLK0;
TIMESPEC "TS_ALL_FOSUM" = FROM TG_ALL_FFS TO TG_FOSUM TS_SCLK0;
#
#TIMESPEC "TS_FISUM_ALL" = FROM TG_FISUM TO TG_ALL_FFS TS_SCLK0;
TIMESPEC "TS_FOSUM_ALL" = FROM TG_FOSUM TO TG_ALL_FFS TS_SCLK0;
#
#TIMEGRP "TG_I2CRDAT" = ffs("i2c_rdat*");
#
#TIMESPEC "TS_ALL_I2CRDAT" = FROM TG_ALL_FFS TO TG_I2CRDAT 10.501 ns;
\ No newline at end of file
x359.v 0 → 100644
View file @ 1727b764
This source diff could not be displayed because it is too large. You can view the blob instead.
x359.xise 0 → 100644
View file @ 1727b764
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="channel_rd_short.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="channel_rd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="channel_wr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="clkios353.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="dcm_phase.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ddr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="glbl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="i2csbr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ioports353.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="macros353.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr_arbiter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr_line_rd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr_line_wr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr_refresh.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="mcontr359.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sdram_phase.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sensor_phase359_tb.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="sensor_phase359_vact.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sensor_phase359.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sensor12bits.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="sync_frames.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="x359_pad.txt" xil_pn:type="FILE_USERDOC"/>
<file xil_pn:name="x359.tf" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="x359.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="x359.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1200e" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|x359" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="x359.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/x359" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="x359" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="x359_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="x359_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="x359_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="x359_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="xb359bbbb" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-11T19:33:34" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C64BC2AC8CDC8A84ADB95E2DDE4626A5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/x359" xil_pn:name="x359.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="ddr_parameters.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>
x359_import.tcl 0 → 100644
View file @ 1727b764
# ProjectNavigator SourceControl recreation script
#
# This script is text version of significant (but possibly not all)
# the information contained in the ISE project file. It is generated
# and used by the ProjectNavigator application's source control
# import feature.
#
# When using this script from the command line to recreate the ISE
# project, it should first be sourced from within an xtclsh shell.
# Next, the import procedure should be called to perform the import.
# When calling the import procedure, pass the new project directory
# and the source directory. If neither are specified, the current
# working directory is assumed for both.
#
# Internally this script has two file lists. One variable (import_files)
# has the set of files to copy into the project directory. The other
# variable (user_files) has the set of files to add into the project.
#
#
# This script is not intended for direct customer editing.
#
# Copyright 2006, Xilinx, Inc.
#
# Helper to copy files from the source staging area
# back into the destination work area.
# This proc will be call for each file copied.
# While not supported, one could do interesting things with this
# proc, since each file hits it.
proc CopyIn { srcfile work_area copy_option } {
set staging_area [pwd]
if { [ expr { [ file pathtype $srcfile ] == "absolute" || \
[string index $srcfile 0 ] == "/" || \
[string index $srcfile 1 ] == ":" } ] } {
set workfile $srcfile
} else {
set workfile [ file join $work_area $srcfile ]
}
if { $copy_option == "flatten" } {
set stagefile [ file join $staging_area [ file tail $srcfile ] ]
} elseif { [ file pathtype $srcfile ] != "relative" } {
set srcfile [ string map {: _} $srcfile ]
set stagefile [ file join $staging_area absolute $srcfile ]
} elseif { [ expr { $copy_option == "absremote" } && { [string equal -length 2 $srcfile ".." ] } ] } {
set stagefile [ file join $staging_area outside_relative [ string map {.. up} $srcfile ] ]
} else {
set srcfile [ string map {: _} $srcfile ]
set stagefile [ file join $staging_area $srcfile ]
}
set stagefile [ file normalize $stagefile ]
set workfile [ file normalize $workfile ]
if { [ file exists $stagefile ] } {
if { $stagefile != $workfile } {
file mkdir [ file dirname $workfile ]
file copy -force $stagefile $workfile
}
} else { WARN "\"$stagefile\" does not exist for import copy." }
}
proc ERR { msg } {
puts "ERROR: $msg"
}
proc WARN { msg } {
puts "WARNING: $msg"
}
proc INFO { msg } {
puts "$msg"
}
# Helper that returns 1 if the string is blank, otherwise 0.
proc IsBlank { str } {
if { [string length $str] == 0 } {
return 1
}
return 0
}
# Helper for determining whether a value is 'NULL'.
# Returns 1 if the value is 0; returns 0 if the value is anything else.
proc IsNull { val } {
if { $val == 0 } {
return 1
}
return 0
}
proc HandleException { script { msg "" } } {
set catch_result [catch {
uplevel 1 $script
} RESULT]
if {$catch_result} {
if {![IsBlank $msg]} {
ERR $msg
}
INFO "$RESULT"
INFO "$::errorInfo"
}
}
# These two procs help to load shared libraries in a platform
# independent way.
proc _LoadLibrary {name} {
set libExt [info sharedlibextension]
set libFullName "$name$libExt"
HandleException {
load $libFullName
} "A problem occured loading library $libFullName."
}
proc _LoadFactoryLibrary {Factory} {
HandleException {
Xilinx::Cit::FactoryLoad $Factory
} "A problem occured loading library $Factory."
}
_LoadLibrary libCit_CoreStub
_LoadLibrary libPrjrep_CommonStub
_LoadFactoryLibrary libPrjrep_Common
_LoadLibrary libDpm_SupportStub
_LoadLibrary libDpm_PnfStub
_LoadLibrary libDpm_DefnDataStub
_LoadLibrary libDpm_DesignDataStub
_LoadLibrary libDpm_HdlStub
_LoadLibrary libPrjrep_RepositoryStub
_LoadLibrary libCitI_CoreStub
_LoadLibrary libHdcI_HdcHDProjectStub
_LoadLibrary libTcltaskI_TaskStub
_LoadLibrary libCommonI_CommonStub
_LoadFactoryLibrary libTcltask_Helpers
_LoadFactoryLibrary libHdcC_HDProject
_LoadLibrary libHdcI_HdcContainerStub
# Helper to exectute code only when the (pointer) variable name is valid.
proc OnOkPtr { var_name script } {
if { [ uplevel info exists $var_name ] } {
upvar $var_name var
if { $var != 0 } { return [ uplevel $script ] }
}
}
# Helper to exectute code only when the (pointer) variable name is 0.
proc OnNullPtr { var_name script } {
if { [ uplevel info exists $var_name ] } {
upvar $var_name var
if { $var == 0 } { return [ uplevel $script ] }
}
}
# Helper to exectute code only when the value of variable name is 1.
proc OnSuccess { var_name script } {
if { $val != 0 } { return [ uplevel $script ] }
}
# Helper to exectute code only when the value of variable name is 0.
proc OnFail { val script } {
if { $val != 1 } { return [ uplevel $script ] }
}
# Helper to get a component interface.
proc GetInterface { iUnk id { name "" } } {
if {$iUnk == 0} { return 0 }
set iIface [ $iUnk GetInterface $id ]
OnNullPtr iIface {
if {![IsBlank $name]} {
ERR " Could not get the \"$name\" interface."
}
}
return $iIface
}
# Helper to create a component and return one of its interfaces.
proc CreateComponent { compId ifaceId { name "" } } {
set iUnk [ ::Xilinx::Cit::FactoryCreate $compId ]
set iIface [ GetInterface $iUnk $ifaceId ]
OnNullPtr iIface {
if {![IsBlank $name]} { ERR "Could not create a \"$name\" component." }
}
return $iIface
}
# Helper to release an object
proc Release { args } {
foreach iUnk $args {
set i_refcount [ GetInterface $iUnk $::xilinx::Prjrep::IRefCountID ]
OnNullPtr i_refcount { set i_refcount [ GetInterface $iUnk $::xilinx::CommonI::IRefCountID ] }
OnOkPtr i_refcount { $i_refcount Release }
}
}
# Helper to loop over IIterator based pointers.
proc ForEachIterEle { _ele_var_name _iter script } {
if {$_iter == 0} { return 0 }
upvar $_ele_var_name ele
for { $_iter First } { ![ $_iter IsEnd ] } { $_iter Next } {
set ele [ $_iter CurrentItem ]
set returned_val [ uplevel $script ]
}
}
# Helper to get the Tcl Project Manager, if possible.
proc GetTclProjectMgr { } {
set TclProjectMgrId "{7d528480-1196-4635-aba9-639446e4aa59}"
set iUnk [ Xilinx::CitP::CreateComponent $TclProjectMgrId ]
if {$iUnk == 0} { return 0 }
set iTclProjectMgr [ $iUnk GetInterface $::xilinx::TcltaskI::ITclProjectMgrID ]
OnNullPtr iTclProjectMgr {
ERR "Could not create a \"TclProjectMgr\" component."
}
return $iTclProjectMgr
}
# Helper to get the current Tcl Project, if one is open.
proc GetCurrentTclProject { } {
set iTclProject 0
set iTclProjectMgr [GetTclProjectMgr]
OnOkPtr iTclProjectMgr {
set errmsg ""
$iTclProjectMgr GetCurrentTclProject iTclProject errmsg
}
return $iTclProject
}
# Helper to get the current HDProject, if one is open.
proc GetCurrentHDProject { } {
set iHDProject 0
set iTclProjectMgr [GetTclProjectMgr]
set errmsg ""
OnOkPtr iTclProjectMgr { $iTclProjectMgr GetCurrentHDProject iHDProject errmsg }
OnNullPtr iHDProject {
ERR "Could not get the current HDProject."
}
return $iHDProject
}
# Helper to create a Project Helper.
proc GetProjectHelper { } {
set ProjectHelperID "{0725c3d2-5e9b-4383-a7b6-a80c932eac21}"
set iProjHelper [CreateComponent $ProjectHelperID $::xilinx::Dpm::IProjectHelperID "Project Helper"]
return $iProjHelper
}
# Helper to find out if a project is currently open.
# Returns 1 if a project is open, otherwise 0.
proc IsProjectOpen { } {
set iTclProject [GetCurrentTclProject]
set isOpen [expr {$iTclProject != 0}]
Release $iTclProject
return $isOpen
}
# Helper to return the lock file for the specified project if there is one.
# Returns an empty string if there is no lock file on the specified project.
# This assumes that the project_file is in the current directory.
# It also assumes project_file does not have a path.
proc GetProjectLockFile { project_file } {
INFO "Checking for a lock file for \"$project_file\"."
set lock_file "__ISE_repository_${project_file}_.lock"
if { [ file isfile "$lock_file" ] } {
return $lock_file
}
return
}
# Helper to move aside the project file.
# This assumes that the project_file is in the current directory.
proc MoveProject { project_file backup_file } {
INFO "Moving aside the project \"$project_file\" so that it can be recreated."
INFO "The project will be backed up as \"$backup_file\"."
if { ![ file isfile "$project_file" ] } {
WARN "Could not move \"$project_file\"; it does not exist or is not a file."
return 1
}
file rename -force "$project_file" "$backup_file"
# We will need to bail if the project still exists.
if { [ file isfile "$project_file" ] } {
ERR "Could not remove \"$project_file\"; unable to recreate the project.."
return 0
}
return 1
}
# Helper to open a project and return a project facilitator (pointer).
proc OpenFacilProject { project_name } {
# first make sure the tcl project mgr singleton exists
GetTclProjectMgr
# get a Project Helper and open the project.
set iProjHelper [GetProjectHelper]
if {$iProjHelper == 0} { return 0 }
set result [$iProjHelper Open $project_name]
OnFail $result {
if {$result == 576460769483292673} {
ERR "Could not open the project \"$project_name\" because it is locked."
} else {
ERR "Could not open the \"$project_name\" project."
}
Release $iProjHelper
set iProjHelper 0
}
return $iProjHelper
}
# Helper to close and release a project.
proc CloseFacilProject { iProjHelper } {
if {$iProjHelper == 0} { return }
$iProjHelper Close
Release $iProjHelper
}
# Helper to get the Project from the Project Helper.
# Clients must release this.
proc GetProject { iProjHelper } {
if {$iProjHelper == 0} { return 0 }
set dpm_project 0
$iProjHelper GetDpmProject dpm_project
set iProject [ GetInterface $dpm_project $xilinx::Dpm::IProjectID ]
OnNullPtr iProject {
ERR "Could not get the Project from the Project Helper."
}
return $iProject
}
# Helper to get the File Manager from the Project Helper.
# Clients must release this.
proc GetFileManager { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iFileMgr [ GetInterface $iProject $xilinx::Dpm::IFileManagerID ]
OnNullPtr iFileMgr {
ERR "Could not get the File Manager from the Project Helper."
}
# Don't release the project here, clients will release it
# when they release its IFileManager interface.
return $iFileMgr
}
# Helper to get the Source Library Manager from the Project Helper.
# Clients must release this.
proc GetSourceLibraryManager { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iSourceLibraryMgr [ GetInterface $iProject $xilinx::Dpm::ISourceLibraryManagerID ]
OnNullPtr iSourceLibraryMgr {
ERR "Could not get the Source Library Manager from the Project Helper."
}
# Don't release the project here, clients will release it
# when they release its IFileManager interface.
return $iSourceLibraryMgr
}
# Helper to get the ProjSrcHelper from the Project Helper.
# Clients must NOT release this.
proc GetProjSrcHelper { iProjHelper } {
set iSrcHelper [ GetInterface $iProjHelper $::xilinx::Dpm::IProjSrcHelperID IProjSrcHelper ]
OnNullPtr iSrcHelper {
ERR "Could not get the ProjSrcHelper from the Project Helper."
}
return $iSrcHelper
}
# Helper to get the ScratchPropertyManager from the Project Helper.
# Clients must NOT release this.
proc GetScratchPropertyManager { iProjHelper } {
set iPropTableFetch [ GetInterface $iProjHelper $xilinx::Dpm::IPropTableFetchID IPropTableFetch ]
set prop_table_comp 0
OnOkPtr iPropTableFetch {
$iPropTableFetch GetPropTable prop_table_comp
}
set iScratch [ GetInterface $prop_table_comp $xilinx::Dpm::IScratchPropertyManagerID ]
OnNullPtr iScratch {
ERR "Could not get the Scratch Property Manager from the Project Helper."
}
return $iScratch
}
# Helper to get the Design from the Project Helper.
# Clients must release this.
proc GetDesign { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iDesign 0
OnOkPtr iProject { $iProject GetDesign iDesign }
OnNullPtr iDesign {
ERR "Could not get the Design from the Project Helper."
}
Release $iProject
return $iDesign
}
# Helper to get the Data Store from the Project Helper.
# Clients must NOT release this.
proc GetDataStore { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iDataStore 0
OnOkPtr iDesign { $iDesign GetDataStore iDataStore }
OnNullPtr iDataStore {
ERR "Could not get the Data Store from the Project Helper."
}
Release $iDesign
return $iDataStore
}
# Helper to get the View Manager from the Project Helper.
# Clients must NOT release this.
proc GetViewManager { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iViewMgr [ GetInterface $iDesign $xilinx::Dpm::IViewManagerID ]
OnNullPtr iViewMgr {
ERR "Could not get the View Manager from the Project Helper."
}
# Don't release the design here, clients will release it
# when they release its IViewManager interface.
return $iViewMgr
}
# Helper to get the Property Manager from the Project Helper.
# Clients must release this.
proc GetPropertyManager { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iPropMgr 0
OnOkPtr iDesign { $iDesign GetPropertyManager iPropMgr }
OnNullPtr iPropMgr {
ERR "Could not get the Property Manager from the Project Helper."
}
Release $iDesign
return $iPropMgr
}
# Helper to find a property template, based on prop_name
# Clients must NOT release this.
proc GetPropertyTemplate { iProjHelper prop_name } {
set iPropTempl 0
set iUnk 0
set iDefdataId 0
set iPropTemplStore 0
set iDataStore [GetDataStore $iProjHelper]
OnOkPtr iDataStore { $iDataStore GetComponentByName $prop_name iUnk }
OnOkPtr iUnk { set iDefdataId [ GetInterface $iUnk $xilinx::Dpm::IDefDataIdID IDefDataId ] }
OnOkPtr iDefdataId {
set iPropTemplStore [ GetInterface $iDataStore $xilinx::Dpm::IPropertyTemplateStoreID IPropertyTemplateStore ]
}
OnOkPtr iPropTemplStore { $iPropTemplStore GetPropertyTemplate $iDefdataId iPropTempl }
OnNullPtr iPropTempl {
WARN "Could not get the property template for \"$prop_name\"."
}
return $iPropTempl
}
# Helper to get a component's name.
proc GetName { iUnk } {
set name ""
set iName [ GetInterface $iUnk $xilinx::Prjrep::INameID IName ]
OnOkPtr iName { $iName GetName name }
return $name
}
# Helper to get the name of a view's type.
proc GetViewTypeName { iView } {
set typeName ""
set iType 0
set iDefdataType 0
OnOkPtr iView { $iView GetType iType }
OnOkPtr iType {
set iDefdataType [ GetInterface $iType $xilinx::Dpm::IDefDataIdID IDefDataId ]
}
OnOkPtr iDefdataType { $iDefdataType GetID typeName }
return $typeName
}
# Helper to find a view and return its context.
# Must clients release this?
proc GetViewContext { iProjHelper view_id view_name } {
# Simply return if the view_id or view_name is empty.
if { [IsBlank $view_id] || [IsBlank $view_name] } { return 0 }
set foundview 0
set viewiter 0
set iViewMgr [GetViewManager $iProjHelper]
OnOkPtr iViewMgr { $iViewMgr GetViews viewiter }
ForEachIterEle view $viewiter {
set typeName [GetViewTypeName $view]
set name [GetName $view]
if { [ string equal $name $view_name ] && [ string equal $view_id $typeName ] } {
set foundview $view
}
}
set context [ GetInterface $foundview $xilinx::Dpm::IPropertyContextID ]
OnNullPtr context {
WARN "Could not get the context for view \"$view_id\":\"$view_name\"."
}
return $context
}
# Helper to get a string property instance from the property manager.
proc GetStringPropertyInstance { iProjHelper simple_id } {
set iPropMgr [GetPropertyManager $iProjHelper]
if {$iPropMgr == 0} { return 0 }
set iPropInst 0
$iPropMgr GetStringProperty $simple_id iPropInst
OnNullPtr iPropInst { WARN "Could not get the string property instance $simple_id." }
Release $iPropMgr
return $iPropInst
}
# Helper to get a property instance from the property manager.
proc GetPropertyInstance { iProjHelper view_name view_id prop_name } {
set iPropInst 0
set iPropTempl [ GetPropertyTemplate $iProjHelper $prop_name ]
if {$iPropTempl == 0} { return 0 }
set context [ GetViewContext $iProjHelper $view_id $view_name ]
set iPropMgr [GetPropertyManager $iProjHelper]
if {$iPropMgr == 0} { return 0 }
$iPropMgr GetPropertyInstance $iPropTempl $context iPropInst
OnNullPtr iPropInst {
if { ![IsBlank $view_id] && ![IsBlank $view_name] } {
WARN "Could not get the context sensitive property instance $prop_name."
} else {
WARN "Could not get the property instance $prop_name."
}
}
Release $iPropMgr
return $iPropInst
}
# Helper to store properties back into the property manager.
proc RestoreProcessProperties { iProjHelper process_props } {
INFO "Restoring process properties"
foreach { unused view_name view_id simple_id prop_name prop_val } $process_props {
set iPropInst 0
if {![IsBlank $simple_id]} {
set iPropInst [ GetStringPropertyInstance $iProjHelper $simple_id ]
} else {
set iPropInst [ GetPropertyInstance $iProjHelper $view_name $view_id $prop_name ]
}
OnOkPtr iPropInst {
OnFail [ $iPropInst SetStringValue "$prop_val" ] {
WARN "Could not set the value of the $prop_name property to \"$prop_val\"."
}
}
Release $iPropInst
}
}
# Helper to recreate partitions from the variable name with
# a list of instance names.
proc RestorePartitions { namelist } {
INFO "Restoring partitions."
set iHDProject [ GetCurrentHDProject ]
OnOkPtr iHDProject {
foreach name $namelist {
set iPartition [ $iHDProject CreatePartition "$name" ]
}
}
}
# Helper to create and populate a library
#
proc CreateLibrary { iProjHelper libname filelist } {
set iLibMgr [ GetSourceLibraryManager $iProjHelper ]
set iFileMgr [ GetFileManager $iProjHelper ]
if {$iLibMgr == 0} { return 0 }
if {$iFileMgr == 0} { return 0 }
$iLibMgr CreateSourceLibrary "libname" ilib
OnOkPtr ilib {
foreach filename $filelist {
set argfile [ file normalize "$filename" ]
set found 0
set fileiter 0
$iFileMgr GetFiles fileiter
ForEachIterEle ifile $fileiter {
set path ""
set file ""
$ifile getPath path file
set currentfile [ file normalize [ file join "$path" "$file" ] ]
if { $currentfile == $argfile } {
set found 1
$ilib AddFile ifile
break
}
}
OnNullPtr found {
WARN "Could not add the file \"$filename\" to the library \"$libname\"."
}
}
}
}
# Helper to create source libraries and populate them.
proc RestoreSourceLibraries { iProjHelper libraries } {
INFO "Restoring source libraries."
foreach { libname filelist } $libraries {
CreateLibrary $iProjHelper "$libname" $filelist
}
}
# Helper to add user files to the project using the PnF.
proc AddUserFiles { iProjHelper files } {
INFO "Adding User files."
set iconflict 0
set iSrcHelper [ GetProjSrcHelper $iProjHelper ]
if {$iSrcHelper == 0} { return 0 }
foreach filename $files {
INFO "Adding the file \"$filename\" to the project."
set result [$iSrcHelper AddSourceFile "$filename" iconflict]
OnFail $result {
if {$result == 6} {
INFO "The file \"$filename\" is already in the project."
} else {
ERR "A problem occurred adding the file \"$filename\" to the project."
}
}
}
}
# Helper to add files to the project and set their origination.
# Valid origination values are:
# 0 - User
# 1 - Generated
# 2 - Imported
# Files of origination "User" are added through the facilitator,
# otherwise they are added directly to the File Manager.
proc AddImportedFiles { iProjHelper files origination } {
switch $origination {
0 { INFO "Adding User files." }
1 { INFO "Adding Generated files." }
2 { INFO "Adding Imported files." }
default {
ERR "Invalid parameter: origination was set to \"$origination\", but may only be 0, 1, or 2."
return 0
}
}
set iFileMgr [ GetFileManager $iProjHelper ]
if {$iFileMgr == 0} { return 0 }
foreach filename $files {
set file_type 0
set hdl_file 0
set result [$iFileMgr AddFile "$filename" $file_type hdl_file]
OnFail $result {
if {$result == 6} {
INFO "The file \"$filename\" is already in the project."
} elseif { $hdl_file == 0 } {
ERR "A problem occurred adding the file \"$filename\" to the project."
}
}
OnOkPtr hdl_file {
set ifile [ GetInterface $hdl_file $xilinx::Dpm::IFileID IFile ]
OnOkPtr ifile {
set result [ $ifile SetOrigination $origination ]
if {$result != 1} {
ERR "A problem occurred setting the origination of \"$filename\" to \"$origination\"."
}
Release $ifile
}
}
}
return 1
}
proc RestoreProjectSettings { iProjHelper project_settings } {
INFO "Restoring device settings"
set iScratch [GetScratchPropertyManager $iProjHelper]
set iPropIter 0
set iPropSet [ GetInterface $iScratch $xilinx::Dpm::IPropertyNodeSetID IPropertyNodeSet ]
OnOkPtr iPropSet {
$iPropSet GetIterator iPropIter
}
set index 0
set lastindex [llength $project_settings]
ForEachIterEle prop_node $iPropIter {
set prop_instance 0
$prop_node GetPropertyInstance prop_instance
if { $index < $lastindex } {
set argname [ lindex $project_settings $index ]
set argvalue [ lindex $project_settings [ expr $index + 1 ] ]
} else {
set argname {}
set argvalue {}
}
if { $prop_instance != 0 } {
set name {}
$prop_instance GetName name
if { [string equal $name $argname ] } {
$prop_instance SetStringValue $argvalue
incr index
incr index
}
}
Release $prop_instance
}
$iScratch Commit
# initialize
$iProjHelper Init
}
# Helper to load a source control configuration from a stream
# and then store it back into an ise file.
proc RestoreSourceControlOptions { prjfile istream } {
INFO "Restoring source control options"
set config_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlConfigurationCompID ]
OnOkPtr config_comp { set ipersist [ $config_comp GetInterface $xilinx::Prjrep::IPersistID ] }
OnOkPtr config_comp { set igetopts [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IGetOptionsID ] }
set helper_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlHelpCompID ]
OnOkPtr helper_comp { set ihelper [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IHelperID ] }
OnOkPtr ipersist { $ipersist Load istream }
OnOkPtr ihelper { OnOkPtr igetopts { $ihelper SaveOptions $prjfile $igetopts } }
Release $helper_comp $config_comp
}
proc import { {working_area ""} {staging_area ""} { srcctrl_comp 0 } } {
set project_file "x359.ise"
set old_working_dir [pwd]
# intialize the new project directory (work) and
# source control reference directory (staging) to
# current working directory, when not specified
if { $working_area == "" } { set working_area [pwd] }
if { $staging_area == "" } { set staging_area [pwd] }
set copy_option relative
set import_files {
"x359.v"
"ddr.v"
"mcontr359.v"
"ioports353.v"
"x359.tf"
"channel_wr.v"
"channel_rd.v"
"channel_rd_short.v"
"mcontr_arbiter.v"
"mcontr_cmd.v"
"mcontr_line_rd"
"mcontr_line_wr"
"mcontr_refresh"
"x359.ucf"
"sensor.dat"
"clkios353.v"
"i2csbr.v"
"ddr_parameters.v"
"sensor12bits.v"
"sdram_phase.v"
"macros353.v"
"glbl.v"
"x359_sim.sh"}
INFO "Copying files from \"$staging_area\" to \"$working_area\""
# Must be in the staging directory before calling CopyIn.
cd [file normalize "$staging_area"]
foreach file $import_files {
CopyIn "$file" "$working_area" $copy_option
}
set iProjHelper 0
# Bail if a project currently open.
if {[IsProjectOpen]} {
ERR "The project must be closed before performing this operation."
return 0
}
# Must be in the working area (i.e. project directory) before calling recreating the project.
cd [file normalize "$working_area"]
INFO "Recreating project \"$project_file\"."
HandleException {
set iProjHelper [ OpenFacilProject "$project_file"]
} "A problem occurred while creating the project \"$project_file\"."
if {$iProjHelper == 0} {
cd "$old_working_dir"
return 0
}
set project_settings {
"PROP_DevFamily" "Spartan3E"
"PROP_DevDevice" "xc3s1200e"
"PROP_DevPackage" "ft256"
"PROP_DevSpeed" "-4"
"PROP_Top_Level_Module_Type" "HDL"
"PROP_Synthesis_Tool" "XST (VHDL/Verilog)"
"PROP_Simulator" "ISE Simulator (VHDL/Verilog)"
"PROP_PreferredLanguage" "Verilog"
"PROP_Enable_Message_Capture" "true"
"PROP_Enable_Message_Filtering" "true"
"PROP_Enable_Incremental_Messaging" "true"
}
HandleException {
RestoreProjectSettings $iProjHelper $project_settings
} "A problem occured while restoring project settings."
set user_files {
"x359.v"
"ddr.v"
"mcontr359.v"
"ioports353.v"
"x359.tf"
"channel_wr.v"
"channel_rd.v"
"channel_rd_short.v"
"mcontr_arbiter.v"
"mcontr_cmd.v"
"mcontr_line_rd"
"mcontr_line_wr"
"mcontr_refresh"
"x359.ucf"
"sensor.dat"
"clkios353.v"
"i2csbr.v"
"ddr_parameters.v"
"sensor12bits.v"
"sdram_phase.v"
"macros353.v"
"glbl.v"
"x359_sim.sh"}
HandleException {
AddUserFiles $iProjHelper $user_files
} "A problem occured while restoring user files."
set imported_files {}
set origination 2
HandleException {
AddImportedFiles $iProjHelper $imported_files $origination
} "A problem occured while restoring imported files."
set process_props {
"A" "" "" "" "PROPEXT_SynthMultStyle_virtex2" "Auto"
"A" "" "" "" "PROPEXT_xilxBitgCfg_Rate_spartan3e" "Default (1)"
"A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex2" "5"
"A" "" "" "" "PROPEXT_xilxSynthAddBufg_spartan3e" "24"
"A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex2" "500"
"A" "" "" "" "PROP_CPLDFitkeepio" "false"
"A" "" "" "" "PROP_CompxlibAbelLib" "true"
"A" "" "" "" "PROP_CompxlibCPLDDetLib" "true"
"A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" ""
"A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX/<language>/<simulator>"
"A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite"
"A" "" "" "" "PROP_CompxlibSimPath" "Search in Path"
"A" "" "" "" "PROP_CompxlibSimPrimatives" "true"
"A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true"
"A" "" "" "" "PROP_CurrentFloorplanFile" ""
"A" "" "" "" "PROP_DesignName" "x359"
"A" "" "" "" "PROP_Dummy" "dum1"
"A" "" "" "" "PROP_EnableWYSIWYG" "None"
"A" "" "" "" "PROP_Enable_Incremental_Messaging" "true"
"A" "" "" "" "PROP_Enable_Message_Capture" "true"
"A" "" "" "" "PROP_Enable_Message_Filtering" "true"
"A" "" "" "" "PROP_FitterReportFormat" "HTML"
"A" "" "" "" "PROP_FlowDebugLevel" "0"
"A" "" "" "" "PROP_FunctionBlockInputLimit" "38"
"A" "" "" "" "PROP_ISimLibSearchOrderFile" ""
"A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time"
"A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false"
"A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false"
"A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false"
"A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false"
"A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false"
"A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false"
"A" "" "" "" "PROP_ISimUutInstName" "UUT"
"A" "" "" "" "PROP_ImpactProjectFile" ""
"A" "" "" "" "PROP_Parse_Target" "synthesis"
"A" "" "" "" "PROP_PartitionCreateDelete" ""
"A" "" "" "" "PROP_PartitionForcePlacement" ""
"A" "" "" "" "PROP_PartitionForceSynth" ""
"A" "" "" "" "PROP_PartitionForceTranslate" ""
"A" "" "" "" "PROP_PlsClockEnable" "true"
"A" "" "" "" "PROP_PostTrceFastPath" "false"
"A" "" "" "" "PROP_PreTrceFastPath" "false"
"A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false"
"A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false"
"A" "" "" "" "PROP_SimModelOtherNetgenOpts" ""
"A" "" "" "" "PROP_SimModelRetainHierarchy" "true"
"A" "" "" "" "PROP_SynthCaseImplStyle" "None"
"A" "" "" "" "PROP_SynthDecoderExtract" "true"
"A" "" "" "" "PROP_SynthEncoderExtract" "Yes"
"A" "" "" "" "PROP_SynthExtractMux" "Yes"
"A" "" "" "" "PROP_SynthExtractRAM" "true"
"A" "" "" "" "PROP_SynthExtractROM" "true"
"A" "" "" "" "PROP_SynthFsmEncode" "Auto"
"A" "" "" "" "PROP_SynthLogicalShifterExtract" "true"
"A" "" "" "" "PROP_SynthOpt" "Speed"
"A" "" "" "" "PROP_SynthOptEffort" "High"
"A" "" "" "" "PROP_SynthResSharing" "true"
"A" "" "" "" "PROP_SynthShiftRegExtract" "false"
"A" "" "" "" "PROP_SynthXORCollapse" "true"
"A" "" "" "" "PROP_Top_Level_Module_Type" "HDL"
"A" "" "" "" "PROP_UseDataGate" "true"
"A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor"
"A" "" "" "" "PROP_UserEditorCustomSetting" ""
"A" "" "" "" "PROP_UserEditorPreference" "ISE Text Editor"
"A" "" "" "" "PROP_XPowerOptInputTclScript" ""
"A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default"
"A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default"
"A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default"
"A" "" "" "" "PROP_XPowerOptOutputFile" "Default"
"A" "" "" "" "PROP_XPowerOptVerboseRpt" "false"
"A" "" "" "" "PROP_XPowerOtherXPowerOpts" ""
"A" "" "" "" "PROP_XplorerMode" "Off"
"A" "" "" "" "PROP_bitgen_otherCmdLineOptions" ""
"A" "" "" "" "PROP_cpldBestFit" "false"
"A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source"
"A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" ""
"A" "" "" "" "PROP_fitGenSimModel" "false"
"A" "" "" "" "PROP_hprep6_autosig" "false"
"A" "" "" "" "PROP_hprep6_otherCmdLineOptions" ""
"A" "" "" "" "PROP_ibiswriterShowAllModels" "false"
"A" "" "" "" "PROP_impactConfigFileName_CPLD" ""
"A" "" "" "" "PROP_mapUseRLOCConstraints" "true"
"A" "" "" "" "PROP_map_otherCmdLineOptions" ""
"A" "" "" "" "PROP_mpprRsltToCopy" ""
"A" "" "" "" "PROP_mpprViewPadRptsForAllRslt" "true"
"A" "" "" "" "PROP_mpprViewParRptsForAllRslt" "true"
"A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true"
"A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" ""
"A" "" "" "" "PROP_parTimingAnalyzerLoadDesign" "true"
"A" "" "" "" "PROP_parUseTimingConstraints" "true"
"A" "" "" "" "PROP_par_otherCmdLineOptions" ""
"A" "" "" "" "PROP_primeCorrelateOutput" "false"
"A" "" "" "" "PROP_primeFlatternOutputNetlist" "false"
"A" "" "" "" "PROP_primeTopLevelModule" ""
"A" "" "" "" "PROP_primetimeBlockRamData" ""
"A" "" "" "" "PROP_taengine_otherCmdLineOptions" ""
"A" "" "" "" "PROP_xcpldFitDesInit" "Low"
"A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32"
"A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true"
"A" "" "" "" "PROP_xcpldFitDesSlew" "Fast"
"A" "" "" "" "PROP_xcpldFitDesTimingCst" "true"
"A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper"
"A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper"
"A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18"
"A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density"
"A" "" "" "" "PROP_xcpldFittimRptOption" "Summary"
"A" "" "" "" "PROP_xcpldUseGlobalClocks" "true"
"A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true"
"A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true"
"A" "" "" "" "PROP_xcpldUseLocConst" "Always"
"A" "" "" "" "PROP_xilxBitgCfg_Code" "0x03594001"
"A" "" "" "" "PROP_xilxBitgCfg_DCMShutdown" "false"
"A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false"
"A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TDO" "Float"
"A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down"
"A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration"
"A" "" "" "" "PROP_xilxBitgStart_Clk" "JTAG Clock"
"A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false"
"A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "5"
"A" "" "" "" "PROP_xilxBitgStart_IntDone" "false"
"A" "" "" "" "PROP_xilxMapAllowLogicOpt" "true"
"A" "" "" "" "PROP_xilxMapCoverMode" "Speed"
"A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false"
"A" "" "" "" "PROP_xilxMapPackRegInto" "For Inputs and Outputs"
"A" "" "" "" "PROP_xilxMapReplicateLogic" "true"
"A" "" "" "" "PROP_xilxMapReportDetail" "true"
"A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false"
"A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "true"
"A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true"
"A" "" "" "" "PROP_xilxNgdbldIOPads" "false"
"A" "" "" "" "PROP_xilxNgdbldMacro" ""
"A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp"
"A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false"
"A" "" "" "" "PROP_xilxNgdbldUR" ""
"A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false"
"A" "" "" "" "PROP_xilxNgdbld_AUL" "false"
"A" "" "" "" "PROP_xilxPARplacerCostTable" "1"
"A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None"
"A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None"
"A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route"
"A" "" "" "" "PROP_xilxPARuseBondedIO" "false"
"A" "" "" "" "PROP_xilxPostTrceAdvAna" "true"
"A" "" "" "" "PROP_xilxPostTrceRpt" "Verbose Report"
"A" "" "" "" "PROP_xilxPostTrceRptLimit" "3"
"A" "" "" "" "PROP_xilxPostTrceStamp" ""
"A" "" "" "" "PROP_xilxPostTrceTSIFile" ""
"A" "" "" "" "PROP_xilxPostTrceUncovPath" ""
"A" "" "" "" "PROP_xilxPreTrceAdvAna" "false"
"A" "" "" "" "PROP_xilxPreTrceRpt" "Verbose Report"
"A" "" "" "" "PROP_xilxPreTrceRptLimit" "3"
"A" "" "" "" "PROP_xilxPreTrceUncovPath" ""
"A" "" "" "" "PROP_xilxSynthAddIObuf" "true"
"A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets"
"A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No"
"A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes"
"A" "" "" "" "PROP_xilxSynthMacroPreserve" "true"
"A" "" "" "" "PROP_xilxSynthRegBalancing" "No"
"A" "" "" "" "PROP_xilxSynthRegDuplication" "true"
"A" "" "" "" "PROP_xilxSynthXORPreserve" "true"
"A" "" "" "" "PROP_xstAsynToSync" "false"
"A" "" "" "" "PROP_xstAutoBRAMPacking" "false"
"A" "" "" "" "PROP_xstBRAMUtilRatio" "100"
"A" "" "" "" "PROP_xstBusDelimiter" "<>"
"A" "" "" "" "PROP_xstCase" "Maintain"
"A" "" "" "" "PROP_xstCoresSearchDir" ""
"A" "" "" "" "PROP_xstCrossClockAnalysis" "false"
"A" "" "" "" "PROP_xstEquivRegRemoval" "true"
"A" "" "" "" "PROP_xstFsmStyle" "LUT"
"A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes"
"A" "" "" "" "PROP_xstGenericsParameters" ""
"A" "" "" "" "PROP_xstHierarchySeparator" "/"
"A" "" "" "" "PROP_xstIniFile" ""
"A" "" "" "" "PROP_xstLibSearchOrder" ""
"A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false"
"A" "" "" "" "PROP_xstPackIORegister" "Auto"
"A" "" "" "" "PROP_xstReadCores" "true"
"A" "" "" "" "PROP_xstSlicePacking" "true"
"A" "" "" "" "PROP_xstSliceUtilRatio" "100"
"A" "" "" "" "PROP_xstUseClockEnable" "Yes"
"A" "" "" "" "PROP_xstUseSyncReset" "Auto"
"A" "" "" "" "PROP_xstUseSyncSet" "Auto"
"A" "" "" "" "PROP_xstUseSynthConstFile" "true"
"A" "" "" "" "PROP_xstUserCompileList" ""
"A" "" "" "" "PROP_xstVeriIncludeDir_Global" ""
"A" "" "" "" "PROP_xstVerilog2001" "true"
"A" "" "" "" "PROP_xstVerilogMacros" ""
"A" "" "" "" "PROP_xstWorkDir" "./xst"
"A" "" "" "" "PROP_xstWriteTimingConstraints" "false"
"A" "" "" "" "PROP_xst_otherCmdLineOptions" ""
"A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "Module|x359_tf"
"A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimIncreCompilation" "true"
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifySearchDirectory" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimValueRangeCheck" "false"
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedResultsFuse" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedResultsISim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_BehavioralFuse" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_BehavioralSimulationISim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "Module|x359_tf"
"A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "Module|x359_tf"
"A" "AutoGeneratedView" "VIEW_Post-ParFuse" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true"
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true"
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" ""
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" ""
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false"
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-ParSimulationISim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "Module|x359_tf"
"A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "Module|x359_tf"
"A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimCompileForHdlDebug" "true"
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimIncreCompilation" "true"
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" ""
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDir" ""
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDirectory" ""
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimValueRangeCheck" "false"
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Structural" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_TBWBehavioralFuse" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationISim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParFuse" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true"
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true"
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false"
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationISim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true"
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimIncreCompilation" "true"
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" ""
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifySearchDirectory" ""
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimValueRangeCheck" "false"
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_UpdatedBitstream" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "Module|x359"
"A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" ""
"A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "Module|x359_tf"
"B" "" "" "" "PROP_AutoGenFile" "false"
"B" "" "" "" "PROP_DevFamily" "Spartan3E"
"B" "" "" "" "PROP_FitterOptimization_xpla3" "Density"
"B" "" "" "" "PROP_ISimCustomCompilationOrderFile" ""
"B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" ""
"B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" ""
"B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" ""
"B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" ""
"B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" ""
"B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false"
"B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false"
"B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true"
"B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true"
"B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true"
"B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true"
"B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tb" "false"
"B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tbw" "false"
"B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tb" "false"
"B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tbw" "false"
"B" "" "" "" "PROP_MapEffortLevel" "High"
"B" "" "" "" "PROP_MapLogicOptimization" "true"
"B" "" "" "" "PROP_MapPlacerCostTable" "1"
"B" "" "" "" "PROP_MapPowerReduction" "false"
"B" "" "" "" "PROP_MapRegDuplication" "true"
"B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT"
"B" "" "" "" "PROP_Simulator" "ISE Simulator (VHDL/Verilog)"
"B" "" "" "" "PROP_SynthConstraintsFile" ""
"B" "" "" "" "PROP_SynthMuxStyle" "Auto"
"B" "" "" "" "PROP_SynthRAMStyle" "Distributed"
"B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false"
"B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000"
"B" "" "" "" "PROP_XPowerOptUseTimeBased" "false"
"B" "" "" "" "PROP_impactBaud" "None"
"B" "" "" "" "PROP_impactConfigMode" "None"
"B" "" "" "" "PROP_impactPort" "None"
"B" "" "" "" "PROP_mpprViewPadRptForSelRslt" ""
"B" "" "" "" "PROP_mpprViewParRptForSelRslt" ""
"B" "" "" "" "PROP_parGenAsyDlyRpt" "true"
"B" "" "" "" "PROP_parGenClkRegionRpt" "true"
"B" "" "" "" "PROP_parGenSimModel" "false"
"B" "" "" "" "PROP_parGenTimingRpt" "true"
"B" "" "" "" "PROP_parMpprNodelistFile" ""
"B" "" "" "" "PROP_parMpprParIterations" "3"
"B" "" "" "" "PROP_parMpprResultsDirectory" "mppr_result"
"B" "" "" "" "PROP_parMpprResultsToSave" ""
"B" "" "" "" "PROP_parPowerReduction" "false"
"B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true"
"B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28"
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false"
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false"
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false"
"B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false"
"B" "" "" "" "PROP_xilxMapPackfactor" "100"
"B" "" "" "" "PROP_xilxPAReffortLevel" "Standard"
"B" "" "" "" "PROP_xstMoveFirstFfStage" "true"
"B" "" "" "" "PROP_xstMoveLastFfStage" "true"
"B" "" "" "" "PROP_xstROMStyle" "Distributed"
"B" "" "" "" "PROP_xstSafeImplement" "No"
"B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" ""
"B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" ""
"C" "" "" "" "PROP_AceActiveName" ""
"C" "" "" "" "PROP_CompxlibLang" "VHDL"
"C" "" "" "" "PROP_DevDevice" "xc3s1200e"
"C" "" "" "" "PROP_DevFamilyPMName" "spartan3e"
"C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns"
"C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns"
"C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns"
"C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns"
"C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd"
"C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd"
"C" "" "" "" "PROP_MapExtraEffort" "Normal"
"C" "" "" "" "PROP_SimModelGenMultiHierFile" "false"
"C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps"
"C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1"
"C" "" "" "" "PROP_impactConfigFileName" ""
"C" "" "" "" "PROP_xilxPARextraEffortLevel" "Normal"
"D" "" "" "" "PROP_CompxlibUni9000Lib" "true"
"D" "" "" "" "PROP_CompxlibUniSimLib" "true"
"D" "" "" "" "PROP_DevPackage" "ft256"
"D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)"
"E" "" "" "" "PROP_DevSpeed" "-4"
"E" "" "" "" "PROP_PreferredLanguage" "Verilog"
"F" "" "" "" "PROP_ChangeDevSpeed" "-4"
"F" "" "" "" "PROP_SimModelTarget" "Verilog"
"F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog"
"F" "" "" "" "PROP_xilxPostTrceSpeed" "-4"
"F" "" "" "" "PROP_xilxPreTrceSpeed" "-4"
"G" "" "" "" "PROP_PostSynthSimModelName" "x359_synthesis.v"
"G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true"
"G" "" "" "" "PROP_SimModelGenArchOnly" "false"
"G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true"
"G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelNoEscapeSignal" "false"
"G" "" "" "" "PROP_SimModelOutputExtIdent" "false"
"G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure"
"G" "" "" "" "PROP_SimModelRenTopLevMod" ""
"G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "x359_map.v"
"G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "x359_timesim.v"
"G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "x359_tf.map_tfw"
"G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "x359_tf.timesim_tfw"
"G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "x359_tf.translate_tfw"
"G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "x359_translate.v"
"H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false"
"H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false"
"H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default"
"H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "x359"
"H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "x359"
"H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "x359"
"H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "x359"
"I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT"
"I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT"
"I" "" "" "" "PROP_SimModelRocPulseWidth" "100"
"I" "" "" "" "PROP_SimModelTocPulseWidth" "0"}
HandleException {
RestoreProcessProperties $iProjHelper $process_props
} "A problem occured while restoring process properties."
# library names and their members
set libraries {
}
HandleException {
RestoreSourceLibraries $iProjHelper $libraries
} "A problem occured while restoring source libraries."
# partition names for recreation
set partition_names {
}
HandleException {
RestorePartitions $partition_names
} "A problem occured while restoring partitions."
set opts_stream [ [Xilinx::Cit::FactoryCreate $::xilinx::Dpm::StreamBufferCompID ] GetInterface $xilinx::Prjrep::IStreamID ]
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "0"
$opts_stream WriteString "0"
$opts_stream WriteString "3"
$opts_stream WriteString "1"
$opts_stream WriteString "1"
$opts_stream WriteString "1"
$opts_stream WriteString "2"
$opts_stream WriteString "5"
$opts_stream WriteString "x359.syr"
$opts_stream WriteString "x359_map.mrp"
$opts_stream WriteString "x359.bit"
$opts_stream WriteString "x359.par"
$opts_stream WriteString "x359_pad.txt"
$opts_stream WriteString "7"
$opts_stream WriteString "x359_guide.ncd"
$opts_stream WriteString "x359_tf.map_tfw"
$opts_stream WriteString "x359_tf.timesim_tfw"
$opts_stream WriteString "x359_tf.translate_tfw"
$opts_stream WriteString "xpower.vcd"
$opts_stream WriteString "xpower.vcd"
$opts_stream WriteString "./xst"
$opts_stream WriteString "1"
RestoreSourceControlOptions "$project_file" $opts_stream
Release $opts_stream
if { $srcctrl_comp != 0 } {
set i_prjref [ $srcctrl_comp GetInterface $::xilinx::Dpm::IProjectHelperReferenceID ]
$i_prjref Set iProjHelper
} elseif {$iProjHelper != 0} {
$iProjHelper Close
}
Release $iProjHelper
# return back
cd $old_working_dir
}
x359_map.mrp 0 → 100644
View file @ 1727b764
This source diff could not be displayed because it is too large. You can view the blob instead.
x359_pad.txt 0 → 100644
View file @ 1727b764
Release 12.3 - par M.70d (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Jan 12 13:54:10 2012
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: x359_map.ncd
OUTPUT FILE: x359_pad.txt
PART TYPE: xc3s1200e
SPEED GRADE: -4
PACKAGE: ft256
Pinout by Pin Number:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction |IO Standard |IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | |
|A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | |
|A4 | |DIFFS |IO_L17N_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|A5 |PX_DCLK3 |IOB |IO_L17P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | |
|A7 |PXD3<4> |IBUF |IO |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|A8 |CLK0 |IBUF |IP_L10P_0/GCLK8 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|A9 |PXD3<9> |IBUF |IO_L09N_0/GCLK7 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|A10 |PX_SCL3 |IOB |IO_L09P_0/GCLK6 |BIDIR |LVCMOS25* |0 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | |
|A12 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|A13 |PX_HACT2 |IBUF |IO_L03N_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|A14 |PX_DCLK2 |IOB |IO_L01N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|A15 | | |TCK | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 |CNVSYNC |IOB |IO_L01P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|B2 |CNVCLK |IOB |IO_L01N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|B3 | |DIFFS |IO_L19N_0/HSWAP |UNUSED | |0 | | | | | | | | |
|B4 |AUXSDA |IOB |IO |BIDIR |LVCMOS25* |0 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B6 |PX_VACT3 |IBUF |IO |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|B7 |PXD3<5> |IBUF |IO_L13P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|B8 |CLK1 |IBUF |IP_L10N_0/GCLK9 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|B9 | | |GND | | | | | | | | | | | |
|B10 |PX_SDA3 |IOB |IO |BIDIR |LVCMOS25* |0 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|B11 |PX_ARST3 |IOB |IO_L05N_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|B12 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B13 |PX_VACT2 |IBUF |IO_L03P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|B14 |PXD2<2> |IBUF |IO_L01P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|B15 | | |TMS | | | | | | | | | | | |
|B16 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|C1 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | |
|C2 |RUN |IOB |IO_L02N_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|C3 | |DIFFM |IO_L19P_0 |UNUSED | |0 | | | | | | | | |
|C4 |AUXSCL |IOB |IO_L18N_0 |BIDIR |LVCMOS25* |0 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|C5 | |DIFFM |IO_L18P_0 |UNUSED | |0 | | | | | | | | |
|C6 |PX_HACT3 |IBUF |IO_L15P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|C7 |PXD3<3> |IBUF |IO_L13N_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|C8 |PXD3<7> |IBUF |IO_L11P_0/GCLK10 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|C9 |CLK2 |IBUF |IP_L07N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|C10 | |DIFFMI |IP_L07P_0 |UNUSED | |0 | | | | | | | | |
|C11 |PX_MRST3 |IOB |IO_L05P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|C12 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | |
|C13 |ALWAYS0 |IBUF |IP |INPUT |LVCMOS25* |0 | | |PULLDOWN |NONE | |UNLOCATED |NO |NONE |
|C14 | | |TDO | | | | | | | | | | | |
|C15 |PXD2<4> |IBUF |IO_L19N_1/LDC2 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|C16 |PXD2<3> |IBUF |IO_L19P_1/LDC1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|D1 | |DIFFM |IO_L05P_3 |UNUSED | |3 | | | | | | | | |
|D2 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|D3 | | |PROG_B | | | | | | | | | | | |
|D4 | | |VCCINT | | | | | | | |1.2 | | | |
|D5 | |DIFFMI |IP_L16P_0 |UNUSED | |0 | | | | | | | | |
|D6 | |DIFFS |IO_L15N_0 |UNUSED | |0 | | | | | | | | |
|D7 |PXD3<2> |IBUF |IO_L14N_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|D8 |PXD3<8> |IBUF |IO_L11N_0/GCLK11 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|D9 |PXD3<10> |IBUF |IO/VREF_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|D10 |PX_ARO3 |IOB |IO_L06P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|D11 | |DIFFM |IO_L04P_0 |UNUSED | |0 | | | | | | | | |
|D12 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | |
|D14 |PX_DCLK1 |IOB |IO_L18N_1/LDC0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|D15 |PX_HACT1 |IBUF |IO_L18P_1/HDC |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|D16 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | |
|E1 | |DIFFS |IO_L05N_3 |UNUSED | |3 | | | | | | | | |
|E2 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|E3 |HACT |IOB |IO_L03P_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E4 |DCLK |IBUF |IO_L03N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|E5 | | |VCCINT | | | | | | | |1.2 | | | |
|E6 | |DIFFSI |IP_L16N_0 |UNUSED | |0 | | | | | | | | |
|E7 | |DIFFM |IO_L14P_0 |UNUSED | |0 | | | | | | | | |
|E8 |PXD3<6> |IBUF |IO_L12P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|E9 |PXD3<11> |IBUF |IO_L08P_0/GCLK4 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|E10 |PXD3<0> |IBUF |IO_L06N_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|E11 | |DIFFS |IO_L04N_0 |UNUSED | |0 | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |1.2 | | | |
|E13 |PX_VACT1 |IBUF |IO_L17P_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
|E14 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|E15 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|E16 |PXD2<5> |IBUF |IO_L17N_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | |
|F2 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|F3 | |DIFFM |IO_L04P_3 |UNUSED | |3 | | | | | | | | |
|F4 |BPF |IOB |IO_L04N_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|F5 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|F8 |SENSPGM3 |IOB |IO_L12N_0 |BIDIR |LVCMOS25* |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|F9 |PXD3<1> |IBUF |IO_L08N_0/GCLK5 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|F10 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|F11 | | |GND | | | | | | | | | | | |
|F12 |PXD1<3> |IBUF |IO_L16N_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|F13 |PXD1<2> |IBUF |IO_L16P_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|F14 |PXD2<7> |IBUF |IO_L15P_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|F15 |PXD2<6> |IBUF |IO_L15N_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | |
|G1 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | |
|G2 |PXD<2> |IOB |IO_L07N_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G3 |PXD<0> |IOB |IO_L07P_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G4 |VACT |IOB |IO_L06N_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|G5 | |DIFFM |IO_L06P_3 |UNUSED | |3 | | | | | | | | |
|G6 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|G7 | | |GND | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | |
|G11 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|G12 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|G13 |PXD1<4> |IBUF |IO_L14P_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|G14 |PXD2<10> |IBUF |IO_L14N_1/A0 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|G15 |PXD2<9> |IBUF |IO_L13P_1/A2 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|G16 |PXD2<8> |IBUF |IO_L13N_1/A1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|H1 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|H2 | | |GND | | | | | | | | | | | |
|H3 | |DIFFM |IO_L09P_3/LHCLK2 |UNUSED | |3 | | | | | | | | |
|H4 |PXD<3> |IOB |IO_L09N_3/LHCLK3/IRDY2 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H5 |PXD<1> |IOB |IO_L08P_3/LHCLK0 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H6 |SCL0 |IOB |IO_L08N_3/LHCLK1 |BIDIR |LVCMOS25* |3 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|H7 | | |GND | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |GND | | | | | | | | | | | |
|H11 |PXD1<6> |IBUF |IO_L12N_1/A3/RHCLK7 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|H12 |PXD1<5> |IBUF |IO_L12P_1/A4/RHCLK6 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|H13 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | |
|H14 |PX_SCL2 |IOB |IO_L11N_1/A5/RHCLK5 |BIDIR |LVCMOS25* |1 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|H15 |PXD2<11> |IBUF |IO_L11P_1/A6/RHCLK4/IRDY1|INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|H16 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|J1 |PXD<7> |IOB |IO_L12P_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J2 |PXD<5> |IOB |IO_L10P_3/LHCLK4/TRDY2 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J3 |PXD<4> |IOB |IO_L10N_3/LHCLK5 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J4 |PXD<6> |IOB |IO_L11N_3/LHCLK7 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J5 |SDA0 |IOB |IO_L11P_3/LHCLK6 |BIDIR |LVCMOS25* |3 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|J6 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|J7 | | |GND | | | | | | | | | | | |
|J8 | | |GND | | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | |
|J11 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|J12 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|J13 |PXD1<8> |IBUF |IO_L10N_1/A7/RHCLK3/TRDY1|INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|J14 |PXD1<7> |IBUF |IO_L10P_1/A8/RHCLK2 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|J15 | | |GND | | | | | | | | | | | |
|J16 |PX_SDA2 |IOB |IO_L09N_1/A9/RHCLK1 |BIDIR |LVCMOS25* |1 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|K1 |PXD<8> |IOB |IO_L12N_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|K2 |SDA<3> |IOB |IO_L13P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|K3 |SDA<1> |IOB |IO_L13N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|K4 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|K5 |MRST |IBUF |IO_L15P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|K6 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|K7 | | |GND | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | |
|K11 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|K12 |PXD1<10> |IBUF |IO_L07N_1/A11 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|K13 |PXD1<11> |IBUF |IO_L07P_1/A12 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|K14 |PXD1<9> |IBUF |IO_L08N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|K15 |PX_ARST2 |IOB |IO_L08P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|K16 |PX_MRST2 |IOB |IO_L09P_1/A10/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | |
|L2 | |DIFFS |IO_L14N_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|L3 |PXD<9> |IOB |IO_L14P_3 |OUTPUT |LVCMOS25* |3 |2 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L4 |SDA<14> |IOB |IO_L17N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|L5 |ARST |IBUF |IO_L15N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|L6 | | |GND | | | | | | | | | | | |
|L7 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|L8 |SDD<7> |IOB |IO_L09N_2/D6/GCLK13 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|L9 | |DIFFM |IO_L13P_2/M0 |UNUSED | |2 | | | | | | | | |
|L10 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 |PX_SDA1 |IOB |IO_L05P_1 |BIDIR |LVCMOS25* |1 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|L13 |PX_SCL1 |IOB |IO_L05N_1 |BIDIR |LVCMOS25* |1 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|L14 |SENSPGM2 |IOB |IO_L06P_1 |BIDIR |LVCMOS25* |1 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|L15 |PX_ARO2 |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
|M1 |SDA<2> |IOB |IO_L16P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|M2 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|M3 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|M4 |SDA<5> |IOB |IO_L17P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|M5 | | |VCCINT | | | | | | | |1.2 | | | |
|M6 |SDRAS |IOB |IO_L05P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M7 |SDWE |IOB |IO |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M8 |SDLDM |IOB |IO_L09P_2/D7/GCLK12 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M9 |SDD<6> |IOB |IO_L13N_2/DIN/D0 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|M10 |SDD<10> |IOB |IO_L15N_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|M11 | |DIFFSI |IP_L17N_2 |UNUSED | |2 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|M14 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|M16 |PXD2<0> |IBUF |IO_L04N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|N1 |SDA<10> |IOB |IO_L16N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|N2 |ARO |IBUF |IP/VREF_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|N3 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|N4 | | |VCCINT | | | | | | | |1.2 | | | |
|N5 |SDA<8> |IOB |IO_L03N_2/MOSI/CSI_B |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|N6 |SDCLKE |IOB |IO_L05N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|N7 |SDCAS |IOB |IO_L07P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|N8 |LDQS |IOB |IO_L10P_2/D4/GCLK14 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N9 |SDD<5> |IOB |IO_L12N_2/D1/GCLK3 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N10 |SDD<3> |IOB |IO_L15P_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N11 | |DIFFMI |IP_L17P_2 |UNUSED | |2 | | | | | | | | |
|N12 |SDD<2> |IOB |IO_L18N_2/A20 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N13 | | |VCCINT | | | | | | | |1.2 | | | |
|N14 |PX_ARST1 |IOB |IO_L03P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|N15 |PX_MRST1 |IOB |IO_L03N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|N16 |PXD2<1> |IBUF |IO_L04P_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P1 |SDA<0> |IOB |IO_L18N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|P2 |SDA<13> |IOB |IO_L18P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|P3 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|P4 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|P5 |SDA<7> |IOB |IO_L03P_2/DOUT/BUSY |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P6 |SDA<11> |IOB |IO_L06N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P7 |SDA<12> |IOB |IO_L07N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P8 |UDQS |IOB |IO_L10N_2/D3/GCLK15 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P9 |SDD<8> |IOB |IO_L12P_2/D2/GCLK2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P10 |SDD<9> |IOB |IO_L14P_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P11 |SDD<11> |IOB |IO_L16N_2/A22 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P12 |SDD<12> |IOB |IO_L18P_2/A21 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P13 | |IOB |IO/VREF_2 |VREF Required| |2 | | | | |1.25 | | | |
|P14 |SDD<15> |IOB |IO_L20P_2/VS0/A17 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P15 |PX_ARO1 |IOB |IO_L02N_1/A13 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |YES |NONE |
|P16 |SENSPGM1 |IOB |IO_L02P_1/A14 |BIDIR |LVCMOS25* |1 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|R1 |SDNCLK |DIFFS |IO_L19N_3 |OUTPUT |DIFF_SSTL2_I|3 | | |NONE** | | |LOCATED |NO |NONE |
|R2 |SDCLK |DIFFM |IO_L19P_3 |OUTPUT |DIFF_SSTL2_I|3 | | |NONE** | | |LOCATED |NO |NONE |
|R3 |SDCLK_FB |DIFFSI |IP_L02N_2 |INPUT |DIFF_SSTL2_I|2 | | | |NONE | |LOCATED |NO |NONE |
|R4 | |IOB |IO/VREF_2 |VREF Required| |2 | | | | |1.25 | | | |
|R5 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|R6 |SDA<9> |IOB |IO_L06P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|R7 | |DIFFMI |IP_L08P_2 |UNUSED | |2 | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | |
|R9 | |DIFFSI |IP_L11N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
|R10 | |DIFFS |IO_L14N_2/VREF_2 |VREF Required| |2 | | | | |1.25 | | | |
|R11 |SDD<4> |IOB |IO_L16P_2/A23 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R12 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|R13 |SDD<13> |IOB |IO_L19N_2/VS1/A18 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R14 |SDD<0> |IOB |IO_L20N_2/CCLK |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R15 |PXD1<1> |IBUF |IO_L01N_1/A15 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|R16 |PXD1<0> |IBUF |IO_L01P_1/A16 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|T1 | | |GND | | | | | | | | | | | |
|T2 | |IBUF |IP |UNUSED | |2 | | | | | | | | |
|T3 |SDNCLK_FB |DIFFMI |IP_L02P_2 |INPUT |DIFF_SSTL2_I|2 | | | |NONE | |LOCATED |NO |NONE |
|T4 |SDA<4> |IOB |IO_L04P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T5 |SDA<6> |IOB |IO_L04N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | |
|T7 | |DIFFSI |IP_L08N_2/VREF_2 |VREF Required| |2 | | | | |1.25 | | | |
|T8 |SDUDM |IOB |IO/D5 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T9 | |DIFFMI |IP_L11P_2/RDWR_B/GCLK0 |UNUSED | |2 | | | | | | | | |
|T10 | |IOB |IO/M1 |UNUSED | |2 | | | | | | | | |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | |
|T12 |SDD<1> |IOB |IO |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|T13 |SDD<14> |IOB |IO_L19P_2/VS2/A19 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|T14 | |IBUF |IP |UNUSED | |2 | | | | | | | | |
|T15 | | |DONE | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
x359_sim.sh 0 → 100755
View file @ 1727b764
#!/bin/bash
#XILINX=/home/andrey/Xilinx91i
#modified version
#XILINX=/home/andrey/xil91
#echo "$XILINX/verilog/src/unisims"
#echo iverilog -v -o x359.vvp -Dlegacy_model -s x359_tf -s glbl \
#-y $XILINX/verilog/src/unisims \
#x359_1.tf \
#x359.v \
#i2csbr.v \
#glbl.v
UNISIMS="../unisims"
rm -vf x359_sim.lxt
rm -vf x359.vvp
iverilog -v -o x359.vvp -Dlegacy_model -s x359_tf -s glbl \
-y $UNISIMS \
x359.tf \
x359.v \
i2csbr.v \
ddr.v \
clkios353.v \
sdram_phase.v \
dcm_phase.v \
ioports353.v \
sync_frames.v \
mcontr359.v \
mcontr_cmd.v \
mcontr_arbiter.v \
mcontr_refresh.v \
mcontr_line_wr.v \
mcontr_line_rd.v \
channel_wr.v \
channel_rd.v \
sensor_phase359.v \
sensor_phase359_vact.v \
channel_rd_short.v \
macros353.v \
sensor12bits.v \
glbl.v
vvp -v x359.vvp -lxt2 || { echo "vvp failed"; exit 1; }
#
gtkwave x359_sim.lxt x359.sav
#-y$XILINX/verilog/src/simprims
#-y$XILINX/verilog/src/unisims
exit 0
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