pax_global_header 0000666 0000000 0000000 00000000064 12771526326 0014525 g ustar 00root root 0000000 0000000 52 comment=b4eb8e5632de2b54a4872cc6892094d518621e17
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/ 0000775 0000000 0000000 00000000000 12771526326 0017030 5 ustar 00root root 0000000 0000000 x359-b4eb8e5632de2b54a4872cc6892094d518621e17/.gitignore 0000664 0000000 0000000 00000000674 12771526326 0021027 0 ustar 00root root 0000000 0000000 unisims
vivado_*
syntax_*
simulation/*
simulation_data/*
quartus_logs/ *
www/*
constraints/*
ise_*
attic/*
hardware_tests/*
IVERILOG_INCLUDE.v
*DEBUG_VDT*
*.kate-swp
*.old
*.new
*.bad
*.pyc
*.pickle
*.tmp
debug/*
html/*
man/*
.project
.pydevproject
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
workingSet.psf
*.fst
cocotb/Makefile
cocotb/sim_build
cocotb/results.xml
*.directory
/html.tar.gz
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/.settings/ 0000775 0000000 0000000 00000000000 12771526326 0020746 5 ustar 00root root 0000000 0000000 x359-b4eb8e5632de2b54a4872cc6892094d518621e17/.settings/com.elphel.vdt.FPGA_project.prefs 0000664 0000000 0000000 00000000672 12771526326 0027100 0 ustar 00root root 0000000 0000000 FPGA_project_@_ImplementationTopFile=x359.v
FPGA_project_@_SimulationTopFile=x359.tf
FPGA_project_@_SimulationTopModule=testbench359
FPGA_project_@_part=xc3s1200eft256-4
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/.settings/com.elphel.vdt.prefs 0000664 0000000 0000000 00000000227 12771526326 0024632 0 ustar 00root root 0000000 0000000 com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/Makefile 0000664 0000000 0000000 00000001224 12771526326 0020467 0 ustar 00root root 0000000 0000000 include $(AXIS_TOP_DIR)/tools/build/Rules.axis
OWN = -o root -g root
DOCUMENTROOT = $(prefix)/usr/html
TESTSCRIPTS = $(DOCUMENTROOT)/359
INCLUDES = $(prefix)/usr/html/includes
INSTDOCS = 0644
PHPSCRIPTS= test_scripts/10359_controls.html \
test_scripts/10359_mem_test.php \
test_scripts/10359_modes.php \
test_scripts/phases_adjust.php \
test_scripts/reg_read.php \
test_scripts/reg_write.php \
test_scripts/sensors_init.php \
all:
install:
$(INSTALL) $(OWN) -d $(DOCUMENTROOT)
$(INSTALL) $(OWN) -d $(TESTSCRIPTS)
#install files
$(INSTALL) $(OWN) -m $(INSTDOCS) $(PHPSCRIPTS) $(TESTSCRIPTS)
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/README.md 0000664 0000000 0000000 00000000234 12771526326 0020306 0 ustar 00root root 0000000 0000000 # x359
As of now - it is just code from NC353 project with usable bitsteam. Yet to be cleaned up, and made suitable for re-compiling with the current tools
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/channel_rd.v 0000664 0000000 0000000 00000022574 12771526326 0021326 0 ustar 00root root 0000000 0000000 /*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_rd.v
*! DESCRIPTION: channel for read from sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see .
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_rd.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:09:03 dzhimiev
*! 0. based on channel0.v (theora)
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
`timescale 1 ns / 1 ps
module channel_rd (
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
start2,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
sddi, //[31:0]
rq_busy,
//SDRAM controller inteface (mcontr_line_rd)
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
obre, // output read enable, advance address
ch1a,
obdat, // [15:0] output dtata
next_line, // advance to the next scan line (and next block RAM page if needed)
ao
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input [ 11:0] ch1a;
input start;
input start2;
input rq_busy;
output rq;
output rq_urgent;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
input [31:0] sddi; // data from SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input obre; // output read enable
output[15:0] obdat; // [15:0] output dtata
input next_line;
output [10:0] ao;
wire predrun;
reg we;
reg done;
reg [10:0] a=0;
reg [2:0] rq_cnt=0;
wire init0;
reg init_pclk;
wire page_used0;
reg page_used;
reg rq;
reg rq_urgent;
reg [1:0] obpage;
reg [7:0] obaddr;
wire next_opage;
reg cs,cs0;
reg [21:0] sa=0;
reg [7:0] obre_cnt=0;
reg [4:0] len;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [7:0] ny_cnt=0;
reg [7:0] nx_cnt=0;
reg [1:0] bank=0;
assign next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
always @ (negedge clk) init_pclk <= init;
always @ (negedge clk) page_used <= !init_pclk && next_opage;
always @ (negedge clk) begin
if (init_pclk | next_opage) obre_cnt[7:0] <= 0;
else if (obre) obre_cnt[7:0] <= obre_cnt[7:0] + 1;
end
//wire switch_order=0;
always @ (negedge clk) begin
if (init) rq_cnt <= 0;
else if (start2)
if (rq_busy) rq_cnt <= rq_cnt + 1;
else rq_cnt <= rq_cnt;
else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
rq <= enrq & (start2 | (rq & !start));
rq_urgent <= enrq & start2 & (rq_cnt==3);
end
assign ao[10:0]=a[10:0];
always @ (negedge clk) begin
we <= predrun;
done <= we & !predrun;
if (init) a[10:0] <= 11'b0;
else if (we) a[10:0] <= a[10:0] + 1;
//if (init) a[9:0] <= 10'b0;
//else if (we) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg [11:10] ch1a_d=0;
always @ (negedge clk) begin
ch1a_d[11:10] <= ch1a[11:10];
end
wire [15:0] obdat_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(obdat_0[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & !ch1a[11] & !ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & !a[10] & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_1;
RAMB16_S18_S36 i_buf_1 (
.DOA(obdat_1[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & !ch1a[11] & ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & !a[10] & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_2;
RAMB16_S18_S36 i_buf_2 (
.DOA(obdat_2[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & ch1a[11] & !ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & a[10] & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
wire [15:0] obdat_3;
RAMB16_S18_S36 i_buf_3 (
.DOA(obdat_3[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(obre & ch1a[11] & ch1a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(we & a[10] & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
assign obdat=ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
endmodule
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/channel_rd_short.v 0000664 0000000 0000000 00000014707 12771526326 0022544 0 ustar 00root root 0000000 0000000 /*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_rd_short.v
*! DESCRIPTION: channel for read from sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see .
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_rd_short.v,v $
*! Revision 1.4 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*/
`timescale 1 ns / 1 ps
module channel_rd_short (
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
start2,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
sddi, //[31:0]
rq_busy,
//SDRAM controller inteface (mcontr_line_rd)
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
obre, // output read enable, advance address
ch1a,
obdat, // [15:0] output dtata
next_line, // advance to the next scan line (and next block RAM page if needed)
ao
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input [ 11:0] ch1a;
input start;
input start2;
input rq_busy;
output rq;
output rq_urgent;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
input [31:0] sddi; // data from SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input obre; // output read enable
output[15:0] obdat; // [15:0] output dtata
input next_line;
output [10:0] ao;
wire predrun;
reg we;
reg done;
reg [10:0] a=0;
reg [2:0] rq_cnt=0;
wire init0;
reg init_pclk;
wire page_used0;
reg page_used;
reg rq;
reg rq_urgent;
reg [1:0] obpage;
reg [7:0] obaddr;
wire next_opage;
reg cs,cs0;
reg [21:0] sa=0;
reg [7:0] obre_cnt=0;
reg [4:0] len;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [7:0] ny_cnt=0;
reg [7:0] nx_cnt=0;
reg [1:0] bank=0;
assign next_opage=0;//((next_line & (obre_cnt[7:0]!=8'h0)) | ((obre_cnt[7:0]==8'hff) & obre));
always @ (negedge clk) init_pclk <= init;
always @ (negedge clk) page_used <= !init_pclk && next_opage;
always @ (negedge clk) begin
if (init_pclk | next_opage) obre_cnt[7:0] <= 0;
else if (obre) obre_cnt[7:0] <= obre_cnt[7:0] + 1;
end
//wire switch_order=0;
always @ (negedge clk) begin
if (init) rq_cnt <= 0;
else if (start2)
if (rq_busy) rq_cnt <= rq_cnt + 1;
else rq_cnt <= rq_cnt;
else if (!rq_busy & rq_cnt!=0) rq_cnt <= rq_cnt - 1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
rq <= enrq & (start2 | (rq & !start));
rq_urgent <= enrq & start2 & (rq_cnt==3);
end
assign ao[10:0]=a[10:0];
always @ (negedge clk) begin
we <= predrun;
done <= we & !predrun;
if (init) a[10:0] <= 11'b0;
else if (we) a[10:0] <= a[10:0] + 1;
//if (init) a[9:0] <= 10'b0;
//else if (we) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg [11:10] ch1a_d=0;
always @ (negedge clk) begin
ch1a_d[11:10] <= ch1a[11:10];
end
wire [15:0] obdat_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(obdat_0[15:0]), // Port A 16-bit Data Output - compressor side
.ADDRA(ch1a[9:0]),
.CLKA(!clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(sddi[31:0]), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(we) // Port B Write Enable Input
);
wire [15:0] obdat_1;
wire [15:0] obdat_2;
wire [15:0] obdat_3;
assign obdat=obdat_0;//ch1a_d[11]?(ch1a_d[10]?obdat_3:obdat_2):(ch1a_d[10]?obdat_1:obdat_0);
endmodule
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/channel_wr.v 0000664 0000000 0000000 00000020561 12771526326 0021343 0 ustar 00root root 0000000 0000000 /*
*! -----------------------------------------------------------------------------**
*! FILE NAME : channel_wr.v
*! DESCRIPTION: channel for write to sdram
*! Copyright (C) 2008 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*! This program is free software: you can redistribute it and/or modify
*! it under the terms of the GNU General Public License as published by
*! the Free Software Foundation, either version 3 of the License, or
*! (at your option) any later version.
*!
*! This program is distributed in the hope that it will be useful,
*! but WITHOUT ANY WARRANTY; without even the implied warranty of
*! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*! GNU General Public License for more details.
*!
*! You should have received a copy of the GNU General Public License
*! along with this program. If not, see .
*! -----------------------------------------------------------------------------**
*!
*! $Log: channel_wr.v,v $
*! Revision 1.5 2010/05/14 18:48:35 dzhimiev
*! 1. added hacts shifts for buffered channels
*! 2. set fixed SDRAM spaces
*!
*! Revision 1.1 2009/06/11 17:39:00 dzhimiev
*! new initial version
*! 1. simulation and board test availability
*!
*! Revision 1.1 2008/12/08 09:09:35 dzhimiev
*! 0. based on channel0.v (theora)
*! 1. set up of the data path for the transform
*! 2. 2 read and 2 write channels
*! 3. in snapshot mode - 3 frames output sequence -
*! 1st - direct
*! 2nd - stored 'direct' from the 1st buffer
*! 3rd - stored '1st buffer' from the 2nd buffer
*!
*/
`timescale 1 ns / 1 ps
module channel_wr(
clk, // SDRAM clock (negedge)
enrq, // enable channel requests (does not reset if 0)
fsa, // [11:0] frame start address (12 MSBs of SDRAM row address)
// Using the same values for channels 0..2?
init, // resets channel
x_max,
x_shift,
nx_max,
y_max,
y_shift,
ny_max,
fill_order,
// arbiter interface
start,
rq, // request - want at least one access
rq_urgent,// need 3 or 4 accesses
//SDRAM controller inteface (mcontr_line_wr)
sddo, //[31:0]
predrun,
sa, //[16:0]
len, // access length
// external interface (compressor)
ibwe, // input data write enable, advance address
ch0a,
ibdat, // [15:0] input data (1 or 2 pixels)
next_line // advance to the next scan line (and next block RAM page if needed)
);
input clk;
input enrq;
input [11:0] fsa;
input init;
input start;
output rq;
output rq_urgent;
output [31:0] sddo; //[31:0] - data to SDRAM
input predrun;
output [21:0] sa;
output [4:0] len;
input ibwe;
input [10:0] ch0a;
input [15:0] ibdat;
input next_line;
input [7:0] x_max;
input [7:0] x_shift;
input [7:0] nx_max;
input [13:0] y_max;
input [7:0] y_shift;
input [7:0] ny_max;
input fill_order;
wire next_line;
wire predrun;
reg re;
reg done;
reg [9:0] a;
reg [4:0] full_pages_in_buffer;
wire init0;
reg init_pclk;
wire page_prepared0;
reg page_prepared;
reg rq=0;
//wire rq;
reg rq_urgent;
reg [21:0] sa=0;
reg [7:0] ibwe_cnt=0;
reg [4:0] len;
wire [10:0] ch0a;
// parameter x_max=7;
// parameter x_shift=8;
// parameter nx_max=17;
// parameter y_max=4;
// parameter y_shift=4;
// parameter ny_max=9;
reg [ 6:0] x=0, nx=0;
reg [12:0] y=0, ny=0;
reg [ 7:0] ny_cnt=0;
reg [ 7:0] nx_cnt=0;
reg [1:0] bank=0;
wire next_ipage;
always @ (posedge clk)
if (init) init_pclk <= 1;
else init_pclk <= 0;
always @ (negedge clk)
if (!init_pclk & next_ipage) page_prepared <= 1;
else page_prepared <= 0;
always @ (posedge clk) begin
if (init_pclk | next_ipage) ibwe_cnt[7:0] <= 0;
else if (ibwe) ibwe_cnt[7:0] <= ibwe_cnt[7:0] + 1;
end
//assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'hff) & ibwe));
//assign next_ipage=((next_line & (ibwe_cnt[7:0]!=8'h0)) | ((ibwe_cnt[7:0]==8'h7f) & ibwe));
assign next_ipage=0;//((ibwe_cnt[5:0]==63) & ibwe);
always @ (negedge clk) begin
if (init)
full_pages_in_buffer <= 5'h0;
else if (next_line & start)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0];
else if (next_line)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] +1;
else if (start)
if (full_pages_in_buffer[4:0]!=0)
full_pages_in_buffer[4:0] <= full_pages_in_buffer[4:0] -1;
if (init) begin
sa[21:0]<= {fsa[11:0],10'b0};
nx <= 0;
nx_cnt <= 0;
ny <= 0;
ny_cnt <= 0;
{y[11:0],bank[1:0]} <= 0;
end
else if (start)
begin
// if ({y[11:0],bank[1:0]}==y_max[13:0]) begin
// {y[11:0],bank[1:0]} <= 0;
// if (nx_cnt==nx_max) begin
// nx <= 0;
// nx_cnt <= 0;
// end
// else begin
// nx <= nx + x_shift;
// nx_cnt <= nx_cnt + 1;
// end
// end
// else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
if (nx_cnt==nx_max) begin
nx <= 0;
nx_cnt <= 0;
if ({y[11:0],bank[1:0]}==y_max[13:0]) {y[11:0],bank[1:0]} <= 0;
else {y[11:0],bank[1:0]} <= {y[11:0],bank[1:0]} + 1;
end
else begin
nx <= nx + x_shift;
nx_cnt <= nx_cnt + 1;
end
//sa[21:10]<= ny[11:0] + y[11:0];
sa[21] <= sa[21];
//sa[20:10]<= ny[10:0] + y[10:0];
sa[20:10]<= {sa[20],y[9:0]};
sa[9:2] <= {1'b0,nx[6:0]};
sa[1:0] <= bank[1:0];
end
len[4:0] <= x_max;
if (!start)
rq <= ((next_line|rq) & enrq & !init);//|(rq & !start);
else
// rq <= 0;
rq <= enrq & (full_pages_in_buffer[4:0] != 1);
rq_urgent <= enrq & (full_pages_in_buffer[3] | (full_pages_in_buffer[3:0]==7)); //>=3
end
//assign rq=next_line&enrq&!init;
always @ (negedge clk) begin
re <= predrun;
done <= re & !predrun;
if (init) a[9:0] <= 10'b0;
else if (re) a[9:0] <= a[9:0] + 1;
//if (init) a[8:7] <= 2'h0;
//else if (done) a[8:7] <= a[8:7] + 1;
end
reg a_d=0;
always @ (negedge clk) begin
a_d <= a[9];
end
wire [31:0] sddo_0;
RAMB16_S18_S36 i_buf_0 (
.DOA(), // Port A 16-bit Data Output - compressor side
.DOPA(), // Port A 2-bit Parity Output
.ADDRA(ch0a[9:0]),
.CLKA(clk), // Port A Clock
.DIA(ibdat[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(ibwe & !ch0a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(sddo_0[31:0]), // Port B 32-bit Data Output - SDRAM side
.DOPB(), // Port B 4-bit Parity Output
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(32'h0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(re & !a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
wire [31:0] sddo_1;
RAMB16_S18_S36 i_buf_1 (
.DOA(), // Port A 16-bit Data Output - compressor side
.DOPA(), // Port A 2-bit Parity Output
.ADDRA(ch0a[9:0]),
.CLKA(clk), // Port A Clock
.DIA(ibdat[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(ibwe & ch0a[10]), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(sddo_1[31:0]), // Port B 32-bit Data Output - SDRAM side
.DOPB(), // Port B 4-bit Parity Output
.ADDRB(a[8:0]), // Port B 9-bit Address Input
.CLKB(!clk), // Port B Clock
.DIB(32'h0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(re & a[9]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
assign sddo[31:0]=a_d?sddo_1[31:0]:sddo_0[31:0];
endmodule
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/clkios353.v 0000664 0000000 0000000 00000032500 12771526326 0020736 0 ustar 00root root 0000000 0000000 /*
** -----------------------------------------------------------------------------**
** clkios353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002-2006 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see .
** -----------------------------------------------------------------------------**
**
** $Log: clkios353.v,v $
** Revision 1.5 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
** Revision 1.1 2009/06/11 17:39:00 dzhimiev
** new initial version
** 1. simulation and board test availability
**
** Revision 1.1 2008/12/08 09:07:57 dzhimiev
** 1. set up of the data path for the transform
** 2. 2 read and 2 write channels
** 3. in snapshot mode - 3 frames output sequence -
** 1st - direct
** 2nd - stored 'direct' from the 1st buffer
** 3rd - stored '1st buffer' from the 2nd buffer
**
** Revision 1.1 2008/04/23 01:55:49 dzhimiev
** 1. added x359 files to src lists
** 2. x359 read/write DDR
** 3. x359 3 channels mux directly to out
** 4. x359 one channel through DDR and another directly frames switching at out
**
*/
// Some placement constraints are in this file
`timescale 1 ns / 1 ps
module dcm333(
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
sdcl_fb,
xclk, // 60MHz for compressor
phsel, // additional phase control for SDRAM CLK
dcm_rst, // reset DCM phase
dcm_incdec, // variable phase control to adjust SDCLK so read DQS is aligned with sclk90/sclk270
dcm_en,
dcm_clk,
dcm_done,
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input sclk;
output xclk;
output SDCLK, SDNCLK;
input [1:0] phsel;
input sdcl_fb;
input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done;
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire isdclk0, isdclk90, isdclk180, isdclk270;
wire ixclk;
wire gsdclk; //used only for the feedback
wire isdclk;
reg dcm_done;
wire dcm_done_dcm; // single-cycle
assign isdclk=phsel[1]? (phsel[0]?isdclk270:isdclk180):(phsel[0]?isdclk90:isdclk0);
FD i_ixclk (.C(sclk), .D(!ixclk), .Q(ixclk));
BUFG i_xclk (.I(ixclk), .O(xclk));
// second - adjustable DCM. Will be adjusted so read DQS (dependent on SDCLK) will be aligned with sclk90/270
// maybe will need some delay as there is DLL in SDRAM and responce may be slow.
DCM i_dcm2(
.CLKIN (sclk),
// .CLKFB (gsdclk), // initial
.CLKFB (isdclk90),
// .CLKFB (sdcl_fb),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (dcm_clk),.DSSEN (1'b0),
.CLK0 (isdclk0),
.CLK90 (isdclk90),
.CLK180 (isdclk180),
.CLK270 (isdclk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE (dcm_done_dcm));
// s-ynthesis attribute loc of i_dcm2 is "DCM_X1Y1"
// synthesis attribute CLK_FEEDBACK of i_dcm2 is "1X"
// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm2 is "FALSE"
// synthesis attribute CLKIN_PERIOD of i_dcm2 is 8.33333
// synthesis attribute CLKOUT_PHASE_SHIFT of i_dcm2 is "VARIABLE"
// synthesis attribute DESKEW_ADJUST of i_dcm2 is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DLL_FREQUENCY_MODE of i_dcm2 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm2 is "TRUE"
// put here default phase shift ....
// synthesis attribute PHASE_SHIFT of i_dcm2 is 0
// synthesis translate_off
// defparam i_dcm2.CLK_FEEDBACK="1X";
// defparam i_dcm2.CLKIN_DIVIDE_BY_2="FALSE";
// defparam i_dcm2.CLKIN_PERIOD=8.33333;
// defparam i_dcm2.CLKOUT_PHASE_SHIFT="VARIABLE";
// defparam i_dcm2.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
// defparam i_dcm2.DLL_FREQUENCY_MODE="LOW";
// defparam i_dcm2.DUTY_CYCLE_CORRECTION="TRUE";
// defparam i_dcm2.PHASE_SHIFT=0;
// synthesis translate_on
BUFG i_gsdclk (.I(isdclk90), .O(gsdclk));
OBUFDS i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
// OBUFDS i_SDCLK (.O(SDNCLK),.OB(SDCLK),.I(!isdclk));
// make dcm_done behave as dcm_ready
always @ (posedge dcm_clk or posedge dcm_rst)
if (dcm_rst) dcm_done <= 1'b1;
else if (dcm_en) dcm_done <=1'b0;
else if (dcm_done_dcm) dcm_done <=1'b1;
endmodule
module clockios353(
CLK0, // input clock pad - 120MHz
sclk0, // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge)
/*sclk90,*/ // global clock, 120MHz, phase=90 (strobe data write to sdram)
sclk180, // global clock, 120MHz, phase=180 (just to generate DQS :-( )
sclk270, // global clock, 120MHz, phase=270 (strobe data write to sdram)
iclk0, //before BUFG
dcmrst, //reset dcm
locked, // dcm locked
status // dcm status (bit 1 - dcm clkin stopped)
);
input CLK0;
output sclk0,/*sclk90,*/sclk270,sclk180;
output iclk0;
input dcmrst; //reset dcm
output [7:0] status; // dcm status (bit 1 - dcm clkin stopped)
output locked; // dcm locked
wire iclk0;
wire isclk0, /*isclk90,*/ isclk270, isclk180;
BUFG i_iclk0 (.I(CLK0), .O(iclk0));
// DCM - just 4 phases out
DCM i_dcm1(
.CLKIN (iclk0),
.CLKFB (sclk0),
.RST (dcmrst), .PSEN (1'b0),.PSINCDEC (1'b0), .PSCLK (1'b0),.DSSEN (1'b0),
.CLK0 (isclk0),
.CLK90 (/*isclk90*/),
.CLK180 (isclk180),
.CLK270 (isclk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (status[7:0]),
.LOCKED (locked),
.PSDONE ());
// s- ynthesis attribute loc of i_dcm1 is "DCM_X0Y0"
// synthesis attribute CLK_FEEDBACK of i_dcm1 is "1X"
// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm1 is "FALSE"
// synthesis attribute CLKIN_PERIOD of i_dcm1 is 8.33333
// synthesis attribute DESKEW_ADJUST of i_dcm1 is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DLL_FREQUENCY_MODE of i_dcm1 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm1 is "TRUE"
// synthesis translate_off
defparam i_dcm1.CLK_FEEDBACK="1X";
defparam i_dcm1.CLKIN_DIVIDE_BY_2="FALSE";
defparam i_dcm1.CLKIN_PERIOD=8.33333;
defparam i_dcm1.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
defparam i_dcm1.DLL_FREQUENCY_MODE="LOW";
defparam i_dcm1.DUTY_CYCLE_CORRECTION="TRUE";
// synthesis translate_on
BUFG i_sclk0 (.I(isclk0),. O(sclk0));
// s-ynthesis attribute loc of i_sclk0 is "BUFGMUX0"
/* BUFG i_sclk90 (.I(isclk90), .O(sclk90)); */
// s-ynthesis attribute loc of i_sclk90 is "BUFGMUX1"
BUFG i_sclk180(.I(isclk180),.O(sclk180));
// s-ynthesis attribute loc of i_sclk180 is "BUFGMUX2"
BUFG i_sclk270(.I(isclk270),.O(sclk270));
// s-ynthesis attribute loc of i_sclk270 is "BUFGMUX3"
endmodule
/*
module clock_pclk( clk0, // global clock (phase =0)
CLK1, // external input clock
pclk, // global clock, sensor pixel rate
clk_en, // enable clock output to sensor
pclk_src,// [3:0] - source fror the pclk
dclk); // clock output to sensor (sync to pclk)
input CLK1,clk0,clk_en;
input [3:0] pclk_src;
output pclk,dclk;
wire ipclk,dclk,pclk;
reg clk_en_r;
IBUF i_iclk1 (.I(CLK1), .O(iclk1));
// and global clock (divided by 1, 1.5,2,...,8)
pclk_cntrl i_pclk_cntrl(.ext_clk(iclk1), // external clock, may be stopped (will wait for up to 16 clk periods?)
.clk(clk0), // always running global clock
.div(pclk_src[3:0]), // 0: q=ext_clk
// 1: q=clk - temporary made clk/1.5 - not to fry MI1300
// 2: q=clk/1.5
//...0'hf: q=clk/8
.q(ipclk)); // output clock
always @ (posedge pclk) clk_en_r<=clk_en;
assign dclk=!clk_en_r || !ipclk;
BUFG i_pclk (.I(ipclk), .O(pclk));
endmodule
// switches between external clock (no divisor)
// and global clock (divided by 1, 1.5,2,...,8)
module pclk_cntrl(ext_clk, // external clock, may be stopped (will wait for up to 16 clk periods?)
clk, // always running global clock
div, // 0: q=ext_clk
// 1: q=clk - temporary made clk/1.5 - not to fry MI1300
// 2: q=clk/1.5
//...0'hf: q=clk/8
q); // output clock
input ext_clk;
input clk;
input [3:0] div;
output q;
reg ena;
reg enb;
// reg clksel;
wire [3:0] div_p;
wire blank;
wire copy_div,blank_off;
wire a_on, a_off0, b_on, b_off;
reg [3:0] da0; // from a_start to a_on
reg [3:0] da1; // from a_on to a_off
reg [3:0] db0; // from a_start to a_on
reg [3:0] db1; // from a_on to a_off
reg a_start;
reg b_start;
reg a_off;
reg a_singleon; // a stays on for 1 cycle;
reg use_b;
wire a,b,ab;
FDE i_div_p0 (.C(clk),.CE(copy_div),.D(div[0]),.Q(div_p[0]));
FDE i_div_p1 (.C(clk),.CE(copy_div),.D(div[1]),.Q(div_p[1]));
FDE i_div_p2 (.C(clk),.CE(copy_div),.D(div[2]),.Q(div_p[2]));
FDE i_div_p3 (.C(clk),.CE(copy_div),.D(div[3]),.Q(div_p[3]));
always @ (posedge enb or posedge ext_clk) begin
if (enb) ena <=1'b0;
else ena <= (div[3:0]==4'b0);
end
always @ (posedge clk) begin
enb <= (div_p[3:0]!=4'b0);
a_off <= a_singleon?a_on:a_off0;
a_start <= blank_off || (!blank && (a_singleon?a_on:a_off0));
end
always @ (negedge clk) begin
b_start <= a_start;
use_b <= (div_p[3:0]!=4'h0) && (div_p[1:0]!=2'h3);
end
FD i_blank (.C(clk),.D((div[3:0] != div_p[3:0]) || (blank && !blank_off)),.Q(blank)); // add always blank if (div==0)? no!
SRL16 i_copy_div (.Q(copy_div),.D((div[3:0] != div_p[3:0]) && !blank), .CLK(clk), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=max (16)
SRL16 i_blank_off(.Q(blank_off),.D(copy_div), .CLK(clk), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0)); // 2
SRL16 i_a_on (.Q(a_on), .D(a_start), .CLK(clk), .A0(da0[0]), .A1(da0[1]), .A2(da0[2]), .A3(da0[3]));
SRL16 i_a_off0(.Q(a_off0),.D(a_on), .CLK(clk), .A0(da1[0]), .A1(da1[1]), .A2(da1[2]), .A3(da1[3]));
SRL16_1 i_b_on (.Q(b_on), .D(b_start), .CLK(clk), .A0(db0[0]), .A1(db0[1]), .A2(db0[2]), .A3(db0[3]));
SRL16_1 i_b_off (.Q(b_off), .D(b_on), .CLK(clk), .A0(db1[0]), .A1(db1[1]), .A2(db1[2]), .A3(db1[3]));
FD i_a (.C(clk),.D(enb && (a_on || (a && !a_off))),.Q(a));
FD_1 i_b (.C(clk),.D(use_b && (b_on || (b && !b_off))),.Q(b));
assign ab= ~(a ^ b);
assign q= (!ena || ext_clk) && (!enb || ab);
always @ (posedge clk) case (div_p[3:0])
4'h0: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end // any, not used
// 4'h1: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b1; end
4'h1: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)
4'h2: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b0; end
4'h3: begin da0<=4'h0; da1<=4'h0; a_singleon<=1'b1; end
4'h4: begin da0<=4'h3; da1<=4'h0; a_singleon<=1'b1; end
4'h5: begin da0<=4'h2; da1<=4'h1; a_singleon<=1'b0; end
4'h6: begin da0<=4'h1; da1<=4'h3; a_singleon<=1'b0; end
4'h7: begin da0<=4'h1; da1<=4'h0; a_singleon<=1'b0; end
4'h8: begin da0<=4'h6; da1<=4'h0; a_singleon<=1'b0; end
4'h9: begin da0<=4'h4; da1<=4'h3; a_singleon<=1'b0; end
4'ha: begin da0<=4'h2; da1<=4'h6; a_singleon<=1'b0; end
4'hb: begin da0<=4'h2; da1<=4'h1; a_singleon<=1'b0; end
4'hc: begin da0<=4'h9; da1<=4'h1; a_singleon<=1'b0; end
4'hd: begin da0<=4'h6; da1<=4'h5; a_singleon<=1'b0; end
4'he: begin da0<=4'h3; da1<=4'h9; a_singleon<=1'b0; end
4'hf: begin da0<=4'h3; da1<=4'h2; a_singleon<=1'b0; end
endcase
always @ (negedge clk) case (div_p[3:0])
4'h0: begin db0<=4'h0; db1<=4'h0; end
// 4'h1: begin db0<=4'h1; db1<=4'h0; end
4'h1: begin db0<=4'h0; db1<=4'h0; end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)
4'h2: begin db0<=4'h0; db1<=4'h0; end
4'h3: begin db0<=4'h0; db1<=4'h0; end
4'h4: begin db0<=4'h0; db1<=4'h0; end
4'h5: begin db0<=4'h0; db1<=4'h2; end
4'h6: begin db0<=4'h2; db1<=4'h1; end
4'h7: begin db0<=4'h0; db1<=4'h0; end
4'h8: begin db0<=4'h1; db1<=4'h1; end
4'h9: begin db0<=4'h1; db1<=4'h4; end
4'ha: begin db0<=4'h4; db1<=4'h2; end
4'hb: begin db0<=4'h0; db1<=4'h0; end
4'hc: begin db0<=4'h2; db1<=4'h2; end
4'hd: begin db0<=4'h2; db1<=4'h6; end
4'he: begin db0<=4'h6; db1<=4'h3; end
4'hf: begin db0<=4'h0; db1<=4'h0; end
endcase
endmodule
*/
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/dcm_phase.v 0000664 0000000 0000000 00000013715 12771526326 0021151 0 ustar 00root root 0000000 0000000 /*
** -----------------------------------------------------------------------------**
** dcm_phase.v
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see .
** -----------------------------------------------------------------------------**
**
** $Log: dcm_phase.v,v $
** Revision 1.2 2010/05/14 18:48:35 dzhimiev
** 1. added hacts shifts for buffered channels
** 2. set fixed SDRAM spaces
**
*/
`timescale 1 ns / 1 ps
module dcm_phase (
cclk, // command clock for shift
wcmd, // decoded address - enables wclk
cmd, // CPU write data [3:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// 4 - incr pahse90
// 8 - decrease phase90
// c - reset phase90
iclk, // DCM input clock
clk_fb, // feed back clock
clk0, // global output clock, phase 0
clk90, // global output clock, phase 90
clk180, // global output clock, phase 180
clk270, // global output clock, phase 270
dcm_phase, // current DCM phase (small steps)
dcm_phase_90,// current DCM quarter (90 degrees steps)
dcm_done, // DCM command done
dcm_status, // DCM status (bit 1 - dcm clkin stopped)
dcm_locked // DCM "Locked" pin
);
parameter NO_SHIFT90=0; //wanted to choose between clk0 BUFGs
input cclk;
input wcmd;
input [ 3:0] cmd;
input iclk;
input clk_fb;
output clk0;
output clk90;
output clk180;
output clk270;
output [8:0] dcm_phase;
output [1:0] dcm_phase_90;
output dcm_done;
output [7:0] dcm_status;
output dcm_locked;
reg dcm_rst=0;
wire dcm_rst_cmd;
reg [2:0] dcm_drst=0;
reg [2:0] dcm_reset_done=0;
wire dcm_done_dcm;
reg dcm_en=0;
reg dcm_incdec=0;
reg [8:0] phase_reg=0;
reg [1:0] phase90_reg=0;
reg dcm_done=0;
assign dcm_phase[8:0] = phase_reg[8:0];
assign dcm_phase_90[1:0] = NO_SHIFT90? 0 : phase90_reg[1:0];
FD i_dcm_rst_cmd(.Q(dcm_rst_cmd), .D((wcmd && (cmd[1:0] == 2'b11)) || (dcm_rst_cmd && !dcm_drst[2])), .C(cclk));
// shift commands are synchronous to the command clock
always @ (posedge cclk) begin
dcm_reset_done[2:0] <= {dcm_reset_done[1] & ~dcm_reset_done[0], dcm_reset_done[0], dcm_rst}; // sync to cclkl end of dcm reset
dcm_en <= wcmd && (cmd[1]!=cmd[0]);
dcm_incdec <= wcmd && cmd[0];
if (wcmd) begin
if (cmd[0] && cmd[1]) phase_reg[8:0] <= 9'h0;
else if (cmd[0]) phase_reg[8:0] <= phase_reg[8:0] +1;
else if (cmd[1]) phase_reg[8:0] <= phase_reg[8:0] -1;
end
if (wcmd) begin
if (cmd[2] && cmd[3]) phase90_reg[1:0] <= 2'h0;
else if (cmd[2]) phase90_reg[1:0] <= phase90_reg[1:0] +1;
else if (cmd[3]) phase90_reg[1:0] <= phase90_reg[1:0] -1;
end
end
// dcm_rst is synchronous to incoming clock
always @ (posedge iclk) begin
dcm_drst[2:0] <= dcm_drst[2]? 3'b0:{dcm_drst[1], dcm_drst[0], dcm_rst_cmd};
dcm_rst <= dcm_drst[0] || dcm_drst[1] || dcm_drst[2] ;
end
// make dcm_done behave as dcm_ready
always @ (posedge cclk)
if (wcmd && |cmd[2:0]) dcm_done <= 0;
else if (dcm_done_dcm || dcm_reset_done[2]) dcm_done <= 1;
/// DCM to compensate sensor delays. Adjustment for data phase - both fine and 90-degrees, hact/vact - 90-degree steps relative to data
DCM_SP #(
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), //96Hz
.CLKOUT_PHASE_SHIFT("VARIABLE"),// Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) i_dcm_sensor(
.CLKIN (iclk),
.CLKFB (clk_fb),
.RST (dcm_rst),
.PSEN (dcm_en),
.PSINCDEC (dcm_incdec),
.PSCLK (cclk),
.DSSEN (1'b0),
.CLK0 (pre_clk0),
.CLK90 (pre_clk90), // adjust tap
.CLK180 (pre_clk180), // adjust tap
.CLK270 (pre_clk270),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (dcm_status[7:0]),
.LOCKED (dcm_locked),
.PSDONE (dcm_done_dcm)
);
wire pre_clk = phase90_reg[1]? (phase90_reg[0]? pre_clk270:pre_clk180) : (phase90_reg[0]? pre_clk90:pre_clk0);
BUFG i_clk0a (.I(NO_SHIFT90?pre_clk0:pre_clk), .O(clk0));
// BUFG i_clk0b (.I(pre_clk), .O(clk0));
BUFG i_clk90 (.I(pre_clk90), .O(clk90));
BUFG i_clk180 (.I(pre_clk180), .O(clk180));
BUFG i_clk270 (.I(pre_clk270), .O(clk270));
endmodule
x359-b4eb8e5632de2b54a4872cc6892094d518621e17/ddr.v 0000664 0000000 0000000 00000156505 12771526326 0020004 0 ustar 00root root 0000000 0000000 /****************************************************************************************
*
* File Name: ddr.v
* Version: 5.7
* Model: BUS Functional
*
* Dependencies: ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate)
*
* Limitation: - Doesn't check for 8K-cycle refresh.
* - Doesn't check power-down entry/exit
* - Doesn't check self-refresh entry/exit.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 2.1 SPH 03/19/2002 - Second Release
* - Fix tWR and several incompatability
* between different simulators
* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
* - Added tDQSH and tDQSL timing checks.
* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
* - Changed Dq_buf size to [15:0]
* 5.0 JMK 06/16/2004 - Added read to write checking.
* - Added read with precharge truncation to write checking.
* - Added associative memory array to reduce memory consumption.
* - Added checking for required DQS edges during write.
* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
* - Fixed wdqs_valid window.
* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
* - Added tRFC checking during Load Mode and Precharge.
* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
* JMK 02/11/2005 - Changed the display format for numbers to hex.
* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
* - Renamed parameters file with .vh extension.
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1 ns / 1 ps
module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
`include "ddr_parameters.v"
// Port Declarations
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
input [ADDR_BITS - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [DM_BITS - 1 : 0] Dm;
// Internal Wires (fixed width)
wire [15 : 0] Dq_in;
wire [1 : 0] Dqs_in;
wire [1 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [15 : 0] dq_rise;
reg [1 : 0] dm_rise;
reg [15 : 0] dq_fall;
reg [1 : 0] dm_fall;
reg [3 : 0] dm_pair;
reg [15 : 0] Dq_buf;
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
reg Dqs_int;
// Dqs buffer
reg [DQS_BITS - 1 : 0] Dqs_out;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out;
// Read pipeline variables
reg Read_cmnd [0 : 6];
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg Write_cmnd [0 : 3];
reg [1 : 0] Write_bank [0 : 3];
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
// Auto precharge variables
reg Read_precharge [0 : 3];
reg Write_precharge [0 : 3];
integer Count_precharge [0 : 3];
// Manual precharge variables
reg A10_precharge [0 : 6];
reg [1 : 0] Bank_precharge [0 : 6];
reg Cmnd_precharge [0 : 6];
// Burst terminate variables
reg Cmnd_bst [0 : 6];
// Memory Banks
`ifdef FULL_MEM
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<= 2) begin
if (Debug) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end else begin
aref_count = 0;
@ (aref_count >= 2) begin
if (Debug) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end
end
end
end
end
end
end
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
mem_array[addr] = data;
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i === mem_used) begin
if (i === (1<= burst_length) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
read_precharge_truncation = 4'h0;
end
end
endtask
// Manual Precharge Pipeline
task Manual_Precharge_Pipeline;
begin
// A10 Precharge Pipeline
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = A10_precharge[4];
A10_precharge[4] = A10_precharge[5];
A10_precharge[5] = A10_precharge[6];
A10_precharge[6] = 1'b0;
// Bank Precharge Pipeline
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = Bank_precharge[4];
Bank_precharge[4] = Bank_precharge[5];
Bank_precharge[5] = Bank_precharge[6];
Bank_precharge[6] = 2'b0;
// Command Precharge Pipeline
Cmnd_precharge[0] = Cmnd_precharge[1];
Cmnd_precharge[1] = Cmnd_precharge[2];
Cmnd_precharge[2] = Cmnd_precharge[3];
Cmnd_precharge[3] = Cmnd_precharge[4];
Cmnd_precharge[4] = Cmnd_precharge[5];
Cmnd_precharge[5] = Cmnd_precharge[6];
Cmnd_precharge[6] = 1'b0;
// Terminate a Read if same bank or all banks
if (Cmnd_precharge[0] === 1'b1) begin
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
if (Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
read_precharge_truncation = 4'hF;
end
end
end
end
endtask
// Burst Terminate Pipeline
task Burst_Terminate_Pipeline;
begin
// Command Precharge Pipeline
Cmnd_bst[0] = Cmnd_bst[1];
Cmnd_bst[1] = Cmnd_bst[2];
Cmnd_bst[2] = Cmnd_bst[3];
Cmnd_bst[3] = Cmnd_bst[4];
Cmnd_bst[4] = Cmnd_bst[5];
Cmnd_bst[5] = Cmnd_bst[6];
Cmnd_bst[6] = 1'b0;
// Terminate a Read regardless of banks
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// read command pipeline
Read_cmnd [0] = Read_cmnd [1];
Read_cmnd [1] = Read_cmnd [2];
Read_cmnd [2] = Read_cmnd [3];
Read_cmnd [3] = Read_cmnd [4];
Read_cmnd [4] = Read_cmnd [5];
Read_cmnd [5] = Read_cmnd [6];
Read_cmnd [6] = 1'b0;
// read bank pipeline
Read_bank [0] = Read_bank [1];
Read_bank [1] = Read_bank [2];
Read_bank [2] = Read_bank [3];
Read_bank [3] = Read_bank [4];
Read_bank [4] = Read_bank [5];
Read_bank [5] = Read_bank [6];
Read_bank [6] = 2'b0;
// read column pipeline
Read_cols [0] = Read_cols [1];
Read_cols [1] = Read_cols [2];
Read_cols [2] = Read_cols [3];
Read_cols [3] = Read_cols [4];
Read_cols [4] = Read_cols [5];
Read_cols [5] = Read_cols [6];
Read_cols [6] = 0;
// Initialize Read command
if (Read_cmnd [0] === 1'b1) begin
Data_out_enable = 1'b1;
Bank_addr = Read_bank [0];
Cols_addr = Read_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Bank Address", $time);
endcase
end
// Toggle Dqs during Read command
if (Data_out_enable === 1'b1) begin
Dqs_int = 1'b0;
if (Dqs_out === {DQS_BITS{1'b0}}) begin
Dqs_out = {DQS_BITS{1'b1}};
end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
Dqs_out = {DQS_BITS{1'b0}};
end else begin
Dqs_out = {DQS_BITS{1'b0}};
end
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
Dqs_out = {DQS_BITS{1'bz}};
end
// Initialize dqs for Read command
if (Read_cmnd [2] === 1'b1) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_out = {DQS_BITS{1'b0}};
end
end
// Read latch
if (Data_out_enable === 1'b1) begin
// output data
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
if (Debug) begin
$display ("At time %t READ : Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
end
end else begin
Dq_out = {DQ_BITS{1'bz}};
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Write command pipeline
Write_cmnd [0] = Write_cmnd [1];
Write_cmnd [1] = Write_cmnd [2];
Write_cmnd [2] = Write_cmnd [3];
Write_cmnd [3] = 1'b0;
// Write command pipeline
Write_bank [0] = Write_bank [1];
Write_bank [1] = Write_bank [2];
Write_bank [2] = Write_bank [3];
Write_bank [3] = 2'b0;
// Write column pipeline
Write_cols [0] = Write_cols [1];
Write_cols [1] = Write_cols [2];
Write_cols [2] = Write_cols [3];
Write_cols [3] = {COL_BITS{1'b0}};
// Initialize Write command
if (Write_cmnd [0] === 1'b1) begin
Data_in_enable = 1'b1;
Bank_addr = Write_bank [0];
Cols_addr = Write_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Row Address", $time);
endcase
end
// Write data
if (Data_in_enable === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
if (~&dm_fall) begin
if (Debug) begin
$display ("At time %t WRITE: Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
if (~&dm_rise) begin
if (Debug) begin
$display ("At time %t WRITE: Bank = %x, Row = %x, Col = %x, Data = %x", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $time;
2'd1 : WR_chk1 = $time;
2'd2 : WR_chk2 = $time;
2'd3 : WR_chk3 = $time;
default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
endcase
// tWTR check
if (Read_enable === 1'b1) begin
$display ("At time %t ERROR: tWTR violation during Read", $time);
end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. BL/2 cycles after command
if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Read_precharge[0] = 1'b0;
end
end
if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Read_precharge[1] = 1'b0;
end
end
if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Read_precharge[2] = 1'b0;
end
end
if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Read_precharge[3] = 1'b0;
end
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Write_precharge[0] = 1'b0;
end
end
if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Write_precharge[1] = 1'b0;
end
end
if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Write_precharge[2] = 1'b0;
end
end
if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Write_precharge[3] = 1'b0;
end
end
end
endtask
// DLL Counter
task DLL_Counter;
begin
if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
DLL_count = DLL_count + 1;
if (DLL_count >= 200) begin
DLL_done = 1'b1;
end
end
end
endtask
// Control Logic
task Control_Logic;
begin
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t AREF : Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
end
// LMR/EMR to Auto Refresh
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
if (!no_halt) $stop (0);
end else begin
aref_count = aref_count + 1;
RFC_chk = $time;
end
end
// Extended Mode Register
if (Ext_mode_enable === 1'b1) begin
if (Debug) begin
$display ("At time %t EMR : Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
if (!no_halt) $stop (0);
end else begin
if (Addr[0] === 1'b0) begin
DLL_enable = 1'b1;
if (Debug) begin
$display ("At time %t EMR : Enable DLL", $time);
end
end else begin
DLL_enable = 1'b0;
if (Debug) begin
$display ("At time %t EMR : Disable DLL", $time);
end
end
MRD_chk = $time;
end
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (Debug) begin
$display ("At time %t LMR : Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
end else begin
// Register Mode
Mode_reg = Addr;
// DLL Reset
if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
DLL_reset = 1'b1;
DLL_done = 1'b0;
DLL_count = 0;
end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
$display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
$display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("At time %t LMR : Burst Length = 2", $time);
3'b010 : $display ("At time %t LMR : Burst Length = 4", $time);
3'b011 : $display ("At time %t LMR : Burst Length = 8", $time);
default : $display ("At time %t ERROR: Burst Length not supported", $time);
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("At time %t LMR : CAS Latency = 2", $time);
3'b110 : $display ("At time %t LMR : CAS Latency = 2.5", $time);
3'b011 : $display ("At time %t LMR : CAS Latency = 3", $time);
default : $display ("At time %t ERROR: CAS Latency not supported", $time);
endcase
// Record current tMRD time
MRD_chk = $time;
end
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
end
// Display Debug Message
if (Debug) begin
$display ("At time %t ACT : Bank = %x, Row = %x", $time, Ba, Addr);
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
end
// LMR/EMR to Activate
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
end
// AutoRefresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
if (!no_halt) $stop (0);
end else begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk0 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk0 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $time;
RCD_chk0 = $time;
RAS_chk0 = $time;
RAP_chk0 = $time;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk1 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk1 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $time;
RCD_chk1 = $time;
RAS_chk1 = $time;
RAP_chk1 = $time;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk2 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %x", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk2 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %x", $time, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $time;
RCD_chk2 = $time;
RAS_chk2 = $time;
RAP_chk2 = $time;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk3 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk3 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $time;
RCD_chk3 = $time;
RAS_chk3 = $time;
RAP_chk3 = $time;
end
// Record variable for checking violation
RRD_chk = $time;
Prev_bank = Ba;
read_precharge_truncation[Ba] = 1'b0;
end
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
end
// LMR/EMR to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Precharge", $time);
end
// AutoRefresh to Precharge
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Precharge", $time);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge Bank
if ($time - RAS_chk0 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk0 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk1 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk2 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk3 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Prech_count is to make sure we have met part of the initialization sequence
Prech_count = Prech_count + 1;
// Pipeline for READ
A10_precharge [cas_latency_x2] = Addr[10];
Bank_precharge[cas_latency_x2] = Ba;
Cmnd_precharge[cas_latency_x2] = 1'b1;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display Debug Message
if (Debug) begin
$display ("At time %t BST : Burst Terminate",$time);
end
if (Data_in_enable === 1'b1) begin
// Illegal to burst terminate a Write
$display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
if (!no_halt) $stop (0);
end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
// Illegal to burst terminate a Read with Auto Precharge
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
end else begin
// Burst Terminate Command Pipeline for Read
Cmnd_bst[cas_latency_x2] = 1'b1;
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
end
// Check for DLL reset before Read
if (DLL_reset === 1 && DLL_done === 0) begin
$display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
end
// Display Debug Message
if (Debug) begin
$display ("At time %t READ : Bank = %x, Col = %x", $time, Ba, {Addr [11], Addr [9 : 0]});
end
// Terminate a Write
if (Data_in_enable === 1'b1) begin
Data_in_enable = 1'b0;
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Read", $time);
end
// Activate to Read with Auto Precharge
if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
$display ("At time %t ERROR: tRAP violation during Read", $time);
end
// Interrupt a Read with Auto Precharge (same bank only)
if (Read_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Read_precharge [Ba]= 1'b0;
end
end
// Activate to Read
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Read", $time);
if (!no_halt) $stop (0);
end else begin
// CAS Latency pipeline
Read_cmnd[cas_latency_x2] = 1'b1;
Read_bank[cas_latency_x2] = Ba;
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
if (!no_halt) $stop (0);
end
// display debug message
if (Debug) begin
$display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Activate to Write
if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Write to Bank %x", $time, Ba);
end
// Read to Write
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
if (Data_out_enable || read_precharge_truncation) begin
$display("At time %t ERROR: Read to Write violation", $time);
end
end
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Write_precharge [Ba]= 1'b0;
end
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Write", $time);
if (!no_halt) $stop (0);
end else begin
// Pipeline for Write
Write_cmnd [3] = 1'b1;
Write_bank [3] = Ba;
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
end
endtask
task check_neg_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i