...
 
Commits (8)
......@@ -52,7 +52,7 @@
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150728152838290.log</location>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150729134023977.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
......@@ -72,7 +72,7 @@
<link>
<name>ise_state/x353-synth.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150728152838290.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150729134023977.tgz</location>
</link>
</linkedResources>
</projectDescription>
com.elphel.store.context.iverilog=iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_117_GTKWaveSavFile<-@\#\#@->iverilog_96_Param_Exe<-@\#\#@->iverilog_97_VVP_Exe<-@\#\#@->iverilog_98_GtkWave_Exe<-@\#\#@->iverilog_108_ShowNoProblem<-@\#\#@->iverilog_111_SaveLogsPreprocessor<-@\#\#@->iverilog_112_SaveLogsSimulator<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_117_GTKWaveSavFile<-@\#\#@->iverilog_96_Param_Exe<-@\#\#@->iverilog_97_VVP_Exe<-@\#\#@->iverilog_98_GtkWave_Exe<-@\#\#@->iverilog_108_ShowNoProblem<-@\#\#@->iverilog_111_SaveLogsPreprocessor<-@\#\#@->iverilog_112_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->
eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
iverilog_103_IncludeDir=${verilog_project_loc}/ddr<-@\#\#@->
iverilog_104_ExtraFiles=glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/ddr<-@\#\#@->
iverilog_108_ShowNoProblem=true
iverilog_109_ShowNoProblem=true
iverilog_111_SaveLogsPreprocessor=true
iverilog_112_SaveLogsSimulator=true
iverilog_114_SaveLogsSimulator=true
iverilog_117_GTKWaveSavFile=${verilog_project_loc}/x353_1.sav
iverilog_96_Param_Exe=/usr/local/bin/iverilog
iverilog_97_VVP_Exe=/usr/local/bin/vvp
......
......@@ -668,5 +668,23 @@ assign conv20_pre_first_out= conv18_pre_first_out;
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
`ifdef SIMULATION
reg [8:0] sim_dout_cntr;
reg sim_dav;
//converter_type_r
always @(posedge clk) begin
if ( inc_sdrama && ! sim_dav) $display("CMPRS INPUT converter type= %x @ %t",converter_type_r, $time);
sim_dav <= inc_sdrama;
if (!sim_dav) sim_dout_cntr <= 0;
else sim_dout_cntr <= sim_dout_cntr + 1;
if (sim_dav) begin
$display("CMPRS INPUT %x:%x @ %t",sim_dout_cntr, di, $time);
end
end
`endif
endmodule
......@@ -658,16 +658,15 @@ end
// assign p2b_all = addsub2b_comp * memory2a[15:0];
// assign p3b_all = addsub3b_comp * memory3a[15:0];
// assign p4b_all = addsub4b_comp * memory4a[15:0];
///AF2015:
// assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
// assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
// assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
// assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
assign p1b_all = addsub1b_comp * memory1a;
assign p2b_all = addsub2b_comp * memory2a;
assign p3b_all = addsub3b_comp * memory3a;
assign p4b_all = addsub4b_comp * memory4a;
assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
// assign p1b_all = addsub1b_comp * memory1a;
// assign p2b_all = addsub2b_comp * memory2a;
// assign p3b_all = addsub3b_comp * memory3a;
// assign p4b_all = addsub4b_comp * memory4a;
always @ (posedge clk)
begin
......
This diff is collapsed.
......@@ -229,6 +229,7 @@ module sensorpix( pclk, // clock (==pclk)
assign interp_data[9:0] = table_base_r[9:0]+table_mult_r[17:8]+table_mult_r[7]; //round
assign cdata[7:0] = interp_data[9:2]; //truncate
reg [7:0] pd_lenscorr_out_d2; // AF2015
always @ (posedge pclk) begin
table_base[9:0] <= table_base_w[9:0];
table_diff[10:0] <= table_diff_w[7]?
......@@ -236,6 +237,7 @@ module sensorpix( pclk, // clock (==pclk)
{{4{table_diff_w[6]}},table_diff_w[6:0]};
/// dsat_r[7:0] <= dsat[7:0];
pd_lenscorr_out_d[7:0] <= pd_lenscorr_out[7:0];
pd_lenscorr_out_d2 <= pd_lenscorr_out_d; // AF2015 - one more cycle delay
table_mult_r[17:7] <= table_mult[17:7];
table_base_r[ 9:0] <= table_base[ 9:0];
end
......@@ -244,7 +246,8 @@ module sensorpix( pclk, // clock (==pclk)
MULT18X18 i_table_mult (
.P(table_mult), // 36-bit multiplier output
.A({{7{table_diff[10]}},table_diff[10:0]}), // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input
// .B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d2[7:0]}) // 18-bit multiplier input // AF2015 - one more cycle delay
);
......@@ -360,7 +363,8 @@ module sensorpix( pclk, // clock (==pclk)
/// NOTE: adding 5 cycles here
SRL16 i_hact_dly3 (.Q(hact_dly3), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(pclk), .D(hact_m)); // dly=2+1+5
SRL16 i_en_out (.Q(en_out), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(en)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
//AF2015 SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
assign incbwa= (dwe && (wa[7:0]==8'hff)) || (|wa[7:0] && !hact_out);
always @ (posedge pclk) begin
wpage <= incbwa;
......@@ -419,13 +423,25 @@ module sensorpix( pclk, // clock (==pclk)
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b1) // Port B Write Enable Input
);
/// AF2015 *************** Fixing old bug - moved outside ******************
/*
reg [1:0] newline_d;
reg [1:0] linerun_d;
always @ (posedge pclk) begin
newline_d <= {newline_d[0],hact & ~hact_d[0]};
linerun_d <= {linerun_d[0],hact_d[1]};
end
*/
lens_flat i_lens_flat(.sclk(sclk), /// system clock @negedge
.wen(we_lensff), /// write LSW from di
.di(wd[15:0]), /// [15:0] data in
.pclk(pclk), /// pixel clock (@pclk)
.fstart(en && !en_d), /// frame start - single clock (will have frame latency as coefficients are written after the fstart)
.newline(hact & ~hact_d[0]), /// start of scan line - ahead of linerun
// .newline(newline_d[1]), /// start of scan line - ahead of linerun
.linerun(hact_d[1]), /// active pixel output - latency will be = 3 clocks
// .linerun(linerun_d[1]), /// active pixel output - latency will be = 3 clocks
.bayer(bayer[1:0]),
.pixdi(pd_lenscorr_in[15:0]), /// pixel data in,16 bit (normal data is positive, 15 bits)
.pixdo(pd_lenscorr_out[15:0]) /// pixel data out, same format as input
......
......@@ -976,8 +976,14 @@ rtc353 i_rtc353 (.mclk(sclk0), // system clock (negedge)
.psec(psec[31:0]), // [31:0] seconds counter output
.usec(running_usec[19:0]), // [19:0] running usec output
.sec(running_sec[31:0])); //[31:0] running seconds counter output
// AF2015 - delaying to match
reg ihact_d;
reg ihact_ts_d;
always @ (posedge pclk) begin
ihact_d <= ihact;
ihact_ts_d <= ihact_ts;
end
timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge)
.pre_we(da_timestamp), // 1 cycle ahead of writing data
.wd(idi[1:0]), // [31:0] data to write, valid 1 cycle after pre_we, wa
......@@ -985,7 +991,8 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge)
.pxdi(ipxd[15:0]), // [9:0] pixel data from sensor
.pxdo(ipxd_ts[15:0]), // [9:0] data to replace pxdi (next cycle)
.vacts(vacts_every), // vertical sync (actual sensor)
.hacti(ihact), // hact input
// .hacti(ihact), // hact input
.hacti(ihact_d), // hact input
.hacto(ihact_ts), // hact output (next cycle)
.sec(ts_sync_sec[31:0]), // [31:0] number of seconds
.usec(ts_sync_usec[19:0]), // [19:0] number of microseconds
......@@ -1305,7 +1312,9 @@ sensorpix i_sensorpix(
.hact_out(line_run),
// sensor interface
.hact(ihact_ts), // line active
//AF2015 .hact(ihact_ts), // line active
.hact(ihact_ts_d), // line active
.pxd(ipxd_ts[15:0]), // [9:0] - 10 bit pixel data
// channel 0 (data->SDRAM) interface
.dwe(sens_we), // WE to SDRAM buffer
......
This diff is collapsed.
......@@ -35,7 +35,8 @@ module testbench353();
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
parameter FPGA_XTRA_CYCLES= 1500; // 1072+;
parameter HISTOGRAM_LEFT= 0; //2; // left
parameter HISTOGRAM_TOP = 2; // top
// parameter HISTOGRAM_TOP = 2; // top
parameter HISTOGRAM_TOP = 8; // top - otherwise no time to erase
parameter HISTOGRAM_WIDTH= 6; // width
parameter HISTOGRAM_HEIGHT=6; // height
parameter CLK0_PER = 6.25; //160MHz
......@@ -48,7 +49,7 @@ module testbench353();
`include "IVERILOG_INCLUDE.v"
`else
initial $display("IVERILOG is not defined");
parameter lxtname = "x353_1.lxt";
parameter fstname = "x353_1.fst";
`endif
`ifdef SYNC_COMPRESS
......@@ -513,8 +514,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
initial begin
// $dumpfile("x353.lxt");
$dumpfile(lxtname);
// $dumpfile("x353.fst");
$dumpfile(fstname);
$dumpvars(0,testbench353); //testbench353 cannot be resolved to a signal or parameter //SuppressThisWarning Veditor
TTRIG = 1;
CLK3 = 0;
......@@ -964,7 +965,11 @@ end
cpu_wr('h4c,'h1); // time stamp mode 1 (
//AF2015 cpu_wr('h4c,'h1); // time stamp mode 1 (
cpu_wr('h4c,'h0); // time stamp mode off (not supported in 393!) (
// +++++++++++ photofinish mode ++++++++++
// init_chan (0,0,1,1,'h200000,'h07,'h1f); //
// cpu_wr('h48,'h2); // time stamp mode 2
......@@ -1113,12 +1118,16 @@ $display ("saturation=2");
`endif
/// instead of the combined command above, trying separate ones
cpu_wr('h62,'h0c000040); // quality page 0
// cpu_wr('h62,'h0c000040); // quality page 0 quantization table
cpu_wr('h62,'h0c000048); // quality page 1 quantization table
cpu_wr('h62,'h0c002200); // color - mode 1
// cpu_wr('h62,'h0c002400); // JP46 - mode 2
cpu_wr('h62,'h0c000006); // mode - single
/// cpu_wr('h62,'h0c000006); // mode - single
cpu_wr('h63,'h0c000006); // mode - single // do it one frame later?
cpu_wr('h62, 'h4e000000 | 'h4 );// bayer=0
cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
//AF2015 cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
cpu_wr('h66, 'h4e000000 | 'h5 );// bayer=1 AF2015 - make it later to compare with 393
/*
AX(0x000000): writing 0x000000 to 0x31
......@@ -1136,12 +1145,14 @@ $display ("saturation=2");
*/
cpu_wr('h62,'h31000000); // [AX] => 0x0
cpu_wr('h62,'h31080000); // [AY] => 0
// Lens flat field correction
// cpu_wr('h62,'h31000000); // [AX] => 0x0
// cpu_wr('h62,'h31080000); // [AY] => 0
cpu_wr('h62,'h31108000); // [C] => 0x8000
cpu_wr('h62,'h31200000); // [BX] => 0
cpu_wr('h62,'h31400000); // [BY] => 0
cpu_wr('h62,'h31380000); // [BX] => 0x180000; // 0
cpu_wr('h62,'h31580000); // [BY] => 0x180000; // 0
// cpu_wr('h62,'h31200000); // [BX] => 0x180000; // 0
// cpu_wr('h62,'h31400000); // [BY] => 0x180000; // 0
cpu_wr('h62,'h31608000); // [scales0] => 32768
cpu_wr('h62,'h31628000); // [scales1] => 32768
......@@ -1151,11 +1162,14 @@ $display ("saturation=2");
cpu_wr('h62,'h31690000); // [fatzero_out] => 0
cpu_wr('h62,'h316a0001); // [post_scale] => 3 - X
cpu_wr('h63,'h31020000); // [AX] => 0x20000
cpu_wr('h63,'h310a0000); // [AY] => 0x20000
// cpu_wr('h63,'h31020000); // [AX] => 0x20000
// cpu_wr('h63,'h310a0000); // [AY] => 0x20000
cpu_wr('h62,'h31020000); // [AX] => 0x20000
cpu_wr('h62,'h310a0000); // [AY] => 0x20000
cpu_wr('h64,'h31200000); // [BX] => 0x180000
cpu_wr('h64,'h31400000); // [BY] => 0x180000
// TODO: move to 'h62 (together with 393)
// cpu_wr('h64,'h31200000); // [BX] => 0x180000
// cpu_wr('h64,'h31400000); // [BY] => 0x180000
`ifdef CONTINUOUS_COMPRESSION
TEST_TITLE = "START_CONTINUOUS_COMPRESSION";
......@@ -1185,10 +1199,17 @@ task program_compressor;
*/
`ifdef CONTINUOUS_COMPRESSION
// program_compressor ('h65,0,0,0, 2, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=100?
program_compressor ('h65,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=70?
//AF2015 program_compressor ('h65,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=70?
// tile mode = 1 (center of 20x20
// program_compressor ('h65,0,0,1, 1, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 15 (jpeg), shift 0 quality=100, JPEG
// Add bayer shift to compensate for tile shift
// program_compressor ('h65,0,3,1, 1, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 15 (jpeg), shift 0 quality=100, JPEG
program_compressor ('h65,0,3,1, 1, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 15 (jpeg), shift 0 quality=70?, JPEG
`else
program_compressor ('h64,0,0,0, 2, 1,0,2); //focus mode 0 - sub dc, single, mode 7 (jp46), shift 0 quality=100?
program_compressor ('h65,0,0,0, 2, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=100?
// program_compressor ('h64,0,0,0, 2, 1,0,2); //focus mode 0 - sub dc, single, mode 7 (jp46), shift 0 quality=100?
// program_compressor ('h65,0,0,0, 2, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=100?
program_compressor ('h64,0,0,0, 2, 1,1,2); //focus mode 0 - sub dc, single, mode 7 (jp46), shift 0 quality=70?
program_compressor ('h65,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=70?
program_compressor ('h66,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 2 (jp46), shift 0 quality=70?
`endif
......