Commit fbce217a authored by Andrey Filippov's avatar Andrey Filippov
Browse files

minor code fixes to make it simulate with iverilog

parent 63198817

.project

+7 −0
Original line number Diff line number Diff line
@@ -8,4 +8,11 @@ 
	</buildSpec>

	<natures>

	</natures>

	<linkedResources>

		<link>

			<name>ise_logs/ISEPartgen.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>

		</link>

	</linkedResources>

</projectDescription>

control/camsync.v

+2 −2
Original line number Diff line number Diff line
@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge 
      if (set_period) rep_en <= !high_zero;

    end



    MSRL16 i_start_pclk16   (.Q(start_pclk16),   .A('hf), .CLK(pclk), .D(start_pclk[2]));

    MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1));

    MSRL16 i_start_pclk16   (.Q(start_pclk16),   .A(4'hf), .CLK(pclk), .D(start_pclk[2]));

    MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));



//! synchronize start from sclk to pclk    

//! Generating repetition (period should be exactly N, not N+/-1) and output pulse

coring.dat.v→coring.dat

+0 −0

File moved.

View file

ddr/ddr.v

+1 −1
Original line number Diff line number Diff line
@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); 
    assign    Dq  = Dq_out;



    // Debug message

    wire      Debug = 1'b1;

//    wire      Debug = 1'b1;



    // Timing Check

    time      MRD_chk;

extras/imu_logger.v

+2 −1
Original line number Diff line number Diff line
@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps ( 
                        .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored

                        .ra({channel[1:0],timestamp_sel[1:0]}),   // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high

                        .dout(timestamps_rdata[15:0]));// output data

wire [0:0] debug_state_unused;

rs232_rcv i_rs232_rcv (.xclk(xclk),           // half frequency (80 MHz nominal)

                       .bitHalfPeriod(bitHalfPeriod[15:0]),  // half of the serial bit duration, in xclk cycles

                       .ser_di(ser_di),              // rs232 (ttl) serial data in
@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) 
                       .ser_do(ser_do),         // serial data out(@posedge xclk) LSB first!

                       .ser_do_stb(ser_do_stb),    // output data strobe (@posedge xclk), first cycle after ser_do becomes valid

//                       .debug(debug_state[4:0]),

                       .debug(debug_state[15:12]),

                       .debug({debug_state_unused,debug_state[15:12]}),

                       .bit_dur_cntr(debug_state[31:16]),

                       .bit_cntr(debug_state[11:7])

                       );