Initial commit of the x353 files as they were in the NC353 camera codebase

control_regs.v

+/*
+** -----------------------------------------------------------------------------**
+** control_regs.v
+**
+** various control bits (what was a single control register before)
+**
+** Copyright (C) 2008 Elphel, Inc
+**
+** -----------------------------------------------------------------------------**
+**  This file is part of X353
+**  X353 is free software - hardware description language (HDL) code.
+** 
+**  This program is free software: you can redistribute it and/or modify
+**  it under the terms of the GNU General Public License as published by
+**  the Free Software Foundation, either version 3 of the License, or
+**  (at your option) any later version.
+**
+**  This program is distributed in the hope that it will be useful,
+**  but WITHOUT ANY WARRANTY; without even the implied warranty of
+**  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+**  GNU General Public License for more details.
+**
+**  You should have received a copy of the GNU General Public License
+**  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+** -----------------------------------------------------------------------------**
+**
+*/
+
+module control_regs     (sclk,    // @negedge
+                         wen,     // sync to address and d[0:15]
+                         wa,      // [1:0] register select
+                         di,      // [15:0] data in
+/// outputs
+                         bayer_phase, //[1:0]
+                         hact_regen,
+                         reset_mcontr,
+                         break_frames, /// Enable ending frame if no more data is available
+                         zoran,
+                         use_sensor_clk,
+                         xt_pol,
+                         arst,
+                         aro,
+                         encnvclk,
+                         sensor_trigger,
+                         mrst,
+                         external_timestamp, // use external timestamp if available
+                         output_timestamp,   // output timestamp, not just pulse
+                         dclkmode,
+                         pxd14,
+                         latehact, //[1:0]=dcr[22:21];//  register hact, vact N/4 Tpclk later than data (needed for MT9P001 @ 96MHz)
+                         pclksrc,  //[1:0]=dcr[25:24]; // pclk source
+                         hfc_sel,   //[2:0]=dcr[30:28];
+                         blockvsync, // block vsync from sensor to sequencers
+                         compressed_frames // 8-bit selection of which frames (modulo 8) to compress. deafaults to 'hff
+                      );   // [2:0] current frame modulo 8
+    input         sclk;
+    input         wen;
+    input  [ 1:0] wa;
+    input  [15:0] di;
+    output [ 1:0] bayer_phase; //[1:0]
+    output        hact_regen;
+    output        reset_mcontr;
+    output        break_frames; /// Enable ending frame if no more data is available
+    output        zoran;
+    output        use_sensor_clk;
+    output        xt_pol;
+    output        arst;
+    output        aro;
+    output        encnvclk;
+    output        sensor_trigger;
+    output        mrst;
+    output        external_timestamp;
+    output        output_timestamp;
+    output  [7:0] compressed_frames;
+    output        dclkmode;
+    output        pxd14;
+    output  [1:0] latehact; //[1:0]=dcr[22:21];//  register hact, vact N/4 Tpclk later than data (needed for MT9P001 @ 96MHz)
+    output  [1:0] pclksrc;  //[1:0]=dcr[25:24]; // pclk source
+    output  [2:0] hfc_sel;  //[2:0]=dcr[30:28];
+    output        blockvsync; // block vsync from sensor to sequencers
+    reg     [1:0] wend; // we delayed
+    reg     [1:0] wad;  // address delayed
+    reg     [2:0] reg_wr; // write data to registers (group 0, group1)
+    reg    [15:0] d1;
+    reg    [31:0] d2;
+    reg     [7:0] compressed_frames=8'hff; // TODO change other FDE_1 to registers
+
+    always @ (negedge sclk) begin
+      wend[1:0] <= {wend[0], wen};
+      if (wen) wad[1:0] <= wa[1:0];
+      reg_wr[2:0] <= {wend[1] & (wad[1:0]==2'h1), wend[1] & (wad[1:0]==2'h3), wend[1] & (wad[1:0]==2'h2)};
+      if (wen || wend[0]) d1[15:0] <= di[15:0];
+      if (wend[0]) d2[15: 0] <= d1[15:0];
+      if (wend[1]) d2[31:16] <= d1[15:0];
+
+    end
+    FDE_1 i_bayer_phase_0     (.C(sclk),.CE(reg_wr[0] & d2[ 2]),.D(d2[ 0]), .Q(bayer_phase[0]));
+    FDE_1 i_bayer_phase_1     (.C(sclk),.CE(reg_wr[0] & d2[ 2]),.D(d2[ 1]), .Q(bayer_phase[1]));
+    FDE_1 i_hact_regen        (.C(sclk),.CE(reg_wr[0] & d2[ 4]),.D(d2[ 3]), .Q(hact_regen));
+    FDE_1 i_reset_mcontr      (.C(sclk),.CE(reg_wr[0] & d2[ 6]),.D(d2[ 5]), .Q(reset_mcontr));
+    FDE_1 i_zoran             (.C(sclk),.CE(reg_wr[0] & d2[ 8]),.D(d2[ 7]), .Q(zoran));
+    FDE_1 i_use_sensor_clk    (.C(sclk),.CE(reg_wr[0] & d2[10]),.D(d2[ 9]), .Q(use_sensor_clk));
+    FDE_1 i_xt_pol            (.C(sclk),.CE(reg_wr[0] & d2[12]),.D(d2[11]), .Q(xt_pol));
+    FDE_1 i_arst              (.C(sclk),.CE(reg_wr[0] & d2[14]),.D(d2[13]), .Q(arst));
+    FDE_1 i_aro               (.C(sclk),.CE(reg_wr[0] & d2[16]),.D(d2[15]), .Q(aro));
+    FDE_1 i_encnvclk          (.C(sclk),.CE(reg_wr[0] & d2[18]),.D(d2[17]), .Q(encnvclk));
+    FDE_1 i_sensor_trigger    (.C(sclk),.CE(reg_wr[0] & d2[20]),.D(d2[19]), .Q(sensor_trigger));
+    FDE_1 i_break_frames      (.C(sclk),.CE(reg_wr[0] & d2[22]),.D(d2[21]), .Q(break_frames));
+     
+    FDE_1 i_mrst              (.C(sclk),.CE(reg_wr[1] & d2[ 1]),.D(d2[ 0]), .Q(mrst));
+    FDE_1 i_external_timestamp(.C(sclk),.CE(reg_wr[1] & d2[ 3]),.D(d2[ 2]), .Q(external_timestamp));
+    FDE_1 i_dclkmode          (.C(sclk),.CE(reg_wr[1] & d2[ 5]),.D(d2[ 4]), .Q(dclkmode));
+    FDE_1 i_pxd14             (.C(sclk),.CE(reg_wr[1] & d2[ 7]),.D(d2[ 6]), .Q(pxd14));
+    FDE_1 i_latehact_0        (.C(sclk),.CE(reg_wr[1] & d2[10]),.D(d2[ 8]), .Q(latehact[0]));
+    FDE_1 i_latehact_1        (.C(sclk),.CE(reg_wr[1] & d2[10]),.D(d2[ 9]), .Q(latehact[1]));
+    FDE_1 i_pclksrc_0         (.C(sclk),.CE(reg_wr[1] & d2[13]),.D(d2[11]), .Q(pclksrc[0]));
+    FDE_1 i_pclksrc_1         (.C(sclk),.CE(reg_wr[1] & d2[13]),.D(d2[12]), .Q(pclksrc[1]));
+    FDE_1 i_hfc_sel_0         (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[14]), .Q(hfc_sel[0]));
+    FDE_1 i_hfc_sel_1         (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[15]), .Q(hfc_sel[1]));
+    FDE_1 i_hfc_sel_2         (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[16]), .Q(hfc_sel[2]));
+    FDE_1 i_blockvsync        (.C(sclk),.CE(reg_wr[1] & d2[19]),.D(d2[18]), .Q(blockvsync));
+    FDE_1 i_output_timestamp  (.C(sclk),.CE(reg_wr[1] & d2[21]),.D(d2[20]), .Q(output_timestamp));
+
+    always @ (negedge sclk) begin
+      if (reg_wr[2] & d2[8]) compressed_frames[7:0] <= d2[7:0];
+    end
+    
+endmodule

coring.dat.v

+  0000  0000  1111  1111  1111  1111  2222  2222
+  2222  2222  3333  3333  3333  3333  4444  4444
+  4444  4444  5555  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+ 
+  0000  0000  1111  1111  1111  1111  2222  2222
+  2222  2222  3333  3333  3333  3333  4444  4444
+  4444  4444  5555  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+ 
+  0000  0000  1000  1111  1111  1111  2221  2222
+  2222  2222  3332  3333  3333  3333  4444  4444
+  4444  4444  5555  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  1000  1111  1111  1111  2221  2222
+  2222  2222  3332  3333  3333  3333  4444  4444
+  4444  4444  5555  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  1000  1111  1111  2211  2222
+  2222  2222  3332  3333  3333  3333  4443  4444
+  4444  4444  5554  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  0000  1000  1111  1111  2211  2222
+  2222  2222  3332  3333  3333  3333  4443  4444
+  4444  4444  5554  5555  5555  5555  6666  6666
+  6666  6666  7777  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  0000  0000  1000  1111  1111
+  2111  2222  2222  3332  3333  3333  4433  4444
+  4444  4444  5554  5555  5555  5555  6665  6666
+  6666  6666  7776  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  0000  0000  0000  1000  1111  1111
+  2111  2222  2222  3332  3333  3333  4433  4444
+  4444  4444  5554  5555  5555  5555  6665  6666
+  6666  6666  7776  7777  7777  7777  8888  8888
+  8888  8888  9999  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  0000  0000  0000  0000  1100
+  1111  1111  1111  2222  2222  3222  3333  3333
+  4444  4444  5444  5555  5555  5555  6665  6666
+  6666  6666  7776  7777  7777  7777  8887  8888
+  8888  8888  9998  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  0000  0000  0000  0000  0000  1100
+  1111  1111  1111  2222  2222  3222  3333  3333
+  4444  4444  5444  5555  5555  5555  6665  6666
+  6666  6666  7776  7777  7777  7777  8887  8888
+  8888  8888  9998  9999  9999  9999  aaaa  aaaa
+  aaaa  aaaa  bbbb  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  1110  1111  1111  1111  2221  2222  2222
+  3333  3333  4433  4444  5444  5555  5555  6665
+  6666  6666  7766  7777  7777  7777  8887  8888
+  8888  8888  9998  9999  9999  9999  aaa9  aaaa
+  aaaa  aaaa  bbba  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  1110  1111  1111  1111  2221  2222  2222
+  3333  3333  4433  4444  5444  5555  5555  6665
+  6666  6666  7766  7777  7777  7777  8887  8888
+  8888  8888  9998  9999  9999  9999  aaa9  aaaa
+  aaaa  aaaa  bbba  bbbb  bbbb  bbbb  cccc  cccc
+  cccc  cccc  dddd  dddd  dddd  dddd  eeee  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  1111  1111  1111  1111  1111  1111  2222
+  2222  2222  3332  3333  3333  4444  4444  5555
+  5555  6666  7666  7777  8877  8888  9998  9999
+  aa99  aaaa  baaa  bbbb  bbbb  bbbb  cccb  cccc
+  cccc  cccc  dddc  dddd  dddd  dddd  eeed  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  1111  1111  1111  1111  1111  1111  2222
+  2222  2222  3332  3333  3333  4444  4444  5555
+  5555  6666  7666  7777  8877  8888  9998  9999
+  aa99  aaaa  baaa  bbbb  bbbb  bbbb  cccb  cccc
+  cccc  cccc  dddc  dddd  dddd  dddd  eeed  eeee
+  eeee  eeee  ffff  ffff  ffff  ffff  ffff  ffff
+
+
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  1100  1111  1111  1111  1111  2111  2222  3222
+  3333  5444  6655  9877  cba9  feed  ffff  ffff
+
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  0000  0000  0000  0000  0000  0000  0000  0000
+  1100  1111  1111  1111  1111  2111  2222  3222
+  3333  5444  6655  9877  cba9  feed  ffff  ffff

ddr_parameters.v

+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
+    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.4; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.4; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.5; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else
+`define sg75Z                       //              Timing Parameters for -75Z (CL = 2)
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =     0.5; // tDQSS  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
+    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+//    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRC              =  63.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    20.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`endif
+`endif
+`endif
+
+    // Size Parameters based on Part Width
+
+`ifdef x4
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used
+`else
+`ifdef x8
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
+`else
+`define x16
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
+`endif
+`endif
+
+    parameter full_mem_bits    = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+//    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 12;                   // Set this parameter to control how many unique addresses are used
+
+    parameter no_halt          =       1; // If set to 1, the model won't halt on command sequence/major errors
+    parameter Debug            =       1; // Turn on debug message

dma_fifo353.v

+/*
+** -----------------------------------------------------------------------------**
+** dma_fifosync353.v
+**
+** DMA controller/fifo
+**
+** Copyright (C) 2002-2007 Elphel, Inc.
+**
+** -----------------------------------------------------------------------------**
+**  This file is part of X353
+**  X353 is free software - hardware description language (HDL) code.
+** 
+**  This program is free software: you can redistribute it and/or modify
+**  it under the terms of the GNU General Public License as published by
+**  the Free Software Foundation, either version 3 of the License, or
+**  (at your option) any later version.
+**
+**  This program is distributed in the hope that it will be useful,
+**  but WITHOUT ANY WARRANTY; without even the implied warranty of
+**  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+**  GNU General Public License for more details.
+**
+**  You should have received a copy of the GNU General Public License
+**  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+** -----------------------------------------------------------------------------**
+**
+*/
+// with long 8-cycle bursts it makes sense to move everything to internal clock domain (no need fro Gray counters)
+// uses GCLK buffer (so 2 for 2 DMA channels)
+module dma_fifo_sync (	clk,		// system clock, 120MHz? (currentle negedge used)
+						pre_wen,	// decoded addresses (valid @ negedge clk)
+						wd,		      // {enable update, pio_mode, enable channel}
+
+						dreq,		// DREQ output to CPU
+						dack, 	// DACK input from CPU
+//                  re,      // read enable (CE | OE)
+                  oe,      // just OE
+                  pioinc,  // increment buffer address in PIO mode
+						d,			// [31:0]	- data to cpu
+                  we,      // write enable (sync to posedge clk)
+                  di,      // 16-bit data to write (sync to posedge clk)
+						enabled, // channel enabled
+						real_empty
+                  ,test1,
+                  test2
+                  );	// pessimistic, with several clk delay
+
+    input			clk;
+    input			pre_wen;
+    input 	[2:0] wd; // bit2 - enable update of bits [1:0], bit 0 - enable channel, bit 1 - PIO mode
+    output			dreq;
+    input			dack;
+//    input         re;
+    input         oe;
+    input         pioinc;
+    output [31:0]	d;
+    input         we;
+    input  [15:0] di;
+	 output			enabled;
+	 output			real_empty;
+
+    output [7:0] test1;
+    output [7:0] test2;
+
+	 reg           wen;
+    wire          en;
+    reg    [9:0]  wab;      // binary write counter
+    reg    [8:0]  rab;      // binary read counter
+
+    wire          rst;
+    reg    [3:0]  empties;
+    wire          en0;
+    wire          pio, pio0; //enable pio read mode
+    
+    reg    [2:0]  di_d;
+    assign rst=!en;
+	 assign enabled=en;
+    
+	 assign real_empty=empties[3];
+    assign test1=rab[7:0];
+    assign test2=wab[7:0];
+
+    wire   swclk; // global clock, switched between OE (when DACK active) and extra pulse generated to read first word from FIFO.
+    reg    firstclk; // generated 1-clk_long pulse as a source for swclk
+    reg    written_burst; // 16 of 16-bit words are just written to FIFO
+    wire   mem_re;        // memory RE signal (alo increments counters)
+    reg    dreq;
+    reg    [1:0] burst_start_sync;  // 1 clk long pulse (clk-sync) after start of the DMA burst
+    reg    [1:0] dack_r; // synchronize to clk, dual to prevent metastability
+    reg    [9:0] infifo;    // number of words in FIFO (10 bits, to implement overflow)
+    reg          first_four; // sync to OE
+    reg    [2:0] first_four_r; // sync to clk
+    reg          nempty; // registered fifo_not_empty 
+    reg          lessthan2; // registered fifo has less than 2 words
+    assign mem_re= dreq || !dack_r[1] || (rab[2:0]!=3'b0);
+
+
+    always @ (negedge clk) begin
+      wen <= pre_wen;
+      di_d[2:0] <= wd[2:0];
+    end
+ 	 FDE_1 i_en0       (.C(clk), .D(di_d[0]), .CE(wen & di_d[2]), .Q(en0));
+ 	 FD    i_en_tig_   (.C(clk), .D(en0),          .Q(en));
+ 	 FDE_1 i_pio0      (.C(clk), .D(di_d[1]), .CE(wen & di_d[2]), .Q(pio0));
+ 	 FD    i_pio_tig_  (.C(clk), .D(pio0),            .Q(pio));
+    BUFG i_swclk (.O(swclk),.I(dack?oe:(!firstclk && !(pio && pioinc))));
+
+
+    always @ (posedge clk) begin
+      if      (rst) wab[9:0] <= 10'b0;
+      else if ( we) wab[9:0] <= wab[9:0] + 1;
+      written_burst <= we && (wab[3:0]==4'hf);
+      nempty    <= (infifo[9:0]!=10'h0);
+      lessthan2 <= (infifo[9:1]== 9'h0);
+      if (!en) infifo[9:0] <= 10'h0;
+      else if ( written_burst && !burst_start_sync[0]) infifo[9:0] <= infifo[9:0]+1;
+      else if (!written_burst &&  burst_start_sync[0]) infifo[9:0] <= infifo[9:0]-1;
+      dack_r[1:0] <= {dack_r[0], dack};
+
+      if (rst || firstclk) firstclk <= 1'b0;
+//      else if (!pio && written_burst && !dreq && !dack_r[1]) firstclk <= 1'b1; //dreq & dack_r1[1] overlap
+// don't need to add &&!burst_start_sync[1] as burst_start_sync[1] overlaps with dack_r[1]
+      else if (!pio && nempty && !dreq && !dack_r[1]) firstclk <= 1'b1; //dreq & dack_r1[1] overlap
+
+//      if (rst || ((infifo[9:0]==10'h0) && burst_start_sync[1])) dreq <= 1'b0;
+// changed to faster (registered) version. burst_start_sync[1] happens just first cycle after infifo[9:0] was decremented
+// so we need that a cycle it was >1, not !=0. We can miss increment count (written_burst), but don't bother
+// adding condition - not a great loss.
+      if (rst || (lessthan2 && burst_start_sync[1])) dreq <= 1'b0;
+      else if (firstclk)                             dreq <= 1'b1;
+      
+      burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]};
+
+      first_four_r[2:0]={first_four_r[1:0],first_four};
+      
+      
+	   empties[3:0]	<=	{4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1};
+    end
+
+    always @ (posedge rst or posedge swclk) begin
+      if (rst) rab[8:0] <= 9'h0;
+      else if (mem_re) rab[8:0] <= rab[8:0] + 1;
+      if (rst) first_four <= 1'b0;
+      else if (rab[1:0]==2'h1) first_four <= ~rab[2];
+    end
+
+
+
+   RAMB16_S18_S36 i_dmafifobuff  (
+      .DOA(),              // Port A 16-bit Data Output - FPN (sensor) side
+      .DOPA(),             // Port A 2-bit Parity Output
+      .ADDRA(wab[9:0]),    // Port A 10-bit Address Input
+//      .CLKA(!clk),         // Port A Clock
+      .CLKA(clk),          // Port A Clock
+      .DIA(di[15:0]),      // Port A 16-bit Data Input
+      .DIPA(2'b0),         // Port A 2-bit parity Input
+      .ENA(we),            // Port A RAM Enable Input
+      .SSRA(1'b0),         // Port A Synchronous Set/Reset Input
+      .WEA(1'b1),          // Port A Write Enable Input
+
+      .DOB(d),             // Port B 32-bit Data Output - SDRAM side
+      .DOPB(),             // Port B 4-bit Parity Output
+      .ADDRB(rab[8:0]),    // Port B 9-bit Address Input
+      .CLKB(swclk),        // Port B Clock
+      .DIB(32'b0),         // Port B 32-bit Data Input
+      .DIPB(4'b0),         // Port-B 4-bit parity Input
+      .ENB(mem_re),        // PortB RAM Enable Input
+      .SSRB(1'b0),         // Port B Synchronous Set/Reset Input
+      .WEB(1'b0)           // Port B Write Enable Input
+   );
+endmodule
+
+

focus_filt.dat

+   0000  0111  0444  0888  0fff  0fff  0888  0000
+   0111  0111  0444  0888  0fff  0fff  0888  0000
+   0444  0444  0888  0fff  0fff  0888  0444  0000
+   0888  0888  0fff  0fff  0888  0444  0222  0000
+   0fff  0fff  0fff  0888  0444  0222  0111  0000
+   0fff  0fff  0888  0444  0222  0111  0000  0000
+   0888  0888  0444  0222  0111  0000  0000  0000
+   0000  0000  0000  0000  0000  0000  0000  0000
+
+   0000  1111  4444  8888  ffff  ffff  8888  0000
+   1111  1111  4444  8888  ffff  ffff  8888  0000
+   4444  4444  8888  ffff  ffff  8888  4444  0000
+   8888  8888  ffff  ffff  8888  4444  2222  0000
+   ffff  ffff  ffff  8888  4444  2222  1111  0000
+   ffff  ffff  8888  4444  2222  1111  0000  0000
+   8888  8888  4444  2222  1111  0000  0000  0000
+   0000  0000  0000  0000  0000  0000  0000  0000