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Commit 8d77d7f8 authored by Andrey Filippov's avatar Andrey Filippov
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replaced attributes with parameters fro physical constraints

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.project
View file @ 8d77d7f8
...@@ -12,22 +12,22 @@ ...@@ -12,22 +12,22 @@
<link> <link>
<name>ise_logs/ISEBitgen.log</name> <name>ise_logs/ISEBitgen.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150727142725079.log</location> <location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150727191231906.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISEMap.log</name> <name>ise_logs/ISEMap.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150727164109616.log</location> <location>/home/andrey/git/x353/ise_logs/ISEMap-20150727191231906.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISENGDBuild.log</name> <name>ise_logs/ISENGDBuild.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150727164109616.log</location> <location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150727191231906.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISEPAR.log</name> <name>ise_logs/ISEPAR.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150727142725079.log</location> <location>/home/andrey/git/x353/ise_logs/ISEPAR-20150727191231906.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISEPartgen.log</name> <name>ise_logs/ISEPartgen.log</name>
...@@ -37,37 +37,37 @@ ...@@ -37,37 +37,37 @@
<link> <link>
<name>ise_logs/ISETraceMap.log</name> <name>ise_logs/ISETraceMap.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150727164109616.log</location> <location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150727191231906.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISETracePAR.log</name> <name>ise_logs/ISETracePAR.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150727142725079.log</location> <location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150727191634237.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISExst.log</name> <name>ise_logs/ISExst.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150727170341943.log</location> <location>/home/andrey/git/x353/ise_logs/ISExst-20150727191119507.log</location>
</link> </link>
<link> <link>
<name>ise_state/x353-map.tgz</name> <name>ise_state/x353-map.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150727164109616.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-map-20150727191231906.tgz</location>
</link> </link>
<link> <link>
<name>ise_state/x353-ngdbuild.tgz</name> <name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150727164109616.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150727191231906.tgz</location>
</link> </link>
<link> <link>
<name>ise_state/x353-par.tgz</name> <name>ise_state/x353-par.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-par-20150727142725079.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-par-20150727191231906.tgz</location>
</link> </link>
<link> <link>
<name>ise_state/x353-synth.tgz</name> <name>ise_state/x353-synth.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150727170341943.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-synth-20150727191119507.tgz</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
control/clkios353.v
View file @ 8d77d7f8
...@@ -121,7 +121,9 @@ endmodule ...@@ -121,7 +121,9 @@ endmodule
module clockios353( module clockios353#(
parameter IOSTANDARD = "LVCMOS33"
)(
CLK0, // input clock pad - 120MHz CLK0, // input clock pad - 120MHz
sclk0, // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge) sclk0, // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge)
/*sclk90,*/ // global clock, 120MHz, phase=90 (strobe data write to sdram) /*sclk90,*/ // global clock, 120MHz, phase=90 (strobe data write to sdram)
...@@ -143,7 +145,7 @@ module clockios353( ...@@ -143,7 +145,7 @@ module clockios353(
wire iclk0; wire iclk0;
wire isclk0, /*isclk90,*/ isclk270, isclk180; wire isclk0, /*isclk90,*/ isclk270, isclk180;
IBUFG i_iclk0 (.I(CLK0), .O(iclk0)); IBUFG #(.IOSTANDARD(IOSTANDARD)) i_iclk0 (.I(CLK0), .O(iclk0));
// DCM - just 4 phases out // DCM - just 4 phases out
DCM #( DCM #(
.CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_DIVIDE_BY_2("FALSE"),
......
control/ioports353.v
View file @ 8d77d7f8
...@@ -27,15 +27,37 @@ ...@@ -27,15 +27,37 @@
*/ */
module dmapads (dreq0,dack0,idreq0,idack0,dreq1,dack1,idreq1,idack1); module dmapads#(
parameter IOSTANDARD_SYS = "LVCMOS33",
parameter SLEW_SYS_DREQ = "SLOW",
parameter DRIVE_SYS_DREQ = 4,
parameter IBUF_DELAY_SYS_DACK = "0",
parameter IFD_DELAY_SYS_DACK = "0"
) (dreq0,dack0,idreq0,idack0,dreq1,dack1,idreq1,idack1);
output dreq0,dreq1; output dreq0,dreq1;
input dack0,dack1; input dack0,dack1;
input idreq0,idreq1; input idreq0,idreq1;
output idack0,idack1; output idack0,idack1;
OBUF i_dreq0 (.I(idreq0), .O(dreq0)); OBUF #(
IBUF i_dack0 (.I(dack0), .O(idack0)); .IOSTANDARD(IOSTANDARD_SYS),
OBUF i_dreq1 (.I(idreq1), .O(dreq1)); .DRIVE(DRIVE_SYS_DREQ),
IBUF i_dack1 (.I(dack1), .O(idack1)); .SLEW(SLEW_SYS_DREQ))
i_dreq0 (.I(idreq0), .O(dreq0));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE (IBUF_DELAY_SYS_DACK),
.IFD_DELAY_VALUE (IFD_DELAY_SYS_DACK))
i_dack0 (.I(dack0), .O(idack0));
OBUF #(
.IOSTANDARD(IOSTANDARD_SYS),
.DRIVE(DRIVE_SYS_DREQ),
.SLEW(SLEW_SYS_DREQ))
i_dreq1 (.I(idreq1), .O(dreq1));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE (IBUF_DELAY_SYS_DACK),
.IFD_DELAY_VALUE (IFD_DELAY_SYS_DACK))
i_dack1 (.I(dack1), .O(idack1));
endmodule endmodule
...@@ -54,7 +76,23 @@ module i2cpads (sda,scl,sda_o,sda_i,sda_en,scl_o,scl_i,scl_en); ...@@ -54,7 +76,23 @@ module i2cpads (sda,scl,sda_o,sda_i,sda_en,scl_o,scl_i,scl_en);
IOBUF i_scl0 (.I(scl_o), .T(!scl_en), .O(scl_i), .IO(scl)); IOBUF i_scl0 (.I(scl_o), .T(!scl_en), .O(scl_i), .IO(scl));
endmodule endmodule
module sysinterface(clk, module sysinterface #(
parameter IOSTANDARD_SYS = "LVCMOS33",
parameter SLEW_SYS = "SLOW",
parameter DRIVE_SYS = 8,
parameter IBUF_DELAY_SYS_A = "0",
parameter IFD_DELAY_SYS_A = "0",
parameter IBUF_DELAY_SYS_D = "0",
parameter IFD_DELAY_SYS_D = "0",
parameter IBUF_DELAY_SYS_WOE = "0",
parameter IFD_DELAY_SYS_WOE = "0",
parameter IBUF_DELAY_SYS_CE = "0",
parameter IFD_DELAY_SYS_CE = "0") (
clk,
drv_bus, // drive system bus (to write to system memory) drv_bus, // drive system bus (to write to system memory)
d, // 32 bit D[31:0] data pads d, // 32 bit D[31:0] data pads
oe, // OE pad oe, // OE pad
...@@ -280,10 +318,26 @@ module sysinterface(clk, ...@@ -280,10 +318,26 @@ module sysinterface(clk,
// [2] - output high 16 (8) // [2] - output high 16 (8)
assign am[7:0]= wra? as[7:0] : ia[7:0]; assign am[7:0]= wra? as[7:0] : ia[7:0];
IBUF i_oe (.I(oe), .O(ioe )); IBUF #(
IBUF i_ce (.I(ce), .O(ice )); .IOSTANDARD (IOSTANDARD_SYS),
IBUF i_ce1 (.I(ce1), .O(ice1)); .IBUF_DELAY_VALUE(IBUF_DELAY_SYS_WOE),
ipadql i_we (.g(cwr),.q(iwe),.qr(irnw),.d(we)); .IFD_DELAY_VALUE(IFD_DELAY_SYS_WOE))
i_oe (.I(oe), .O(ioe ));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE(IBUF_DELAY_SYS_CE),
.IFD_DELAY_VALUE(IFD_DELAY_SYS_CE))
i_ce (.I(ce), .O(ice ));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE(IBUF_DELAY_SYS_WOE),
.IFD_DELAY_VALUE(IFD_DELAY_SYS_WOE))
i_ce1 (.I(ce1), .O(ice1));
ipadql #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY(IBUF_DELAY_SYS_WOE),
.IFD_DELAY(IFD_DELAY_SYS_WOE))
i_we (.g(cwr),.q(iwe),.qr(irnw),.d(we));
// negative pulse - with CE (zero w.s.) - only with WE, with CE1 (EW=1) - both WE and OE // negative pulse - with CE (zero w.s.) - only with WE, with CE1 (EW=1) - both WE and OE
BUFG i_cwr (.I((ice | iwe) & (ice1 | (iwe & ioe))), .O(cwr)); BUFG i_cwr (.I((ice | iwe) & (ice1 | (iwe & ioe))), .O(cwr));
...@@ -377,19 +431,32 @@ module sysinterface(clk, ...@@ -377,19 +431,32 @@ module sysinterface(clk,
da_imu <= wr_state[0] && wnr_seq_mux && (a_pio_seq_mux[7:1]==7'h3f); // IMU control (0x7e-0x7f) da_imu <= wr_state[0] && wnr_seq_mux && (a_pio_seq_mux[7:1]==7'h3f); // IMU control (0x7e-0x7f)
end end
bpadql i_a0 (.g(cwr),.q(ia[ 0]),.qr(ial[ 0]),.io(a[ 0]),.t(!drv_bus),.d(ao[ 0])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a1 (.g(cwr),.q(ia[ 1]),.qr(ial[ 1]),.io(a[ 1]),.t(!drv_bus),.d(ao[ 1])); i_a0 (.g(cwr),.q(ia[ 0]),.qr(ial[ 0]),.io(a[ 0]),.t(!drv_bus),.d(ao[ 0]));
bpadql i_a2 (.g(cwr),.q(ia[ 2]),.qr(ial[ 2]),.io(a[ 2]),.t(!drv_bus),.d(ao[ 2])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a3 (.g(cwr),.q(ia[ 3]),.qr(ial[ 3]),.io(a[ 3]),.t(!drv_bus),.d(ao[ 3])); i_a1 (.g(cwr),.q(ia[ 1]),.qr(ial[ 1]),.io(a[ 1]),.t(!drv_bus),.d(ao[ 1]));
bpadql i_a4 (.g(cwr),.q(ia[ 4]),.qr(ial[ 4]),.io(a[ 4]),.t(!drv_bus),.d(ao[ 4])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a5 (.g(cwr),.q(ia[ 5]),.qr(ial[ 5]),.io(a[ 5]),.t(!drv_bus),.d(ao[ 5])); i_a2 (.g(cwr),.q(ia[ 2]),.qr(ial[ 2]),.io(a[ 2]),.t(!drv_bus),.d(ao[ 2]));
bpadql i_a6 (.g(cwr),.q(ia[ 6]),.qr(ial[ 6]),.io(a[ 6]),.t(!drv_bus),.d(ao[ 6])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a7 (.g(cwr),.q(ia[ 7]),.qr(ial[ 7]),.io(a[ 7]),.t(!drv_bus),.d(ao[ 7])); i_a3 (.g(cwr),.q(ia[ 3]),.qr(ial[ 3]),.io(a[ 3]),.t(!drv_bus),.d(ao[ 3]));
bpadql i_a8 (.g(cwr),.q(), .qr(), .io(a[ 8]),.t(!drv_bus),.d(ao[ 8])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a9 (.g(cwr),.q(), .qr(), .io(a[ 9]),.t(!drv_bus),.d(ao[ 9])); i_a4 (.g(cwr),.q(ia[ 4]),.qr(ial[ 4]),.io(a[ 4]),.t(!drv_bus),.d(ao[ 4]));
bpadql i_a10(.g(cwr),.q(), .qr(), .io(a[10]),.t(!drv_bus),.d(ao[10])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
bpadql i_a11(.g(cwr),.q(), .qr(), .io(a[11]),.t(!drv_bus),.d(ao[11])); i_a5 (.g(cwr),.q(ia[ 5]),.qr(ial[ 5]),.io(a[ 5]),.t(!drv_bus),.d(ao[ 5]));
bpadql i_a12(.g(cwr),.q(), .qr(), .io(a[12]),.t(!drv_bus),.d(ao[12])); bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a6 (.g(cwr),.q(ia[ 6]),.qr(ial[ 6]),.io(a[ 6]),.t(!drv_bus),.d(ao[ 6]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a7 (.g(cwr),.q(ia[ 7]),.qr(ial[ 7]),.io(a[ 7]),.t(!drv_bus),.d(ao[ 7]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a8 (.g(cwr),.q(), .qr(), .io(a[ 8]),.t(!drv_bus),.d(ao[ 8]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a9 (.g(cwr),.q(), .qr(), .io(a[ 9]),.t(!drv_bus),.d(ao[ 9]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a10(.g(cwr),.q(), .qr(), .io(a[10]),.t(!drv_bus),.d(ao[10]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a11(.g(cwr),.q(), .qr(), .io(a[11]),.t(!drv_bus),.d(ao[11]));
bpadql #(.IOSTANDARD (IOSTANDARD_SYS),.SLEW(SLEW_SYS),.DRIVE(DRIVE_SYS),.IBUF_DELAY(IBUF_DELAY_SYS_A),.IFD_DELAY(IFD_DELAY_SYS_A))
i_a12(.g(cwr),.q(), .qr(), .io(a[12]),.t(!drv_bus),.d(ao[12]));
// inter-clock synchronization // inter-clock synchronization
FDCE i_sync0 (.Q(sync0), .C(cwr),.CE(1'b1),.CLR(sync2),.D(1'b1)); FDCE i_sync0 (.Q(sync0), .C(cwr),.CE(1'b1),.CLR(sync2),.D(1'b1));
...@@ -401,12 +468,24 @@ module sysinterface(clk, ...@@ -401,12 +468,24 @@ module sysinterface(clk,
FD i_sync_cwr_on (.Q(sync_cwr_on), .C(clk),.D(sync_cwr_start1 || (sync_cwr_on && !sync1))); FD i_sync_cwr_on (.Q(sync_cwr_on), .C(clk),.D(sync_cwr_start1 || (sync_cwr_on && !sync1)));
LUT4 #(.INIT(16'hAA80)) i_dataouten ( .I0(1'b1), .I1(ice1), .I2(ice), .I3(ioe), .O(t)); LUT4 #(.INIT(16'hAA80)) i_dataouten ( .I0(1'b1), .I1(ice1), .I2(ice), .I3(ioe), .O(t));
dpads32 i_dmapads32(.c(cwr),.t(t),.d(iod[31:0]),.q(id0[31:0]),.dq(d[31:0])); dpads32 #(
.IOSTANDARD (IOSTANDARD_SYS),
.SLEW (SLEW_SYS),
.DRIVE (DRIVE_SYS),
.IBUF_DELAY (IBUF_DELAY_SYS_D),
.IFD_DELAY (IFD_DELAY_SYS_D))
i_dmapads32(.c(cwr),.t(t),.d(iod[31:0]),.q(id0[31:0]),.dq(d[31:0]));
endmodule endmodule
module dpads32(c,t,d,q,dq); module dpads32 #(
parameter IOSTANDARD = "LVCMOS33",
parameter SLEW = "SLOW",
parameter DRIVE = 8,
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
) (c,t,d,q,dq);
input c,t; input c,t;
input [31:0] d; input [31:0] d;
output [31:0] q; output [31:0] q;
...@@ -416,38 +495,70 @@ module dpads32(c,t,d,q,dq); ...@@ -416,38 +495,70 @@ module dpads32(c,t,d,q,dq);
// s---ynthesis attribute KEEP_HIERARCHY of i_t1 is true // s---ynthesis attribute KEEP_HIERARCHY of i_t1 is true
BUF i_t0 (.I(t), .O(t0)); BUF i_t0 (.I(t), .O(t0));
BUF i_t1 (.I(t), .O(t1)); BUF i_t1 (.I(t), .O(t1));
dio1 i_d0 (.c(c),.t(t0),.d(d[ 0]),.q(q[ 0]),.dq(dq[ 0])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d1 (.c(c),.t(t0),.d(d[ 1]),.q(q[ 1]),.dq(dq[ 1])); i_d0 (.c(c),.t(t0),.d(d[ 0]),.q(q[ 0]),.dq(dq[ 0]));
dio1 i_d2 (.c(c),.t(t0),.d(d[ 2]),.q(q[ 2]),.dq(dq[ 2])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d3 (.c(c),.t(t0),.d(d[ 3]),.q(q[ 3]),.dq(dq[ 3])); i_d1 (.c(c),.t(t0),.d(d[ 1]),.q(q[ 1]),.dq(dq[ 1]));
dio1 i_d4 (.c(c),.t(t0),.d(d[ 4]),.q(q[ 4]),.dq(dq[ 4])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d5 (.c(c),.t(t0),.d(d[ 5]),.q(q[ 5]),.dq(dq[ 5])); i_d2 (.c(c),.t(t0),.d(d[ 2]),.q(q[ 2]),.dq(dq[ 2]));
dio1 i_d6 (.c(c),.t(t0),.d(d[ 6]),.q(q[ 6]),.dq(dq[ 6])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d7 (.c(c),.t(t0),.d(d[ 7]),.q(q[ 7]),.dq(dq[ 7])); i_d3 (.c(c),.t(t0),.d(d[ 3]),.q(q[ 3]),.dq(dq[ 3]));
dio1 i_d8 (.c(c),.t(t0),.d(d[ 8]),.q(q[ 8]),.dq(dq[ 8])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d9 (.c(c),.t(t0),.d(d[ 9]),.q(q[ 9]),.dq(dq[ 9])); i_d4 (.c(c),.t(t0),.d(d[ 4]),.q(q[ 4]),.dq(dq[ 4]));
dio1 i_d10 (.c(c),.t(t1),.d(d[10]),.q(q[10]),.dq(dq[10])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d11 (.c(c),.t(t1),.d(d[11]),.q(q[11]),.dq(dq[11])); i_d5 (.c(c),.t(t0),.d(d[ 5]),.q(q[ 5]),.dq(dq[ 5]));
dio1 i_d12 (.c(c),.t(t1),.d(d[12]),.q(q[12]),.dq(dq[12])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d13 (.c(c),.t(t1),.d(d[13]),.q(q[13]),.dq(dq[13])); i_d6 (.c(c),.t(t0),.d(d[ 6]),.q(q[ 6]),.dq(dq[ 6]));
dio1 i_d14 (.c(c),.t(t1),.d(d[14]),.q(q[14]),.dq(dq[14])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d15 (.c(c),.t(t1),.d(d[15]),.q(q[15]),.dq(dq[15])); i_d7 (.c(c),.t(t0),.d(d[ 7]),.q(q[ 7]),.dq(dq[ 7]));
dio1 i_d16 (.c(c),.t(t1),.d(d[16]),.q(q[16]),.dq(dq[16])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d17 (.c(c),.t(t0),.d(d[17]),.q(q[17]),.dq(dq[17])); i_d8 (.c(c),.t(t0),.d(d[ 8]),.q(q[ 8]),.dq(dq[ 8]));
dio1 i_d18 (.c(c),.t(t1),.d(d[18]),.q(q[18]),.dq(dq[18])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d19 (.c(c),.t(t1),.d(d[19]),.q(q[19]),.dq(dq[19])); i_d9 (.c(c),.t(t0),.d(d[ 9]),.q(q[ 9]),.dq(dq[ 9]));
dio1 i_d20 (.c(c),.t(t1),.d(d[20]),.q(q[20]),.dq(dq[20])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d21 (.c(c),.t(t1),.d(d[21]),.q(q[21]),.dq(dq[21])); i_d10 (.c(c),.t(t1),.d(d[10]),.q(q[10]),.dq(dq[10]));
dio1 i_d22 (.c(c),.t(t0),.d(d[22]),.q(q[22]),.dq(dq[22])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d23 (.c(c),.t(t1),.d(d[23]),.q(q[23]),.dq(dq[23])); i_d11 (.c(c),.t(t1),.d(d[11]),.q(q[11]),.dq(dq[11]));
dio1 i_d24 (.c(c),.t(t0),.d(d[24]),.q(q[24]),.dq(dq[24])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d25 (.c(c),.t(t1),.d(d[25]),.q(q[25]),.dq(dq[25])); i_d12 (.c(c),.t(t1),.d(d[12]),.q(q[12]),.dq(dq[12]));
dio1 i_d26 (.c(c),.t(t0),.d(d[26]),.q(q[26]),.dq(dq[26])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d27 (.c(c),.t(t0),.d(d[27]),.q(q[27]),.dq(dq[27])); i_d13 (.c(c),.t(t1),.d(d[13]),.q(q[13]),.dq(dq[13]));
dio1 i_d28 (.c(c),.t(t0),.d(d[28]),.q(q[28]),.dq(dq[28])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d29 (.c(c),.t(t0),.d(d[29]),.q(q[29]),.dq(dq[29])); i_d14 (.c(c),.t(t1),.d(d[14]),.q(q[14]),.dq(dq[14]));
dio1 i_d30 (.c(c),.t(t1),.d(d[30]),.q(q[30]),.dq(dq[30])); dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
dio1 i_d31 (.c(c),.t(t1),.d(d[31]),.q(q[31]),.dq(dq[31])); i_d15 (.c(c),.t(t1),.d(d[15]),.q(q[15]),.dq(dq[15]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d16 (.c(c),.t(t1),.d(d[16]),.q(q[16]),.dq(dq[16]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d17 (.c(c),.t(t0),.d(d[17]),.q(q[17]),.dq(dq[17]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d18 (.c(c),.t(t1),.d(d[18]),.q(q[18]),.dq(dq[18]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d19 (.c(c),.t(t1),.d(d[19]),.q(q[19]),.dq(dq[19]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d20 (.c(c),.t(t1),.d(d[20]),.q(q[20]),.dq(dq[20]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d21 (.c(c),.t(t1),.d(d[21]),.q(q[21]),.dq(dq[21]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d22 (.c(c),.t(t0),.d(d[22]),.q(q[22]),.dq(dq[22]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d23 (.c(c),.t(t1),.d(d[23]),.q(q[23]),.dq(dq[23]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d24 (.c(c),.t(t0),.d(d[24]),.q(q[24]),.dq(dq[24]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d25 (.c(c),.t(t1),.d(d[25]),.q(q[25]),.dq(dq[25]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d26 (.c(c),.t(t0),.d(d[26]),.q(q[26]),.dq(dq[26]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d27 (.c(c),.t(t0),.d(d[27]),.q(q[27]),.dq(dq[27]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d28 (.c(c),.t(t0),.d(d[28]),.q(q[28]),.dq(dq[28]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d29 (.c(c),.t(t0),.d(d[29]),.q(q[29]),.dq(dq[29]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d30 (.c(c),.t(t1),.d(d[30]),.q(q[30]),.dq(dq[30]));
dio1 #(.IOSTANDARD (IOSTANDARD),.SLEW(SLEW),.DRIVE(DRIVE),.IBUF_DELAY(IBUF_DELAY),.IFD_DELAY(IFD_DELAY))
i_d31 (.c(c),.t(t1),.d(d[31]),.q(q[31]),.dq(dq[31]));
endmodule endmodule
...@@ -692,68 +803,124 @@ FD_1 #(.INIT(1'b1)) i_dr (.C(c), .D(d0), .Q(dr)); ...@@ -692,68 +803,124 @@ FD_1 #(.INIT(1'b1)) i_dr (.C(c), .D(d0), .Q(dr));
endmodule endmodule
module ipadql(g,q,qr,d); // module ipadql#(
parameter IOSTANDARD = "LVCMOS33",
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(g,q,qr,d); //
input g; input g;
output q; output q;
output qr; output qr;
input d; input d;
ipadql0 i_q (.g(g),.q(q),.qr(qr),.d(d)); ipadql0 #(
.IOSTANDARD (IOSTANDARD),
.IBUF_DELAY (IBUF_DELAY),
.IFD_DELAY (IFD_DELAY))
i_q (.g(g),.q(q),.qr(qr),.d(d));
// s--ynthesis attribute KEEP_HIERARCHY of i_q is "TRUE" // s--ynthesis attribute KEEP_HIERARCHY of i_q is "TRUE"
endmodule endmodule
module ipadql0(g,q,qr,d); module ipadql0#(
parameter IOSTANDARD = "LVCMOS33",
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(g,q,qr,d);
input g; input g;
output q; output q;
output qr; output qr;
input d; input d;
IBUF i_q (.I(d), .O(q)); IBUF #(
.IOSTANDARD (IOSTANDARD),
.IBUF_DELAY_VALUE (IBUF_DELAY),
.IFD_DELAY_VALUE (IFD_DELAY))
i_q (.I(d), .O(q));
LD i_qr (.G(g), .D(q), .Q(qr)); LD i_qr (.G(g), .D(q), .Q(qr));
// synthesis attribute IOB of i_qr is "TRUE" // synthesis attribute IOB of i_qr is "TRUE"
// synthesis attribute NODELAY of i_q is "TRUE" // synthesis attribute NODELAY of i_q is "TRUE"
endmodule endmodule
module bpadql(g,q,qr,io,t,d); // module bpadql#(
parameter IOSTANDARD = "LVCMOS33",
parameter SLEW = "SLOW",
parameter DRIVE = 8,
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(g,q,qr,io,t,d); //
input g; input g;
output q; output q;
output qr; output qr;
inout io; inout io;
input t; input t;
input d; input d;
bpadql0 i_q (.g(g),.q(q),.qr(qr),.io(io),.t(t),.d(d)); bpadql0 #(
// s--ynthesis attribute KEEP_HIERARCHY of i_q is "TRUE" .IOSTANDARD (IOSTANDARD),
.SLEW (SLEW),
.DRIVE (DRIVE),
.IBUF_DELAY (IBUF_DELAY),
.IFD_DELAY (IFD_DELAY)
)i_q (.g(g),.q(q),.qr(qr),.io(io),.t(t),.d(d));
endmodule endmodule
module bpadql0(g,q,qr,io,t,d); module bpadql0#(
parameter IOSTANDARD = "LVCMOS33",
parameter SLEW = "SLOW",
parameter DRIVE = 8,
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(g,q,qr,io,t,d);
input g; input g;
output q; output q;
output qr; output qr;
inout io; inout io;
input t; input t;
input d; input d;
IOBUF i_q (.I(d), .T(t),.O(q), .IO(io)); IOBUF #(
.IOSTANDARD (IOSTANDARD),
.SLEW (SLEW),
.DRIVE (DRIVE),
.IBUF_DELAY_VALUE (IBUF_DELAY),
.IFD_DELAY_VALUE (IFD_DELAY)
) i_q (.I(d), .T(t),.O(q), .IO(io));
LD i_qr (.G(g), .D(q), .Q(qr)); LD i_qr (.G(g), .D(q), .Q(qr));
// synthesis attribute IOB of i_qr is "TRUE" // synthesis attribute IOB of i_qr is "TRUE"
// synthesis attribute NODELAY of i_q is "TRUE"
endmodule endmodule
module dio1(c,t,d,q,dq); module dio1 #(
parameter IOSTANDARD = "LVCMOS33",
parameter SLEW = "SLOW",
parameter DRIVE = 8,
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(c,t,d,q,dq);
input c; input c;
input t; input t;
input d; input d;
output q; output q;
inout dq; inout dq;
dio0 i_dq (.c(c),.t(t),.d(d),.q(q),.dq(dq)); dio0 #(
.IOSTANDARD (IOSTANDARD),
.SLEW (SLEW),
.DRIVE (DRIVE),
.IBUF_DELAY (IBUF_DELAY),
.IFD_DELAY (IFD_DELAY)
) i_dq (.c(c),.t(t),.d(d),.q(q),.dq(dq));
// s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE" // s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule endmodule
module dio0(c,t,d,q,dq); module dio0 #(
parameter IOSTANDARD = "LVCMOS33",
parameter SLEW = "SLOW",
parameter DRIVE = 8,
parameter IBUF_DELAY = "0",
parameter IFD_DELAY = "0"
)(c,t,d,q,dq);
input c; input c;
input t; input t;
input d; input d;
...@@ -762,10 +929,15 @@ module dio0(c,t,d,q,dq); ...@@ -762,10 +929,15 @@ module dio0(c,t,d,q,dq);
wire q0; wire q0;
IOBUF i_dq (.I(d), .T(t),.O(q0), .IO(dq)); IOBUF #(
.IOSTANDARD (IOSTANDARD),
.SLEW (SLEW),
.DRIVE (DRIVE),
.IBUF_DELAY_VALUE (IBUF_DELAY),
.IFD_DELAY_VALUE (IFD_DELAY)
) i_dq (.I(d), .T(t),.O(q0), .IO(dq));
FD i_q (.C(c), .D(q0), .Q(q)); FD i_q (.C(c), .D(q0), .Q(q));
// synthesis attribute IOB of i_q is "TRUE" // synthesis attribute IOB of i_q is "TRUE"
// synthesis attribute NODELAY of i_dq is "TRUE"
endmodule endmodule
sensor/sensor_phase353.v
View file @ 8d77d7f8
...@@ -26,7 +26,12 @@ ...@@ -26,7 +26,12 @@
** **
*/ */
module sensor_phase353 (cclk, // command clock (posedge, invert on input if needed) module sensor_phase353 #(
parameter IOSTANDARD_SENSOR = "LVCMOS33",
parameter IFD_DELAY_SENSOR_VHACT = "0",
parameter IBUF_DELAY_SENSOR_VHACT = "0"
)(
cclk, // command clock (posedge, invert on input if needed)
wcmd, // write command wcmd, // write command
cmd, // CPU write data [5:0] cmd, // CPU write data [5:0]
// 0 - nop, just reset status data // 0 - nop, just reset status data
...@@ -72,7 +77,7 @@ NET "hact_length*" TIG; ...@@ -72,7 +77,7 @@ NET "hact_length*" TIG;
*/ */
parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width
`ifdef IVERILOG `ifdef SIMULATION
parameter IS_SIMUL=1; parameter IS_SIMUL=1;
`else `else
parameter IS_SIMUL=0; parameter IS_SIMUL=0;
...@@ -278,8 +283,16 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata)) ...@@ -278,8 +283,16 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
wire ihact00,ivact00; wire ihact00,ivact00;
/// some are double cycle /// some are double cycle
IBUF i_hact (.I(HACT), .O(ihact)); IBUF #(
IBUF i_vact (.I(VACT), .O(ivact)); .IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_VHACT),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_VHACT)
) i_hact (.I(HACT), .O(ihact));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_VHACT),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_VHACT)
) i_vact (.I(VACT), .O(ivact));
always @ (posedge gclk_idata) begin always @ (posedge gclk_idata) begin
hact_q1 <= ihact00; hact_q1 <= ihact00;
vact_q1 <= ivact00; vact_q1 <= ivact00;
...@@ -307,6 +320,7 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata)) ...@@ -307,6 +320,7 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
// FD i_vact_q1 (.C(gclk_idata), .D(ivact00), .Q(vact_q1)); // FD i_vact_q1 (.C(gclk_idata), .D(ivact00), .Q(vact_q1));
FDCE i_sync_alt_d0 (.Q(sync_alt_d0), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(sync_alt)); FDCE i_sync_alt_d0 (.Q(sync_alt_d0), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(sync_alt));
FDCE i_idi_0 (.Q(idi[ 0]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 0])); FDCE i_idi_0 (.Q(idi[ 0]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 0]));
FDCE i_idi_1 (.Q(idi[ 1]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 1])); FDCE i_idi_1 (.Q(idi[ 1]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 1]));
FDCE i_idi_2 (.Q(idi[ 2]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 2])); FDCE i_idi_2 (.Q(idi[ 2]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 2]));
...@@ -319,34 +333,7 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata)) ...@@ -319,34 +333,7 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9])); FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9]));
FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10])); FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10]));
FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11])); FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11]));
// synthesis attribute IOB of i_sync_alt_d0 is "TRUE"
// synthesis attribute IOB of i_idi_0 is "TRUE"
// synthesis attribute IOB of i_idi_1 is "TRUE"
// synthesis attribute IOB of i_idi_2 is "TRUE"
// synthesis attribute IOB of i_idi_3 is "TRUE"
// synthesis attribute IOB of i_idi_4 is "TRUE"
// synthesis attribute IOB of i_idi_5 is "TRUE"
// synthesis attribute IOB of i_idi_6 is "TRUE"
// synthesis attribute IOB of i_idi_7 is "TRUE"
// synthesis attribute IOB of i_idi_8 is "TRUE"
// synthesis attribute IOB of i_idi_9 is "TRUE"
// synthesis attribute IOB of i_idi_10 is "TRUE"
// synthesis attribute IOB of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_sync_alt_d0 is "TRUE"
// synthesis attribute NODELAY of i_idi_0 is "TRUE"
// synthesis attribute NODELAY of i_idi_1 is "TRUE"
// synthesis attribute NODELAY of i_idi_2 is "TRUE"
// synthesis attribute NODELAY of i_idi_3 is "TRUE"
// synthesis attribute NODELAY of i_idi_4 is "TRUE"
// synthesis attribute NODELAY of i_idi_5 is "TRUE"
// synthesis attribute NODELAY of i_idi_6 is "TRUE"
// synthesis attribute NODELAY of i_idi_7 is "TRUE"
// synthesis attribute NODELAY of i_idi_8 is "TRUE"
// synthesis attribute NODELAY of i_idi_9 is "TRUE"
// synthesis attribute NODELAY of i_idi_10 is "TRUE"
// synthesis attribute NODELAY of i_idi_11 is "TRUE"
// synthesis attribute NODELAY of i_ihact is "TRUE"
// synthesis attribute NODELAY of i_ivact is "TRUE"
reg [1:0] shact_zero; // shact was zero (inactive), sync to gclk_data reg [1:0] shact_zero; // shact was zero (inactive), sync to gclk_data
always @ (posedge gclk_idata) if (en_idata) begin always @ (posedge gclk_idata) if (en_idata) begin
idi14[13:4] <= idi[11:2]; idi14[13:4] <= idi[11:2];
......
sensor/sensorpads353.v
View file @ 8d77d7f8
...@@ -28,7 +28,21 @@ ...@@ -28,7 +28,21 @@
module sensorpads (/// interface to DCM module sensorpads #(
parameter IOSTANDARD_SENSOR = "LVCMOS33",
parameter SLEW_SENSOR = "SLOW",
parameter DRIVE_SENSOR = 4,
parameter IOSTANDARD_SENSOR_CLK = "LVCMOS33",
parameter SLEW_SENSOR_CLK = "SLOW",
parameter DRIVE_SENSOR_CLK = 4,
parameter IFD_DELAY_SENSOR_PXD = "0",
parameter IFD_DELAY_SENSOR_VHACT = "0",
parameter IBUF_DELAY_SENSOR_PXD = "0",
parameter IBUF_DELAY_SENSOR_VHACT = "0"
) (
sclk, // system clock, @negedge sclk, // system clock, @negedge
cmd, // [6:0] command for phase adjustment @ negedge (sclk) MSB - reset pclk2x DCM cmd, // [6:0] command for phase adjustment @ negedge (sclk) MSB - reset pclk2x DCM
wcmd, // write command@ negedge (slck) wcmd, // write command@ negedge (slck)
...@@ -137,8 +151,11 @@ module sensorpads (/// interface to DCM ...@@ -137,8 +151,11 @@ module sensorpads (/// interface to DCM
wire [11:0] pxdi; wire [11:0] pxdi;
//Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock... //Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock...
assign fifo_clkin=(clk_sel && !dclkmode)?sens_clk:clk; assign fifo_clkin=(clk_sel && !dclkmode)?sens_clk:clk;
sensor_phase353 sensor_phase353 #(
i_sensor_phase (.cclk(!sclk), // command clock (posedge, invert on input if needed) .IOSTANDARD_SENSOR (IOSTANDARD_SENSOR),
.IFD_DELAY_SENSOR_VHACT (IFD_DELAY_SENSOR_VHACT),
.IBUF_DELAY_SENSOR_VHACT (IBUF_DELAY_SENSOR_VHACT)
)i_sensor_phase (.cclk(!sclk), // command clock (posedge, invert on input if needed)
.wcmd(wcmd), // write command .wcmd(wcmd), // write command
.cmd(cmd[5:0]),// CPU write data [5:0] .cmd(cmd[5:0]),// CPU write data [5:0]
// 0 - nop, just reset status data // 0 - nop, just reset status data
...@@ -176,26 +193,102 @@ sensor_phase353 ...@@ -176,26 +193,102 @@ sensor_phase353
IOBUF i_mrst (.I(imrst), .IO(mrst), .T(xpgmen), .O(xfpgadone)); IOBUF #(
OBUF i_arst (.I(xpgmen? xfpgatms : iarst), .O(arst)); .IOSTANDARD (IOSTANDARD_SENSOR),
OBUF i_aro (.I(xpgmen? xfpgatck : iaro), .O(aro )); .SLEW (SLEW_SENSOR),
.DRIVE (DRIVE_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_mrst (.I(imrst), .IO(mrst), .T(xpgmen), .O(xfpgadone));
OBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.SLEW (SLEW_SENSOR),
.DRIVE (DRIVE_SENSOR)
) i_arst (.I(xpgmen? xfpgatms : iarst), .O(arst));
OBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.SLEW (SLEW_SENSOR),
.DRIVE (DRIVE_SENSOR)
) i_aro (.I(xpgmen? xfpgatck : iaro), .O(aro ));
IOBUF i_dclk (.I(clk), .IO(dclk), .T(dclkmode), .O(idclk)); IOBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR_CLK),
.SLEW (SLEW_SENSOR_CLK),
.DRIVE (DRIVE_SENSOR_CLK),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_dclk (.I(clk), .IO(dclk), .T(dclkmode), .O(idclk));
IBUF i_bpf (.I(bpf), .O(sens_clk)); IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
IOBUF i_pxd0 (.IO(pxd[ 0]), .I(xpgmen?xfpgatdi:cnvctl[0]), .T(~(cnven | xpgmen)), .O(pxdi[0])); .IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
IOBUF i_pxd1 (.IO(pxd[ 1]), .I( cnvctl[1]), .T(~ cnven | xpgmen ), .O(pxdi[1])); .IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
IBUF i_pxd2 (.I (pxd[ 2]), .O(pxdi[ 2])); ) i_bpf (.I(bpf), .O(sens_clk));
IBUF i_pxd3 (.I (pxd[ 3]), .O(pxdi[ 3]));
IBUF i_pxd4 (.I (pxd[ 4]), .O(pxdi[ 4])); IOBUF #(
IBUF i_pxd5 (.I (pxd[ 5]), .O(pxdi[ 5])); .IOSTANDARD (IOSTANDARD_SENSOR),
IBUF i_pxd6 (.I (pxd[ 6]), .O(pxdi[ 6])); .SLEW (SLEW_SENSOR),
IBUF i_pxd7 (.I (pxd[ 7]), .O(pxdi[ 7])); .DRIVE (DRIVE_SENSOR),
IBUF i_pxd8 (.I (pxd[ 8]), .O(pxdi[ 8])); .IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
IBUF i_pxd9 (.I (pxd[ 9]), .O(pxdi[ 9])); .IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
IBUF i_pxd10 (.I (pxd[10]), .O(pxdi[10])); ) i_pxd0 (.IO(pxd[ 0]), .I(xpgmen?xfpgatdi:cnvctl[0]), .T(~(cnven | xpgmen)), .O(pxdi[0]));
IBUF i_pxd11 (.I (pxd[11]), .O(pxdi[11])); IOBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.SLEW (SLEW_SENSOR),
.DRIVE (DRIVE_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd1 (.IO(pxd[ 1]), .I( cnvctl[1]), .T(~ cnven | xpgmen ), .O(pxdi[1]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd2 (.I (pxd[ 2]), .O(pxdi[ 2]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd3 (.I (pxd[ 3]), .O(pxdi[ 3]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd4 (.I (pxd[ 4]), .O(pxdi[ 4]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd5 (.I (pxd[ 5]), .O(pxdi[ 5]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd6 (.I (pxd[ 6]), .O(pxdi[ 6]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd7 (.I (pxd[ 7]), .O(pxdi[ 7]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd8 (.I (pxd[ 8]), .O(pxdi[ 8]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd9 (.I (pxd[ 9]), .O(pxdi[ 9]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd10 (.I (pxd[10]), .O(pxdi[10]));
IBUF #(
.IOSTANDARD (IOSTANDARD_SENSOR),
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_PXD),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_PXD)
) i_pxd11 (.I (pxd[11]), .O(pxdi[11]));
assign xfpgatdo=pxdi[1]; assign xfpgatdo=pxdi[1];
//pxdi[11:0] //pxdi[11:0]
......
x353.v
View file @ 8d77d7f8
...@@ -32,17 +32,49 @@ ...@@ -32,17 +32,49 @@
`define debug_mcontr_reset `define debug_mcontr_reset
// `define DEBUG_IMU // `define DEBUG_IMU
module x353 #( module x353 #(
parameter IOSTANDARD_CLK = "LVCMOS33",
parameter IOSTANDARD_SYS = "LVCMOS33",
parameter SLEW_SYS = "SLOW",
parameter DRIVE_SYS = 8,
parameter IBUF_DELAY_SYS_A = "0",
parameter IFD_DELAY_SYS_A = "0",
parameter IBUF_DELAY_SYS_D = "0",
parameter IFD_DELAY_SYS_D = "0",
parameter IBUF_DELAY_SYS_WOE = "0",
parameter IFD_DELAY_SYS_WOE = "0",
parameter IBUF_DELAY_SYS_CE = "0",
parameter IFD_DELAY_SYS_CE = "0",
parameter IBUF_DELAY_SYS_DACK = "0",
parameter IFD_DELAY_SYS_DACK = "0",
parameter IBUF_DELAY_SYS_SDCLK = "0",
parameter IFD_DELAY_SYS_SDCLK = "0",
parameter SLEW_SYS_DREQ = "SLOW",
parameter DRIVE_SYS_DREQ = 4,
parameter IOSTANDARD_EXT = "LVCMOS33", parameter IOSTANDARD_EXT = "LVCMOS33",
parameter SLEW_EXT = "SLOW", parameter SLEW_EXT = "SLOW",
parameter DRIVE_EXT = 12, parameter DRIVE_EXT = 12,
parameter IOSTANDARD_SENSOR = "LVCMOS33", parameter IOSTANDARD_SENSOR = "LVCMOS25",
parameter SLEW_SENSOR = "SLOW", parameter SLEW_SENSOR = "SLOW",
parameter DRIVE_SENSOR = 4, parameter DRIVE_SENSOR = 4,
parameter IOSTANDARD_SENSOR_CLK = "LVCMOS33", parameter IOSTANDARD_SENSOR_CLK = "LVCMOS25",
parameter SLEW_SENSOR_CLK = "SLOW", parameter SLEW_SENSOR_CLK = "SLOW",
parameter DRIVE_SENSOR_CLK = 4, parameter DRIVE_SENSOR_CLK = 4,
parameter IFD_DELAY_SENSOR_PXD = "0",
parameter IFD_DELAY_SENSOR_VHACT ="0",
parameter IBUF_DELAY_SENSOR_PXD = "0",
parameter IBUF_DELAY_SENSOR_VHACT ="0",
parameter IOSTANDARD_SDRAM = "SSTL2_I", parameter IOSTANDARD_SDRAM = "SSTL2_I",
parameter DRIVE_SDRAM_DATA = 12, parameter DRIVE_SDRAM_DATA = 12,
...@@ -770,28 +802,52 @@ wire [3:0] restart; // reinitialize mcontr channels (normally after frame syn ...@@ -770,28 +802,52 @@ wire [3:0] restart; // reinitialize mcontr channels (normally after frame syn
wire drv_bus=1'b0;// drive system bus (to write to system memory) wire drv_bus=1'b0;// drive system bus (to write to system memory)
wire nevr; // never true; wire nevr; // never true;
wire isys_sdclki, ibrin; wire isys_sdclki, ibrin;
assign BROUT=1'b0; // assign BROUT=1'b0;
assign SYS_BUSEN=1'b1; OBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
IBUF i_SYS_SDCLKI(.I(SYS_SDCLKI), .O(isys_sdclki)); .DRIVE (DRIVE_SYS_DREQ),
IBUF i_BRIN (.I(BRIN), .O(ibrin)); .SLEW (SLEW_SYS_DREQ))
i_BROUT (
.I(1'b0),
.O(BROUT));
// assign SYS_BUSEN=1'b1;
OBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.DRIVE (DRIVE_SYS_DREQ),
.SLEW (SLEW_SYS_DREQ))
i_SYS_BUSEN (
.I(1'b1),
.O(SYS_BUSEN));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE (IBUF_DELAY_SYS_SDCLK),
.IFD_DELAY_VALUE (IFD_DELAY_SYS_SDCLK))
i_SYS_SDCLKI(
.I (SYS_SDCLKI),
.O (isys_sdclki));
IBUF #(
.IOSTANDARD (IOSTANDARD_SYS),
.IBUF_DELAY_VALUE (IBUF_DELAY_SYS_DACK),
.IFD_DELAY_VALUE (IFD_DELAY_SYS_DACK))
i_BRIN (.I(BRIN), .O(ibrin));
wire idummyvref; wire idummyvref;
IOBUF i_dummyvref (.I(1'b0), .T(nevr), .O(idummyvref), .IO(DUMMYVFEF)); IOBUF #(.IOSTANDARD(IOSTANDARD_SDRAM)) i_dummyvref (.I(1'b0), .T(nevr), .O(idummyvref), .IO(DUMMYVFEF));
IBUF i_always0 (.I(ALWAYS0),.O(nevr)); IBUF #(.IOSTANDARD(IOSTANDARD_SENSOR)) i_always0 (.I(ALWAYS0),.O(nevr)); // same bank as sesnor, 2.5V
// That will keep isys_sdclki && ibrin && isenspgm && idummyvref && sdcl_fb from being optimized into oblivion // That will keep isys_sdclki && ibrin && isenspgm && idummyvref && sdcl_fb from being optimized into oblivion
wire sdcl_fb; wire sdcl_fb;
wire never=nevr && isys_sdclki && ibrin && idummyvref && sdcl_fb; wire never=nevr && isys_sdclki && ibrin && idummyvref && sdcl_fb;
IOBUF i_BA0 (.I(1'b0), .T(!never),.O(), .IO(BA[0])); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_BA0 (.I(1'b0), .T(!never),.O(), .IO(BA[0]));
IOBUF i_BA1 (.I(1'b0), .T(!never),.O(), .IO(BA[1])); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_BA1 (.I(1'b0), .T(!never),.O(), .IO(BA[1]));
IOBUF i_SYS_SDWE (.I(1'b1), .T(!never),.O(), .IO(SYS_SDWE)); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_SYS_SDWE (.I(1'b1), .T(!never),.O(), .IO(SYS_SDWE));
IOBUF i_SYS_SDCAS (.I(1'b1), .T(!never),.O(), .IO(SYS_SDCAS)); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_SYS_SDCAS (.I(1'b1), .T(!never),.O(), .IO(SYS_SDCAS));
IOBUF i_SYS_SDRAS (.I(1'b1), .T(!never),.O(), .IO(SYS_SDRAS)); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_SYS_SDRAS (.I(1'b1), .T(!never),.O(), .IO(SYS_SDRAS));
IOBUF i_SYS_SDCLK (.I(1'b0), .T(!never),.O(), .IO(SYS_SDCLK)); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_SYS_SDCLK (.I(1'b0), .T(!never),.O(), .IO(SYS_SDCLK));
IOBUF i_BG (.I(1'b1), .T(!never),.O(), .IO(BG)); IOBUF #(.IOSTANDARD(IOSTANDARD_SYS)) i_BG (.I(1'b1), .T(!never),.O(), .IO(BG));
// synchronize vacts to negedge of the system clock (sclk) -> vacts_sclk // synchronize vacts to negedge of the system clock (sclk) -> vacts_sclk
FDCE i_vacts_sclki(.C(pclk),.CE(vacts),.CLR(vacts_sclko[1]),.D(1'b1), .Q(vacts_sclki)); FDCE i_vacts_sclki(.C(pclk),.CE(vacts),.CLR(vacts_sclko[1]),.D(1'b1), .Q(vacts_sclki));
...@@ -799,7 +855,19 @@ FDCE i_vacts_sclki(.C(pclk),.CE(vacts),.CLR(vacts_sclko[1]),.D(1'b1), .Q(vacts_s ...@@ -799,7 +855,19 @@ FDCE i_vacts_sclki(.C(pclk),.CE(vacts),.CLR(vacts_sclko[1]),.D(1'b1), .Q(vacts_s
always @ (negedge sclk0) vacts_sclko[1:0] <= {vacts_sclko[0] & ~blockvsync, vacts_sclki && ! vacts_sclko[0] && !vacts_sclko[1]}; always @ (negedge sclk0) vacts_sclko[1:0] <= {vacts_sclko[0] & ~blockvsync, vacts_sclki && ! vacts_sclko[0] && !vacts_sclko[1]};
sysinterface i_sysinterface(.clk(sclk0), sysinterface#(
.IOSTANDARD_SYS (IOSTANDARD_SYS),
.SLEW_SYS (SLEW_SYS),
.DRIVE_SYS (DRIVE_SYS),
.IBUF_DELAY_SYS_A (IBUF_DELAY_SYS_A),
.IFD_DELAY_SYS_A (IFD_DELAY_SYS_A),
.IBUF_DELAY_SYS_D (IBUF_DELAY_SYS_D),
.IFD_DELAY_SYS_D (IFD_DELAY_SYS_D),
.IBUF_DELAY_SYS_WOE (IBUF_DELAY_SYS_WOE),
.IFD_DELAY_SYS_WOE (IFD_DELAY_SYS_WOE),
.IBUF_DELAY_SYS_CE (IBUF_DELAY_SYS_CE),
.IFD_DELAY_SYS_CE (IFD_DELAY_SYS_CE)
) i_sysinterface(.clk(sclk0),
.drv_bus(drv_bus), // drive system bus (to write to system memory) .drv_bus(drv_bus), // drive system bus (to write to system memory)
.d(D[31:0]), // 32 bit D[31:0] data pads .d(D[31:0]), // 32 bit D[31:0] data pads
.oe(OE), // OE pad .oe(OE), // OE pad
...@@ -965,7 +1033,8 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge) ...@@ -965,7 +1033,8 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge)
//wire dcm_locked; //wire dcm_locked;
//wire [7:0] dcm_status; //wire [7:0] dcm_status;
clockios353 i_iclockios(.CLK0(CLK0), // input clock pad - 120MHz clockios353 #(.IOSTANDARD(IOSTANDARD_CLK)) i_iclockios(
.CLK0(CLK0), // input clock pad - 120MHz
.sclk0(sclk0), // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge) .sclk0(sclk0), // global clock, 120MHz, phase=0 (addresses, commands should be strobed at neg edge)
.sclk180(sclk180), // global clock, 120MHz, phase=180 (maybe will not be needed) .sclk180(sclk180), // global clock, 120MHz, phase=180 (maybe will not be needed)
.sclk270(sclk270), // global clock, 120MHz, phase=270 (strobe data write to sdram) .sclk270(sclk270), // global clock, 120MHz, phase=270 (strobe data write to sdram)
...@@ -979,7 +1048,7 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge) ...@@ -979,7 +1048,7 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge)
//wire pclkig; // global buffered pclki (maybe not needed at all - just to drive sensor_phase)? //wire pclkig; // global buffered pclki (maybe not needed at all - just to drive sensor_phase)?
//wire sens_clk; // clock from sensor //wire sens_clk; // clock from sensor
IBUF i_pclki (.I(CLK1), .O(pclki)); IBUF #(.IOSTANDARD(IOSTANDARD_CLK)) i_pclki (.I(CLK1), .O(pclki));
//assign pclkig= pclki; //assign pclkig= pclki;
//assign pclkig= pclk; //assign pclkig= pclk;
...@@ -1010,14 +1079,21 @@ BUFGMUX i_pclk (.O(pclk), .I0(pclki), .I1(sens_clk), .S(|cb_pclksrc[1:0])); ...@@ -1010,14 +1079,21 @@ BUFGMUX i_pclk (.O(pclk), .I0(pclki), .I1(sens_clk), .S(|cb_pclksrc[1:0]));
); );
dmapads i_dmapads ( .dreq0(DREQ0), dmapads#(
.dack0(DACK0), .IOSTANDARD_SYS (IOSTANDARD_SYS),
.idreq0(idreq0), .SLEW_SYS_DREQ (SLEW_SYS_DREQ),
.idack0(idack0), .DRIVE_SYS_DREQ (DRIVE_SYS_DREQ),
.dreq1(DREQ1), .IBUF_DELAY_SYS_DACK (IBUF_DELAY_SYS_DACK),
.dack1(DACK1), .IFD_DELAY_SYS_DACK (IFD_DELAY_SYS_DACK)
.idreq1(idreq1), ) i_dmapads (
.idack1(idack1) .dreq0 (DREQ0),
.dack0 (DACK0),
.idreq0 (idreq0),
.idack0 (idack0),
.dreq1 (DREQ1),
.dack1 (DACK1),
.idreq1 (idreq1),
.idack1 (idack1)
); );
//cb_pxd14 //cb_pxd14
assign ihact=iihact; assign ihact=iihact;
...@@ -1039,12 +1115,17 @@ end ...@@ -1039,12 +1115,17 @@ end
sensorpads #( sensorpads #(
.IOSTANDARD_SENSOR (IOSTANDARD_SENSOR), .IOSTANDARD_SENSOR (IOSTANDARD_SENSOR),
.SLEW_SENSOR (SLEW_SENSOR), .SLEW_SENSOR (SLEW_SENSOR),
.DRIVE_SENSOR (DRIVE_SENSOR), .DRIVE_SENSOR (DRIVE_SENSOR),
.IOSTANDARD_SENSOR_CLK (IOSTANDARD_SENSOR_CLK), .IOSTANDARD_SENSOR_CLK (IOSTANDARD_SENSOR_CLK),
.SLEW_SENSOR_CLK (SLEW_SENSOR_CLK), .SLEW_SENSOR_CLK (SLEW_SENSOR_CLK),
.DRIVE_SENSOR_CLK (DRIVE_SENSOR_CLK) .DRIVE_SENSOR_CLK (DRIVE_SENSOR_CLK),
.IFD_DELAY_SENSOR_PXD (IFD_DELAY_SENSOR_PXD),
.IFD_DELAY_SENSOR_VHACT (IFD_DELAY_SENSOR_VHACT),
.IBUF_DELAY_SENSOR_PXD (IBUF_DELAY_SENSOR_PXD),
.IBUF_DELAY_SENSOR_VHACT (IBUF_DELAY_SENSOR_VHACT)
) i_sensorpads( ) i_sensorpads(
.sclk(sclk0), // system clock, @negedge .sclk(sclk0), // system clock, @negedge
.cmd(idi[10:4]), // [6:0] command for phase adjustment @ negedge (slck) (MSB - reset x2 DCM) .cmd(idi[10:4]), // [6:0] command for phase adjustment @ negedge (slck) (MSB - reset x2 DCM)
...@@ -1743,18 +1824,22 @@ end ...@@ -1743,18 +1824,22 @@ end
); // [2:0] current frame modulo 8 ); // [2:0] current frame modulo 8
OBUF i_irq (.I(!iirq), .O(IRQ) ); OBUF #(
.IOSTANDARD(IOSTANDARD_SYS),
.DRIVE(DRIVE_SYS),
.SLEW(SLEW_SYS))
i_irq (.I(!iirq), .O(IRQ) );
// dummy module instances // dummy module instances
(* keep *) (* keep *)
wire iclk2; // SuppressThisWarning Veditor UNUSED wire iclk2; // SuppressThisWarning Veditor UNUSED
IBUF i_iclk2 (.I(CLK2), .O(iclk2)); IBUF #(.IOSTANDARD(IOSTANDARD_CLK)) i_iclk2 (.I(CLK2), .O(iclk2));
(* keep *) (* keep *)
wire iclk4; // SuppressThisWarning Veditor UNUSED wire iclk4; // SuppressThisWarning Veditor UNUSED
IBUF i_iclk4 (.I(CLK4), .O(iclk4)); IBUF #(.IOSTANDARD(IOSTANDARD_CLK)) i_iclk4 (.I(CLK4), .O(iclk4));
IBUF i_iclk3 (.I(CLK3), .O(iclk3)); IBUF #(.IOSTANDARD(IOSTANDARD_CLK)) i_iclk3 (.I(CLK3), .O(iclk3));
// temporary assignments for outputs - connect later where it belongs // temporary assignments for outputs - connect later where it belongs
......
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