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Elphel
vdt-plugin
Commits
c2d1f2e6
Commit
c2d1f2e6
authored
Apr 05, 2014
by
Andrey Filippov
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More parsing of synthesis tools output
parent
92c30747
Changes
3
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Side-by-side
Showing
3 changed files
with
28 additions
and
12 deletions
+28
-12
parser_vivado.py
parsers/parser_vivado.py
+25
-9
ise_xst.xml
tools/Xilinx_ISE/ise_xst.xml
+2
-2
vivado_proto.xml
tools/Xilinx_Vivado/vivado_proto.xml
+1
-1
No files found.
parsers/parser_vivado.py
View file @
c2d1f2e6
...
...
@@ -5,6 +5,11 @@ import re
pattern
=
re
.
compile
(
"
\
[[^[:]*:
\
d*]"
)
START_REF
=
"(
\\
"
END_REF
=
" )"
patternFlatRef
=
re
.
compile
(
"
\
(([A-Za-z_$][A-Za-z_$0-9]*)
\
)"
)
patternHierRef
=
re
.
compile
(
"
\
(
\\
\
(
\
S*)
\
)"
)
patternModule
=
re
.
compile
(
"module ([A-Za-z_$][A-Za-z_$0-9]*)
\
."
)
#PREFIX_REF="@{"
#SUFFIX_REF="}@"
PREFIX_REF
=
""
...
...
@@ -48,13 +53,20 @@ def hasFileVivado(string): # [*:*]
def
getLineSignalBit
(
string
):
# sys.stdout.write(START_REF)
if
START_REF
in
string
:
start
=
string
.
find
(
START_REF
)
end
=
string
.
find
(
END_REF
,
start
)
if
end
<
0
:
return
None
line
=
string
[:
start
]
+
PREFIX_REF
+
"
%
s"
+
SUFFIX_REF
+
string
[
end
+
len
(
END_REF
):]
ref
=
string
[
start
+
len
(
START_REF
):
end
]
m
=
patternHierRef
.
search
(
string
)
if
not
m
:
m
=
patternFlatRef
.
search
(
string
)
# if START_REF in string:
if
m
:
# start = string.find(START_REF)
# end = string.find(END_REF,start)
# if end <0:
# return None
# line=string[:start]+PREFIX_REF+"%s"+SUFFIX_REF+string[end+len(END_REF):]
# ref=string[start+len(START_REF):end]
line
=
string
[:
m
.
start
(
0
)]
+
PREFIX_REF
+
"
%
s"
+
SUFFIX_REF
+
string
[
m
.
end
(
0
):]
# ref=string[m.start(1):m.end(1)]
ref
=
m
.
group
(
1
)
# replace "/" (used in Xilinx Vivado) with "." for Verilog
ref
=
ref
.
replace
(
"/"
,
"."
)
if
"["
in
ref
:
...
...
@@ -103,13 +115,17 @@ def printLineRef(pRef):
global
global_mode
global
global_db
global
global_top_module
mod
=
global_top_module
m
=
patternModule
.
search
(
pRef
[
0
])
if
m
:
mod
=
m
.
group
(
1
)
if
pRef
:
ranges
=
getRanges
(
pRef
)
if
ranges
:
# line=pRef[0]
ref
=
pRef
[
1
];
if
global_top_module
:
ref
=
global_top_module
+
"."
+
ref
if
mod
:
ref
=
mod
+
"."
+
ref
for
rng
in
ranges
:
if
(
rng
[
0
]
<
0
):
sys
.
stdout
.
write
(
pRef
[
0
]
%
(
ref
))
...
...
tools/Xilinx_ISE/ise_xst.xml
View file @
c2d1f2e6
...
...
@@ -261,7 +261,7 @@
<parameter
id=
"bufr"
label=
"Maximum bufr number"
tooltip=
"Maximum number of regional clock buffers"
default=
""
visible=
"true"
omit=
""
type=
"String"
format=
"Dash"
/>
<parameter
id=
"bus_delimiter"
label=
"Bus delimiters"
tooltip=
"Bus delimiter characters"
default=
"<>"
visible=
"true"
omit=
"<>"
type=
"BusDelimeterType"
format=
"
Quoted
Dash"
/>
default=
"<>"
visible=
"true"
omit=
"<>"
type=
"BusDelimeterType"
format=
"Dash"
/>
<parameter
id=
"case"
label=
"Case"
tooltip=
"Treating the character case"
default=
"maintain"
visible=
"true"
omit=
"maintain"
type=
"CaseType"
format=
"Dash"
/>
<parameter
id=
"decoder_extract"
label=
"Decoder extract"
tooltip=
"Automatic Decoder extract"
...
...
@@ -290,7 +290,7 @@
<parameter
id=
"hdl_compilation_order"
label=
"Compilation order"
tooltip=
"HDL compilation order"
default=
"auto"
visible=
"true"
omit=
"auto"
type=
"AutoUserType"
format=
"Dash"
/>
<parameter
id=
"hierarchy_separator"
label=
"Hierarchy separator"
tooltip=
"Hierarchy separator character"
default=
"/"
visible=
"true"
omit=
"/"
type=
"HierarchySeparatorType"
format=
"
Quoted
Dash"
/>
default=
"/"
visible=
"true"
omit=
"/"
type=
"HierarchySeparatorType"
format=
"Dash"
/>
<parameter
id=
"ifmt"
label=
"input format"
tooltip=
"Type of the HDL source files"
default=
"mixed"
visible=
"true"
omit=
"mixed"
type=
"InputFormatType"
format=
"Dash"
/>
<!-- Try if XST can accept multiple source files as '-ifn file1.v file2.v -other_option, if not - will generate/use command file -->
...
...
tools/Xilinx_Vivado/vivado_proto.xml
View file @
c2d1f2e6
...
...
@@ -56,7 +56,7 @@
visible=
"true"
type=
"String"
format=
"CopyValue"
/>
<parameter
id=
"InstanceSuffix"
label=
"Instance suffix"
tooltip=
"Regular expression to match/remove name suffixes automatically added by the tools"
default=
"_reg"
default=
"_reg
|__parameterized[0-9]*
"
visible=
"true"
type=
"String"
format=
"CopyValue"
/>
<parameter
id=
"parser_mode"
label=
"Parser mode"
tooltip=
"Parser mode (consolidation of bits of the same instance)"
...
...
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