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bin
tmp
\ No newline at end of file
tmp
src/com/elphel/vdt/veditor
_generated
src/com/elphel/vdt/core/launching/VDTErrorParser.java
about_veditor.html
ChangeLogVeditor.txt
CONTRIBUTORS_VEDITOR.txt
README.md 0 → 100644
View file @ 97b4083b
VDT plugin
==========
Table of Contents
-----------------
* [VDT plugin documentation](#vdt-plugin-documentation)
* [Instalation of VDT plugin and related programs](#instalation-of-vdt-plugin-and-related-programs)
* [Installation of Xilinx tools](#installation-of-xilinx-tools)
* [Programs and libraries installed from (K)ubuntu repositories](#programs-and-libraries-installed-from-kubuntu-repositories)
* [GtkWave (3.3.58-1)](#gtkwave-3358-1)
* [other programs needed for building Icarus Verilog](#other-programs-needed-for-building-icarus-verilog)
* [Java JDK](#java-jdk)
* [Icarus Verilog](#icarus-verilog)
* [JavaCC](#javacc)
* [Eclipse IDE](#eclipse-ide)
* [Installation of VDT plugin itself](#installation-of-vdt-plugin-itself)
* [Clone VDT plugin source code](#clone-vdt-plugin-source-code)
* [Run VEditor installation/patch script from within the top directory of vdt-plugin](#run-veditor-installationpatch-script-from-within-the-top-directory-of-vdt-plugin)
* [Import the VDT plugin project into the Eclipse workspace.](#import-the-vdt-plugin-project-into-the-eclipse-workspace)
* [Configuring JavaCC (optional)](#configuring-javacc-optional)
* [Building and running VDT](#building-and-running-vdt)
* [Import and configuration of the sample project in VDT](#import-and-configuration-of-the-sample-project-in-vdt)
* [Import eddr3 project](#import-eddr3-project)
* [Configuration of VDT for eddr3 project](#configuration-of-vdt-for-eddr3-project)
* [Configure access to the server with Xilinx tools](#configure-access-to-the-server-with-xilinx-tools)
* [Copy unisims library to the local directory](#copy-unisims-library-to-the-local-directory)
* [Patch primitive(s) to work with Icarus Verilog](#patch-primitives-to-work-with-icarus-verilog)
* [Simulating eddr3 project with Icarus Verilog](#simulating-eddr3-project-with-icarus-verilog)
##VDT plugin documentation
Documentation is available in a separate [vdt_docs](https://github.com/Elphel/vdt-docs) repository.
##Instalation of VDT plugin and related programs
VDT plugin for Eclipse is designed to integrate different tools for Verilog-based FPGA design.
Currently it supports only GNU/Linux operating system and tool specification file support
Icarus Verilog simulator and Xilinx ISE and Vivado Webpack design suites.
Below is detailed step-by-step installation procedure for Kubuntu 14.04 LTS (other GNU/Linux systems
should not require significantly different installation). Latest tested versions of the programs
are also specified.
### Installation of Xilinx tools
Xilinx Webpack software (free for download) needs to be installed on a GNU/Linux computer according
to the manufacturer recommendations on the same computer as the rest of the software or (preferably)
on a separate system. VDT uses ssh and rsync access to the server running tools, the server can be
in the same LAN or accessed over the WAN. Both ISE and Vivado tools are supported.
### Programs and libraries installed from (K)ubuntu repositories
#### GtkWave (3.3.58-1)
```
sudo apt-get install gtkwave
```
#### other programs needed for building Icarus Verilog
```
sudo apt-get install autoconf gperf flex bison g++ zlib1g-dev libbz2-dev
```
#### Java JDK
For most tasks JRE is sufficient, but if you would like to be able to modify and recompile Verilog
language parsing you will need java compiler that comes with the full JDK
```
sudo apt-get install openjdk-7-jdk
```
### Icarus Verilog
Icarus Verilog has to be compiled from the source code that is available in git repository:
```
git clone git://github.com/steveicarus/iverilog.git
cd iverilog
sh autoconf.sh
./configure
Update: Removed instructions to modify Icarus code - current version does not need
them anymore, so just proceed with
make
sudo make install
```
Default VDT configuration assumes Icarus is installed to the /usr/local/bin
### JavaCC
Java compiler compiler is optional, as VDT provide both Verilog grammar source files
and generated Java files. It is needed only if you need to change and recompile these
files (for example adding support to not yet covered Verilog features).
[JavaCC]( https://java.net/projects/javacc) can be downloaded as
[javacc-6.0.zip]( https://java.net/projects/javacc/downloads/download/javacc-6.0.zip)
Unzip it in any convenient location - this location will be provided to Eclipse later.
### Eclipse IDE
You will need _Eclipse IDE for Java EE Developers_ (capable of plugin development),
latest tested version is Luna
(eclipse-jee-luna-SR1-linux-gtk-x86_64.tar.gz). VDT plugin is experimental and I would
recommend to have a separate (from your other development) installation. VDT uses
modified version of [VEditor](http://sourceforge.net/projects/veditor/) and any other
versions of VEditor installed will conflict with VDT.
**Update:** Mars ( eclipse-jee-mars-R-linux-gtk-x86_64.tar.gz ) seems to be working too if
Gtk3 is disabled (Gtk2 used instead) by adding the following 2 lines:
```
--launcher.GTK_version
2
```
are added just before line
```
--launcher.appendVmargs.
```
in the eclipse.ini file. With Gtk 3 the hover text (such as problems, module instance templates)
is shown black on black background and tool states icons are invisible.
### Installation of VDT plugin itself
VDT plugin uses modified VEditor plugin for Eclipse and because of the license incompatibility
(Eclipse Public License v1.0 for VEditor and GNU General Public License v3.0+ for VDT plugin)
it is not possible to distribute a pre-compiled version (.jar file), so the plugin code has to be
merged (using provided script) and compiled/built as Eclipse plugin project.
####Clone VDT plugin source code
```
git clone git@github.com:Elphel/vdt-plugin.git
```
###Run VEditor installation/patch script from within the top directory of vdt-plugin
```
./install_and_patch_veditor.sh
```
This will clone the original VEditor source tree as tmp/unmodified_veditor_1_2_0_clone,
re-organize files to match VDT plugin code tree, apply patch and copy the produced files
to VDT project locations (most under src/com/elphel/vdt/veditor and _generated), these
files/directories are listed in .gitignore . When VEditor-related part of the VDT code
will be changed (and so the vdt-veditor.patch) you will need to run
./install_and_patch_veditor.sh again
####Import the VDT plugin project into the Eclipse workspace.
At this stage I hit GTK bug that caused Eclipse to crash, working solution is described
in https://bugs.kde.org/show_bug.cgi?id=339174 :
For oxygen, edit the normally already existing file
**/usr/share/themes/oxygen-gtk/gtk-2.0/gtkrc** and change **GtkComboBox::appears-as-list = 1**
into **GtkComboBox::appears-as-list = 0**
```
File->Import->Git->Projects from Git->Existing local repository-> Select directory where you cloned VDT
Import Existing Projects (wizard selection)
```
Keep both **parsers** and **vdt** checked and press **Finish**
####Configuring JavaCC (optional)
In the **Project Explorer** window, expand the **vdt** project folder, right-click
the **buildjavacc.xml** file and select **Properties**.
In the new dialog window select **Run/Debug Settings**, press **New** and agree to
the only suggested option: **Ant Build**.
Then Select **Environment** tab and enter two variables by pressing **New** and then
Name: **ECLIPSE_HOME**
Value: Folder path that contains Eclipse executable
Name: **JAVACC_HOME**
Value: Folder path where **javacc-6.0.zip** was unpacked (ending with /javacc-6.0).
####Building and running VDT
In the "Project Explorer" window, expand the 'vdt' project folder and double-click (open)
the **plugin.xml** file.
Select the **Overview** tab at the bottom of the appeared window.
Under the **Testing** label, click the **Launch an Eclipe application** link.
You may also use "Run Eclipse Application" (green triangle) or "Debug Eclipse Application"
(green bug) buttons on Eclipse toolbar to launch
A new instance of Eclipse will open, this new Eclipse will have VDT plugin activated.
You may minimize the original Eclipse window at this point (it can be used to monitor
and fix plugin errors). Next you may create a new FPGA development project or import
an existing one. We will use DDR3 memory interface project as an example.
## Import and configuration of the sample project in VDT
Sample project is a DDR3 memory interface for Xilinx Zynq SOC that does not depend on
undocumented featuers and encrypted modules and can be simulated with the Free Software
tools.
### Import eddr3 project
```
git clone git@github.com:Elphel/eddr3.git
```
From the Eclipse instance that runs VDT plugin (not the one with the VDT source code)
use the same steps as for importing VDT plugin code (described above):
```
File->Import->Git->Projects from Git->Existing local repository-> Select directory where you cloned eddr3
Import Existing Projects (wizard selection)
```
Keep **eddr3** checked and press **Finish**
### Configuration of VDT for eddr3 project
The cloned eddr3 project does not include Verilog modules of Xilinx primitives that are
required even for simulation of the design. The required library (unisims) is included
with the Xilinx Vivado software and the proprietary license does not allow to redistribute
it. VDT provides means to copy this library from your Vivado installation to the project,
So for the next step you need Xilinx software to be installed on the same or different
computer running GNU/Linux.
Open the top module (ddrc_test01.v) in the Editor (seems to be a bug that prevents
configuration without that step)
Open "Verilog/VHDL' perspective:
```
Window->Open Perspective->Other->Verilog/VHDL
```
It should look as shown on screenshots in [VDT-UserManualAddendum.pdf](https://github.com/Elphel/vdt-docs/blob/master/VDT-UserManualAddendum.pdf?raw=true),
with bottom-left panel showind "Design Menu" and FPGA-related tools
#### Configure access to the server with Xilinx tools
In the "Design menu" panel select "Package" icon, it will open a dialog with "Xilinx server setup"
tab active.
If you have Xilinx tools installed on the same computer as VDT, leave the default value for
*Remote Host IP* (localhost) and *Remote user name* (your current login name).
If you are using phisically different computer - change the both fields as needed.
You may also change Vivado Release to the current one, installation directory (if different from the
default) and configure same parameters for Xilinx ISE if you plan to use it (VDT supports both)
Next you need to setup password-less access to the tools server based on the key pairs:
Generate ssh key (if you do not have it already). Use command line tool or expand
*Vivado Tools* in the design menu, right-click *Start remote Vivado session* and select
*Generate public key* (or use a key icon on the Design menu toolbar)
Send this key to the server - you may either use a command-line program *ssh-copy-id* or right-click
*Start remote Vivado session* and select *Setup connection to user@server* (tools icon on the toolbar).
This operation requires you to enter the password for the server and this requires a separate program
to be installed, you can do this with
```
sudo apt-get install ssh-askpass
```
If ssh will not find *ssh-askpass* or a similar program, it will fail and Eclipse console output will
output the resolution suggestions.
With ssh-askpass a separate dialog window will open, likely the first question will be not the password
itself, but your permission to connect to an unknown host, so just enter *yes* there.
If everything was configured correctly you may try opening remote Vivado session (later it will
happen automatically when needed):
Right-click *Start remote Vivado session* and select *Launch Vivado* (door with entering green arrow icon
on the toolbar)
If everything is correct, in Eclipse console you will see
```
puts "@@FINISH@@"
```
and a few secods later server response ending with
```
@@FINISH@@
```
@@FINISH@@ sequence is just a marker to know server successfully finished the requested command
*Start remote Vivado session* shold now show pulsating green dot to the right of it and the console is
open for both VDT communication and you can also manually enter TCL commands as covered in Xilinx Vivado
manuals.
#### Copy unisims library to the local directory
```
Vivado Tools -> Vivado utilities -> Copy Vivado primitives library to the local project
```
#### Patch primitive(s) to work with Icarus Verilog
Some of the Xilinx primitives can not be simulated correctly with Icarus Verilog, we will add more patches
when we'll hit particular problems, for eddr3 only one file needs to be patched - OSERDESE1.v
Run patch command from the unisms subdirectory of the eddr3 project :
```bash
~/git/eddr3/unisims$ patch -p1 < ../unisims_patches/OSERDESE1.diff
```
## Simulating eddr3 project with Icarus Verilog
```
Design Menu -> Verilog Development tools -> Icarus Verilog simulator
```
If everything will work correctly, Icarus will compile and simulate the design (some warnings in the beginning are not fixed yet). After that GTKWave will
open the simulation results.
In the case of problems you may get more verbose output in the console if you right-click on the
*Icarus Verilog Simulator*, select *Tool parameters*, open *Options tab* and check *Show output
with no errors/warnings*
build.properties
View file @ 97b4083b
......@@ -14,7 +14,8 @@ bin.includes = icons/,\
LICENSE,\
INSTALL,\
CONTRIBUTORS_VEDITOR.txt,\
parsers/
parsers/,\
bin/
#
# Set the following to override the environment
......
install_and_patch_veditor.sh
View file @ 97b4083b
......@@ -14,7 +14,7 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with Eclipse or Eclipse plugins (or a modified version of those libraries),
......@@ -33,7 +33,7 @@ INITIAL_DIRECTORY=`pwd`
if [ ! -f "$PATCH_FILE" ]; then
echo "Patch file $INITIAL_DIRECTORY/$PATCH_FILE is not found"
exit 1
fi
fi
if [ ! -d "$TMPDIR" ]; then
mkdir "$TMPDIR"
fi
......@@ -44,7 +44,7 @@ cp -v "$PATCH_FILE" "$TMPDIR"
cd "$TMPDIR"
if [ ! -d "$GITREPO" ]; then
git clone "$GITURL"
fi
fi
mkdir -p vdt-veditor/src/com/elphel/vdt/core/launching
#Different structure of the files generated by JavaCC, manual copying
mkdir -p vdt-veditor/_generated/com/elphel/vdt/veditor/parser/verilog
......
parsers/parser_quartus.py 0 → 100755
View file @ 97b4083b
#!/usr/bin/env python
# -*- coding: utf-8 -*-
# Copyright (C) 2015, Elphel, Inc.
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with Eclipse or Eclipse plugins (or a modified version of those libraries),
# containing parts covered by the terms of EPL/CPL, the licensors of this
# Program grant you additional permission to convey the resulting work.
# {Corresponding Source for a non-source form of such a combination shall
# include the source code for the parts of Eclipse or Eclipse plugins used
# as well as that of the covered work.}
import sys
import argparse
import re
# Global variables
g_topModule = ""
g_toolName = ""
g_mode = ""
g_includeMsgId = True
g_excludeIdList = []
g_disableExcludeList = False
# Lines starting with these markers are of lines of interest
g_msgTypeMarkers = ("Info", "Warning", "Error", "Critical Warning", "Extra Info")
# Command line paramerters, these names should be in sync with those that are passed to the script in XML files (quartus_proto.xml probably)
g_optNames = ["top_module", "tool_name", "parser_mode", "include_msg_id", "exclude_id_list", "disable_exclude_list"]
# Search patterns
patternMsgType = re.compile(".*?:")
patternMsgId = re.compile("[0-9]+")
patternFileLine = re.compile("([^ ]+)[ ]?\(([0-9]+)")
patternFileNameFull = re.compile("File:(.*)Line:")
class MessageContainer:
"""Helper container for parsed message line"""
msgType = ""
msgId = 0
msgText = ""
fileName = ""
fileNameFull = ""
lineNumber = 0
#Private parameters
__discardId = True
def discardId(self, value = None):
if value == None:
return self.__discardId
else:
self.__discardId = value
def getParameters():
"""Extract parameters from command line arguments"""
global g_topModule
global g_toolName
global g_mode
global g_includeMsgId
global g_excludeIdList
global g_disableExcludeList
parser = argparse.ArgumentParser()
for opt in g_optNames:
parser.add_argument("--{}".format(opt))
args = parser.parse_args()
if args.top_module:
g_topModule = args.top_module
if args.tool_name:
g_toolName = args.tool_name
if args.parser_mode:
g_mode = args.parser_mode
if args.include_msg_id:
if args.include_msg_id == "true":
g_includeMsgId = True
else:
g_includeMsgId = False
if args.exclude_id_list:
g_excludeIdList = [int(elem) for elem in args.exclude_id_list.split('-')]
if args.disable_exclude_list:
if args.disable_exclude_list == "true":
g_disableExcludeList = True
else:
g_disableExcludeList = False
def isProblem(line):
"""Check if the line contains meaningful information"""
global g_msgTypeMarkers
retVal = False
strippedLine = line.strip()
for msgType in g_msgTypeMarkers:
if strippedLine.startswith(msgType):
retVal = True
break
return retVal
def getMsgId(line, msg):
"""Extract message ID from log line an set coresponding msg field
line - text string to be parsed
msg - instance of MessageContainer class
return: instance of MessageContainer class
"""
matchedText = patternMsgId.search(line)
if matchedText:
msgId = line[matchedText.start() : matchedText.end()]
msg.msgId = int(msgId)
return msg
def getMsgType(line, msg):
"""Extract message type from log line an set coresponding msg field
line - text string to be parsed
msg - instance of MessageContainer class
return: log line without message type and instance of MessageContainer class
"""
strippedLine = line.strip()
matchedText = patternMsgType.search(strippedLine)
if matchedText:
msgType = strippedLine[matchedText.start() : matchedText.end() - 1]
msg = getMsgId(msgType, msg)
if msg.msgId != 0:
#remove message ID
msg.msgType = msgType.split('(')[0].strip()
msg.discardId(False)
else:
msg.msgType = msgType
return (strippedLine[matchedText.end() + 1:], msg)
def getFileLine(line, msg):
"""Extract file name and line number from log line an set coresponding msg fields
line - text string to be parsed
msg - instance of MessageContainer class
return: log line without extracted information
"""
matchedLine = patternFileLine.search(line)
if matchedLine and len(matchedLine.groups()) == 2:
msg.lineNumber = int(matchedLine.group(2))
msg.fileName = matchedLine.group(1)
#remove part of the string preceding file name as well as trailing braket and colon
#line = line[matchedLine.end(2) + 2:]
return (line, msg)
def getFilePath(line, msg):
"""Extract full file name and line number from log line an set coresponding msg fields
line - text string to be parsed
msg - instance of MessageContainer class
return: log line without extracted information
"""
matchedLine = patternFileNameFull.search(line)
if matchedLine:
msg.fileNameFull = matchedLine.group(1).strip()
line = line[:matchedLine.start() - 1]
return (line, msg)
def getMsgText(line, msg):
msg.msgText = line.strip()
return ("", msg)
def filterMessage(msg):
"""Decide whether this message should be redirected to output or filtered out"""
retVal = True
if msg.msgId in g_excludeIdList and not g_disableExcludeList:
retVal = False
return retVal
def assembleLine(msg):
"""Assemble and return output line"""
if not g_includeMsgId or msg.discardId():
formatStr = "{0}: {2} [{3}:{4:04d}]\n"
else:
formatStr = "{0}: [{1}] {2} [{3}:{4:04d}]\n"
if msg.fileName =="":
problemMarker = g_toolName
else:
problemMarker = msg.fileName
line = formatStr.format(msg.msgType,
msg.msgId,
msg.msgText,
problemMarker,
msg.lineNumber
)
return line
if __name__ == "__main__":
isFiltered = False
getParameters()
for line in iter(sys.stdin.readline, ''):
if isProblem(line):
msg = MessageContainer()
processedLine, msg = getMsgType(line, msg)
processedLine, msg = getFilePath(processedLine, msg)
processedLine, msg = getFileLine(processedLine, msg)
processedLine, msg = getMsgText(processedLine, msg)
if filterMessage(msg):
logLine = assembleLine(msg)
sys.stdout.write(logLine)
else:
isFiltered = True
if isFiltered:
sys.stdout.write("Info: some messages were filtered by python parser in accordance with settings\n")
tools/Altera_Quartus/quartus_asm.xml 0 → 100644
View file @ 97b4083b
<?xml version="1.0" encoding="UTF-8"?>
<!--
/*******************************************************************************
* Copyright (c) 2015 Elphel, Inc.
* This file is a part of VDT plug-in.
* VDT plug-in is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VDT plug-in is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with Eclipse or Eclipse plugins (or a modified version of those libraries),
* containing parts covered by the terms of EPL/CPL, the licensors of this
* Program grant you additional permission to convey the resulting work.
* {Corresponding Source for a non-source form of such a combination shall
* include the source code for the parts of Eclipse or Eclipse plugins used
* as well as that of the covered work.}
*******************************************************************************/
-->
<vdt-project>
<interface name="QuartusAssemblerInterface" extends="QuartusInterface">
</interface>
<tool name="QuartusAssembler" label="Generate a device programming image"
project="FPGA_project"
interface="QuartusAssemblerInterface"
package="FPGA_package"
shell="/bin/bash"
ignore="%QuartusIgnoreSource"
description="Quartus assembler generates a device programming image"
log-dir="QuartusLogDir"
inherits="QuartusToolPrototype"
disable="DisableTool"
>
<depends-list>
<depends state="QuartusSnapshotPlace"/>
</depends-list>
<action-menu>
<action label="Generate bitstream" resourse="" icon="bitstream.png"/>
</action-menu>
<!-- Interfce parameters -->
<parameter id="DisableTool" label="Disable autorun" tooltip="Disable automatic launch of this tool"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<parameter id="BitfileName" label="Bitstream file name" tooltip="Bitstream file name (will have 'sof' extension)"
type="String" default="%%ProjectName" visible="true" readonly="false" format="CopyValue"/>
<parameter id="CreatePof" label="Create .pof" tooltip="Create Programming Object File (.pof)"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<parameter id="ConfigDevice" label="Configuration device" tooltip="Specify Altera configuration device"
type="String" default="EPCS128" visible="true" readonly="false" format="CopyValue"/>
<parameter id="CreateHex" label="Create .hexout" tooltip="Create Hexadecimal (Intel format) Output File (.hexout)"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<input>
<group name="General">
"DisableTool"
"BitfileName"
"CreatePof"
"ConfigDevice"
"CreateHex"
</group>
</input>
<output>
<!-- Start assembler -->
<line name="quartus_run_asm"
dest="QuartusConsole"
mark="``"
sep="\n"
prompt="@@FINISH@@"
success="@@FINISH@@"
log=""
stdout="parser_Quartus">
"cd ~/%QuartusProjectRoot"
"set projectName %%ProjectName"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"load_package flow"
<!-- Reopen project if it was closed somehow -->
"if [is_project_open] {"
"puts \"Project is open, starting assembler\""
"} else {"
"project_open $projectName"
"}"
"if {[catch {execute_module -tool asm} result]} {"
"puts \"Result: $result\""
"puts \"Error: Assembler faild. See the report file.\""
"} else {"
"puts \"Info: Assembly was successful.\""
"}"
<!-- Convert generated sof to pof -->
<if CreatePof="true">
<if-not ConfigDevice="">
"set sof_file %BitfileName.sof"
"set pof_file %BitfileName.pof"
"set device_name %ConfigDevice"
"if {[catch {execute_module -tool cpf -args \"-c -d $device_name $sof_file $pof_file\"} result]} {"
"puts \"Result: $result\""
"puts \"Error: Programming files converter faild. See the report file.\""
"} else {"
"puts \"Info: File convertion was successful.\""
"}"
</if-not>
<if configDevice="">
"puts \"Error: configuration device is not specified, Programmer Object File is not created \""
</if>
</if>
<!-- Convert generated sof to hex -->
<if CreatePof="true">
"set sof_file %BitfileName.sof"
"set hex_file %BitfileName.hexout"
"if {[catch {execute_module -tool cpf -args \"-c $sof_file $hex_file\"} result]} {"
"puts \"Result: $result\""
"puts \"Error: Programming files converter faild. See the report file.\""
"} else {"
"puts \"Info: File convertion was successful.\""
"}"
</if>
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_bitstream">
"-c"
"mkdir -p %QuartusLocalResultDir;"
"rsync -avr -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/%BitfileName.sof"
"%QuartusLocalResultDir/;"
<!-- Copy pof if it was created -->
<if CreatePof="true">
<if-not ConfigDevice="">
"rsync -avr -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/%BitfileName.pof"
"%QuartusLocalResultDir/;"
</if-not>
</if>
<!-- Copy hex if it was created -->
<if CreateHex="true">
"rsync -avr -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/%BitfileName.hexout"
"%QuartusLocalResultDir/;"
</if>
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
</vdt-project>
tools/Altera_Quartus/quartus_drc.xml 0 → 100644
View file @ 97b4083b
<?xml version="1.0" encoding="UTF-8"?>
<!--
/*******************************************************************************
* Copyright (c) 2015 Elphel, Inc.
* This file is a part of VDT plug-in.
* VDT plug-in is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VDT plug-in is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with Eclipse or Eclipse plugins (or a modified version of those libraries),
* containing parts covered by the terms of EPL/CPL, the licensors of this
* Program grant you additional permission to convey the resulting work.
* {Corresponding Source for a non-source form of such a combination shall
* include the source code for the parts of Eclipse or Eclipse plugins used
* as well as that of the covered work.}
*******************************************************************************/
-->
<vdt-project>
<interface name="QuartusDrcInterface" extends="QuartusInterface">
<syntax name="DoubleDashValue" format="--%%ParamValue"/>
<typedef name="ModeType">
<paramtype kind="enum" base="String">
<item value="None" label=""/>
<item value="post_fit" label="Option to perform post-fit design analysis"/>
<item value="post_syn" label="Option to perform post-synthesis design analysis"/>
<item value="rtl" label="Option to perform pre-synthesis design analysis"/>
</paramtype>
</typedef>
</interface>
<tool name="QuartusDrc" label="Perform design check"
project="FPGA_project"
interface="QuartusDrcInterface"
package="FPGA_package"
shell="/bin/bash"
description="Check the reliability of a design on a set of design rules"
log-dir="QuartusLogDir"
inherits="QuartusToolPrototype"
disable="DisableTool"
>
<depends-list>
<depends state="QuartusSnapshotPlace"/>
</depends-list>
<action-menu>
<action label="Design check" resourse="" icon="check.png"/>
</action-menu>
<!-- Interfce parameters -->
<parameter id="DisableTool" label="Disable autorun" tooltip="Disable automatic launch of this tool"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<parameter id="Mode" label="Analysis mode" tooltip="Select analysis mode"
type="ModeType" default="None" omit="None" visible="true" readonly="false" format="DoubleDashValue"/>
<parameter id="lower_priority" label="Lower priority" tooltip="Option to lower priority of the current process"
default="false" visible="true" readonly="false" omit="false" type="Boolean" format="DoubleDashName"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<input>
<group name="General">
"DisableTool"
"Mode"
"lower_priority"
</group>
</input>
<output>
<!-- Assemble quartus_drc arguments line -->
<line name="quartus_drc_args"
dest="QuartusConsole"
sep=" ">
"set drc_args \""
"%lower_priority"
"%Mode"
"\"\n"
</line>
<!-- Start Design Assistant -->
<line name="quartus_run_drc"
dest="QuartusConsole"
mark="``"
sep="\n"
prompt="@@FINISH@@"
success="@@FINISH@@"
log=""
stdout="parser_Quartus">
"cd ~/%QuartusProjectRoot"
"set projectName %%ProjectName"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"load_package flow"
<!-- Reopen project if it was closed somehow -->
"if [is_project_open] {"
"puts \"Project is open, starting assembler\""
"} else {"
"project_open $projectName"
"}"
"if {$drc_args ne \" \"} {"
"if {[catch {execute_module -tool drc -args $drc_args} result]} {"
"puts \"Result: $result\""
"puts \"Error: Design check faild. See the report file.\""
"} else {"
"puts \"Info: Design check was successful.\""
"}"
"} else {"
"if {[catch {execute_module -tool drc} result]} {"
"puts \"Result: $result\""
"puts \"Error: Design check faild. See the report file.\""
"} else {"
"puts \"Info: Design check was successful.\""
"}"
"}"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
</vdt-project>
tools/Altera_Quartus/quartus_interface.xml
View file @ 97b4083b
......@@ -30,6 +30,8 @@
<interface name="QuartusInterface" extends="FPGAPprojectInterface">
<syntax name="GrepFilterProblemSyntax" format='| grep --line-buffered -v "\[%%ParamName"' />
<syntax name="GrepFilterProblemOtherSyntax" format='%(| grep --line-buffered -v "\[%%ParamValue"%|\n%)' />
<syntax name="CmdLineParameterSyntax" format="--%%ParamName %%ParamValue"/>
<syntax name="MsgIdList" format="--exclude_id_list %(%%ParamValue%|-%)"/>
<typedef name="ParserModeType">
<paramtype kind= "enum" base="String">
<item value="0" label="Tool output is parsed immediately"/>
......@@ -116,5 +118,5 @@
</line>
</output>
</tool>
</vdt-project>
tools/Altera_Quartus/quartus_place.xml
View file @ 97b4083b
......@@ -50,7 +50,7 @@ timing and fitting requirements can be met"/>
</typedef>
<typedef name="QuartusRegPack">
<paramtype kind="enum" base="String">
<item value="auto" label="The Fitter automatically chooses the best method to fit the design"/>
<item value="auto" label="The Fitter automatically chooses the best method to fit the design ℃"/>
<item value="off" label="The Fitter does not attempt to place a pair of logic functions in a single logic cell"/>
<item value="normal" label="The fitter places both a combinational and a sequential operation in a logic cell when
it is expected that the placement will not affect performance"/>
......@@ -78,12 +78,12 @@ register cascade chains, or that can be converted to register cascade chains"/>
inherits="QuartusToolPrototype"
>
<action-menu>
<action lable="Place" resource="" icon="mondrian2x2.png"/>
</action-menu>
<depends-list>
<depends state="QuartusSnapshotSynth"/>
</depends-list>
<action-menu>
<action label="Place and route design" resourse="" icon="route66.png"/>
</action-menu>
<!-- Interfce parameters -->
<parameter id="AutosaveQuartusPlace" label="Create snapshot" tooltip="Automaticaly create snapshot after fitter"
......@@ -124,12 +124,33 @@ clock plan. No core placement or routing will be performed"
default="false" visible="true" readonly="false" omit="false" type="Boolean" format="DoubleDashName"/>
<parameter id="recompile" label="Rapid recompile" tooltip="Option to run Quartus Fit in Rapid Recompile mode"
default="false" visible="true" readonly="false" omit="false" type="Bool_on_off" format="DoubleDash"/>
<parameter id="seed" label="Seed" tooltip="Option to used the specified seed value. The Fitter uses this value as the initial placement configuration
<parameter id="seed" label="Seed" tooltip="Option to use the specified seed value. The Fitter uses this value as the initial placement configuration
when attempting to optimize the design timing requirements, including fmax"
default="1" visible="true" omit="1" readonly="false" type="Cardinal" format="DoubleDash"/>
<parameter id="tdc" label="Timing-driven compilation" tooltip="Option to use timing-driven compilation. This option optimizes place and route based on
timing information"
default="false" visible="true" readonly="false" omit="false" type="Bool_on_off" format="DoubleDash"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<input>
<group name="General">
<!-- Same as in project settings-->
......@@ -177,7 +198,7 @@ timing information"
"\"\n"
</line>
<!-- Start fitter -->
<line name="quartus_run_synth"
<line name="quartus_run_pace_and_route"
dest="QuartusConsole"
mark="``"
sep="\n"
......@@ -198,12 +219,19 @@ timing information"
"}"
"if {[catch {execute_module -tool fit -args $par_args} result]} {"
"puts \"Result: $result\""
"puts \"ERROR: Place and route faild. See the report file.\""
"puts \"Error: Place and route faild. See the report file.\""
"} else {"
"puts \"INFO: Place and route was successful.\""
"puts \"Info: Place and route was successful.\""
"}"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
......
tools/Altera_Quartus/quartus_pow.xml 0 → 100644
View file @ 97b4083b
<?xml version="1.0" encoding="UTF-8"?>
<!--
/*******************************************************************************
* Copyright (c) 2015 Elphel, Inc.
* This file is a part of VDT plug-in.
* VDT plug-in is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VDT plug-in is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with Eclipse or Eclipse plugins (or a modified version of those libraries),
* containing parts covered by the terms of EPL/CPL, the licensors of this
* Program grant you additional permission to convey the resulting work.
* {Corresponding Source for a non-source form of such a combination shall
* include the source code for the parts of Eclipse or Eclipse plugins used
* as well as that of the covered work.}
*******************************************************************************/
-->
<vdt-project>
<interface name="QuartusPowInterface" extends="QuartusInterface">
<syntax name="InputFileListSyntax" format="%(--%%ParamName=%%ParamValue%| %)"/>
<typedef name="ToggleRateType">
<paramtype kind="enum" base="String">
<item value="Percent" label="Specify toggle rate in percent"/>
<item value="Transitions per second" label="Specify toggle rate in transitions per second"/>
</paramtype>
</typedef>
<typedef name="InputFileType">
<paramtype kind="enum" base="String">
<item value="SAF" label="Use the specified Signal Activity File (.saf) as input. The SAF contains toggle rates and static probabilities for
output signals in the design"/>
<item value="VCD" label="Use the specified Value Change Dum p(.vcd) as input"/>
<item value="No input" label="Option to instruct the Power Analyzer not to use an input file
to initialize the toggle rates and static probabilities for output signals in the design"/>
</paramtype>
</typedef>
</interface>
<tool name="QuartusPowerAnalyzer" label="Estimate power consumption"
project="FPGA_project"
interface="QuartusPowInterface"
package="FPGA_package"
shell="/bin/bash"
ignore="%QuartusIgnoreSource"
description="Power analyser estimates thermal dynamic power and thermal static poer consumed by the design"
log-dir="QuartusLogDir"
inherits="QuartusToolPrototype"
disable="DisableTool"
>
<depends-list>
<depends state="QuartusSnapshotPlace"/>
</depends-list>
<action-menu>
<action label="Estimate power consumption" resourse="" icon="fire.png"/>
</action-menu>
<!-- Interface parameters -->
<parameter id="DisableTool" label="Disable autorun" tooltip="Disable automatic launch of this tool"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<parameter id="default_input_io_toggle_rate" label="Default input IO toggle rate in %" tooltip="Option to specify a default toggle rate to be used on input I/O pin
signals during power analysis. This value is used if an input I/O pin's toggle rate is not specified by some other mean such as an input
file or user assignment. To specify a default toggle rate for all other signals in the design use the --default_toggle_rate command line option"
type="String" default="" omit="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="default_toggle_rate" label="Default toggle rate in %" tooltip="Option to specify a default toggle rate to be used for all output
signals except input I/O pin signals during power analysis. This value is used if a signal's toggle rate is not specified by some other mean such as
an input file or user assignment and vectorless estimation should not be used"
type="String" default="" omit="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="estimate_power" label="Estimate power" tooltip="Specifying a value of 'off' reduces processing time. For example,
specify the value 'off' for this option if the only desired action is to process a Value Change Dump (VCD) file to produce a Signal Activity File (SAF).
By default, a power estimate is produced"
type="Bool_on_off" default="true" omit="true" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="input_file_type" label="Input file type" tooltip="Select the type of input file. Input file will not be used in case you select 'No file'"
type="InputFileType" default="No input" visible="true" readonly="false" format="None"/>
<parameter id="input_saf" label="Input SAF file" tooltip="Select input SAF file"
type="Filename" default="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="input_vcd" label="Input VCD file" tooltip="Select input VCD file(s)"
type="Filelist" default="" visible="true" readonly="false" format="InputFileListSyntax"/>
<parameter id="output_epe" label="Output Early Power Estimation file" tooltip="Option to write an Early Power Estimation file, summarizing the resources used by
the design. The file can be used to import design information into the PowerPlay Early Power Estimator spreadsheet available from the Altera website"
type="Filename" default="" omit="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="output_saf" label="Output SAF file" tooltip="Option to write out the toggle rates and static probabilities used by the Power Analyzer during the power
analysis to the specified Signal Activity File (.saf)"
type="Filename" default="" omit="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="vcd_filter_glitches" label="Use glitch filtering when reading VCD" tooltip="Option to use glitch filtering when reading VCD Files (.vcd) as input"
type="Bool_on_off" default="true" omit="true" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="voltage" label="Voltage" tooltip="Option to specify the device voltage (mV) when running the PowerPlay Power Analyzer"
type="String" default="" omit="" visible="true" readonly="false" format="DoubleDash"/>
<parameter id="lower_priority" label="Lower priority" tooltip="Option to lower priority of the current process"
default="false" visible="true" readonly="false" omit="false" type="Boolean" format="DoubleDashName"/>
<parameter id="use_vectorless_estimation" label="Use vectorless estimation" tooltip="Option to specify whether or not vectorless estimation should be used to
calculate unspecified toggle rates and static probabilities for the output signals in the design. If set to 'on' then vectorless estimation is used by the PowerPlay Power
Analyzer and the --default_toggle_rate command line option or the value stored in the Quartus II Settings File (.qsf) will be ignored. If set to 'off' then the
PowerPlay Power Analyzer uses the value specified by the command line option --default_toggle_rate or the value stored in the Quartus Settings File (.qsf) as the default toggle rate"
default="false" visible="true" readonly="false" type="Boolean" format="DoubleDashName"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<input>
<group name="General">
"DisableTool"
"use_vectorless_estimation"
"default_input_io_toggle_rate"
"default_toggle_rate"
"estimate_power"
"input_file_type"
"input_saf"
"input_vcd"
"output_epe"
"output_saf"
"vcd_filter_glitches"
"voltage"
"lower_priority"
</group>
</input>
<output>
<!-- Assemble quartus_pow arguments line -->
<line name="quartus_assemble_args"
dest="QuartusConsole"
sep=" ">
"set pow_args \""
<if-not default_input_io_toggle_rate="">
"%default_input_io_toggle_rate%"
</if-not>
<if-not use_vectorless_estimation="true">
<if-not default_toggle_rate="">
"%default_toggle_rate%"
</if-not>
</if-not>
<if use_vectorless_estimation="true">
"%use_vectorless_estimation"
</if>
"%estimate_power"
"%lower_priority"
<if input_file_type="SAF">
<if-not input_saf="">
"%input_saf"
</if-not>
</if>
<if input_file_type="VCD">
<if-not input_vcd="">
"%input_vcd"
</if-not>
</if>
<if input_file_type="No file">
"--no_input_file"
</if>
"%output_epe"
"%output_saf"
"%vcd_filter_glitches"
"%voltage"
"\"\n"
</line>
<!-- Start power optimiser-->
<line name="quartus_run_pow"
dest="QuartusConsole"
mark="``"
sep="\n"
prompt="@@FINISH@@"
success="@@FINISH@@"
log=""
stdout="parser_Quartus">
"cd ~/%QuartusProjectRoot"
"set projectName %%ProjectName"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"load_package flow"
<!-- Reopen project if it was closed somehow -->
"if [is_project_open] {"
"puts \"Project is open, starting power optimiser\""
"} else {"
"project_open $projectName"
"}"
"if {[catch {execute_module -tool pow -args $pow_args} result]} {"
"puts \"Result: $result\""
"puts \"Error: Power optimiser faild. See the report file.\""
"} else {"
"puts \"Info: Power optimiser finished successfully.\""
"}"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
</vdt-project>
tools/Altera_Quartus/quartus_proto.xml
View file @ 97b4083b
......@@ -35,5 +35,95 @@
description="Quartus tool prototype"
abstract="true"
>
<!-- parser parameters -->
<parameter id="PatternErrors" label="Errors" tooltip="Regular expression for error messages"
default=".*(Error:)(.*)\[(.*):([0-9]+)\]"
visible="true" type="String" format="CopyValue"/>
<parameter id="PatternWarnings" label="Warnings" tooltip="Regular expression for warnings messages"
default=".*(Warning:|Critical Warning:)(.*)\[(.*):([0-9]+)\]"
visible="true" type="String" format="CopyValue"/>
<parameter id="PatternInfo" label="Info" tooltip="Regular expression for info messages"
default=".*(Info:)(.*)\[(.*):([0-9]+)\]"
visible="true" type="String" format="CopyValue"/>
<parameter id="InstanceCapture" label="Instance capture"
tooltip="Regular expression to extract hierarchical instance name (outer '()' enclose the hierarchical name itself)"
default="((([#a-zA-Z_$]([a-zA-Z_$0-9]|\[[0-9:]+\])*)(\.|:))+([a-zA-Z_$]([a-zA-Z_$0-9]|\[[0-9:]+\])*))"
visible="true" type="String" format="CopyValue"/>
<parameter id="InstanceSeparator" label="Instance separator"
tooltip="Regular expression to extract hierarchical name separator, for literal '.' it is '\.'"
default="\."
visible="true" type="String" format="CopyValue"/>
<parameter id="InstanceSuffix" label="Instance suffix"
tooltip="Regular expression to match/remove name suffixes automatically added by the tools"
default="_reg|__parameterized[0-9]*"
visible="true" type="String" format="CopyValue"/>
<parameter id="ShowWarnings" label="Show Warnings" tooltip="Parse warning messages"
default="true" type="Boolean" format="None"/>
<parameter id="ShowInfo" label="Show info" tooltip="Parse info messages"
default="true" type="Boolean" format="None"/>
<parameter id="PreGrepW" visible="false"
type="String" format="None" default="?%ShowWarnings=true: |Warning, "/>
<parameter id="PreGrepI" visible="false"
type="String" format="None" default="?%ShowInfo=true: |Info, "/>
<parameter id="GrepEWI" label="Grep filter" tooltip="Calculated grep filter"
default="grep --line-buffered -E 'Error|CRITICAL WARNING%PreGrepW%PreGrepI'"
type="String" format="CopyValue" visible="true" readonly="true"/>
<parameter id="MaxMsg" outid="set_param messaging.defaultLimit" label="Maximal messages" tooltip="Maximum number of messages to output (per type)"
default="1000" visible="true" omit="100" type="Cardinal" format="NameValue"/>
<parameter id="parser_mode" label="Parser mode" tooltip="Parser mode (consolidation of bits of the same instance)"
default="1" visible="true" omit="" type="ParserModeType" format="CmdLineParameterSyntax"/>
<parameter id="parsers_path" label="Parsers Path" tooltip="parsers directory in plugins"
default="%%ParsersPath" visible="true" omit="" type="String" format="CopyValue"/>
<parameter id="parser_name" label="Quartus parser name" tooltip="Quartus output parser script path"
default="parser_quartus.py" visible="true" omit="" type="String" format="CopyValue"/>
<parameter id="include_msg_id" label="Include message ID" tooltip="Include message ID to output"
type="Boolean" default="true" visible="true" readonly="false" format="CmdLineParameterSyntax"/>
<parameter id="exclude_id_list" label="Exclude message ID" tooltip="Exclude messages with these IDs from output"
type="Stringlist" default="" visible="true" readnonly="false" omit="" format="MsgIdList"/>
<parameter id="disable_exclude_list" label="Disable exclude list" tooltip="This option allows temporary disable exclude ID list"
type="Boolean" default="false" visible="true" readonly="false" omit="false" format="CmdLineParameterSyntax"/>
<!-- Invisible parameters-->
<parameter id="tool_name" type="String" default="%%ToolName" visible="false" format="CmdLineParameterSyntax"/>
<parameter id="top_module" type="String" default="%%TopModule" visible="false" format="CmdLineParameterSyntax"/>
<input>
<group name="Parser" weight="10">
"parsers_path"
"parser_name"
"---"
"ShowWarnings"
"ShowInfo"
"MaxMsg"
"GrepEWI"
"---"
"include_msg_id"
"exclude_id_list"
"disable_exclude_list"
"---"
"PatternErrors"
"PatternWarnings"
"PatternInfo"
"InstanceCapture"
"InstanceSeparator"
"InstanceSuffix"
"parser_mode"
</group>
</input>
<output>
<line name="parser_Quartus"
errors="PatternErrors"
warnings="PatternWarnings"
info="PatternInfo"
instance-capture="InstanceCapture"
instance-separator="InstanceSeparator"
instance-suffix="InstanceSuffix">
"-c"
"python -u %parsers_path%parser_name %tool_name %top_module %parser_mode %include_msg_id %exclude_id_list %disable_exclude_list | "
"%GrepEWI"
</line>
</output>
</tool>
</vdt-project>
tools/Altera_Quartus/quartus_synthesis.xml
View file @ 97b4083b
......@@ -28,7 +28,6 @@
-->
<vdt-project>
<interface name="QuartusSynthesisInterface" extends="QuartusInterface">
<syntax name="read_qdc_syntax" format="%(read_qdc %%ParamValue%|\n%)" />
<typedef name="FSMType">
<paramtype kind="enum" base="String">
<item value="auto" label="Allows Analysis and Synthesis to choose the best encoding for the state machine."/>
......@@ -85,11 +84,15 @@ may decrease as fast-synthesis netlists take longer to route."/>
<depends files="FilteredSourceListPar"/>
<depends files="FilteredIncludesListPar"/>
<depends files="ConstraintsFiles"/>
<depends files="PinAssignment"/>
</depends-list>
<action-menu>
<action label="Synthesise with Quartus" resourse="%ImplementationTopFile"
check-extension="false" check-existance="true" icon="Retort.png"/>
<action label="Check by Quartus" resource="%ImplementationTopFile"
check-extension="false" check-existance="true" icon="IconTestTube.png"/>
</action-menu>
<parameter id="analysis_and_elaboration" label="Analysis and elaboration" tooltip= "Option to check all the design files in a design for syntax and
semantec errors, and perform a netlist exraction."
default="false" visible="true" readonly="false" omit="false" type="Boolean" format="DoubleDashName"/>
<parameter id="effort" label="Synthesis effort" tooltip="Option to select synthesis effort level"
default="auto" visible="true" readonly="false" omit="auto" type="SynthesisEffort" format="DoubleDash"/>
<parameter id="family" outid="family" label="Device family" tooltip= "Option to target the specified device family. The family name should not contain any
......@@ -117,17 +120,15 @@ Note: this feature is not licenced for the Web Edition and this parameter should
<parameter id="top" label="Design top module" tooltip= "Top module of the design, determined by the project top file"
default="%%TopModule" visible="true" omit="" readonly="true" type="String" format="Dash"/>
<parameter id="read_qdc" type="Filelist"
format="read_qdc_syntax" default="%ConstraintsFiles" visible="false" />
<parameter id="FilteredSourceListPar" type="Filelist" label="FilteredSourceListPar"
format="ParamListSyntax" default="%%FilteredSourceList" readonly="false" visible="true" />
format="ParamListSyntax" default="%%FilteredSourceList" readonly="false" visible="true"/>
<parameter id="FilteredIncludesListPar" type="Filelist" label="FilteredIncludesListPar"
format="ParamListSyntax" default="%%FilteredIncludesList" readonly="false" visible="true" />
<parameter id="QuartusSynthActionIndex" default="%%ChosenActionIndex"
type="String" format="CopyValue" visible="false" />
format="ParamListSyntax" default="%%FilteredIncludesList" readonly="false" visible="true"/>
<parameter id="ConstraintsFiles" type="Filelist" format="ParamListSyntax"
default="" label="Constraints files" tooltip="Select constraint files to load to Quartus" readonly="false"
visible="true" />
visible="true"/>
<parameter id="PinAssignment" label="Pin assignment file" tooltip="Select pin assignment Tcl script to load to Quartus project"
type="Filename" default="" visible="true" readonly="false" format="ParamListSyntax"/>
<parameter id="AutosaveQuartusSynthesis" label="Create snapshot" tooltip="Automatically create snapshot after successful synthesis"
default="true" type= "Boolean" format="None"/>
......@@ -137,13 +138,41 @@ Note: this feature is not licenced for the Web Edition and this parameter should
default="false" type= "Boolean" format="None"/>
<parameter id="PreTCL" label="Pre-synthesis TCL commands" tooltip="TCL commands to run before synthesis"
type="Stringlist" format="ProgramSyntax" default="" omit=""
readonly="false" visible="true" />
readonly="false" visible="true"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<!-- invisible or calculated parameters -->
<parameter id="analysis_and_elaboration" label="Analysis and elaboration" tooltip="Option to check all the design files in a design for syntax and
semantec errors, and perform a netlist exraction."
default="true" visible="false" readonly="false" omit="" type="Boolean" format="DoubleDashName"/>
<parameter id="QuartusSynthActionIndex" default="%%ChosenActionIndex"
type="String" format="CopyValue" visible="false"/>
<input>
<group name="General">
"FilteredSourceListPar"
"FilteredIncludesListPar"
"ConstraintsFiles"
"PinAssignment"
"AutosaveQuartusSynthesis"
"QuartusSnapshotSynth" <!-- same as in project -->
"ResetProject"
......@@ -152,7 +181,6 @@ Note: this feature is not licenced for the Web Edition and this parameter should
"PreTCL"
</group>
<group name="Synthesis">
"analysis_and_elaboration"
"effort"
"family"
"part_synth"
......@@ -182,6 +210,7 @@ Note: this feature is not licenced for the Web Edition and this parameter should
"%FilteredIncludesListPar"
<if QuartusSynthActionIndex="0">
"%ConstraintsFiles"
"%PinAssignment"
</if>
"%RemoteUser@%RemoteHost:%QuartusProjectRoot"
</line>
......@@ -190,18 +219,22 @@ Note: this feature is not licenced for the Web Edition and this parameter should
dest="QuartusConsole"
sep=" ">
"set synth_args \""
"%part_synth"
"%family"
"%analysis_and_elaboration"
"%effort"
"%ignore_carry_buffers"
"%ignore_cascade_buffers"
"%incremental_compilation"
"%lower_priority"
"%optimize"
"%parallel"
"%state_machine_encoding"
"\"\n"
<if QuartusSynthActionIndex="0">
"%part_synth"
"%family"
"%effort"
"%ignore_carry_buffers"
"%ignore_cascade_buffers"
"%incremental_compilation"
"%lower_priority"
"%optimize"
"%state_machine_encoding"
</if>
<if QuartusSynthActionIndex="1">
"%analysis_and_elaboration"
</if>
"\""
</line>
<line name="quartus_run_synth"
dest="QuartusConsole"
......@@ -219,20 +252,37 @@ Note: this feature is not licenced for the Web Edition and this parameter should
<!-- Load all project files -->
<if ResetProject="true">
"if [is_project_open] { project_close }"
"project_new $projectName -overwrite"
</if>
"if [project_exists $projectName] {"
"project_open $projectName"
"} else {"
"project_new $projectName }"
<!--"set_global_assignment -name VERILOG_FILE %ImplementationTopFile"-->
"set_global_assignment -name TOP_LEVEL_ENTITY %ImplementationTopModule"
"foreach file [list %FilteredSourceListPar] {"
"puts \"Adding $file to project\""
"set_global_assignment -name VERILOG_FILE $file }"
<!-- Add pin assignment to project -->
<if QuartusSynthActionIndex="0">
<if-not PinAssignment="">
"source %PinAssignment"
</if-not>
<if PinAssignment="">
"puts \"No pin assignment file specified\""
</if>
</if>
<!-- Add constraints file(s) to project
Note: the alternative way of adding constraints is through 'read_sdc' Tcl command but
it is supported in quartus_fit and quartus_sta only -->
<if QuartusSynthActionIndex="0">
<if ConstraintsFiles="">
"puts \"No constraints files specified, skipping read_qdc command\";"
"puts \"No constraints files specified\""
</if>
<if-not ConstraintsFiles="">
"%read_qdc"
"foreach file [list %ConstraintsFiles] {"
"puts \"Adding constraints file $file to project\""
"set_global_assignment -name SDC_FILE $file }"
</if-not>
</if>
<!-- Run pre-synthesis TCL commands (if specified) -->
......@@ -247,15 +297,22 @@ Note: this feature is not licenced for the Web Edition and this parameter should
<!-- Start synthesizer -->
"if {[catch {execute_module -tool map -args $synth_args} result]} {"
"puts \"Result: $result\""
"puts \"ERROR: Analysis and Synthesis faild. See the report file.\""
"puts \"Error: Analysis and Synthesis faild. See the report file.\""
"} else {"
"puts \"INFO: Analysis and Synthesis was successful.\""
"puts \"Info: Analysis and Synthesis was successful.\""
"}"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
<!-- Restore tool for QuartusSynthesis -->
<tool name="RestoreQuartusSynthesis"
project="FPGA_project"
......@@ -263,10 +320,10 @@ Note: this feature is not licenced for the Web Edition and this parameter should
package="FPGA_package"
inherits="RestoreQuartus"/>
<!-- Save tool for QuartusSynthesis -->
<tool name="SaveQuartusSynthesis"
project="FPGA_project"
interface="QuartusInterface"
package="FPGA_package"
inherits="SaveQuartus"/>
</vdt-project>
tools/Altera_Quartus/quartus_timing_analyzer.xml 0 → 100644
View file @ 97b4083b
<?xml version="1.0" encoding="UTF-8"?>
<!--
/*******************************************************************************
* Copyright (c) 2015 Elphel, Inc.
* This file is a part of VDT plug-in.
* VDT plug-in is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VDT plug-in is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with Eclipse or Eclipse plugins (or a modified version of those libraries),
* containing parts covered by the terms of EPL/CPL, the licensors of this
* Program grant you additional permission to convey the resulting work.
* {Corresponding Source for a non-source form of such a combination shall
* include the source code for the parts of Eclipse or Eclipse plugins used
* as well as that of the covered work.}
*******************************************************************************/
-->
<vdt-project>
<interface name="QuartusTimequestInterface" extends="QuartusInterface">
<typedef name="TemperatureGradeType">
<paramtype kind="enum" base="String">
<item value="i" label="Industrial grade (-40℃ to 100℃)"/>
<item value="c" label="Commercial grade (0℃ to 85℃)"/>
<item value="m" label="Military grade (-55℃ to 125℃)"/>
<item value="e" label="Extended grade (-40℃ to 125℃)"/>
<item value="a" label="Automotive grade (-40℃ to 125℃)"/>
</paramtype>
</typedef>
<typedef name="TimingModelType">
<paramtype kind="enum" base="String">
<item value="fast" label="Fast corner delay model"/>
<item value="slow" label="Slow corner delay model"/>
</paramtype>
</typedef>
<typedef name="TemperatureRange">
<paramtype kind="number" lo="-55" hi="125" format="%d"/>
</typedef>
</interface>
<tool name="QuartusTimequest" label="Timing analizer interface"
project="FPGA_project"
interface="QuartusTimequestInterface"
package="FPGA_package"
shell="/bin/bash"
description="Quartus static timing analyzer"
log-dir="QuartusLogDir"
state-dir="QuartusLocalDir"
inherits="QuartusToolPrototype"
disable="DisableTool"
>
<depends-list>
<depends state="QuartusSnapshotPlace"/>
</depends-list>
<action-menu>
<action label="Run timing analizer" resourse="" icon="clock.png"/>
</action-menu>
<!-- General parameters-->
<parameter id="DisableTool" label="Disable autorun" tooltip="Disable automatic launch of this tool"
type="Boolean" default="false" visible="true" readonly="false" format="None"/>
<!-- Command line parameters -->
<parameter id="lower_priority" label="Lower priority" tooltip="Option to lower priority of the current process."
type="Boolean" default="false" visible="true" readonly="false" omit="false" format="DoubleDashName"/>
<parameter id="parallel" label="# of processors to use" tooltip="Controls parallel compilation. If 0 is specified, the Quartus software
uses all processors detected on the system. Otherwise, the software attempts to use the specified number of processors.
Note: this feature is not licenced for the Web Edition and this parameter should be set to 1"
type="Cardinal" default="1" visible="true" readonly="false" omit="0" format="DoubleDash"/>
<parameter id="do_report_timing" label="Do report timing" tooltip="For every clock domain, this option reports the most critical
path based on setup slack. This command is equivalent to:&#xD;
report_timing -npaths 1 -to_clock $clock&#xD;
for every clock in the design (where $clock is the clock name)"
type="Boolean" default="false" visible="true" readonly="false" omit="false" format="DoubleDashName"/>
<parameter id="force_dat" label="Force delay annotation" tooltip="Using this option runs the Delay
Annotator and new delays are annotated on the compiler netlist. The compiler netlist is the source from which a timing netlist
is created. This option therefore ensures that new delays are used in the timing netlist. If this option is not set, the
default flow attempts to re-use existing delays in the compiler netlist (if available)"
type="Boolean" default="false" visible="true" readonly="false" omit="false" format="DoubleDashName"/>
<parameter id="grade" label="Temperature grade" tooltip="Option to specify the device temperature grade to use when running
the TimeQuest Timing Analyzer. This option is provided to support what-if analysis and is not recommended for final sign-off analysis"
type="TemperatureGradeType" default="i" visible="true" readonly="false" omit="i" format="DoubleDash"/>
<parameter id="model" label="Timing model" tooltip="Option to specify the timing model to use when running
the TimeQuest Timing Analyzer"
type="TimingModelType" default="fast" visible="true" readonly="false" omit="fast" format="DoubleDash"/>
<parameter id="multicorner" label="Multicorner" tooltip="Creates slack summaries for all available operating conditions,
enabling multi-corner timing analysis"
type="Boolean" default="true" visible="true" readonly="false" omit="true" format="DoubleDashName"/>
<parameter id="report_script" label="Report script" tooltip="Name of the custom Tcl script called at the end of
the default script, but before the netlist is destoryed. The behavior of the default script is equivalent to the
following if this option is specified:&#xD;
project_open 'rev'&#xD;
create_timing_netlist 'options'&#xD;
read_sdc if defined&#xD;
update_timing_netlist&#xD;
create summary panels&#xD;
&#xD;
# The custom script is loaded here&#xD;
source 'script_name'&#xD;
&#xD;
delete_netlist&#xD;
project_close"
type="Filename" default="" visible="true" readonly="false" omit="" format="DoubleDashName"/>
<parameter id="sdc" label="SDC file to read" tooltip="Name of the SDC File to read. If this option is not specified,
the TimeQuest Timing Analyzer reads the default 'rev'.sdc file if it exists"
type="Filename" default="" visible="true" readonly="false" omit="" format="DoubleDashName"/>
<parameter id="speed" label="Speed grade" tooltip="Option to specify the device speed grade to use when running
the TimeQuest Timing Analyzer"
type="Cardinal_1" default="" visible="true" readonly="false" omit="" format="DoubleDash"/>
<parameter id="temperature" label="Temperature" tooltip="Option to specify the device temperature ℃ to use when running
the TimeQuest Timing Analyzer"
type="TemperatureRange" default="" visible="true" readonly="false" omit="" format="DoubleDashName"/>
<parameter id="voltage" label="Voltage" tooltip="Option to specify the device voltage (mV) to use when running
the TimeQuest Timing Analyzer"
type="Cardinal" default="" visible="true" readonly="false" omit="" format="DoubleDashName"/>
<!-- parser parameters, these can differ from base tool and will be stored separately -->
<parameter id="PatternErrors"/>
<parameter id="PatternWarnings"/>
<parameter id="PatternInfo"/>
<parameter id="InstanceCapture"/>
<parameter id="InstanceSeparator"/>
<parameter id="InstanceSuffix"/>
<parameter id="ShowWarnings"/>
<parameter id="ShowInfo"/>
<parameter id="PreGrepW"/>
<parameter id="PreGrepI"/>
<parameter id="GrepEWI"/>
<parameter id="MaxMsg"/>
<parameter id="parser_mode"/>
<parameter id="parsers_path"/>
<parameter id="parser_name"/>
<parameter id="include_msg_id"/>
<parameter id="exclude_id_list"/>
<parameter id="disable_exclude_list"/>
<input>
<group name="General">
"DisableTool"
</group>
<group name="Timing analizer">
"lower_priority"
"parallel"
"do_report_timing"
"force_dat"
"multicorner"
"model"
"grade"
"report_script"
"sdc"
"speed"
"temperature"
"voltage"
</group>
</input>
<output>
<!-- Assemble quartus_sta arguments line -->
<line name="quartus_assemble_args"
dest="QuartusConsole"
sep=" ">
"set sta_args \""
"%do_report_timing"
"%force_dat"
"%grade"
"%lower_priority"
"%model"
"%multicorner"
"%parallel"
"%report_script"
"%sdc"
"%speed"
"%temperature"
"%voltage"
"\""
</line>
<!-- Start timing analyze r-->
<line name="quartus_run_timing_analyser"
dest="QuartusConsole"
mark="``"
sep="\n"
prompt="@@FINISH@@"
success="@@FINISH@@"
log=""
stdout="parser_Quartus">
"cd ~/%QuartusProjectRoot"
"set projectName %%ProjectName"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"load_package flow"
<!-- Reopen project if it was closed somehow -->
"if [is_project_open] {"
"puts \"Project is open, starting timing analizer\""
"} else {"
"project_open $projectName"
"}"
"if {[catch {execute_module -tool sta -args $sta_args} result]} {"
"puts \"Result: $result\""
"puts \"Error: Timing analizer faild. See the report file.\""
"} else {"
"puts \"Info: Timing analysis was successful.\""
"}"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_reports">
"-c"
"mkdir -p %QuartusLocalResultDir ;"
"rsync -av -e ssh"
"%RemoteUser@%RemoteHost:%QuartusProjectRoot/*.rpt"
"%QuartusLocalResultDir/"
</line>
</output>
</tool>
</vdt-project>
tools/DesignMenu.xml
View file @ 97b4083b
......@@ -46,8 +46,8 @@
call="iverilog"/>
</menu>
<menu name="ISE"
label="Xilinx ISE Tools"
icon="ise_logo.png">
label="ISE Tools"
icon="xilinx.png">
<menu name="ISE_utils"
label="ISE utilities"
icon="setup.png">
......@@ -99,7 +99,7 @@
</menu>
<menu name="Vivado"
label="Xilinx Vivado Tools"
label="Vivado Tools"
icon="vivado_logo.png">
<menu name="VivadoUtils"
label="Vivado utilities"
......@@ -183,7 +183,7 @@
call="VivadoBitstream"/>
</menu>
<menu name="Quartus"
label="Altera Quartus tools"
label="Quartus tools"
icon="quartus16x16.png">
<menuitem name="Quartus Server"
label="Start remote Quartus session"
......@@ -197,9 +197,23 @@
label="Place and route design"
icon="route66.png"
call="QuartusPlace"/>
<menuitem name="QuartusTimeQuest"
label="Timing analizer"
icon="clock.png"
call="QuartusTimequest"/>
<menuitem name="QuartusPowerAnalizer"
label="Estimate power comsumption"
icon="fire.png"
call="QuartusPowerAnalyzer"/>
<menuitem name="QuartusDrc"
label="Check Design"
icon="check.png"
call="QuartusDrc"/>
<menuitem name="QuartusAssembler"
label="Generate bitsream"
icon="bitstream.png"
call="QuartusAssembler"/>
</menu>
</menu>
<menu name="MainDesignMenu2"
......
tools/FPGA_project.xml
View file @ 97b4083b
......@@ -245,6 +245,8 @@
type="String" default="" format="CopyValue" readonly="false" />
<parameter id="ImplementationTopFile" label="Implementation top file" tooltip="Project file with top implementation module"
type="Filename" default="" format="CopyValue" readonly="false" />
<parameter id="ImplementationTopModule" label="Implementation top module" tooltip="Project top implementation module"
type="String" default="" format="CopyValue" readonly="false" />
<parameter id="SimulDir" label="Simulation directory" tooltip="Project simulation directory"
type="Pathname" default="simulation" format="CopyValue" readonly="false" />
<!-- Vivado parameters -->
......@@ -300,7 +302,7 @@
type="Pathname" default="quartus_state" format="CopyValue" readonly="false" />
<parameter id="QuartusLocalResultDir" label="Local Quartus results directory"
tooltip="Local project subdirectroy for Xilinx Quartus generated result files"
tooltip="Local project subdirectory for Quartus generated result files"
type="Pathname" default="quartus_results" format="CopyValue" readonly="false" />
<parameter id="QuartusLogDir" label="Local Quartus tool logs directory" tooltip="Local project subdirectroy for Quartus tools log files"
......@@ -385,7 +387,6 @@
label="Disable Vivado bitstream" tooltip="Disable tool Vivado bitstream generator"
default="false"
type="Boolean" format="None" />
"" <!-- same as in project -->
<!-- Invisible (calculated) project-wide parameters -->
<parameter id="SimulDirSlash" type="Pathname" visible="false"
......@@ -475,6 +476,7 @@
<group name="General" label="General parameters">
"part"
"ImplementationTopFile"
"ImplementationTopModule"
</group>
<group name="Simulation" label="Simulation properties">
"SimulationTopFile"
......
tools/Verilog/IVerilog.xml
View file @ 97b4083b
......@@ -47,19 +47,19 @@
<syntax name="LogFileSyntax" format="%%ParamValue-%%BuildStamp.log" />
<syntax name="OutFileSyntax" format="%%ParamValue-%%BuildStamp.ivlg" />
<syntax name="LxtFileSyntax" format="%%ParamValue-%%BuildStamp.lxt" />
<syntax name="FstFileSyntax" format="%%ParamValue-%%BuildStamp.fst" />
<syntax name="LogFileLatestSyntax"
format="ln -sf %%ParamValue-%%BuildStamp.log %SimulDir/%%ParamValue-latest.log;" />
<syntax name="OutputFileLatestSyntax"
format="ln -sf %%ParamValue-%%BuildStamp.ivlg %SimulDir/%%ParamValue-latest.ivlg;" />
<syntax name="LxtFileLatestSyntax"
format="ln -sf %%ParamValue-%%BuildStamp.lxt %SimulDir/%%ParamValue-latest.lxt;" />
<syntax name="FstFileLatestSyntax"
format="ln -sf %%ParamValue-%%BuildStamp.fst %SimulDir/%%ParamValue-latest.fst;" />
<!-- include file has target, not link value -->
<syntax name="LxtParamFileSyntax"
format="parameter lxtname=&quot;%%ParamValue-%%BuildStamp.lxt&quot;;" />
<syntax name="FstParamFileSyntax"
format="parameter fstname=&quot;%%ParamValue-%%BuildStamp.fst&quot;;" />
<syntax name="IncludeParamSyntax" format="%(%%ParamValue%|\n%)" />
......@@ -204,8 +204,8 @@
<parameter id="OutFile" label="Simulator intermediate file prefix"
type="String" default="%%CurrentFileBase" format="OutFileSyntax"
readonly="false" />
<parameter id="LxtDumpFile" label="Simulator LXT dump file prefix"
type="String" default="%%CurrentFileBase" format="LxtFileSyntax"
<parameter id="FstDumpFile" label="Simulator FST dump file prefix"
type="String" default="%%CurrentFileBase" format="FstFileSyntax"
readonly="false" />
<parameter id="GTKWaveSavFile" label="GTKWave sav file"
......@@ -260,8 +260,8 @@
<parameter id="iverilog_include_file" default="IVERILOG_INCLUDE.v"
type="Filename" format="CopyValue" visible="false" />
<parameter id="LxtDumpFileParameter" default="%LxtDumpFileFull"
type="String" format="LxtParamFileSyntax" visible="false" />
<parameter id="FstDumpFileParameter" default="%FstDumpFileFull"
type="String" format="FstParamFileSyntax" visible="false" />
<parameter id="LogFileLatest" default="%LogFile"
type="String" format="LogFileLatestSyntax" visible="false" />
......@@ -269,8 +269,8 @@
<parameter id="OutFileLatest" type="String" default="%OutFile"
format="OutputFileLatestSyntax" visible="false" />
<parameter id="LxtDumpFileLatest" default="%LxtDumpFile"
type="String" format="LxtFileLatestSyntax" visible="false" />
<parameter id="FstDumpFileLatest" default="%FstDumpFile"
type="String" format="FstFileLatestSyntax" visible="false" />
<parameter id="LogFileFull" default="%SimulDir/%LogFile"
visible="false" type="String" format="LogFileSyntax"/>
......@@ -278,8 +278,8 @@
<parameter id="OutFileFull" default="%SimulDir/%OutFile"
visible="false" type="String" format="OutFileSyntax"/>
<parameter id="LxtDumpFileFull" default="%SimulDir/%LxtDumpFile"
visible="false" type="String" format="LxtFileSyntax"/>
<parameter id="FstDumpFileFull" default="%SimulDir/%FstDumpFile"
visible="false" type="String" format="FstFileSyntax"/>
<input>
<group name="files" label="Files">
......@@ -313,7 +313,7 @@
"GtkWave_Exe"
"LogFile"
"OutFile"
"LxtDumpFile"
"FstDumpFile"
"GrepFindErr"
"GrepFindErrWarn"
"GrepSkip1"
......@@ -391,20 +391,20 @@
"%VVP_Exe -v"
"%Param_2"
"%OutFileFull"
"-lxt2 "
"-fst "
<if SaveLogsSimulator="true">
"| tee -a"
"%LogFileFull"
</if>
"|| { echo '*** vvp failed ***'; exit 1; } ;"
"%LxtDumpFileLatest"
"%FstDumpFileLatest"
<!-- no trap for GTKWave -->
"trap '' EXIT;"
<!-- "%Param_2" -->
"%Param_3"
<if ShowWaves="true">
"%GtkWave_Exe"
"%LxtDumpFileFull"
"%FstDumpFileFull"
"%GTKWaveSavFile"
"&amp; "
</if>
......@@ -413,7 +413,7 @@
</line>
<line name="IverilogIncludeFile" dest="iverilog_include_file"
sep="\n">
"%LxtDumpFileParameter"
"%FstDumpFileParameter"
"%IncludeParametersList"
</line>
</output>
......
tools/Xilinx_Vivado/vivado_opt.xml
View file @ 97b4083b
......@@ -67,7 +67,9 @@
default="false" type= "Boolean" format="None"/>
<parameter id="SkipOptimization" label="Skip optimize" tooltip="Do not run opt_design"
default="false" type= "Boolean" format="None"/>
<parameter id="SkipSnapshotOpt" label="Skip snapshot" tooltip="Do not create snapshot after Optimization"
default="false"
type= "Boolean" format="None"/>
<parameter id="PreOptTCL" label="Pre-optimize TCL commands" tooltip="TCL commands to run before opt_design"
type="Stringlist" format="ProgramSyntax" default="" omit=""
......@@ -135,7 +137,8 @@
<group name="General">
"SkipPreOptimization"
"SkipOptimization"
"---"
"SkipSnapshotOpt"
"---"
"SnapshotOpt" <!-- same as in project -->
</group>
<group name="Pre-optimization commands">
......
tools/Xilinx_Vivado/vivado_opt_place.xml
View file @ 97b4083b
......@@ -106,7 +106,7 @@
<parameter id="SkipPhysOpt" label="Skip physical optimize" tooltip="Do not run phys_opt_design"
default="false" type= "Boolean" format="None"/>
<parameter id="SkipSnapshotPlace" label="Skip snapshot save" tooltip="Do not create snapshot after placement"
<parameter id="SkipSnapshotOptPlace" label="Skip snapshot save" tooltip="Do not create snapshot after placement optimization"
default="false" type= "Boolean" format="None"/>
......@@ -236,7 +236,7 @@
"SkipPowerOptimization"
"SkipPlacement"
"SkipPhysOpt"
"SkipSnapshotPlace"
"SkipSnapshotOptPlace"
"---"
"SnapshotOptPlace" <!-- same as in project -->
</group>
......
tools/Xilinx_Vivado/vivado_opt_power.xml
View file @ 97b4083b
......@@ -57,7 +57,9 @@
default="false" type= "Boolean" format="None"/>
<parameter id="PreOptTCL" label="Pre-optimize TCL commands" tooltip="TCL commands to run before power_opt_design"
type="Stringlist" format="ProgramSyntax" default="" omit=""
readonly="false" visible="true" />
readonly="false" visible="true" />
<parameter id="SkipSnapshotOptPower" label="Skip snapshot save" tooltip="Do not create snapshot after power optimization"
default="false" type= "Boolean" format="None"/>
<!-- power_opt_design arguments -->
<parameter id="quiet_pwr_opt" outid="quiet" label="Quiet" tooltip= "Ignore errors, return TCL_OK in any case"
default="false" visible="true" omit="false" type="Boolean" format="DashName"/>
......@@ -103,7 +105,8 @@
<input>
<group name="General">
"SkipPreOptimization"
"SkipPowerOptimization"
"SkipPowerOptimization"
"SkipSnapshotOptPower"
"---"
"SnapshotOptPower" <!-- same as in project -->
</group>
......
tools/Xilinx_Vivado/vivado_place.xml
View file @ 97b4083b
......@@ -142,7 +142,8 @@
<input>
<group name="General">
"SkipPreOptimization"
"SkipPlacement"
"SkipPlacement"
"SkipSnapshotPlace"
"---"
"SnapshotPlace" <!-- same as in project -->
</group>
......
tools/Xilinx_Vivado/vivado_route.xml
View file @ 97b4083b
......@@ -148,7 +148,8 @@
<input>
<group name="General">
"SkipPreRoute"
"SkipSnapshotRoute"
"SkipSnapshotRoute"
"---"
"SnapshotRoute" <!-- same as in project -->
</group>
<group name="Pre-routing commands">
......
vdt-veditor.patch
View file @ 97b4083b
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