<itemvalue="Explore"label="Run multiple passes of optimization to improve results."/>
<itemvalue="ExploreArea"label="Run multiple passes of optimization, with an emphasis on reducing area."/>
<itemvalue="ExploreSequentialArea"label="Run multiple passes of optimization, with an emphasis on reducing registers and related combinational logic."/>
<itemvalue="AddRemap"label="Run the default optimization, and include LUT remapping to reduce logic levels."/>
<itemvalue="RuntimeOptimized"label="Run the fewest iterations, trading optimization results for faster runtime."/>
<itemvalue="Default"label=" Run the default optimization."/>
<parameterid="directive_opt"outid="directive"label="Directive"tooltip="Mode of behaviour for opt_design command, not compatible with individual optimization settings."
<parameterid="dsp_register_opt"label="DSP register optimization"tooltip="Improve critical path delay by moving registers from slices to DSP or from DSP to slices."
<parameterid="bram_register_opt"label="BRAM register optimization"tooltip="Improve critical path delay by moving registers from slices to BRAM or from BRAM to slices."
<itemvalue="min_max"label="Analyze both minimal and maximal times"/>
</paramtype>
</typedef>
<typedefname="PathTypeType">
<paramtypekind="enum"base="String">
<itemvalue="end"label="Shows the endpoint of the path only, with calculated timing values."/>
<itemvalue="summary"label="Displays the startpoints and endpoints with slack calculation."/>
<itemvalue="short"label="Displays the startpoints and endpoints with calculated timing values."/>
<itemvalue="full"label="Displays the full timing path, including startpoints, through points, and endpoints."/>
<itemvalue="full_clock"label="Displays full clock paths in addition to the full timing path."/>
<itemvalue="full_clock_expanded"label=" Displays full clock paths between a master clock and generated clocks in addition to the full_clock timing path."/>