removed auto-generated Makefile

README.md

@@ -5,10 +5,16 @@ just added Eclipse/[VDT](https://github.com/Elphel/vdt-plugin) project files so
 
 __These Verilog source files are not related to any of Elphel camera projects.__
 
-Instructions below are preserved from the original (first fork) repo. With [VDT plugin](https://github.com/Elphel/vdt-plugin) you need
-to install the plugin following the instructions and/or video tutorial, then clone this project and open it in VDT. Cocotb
-will be cloned and installed when you first run the simulation from the IDE GUI. Both Icarus simulation with traditional plain
-Verilog testbench and with Cocotb are supported. 
+Instructions below are preserved from the original (first fork) repo. With [VDT plugin](https://github.com/Elphel/vdt-plugin)
+you need to install the plugin following the instructions and/or video tutorial, then clone this project and open it in VDT.
+THe open any of the Verilog source files in the editor and change perspective:
+
+Window -> Perspective -> Open Perspective -> Other... -> Verilog/VHDL
+
+Icarus and Cocotb tools will be available in the bottom-left panel, under "Simulation".
+
+Cocotb will be cloned from the official Github repository and installed when you first run the simulation from the IDE GUI.
+Both Icarus simulation with traditional plain Verilog testbench and with Cocotb are supported. 
 
 [![Documentation Status](https://readthedocs.org/projects/opencores-jpegencoder/badge/?version=latest)](http://opencores-jpegencoder.readthedocs.org/en/latest/)
 [![Build Status](https://api.travis-ci.org/chiggs/oc_jpegencode.png?branch=master)](https://travis-ci.org/chiggs/oc_jpegencode)

cocotb/Makefile

-PROJECT_ROOT=/home/eyesis/git/oc_jpegencode
-TOPLEVEL=jpeg_top
-MODULE = test_jpeg_top
-VERILOG_SOURCES = $(PROJECT_ROOT)/code/jpeg_top.v  \
- $(PROJECT_ROOT)/code/fifo_out.v  \
- $(PROJECT_ROOT)/code/ff_checker.v  \
- $(PROJECT_ROOT)/code/sync_fifo_32.v  \
- $(PROJECT_ROOT)/code/pre_fifo.v  \
- $(PROJECT_ROOT)/code/sync_fifo_ff.v  \
- $(PROJECT_ROOT)/code/cbd_q_h.v  \
- $(PROJECT_ROOT)/code/rgb2ycbcr.v  \
- $(PROJECT_ROOT)/code/yd_q_h.v  \
- $(PROJECT_ROOT)/code/crd_q_h.v  \
- $(PROJECT_ROOT)/code/cr_huff.v  \
- $(PROJECT_ROOT)/code/cr_quantizer.v  \
- $(PROJECT_ROOT)/code/y_quantizer.v  \
- $(PROJECT_ROOT)/code/y_dct.v  \
- $(PROJECT_ROOT)/code/cb_huff.v  \
- $(PROJECT_ROOT)/code/y_huff.v  \
- $(PROJECT_ROOT)/code/cr_dct.v  \
- $(PROJECT_ROOT)/code/cb_quantizer.v  \
- $(PROJECT_ROOT)/code/cb_dct.v
-GUI=0
-SIM=icarus
-COMPILE_ARGS += -DCOCOTB
-COMPILE_ARGS += -DTRACE
-COMPILE_ARGS += -I$(PROJECT_ROOT)
-SIM_ARGS=-fst
-CUSTOM_COMPILE_DEPS = $(PROJECT_ROOT)/IVERILOG_INCLUDE.v
-CUSTOM_COMPILE_DEPS += $(PROJECT_ROOT)/IVERILOG_INCLUDE.v
-COCOTB_ANSI_OUTPUT=1
-COCOTB=/home/eyesis/git/vdt/cocotb
-include $(COCOTB)/makefiles/Makefile.inc
-include $(COCOTB)/makefiles/Makefile.sim
-clean::
-	-@rm -f *.pyc results.xml 
-	-@rm -f *.jpg