updtated project settings to current VDT

.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v
-FPGA_project_1_SimulationTopModule=UUT
-FPGA_project_2_DUTTopFile=code/jpeg_top.v
-FPGA_project_2_ImplementationTopFile=code/jpeg_top.v
-FPGA_project_3_DUTTopModule=jpeg_top
-FPGA_project_3_ImplementationTopModule=jpeg_top
-com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
+FPGA_project_@_DUTTopFile=code/jpeg_top.v
+FPGA_project_@_DUTTopModule=jpeg_top
+FPGA_project_@_ImplementationTopFile=code/jpeg_top.v
+FPGA_project_@_ImplementationTopModule=jpeg_top
+FPGA_project_@_SimulationTopFile=code/jpeg_top_TB.v
+FPGA_project_@_SimulationTopModule=UUT
+com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->
+com.elphel.store.version.FPGA_project=1.0
 eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs

-cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
-cocotb_110_COCOTB_ANSI_OUTPUT=true
-cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@->
-cocotb_113_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@->
-cocotb_116_GTKWaveSavFile=jpeg_top_01.sav
-cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
-cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw
-com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->
+cocotb_@_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
+cocotb_@_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
+cocotb_@_CocotbMODULE=test_jpeg_top<-@\#\#@->
+cocotb_@_GTKWaveSavFile=jpeg_top_01.gtkw
+cocotb_@_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@->
+com.elphel.store.context.cocotb=cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_MakeCleanPatterns<-@\#\#@->cocotb_@_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->
+com.elphel.store.version.cocotb=0.8
 eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_@_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.version.iverilog=1.1
 eclipse.preferences.version=1
-iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw
-iverilog_123_GTKWaveSavFile=jpegencode_01.sav
+iverilog_@_GTKWaveSavFile=jpeg_top_01.gtkw

.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v
-FPGA_project_1_SimulationTopModule=UUT
-FPGA_project_2_DUTTopFile=code/jpeg_top.v
-FPGA_project_2_ImplementationTopFile=code/jpeg_top.v
-FPGA_project_3_DUTTopModule=jpeg_top
-FPGA_project_3_ImplementationTopModule=jpeg_top
-com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
+FPGA_project_@_DUTTopFile=code/jpeg_top.v
+FPGA_project_@_DUTTopModule=jpeg_top
+FPGA_project_@_ImplementationTopFile=code/jpeg_top.v
+FPGA_project_@_ImplementationTopModule=jpeg_top
+FPGA_project_@_SimulationTopFile=code/jpeg_top_TB.v
+FPGA_project_@_SimulationTopModule=UUT
+com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->
+com.elphel.store.version.FPGA_project=1.0
 eclipse.preferences.version=1

.settings/com.elphel.vdt.cocotb.prefs

-cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
-cocotb_110_COCOTB_ANSI_OUTPUT=true
-cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@->
-cocotb_113_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@->
-cocotb_116_GTKWaveSavFile=jpeg_top_01.sav
-cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
-cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw
-com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->
+cocotb_@_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
+cocotb_@_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
+cocotb_@_CocotbMODULE=test_jpeg_top<-@\#\#@->
+cocotb_@_GTKWaveSavFile=jpeg_top_01.gtkw
+cocotb_@_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@->
+com.elphel.store.context.cocotb=cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_MakeCleanPatterns<-@\#\#@->cocotb_@_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->
+com.elphel.store.version.cocotb=0.8
 eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_@_GTKWaveSavFile<-@\#\#@->
+com.elphel.store.version.iverilog=1.1
 eclipse.preferences.version=1
-iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw
-iverilog_123_GTKWaveSavFile=jpegencode_01.sav
+iverilog_@_GTKWaveSavFile=jpeg_top_01.gtkw

cocotb/test_jpeg_top.py

@@ -35,13 +35,12 @@ def compare(i1, i2):
 @cocotb.coroutine
 def process_image(dut, filename="", debug=False, threshold=0.22):
     """Run an image file through the jpeg encoder and compare the result"""
+    cocotb.fork(Clock(dut.clk, 100).start())
+    #Overwriting debug (original) with the one from env
+    debug = os.getenv('COCOTB_DEBUG') # None/1
     yield Timer(10)
-#    cocotb.fork(Clock(dut.clk, 100).start())
-    """
-    driver = ImageDriver(dut)
-    
-    
 
+    driver = ImageDriver(dut)
     monitor = JpegMonitor(dut)
 
     if debug:                                            # pragma: no cover
@@ -62,10 +61,8 @@ def process_image(dut, filename="", debug=False, threshold=0.22):
     if difference > threshold:                           # pragma: no cover
         raise TestFailure("Resulting image file was too different (%f > %f)" %
                           (difference, threshold))
-    """                      
-"""
+
 tf = TestFactory(process_image)
 tf.add_option("filename", [os.path.join('test_images', f)
                             for f in os.listdir('test_images')])
 tf.generate_tests()
\ No newline at end of file
-"""
\ No newline at end of file