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Commit 7dbd4f7c authored Jul 02, 2016 by Andrey Filippov

updtated project settings to current VDT

parent 2bb85ab0

.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs

+8 −7

Original line number	Diff line number	Diff line
		FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v
		FPGA_project_1_SimulationTopModule=UUT
		FPGA_project_2_DUTTopFile=code/jpeg_top.v
		FPGA_project_2_ImplementationTopFile=code/jpeg_top.v
		FPGA_project_3_DUTTopModule=jpeg_top
		FPGA_project_3_ImplementationTopModule=jpeg_top
		com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
		FPGA_project_@_DUTTopFile=code/jpeg_top.v
		FPGA_project_@_DUTTopModule=jpeg_top
		FPGA_project_@_ImplementationTopFile=code/jpeg_top.v
		FPGA_project_@_ImplementationTopModule=jpeg_top
		FPGA_project_@_SimulationTopFile=code/jpeg_top_TB.v
		FPGA_project_@_SimulationTopModule=UUT
		com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->
		com.elphel.store.version.FPGA_project=1.0
		eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs

+7 −8

Original line number	Diff line number	Diff line
		cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
		cocotb_110_COCOTB_ANSI_OUTPUT=true
		cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@->
		cocotb_113_MakeCleanPatterns=.pyc results.xml<-@\#\#@->.jpg<-@\#\#@->
		cocotb_116_GTKWaveSavFile=jpeg_top_01.sav
		cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
		cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw
		com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->
		cocotb_@_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
		cocotb_@_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
		cocotb_@_CocotbMODULE=test_jpeg_top<-@\#\#@->
		cocotb_@_GTKWaveSavFile=jpeg_top_01.gtkw
		cocotb_@_MakeCleanPatterns=.pyc results.xml<-@\#\#@->.jpg<-@\#\#@->
		com.elphel.store.context.cocotb=cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_MakeCleanPatterns<-@\#\#@->cocotb_@_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->
		com.elphel.store.version.cocotb=0.8
		eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs

+3 −3

Original line number	Diff line number	Diff line
		com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->
		com.elphel.store.context.iverilog=iverilog_@_GTKWaveSavFile<-@\#\#@->
		com.elphel.store.version.iverilog=1.1
		eclipse.preferences.version=1
		iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw
		iverilog_123_GTKWaveSavFile=jpegencode_01.sav
		iverilog_@_GTKWaveSavFile=jpeg_top_01.gtkw

.settings/com.elphel.vdt.FPGA_project.prefs

+8 −7

Original line number	Diff line number	Diff line
		FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v
		FPGA_project_1_SimulationTopModule=UUT
		FPGA_project_2_DUTTopFile=code/jpeg_top.v
		FPGA_project_2_ImplementationTopFile=code/jpeg_top.v
		FPGA_project_3_DUTTopModule=jpeg_top
		FPGA_project_3_ImplementationTopModule=jpeg_top
		com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
		FPGA_project_@_DUTTopFile=code/jpeg_top.v
		FPGA_project_@_DUTTopModule=jpeg_top
		FPGA_project_@_ImplementationTopFile=code/jpeg_top.v
		FPGA_project_@_ImplementationTopModule=jpeg_top
		FPGA_project_@_SimulationTopFile=code/jpeg_top_TB.v
		FPGA_project_@_SimulationTopModule=UUT
		com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->
		com.elphel.store.version.FPGA_project=1.0
		eclipse.preferences.version=1

.settings/com.elphel.vdt.cocotb.prefs

+7 −8

Original line number	Diff line number	Diff line
		cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
		cocotb_110_COCOTB_ANSI_OUTPUT=true
		cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@->
		cocotb_113_MakeCleanPatterns=.pyc results.xml<-@\#\#@->.jpg<-@\#\#@->
		cocotb_116_GTKWaveSavFile=jpeg_top_01.sav
		cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
		cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw
		com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->
		cocotb_@_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
		cocotb_@_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
		cocotb_@_CocotbMODULE=test_jpeg_top<-@\#\#@->
		cocotb_@_GTKWaveSavFile=jpeg_top_01.gtkw
		cocotb_@_MakeCleanPatterns=.pyc results.xml<-@\#\#@->.jpg<-@\#\#@->
		com.elphel.store.context.cocotb=cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_MakeCleanPatterns<-@\#\#@->cocotb_@_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->
		com.elphel.store.version.cocotb=0.8
		eclipse.preferences.version=1