Modifying to run cocotb with vdt

.gitignore

+simulation/*
+*.kate-swp
+cocotb/Makefile
+IVERILOG_INCLUDE.v
+*.pyc
+*.fst
+*.vcd
+cocotb/sim_build
+*.directory
\ No newline at end of file

.project

+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>oc_jpegencode</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.python.pydev.pythonNature</nature>
+	</natures>
+</projectDescription>

.settings/com.elphel.vdt.FPGA_project.prefs

+FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v
+FPGA_project_1_SimulationTopModule=UUT
+FPGA_project_2_DUTTopFile=code/jpeg_top.v
+FPGA_project_2_ImplementationTopFile=code/jpeg_top.v
+FPGA_project_3_DUTTopModule=jpeg_top
+FPGA_project_3_ImplementationTopModule=jpeg_top
+com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
+eclipse.preferences.version=1

.settings/com.elphel.vdt.cocotb.prefs

+cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@->
+cocotb_110_COCOTB_ANSI_OUTPUT=true
+cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@->
+cocotb_113_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@->
+cocotb_116_GTKWaveSavFile=jpeg_top_01.sav
+cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@->
+cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw
+com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->
+eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

+com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->
+eclipse.preferences.version=1
+iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw
+iverilog_123_GTKWaveSavFile=jpegencode_01.sav

.settings/com.elphel.vdt.prefs

+com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
+com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
+eclipse.preferences.version=1

README.md

 oc_jpegencode
 =============
+This repository is for of a fork - it is taken from [https://github.com/chiggs/oc_jpegencode](https://github.com/chiggs/oc_jpegencode),
+just added Eclipse/[VDT](https://github.com/Elphel/vdt-plugin) project files so it can be imported into IDE and run there.
+
+__These Verilog source files are not related to any of Elphel camera projects.__
+
+Instructions below are preserved from the original (first fork) repo. With [VDT plugin](https://github.com/Elphel/vdt-plugin) you need
+to install the plugin following the instructions and/or video tutorial, then clone this project and open it in VDT. Cocotb
+will be cloned and installed when you first run the simulation from the IDE GUI. Both Icarus simulation with traditional plain
+Verilog testbench and with Cocotb are supported. 
 
 [![Documentation Status](https://readthedocs.org/projects/opencores-jpegencoder/badge/?version=latest)](http://opencores-jpegencoder.readthedocs.org/en/latest/)
 [![Build Status](https://api.travis-ci.org/chiggs/oc_jpegencode.png?branch=master)](https://travis-ci.org/chiggs/oc_jpegencode)

cocotb/Makefile

+PROJECT_ROOT=/home/eyesis/git/oc_jpegencode
+TOPLEVEL=jpeg_top
+MODULE = test_jpeg_top
+VERILOG_SOURCES = $(PROJECT_ROOT)/code/jpeg_top.v  \
+ $(PROJECT_ROOT)/code/fifo_out.v  \
+ $(PROJECT_ROOT)/code/ff_checker.v  \
+ $(PROJECT_ROOT)/code/sync_fifo_32.v  \
+ $(PROJECT_ROOT)/code/pre_fifo.v  \
+ $(PROJECT_ROOT)/code/sync_fifo_ff.v  \
+ $(PROJECT_ROOT)/code/cbd_q_h.v  \
+ $(PROJECT_ROOT)/code/rgb2ycbcr.v  \
+ $(PROJECT_ROOT)/code/yd_q_h.v  \
+ $(PROJECT_ROOT)/code/crd_q_h.v  \
+ $(PROJECT_ROOT)/code/cr_huff.v  \
+ $(PROJECT_ROOT)/code/cr_quantizer.v  \
+ $(PROJECT_ROOT)/code/y_quantizer.v  \
+ $(PROJECT_ROOT)/code/y_dct.v  \
+ $(PROJECT_ROOT)/code/cb_huff.v  \
+ $(PROJECT_ROOT)/code/y_huff.v  \
+ $(PROJECT_ROOT)/code/cr_dct.v  \
+ $(PROJECT_ROOT)/code/cb_quantizer.v  \
+ $(PROJECT_ROOT)/code/cb_dct.v
+GUI=0
+SIM=icarus
+COMPILE_ARGS += -DCOCOTB
+COMPILE_ARGS += -DTRACE
+COMPILE_ARGS += -I$(PROJECT_ROOT)
+SIM_ARGS=-fst
+CUSTOM_COMPILE_DEPS = $(PROJECT_ROOT)/IVERILOG_INCLUDE.v
+CUSTOM_COMPILE_DEPS += $(PROJECT_ROOT)/IVERILOG_INCLUDE.v
+COCOTB_ANSI_OUTPUT=1
+COCOTB=/home/eyesis/git/vdt/cocotb
+include $(COCOTB)/makefiles/Makefile.inc
+include $(COCOTB)/makefiles/Makefile.sim
+clean::
+	-@rm -f *.pyc results.xml 
+	-@rm -f *.jpg

cocotb/jpeg_top_01.sav

+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Sun Jun 26 02:53:39 2016
+[*]
+[dumpfile] "/home/eyesis/git/oc_jpegencode/simulation/jpeg_top-20160625205117477.fst"
+[dumpfile_mtime] "Sun Jun 26 02:52:00 2016"
+[dumpfile_size] 18246025
+[savefile] "/home/eyesis/git/oc_jpegencode/cocotb/jpeg_top_01.sav"
+[timestart] 0
+[size] 1920 1171
+[pos] -1921 -572
+*-26.305067 3 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] jpeg_top.
+[sst_width] 204
+[signals_width] 286
+[sst_expanded] 1
+[sst_vpaned_height] 345
+@22
+jpeg_top.JPEG_FF[31:0]
+jpeg_top.JPEG_bitstream[31:0]
+@28
+jpeg_top.clk
+@22
+jpeg_top.data_in[23:0]
+@28
+jpeg_top.data_ready
+jpeg_top.data_ready_FF
+jpeg_top.enable
+@22
+jpeg_top.end_of_file_bitstream_count[4:0]
+@28
+jpeg_top.end_of_file_signal
+jpeg_top.eof_data_partial_ready
+@22
+jpeg_top.orc_reg_in[4:0]
+@28
+jpeg_top.rst
+[pattern_trace] 1
+[pattern_trace] 0

code/jpeg_top.v

@@ -42,7 +42,7 @@ last JPEG_bitstream value is written to the signal "end_of_file_bitstream_count"
 */
 
 `timescale 1ns / 100ps
-
+//`define TRACE
 module jpeg_top(clk, rst, end_of_file_signal, enable, data_in, JPEG_bitstream, 
 data_ready, end_of_file_bitstream_count, eof_data_partial_ready);
 input		clk;
@@ -59,7 +59,6 @@ wire [31:0] JPEG_FF;
 wire data_ready_FF;
 wire [4:0] orc_reg_in;
 
-
  fifo_out u19 (.clk(clk), .rst(rst), .enable(enable), .data_in(data_in), 
  .JPEG_bitstream(JPEG_FF), .data_ready(data_ready_FF), .orc_reg(orc_reg_in));
  
@@ -71,9 +70,10 @@ wire [4:0] orc_reg_in;
  .eof_data_partial_ready(eof_data_partial_ready));
 
 `ifdef TRACE
+`include "IVERILOG_INCLUDE.v"
 initial begin
-  $dumpfile ("waveform.vcd");
-  $dumpvars (0,jpeg_top);
+  $dumpfile (fstname);
+  $dumpvars (0,jpeg_top); //SuppressThisWarning VEditor - VDT bug, does not recognize the name of the top module
 end
 `endif
  

jpegencode_01.sav

+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Tue Jun 28 06:01:58 2016
+[*]
+[dumpfile] "/home/eyesis/git/oc_jpegencode/simulation/jpeg_top_TB-20160628000126896.fst"
+[dumpfile_mtime] "Tue Jun 28 06:01:37 2016"
+[dumpfile_size] 4257098
+[savefile] "/home/eyesis/git/oc_jpegencode/jpegencode_01.sav"
+[timestart] 0
+[size] 1000 600
+[pos] 915 108
+*-25.579470 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] jpeg_top_tb.
+[sst_width] 204
+[signals_width] 286
+[sst_expanded] 1
+[sst_vpaned_height] 146
+@22
+jpeg_top_tb.UUT.JPEG_FF[31:0]
+jpeg_top_tb.UUT.JPEG_bitstream[31:0]
+@28
+jpeg_top_tb.UUT.aaaa[2:0]
+jpeg_top_tb.UUT.clk
+@22
+jpeg_top_tb.UUT.data_in[23:0]
+@28
+jpeg_top_tb.UUT.data_ready
+jpeg_top_tb.UUT.data_ready_FF
+jpeg_top_tb.UUT.enable
+@22
+jpeg_top_tb.UUT.end_of_file_bitstream_count[4:0]
+@28
+jpeg_top_tb.UUT.end_of_file_signal
+jpeg_top_tb.UUT.eof_data_partial_ready
+@22
+jpeg_top_tb.UUT.orc_reg_in[4:0]
+@28
+jpeg_top_tb.UUT.rst
+[pattern_trace] 1
+[pattern_trace] 0

tb/Makefile

-TOPLEVEL=jpeg_top
-MODULE=test_jpeg_top
-
-PWD=$(shell pwd)
-VERILOG_SOURCES = $(PWD)/../code/y_huff.v \
-                  $(PWD)/../code/y_quantizer.v \
-                  $(PWD)/../code/y_dct.v \
-                  $(PWD)/../code/cb_huff.v \
-                  $(PWD)/../code/cb_quantizer.v \
-                  $(PWD)/../code/cb_dct.v \
-                  $(PWD)/../code/cr_huff.v \
-                  $(PWD)/../code/cr_quantizer.v \
-                  $(PWD)/../code/cr_dct.v \
-                  $(PWD)/../code/yd_q_h.v \
-                  $(PWD)/../code/cbd_q_h.v \
-                  $(PWD)/../code/crd_q_h.v \
-                  $(PWD)/../code/rgb2ycbcr.v \
-                  $(PWD)/../code/sync_fifo_ff.v \
-                  $(PWD)/../code/sync_fifo_32.v \
-                  $(PWD)/../code/pre_fifo.v \
-                  $(PWD)/../code/ff_checker.v \
-                  $(PWD)/../code/fifo_out.v \
-                  $(PWD)/../code/jpeg_top.v
-
-include $(COCOTB)/makefiles/Makefile.inc
-include $(COCOTB)/makefiles/Makefile.sim
-
-clean::
-	-@rm -f *.pyc
-	-@rm -f *.jpg
-	-@rm -f results.xml