oc_jpegencode
1.0
JPEGencoder
|
Static Public Member Functions |
Public Attributes |
Inputs | |
clk | |
rst | |
enable | |
Cr11 | [ 10 : 0 ] |
Cr12 | [ 10 : 0 ] |
Cr13 | [ 10 : 0 ] |
Cr14 | [ 10 : 0 ] |
Cr15 | [ 10 : 0 ] |
Cr16 | [ 10 : 0 ] |
Cr17 | [ 10 : 0 ] |
Cr18 | [ 10 : 0 ] |
Cr21 | [ 10 : 0 ] |
Cr22 | [ 10 : 0 ] |
Cr23 | [ 10 : 0 ] |
Cr24 | [ 10 : 0 ] |
Cr25 | [ 10 : 0 ] |
Cr26 | [ 10 : 0 ] |
Cr27 | [ 10 : 0 ] |
Cr28 | [ 10 : 0 ] |
Cr31 | [ 10 : 0 ] |
Cr32 | [ 10 : 0 ] |
Cr33 | [ 10 : 0 ] |
Cr34 | [ 10 : 0 ] |
Cr35 | [ 10 : 0 ] |
Cr36 | [ 10 : 0 ] |
Cr37 | [ 10 : 0 ] |
Cr38 | [ 10 : 0 ] |
Cr41 | [ 10 : 0 ] |
Cr42 | [ 10 : 0 ] |
Cr43 | [ 10 : 0 ] |
Cr44 | [ 10 : 0 ] |
Cr45 | [ 10 : 0 ] |
Cr46 | [ 10 : 0 ] |
Cr47 | [ 10 : 0 ] |
Cr48 | [ 10 : 0 ] |
Cr51 | [ 10 : 0 ] |
Cr52 | [ 10 : 0 ] |
Cr53 | [ 10 : 0 ] |
Cr54 | [ 10 : 0 ] |
Cr55 | [ 10 : 0 ] |
Cr56 | [ 10 : 0 ] |
Cr57 | [ 10 : 0 ] |
Cr58 | [ 10 : 0 ] |
Cr61 | [ 10 : 0 ] |
Cr62 | [ 10 : 0 ] |
Cr63 | [ 10 : 0 ] |
Cr64 | [ 10 : 0 ] |
Cr65 | [ 10 : 0 ] |
Cr66 | [ 10 : 0 ] |
Cr67 | [ 10 : 0 ] |
Cr68 | [ 10 : 0 ] |
Cr71 | [ 10 : 0 ] |
Cr72 | [ 10 : 0 ] |
Cr73 | [ 10 : 0 ] |
Cr74 | [ 10 : 0 ] |
Cr75 | [ 10 : 0 ] |
Cr76 | [ 10 : 0 ] |
Cr77 | [ 10 : 0 ] |
Cr78 | [ 10 : 0 ] |
Cr81 | [ 10 : 0 ] |
Cr82 | [ 10 : 0 ] |
Cr83 | [ 10 : 0 ] |
Cr84 | [ 10 : 0 ] |
Cr85 | [ 10 : 0 ] |
Cr86 | [ 10 : 0 ] |
Cr87 | [ 10 : 0 ] |
Cr88 | [ 10 : 0 ] |
Outputs | |
JPEG_bitstream | [ 31 : 0 ] |
data_ready | |
output_reg_count | [ 4 : 0 ] |
end_of_block_empty |
Signals | |
reg[ 7 : 0 ] | block_counter |
reg[ 11 : 0 ] | Cr11_amp |
reg[ 11 : 0 ] | Cr11_1_pos |
reg[ 11 : 0 ] | Cr11_1_neg |
reg[ 11 : 0 ] | Cr11_diff |
reg[ 11 : 0 ] | Cr11_previous |
reg[ 11 : 0 ] | Cr11_1 |
reg[ 10 : 0 ] | Cr12_amp |
reg[ 10 : 0 ] | Cr12_pos |
reg[ 10 : 0 ] | Cr12_neg |
reg[ 10 : 0 ] | Cr21_pos |
reg[ 10 : 0 ] | Cr21_neg |
reg[ 10 : 0 ] | Cr31_pos |
reg[ 10 : 0 ] | Cr31_neg |
reg[ 10 : 0 ] | Cr22_pos |
reg[ 10 : 0 ] | Cr22_neg |
reg[ 10 : 0 ] | Cr13_pos |
reg[ 10 : 0 ] | Cr13_neg |
reg[ 10 : 0 ] | Cr14_pos |
reg[ 10 : 0 ] | Cr14_neg |
reg[ 10 : 0 ] | Cr15_pos |
reg[ 10 : 0 ] | Cr15_neg |
reg[ 10 : 0 ] | Cr16_pos |
reg[ 10 : 0 ] | Cr16_neg |
reg[ 10 : 0 ] | Cr17_pos |
reg[ 10 : 0 ] | Cr17_neg |
reg[ 10 : 0 ] | Cr18_pos |
reg[ 10 : 0 ] | Cr18_neg |
reg[ 10 : 0 ] | Cr23_pos |
reg[ 10 : 0 ] | Cr23_neg |
reg[ 10 : 0 ] | Cr24_pos |
reg[ 10 : 0 ] | Cr24_neg |
reg[ 10 : 0 ] | Cr25_pos |
reg[ 10 : 0 ] | Cr25_neg |
reg[ 10 : 0 ] | Cr26_pos |
reg[ 10 : 0 ] | Cr26_neg |
reg[ 10 : 0 ] | Cr27_pos |
reg[ 10 : 0 ] | Cr27_neg |
reg[ 10 : 0 ] | Cr28_pos |
reg[ 10 : 0 ] | Cr28_neg |
reg[ 10 : 0 ] | Cr32_pos |
reg[ 10 : 0 ] | Cr32_neg |
reg[ 10 : 0 ] | Cr33_pos |
reg[ 10 : 0 ] | Cr33_neg |
reg[ 10 : 0 ] | Cr34_pos |
reg[ 10 : 0 ] | Cr34_neg |
reg[ 10 : 0 ] | Cr35_pos |
reg[ 10 : 0 ] | Cr35_neg |
reg[ 10 : 0 ] | Cr36_pos |
reg[ 10 : 0 ] | Cr36_neg |
reg[ 10 : 0 ] | Cr37_pos |
reg[ 10 : 0 ] | Cr37_neg |
reg[ 10 : 0 ] | Cr38_pos |
reg[ 10 : 0 ] | Cr38_neg |
reg[ 10 : 0 ] | Cr41_pos |
reg[ 10 : 0 ] | Cr41_neg |
reg[ 10 : 0 ] | Cr42_pos |
reg[ 10 : 0 ] | Cr42_neg |
reg[ 10 : 0 ] | Cr43_pos |
reg[ 10 : 0 ] | Cr43_neg |
reg[ 10 : 0 ] | Cr44_pos |
reg[ 10 : 0 ] | Cr44_neg |
reg[ 10 : 0 ] | Cr45_pos |
reg[ 10 : 0 ] | Cr45_neg |
reg[ 10 : 0 ] | Cr46_pos |
reg[ 10 : 0 ] | Cr46_neg |
reg[ 10 : 0 ] | Cr47_pos |
reg[ 10 : 0 ] | Cr47_neg |
reg[ 10 : 0 ] | Cr48_pos |
reg[ 10 : 0 ] | Cr48_neg |
reg[ 10 : 0 ] | Cr51_pos |
reg[ 10 : 0 ] | Cr51_neg |
reg[ 10 : 0 ] | Cr52_pos |
reg[ 10 : 0 ] | Cr52_neg |
reg[ 10 : 0 ] | Cr53_pos |
reg[ 10 : 0 ] | Cr53_neg |
reg[ 10 : 0 ] | Cr54_pos |
reg[ 10 : 0 ] | Cr54_neg |
reg[ 10 : 0 ] | Cr55_pos |
reg[ 10 : 0 ] | Cr55_neg |
reg[ 10 : 0 ] | Cr56_pos |
reg[ 10 : 0 ] | Cr56_neg |
reg[ 10 : 0 ] | Cr57_pos |
reg[ 10 : 0 ] | Cr57_neg |
reg[ 10 : 0 ] | Cr58_pos |
reg[ 10 : 0 ] | Cr58_neg |
reg[ 10 : 0 ] | Cr61_pos |
reg[ 10 : 0 ] | Cr61_neg |
reg[ 10 : 0 ] | Cr62_pos |
reg[ 10 : 0 ] | Cr62_neg |
reg[ 10 : 0 ] | Cr63_pos |
reg[ 10 : 0 ] | Cr63_neg |
reg[ 10 : 0 ] | Cr64_pos |
reg[ 10 : 0 ] | Cr64_neg |
reg[ 10 : 0 ] | Cr65_pos |
reg[ 10 : 0 ] | Cr65_neg |
reg[ 10 : 0 ] | Cr66_pos |
reg[ 10 : 0 ] | Cr66_neg |
reg[ 10 : 0 ] | Cr67_pos |
reg[ 10 : 0 ] | Cr67_neg |
reg[ 10 : 0 ] | Cr68_pos |
reg[ 10 : 0 ] | Cr68_neg |
reg[ 10 : 0 ] | Cr71_pos |
reg[ 10 : 0 ] | Cr71_neg |
reg[ 10 : 0 ] | Cr72_pos |
reg[ 10 : 0 ] | Cr72_neg |
reg[ 10 : 0 ] | Cr73_pos |
reg[ 10 : 0 ] | Cr73_neg |
reg[ 10 : 0 ] | Cr74_pos |
reg[ 10 : 0 ] | Cr74_neg |
reg[ 10 : 0 ] | Cr75_pos |
reg[ 10 : 0 ] | Cr75_neg |
reg[ 10 : 0 ] | Cr76_pos |
reg[ 10 : 0 ] | Cr76_neg |
reg[ 10 : 0 ] | Cr77_pos |
reg[ 10 : 0 ] | Cr77_neg |
reg[ 10 : 0 ] | Cr78_pos |
reg[ 10 : 0 ] | Cr78_neg |
reg[ 10 : 0 ] | Cr81_pos |
reg[ 10 : 0 ] | Cr81_neg |
reg[ 10 : 0 ] | Cr82_pos |
reg[ 10 : 0 ] | Cr82_neg |
reg[ 10 : 0 ] | Cr83_pos |
reg[ 10 : 0 ] | Cr83_neg |
reg[ 10 : 0 ] | Cr84_pos |
reg[ 10 : 0 ] | Cr84_neg |
reg[ 10 : 0 ] | Cr85_pos |
reg[ 10 : 0 ] | Cr85_neg |
reg[ 10 : 0 ] | Cr86_pos |
reg[ 10 : 0 ] | Cr86_neg |
reg[ 10 : 0 ] | Cr87_pos |
reg[ 10 : 0 ] | Cr87_neg |
reg[ 10 : 0 ] | Cr88_pos |
reg[ 10 : 0 ] | Cr88_neg |
reg[ 3 : 0 ] | Cr11_bits_pos |
reg[ 3 : 0 ] | Cr11_bits_neg |
reg[ 3 : 0 ] | Cr11_bits |
reg[ 3 : 0 ] | Cr11_bits_1 |
reg[ 3 : 0 ] | Cr12_bits_pos |
reg[ 3 : 0 ] | Cr12_bits_neg |
reg[ 3 : 0 ] | Cr12_bits |
reg[ 3 : 0 ] | Cr12_bits_1 |
reg[ 3 : 0 ] | Cr12_bits_2 |
reg[ 3 : 0 ] | Cr12_bits_3 |
reg | Cr11_msb |
reg | Cr12_msb |
reg | Cr12_msb_1 |
reg | data_ready |
reg | enable_1 |
reg | enable_2 |
reg | enable_3 |
reg | enable_4 |
reg | enable_5 |
reg | enable_6 |
reg | enable_7 |
reg | enable_8 |
reg | enable_9 |
reg | enable_10 |
reg | enable_11 |
reg | enable_12 |
reg | enable_13 |
reg | enable_module |
reg | enable_latch_7 |
reg | enable_latch_8 |
reg | Cr12_et_zero |
reg | rollover |
reg | rollover_1 |
reg | rollover_2 |
reg | rollover_3 |
reg | rollover_4 |
reg | rollover_5 |
reg | rollover_6 |
reg | rollover_7 |
reg | Cr21_et_zero |
reg | Cr21_msb |
reg | Cr31_et_zero |
reg | Cr31_msb |
reg | Cr22_et_zero |
reg | Cr22_msb |
reg | Cr13_et_zero |
reg | Cr13_msb |
reg | Cr14_et_zero |
reg | Cr14_msb |
reg | Cr15_et_zero |
reg | Cr15_msb |
reg | Cr16_et_zero |
reg | Cr16_msb |
reg | Cr17_et_zero |
reg | Cr17_msb |
reg | Cr18_et_zero |
reg | Cr18_msb |
reg | Cr23_et_zero |
reg | Cr23_msb |
reg | Cr24_et_zero |
reg | Cr24_msb |
reg | Cr25_et_zero |
reg | Cr25_msb |
reg | Cr26_et_zero |
reg | Cr26_msb |
reg | Cr27_et_zero |
reg | Cr27_msb |
reg | Cr28_et_zero |
reg | Cr28_msb |
reg | Cr32_et_zero |
reg | Cr32_msb |
reg | Cr33_et_zero |
reg | Cr33_msb |
reg | Cr34_et_zero |
reg | Cr34_msb |
reg | Cr35_et_zero |
reg | Cr35_msb |
reg | Cr36_et_zero |
reg | Cr36_msb |
reg | Cr37_et_zero |
reg | Cr37_msb |
reg | Cr38_et_zero |
reg | Cr38_msb |
reg | Cr41_et_zero |
reg | Cr41_msb |
reg | Cr42_et_zero |
reg | Cr42_msb |
reg | Cr43_et_zero |
reg | Cr43_msb |
reg | Cr44_et_zero |
reg | Cr44_msb |
reg | Cr45_et_zero |
reg | Cr45_msb |
reg | Cr46_et_zero |
reg | Cr46_msb |
reg | Cr47_et_zero |
reg | Cr47_msb |
reg | Cr48_et_zero |
reg | Cr48_msb |
reg | Cr51_et_zero |
reg | Cr51_msb |
reg | Cr52_et_zero |
reg | Cr52_msb |
reg | Cr53_et_zero |
reg | Cr53_msb |
reg | Cr54_et_zero |
reg | Cr54_msb |
reg | Cr55_et_zero |
reg | Cr55_msb |
reg | Cr56_et_zero |
reg | Cr56_msb |
reg | Cr57_et_zero |
reg | Cr57_msb |
reg | Cr58_et_zero |
reg | Cr58_msb |
reg | Cr61_et_zero |
reg | Cr61_msb |
reg | Cr62_et_zero |
reg | Cr62_msb |
reg | Cr63_et_zero |
reg | Cr63_msb |
reg | Cr64_et_zero |
reg | Cr64_msb |
reg | Cr65_et_zero |
reg | Cr65_msb |
reg | Cr66_et_zero |
reg | Cr66_msb |
reg | Cr67_et_zero |
reg | Cr67_msb |
reg | Cr68_et_zero |
reg | Cr68_msb |
reg | Cr71_et_zero |
reg | Cr71_msb |
reg | Cr72_et_zero |
reg | Cr72_msb |
reg | Cr73_et_zero |
reg | Cr73_msb |
reg | Cr74_et_zero |
reg | Cr74_msb |
reg | Cr75_et_zero |
reg | Cr75_msb |
reg | Cr76_et_zero |
reg | Cr76_msb |
reg | Cr77_et_zero |
reg | Cr77_msb |
reg | Cr78_et_zero |
reg | Cr78_msb |
reg | Cr81_et_zero |
reg | Cr81_msb |
reg | Cr82_et_zero |
reg | Cr82_msb |
reg | Cr83_et_zero |
reg | Cr83_msb |
reg | Cr84_et_zero |
reg | Cr84_msb |
reg | Cr85_et_zero |
reg | Cr85_msb |
reg | Cr86_et_zero |
reg | Cr86_msb |
reg | Cr87_et_zero |
reg | Cr87_msb |
reg | Cr88_et_zero |
reg | Cr88_msb |
reg | Cr12_et_zero_1 |
reg | Cr12_et_zero_2 |
reg | Cr12_et_zero_3 |
reg | Cr12_et_zero_4 |
reg | Cr12_et_zero_5 |
reg[ 10 : 0 ] | Cr_DC [ 11 : 0 ] |
reg[ 3 : 0 ] | Cr_DC_code_length [ 11 : 0 ] |
reg[ 15 : 0 ] | Cr_AC [ 161 : 0 ] |
reg[ 4 : 0 ] | Cr_AC_code_length [ 161 : 0 ] |
reg[ 7 : 0 ] | Cr_AC_run_code [ 250 : 0 ] |
reg[ 10 : 0 ] | Cr11_Huff |
reg[ 10 : 0 ] | Cr11_Huff_1 |
reg[ 10 : 0 ] | Cr11_Huff_2 |
reg[ 15 : 0 ] | Cr12_Huff |
reg[ 15 : 0 ] | Cr12_Huff_1 |
reg[ 15 : 0 ] | Cr12_Huff_2 |
reg[ 3 : 0 ] | Cr11_Huff_count |
reg[ 3 : 0 ] | Cr11_Huff_shift |
reg[ 3 : 0 ] | Cr11_Huff_shift_1 |
reg[ 3 : 0 ] | Cr11_amp_shift |
reg[ 3 : 0 ] | Cr12_amp_shift |
reg[ 3 : 0 ] | Cr12_Huff_shift |
reg[ 3 : 0 ] | Cr12_Huff_shift_1 |
reg[ 3 : 0 ] | zero_run_length |
reg[ 3 : 0 ] | zrl_1 |
reg[ 3 : 0 ] | zrl_2 |
reg[ 3 : 0 ] | zrl_3 |
reg[ 4 : 0 ] | Cr12_Huff_count |
reg[ 4 : 0 ] | Cr12_Huff_count_1 |
reg[ 4 : 0 ] | output_reg_count |
reg[ 4 : 0 ] | Cr11_output_count |
reg[ 4 : 0 ] | old_orc_1 |
reg[ 4 : 0 ] | old_orc_2 |
reg[ 4 : 0 ] | old_orc_3 |
reg[ 4 : 0 ] | old_orc_4 |
reg[ 4 : 0 ] | old_orc_5 |
reg[ 4 : 0 ] | old_orc_6 |
reg[ 4 : 0 ] | Cr12_oc_1 |
reg[ 4 : 0 ] | orc_3 |
reg[ 4 : 0 ] | orc_4 |
reg[ 4 : 0 ] | orc_5 |
reg[ 4 : 0 ] | orc_6 |
reg[ 4 : 0 ] | orc_7 |
reg[ 4 : 0 ] | orc_8 |
reg[ 4 : 0 ] | Cr12_output_count |
reg[ 4 : 0 ] | Cr12_edge |
reg[ 4 : 0 ] | Cr12_edge_1 |
reg[ 4 : 0 ] | Cr12_edge_2 |
reg[ 4 : 0 ] | Cr12_edge_3 |
reg[ 4 : 0 ] | Cr12_edge_4 |
reg[ 31 : 0 ] | JPEG_bitstream |
reg[ 31 : 0 ] | JPEG_bs |
reg[ 31 : 0 ] | JPEG_bs_1 |
reg[ 31 : 0 ] | JPEG_bs_2 |
reg[ 31 : 0 ] | JPEG_bs_3 |
reg[ 31 : 0 ] | JPEG_bs_4 |
reg[ 31 : 0 ] | JPEG_bs_5 |
reg[ 31 : 0 ] | JPEG_Cr12_bs |
reg[ 31 : 0 ] | JPEG_Cr12_bs_1 |
reg[ 31 : 0 ] | JPEG_Cr12_bs_2 |
reg[ 31 : 0 ] | JPEG_Cr12_bs_3 |
reg[ 31 : 0 ] | JPEG_Cr12_bs_4 |
reg[ 31 : 0 ] | JPEG_ro_bs |
reg[ 31 : 0 ] | JPEG_ro_bs_1 |
reg[ 31 : 0 ] | JPEG_ro_bs_2 |
reg[ 31 : 0 ] | JPEG_ro_bs_3 |
reg[ 31 : 0 ] | JPEG_ro_bs_4 |
reg[ 21 : 0 ] | Cr11_JPEG_LSBs_3 |
reg[ 10 : 0 ] | Cr11_JPEG_LSBs |
reg[ 10 : 0 ] | Cr11_JPEG_LSBs_1 |
reg[ 10 : 0 ] | Cr11_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Cr12_JPEG_LSBs |
reg[ 9 : 0 ] | Cr12_JPEG_LSBs_1 |
reg[ 9 : 0 ] | Cr12_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Cr12_JPEG_LSBs_3 |
reg[ 25 : 0 ] | Cr11_JPEG_bits |
reg[ 25 : 0 ] | Cr11_JPEG_bits_1 |
reg[ 25 : 0 ] | Cr12_JPEG_bits |
reg[ 25 : 0 ] | Cr12_JPEG_LSBs_4 |
reg[ 7 : 0 ] | Cr12_code_entry |
reg | third_8_all_0s |
reg | fourth_8_all_0s |
reg | fifth_8_all_0s |
reg | sixth_8_all_0s |
reg | seventh_8_all_0s |
reg | eighth_8_all_0s |
reg | end_of_block |
reg | code_15_0 |
reg | zrl_et_15 |
reg | end_of_block_output |
reg | end_of_block_empty |
wire[ 7 : 0 ] | code_index |
|
Output |
|
Output |
|
Output |
|
Output |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |
|
Signal |