oc_jpegencode  1.0
JPEGencoder
sync_fifo_32.v
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1 /////////////////////////////////////////////////////////////////////
2 //// ////
3 //// JPEG Encoder Core - Verilog ////
4 //// ////
5 //// Author: David Lundgren ////
6 //// davidklun@gmail.com ////
7 //// ////
8 /////////////////////////////////////////////////////////////////////
9 //// ////
10 //// Copyright (C) 2009 David Lundgren ////
11 //// davidklun@gmail.com ////
12 //// ////
13 //// This source file may be used and distributed without ////
14 //// restriction provided that this copyright statement is not ////
15 //// removed from the file and that any derivative work contains ////
16 //// the original copyright notice and the associated disclaimer.////
17 //// ////
18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
30 //// POSSIBILITY OF SUCH DAMAGE. ////
31 //// ////
32 /////////////////////////////////////////////////////////////////////
33 
34 `timescale 1ns / 100ps
35 
38 input clk;
39 input rst;
40 input read_req;
41 input [31:0] write_data;
43 output [31:0] read_data;
44 output fifo_empty;
45 output rdata_valid;
46 
47 reg [4:0] read_ptr;
48 reg [4:0] write_ptr;
49 reg [31:0] mem [0:15];
50 reg [31:0] read_data;
52 wire [3:0] write_addr = write_ptr[3:0];
53 wire [3:0] read_addr = read_ptr[3:0];
55 assign fifo_empty = (read_ptr == write_ptr);
56 
57 
58 always @(posedge clk)
59  begin
60  if (rst)
61  write_ptr <= {(5){1'b0}};
62  else if (write_enable)
63  write_ptr <= write_ptr + {{4{1'b0}},1'b1};
64  end
65 
66 always @(posedge clk)
67 begin
68  if (rst)
69  rdata_valid <= 1'b0;
70  else if (read_enable)
71  rdata_valid <= 1'b1;
72  else
73  rdata_valid <= 1'b0;
74 end
75 
76 always @(posedge clk)
77  begin
78  if (rst)
79  read_ptr <= {(5){1'b0}};
80  else if (read_enable)
81  read_ptr <= read_ptr + {{4{1'b0}},1'b1};
82 end
83 
84 // Mem write
85 always @(posedge clk)
86  begin
87  if (write_enable)
89  end
90 // Mem Read
91 always @(posedge clk)
92  begin
93  if (read_enable)
95  end
96 
97 endmodule
3469read_addrwire[3:0]
Definition: sync_fifo_32.v:53
3468write_addrwire[3:0]
Definition: sync_fifo_32.v:52
[31:0] 3458write_data
Definition: sync_fifo_32.v:41
3466read_datareg[31:0]
Definition: sync_fifo_32.v:50
3464write_ptrreg[4:0]
Definition: sync_fifo_32.v:48
3470read_enablewire
Definition: sync_fifo_32.v:54
3467rdata_validreg
Definition: sync_fifo_32.v:51
3463read_ptrreg[4:0]
Definition: sync_fifo_32.v:47
[0:15] 3465memreg[31:0]
Definition: sync_fifo_32.v:49