oc_jpegencode
1.0
JPEGencoder
sync_fifo_32.v
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// JPEG Encoder Core - Verilog ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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36
module
sync_fifo_32
(
clk
,
rst
,
read_req
,
write_data
,
write_enable
,
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read_data
,
fifo_empty
,
rdata_valid
);
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input
clk
;
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input
rst
;
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input
read_req
;
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input
[
31
:
0
]
write_data
;
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input
write_enable
;
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output
[
31
:
0
]
read_data
;
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output
fifo_empty
;
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output
rdata_valid
;
46
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reg
[
4
:
0
]
read_ptr
;
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reg
[
4
:
0
]
write_ptr
;
49
reg
[
31
:
0
]
mem
[
0
:
15
];
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reg
[
31
:
0
]
read_data
;
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reg
rdata_valid
;
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wire
[
3
:
0
]
write_addr
=
write_ptr
[
3
:
0
];
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wire
[
3
:
0
]
read_addr
=
read_ptr
[
3
:
0
];
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wire
read_enable
=
read_req
&& (~
fifo_empty
);
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assign
fifo_empty
= (
read_ptr
==
write_ptr
);
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57
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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write_ptr
<= {(
5
){
1'b0
}};
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else
if
(
write_enable
)
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write_ptr
<=
write_ptr
+ {{
4
{
1'b0
}},
1'b1
};
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end
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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rdata_valid
<=
1'b0
;
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else
if
(
read_enable
)
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rdata_valid
<=
1'b1
;
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else
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rdata_valid
<=
1'b0
;
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end
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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read_ptr
<= {(
5
){
1'b0
}};
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else
if
(
read_enable
)
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read_ptr
<=
read_ptr
+ {{
4
{
1'b0
}},
1'b1
};
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end
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// Mem write
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always
@(
posedge
clk
)
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begin
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if
(
write_enable
)
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mem
[
write_addr
] <=
write_data
;
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end
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// Mem Read
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always
@(
posedge
clk
)
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begin
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if
(
read_enable
)
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read_data
<=
mem
[
read_addr
];
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end
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endmodule
sync_fifo_32.3469read_addr
3469read_addrwire[3:0]
Definition:
sync_fifo_32.v:53
sync_fifo_32.3455clk
3455clk
Definition:
sync_fifo_32.v:38
sync_fifo_32
Definition:
sync_fifo_32.v:36
sync_fifo_32.3468write_addr
3468write_addrwire[3:0]
Definition:
sync_fifo_32.v:52
sync_fifo_32.3458write_data
[31:0] 3458write_data
Definition:
sync_fifo_32.v:41
sync_fifo_32.3466read_data
3466read_datareg[31:0]
Definition:
sync_fifo_32.v:50
sync_fifo_32.3464write_ptr
3464write_ptrreg[4:0]
Definition:
sync_fifo_32.v:48
sync_fifo_32.3470read_enable
3470read_enablewire
Definition:
sync_fifo_32.v:54
sync_fifo_32.3459write_enable
3459write_enable
Definition:
sync_fifo_32.v:42
sync_fifo_32.3457read_req
3457read_req
Definition:
sync_fifo_32.v:40
sync_fifo_32.3456rst
3456rst
Definition:
sync_fifo_32.v:39
sync_fifo_32.3467rdata_valid
3467rdata_validreg
Definition:
sync_fifo_32.v:51
sync_fifo_32.3463read_ptr
3463read_ptrreg[4:0]
Definition:
sync_fifo_32.v:47
sync_fifo_32.3465mem
[0:15] 3465memreg[31:0]
Definition:
sync_fifo_32.v:49
sync_fifo_32.3461fifo_empty
3461fifo_empty
Definition:
sync_fifo_32.v:44
code
sync_fifo_32.v
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