oc_jpegencode
1.0
JPEGencoder
sync_fifo_ff.v
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// JPEG Encoder Core - Verilog ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/* This FIFO is used for the ff_checker module. **/
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`timescale 1ns / 100ps
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module
sync_fifo_ff
(
clk
,
rst
,
read_req
,
write_data
,
write_enable
,
rollover_write
,
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read_data
,
fifo_empty
,
rdata_valid
);
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input
clk
;
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input
rst
;
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input
read_req
;
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input
[
90
:
0
]
write_data
;
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input
write_enable
;
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input
rollover_write
;
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output
[
90
:
0
]
read_data
;
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output
fifo_empty
;
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output
rdata_valid
;
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reg
[
4
:
0
]
read_ptr
;
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reg
[
4
:
0
]
write_ptr
;
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reg
[
90
:
0
]
mem
[
0
:
15
];
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reg
[
90
:
0
]
read_data
;
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reg
rdata_valid
;
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wire
[
3
:
0
]
write_addr
=
write_ptr
[
3
:
0
];
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wire
[
3
:
0
]
read_addr
=
read_ptr
[
3
:
0
];
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wire
read_enable
=
read_req
&& (~
fifo_empty
);
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assign
fifo_empty
= (
read_ptr
==
write_ptr
);
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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write_ptr
<= {(
5
){
1'b0
}};
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else
if
(
write_enable
& !
rollover_write
)
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write_ptr
<=
write_ptr
+ {{
4
{
1'b0
}},
1'b1
};
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else
if
(
write_enable
&
rollover_write
)
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write_ptr
<=
write_ptr
+
5'b00010
;
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// A rollover_write means that there have been a total of 4 FF's
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// that have been detected in the bitstream. So an extra set of 32
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// bits will be put into the bitstream (due to the 4 extra 00's added
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// after the 4 FF's), and the input data will have to
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// be delayed by 1 clock cycle as it makes its way into the output
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// bitstream. So the write_ptr is incremented by 2 for a rollover, giving
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// the output the extra clock cycle it needs to write the
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// extra 32 bits to the bitstream. The output
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// will read the dummy data from the FIFO, but won't do anything with it,
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// it will be putting the extra set of 32 bits into the bitstream on that
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// clock cycle.
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end
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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rdata_valid
<=
1'b0
;
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else
if
(
read_enable
)
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rdata_valid
<=
1'b1
;
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else
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rdata_valid
<=
1'b0
;
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end
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
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read_ptr
<= {(
5
){
1'b0
}};
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else
if
(
read_enable
)
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read_ptr
<=
read_ptr
+ {{
4
{
1'b0
}},
1'b1
};
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end
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// Mem write
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always
@(
posedge
clk
)
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begin
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if
(
write_enable
)
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mem
[
write_addr
] <=
write_data
;
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end
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// Mem Read
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always
@(
posedge
clk
)
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begin
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if
(
read_enable
)
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read_data
<=
mem
[
read_addr
];
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end
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endmodule
sync_fifo_ff
Definition:
sync_fifo_ff.v:38
sync_fifo_ff.3481write_ptr
3481write_ptrreg[4:0]
Definition:
sync_fifo_ff.v:51
sync_fifo_ff.3485write_addr
3485write_addrwire[3:0]
Definition:
sync_fifo_ff.v:55
sync_fifo_ff.3480read_ptr
3480read_ptrreg[4:0]
Definition:
sync_fifo_ff.v:50
sync_fifo_ff.3487read_enable
3487read_enablewire
Definition:
sync_fifo_ff.v:57
sync_fifo_ff.3483read_data
3483read_datareg[90:0]
Definition:
sync_fifo_ff.v:53
sync_fifo_ff.3482mem
[0:15] 3482memreg[90:0]
Definition:
sync_fifo_ff.v:52
sync_fifo_ff.3471clk
3471clk
Definition:
sync_fifo_ff.v:40
sync_fifo_ff.3473read_req
3473read_req
Definition:
sync_fifo_ff.v:42
sync_fifo_ff.3486read_addr
3486read_addrwire[3:0]
Definition:
sync_fifo_ff.v:56
sync_fifo_ff.3484rdata_valid
3484rdata_validreg
Definition:
sync_fifo_ff.v:54
sync_fifo_ff.3475write_enable
3475write_enable
Definition:
sync_fifo_ff.v:44
sync_fifo_ff.3474write_data
[90:0] 3474write_data
Definition:
sync_fifo_ff.v:43
sync_fifo_ff.3478fifo_empty
3478fifo_empty
Definition:
sync_fifo_ff.v:47
sync_fifo_ff.3476rollover_write
3476rollover_write
Definition:
sync_fifo_ff.v:45
sync_fifo_ff.3472rst
3472rst
Definition:
sync_fifo_ff.v:41
code
sync_fifo_ff.v
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