oc_jpegencode
1.0
JPEGencoder
|
Static Public Member Functions |
Public Attributes |
Inputs | |
clk | |
rst | |
enable | |
Y11 | [ 10 : 0 ] |
Y12 | [ 10 : 0 ] |
Y13 | [ 10 : 0 ] |
Y14 | [ 10 : 0 ] |
Y15 | [ 10 : 0 ] |
Y16 | [ 10 : 0 ] |
Y17 | [ 10 : 0 ] |
Y18 | [ 10 : 0 ] |
Y21 | [ 10 : 0 ] |
Y22 | [ 10 : 0 ] |
Y23 | [ 10 : 0 ] |
Y24 | [ 10 : 0 ] |
Y25 | [ 10 : 0 ] |
Y26 | [ 10 : 0 ] |
Y27 | [ 10 : 0 ] |
Y28 | [ 10 : 0 ] |
Y31 | [ 10 : 0 ] |
Y32 | [ 10 : 0 ] |
Y33 | [ 10 : 0 ] |
Y34 | [ 10 : 0 ] |
Y35 | [ 10 : 0 ] |
Y36 | [ 10 : 0 ] |
Y37 | [ 10 : 0 ] |
Y38 | [ 10 : 0 ] |
Y41 | [ 10 : 0 ] |
Y42 | [ 10 : 0 ] |
Y43 | [ 10 : 0 ] |
Y44 | [ 10 : 0 ] |
Y45 | [ 10 : 0 ] |
Y46 | [ 10 : 0 ] |
Y47 | [ 10 : 0 ] |
Y48 | [ 10 : 0 ] |
Y51 | [ 10 : 0 ] |
Y52 | [ 10 : 0 ] |
Y53 | [ 10 : 0 ] |
Y54 | [ 10 : 0 ] |
Y55 | [ 10 : 0 ] |
Y56 | [ 10 : 0 ] |
Y57 | [ 10 : 0 ] |
Y58 | [ 10 : 0 ] |
Y61 | [ 10 : 0 ] |
Y62 | [ 10 : 0 ] |
Y63 | [ 10 : 0 ] |
Y64 | [ 10 : 0 ] |
Y65 | [ 10 : 0 ] |
Y66 | [ 10 : 0 ] |
Y67 | [ 10 : 0 ] |
Y68 | [ 10 : 0 ] |
Y71 | [ 10 : 0 ] |
Y72 | [ 10 : 0 ] |
Y73 | [ 10 : 0 ] |
Y74 | [ 10 : 0 ] |
Y75 | [ 10 : 0 ] |
Y76 | [ 10 : 0 ] |
Y77 | [ 10 : 0 ] |
Y78 | [ 10 : 0 ] |
Y81 | [ 10 : 0 ] |
Y82 | [ 10 : 0 ] |
Y83 | [ 10 : 0 ] |
Y84 | [ 10 : 0 ] |
Y85 | [ 10 : 0 ] |
Y86 | [ 10 : 0 ] |
Y87 | [ 10 : 0 ] |
Y88 | [ 10 : 0 ] |
Outputs | |
JPEG_bitstream | [ 31 : 0 ] |
data_ready | |
output_reg_count | [ 4 : 0 ] |
end_of_block_output | |
end_of_block_empty |
Signals | |
reg[ 7 : 0 ] | block_counter |
reg[ 11 : 0 ] | Y11_amp |
reg[ 11 : 0 ] | Y11_1_pos |
reg[ 11 : 0 ] | Y11_1_neg |
reg[ 11 : 0 ] | Y11_diff |
reg[ 11 : 0 ] | Y11_previous |
reg[ 11 : 0 ] | Y11_1 |
reg[ 10 : 0 ] | Y12_amp |
reg[ 10 : 0 ] | Y12_pos |
reg[ 10 : 0 ] | Y12_neg |
reg[ 10 : 0 ] | Y21_pos |
reg[ 10 : 0 ] | Y21_neg |
reg[ 10 : 0 ] | Y31_pos |
reg[ 10 : 0 ] | Y31_neg |
reg[ 10 : 0 ] | Y22_pos |
reg[ 10 : 0 ] | Y22_neg |
reg[ 10 : 0 ] | Y13_pos |
reg[ 10 : 0 ] | Y13_neg |
reg[ 10 : 0 ] | Y14_pos |
reg[ 10 : 0 ] | Y14_neg |
reg[ 10 : 0 ] | Y15_pos |
reg[ 10 : 0 ] | Y15_neg |
reg[ 10 : 0 ] | Y16_pos |
reg[ 10 : 0 ] | Y16_neg |
reg[ 10 : 0 ] | Y17_pos |
reg[ 10 : 0 ] | Y17_neg |
reg[ 10 : 0 ] | Y18_pos |
reg[ 10 : 0 ] | Y18_neg |
reg[ 10 : 0 ] | Y23_pos |
reg[ 10 : 0 ] | Y23_neg |
reg[ 10 : 0 ] | Y24_pos |
reg[ 10 : 0 ] | Y24_neg |
reg[ 10 : 0 ] | Y25_pos |
reg[ 10 : 0 ] | Y25_neg |
reg[ 10 : 0 ] | Y26_pos |
reg[ 10 : 0 ] | Y26_neg |
reg[ 10 : 0 ] | Y27_pos |
reg[ 10 : 0 ] | Y27_neg |
reg[ 10 : 0 ] | Y28_pos |
reg[ 10 : 0 ] | Y28_neg |
reg[ 10 : 0 ] | Y32_pos |
reg[ 10 : 0 ] | Y32_neg |
reg[ 10 : 0 ] | Y33_pos |
reg[ 10 : 0 ] | Y33_neg |
reg[ 10 : 0 ] | Y34_pos |
reg[ 10 : 0 ] | Y34_neg |
reg[ 10 : 0 ] | Y35_pos |
reg[ 10 : 0 ] | Y35_neg |
reg[ 10 : 0 ] | Y36_pos |
reg[ 10 : 0 ] | Y36_neg |
reg[ 10 : 0 ] | Y37_pos |
reg[ 10 : 0 ] | Y37_neg |
reg[ 10 : 0 ] | Y38_pos |
reg[ 10 : 0 ] | Y38_neg |
reg[ 10 : 0 ] | Y41_pos |
reg[ 10 : 0 ] | Y41_neg |
reg[ 10 : 0 ] | Y42_pos |
reg[ 10 : 0 ] | Y42_neg |
reg[ 10 : 0 ] | Y43_pos |
reg[ 10 : 0 ] | Y43_neg |
reg[ 10 : 0 ] | Y44_pos |
reg[ 10 : 0 ] | Y44_neg |
reg[ 10 : 0 ] | Y45_pos |
reg[ 10 : 0 ] | Y45_neg |
reg[ 10 : 0 ] | Y46_pos |
reg[ 10 : 0 ] | Y46_neg |
reg[ 10 : 0 ] | Y47_pos |
reg[ 10 : 0 ] | Y47_neg |
reg[ 10 : 0 ] | Y48_pos |
reg[ 10 : 0 ] | Y48_neg |
reg[ 10 : 0 ] | Y51_pos |
reg[ 10 : 0 ] | Y51_neg |
reg[ 10 : 0 ] | Y52_pos |
reg[ 10 : 0 ] | Y52_neg |
reg[ 10 : 0 ] | Y53_pos |
reg[ 10 : 0 ] | Y53_neg |
reg[ 10 : 0 ] | Y54_pos |
reg[ 10 : 0 ] | Y54_neg |
reg[ 10 : 0 ] | Y55_pos |
reg[ 10 : 0 ] | Y55_neg |
reg[ 10 : 0 ] | Y56_pos |
reg[ 10 : 0 ] | Y56_neg |
reg[ 10 : 0 ] | Y57_pos |
reg[ 10 : 0 ] | Y57_neg |
reg[ 10 : 0 ] | Y58_pos |
reg[ 10 : 0 ] | Y58_neg |
reg[ 10 : 0 ] | Y61_pos |
reg[ 10 : 0 ] | Y61_neg |
reg[ 10 : 0 ] | Y62_pos |
reg[ 10 : 0 ] | Y62_neg |
reg[ 10 : 0 ] | Y63_pos |
reg[ 10 : 0 ] | Y63_neg |
reg[ 10 : 0 ] | Y64_pos |
reg[ 10 : 0 ] | Y64_neg |
reg[ 10 : 0 ] | Y65_pos |
reg[ 10 : 0 ] | Y65_neg |
reg[ 10 : 0 ] | Y66_pos |
reg[ 10 : 0 ] | Y66_neg |
reg[ 10 : 0 ] | Y67_pos |
reg[ 10 : 0 ] | Y67_neg |
reg[ 10 : 0 ] | Y68_pos |
reg[ 10 : 0 ] | Y68_neg |
reg[ 10 : 0 ] | Y71_pos |
reg[ 10 : 0 ] | Y71_neg |
reg[ 10 : 0 ] | Y72_pos |
reg[ 10 : 0 ] | Y72_neg |
reg[ 10 : 0 ] | Y73_pos |
reg[ 10 : 0 ] | Y73_neg |
reg[ 10 : 0 ] | Y74_pos |
reg[ 10 : 0 ] | Y74_neg |
reg[ 10 : 0 ] | Y75_pos |
reg[ 10 : 0 ] | Y75_neg |
reg[ 10 : 0 ] | Y76_pos |
reg[ 10 : 0 ] | Y76_neg |
reg[ 10 : 0 ] | Y77_pos |
reg[ 10 : 0 ] | Y77_neg |
reg[ 10 : 0 ] | Y78_pos |
reg[ 10 : 0 ] | Y78_neg |
reg[ 10 : 0 ] | Y81_pos |
reg[ 10 : 0 ] | Y81_neg |
reg[ 10 : 0 ] | Y82_pos |
reg[ 10 : 0 ] | Y82_neg |
reg[ 10 : 0 ] | Y83_pos |
reg[ 10 : 0 ] | Y83_neg |
reg[ 10 : 0 ] | Y84_pos |
reg[ 10 : 0 ] | Y84_neg |
reg[ 10 : 0 ] | Y85_pos |
reg[ 10 : 0 ] | Y85_neg |
reg[ 10 : 0 ] | Y86_pos |
reg[ 10 : 0 ] | Y86_neg |
reg[ 10 : 0 ] | Y87_pos |
reg[ 10 : 0 ] | Y87_neg |
reg[ 10 : 0 ] | Y88_pos |
reg[ 10 : 0 ] | Y88_neg |
reg[ 3 : 0 ] | Y11_bits_pos |
reg[ 3 : 0 ] | Y11_bits_neg |
reg[ 3 : 0 ] | Y11_bits |
reg[ 3 : 0 ] | Y11_bits_1 |
reg[ 3 : 0 ] | Y12_bits_pos |
reg[ 3 : 0 ] | Y12_bits_neg |
reg[ 3 : 0 ] | Y12_bits |
reg[ 3 : 0 ] | Y12_bits_1 |
reg[ 3 : 0 ] | Y12_bits_2 |
reg[ 3 : 0 ] | Y12_bits_3 |
reg | Y11_msb |
reg | Y12_msb |
reg | Y12_msb_1 |
reg | data_ready |
reg | enable_1 |
reg | enable_2 |
reg | enable_3 |
reg | enable_4 |
reg | enable_5 |
reg | enable_6 |
reg | enable_7 |
reg | enable_8 |
reg | enable_9 |
reg | enable_10 |
reg | enable_11 |
reg | enable_12 |
reg | enable_13 |
reg | enable_module |
reg | enable_latch_7 |
reg | enable_latch_8 |
reg | Y12_et_zero |
reg | rollover |
reg | rollover_1 |
reg | rollover_2 |
reg | rollover_3 |
reg | rollover_4 |
reg | rollover_5 |
reg | rollover_6 |
reg | rollover_7 |
reg | Y21_et_zero |
reg | Y21_msb |
reg | Y31_et_zero |
reg | Y31_msb |
reg | Y22_et_zero |
reg | Y22_msb |
reg | Y13_et_zero |
reg | Y13_msb |
reg | Y14_et_zero |
reg | Y14_msb |
reg | Y15_et_zero |
reg | Y15_msb |
reg | Y16_et_zero |
reg | Y16_msb |
reg | Y17_et_zero |
reg | Y17_msb |
reg | Y18_et_zero |
reg | Y18_msb |
reg | Y23_et_zero |
reg | Y23_msb |
reg | Y24_et_zero |
reg | Y24_msb |
reg | Y25_et_zero |
reg | Y25_msb |
reg | Y26_et_zero |
reg | Y26_msb |
reg | Y27_et_zero |
reg | Y27_msb |
reg | Y28_et_zero |
reg | Y28_msb |
reg | Y32_et_zero |
reg | Y32_msb |
reg | Y33_et_zero |
reg | Y33_msb |
reg | Y34_et_zero |
reg | Y34_msb |
reg | Y35_et_zero |
reg | Y35_msb |
reg | Y36_et_zero |
reg | Y36_msb |
reg | Y37_et_zero |
reg | Y37_msb |
reg | Y38_et_zero |
reg | Y38_msb |
reg | Y41_et_zero |
reg | Y41_msb |
reg | Y42_et_zero |
reg | Y42_msb |
reg | Y43_et_zero |
reg | Y43_msb |
reg | Y44_et_zero |
reg | Y44_msb |
reg | Y45_et_zero |
reg | Y45_msb |
reg | Y46_et_zero |
reg | Y46_msb |
reg | Y47_et_zero |
reg | Y47_msb |
reg | Y48_et_zero |
reg | Y48_msb |
reg | Y51_et_zero |
reg | Y51_msb |
reg | Y52_et_zero |
reg | Y52_msb |
reg | Y53_et_zero |
reg | Y53_msb |
reg | Y54_et_zero |
reg | Y54_msb |
reg | Y55_et_zero |
reg | Y55_msb |
reg | Y56_et_zero |
reg | Y56_msb |
reg | Y57_et_zero |
reg | Y57_msb |
reg | Y58_et_zero |
reg | Y58_msb |
reg | Y61_et_zero |
reg | Y61_msb |
reg | Y62_et_zero |
reg | Y62_msb |
reg | Y63_et_zero |
reg | Y63_msb |
reg | Y64_et_zero |
reg | Y64_msb |
reg | Y65_et_zero |
reg | Y65_msb |
reg | Y66_et_zero |
reg | Y66_msb |
reg | Y67_et_zero |
reg | Y67_msb |
reg | Y68_et_zero |
reg | Y68_msb |
reg | Y71_et_zero |
reg | Y71_msb |
reg | Y72_et_zero |
reg | Y72_msb |
reg | Y73_et_zero |
reg | Y73_msb |
reg | Y74_et_zero |
reg | Y74_msb |
reg | Y75_et_zero |
reg | Y75_msb |
reg | Y76_et_zero |
reg | Y76_msb |
reg | Y77_et_zero |
reg | Y77_msb |
reg | Y78_et_zero |
reg | Y78_msb |
reg | Y81_et_zero |
reg | Y81_msb |
reg | Y82_et_zero |
reg | Y82_msb |
reg | Y83_et_zero |
reg | Y83_msb |
reg | Y84_et_zero |
reg | Y84_msb |
reg | Y85_et_zero |
reg | Y85_msb |
reg | Y86_et_zero |
reg | Y86_msb |
reg | Y87_et_zero |
reg | Y87_msb |
reg | Y88_et_zero |
reg | Y88_msb |
reg | Y12_et_zero_1 |
reg | Y12_et_zero_2 |
reg | Y12_et_zero_3 |
reg | Y12_et_zero_4 |
reg | Y12_et_zero_5 |
reg[ 10 : 0 ] | Y_DC [ 11 : 0 ] |
reg[ 3 : 0 ] | Y_DC_code_length [ 11 : 0 ] |
reg[ 15 : 0 ] | Y_AC [ 161 : 0 ] |
reg[ 4 : 0 ] | Y_AC_code_length [ 161 : 0 ] |
reg[ 7 : 0 ] | Y_AC_run_code [ 250 : 0 ] |
reg[ 10 : 0 ] | Y11_Huff |
reg[ 10 : 0 ] | Y11_Huff_1 |
reg[ 10 : 0 ] | Y11_Huff_2 |
reg[ 15 : 0 ] | Y12_Huff |
reg[ 15 : 0 ] | Y12_Huff_1 |
reg[ 15 : 0 ] | Y12_Huff_2 |
reg[ 3 : 0 ] | Y11_Huff_count |
reg[ 3 : 0 ] | Y11_Huff_shift |
reg[ 3 : 0 ] | Y11_Huff_shift_1 |
reg[ 3 : 0 ] | Y11_amp_shift |
reg[ 3 : 0 ] | Y12_amp_shift |
reg[ 3 : 0 ] | Y12_Huff_shift |
reg[ 3 : 0 ] | Y12_Huff_shift_1 |
reg[ 3 : 0 ] | zero_run_length |
reg[ 3 : 0 ] | zrl_1 |
reg[ 3 : 0 ] | zrl_2 |
reg[ 3 : 0 ] | zrl_3 |
reg[ 4 : 0 ] | Y12_Huff_count |
reg[ 4 : 0 ] | Y12_Huff_count_1 |
reg[ 4 : 0 ] | output_reg_count |
reg[ 4 : 0 ] | Y11_output_count |
reg[ 4 : 0 ] | old_orc_1 |
reg[ 4 : 0 ] | old_orc_2 |
reg[ 4 : 0 ] | old_orc_3 |
reg[ 4 : 0 ] | old_orc_4 |
reg[ 4 : 0 ] | old_orc_5 |
reg[ 4 : 0 ] | old_orc_6 |
reg[ 4 : 0 ] | Y12_oc_1 |
reg[ 4 : 0 ] | orc_3 |
reg[ 4 : 0 ] | orc_4 |
reg[ 4 : 0 ] | orc_5 |
reg[ 4 : 0 ] | orc_6 |
reg[ 4 : 0 ] | orc_7 |
reg[ 4 : 0 ] | orc_8 |
reg[ 4 : 0 ] | Y12_output_count |
reg[ 4 : 0 ] | Y12_edge |
reg[ 4 : 0 ] | Y12_edge_1 |
reg[ 4 : 0 ] | Y12_edge_2 |
reg[ 4 : 0 ] | Y12_edge_3 |
reg[ 4 : 0 ] | Y12_edge_4 |
reg[ 31 : 0 ] | JPEG_bitstream |
reg[ 31 : 0 ] | JPEG_bs |
reg[ 31 : 0 ] | JPEG_bs_1 |
reg[ 31 : 0 ] | JPEG_bs_2 |
reg[ 31 : 0 ] | JPEG_bs_3 |
reg[ 31 : 0 ] | JPEG_bs_4 |
reg[ 31 : 0 ] | JPEG_bs_5 |
reg[ 31 : 0 ] | JPEG_Y12_bs |
reg[ 31 : 0 ] | JPEG_Y12_bs_1 |
reg[ 31 : 0 ] | JPEG_Y12_bs_2 |
reg[ 31 : 0 ] | JPEG_Y12_bs_3 |
reg[ 31 : 0 ] | JPEG_Y12_bs_4 |
reg[ 31 : 0 ] | JPEG_ro_bs |
reg[ 31 : 0 ] | JPEG_ro_bs_1 |
reg[ 31 : 0 ] | JPEG_ro_bs_2 |
reg[ 31 : 0 ] | JPEG_ro_bs_3 |
reg[ 31 : 0 ] | JPEG_ro_bs_4 |
reg[ 21 : 0 ] | Y11_JPEG_LSBs_3 |
reg[ 10 : 0 ] | Y11_JPEG_LSBs |
reg[ 10 : 0 ] | Y11_JPEG_LSBs_1 |
reg[ 10 : 0 ] | Y11_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Y12_JPEG_LSBs |
reg[ 9 : 0 ] | Y12_JPEG_LSBs_1 |
reg[ 9 : 0 ] | Y12_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Y12_JPEG_LSBs_3 |
reg[ 25 : 0 ] | Y11_JPEG_bits |
reg[ 25 : 0 ] | Y11_JPEG_bits_1 |
reg[ 25 : 0 ] | Y12_JPEG_bits |
reg[ 25 : 0 ] | Y12_JPEG_LSBs_4 |
reg[ 7 : 0 ] | Y12_code_entry |
reg | third_8_all_0s |
reg | fourth_8_all_0s |
reg | fifth_8_all_0s |
reg | sixth_8_all_0s |
reg | seventh_8_all_0s |
reg | eighth_8_all_0s |
reg | end_of_block |
reg | code_15_0 |
reg | zrl_et_15 |
reg | end_of_block_output |
reg | end_of_block_empty |
wire[ 7 : 0 ] | code_index |
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