oc_jpegencode  1.0
JPEGencoder
cr_dct.v
Go to the documentation of this file.
1 /////////////////////////////////////////////////////////////////////
2 //// ////
3 //// JPEG Encoder Core - Verilog ////
4 //// ////
5 //// Author: David Lundgren ////
6 //// davidklun@gmail.com ////
7 //// ////
8 /////////////////////////////////////////////////////////////////////
9 //// ////
10 //// Copyright (C) 2009 David Lundgren ////
11 //// davidklun@gmail.com ////
12 //// ////
13 //// This source file may be used and distributed without ////
14 //// restriction provided that this copyright statement is not ////
15 //// removed from the file and that any derivative work contains ////
16 //// the original copyright notice and the associated disclaimer.////
17 //// ////
18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
30 //// POSSIBILITY OF SUCH DAMAGE. ////
31 //// ////
32 /////////////////////////////////////////////////////////////////////
33 
34 /* This module converts the incoming Cr data.
35 The incoming data is unsigned 8 bits, so the data is in the range of 0-255
36 Unlike a typical DCT, the data is not subtracted by 128 to center it around 0.
37 It is only required for the first row, and instead of subtracting 128 from each
38 pixel value, a total value can be subtracted at the end of the first row/column multiply,
39 involving the 8 pixel values and the 8 DCT matrix values.
40 For the other 7 rows of the DCT matrix, the values in each row add up to 0,
41 so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value.
42 Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values
43 by the 8x8 DCT matrix. **/
44 
45 
46 `timescale 1ns / 100ps
47 
58 input clk;
59 input rst;
60 input enable;
61 input [7:0] data_in;
79 
80 
81 integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52;
83 
84 reg [24:0] Cb_temp_11;
85 reg [24:0] Cb11, Cb21, Cb31, Cb41, Cb51, Cb61, Cb71, Cb81, Cb11_final;
104 reg [24:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18;
105 reg [24:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28;
106 reg [24:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
107 reg [24:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48;
108 reg [24:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58;
109 reg [24:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
110 reg [24:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78;
111 reg [24:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88;
141 reg [2:0] count;
145 reg [7:0] data_1;
150 
151 always @(posedge clk)
152 begin // DCT matrix entries
153  T1 = 5793; // .3536
154  T21 = 8035; // .4904
155  T22 = 6811; // .4157
156  T23 = 4551; // .2778
157  T24 = 1598; // .0975
158  T25 = -1598; // -.0975
159  T26 = -4551; // -.2778
160  T27 = -6811; // -.4157
161  T28 = -8035; // -.4904
162  T31 = 7568; // .4619
163  T32 = 3135; // .1913
164  T33 = -3135; // -.1913
165  T34 = -7568; // -.4619
166  T52 = -5793; // -.3536
167 end
168 
169 always @(posedge clk)
170 begin // The inverse DCT matrix entries
171  Ti1 = 5793; // .3536
172  Ti21 = 8035; // .4904
173  Ti22 = 6811; // .4157
174  Ti23 = 4551; // .2778
175  Ti24 = 1598; // .0975
176  Ti25 = -1598; // -.0975
177  Ti26 = -4551; // -.2778
178  Ti27 = -6811; // -.4157
179  Ti28 = -8035; // -.4904
180  Ti31 = 7568; // .4619
181  Ti32 = 3135; // .1913
182  Ti33 = -3135; // -.1913
183  Ti34 = -7568; // -.4619
184  Ti52 = -5793; // -.3536
185 end
186 
187 always @(posedge clk)
188 begin
189  if (rst) begin
190  Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0;
191  Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0;
192  Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0;
193  Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0;
194  Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0;
195  Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0;
196  Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0;
197  Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0;
198  Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0;
199  Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0;
200  Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0;
201  Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0;
202  Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0;
203  Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0;
204  Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0;
205  Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0;
206  end
207  else if (enable_1 & count_8) begin
240  end
241 end
242 
243 always @(posedge clk)
244 begin
245  if (rst) begin
246  Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
247  Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
248  Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
249  Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
250  Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
251  Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
252  Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
253  Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
254  end
255  else if (count_8 & count_of == 1) begin
256  Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0;
257  Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
258  Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0;
259  Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
260  Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0;
261  Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
262  Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0;
263  Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
264  Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0;
265  Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
266  Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0;
267  Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
268  Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0;
269  Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
270  Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0;
271  Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
272  end
273  else if (enable & count_9) begin
274  Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14;
275  Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18;
276  Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24;
277  Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28;
278  Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34;
279  Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38;
280  Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44;
281  Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48;
282  Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54;
283  Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58;
284  Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64;
285  Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68;
286  Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74;
287  Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78;
288  Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84;
289  Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88;
290  end
291 end
292 
293 always @(posedge clk)
294 begin
295  if (rst) begin
296  Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0;
297  Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0;
298  Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0;
299  Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0;
300  Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0;
301  Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0;
302  Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0;
303  Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0;
304  Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0;
305  Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0;
306  Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0;
307  Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0;
308  Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0;
309  Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0;
310  Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0;
311  Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0;
312  end
313  else if (count_10 & count_of == 0) begin
314  Z11_final <= Z11[13] ? Z11[24:14] + 1 : Z11[24:14];
315  Z12_final <= Z12[13] ? Z12[24:14] + 1 : Z12[24:14];
316  Z13_final <= Z13[13] ? Z13[24:14] + 1 : Z13[24:14];
317  Z14_final <= Z14[13] ? Z14[24:14] + 1 : Z14[24:14];
318  Z15_final <= Z15[13] ? Z15[24:14] + 1 : Z15[24:14];
319  Z16_final <= Z16[13] ? Z16[24:14] + 1 : Z16[24:14];
320  Z17_final <= Z17[13] ? Z17[24:14] + 1 : Z17[24:14];
321  Z18_final <= Z18[13] ? Z18[24:14] + 1 : Z18[24:14];
322  Z21_final <= Z21[13] ? Z21[24:14] + 1 : Z21[24:14];
323  Z22_final <= Z22[13] ? Z22[24:14] + 1 : Z22[24:14];
324  Z23_final <= Z23[13] ? Z23[24:14] + 1 : Z23[24:14];
325  Z24_final <= Z24[13] ? Z24[24:14] + 1 : Z24[24:14];
326  Z25_final <= Z25[13] ? Z25[24:14] + 1 : Z25[24:14];
327  Z26_final <= Z26[13] ? Z26[24:14] + 1 : Z26[24:14];
328  Z27_final <= Z27[13] ? Z27[24:14] + 1 : Z27[24:14];
329  Z28_final <= Z28[13] ? Z28[24:14] + 1 : Z28[24:14];
330  Z31_final <= Z31[13] ? Z31[24:14] + 1 : Z31[24:14];
331  Z32_final <= Z32[13] ? Z32[24:14] + 1 : Z32[24:14];
332  Z33_final <= Z33[13] ? Z33[24:14] + 1 : Z33[24:14];
333  Z34_final <= Z34[13] ? Z34[24:14] + 1 : Z34[24:14];
334  Z35_final <= Z35[13] ? Z35[24:14] + 1 : Z35[24:14];
335  Z36_final <= Z36[13] ? Z36[24:14] + 1 : Z36[24:14];
336  Z37_final <= Z37[13] ? Z37[24:14] + 1 : Z37[24:14];
337  Z38_final <= Z38[13] ? Z38[24:14] + 1 : Z38[24:14];
338  Z41_final <= Z41[13] ? Z41[24:14] + 1 : Z41[24:14];
339  Z42_final <= Z42[13] ? Z42[24:14] + 1 : Z42[24:14];
340  Z43_final <= Z43[13] ? Z43[24:14] + 1 : Z43[24:14];
341  Z44_final <= Z44[13] ? Z44[24:14] + 1 : Z44[24:14];
342  Z45_final <= Z45[13] ? Z45[24:14] + 1 : Z45[24:14];
343  Z46_final <= Z46[13] ? Z46[24:14] + 1 : Z46[24:14];
344  Z47_final <= Z47[13] ? Z47[24:14] + 1 : Z47[24:14];
345  Z48_final <= Z48[13] ? Z48[24:14] + 1 : Z48[24:14];
346  Z51_final <= Z51[13] ? Z51[24:14] + 1 : Z51[24:14];
347  Z52_final <= Z52[13] ? Z52[24:14] + 1 : Z52[24:14];
348  Z53_final <= Z53[13] ? Z53[24:14] + 1 : Z53[24:14];
349  Z54_final <= Z54[13] ? Z54[24:14] + 1 : Z54[24:14];
350  Z55_final <= Z55[13] ? Z55[24:14] + 1 : Z55[24:14];
351  Z56_final <= Z56[13] ? Z56[24:14] + 1 : Z56[24:14];
352  Z57_final <= Z57[13] ? Z57[24:14] + 1 : Z57[24:14];
353  Z58_final <= Z58[13] ? Z58[24:14] + 1 : Z58[24:14];
354  Z61_final <= Z61[13] ? Z61[24:14] + 1 : Z61[24:14];
355  Z62_final <= Z62[13] ? Z62[24:14] + 1 : Z62[24:14];
356  Z63_final <= Z63[13] ? Z63[24:14] + 1 : Z63[24:14];
357  Z64_final <= Z64[13] ? Z64[24:14] + 1 : Z64[24:14];
358  Z65_final <= Z65[13] ? Z65[24:14] + 1 : Z65[24:14];
359  Z66_final <= Z66[13] ? Z66[24:14] + 1 : Z66[24:14];
360  Z67_final <= Z67[13] ? Z67[24:14] + 1 : Z67[24:14];
361  Z68_final <= Z68[13] ? Z68[24:14] + 1 : Z68[24:14];
362  Z71_final <= Z71[13] ? Z71[24:14] + 1 : Z71[24:14];
363  Z72_final <= Z72[13] ? Z72[24:14] + 1 : Z72[24:14];
364  Z73_final <= Z73[13] ? Z73[24:14] + 1 : Z73[24:14];
365  Z74_final <= Z74[13] ? Z74[24:14] + 1 : Z74[24:14];
366  Z75_final <= Z75[13] ? Z75[24:14] + 1 : Z75[24:14];
367  Z76_final <= Z76[13] ? Z76[24:14] + 1 : Z76[24:14];
368  Z77_final <= Z77[13] ? Z77[24:14] + 1 : Z77[24:14];
369  Z78_final <= Z78[13] ? Z78[24:14] + 1 : Z78[24:14];
370  Z81_final <= Z81[13] ? Z81[24:14] + 1 : Z81[24:14];
371  Z82_final <= Z82[13] ? Z82[24:14] + 1 : Z82[24:14];
372  Z83_final <= Z83[13] ? Z83[24:14] + 1 : Z83[24:14];
373  Z84_final <= Z84[13] ? Z84[24:14] + 1 : Z84[24:14];
374  Z85_final <= Z85[13] ? Z85[24:14] + 1 : Z85[24:14];
375  Z86_final <= Z86[13] ? Z86[24:14] + 1 : Z86[24:14];
376  Z87_final <= Z87[13] ? Z87[24:14] + 1 : Z87[24:14];
377  Z88_final <= Z88[13] ? Z88[24:14] + 1 : Z88[24:14];
378  end
379 end
380 
381 // output_enable signals the next block, the quantizer, that the input data is ready
382 always @(posedge clk)
383 begin
384  if (rst)
385  output_enable <= 0;
386  else if (!enable_1)
387  output_enable <= 0;
388  else if (count_10 == 0 | count_of)
389  output_enable <= 0;
390  else if (count_10 & count_of == 0)
391  output_enable <= 1;
392 end
393 always @(posedge clk)
394 begin
395  if (rst)
396  Cb_temp_11 <= 0;
397  else if (enable)
398  Cb_temp_11 <= data_in * T1;
399 end
400 
401 always @(posedge clk)
402 begin
403  if (rst)
404  Cb11 <= 0;
405  else if (count == 1 & enable == 1)
406  Cb11 <= Cb_temp_11;
407  else if (enable)
408  Cb11 <= Cb_temp_11 + Cb11;
409 end
410 
411 always @(posedge clk)
412 begin
413  if (rst) begin
414  Cb_temp_21 <= 0;
415  Cb_temp_31 <= 0;
416  Cb_temp_41 <= 0;
417  Cb_temp_51 <= 0;
418  Cb_temp_61 <= 0;
419  Cb_temp_71 <= 0;
420  Cb_temp_81 <= 0;
421  end
422  else if (!enable_1) begin
423  Cb_temp_21 <= 0;
424  Cb_temp_31 <= 0;
425  Cb_temp_41 <= 0;
426  Cb_temp_51 <= 0;
427  Cb_temp_61 <= 0;
428  Cb_temp_71 <= 0;
429  Cb_temp_81 <= 0;
430  end
431  else if (enable_1) begin
439  end
440 end
441 
442 always @(posedge clk)
443 begin
444  if (rst) begin
445  Cb21 <= 0;
446  Cb31 <= 0;
447  Cb41 <= 0;
448  Cb51 <= 0;
449  Cb61 <= 0;
450  Cb71 <= 0;
451  Cb81 <= 0;
452  end
453  else if (!enable_1) begin
454  Cb21 <= 0;
455  Cb31 <= 0;
456  Cb41 <= 0;
457  Cb51 <= 0;
458  Cb61 <= 0;
459  Cb71 <= 0;
460  Cb81 <= 0;
461  end
462  else if (enable_1) begin
463  Cb21 <= Cb_temp_21 + Cb21;
464  Cb31 <= Cb_temp_31 + Cb31;
465  Cb41 <= Cb_temp_41 + Cb41;
466  Cb51 <= Cb_temp_51 + Cb51;
467  Cb61 <= Cb_temp_61 + Cb61;
468  Cb71 <= Cb_temp_71 + Cb71;
469  Cb81 <= Cb_temp_81 + Cb81;
470  end
471 end
472 
473 always @(posedge clk)
474 begin
475  if (rst) begin
476  count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
477  count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
478  count_10 <= 0;
479  end
480  else if (!enable) begin
481  count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
482  count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
483  count_10 <= 0;
484  end
485  else if (enable) begin
486  count <= count + 1; count_3 <= count_1; count_4 <= count_3;
489  end
490 end
491 
492 always @(posedge clk)
493 begin
494  if (rst) begin
495  count_1 <= 0;
496  end
497  else if (count != 7 | !enable) begin
498  count_1 <= 0;
499  end
500  else if (count == 7) begin
501  count_1 <= 1;
502  end
503 end
504 
505 always @(posedge clk)
506 begin
507  if (rst) begin
508  count_of <= 0;
509  count_of_copy <= 0;
510  end
511  else if (!enable) begin
512  count_of <= 0;
513  count_of_copy <= 0;
514  end
515  else if (count_1 == 1) begin
516  count_of <= count_of + 1;
518  end
519 end
520 
521 always @(posedge clk)
522 begin
523  if (rst) begin
524  Cb11_final <= 0;
525  end
526  else if (count_3 & enable_1) begin
527  Cb11_final <= Cb11 - 25'd5932032;
528  /* The Cb values weren't centered on 0 before doing the DCT
529  128 needs to be subtracted from each Cb value before, or in this
530  case, 362 is subtracted from the total, because this is the
531  total obtained by subtracting 128 from each element
532  and then multiplying by the weight
533  assigned by the DCT matrix : 128*8*5793 = 5932032
534  This is only needed for the first row, the values in the rest of
535  the rows add up to 0 **/
536  end
537 end
538 
539 
540 always @(posedge clk)
541 begin
542  if (rst) begin
543  Cb21_final <= 0; Cb21_final_prev <= 0;
544  Cb31_final <= 0; Cb31_final_prev <= 0;
545  Cb41_final <= 0; Cb41_final_prev <= 0;
546  Cb51_final <= 0; Cb51_final_prev <= 0;
547  Cb61_final <= 0; Cb61_final_prev <= 0;
548  Cb71_final <= 0; Cb71_final_prev <= 0;
549  Cb81_final <= 0; Cb81_final_prev <= 0;
550  end
551  else if (!enable_1) begin
552  Cb21_final <= 0; Cb21_final_prev <= 0;
553  Cb31_final <= 0; Cb31_final_prev <= 0;
554  Cb41_final <= 0; Cb41_final_prev <= 0;
555  Cb51_final <= 0; Cb51_final_prev <= 0;
556  Cb61_final <= 0; Cb61_final_prev <= 0;
557  Cb71_final <= 0; Cb71_final_prev <= 0;
558  Cb81_final <= 0; Cb81_final_prev <= 0;
559  end
560  else if (count_4 & enable_1) begin
568  end
569 end
570 
571 always @(posedge clk)
572 begin
573  if (rst) begin
574  Cb21_final_diff <= 0; Cb31_final_diff <= 0;
575  Cb41_final_diff <= 0; Cb51_final_diff <= 0;
576  Cb61_final_diff <= 0; Cb71_final_diff <= 0;
577  Cb81_final_diff <= 0;
578  end
579  else if (count_5 & enable_1) begin
587  end
588 end
589 
590 always @(posedge clk)
591 begin
592  case (count)
593  3'b000: Cb2_mul_input <= T21;
594  3'b001: Cb2_mul_input <= T22;
595  3'b010: Cb2_mul_input <= T23;
596  3'b011: Cb2_mul_input <= T24;
597  3'b100: Cb2_mul_input <= T25;
598  3'b101: Cb2_mul_input <= T26;
599  3'b110: Cb2_mul_input <= T27;
600  3'b111: Cb2_mul_input <= T28;
601  endcase
602 end
603 
604 always @(posedge clk)
605 begin
606  case (count)
607  3'b000: Cb3_mul_input <= T31;
608  3'b001: Cb3_mul_input <= T32;
609  3'b010: Cb3_mul_input <= T33;
610  3'b011: Cb3_mul_input <= T34;
611  3'b100: Cb3_mul_input <= T34;
612  3'b101: Cb3_mul_input <= T33;
613  3'b110: Cb3_mul_input <= T32;
614  3'b111: Cb3_mul_input <= T31;
615  endcase
616 end
617 
618 always @(posedge clk)
619 begin
620  case (count)
621  3'b000: Cb4_mul_input <= T22;
622  3'b001: Cb4_mul_input <= T25;
623  3'b010: Cb4_mul_input <= T28;
624  3'b011: Cb4_mul_input <= T26;
625  3'b100: Cb4_mul_input <= T23;
626  3'b101: Cb4_mul_input <= T21;
627  3'b110: Cb4_mul_input <= T24;
628  3'b111: Cb4_mul_input <= T27;
629  endcase
630 end
631 
632 always @(posedge clk)
633 begin
634  case (count)
635  3'b000: Cb5_mul_input <= T1;
636  3'b001: Cb5_mul_input <= T52;
637  3'b010: Cb5_mul_input <= T52;
638  3'b011: Cb5_mul_input <= T1;
639  3'b100: Cb5_mul_input <= T1;
640  3'b101: Cb5_mul_input <= T52;
641  3'b110: Cb5_mul_input <= T52;
642  3'b111: Cb5_mul_input <= T1;
643  endcase
644 end
645 
646 always @(posedge clk)
647 begin
648  case (count)
649  3'b000: Cb6_mul_input <= T23;
650  3'b001: Cb6_mul_input <= T28;
651  3'b010: Cb6_mul_input <= T24;
652  3'b011: Cb6_mul_input <= T22;
653  3'b100: Cb6_mul_input <= T27;
654  3'b101: Cb6_mul_input <= T25;
655  3'b110: Cb6_mul_input <= T21;
656  3'b111: Cb6_mul_input <= T26;
657  endcase
658 end
659 
660 always @(posedge clk)
661 begin
662  case (count)
663  3'b000: Cb7_mul_input <= T32;
664  3'b001: Cb7_mul_input <= T34;
665  3'b010: Cb7_mul_input <= T31;
666  3'b011: Cb7_mul_input <= T33;
667  3'b100: Cb7_mul_input <= T33;
668  3'b101: Cb7_mul_input <= T31;
669  3'b110: Cb7_mul_input <= T34;
670  3'b111: Cb7_mul_input <= T32;
671  endcase
672 end
673 
674 always @(posedge clk)
675 begin
676  case (count)
677  3'b000: Cb8_mul_input <= T24;
678  3'b001: Cb8_mul_input <= T26;
679  3'b010: Cb8_mul_input <= T22;
680  3'b011: Cb8_mul_input <= T28;
681  3'b100: Cb8_mul_input <= T21;
682  3'b101: Cb8_mul_input <= T27;
683  3'b110: Cb8_mul_input <= T23;
684  3'b111: Cb8_mul_input <= T25;
685  endcase
686 end
687 
688 // Inverse DCT matrix entries
689 always @(posedge clk)
690 begin
691  case (count_of_copy)
692  3'b000: Ti2_mul_input <= Ti28;
693  3'b001: Ti2_mul_input <= Ti21;
694  3'b010: Ti2_mul_input <= Ti22;
695  3'b011: Ti2_mul_input <= Ti23;
696  3'b100: Ti2_mul_input <= Ti24;
697  3'b101: Ti2_mul_input <= Ti25;
698  3'b110: Ti2_mul_input <= Ti26;
699  3'b111: Ti2_mul_input <= Ti27;
700  endcase
701 end
702 
703 always @(posedge clk)
704 begin
705  case (count_of_copy)
706  3'b000: Ti3_mul_input <= Ti31;
707  3'b001: Ti3_mul_input <= Ti31;
708  3'b010: Ti3_mul_input <= Ti32;
709  3'b011: Ti3_mul_input <= Ti33;
710  3'b100: Ti3_mul_input <= Ti34;
711  3'b101: Ti3_mul_input <= Ti34;
712  3'b110: Ti3_mul_input <= Ti33;
713  3'b111: Ti3_mul_input <= Ti32;
714  endcase
715 end
716 
717 always @(posedge clk)
718 begin
719  case (count_of_copy)
720  3'b000: Ti4_mul_input <= Ti27;
721  3'b001: Ti4_mul_input <= Ti22;
722  3'b010: Ti4_mul_input <= Ti25;
723  3'b011: Ti4_mul_input <= Ti28;
724  3'b100: Ti4_mul_input <= Ti26;
725  3'b101: Ti4_mul_input <= Ti23;
726  3'b110: Ti4_mul_input <= Ti21;
727  3'b111: Ti4_mul_input <= Ti24;
728  endcase
729 end
730 
731 always @(posedge clk)
732 begin
733  case (count_of_copy)
734  3'b000: Ti5_mul_input <= Ti1;
735  3'b001: Ti5_mul_input <= Ti1;
736  3'b010: Ti5_mul_input <= Ti52;
737  3'b011: Ti5_mul_input <= Ti52;
738  3'b100: Ti5_mul_input <= Ti1;
739  3'b101: Ti5_mul_input <= Ti1;
740  3'b110: Ti5_mul_input <= Ti52;
741  3'b111: Ti5_mul_input <= Ti52;
742  endcase
743 end
744 
745 always @(posedge clk)
746 begin
747  case (count_of_copy)
748  3'b000: Ti6_mul_input <= Ti26;
749  3'b001: Ti6_mul_input <= Ti23;
750  3'b010: Ti6_mul_input <= Ti28;
751  3'b011: Ti6_mul_input <= Ti24;
752  3'b100: Ti6_mul_input <= Ti22;
753  3'b101: Ti6_mul_input <= Ti27;
754  3'b110: Ti6_mul_input <= Ti25;
755  3'b111: Ti6_mul_input <= Ti21;
756  endcase
757 end
758 
759 always @(posedge clk)
760 begin
761  case (count_of_copy)
762  3'b000: Ti7_mul_input <= Ti32;
763  3'b001: Ti7_mul_input <= Ti32;
764  3'b010: Ti7_mul_input <= Ti34;
765  3'b011: Ti7_mul_input <= Ti31;
766  3'b100: Ti7_mul_input <= Ti33;
767  3'b101: Ti7_mul_input <= Ti33;
768  3'b110: Ti7_mul_input <= Ti31;
769  3'b111: Ti7_mul_input <= Ti34;
770  endcase
771 end
772 
773 always @(posedge clk)
774 begin
775  case (count_of_copy)
776  3'b000: Ti8_mul_input <= Ti25;
777  3'b001: Ti8_mul_input <= Ti24;
778  3'b010: Ti8_mul_input <= Ti26;
779  3'b011: Ti8_mul_input <= Ti22;
780  3'b100: Ti8_mul_input <= Ti28;
781  3'b101: Ti8_mul_input <= Ti21;
782  3'b110: Ti8_mul_input <= Ti27;
783  3'b111: Ti8_mul_input <= Ti23;
784  endcase
785 end
786 
787 // Rounding stage
788 always @(posedge clk)
789 begin
790  if (rst) begin
791  data_1 <= 0;
792  Cb11_final_1 <= 0; Cb21_final_1 <= 0; Cb31_final_1 <= 0; Cb41_final_1 <= 0;
793  Cb51_final_1 <= 0; Cb61_final_1 <= 0; Cb71_final_1 <= 0; Cb81_final_1 <= 0;
794  Cb11_final_2 <= 0; Cb21_final_2 <= 0; Cb31_final_2 <= 0; Cb41_final_2 <= 0;
795  Cb51_final_2 <= 0; Cb61_final_2 <= 0; Cb71_final_2 <= 0; Cb81_final_2 <= 0;
796  Cb11_final_3 <= 0; Cb11_final_4 <= 0;
797  end
798  else if (enable) begin
799  data_1 <= data_in;
800  Cb11_final_1 <= Cb11_final[13] ? Cb11_final[24:14] + 1 : Cb11_final[24:14];
801  Cb11_final_2[31:11] <= Cb11_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
802  Cb11_final_2[10:0] <= Cb11_final_1;
803  // Need to sign extend Cb11_final_1 and the other registers to store a negative
804  // number as a twos complement number. If you don't sign extend, then a negative number
805  // will be stored incorrectly as a positive number. For example, -215 would be stored
806  // as 1833 without sign extending
809  Cb21_final_1 <= Cb21_final_diff[13] ? Cb21_final_diff[24:14] + 1 : Cb21_final_diff[24:14];
810  Cb21_final_2[31:11] <= Cb21_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
811  Cb21_final_2[10:0] <= Cb21_final_1;
812  Cb31_final_1 <= Cb31_final_diff[13] ? Cb31_final_diff[24:14] + 1 : Cb31_final_diff[24:14];
813  Cb31_final_2[31:11] <= Cb31_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
814  Cb31_final_2[10:0] <= Cb31_final_1;
815  Cb41_final_1 <= Cb41_final_diff[13] ? Cb41_final_diff[24:14] + 1 : Cb41_final_diff[24:14];
816  Cb41_final_2[31:11] <= Cb41_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
817  Cb41_final_2[10:0] <= Cb41_final_1;
818  Cb51_final_1 <= Cb51_final_diff[13] ? Cb51_final_diff[24:14] + 1 : Cb51_final_diff[24:14];
819  Cb51_final_2[31:11] <= Cb51_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
820  Cb51_final_2[10:0] <= Cb51_final_1;
821  Cb61_final_1 <= Cb61_final_diff[13] ? Cb61_final_diff[24:14] + 1 : Cb61_final_diff[24:14];
822  Cb61_final_2[31:11] <= Cb61_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
823  Cb61_final_2[10:0] <= Cb61_final_1;
824  Cb71_final_1 <= Cb71_final_diff[13] ? Cb71_final_diff[24:14] + 1 : Cb71_final_diff[24:14];
825  Cb71_final_2[31:11] <= Cb71_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
826  Cb71_final_2[10:0] <= Cb71_final_1;
827  Cb81_final_1 <= Cb81_final_diff[13] ? Cb81_final_diff[24:14] + 1 : Cb81_final_diff[24:14];
828  Cb81_final_2[31:11] <= Cb81_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
829  Cb81_final_2[10:0] <= Cb81_final_1;
830  // The bit in place 13 is the fraction part, for rounding purposes
831  // if it is 1, then you need to add 1 to the bits in 22-14,
832  // if bit 13 is 0, then the bits in 22-14 won't change
833  end
834 end
835 
836 always @(posedge clk)
837 begin
838  if (rst) begin
839  enable_1 <= 0;
840  end
841  else begin
842  enable_1 <= enable;
843  end
844 end
845 
846 endmodule
1897Z85_finalreg[10:0]
Definition: cr_dct.v:140
1644Ti25integer
Definition: cr_dct.v:82
1819Cb51_finalreg[24:0]
Definition: cr_dct.v:116
1817Cb31_finalreg[24:0]
Definition: cr_dct.v:116
1699Z_temp_46reg[31:0]
Definition: cr_dct.v:95
1677Z_temp_18reg[31:0]
Definition: cr_dct.v:89
1679Z_temp_22reg[31:0]
Definition: cr_dct.v:90
1756Z37reg[24:0]
Definition: cr_dct.v:106
1882Z66_finalreg[10:0]
Definition: cr_dct.v:136
1659Cb61reg[24:0]
Definition: cr_dct.v:85
1841Z15_finalreg[10:0]
Definition: cr_dct.v:126
1814Cb71_final_1reg[10:0]
Definition: cr_dct.v:115
1723Z_temp_76reg[31:0]
Definition: cr_dct.v:101
1895Z83_finalreg[10:0]
Definition: cr_dct.v:139
1708Z_temp_57reg[31:0]
Definition: cr_dct.v:97
1709Z_temp_58reg[31:0]
Definition: cr_dct.v:97
1811Cb41_final_1reg[10:0]
Definition: cr_dct.v:114
1685Z_temp_28reg[31:0]
Definition: cr_dct.v:91
1917Cb3_mul_inputinteger
Definition: cr_dct.v:146
1789Z78reg[24:0]
Definition: cr_dct.v:110
1693Z_temp_38reg[31:0]
Definition: cr_dct.v:93
1742Z21reg[24:0]
Definition: cr_dct.v:105
1928Ti7_mul_inputinteger
Definition: cr_dct.v:149
1692Z_temp_37reg[31:0]
Definition: cr_dct.v:93
1653Cb_temp_11reg[24:0]
Definition: cr_dct.v:84
1929Ti8_mul_inputinteger
Definition: cr_dct.v:149
1671Z_temp_12reg[31:0]
Definition: cr_dct.v:88
1625T1integer
Definition: cr_dct.v:81
1818Cb41_finalreg[24:0]
Definition: cr_dct.v:116
1556clk
Definition: cr_dct.v:58
1767Z52reg[24:0]
Definition: cr_dct.v:108
1705Z_temp_54reg[31:0]
Definition: cr_dct.v:96
1626T21integer
Definition: cr_dct.v:81
1920Cb6_mul_inputinteger
Definition: cr_dct.v:147
1694Z_temp_41reg[31:0]
Definition: cr_dct.v:94
1853Z31_finalreg[10:0]
Definition: cr_dct.v:129
1784Z73reg[24:0]
Definition: cr_dct.v:110
1728Z_temp_83reg[31:0]
Definition: cr_dct.v:102
1786Z75reg[24:0]
Definition: cr_dct.v:110
1654Cb11reg[24:0]
Definition: cr_dct.v:85
1673Z_temp_14reg[31:0]
Definition: cr_dct.v:88
1852Z28_finalreg[10:0]
Definition: cr_dct.v:128
1927Ti6_mul_inputinteger
Definition: cr_dct.v:149
1794Z85reg[24:0]
Definition: cr_dct.v:111
1706Z_temp_55reg[31:0]
Definition: cr_dct.v:97
1805Cb61_final_2reg[31:0]
Definition: cr_dct.v:113
1923Ti2_mul_inputinteger
Definition: cr_dct.v:148
1701Z_temp_48reg[31:0]
Definition: cr_dct.v:95
1686Z_temp_31reg[31:0]
Definition: cr_dct.v:92
1822Cb81_finalreg[24:0]
Definition: cr_dct.v:117
1632T27integer
Definition: cr_dct.v:81
1684Z_temp_27reg[31:0]
Definition: cr_dct.v:91
1670Z_temp_11reg[31:0]
Definition: cr_dct.v:88
1734Z11reg[24:0]
Definition: cr_dct.v:104
1665Cb_temp_41reg[31:0]
Definition: cr_dct.v:86
1674Z_temp_15reg[31:0]
Definition: cr_dct.v:89
1763Z46reg[24:0]
Definition: cr_dct.v:107
1905count_3reg
Definition: cr_dct.v:143
1893Z81_finalreg[10:0]
Definition: cr_dct.v:139
1698Z_temp_45reg[31:0]
Definition: cr_dct.v:95
1918Cb4_mul_inputinteger
Definition: cr_dct.v:146
1887Z73_finalreg[10:0]
Definition: cr_dct.v:137
1886Z72_finalreg[10:0]
Definition: cr_dct.v:137
1658Cb51reg[24:0]
Definition: cr_dct.v:85
1849Z25_finalreg[10:0]
Definition: cr_dct.v:128
1750Z31reg[24:0]
Definition: cr_dct.v:106
1845Z21_finalreg[10:0]
Definition: cr_dct.v:127
1860Z38_finalreg[10:0]
Definition: cr_dct.v:130
1851Z27_finalreg[10:0]
Definition: cr_dct.v:128
1799Cb21_final_2reg[31:0]
Definition: cr_dct.v:112
1737Z14reg[24:0]
Definition: cr_dct.v:104
1738Z15reg[24:0]
Definition: cr_dct.v:104
1636T33integer
Definition: cr_dct.v:81
1821Cb71_finalreg[24:0]
Definition: cr_dct.v:117
1656Cb31reg[24:0]
Definition: cr_dct.v:85
1691Z_temp_36reg[31:0]
Definition: cr_dct.v:93
1633T28integer
Definition: cr_dct.v:81
1787Z76reg[24:0]
Definition: cr_dct.v:110
1791Z82reg[24:0]
Definition: cr_dct.v:111
1721Z_temp_74reg[31:0]
Definition: cr_dct.v:100
1873Z55_finalreg[10:0]
Definition: cr_dct.v:134
1793Z84reg[24:0]
Definition: cr_dct.v:111
1836Cb81_final_diffreg[24:0]
Definition: cr_dct.v:124
1809Cb21_final_1reg[10:0]
Definition: cr_dct.v:114
1759Z42reg[24:0]
Definition: cr_dct.v:107
1863Z43_finalreg[10:0]
Definition: cr_dct.v:131
1726Z_temp_81reg[31:0]
Definition: cr_dct.v:102
1689Z_temp_34reg[31:0]
Definition: cr_dct.v:92
1823Cb21_final_prevreg[24:0]
Definition: cr_dct.v:118
1651Ti34integer
Definition: cr_dct.v:82
1744Z23reg[24:0]
Definition: cr_dct.v:105
1900Z88_finalreg[10:0]
Definition: cr_dct.v:140
1702Z_temp_51reg[31:0]
Definition: cr_dct.v:96
1745Z24reg[24:0]
Definition: cr_dct.v:105
1901countreg[2:0]
Definition: cr_dct.v:141
1833Cb71_final_prevreg[24:0]
Definition: cr_dct.v:123
1862Z42_finalreg[10:0]
Definition: cr_dct.v:131
1634T31integer
Definition: cr_dct.v:81
1777Z64reg[24:0]
Definition: cr_dct.v:109
1835Cb81_final_prevreg[24:0]
Definition: cr_dct.v:124
1629T24integer
Definition: cr_dct.v:81
1866Z46_finalreg[10:0]
Definition: cr_dct.v:132
1792Z83reg[24:0]
Definition: cr_dct.v:111
1666Cb_temp_51reg[31:0]
Definition: cr_dct.v:86
1757Z38reg[24:0]
Definition: cr_dct.v:106
1864Z44_finalreg[10:0]
Definition: cr_dct.v:131
1785Z74reg[24:0]
Definition: cr_dct.v:110
1716Z_temp_67reg[31:0]
Definition: cr_dct.v:99
1778Z65reg[24:0]
Definition: cr_dct.v:109
1790Z81reg[24:0]
Definition: cr_dct.v:111
1898Z86_finalreg[10:0]
Definition: cr_dct.v:140
1766Z51reg[24:0]
Definition: cr_dct.v:108
1661Cb81reg[24:0]
Definition: cr_dct.v:85
1760Z43reg[24:0]
Definition: cr_dct.v:107
1907count_5reg
Definition: cr_dct.v:143
1739Z16reg[24:0]
Definition: cr_dct.v:104
1826Cb31_final_diffreg[24:0]
Definition: cr_dct.v:119
1662Cb11_finalreg[24:0]
Definition: cr_dct.v:85
1761Z44reg[24:0]
Definition: cr_dct.v:107
1710Z_temp_61reg[31:0]
Definition: cr_dct.v:98
1899Z87_finalreg[10:0]
Definition: cr_dct.v:140
1774Z61reg[24:0]
Definition: cr_dct.v:109
1736Z13reg[24:0]
Definition: cr_dct.v:104
1828Cb41_final_diffreg[24:0]
Definition: cr_dct.v:120
1906count_4reg
Definition: cr_dct.v:143
1820Cb61_finalreg[24:0]
Definition: cr_dct.v:117
1715Z_temp_66reg[31:0]
Definition: cr_dct.v:99
1770Z55reg[24:0]
Definition: cr_dct.v:108
1743Z22reg[24:0]
Definition: cr_dct.v:105
1735Z12reg[24:0]
Definition: cr_dct.v:104
1782Z71reg[24:0]
Definition: cr_dct.v:110
1642Ti23integer
Definition: cr_dct.v:82
1748Z27reg[24:0]
Definition: cr_dct.v:105
1803Cb41_final_2reg[31:0]
Definition: cr_dct.v:112
1911enable_1reg
Definition: cr_dct.v:143
1857Z35_finalreg[10:0]
Definition: cr_dct.v:130
1796Z87reg[24:0]
Definition: cr_dct.v:111
1683Z_temp_26reg[31:0]
Definition: cr_dct.v:91
1557rst
Definition: cr_dct.v:59
1813Cb61_final_1reg[10:0]
Definition: cr_dct.v:115
1839Z13_finalreg[10:0]
Definition: cr_dct.v:125
1764Z47reg[24:0]
Definition: cr_dct.v:107
1825Cb31_final_prevreg[24:0]
Definition: cr_dct.v:119
1922Cb8_mul_inputinteger
Definition: cr_dct.v:147
1652Ti52integer
Definition: cr_dct.v:82
1703Z_temp_52reg[31:0]
Definition: cr_dct.v:96
1861Z41_finalreg[10:0]
Definition: cr_dct.v:131
1829Cb51_final_prevreg[24:0]
Definition: cr_dct.v:121
1795Z86reg[24:0]
Definition: cr_dct.v:111
1558enable
Definition: cr_dct.v:60
1628T23integer
Definition: cr_dct.v:81
1874Z56_finalreg[10:0]
Definition: cr_dct.v:134
1902count_ofreg[2:0]
Definition: cr_dct.v:142
1801Cb11_final_4reg[31:0]
Definition: cr_dct.v:112
1773Z58reg[24:0]
Definition: cr_dct.v:108
1704Z_temp_53reg[31:0]
Definition: cr_dct.v:96
1908count_6reg
Definition: cr_dct.v:143
1847Z23_finalreg[10:0]
Definition: cr_dct.v:127
1884Z68_finalreg[10:0]
Definition: cr_dct.v:136
1762Z45reg[24:0]
Definition: cr_dct.v:107
1648Ti31integer
Definition: cr_dct.v:82
1834Cb71_final_diffreg[24:0]
Definition: cr_dct.v:123
1752Z33reg[24:0]
Definition: cr_dct.v:106
1725Z_temp_78reg[31:0]
Definition: cr_dct.v:101
1731Z_temp_86reg[31:0]
Definition: cr_dct.v:103
1755Z36reg[24:0]
Definition: cr_dct.v:106
1914count_10reg
Definition: cr_dct.v:144
1676Z_temp_17reg[31:0]
Definition: cr_dct.v:89
1675Z_temp_16reg[31:0]
Definition: cr_dct.v:89
1765Z48reg[24:0]
Definition: cr_dct.v:107
1880Z64_finalreg[10:0]
Definition: cr_dct.v:135
1891Z77_finalreg[10:0]
Definition: cr_dct.v:138
1832Cb61_final_diffreg[24:0]
Definition: cr_dct.v:122
1909count_7reg
Definition: cr_dct.v:143
1877Z61_finalreg[10:0]
Definition: cr_dct.v:135
1669Cb_temp_81reg[31:0]
Definition: cr_dct.v:87
1875Z57_finalreg[10:0]
Definition: cr_dct.v:134
1788Z77reg[24:0]
Definition: cr_dct.v:110
1631T26integer
Definition: cr_dct.v:81
1776Z63reg[24:0]
Definition: cr_dct.v:109
1697Z_temp_44reg[31:0]
Definition: cr_dct.v:94
1641Ti22integer
Definition: cr_dct.v:82
1695Z_temp_42reg[31:0]
Definition: cr_dct.v:94
[7:0] 1559data_in
Definition: cr_dct.v:61
1913count_9reg
Definition: cr_dct.v:144
1637T34integer
Definition: cr_dct.v:81
1727Z_temp_82reg[31:0]
Definition: cr_dct.v:102
1844Z18_finalreg[10:0]
Definition: cr_dct.v:126
1643Ti24integer
Definition: cr_dct.v:82
1896Z84_finalreg[10:0]
Definition: cr_dct.v:139
1868Z48_finalreg[10:0]
Definition: cr_dct.v:132
1824Cb21_final_diffreg[24:0]
Definition: cr_dct.v:118
1713Z_temp_64reg[31:0]
Definition: cr_dct.v:98
1878Z62_finalreg[10:0]
Definition: cr_dct.v:135
1800Cb11_final_3reg[31:0]
Definition: cr_dct.v:112
1657Cb41reg[24:0]
Definition: cr_dct.v:85
1712Z_temp_63reg[31:0]
Definition: cr_dct.v:98
1707Z_temp_56reg[31:0]
Definition: cr_dct.v:97
1751Z32reg[24:0]
Definition: cr_dct.v:106
1859Z37_finalreg[10:0]
Definition: cr_dct.v:130
1746Z25reg[24:0]
Definition: cr_dct.v:105
1856Z34_finalreg[10:0]
Definition: cr_dct.v:129
1779Z66reg[24:0]
Definition: cr_dct.v:109
1810Cb31_final_1reg[10:0]
Definition: cr_dct.v:114
1843Z17_finalreg[10:0]
Definition: cr_dct.v:126
1630T25integer
Definition: cr_dct.v:81
1919Cb5_mul_inputinteger
Definition: cr_dct.v:146
Definition: cr_dct.v:48
1646Ti27integer
Definition: cr_dct.v:82
1890Z76_finalreg[10:0]
Definition: cr_dct.v:138
1827Cb41_final_prevreg[24:0]
Definition: cr_dct.v:120
1888Z74_finalreg[10:0]
Definition: cr_dct.v:137
1797Z88reg[24:0]
Definition: cr_dct.v:111
1871Z53_finalreg[10:0]
Definition: cr_dct.v:133
1730Z_temp_85reg[31:0]
Definition: cr_dct.v:103
1838Z12_finalreg[10:0]
Definition: cr_dct.v:125
1719Z_temp_72reg[31:0]
Definition: cr_dct.v:100
1870Z52_finalreg[10:0]
Definition: cr_dct.v:133
1876Z58_finalreg[10:0]
Definition: cr_dct.v:134
1753Z34reg[24:0]
Definition: cr_dct.v:106
1660Cb71reg[24:0]
Definition: cr_dct.v:85
1924Ti3_mul_inputinteger
Definition: cr_dct.v:148
1816Cb21_finalreg[24:0]
Definition: cr_dct.v:116
1846Z22_finalreg[10:0]
Definition: cr_dct.v:127
1921Cb7_mul_inputinteger
Definition: cr_dct.v:147
1808Cb11_final_1reg[10:0]
Definition: cr_dct.v:114
1889Z75_finalreg[10:0]
Definition: cr_dct.v:138
1872Z54_finalreg[10:0]
Definition: cr_dct.v:133
1892Z78_finalreg[10:0]
Definition: cr_dct.v:138
1807Cb81_final_2reg[31:0]
Definition: cr_dct.v:113
1802Cb31_final_2reg[31:0]
Definition: cr_dct.v:112
1768Z53reg[24:0]
Definition: cr_dct.v:108
1655Cb21reg[24:0]
Definition: cr_dct.v:85
1855Z33_finalreg[10:0]
Definition: cr_dct.v:129
1687Z_temp_32reg[31:0]
Definition: cr_dct.v:92
1775Z62reg[24:0]
Definition: cr_dct.v:109
1894Z82_finalreg[10:0]
Definition: cr_dct.v:139
1740Z17reg[24:0]
Definition: cr_dct.v:104
1854Z32_finalreg[10:0]
Definition: cr_dct.v:129
1858Z36_finalreg[10:0]
Definition: cr_dct.v:130
1812Cb51_final_1reg[10:0]
Definition: cr_dct.v:115
1754Z35reg[24:0]
Definition: cr_dct.v:106
1780Z67reg[24:0]
Definition: cr_dct.v:109
1700Z_temp_47reg[31:0]
Definition: cr_dct.v:95
1733Z_temp_88reg[31:0]
Definition: cr_dct.v:103
1649Ti32integer
Definition: cr_dct.v:82
1879Z63_finalreg[10:0]
Definition: cr_dct.v:135
1682Z_temp_25reg[31:0]
Definition: cr_dct.v:91
1717Z_temp_68reg[31:0]
Definition: cr_dct.v:99
1885Z71_finalreg[10:0]
Definition: cr_dct.v:137
1830Cb51_final_diffreg[24:0]
Definition: cr_dct.v:121
1771Z56reg[24:0]
Definition: cr_dct.v:108
1664Cb_temp_31reg[31:0]
Definition: cr_dct.v:86
1910count_8reg
Definition: cr_dct.v:143
1772Z57reg[24:0]
Definition: cr_dct.v:108
1749Z28reg[24:0]
Definition: cr_dct.v:105
1912output_enablereg
Definition: cr_dct.v:143
1720Z_temp_73reg[31:0]
Definition: cr_dct.v:100
1758Z41reg[24:0]
Definition: cr_dct.v:107
1638T52integer
Definition: cr_dct.v:81
1729Z_temp_84reg[31:0]
Definition: cr_dct.v:102
1635T32integer
Definition: cr_dct.v:81
1840Z14_finalreg[10:0]
Definition: cr_dct.v:125
1678Z_temp_21reg[31:0]
Definition: cr_dct.v:90
1926Ti5_mul_inputinteger
Definition: cr_dct.v:148
1837Z11_finalreg[10:0]
Definition: cr_dct.v:125
1904count_1reg
Definition: cr_dct.v:143
1696Z_temp_43reg[31:0]
Definition: cr_dct.v:94
1798Cb11_final_2reg[31:0]
Definition: cr_dct.v:112
1681Z_temp_24reg[31:0]
Definition: cr_dct.v:90
1722Z_temp_75reg[31:0]
Definition: cr_dct.v:101
1881Z65_finalreg[10:0]
Definition: cr_dct.v:136
1668Cb_temp_71reg[31:0]
Definition: cr_dct.v:87
1647Ti28integer
Definition: cr_dct.v:82
1831Cb61_final_prevreg[24:0]
Definition: cr_dct.v:122
1718Z_temp_71reg[31:0]
Definition: cr_dct.v:100
1869Z51_finalreg[10:0]
Definition: cr_dct.v:133
1925Ti4_mul_inputinteger
Definition: cr_dct.v:148
1663Cb_temp_21reg[31:0]
Definition: cr_dct.v:86
1815Cb81_final_1reg[10:0]
Definition: cr_dct.v:115
1724Z_temp_77reg[31:0]
Definition: cr_dct.v:101
1650Ti33integer
Definition: cr_dct.v:82
1667Cb_temp_61reg[31:0]
Definition: cr_dct.v:87
1714Z_temp_65reg[31:0]
Definition: cr_dct.v:99
1783Z72reg[24:0]
Definition: cr_dct.v:110
1741Z18reg[24:0]
Definition: cr_dct.v:104
1732Z_temp_87reg[31:0]
Definition: cr_dct.v:103
1916Cb2_mul_inputinteger
Definition: cr_dct.v:146
1915data_1reg[7:0]
Definition: cr_dct.v:145
1672Z_temp_13reg[31:0]
Definition: cr_dct.v:88
1867Z47_finalreg[10:0]
Definition: cr_dct.v:132
1883Z67_finalreg[10:0]
Definition: cr_dct.v:136
1769Z54reg[24:0]
Definition: cr_dct.v:108
1640Ti21integer
Definition: cr_dct.v:82
1711Z_temp_62reg[31:0]
Definition: cr_dct.v:98
1747Z26reg[24:0]
Definition: cr_dct.v:105
1865Z45_finalreg[10:0]
Definition: cr_dct.v:132
1903count_of_copyreg[2:0]
Definition: cr_dct.v:142
1639Ti1integer
Definition: cr_dct.v:82
1850Z26_finalreg[10:0]
Definition: cr_dct.v:128
1806Cb71_final_2reg[31:0]
Definition: cr_dct.v:113
1690Z_temp_35reg[31:0]
Definition: cr_dct.v:93
1645Ti26integer
Definition: cr_dct.v:82
1781Z68reg[24:0]
Definition: cr_dct.v:109
1688Z_temp_33reg[31:0]
Definition: cr_dct.v:92
1627T22integer
Definition: cr_dct.v:81
1842Z16_finalreg[10:0]
Definition: cr_dct.v:126
1680Z_temp_23reg[31:0]
Definition: cr_dct.v:90
1848Z24_finalreg[10:0]
Definition: cr_dct.v:127
1804Cb51_final_2reg[31:0]
Definition: cr_dct.v:113