oc_jpegencode 1.0 JPEGencoder

sync_fifo_ff.v
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1 /////////////////////////////////////////////////////////////////////
2 //// ////
3 //// JPEG Encoder Core - Verilog ////
4 //// ////
5 //// Author: David Lundgren ////
6 //// davidklun@gmail.com ////
7 //// ////
8 /////////////////////////////////////////////////////////////////////
9 //// ////
10 //// Copyright (C) 2009 David Lundgren ////
11 //// davidklun@gmail.com ////
12 //// ////
13 //// This source file may be used and distributed without ////
14 //// restriction provided that this copyright statement is not ////
15 //// removed from the file and that any derivative work contains ////
16 //// the original copyright notice and the associated disclaimer.////
17 //// ////
18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
30 //// POSSIBILITY OF SUCH DAMAGE. ////
31 //// ////
32 /////////////////////////////////////////////////////////////////////
33
34 /* This FIFO is used for the ff_checker module. **/
35
36 `timescale 1ns / 100ps
37
38 module sync_fifo_ff (clk, rst, read_req, write_data, write_enable, rollover_write,
39 read_data, fifo_empty, rdata_valid);
40 input clk;
41 input rst;
42 input read_req;
43 input [90:0] write_data;
44 input write_enable;
45 input rollover_write;
46 output [90:0] read_data;
47 output fifo_empty;
48 output rdata_valid;
49
50 reg [4:0] read_ptr;
51 reg [4:0] write_ptr;
52 reg [90:0] mem [0:15];
53 reg [90:0] read_data;
54 reg rdata_valid;
55 wire [3:0] write_addr = write_ptr[3:0];
56 wire [3:0] read_addr = read_ptr[3:0];
57 wire read_enable = read_req && (~fifo_empty);
58 assign fifo_empty = (read_ptr == write_ptr);
59
60
61 always @(posedge clk)
62 begin
63 if (rst)
64 write_ptr <= {(5){1'b0}};
65 else if (write_enable & !rollover_write)
66 write_ptr <= write_ptr + {{4{1'b0}},1'b1};
67 else if (write_enable & rollover_write)
68 write_ptr <= write_ptr + 5'b00010;
69 // A rollover_write means that there have been a total of 4 FF's
70 // that have been detected in the bitstream. So an extra set of 32
71 // bits will be put into the bitstream (due to the 4 extra 00's added
72 // after the 4 FF's), and the input data will have to
73 // be delayed by 1 clock cycle as it makes its way into the output
74 // bitstream. So the write_ptr is incremented by 2 for a rollover, giving
75 // the output the extra clock cycle it needs to write the
76 // extra 32 bits to the bitstream. The output
77 // will read the dummy data from the FIFO, but won't do anything with it,
78 // it will be putting the extra set of 32 bits into the bitstream on that
79 // clock cycle.
80 end
81
82 always @(posedge clk)
83 begin
84 if (rst)
85 rdata_valid <= 1'b0;
86 else if (read_enable)
87 rdata_valid <= 1'b1;
88 else
89 rdata_valid <= 1'b0;
90 end
91
92 always @(posedge clk)
93 begin
94 if (rst)
95 read_ptr <= {(5){1'b0}};
96 else if (read_enable)
97 read_ptr <= read_ptr + {{4{1'b0}},1'b1};
98 end
99
100 // Mem write
101 always @(posedge clk)
102 begin
103 if (write_enable)
104 mem[write_addr] <= write_data;
105 end
106 // Mem Read
107 always @(posedge clk)
108 begin
109 if (read_enable)
110 read_data <= mem[read_addr];
111 end
112
113 endmodule
sync_fifo_ff
Definition: sync_fifo_ff.v:38
sync_fifo_ff.3481write_ptr
3481write_ptrreg[4:0]
Definition: sync_fifo_ff.v:51
sync_fifo_ff.3485write_addr
3485write_addrwire[3:0]
Definition: sync_fifo_ff.v:55
sync_fifo_ff.3480read_ptr
3480read_ptrreg[4:0]
Definition: sync_fifo_ff.v:50
sync_fifo_ff.3487read_enable
3487read_enablewire
Definition: sync_fifo_ff.v:57
sync_fifo_ff.3483read_data
3483read_datareg[90:0]
Definition: sync_fifo_ff.v:53
sync_fifo_ff.3482mem
[0:15] 3482memreg[90:0]
Definition: sync_fifo_ff.v:52
sync_fifo_ff.3471clk
3471clk
Definition: sync_fifo_ff.v:40
sync_fifo_ff.3473read_req
3473read_req
Definition: sync_fifo_ff.v:42
sync_fifo_ff.3486read_addr
3486read_addrwire[3:0]
Definition: sync_fifo_ff.v:56
sync_fifo_ff.3484rdata_valid
3484rdata_validreg
Definition: sync_fifo_ff.v:54
sync_fifo_ff.3475write_enable
3475write_enable
Definition: sync_fifo_ff.v:44
sync_fifo_ff.3474write_data
[90:0] 3474write_data
Definition: sync_fifo_ff.v:43
sync_fifo_ff.3478fifo_empty
3478fifo_empty
Definition: sync_fifo_ff.v:47
sync_fifo_ff.3476rollover_write
3476rollover_write
Definition: sync_fifo_ff.v:45
sync_fifo_ff.3472rst
3472rst
Definition: sync_fifo_ff.v:41