oc_jpegencode  1.0
JPEGencoder
fifo_out.v
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1 /////////////////////////////////////////////////////////////////////
2 //// ////
3 //// JPEG Encoder Core - Verilog ////
4 //// ////
5 //// Author: David Lundgren ////
6 //// davidklun@gmail.com ////
7 //// ////
8 /////////////////////////////////////////////////////////////////////
9 //// ////
10 //// Copyright (C) 2009 David Lundgren ////
11 //// davidklun@gmail.com ////
12 //// ////
13 //// This source file may be used and distributed without ////
14 //// restriction provided that this copyright statement is not ////
15 //// removed from the file and that any derivative work contains ////
16 //// the original copyright notice and the associated disclaimer.////
17 //// ////
18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
30 //// POSSIBILITY OF SUCH DAMAGE. ////
31 //// ////
32 /////////////////////////////////////////////////////////////////////
33 
34 /* This module takes the y, cb, and cr inputs from the pre_fifo module,
35 and it combines the bits into the jpeg_bitstream. It uses 3 FIFO's to
36 write the y, cb, and cr data while it's processing the data. The output
37 of this module goes to the input of the ff_checker module, to check for
38 any FF's in the bitstream.
39 */
40 `timescale 1ns / 100ps
41 
43 input clk, rst, enable;
44 input [23:0] data_in;
45 output [31:0] JPEG_bitstream;
46 output data_ready;
47 output [4:0] orc_reg;
48 
49 
50 
52 wire [4:0] cr_orc, cb_orc, y_orc;
53 wire [31:0] y_bits_out;
62 reg [4:0] static_orc_6;
106 
107 
116 
121 
126 
131 
136 
141 
142  always @(posedge clk)
143  begin
144  if (rst)
145  fifo_mux <= 0;
146  else if (end_of_block_output)
147  fifo_mux <= fifo_mux + 1;
148  end
149 
150 always @(posedge clk)
151 begin
152  if (y_fifo_empty || read_mux != 3'b001)
153  y_read_req <= 0;
154  else if (!y_fifo_empty && read_mux == 3'b001)
155  y_read_req <= 1;
156 end
157 
158 always @(posedge clk)
159 begin
160  if (cb_fifo_empty || read_mux != 3'b010)
161  cb_read_req <= 0;
162  else if (!cb_fifo_empty && read_mux == 3'b010)
163  cb_read_req <= 1;
164 end
165 
166 always @(posedge clk)
167 begin
168  if (cr_fifo_empty || read_mux != 3'b100)
169  cr_read_req <= 0;
170  else if (!cr_fifo_empty && read_mux == 3'b100)
171  cr_read_req <= 1;
172 end
173 
174 always @(posedge clk)
175 begin
176  if (rst) begin
177  br_1 <= 0; br_2 <= 0; br_3 <= 0; br_4 <= 0; br_5 <= 0; br_6 <= 0;
178  br_7 <= 0; br_8 <= 0;
179  static_orc_1 <= 0; static_orc_2 <= 0; static_orc_3 <= 0;
180  static_orc_4 <= 0; static_orc_5 <= 0; static_orc_6 <= 0;
181  data_ready <= 0; eobe_1 <= 0;
182  end
183  else begin
184  br_1 <= bits_ready & !eobe_1; br_2 <= br_1; br_3 <= br_2;
185  br_4 <= br_3; br_5 <= br_4; br_6 <= br_5;
186  br_7 <= br_6; br_8 <= br_7;
191  eobe_1 <= y_eob_empty;
192  end
193 end
194 
195 always @(posedge clk)
196 begin
197  if (rst)
198  rollover_eob <= 0;
199  else if (br_3)
201 end
202 
203 always @(posedge clk)
204 begin
205  if (rst) begin
206  rollover_1 <= 0; rollover_2 <= 0; rollover_3 <= 0;
207  rollover_4 <= 0; rollover_5 <= 0; rollover_6 <= 0;
208  rollover_7 <= 0; eob_1 <= 0; eob_2 <= 0;
209  eob_3 <= 0; eob_4 <= 0;
210  eob_early_out_enable <= 0;
211  end
212  else begin
218  eob_2 <= eob_1; eob_3 <= eob_2; eob_4 <= eob_3;
220  end
221 end
222 
223 always @(posedge clk)
224 begin
225  case (bits_mux)
229  default: rollover <= y_out_enable_1 & !eob_4;
230  endcase
231 end
232 
233 always @(posedge clk)
234 begin
235  if (rst)
236  orc <= 0;
237  else if (enable_20)
238  orc <= orc_cr + cr_orc_1;
239 end
240 
241 always @(posedge clk)
242 begin
243  if (rst)
244  orc_cb <= 0;
245  else if (eob_1)
246  orc_cb <= orc + y_orc_1;
247 end
248 
249 always @(posedge clk)
250 begin
251  if (rst)
252  orc_cr <= 0;
253  else if (enable_5)
254  orc_cr <= orc_cb + cb_orc_1;
255 end
256 
257 always @(posedge clk)
258 begin
259  if (rst) begin
261  end
262  else begin
266  end
267 end
268 
269 always @(posedge clk)
270 begin
271  case (bits_mux)
272  3'b001: jpeg <= y_bits_out;
273  3'b010: jpeg <= cb_bits_out;
274  3'b100: jpeg <= cr_bits_out;
275  default: jpeg <= y_bits_out;
276  endcase
277 end
278 
279 always @(posedge clk)
280 begin
281  case (bits_mux)
282  3'b001: bits_ready <= y_out_enable;
283  3'b010: bits_ready <= cb_out_enable;
284  3'b100: bits_ready <= cr_out_enable;
285  default: bits_ready <= y_out_enable;
286  endcase
287 end
288 
289 always @(posedge clk)
290 begin
291  case (bits_mux)
292  3'b001: sorc_reg <= orc;
293  3'b010: sorc_reg <= orc_cb;
294  3'b100: sorc_reg <= orc_cr;
295  default: sorc_reg <= orc;
296  endcase
297 end
298 
299 always @(posedge clk)
300 begin
301  case (old_orc_mux)
302  3'b001: roll_orc_reg <= orc;
303  3'b010: roll_orc_reg <= orc_cb;
304  3'b100: roll_orc_reg <= orc_cr;
305  default: roll_orc_reg <= orc;
306  endcase
307 end
308 
309 always @(posedge clk)
310 begin
311  case (bits_mux)
312  3'b001: orc_reg <= orc;
313  3'b010: orc_reg <= orc_cb;
314  3'b100: orc_reg <= orc_cr;
315  default: orc_reg <= orc;
316  endcase
317 end
318 
319 always @(posedge clk)
320 begin
321  case (old_orc_mux)
322  3'b001: old_orc_reg <= orc_cr;
323  3'b010: old_orc_reg <= orc;
324  3'b100: old_orc_reg <= orc_cb;
325  default: old_orc_reg <= orc_cr;
326  endcase
327 end
328 
329 always @(posedge clk)
330 begin
331  if (rst)
332  bits_mux <= 3'b001; // Y
333  else if (enable_3)
334  bits_mux <= 3'b010; // Cb
335  else if (enable_19)
336  bits_mux <= 3'b100; // Cr
337  else if (enable_35)
338  bits_mux <= 3'b001; // Y
339 end
340 
341 always @(posedge clk)
342 begin
343  if (rst)
344  old_orc_mux <= 3'b001; // Y
345  else if (enable_1)
346  old_orc_mux <= 3'b010; // Cb
347  else if (enable_6)
348  old_orc_mux <= 3'b100; // Cr
349  else if (enable_22)
350  old_orc_mux <= 3'b001; // Y
351 end
352 
353 always @(posedge clk)
354 begin
355  if (rst)
356  read_mux <= 3'b001; // Y
357  else if (enable_1)
358  read_mux <= 3'b010; // Cb
359  else if (enable_17)
360  read_mux <= 3'b100; // Cr
361  else if (enable_33)
362  read_mux <= 3'b001; // Y
363 end
364 
365 always @(posedge clk)
366 begin
367  if (rst) begin
368  cr_orc_1 <= 0; cb_orc_1 <= 0; y_orc_1 <= 0;
369  end
370  else if (end_of_block_output) begin
371  cr_orc_1 <= cr_orc;
372  cb_orc_1 <= cb_orc;
373  y_orc_1 <= y_orc;
374  end
375 end
376 
377 
378 always @(posedge clk)
379 begin
380  if (rst) begin
381  jpeg_ro_5 <= 0; edge_ro_5 <= 0;
382  end
383  else if (br_5) begin
384  jpeg_ro_5 <= (edge_ro_4 <= 1) ? jpeg_ro_4 << 1 : jpeg_ro_4;
385  edge_ro_5 <= (edge_ro_4 <= 1) ? edge_ro_4 : edge_ro_4 - 1;
386  end
387 end
388 
389 always @(posedge clk)
390 begin
391  if (rst) begin
392  jpeg_5 <= 0; orc_5 <= 0; jpeg_ro_4 <= 0; edge_ro_4 <= 0;
393  end
394  else if (br_4) begin
395  jpeg_5 <= (orc_4 >= 1) ? jpeg_4 >> 1 : jpeg_4;
396  orc_5 <= (orc_4 >= 1) ? orc_4 - 1 : orc_4;
397  jpeg_ro_4 <= (edge_ro_3 <= 2) ? jpeg_ro_3 << 2 : jpeg_ro_3;
398  edge_ro_4 <= (edge_ro_3 <= 2) ? edge_ro_3 : edge_ro_3 - 2;
399  end
400 end
401 
402 always @(posedge clk)
403 begin
404  if (rst) begin
405  jpeg_4 <= 0; orc_4 <= 0; jpeg_ro_3 <= 0; edge_ro_3 <= 0;
406  end
407  else if (br_3) begin
408  jpeg_4 <= (orc_3 >= 2) ? jpeg_3 >> 2 : jpeg_3;
409  orc_4 <= (orc_3 >= 2) ? orc_3 - 2 : orc_3;
410  jpeg_ro_3 <= (edge_ro_2 <= 4) ? jpeg_ro_2 << 4 : jpeg_ro_2;
411  edge_ro_3 <= (edge_ro_2 <= 4) ? edge_ro_2 : edge_ro_2 - 4;
412  end
413 end
414 
415 always @(posedge clk)
416 begin
417  if (rst) begin
418  jpeg_3 <= 0; orc_3 <= 0; jpeg_ro_2 <= 0; edge_ro_2 <= 0;
419  end
420  else if (br_2) begin
421  jpeg_3 <= (orc_2 >= 4) ? jpeg_2 >> 4 : jpeg_2;
422  orc_3 <= (orc_2 >= 4) ? orc_2 - 4 : orc_2;
423  jpeg_ro_2 <= (edge_ro_1 <= 8) ? jpeg_ro_1 << 8 : jpeg_ro_1;
424  edge_ro_2 <= (edge_ro_1 <= 8) ? edge_ro_1 : edge_ro_1 - 8;
425  end
426 end
427 
428 always @(posedge clk)
429 begin
430  if (rst) begin
431  jpeg_2 <= 0; orc_2 <= 0; jpeg_ro_1 <= 0; edge_ro_1 <= 0;
432  end
433  else if (br_1) begin
434  jpeg_2 <= (orc_1 >= 8) ? jpeg_1 >> 8 : jpeg_1;
435  orc_2 <= (orc_1 >= 8) ? orc_1 - 8 : orc_1;
436  jpeg_ro_1 <= (orc_reg_delay <= 16) ? jpeg_delay << 16 : jpeg_delay;
438  end
439 end
440 
441 always @(posedge clk)
442 begin
443  if (rst) begin
444  jpeg_1 <= 0; orc_1 <= 0; jpeg_delay <= 0; orc_reg_delay <= 0;
445  end
446  else if (bits_ready) begin
447  jpeg_1 <= (orc_reg >= 16) ? jpeg >> 16 : jpeg;
448  orc_1 <= (orc_reg >= 16) ? orc_reg - 16 : orc_reg;
449  jpeg_delay <= jpeg;
451  end
452 end
453 
454 always @(posedge clk)
455 begin
456  if (rst) begin
457  enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; enable_4 <= 0; enable_5 <= 0;
458  enable_6 <= 0; enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; enable_10 <= 0;
459  enable_11 <= 0; enable_12 <= 0; enable_13 <= 0; enable_14 <= 0; enable_15 <= 0;
460  enable_16 <= 0; enable_17 <= 0; enable_18 <= 0; enable_19 <= 0; enable_20 <= 0;
461  enable_21 <= 0; enable_22 <= 0; enable_23 <= 0; enable_24 <= 0; enable_25 <= 0;
462  enable_26 <= 0; enable_27 <= 0; enable_28 <= 0; enable_29 <= 0; enable_30 <= 0;
463  enable_31 <= 0; enable_32 <= 0; enable_33 <= 0; enable_34 <= 0; enable_35 <= 0;
464  end
465  else begin
473  enable_21 <= enable_20;
477  enable_31 <= enable_30;
479  enable_35 <= enable_34;
480  end
481 end
482 
483 always @(posedge clk)
484 begin
485  if (rst)
486  JPEG_bitstream[31] <= 0;
487  else if (br_7 & rollover_6)
488  JPEG_bitstream[31] <= jpeg_6[31];
489  else if (br_6 && static_orc_6 == 0)
490  JPEG_bitstream[31] <= jpeg_6[31];
491 end
492 
493 always @(posedge clk)
494 begin
495  if (rst)
496  JPEG_bitstream[30] <= 0;
497  else if (br_7 & rollover_6)
498  JPEG_bitstream[30] <= jpeg_6[30];
499  else if (br_6 && static_orc_6 <= 1)
500  JPEG_bitstream[30] <= jpeg_6[30];
501 end
502 
503 always @(posedge clk)
504 begin
505  if (rst)
506  JPEG_bitstream[29] <= 0;
507  else if (br_7 & rollover_6)
508  JPEG_bitstream[29] <= jpeg_6[29];
509  else if (br_6 && static_orc_6 <= 2)
510  JPEG_bitstream[29] <= jpeg_6[29];
511 end
512 
513 always @(posedge clk)
514 begin
515  if (rst)
516  JPEG_bitstream[28] <= 0;
517  else if (br_7 & rollover_6)
518  JPEG_bitstream[28] <= jpeg_6[28];
519  else if (br_6 && static_orc_6 <= 3)
520  JPEG_bitstream[28] <= jpeg_6[28];
521 end
522 
523 always @(posedge clk)
524 begin
525  if (rst)
526  JPEG_bitstream[27] <= 0;
527  else if (br_7 & rollover_6)
528  JPEG_bitstream[27] <= jpeg_6[27];
529  else if (br_6 && static_orc_6 <= 4)
530  JPEG_bitstream[27] <= jpeg_6[27];
531 end
532 
533 always @(posedge clk)
534 begin
535  if (rst)
536  JPEG_bitstream[26] <= 0;
537  else if (br_7 & rollover_6)
538  JPEG_bitstream[26] <= jpeg_6[26];
539  else if (br_6 && static_orc_6 <= 5)
540  JPEG_bitstream[26] <= jpeg_6[26];
541 end
542 
543 always @(posedge clk)
544 begin
545  if (rst)
546  JPEG_bitstream[25] <= 0;
547  else if (br_7 & rollover_6)
548  JPEG_bitstream[25] <= jpeg_6[25];
549  else if (br_6 && static_orc_6 <= 6)
550  JPEG_bitstream[25] <= jpeg_6[25];
551 end
552 
553 always @(posedge clk)
554 begin
555  if (rst)
556  JPEG_bitstream[24] <= 0;
557  else if (br_7 & rollover_6)
558  JPEG_bitstream[24] <= jpeg_6[24];
559  else if (br_6 && static_orc_6 <= 7)
560  JPEG_bitstream[24] <= jpeg_6[24];
561 end
562 
563 always @(posedge clk)
564 begin
565  if (rst)
566  JPEG_bitstream[23] <= 0;
567  else if (br_7 & rollover_6)
568  JPEG_bitstream[23] <= jpeg_6[23];
569  else if (br_6 && static_orc_6 <= 8)
570  JPEG_bitstream[23] <= jpeg_6[23];
571 end
572 
573 always @(posedge clk)
574 begin
575  if (rst)
576  JPEG_bitstream[22] <= 0;
577  else if (br_7 & rollover_6)
578  JPEG_bitstream[22] <= jpeg_6[22];
579  else if (br_6 && static_orc_6 <= 9)
580  JPEG_bitstream[22] <= jpeg_6[22];
581 end
582 
583 always @(posedge clk)
584 begin
585  if (rst)
586  JPEG_bitstream[21] <= 0;
587  else if (br_7 & rollover_6)
588  JPEG_bitstream[21] <= jpeg_6[21];
589  else if (br_6 && static_orc_6 <= 10)
590  JPEG_bitstream[21] <= jpeg_6[21];
591 end
592 
593 always @(posedge clk)
594 begin
595  if (rst)
596  JPEG_bitstream[20] <= 0;
597  else if (br_7 & rollover_6)
598  JPEG_bitstream[20] <= jpeg_6[20];
599  else if (br_6 && static_orc_6 <= 11)
600  JPEG_bitstream[20] <= jpeg_6[20];
601 end
602 
603 always @(posedge clk)
604 begin
605  if (rst)
606  JPEG_bitstream[19] <= 0;
607  else if (br_7 & rollover_6)
608  JPEG_bitstream[19] <= jpeg_6[19];
609  else if (br_6 && static_orc_6 <= 12)
610  JPEG_bitstream[19] <= jpeg_6[19];
611 end
612 
613 always @(posedge clk)
614 begin
615  if (rst)
616  JPEG_bitstream[18] <= 0;
617  else if (br_7 & rollover_6)
618  JPEG_bitstream[18] <= jpeg_6[18];
619  else if (br_6 && static_orc_6 <= 13)
620  JPEG_bitstream[18] <= jpeg_6[18];
621 end
622 
623 always @(posedge clk)
624 begin
625  if (rst)
626  JPEG_bitstream[17] <= 0;
627  else if (br_7 & rollover_6)
628  JPEG_bitstream[17] <= jpeg_6[17];
629  else if (br_6 && static_orc_6 <= 14)
630  JPEG_bitstream[17] <= jpeg_6[17];
631 end
632 
633 always @(posedge clk)
634 begin
635  if (rst)
636  JPEG_bitstream[16] <= 0;
637  else if (br_7 & rollover_6)
638  JPEG_bitstream[16] <= jpeg_6[16];
639  else if (br_6 && static_orc_6 <= 15)
640  JPEG_bitstream[16] <= jpeg_6[16];
641 end
642 
643 always @(posedge clk)
644 begin
645  if (rst)
646  JPEG_bitstream[15] <= 0;
647  else if (br_7 & rollover_6)
648  JPEG_bitstream[15] <= jpeg_6[15];
649  else if (br_6 && static_orc_6 <= 16)
650  JPEG_bitstream[15] <= jpeg_6[15];
651 end
652 
653 always @(posedge clk)
654 begin
655  if (rst)
656  JPEG_bitstream[14] <= 0;
657  else if (br_7 & rollover_6)
658  JPEG_bitstream[14] <= jpeg_6[14];
659  else if (br_6 && static_orc_6 <= 17)
660  JPEG_bitstream[14] <= jpeg_6[14];
661 end
662 
663 always @(posedge clk)
664 begin
665  if (rst)
666  JPEG_bitstream[13] <= 0;
667  else if (br_7 & rollover_6)
668  JPEG_bitstream[13] <= jpeg_6[13];
669  else if (br_6 && static_orc_6 <= 18)
670  JPEG_bitstream[13] <= jpeg_6[13];
671 end
672 
673 always @(posedge clk)
674 begin
675  if (rst)
676  JPEG_bitstream[12] <= 0;
677  else if (br_7 & rollover_6)
678  JPEG_bitstream[12] <= jpeg_6[12];
679  else if (br_6 && static_orc_6 <= 19)
680  JPEG_bitstream[12] <= jpeg_6[12];
681 end
682 
683 always @(posedge clk)
684 begin
685  if (rst)
686  JPEG_bitstream[11] <= 0;
687  else if (br_7 & rollover_6)
688  JPEG_bitstream[11] <= jpeg_6[11];
689  else if (br_6 && static_orc_6 <= 20)
690  JPEG_bitstream[11] <= jpeg_6[11];
691 end
692 
693 always @(posedge clk)
694 begin
695  if (rst)
696  JPEG_bitstream[10] <= 0;
697  else if (br_7 & rollover_6)
698  JPEG_bitstream[10] <= jpeg_6[10];
699  else if (br_6 && static_orc_6 <= 21)
700  JPEG_bitstream[10] <= jpeg_6[10];
701 end
702 
703 always @(posedge clk)
704 begin
705  if (rst)
706  JPEG_bitstream[9] <= 0;
707  else if (br_7 & rollover_6)
708  JPEG_bitstream[9] <= jpeg_6[9];
709  else if (br_6 && static_orc_6 <= 22)
710  JPEG_bitstream[9] <= jpeg_6[9];
711 end
712 
713 always @(posedge clk)
714 begin
715  if (rst)
716  JPEG_bitstream[8] <= 0;
717  else if (br_7 & rollover_6)
718  JPEG_bitstream[8] <= jpeg_6[8];
719  else if (br_6 && static_orc_6 <= 23)
720  JPEG_bitstream[8] <= jpeg_6[8];
721 end
722 
723 always @(posedge clk)
724 begin
725  if (rst)
726  JPEG_bitstream[7] <= 0;
727  else if (br_7 & rollover_6)
728  JPEG_bitstream[7] <= jpeg_6[7];
729  else if (br_6 && static_orc_6 <= 24)
730  JPEG_bitstream[7] <= jpeg_6[7];
731 end
732 
733 always @(posedge clk)
734 begin
735  if (rst)
736  JPEG_bitstream[6] <= 0;
737  else if (br_7 & rollover_6)
738  JPEG_bitstream[6] <= jpeg_6[6];
739  else if (br_6 && static_orc_6 <= 25)
740  JPEG_bitstream[6] <= jpeg_6[6];
741 end
742 
743 always @(posedge clk)
744 begin
745  if (rst)
746  JPEG_bitstream[5] <= 0;
747  else if (br_7 & rollover_6)
748  JPEG_bitstream[5] <= jpeg_6[5];
749  else if (br_6 && static_orc_6 <= 26)
750  JPEG_bitstream[5] <= jpeg_6[5];
751 end
752 
753 always @(posedge clk)
754 begin
755  if (rst)
756  JPEG_bitstream[4] <= 0;
757  else if (br_7 & rollover_6)
758  JPEG_bitstream[4] <= jpeg_6[4];
759  else if (br_6 && static_orc_6 <= 27)
760  JPEG_bitstream[4] <= jpeg_6[4];
761 end
762 
763 always @(posedge clk)
764 begin
765  if (rst)
766  JPEG_bitstream[3] <= 0;
767  else if (br_7 & rollover_6)
768  JPEG_bitstream[3] <= jpeg_6[3];
769  else if (br_6 && static_orc_6 <= 28)
770  JPEG_bitstream[3] <= jpeg_6[3];
771 end
772 
773 always @(posedge clk)
774 begin
775  if (rst)
776  JPEG_bitstream[2] <= 0;
777  else if (br_7 & rollover_6)
778  JPEG_bitstream[2] <= jpeg_6[2];
779  else if (br_6 && static_orc_6 <= 29)
780  JPEG_bitstream[2] <= jpeg_6[2];
781 end
782 
783 always @(posedge clk)
784 begin
785  if (rst)
786  JPEG_bitstream[1] <= 0;
787  else if (br_7 & rollover_6)
788  JPEG_bitstream[1] <= jpeg_6[1];
789  else if (br_6 && static_orc_6 <= 30)
790  JPEG_bitstream[1] <= jpeg_6[1];
791 end
792 
793 always @(posedge clk)
794 begin
795  if (rst)
796  JPEG_bitstream[0] <= 0;
797  else if (br_7 & rollover_6)
798  JPEG_bitstream[0] <= jpeg_6[0];
799  else if (br_6 && static_orc_6 <= 31)
800  JPEG_bitstream[0] <= jpeg_6[0];
801 end
802 
803 always @(posedge clk)
804 begin
805  if (rst) begin
806  jpeg_6 <= 0;
807  end
808  else if (br_5 | br_6) begin
809  jpeg_6[31] <= (rollover_5 & static_orc_5 > 0) ? jpeg_ro_5[31] : jpeg_5[31];
810  jpeg_6[30] <= (rollover_5 & static_orc_5 > 1) ? jpeg_ro_5[30] : jpeg_5[30];
811  jpeg_6[29] <= (rollover_5 & static_orc_5 > 2) ? jpeg_ro_5[29] : jpeg_5[29];
812  jpeg_6[28] <= (rollover_5 & static_orc_5 > 3) ? jpeg_ro_5[28] : jpeg_5[28];
813  jpeg_6[27] <= (rollover_5 & static_orc_5 > 4) ? jpeg_ro_5[27] : jpeg_5[27];
814  jpeg_6[26] <= (rollover_5 & static_orc_5 > 5) ? jpeg_ro_5[26] : jpeg_5[26];
815  jpeg_6[25] <= (rollover_5 & static_orc_5 > 6) ? jpeg_ro_5[25] : jpeg_5[25];
816  jpeg_6[24] <= (rollover_5 & static_orc_5 > 7) ? jpeg_ro_5[24] : jpeg_5[24];
817  jpeg_6[23] <= (rollover_5 & static_orc_5 > 8) ? jpeg_ro_5[23] : jpeg_5[23];
818  jpeg_6[22] <= (rollover_5 & static_orc_5 > 9) ? jpeg_ro_5[22] : jpeg_5[22];
819  jpeg_6[21] <= (rollover_5 & static_orc_5 > 10) ? jpeg_ro_5[21] : jpeg_5[21];
820  jpeg_6[20] <= (rollover_5 & static_orc_5 > 11) ? jpeg_ro_5[20] : jpeg_5[20];
821  jpeg_6[19] <= (rollover_5 & static_orc_5 > 12) ? jpeg_ro_5[19] : jpeg_5[19];
822  jpeg_6[18] <= (rollover_5 & static_orc_5 > 13) ? jpeg_ro_5[18] : jpeg_5[18];
823  jpeg_6[17] <= (rollover_5 & static_orc_5 > 14) ? jpeg_ro_5[17] : jpeg_5[17];
824  jpeg_6[16] <= (rollover_5 & static_orc_5 > 15) ? jpeg_ro_5[16] : jpeg_5[16];
825  jpeg_6[15] <= (rollover_5 & static_orc_5 > 16) ? jpeg_ro_5[15] : jpeg_5[15];
826  jpeg_6[14] <= (rollover_5 & static_orc_5 > 17) ? jpeg_ro_5[14] : jpeg_5[14];
827  jpeg_6[13] <= (rollover_5 & static_orc_5 > 18) ? jpeg_ro_5[13] : jpeg_5[13];
828  jpeg_6[12] <= (rollover_5 & static_orc_5 > 19) ? jpeg_ro_5[12] : jpeg_5[12];
829  jpeg_6[11] <= (rollover_5 & static_orc_5 > 20) ? jpeg_ro_5[11] : jpeg_5[11];
830  jpeg_6[10] <= (rollover_5 & static_orc_5 > 21) ? jpeg_ro_5[10] : jpeg_5[10];
831  jpeg_6[9] <= (rollover_5 & static_orc_5 > 22) ? jpeg_ro_5[9] : jpeg_5[9];
832  jpeg_6[8] <= (rollover_5 & static_orc_5 > 23) ? jpeg_ro_5[8] : jpeg_5[8];
833  jpeg_6[7] <= (rollover_5 & static_orc_5 > 24) ? jpeg_ro_5[7] : jpeg_5[7];
834  jpeg_6[6] <= (rollover_5 & static_orc_5 > 25) ? jpeg_ro_5[6] : jpeg_5[6];
835  jpeg_6[5] <= (rollover_5 & static_orc_5 > 26) ? jpeg_ro_5[5] : jpeg_5[5];
836  jpeg_6[4] <= (rollover_5 & static_orc_5 > 27) ? jpeg_ro_5[4] : jpeg_5[4];
837  jpeg_6[3] <= (rollover_5 & static_orc_5 > 28) ? jpeg_ro_5[3] : jpeg_5[3];
838  jpeg_6[2] <= (rollover_5 & static_orc_5 > 29) ? jpeg_ro_5[2] : jpeg_5[2];
839  jpeg_6[1] <= (rollover_5 & static_orc_5 > 30) ? jpeg_ro_5[1] : jpeg_5[1];
840  jpeg_6[0] <= jpeg_5[0];
841  end
842 end
843 
844  endmodule
3295enable_11reg
Definition: fifo_out.v:71
3286enable_2reg
Definition: fifo_out.v:69
3268jpeg_1reg[31:0]
Definition: fifo_out.v:65
3235cr_eob_emptywire
Definition: fifo_out.v:57
3351cb_bits_out2wire[31:0]
Definition: fifo_out.v:82
3334rollover_2reg
Definition: fifo_out.v:78
3319enable_35reg
Definition: fifo_out.v:75
3227y_bits_outwire[31:0]
Definition: fifo_out.v:53
3277y_orc_1reg[4:0]
Definition: fifo_out.v:66
3322read_muxreg[2:0]
Definition: fifo_out.v:76
3366cr_JPEG_bitstream2wire[31:0]
Definition: fifo_out.v:91
3362y_write_enablewire
Definition: fifo_out.v:87
3311enable_27reg
Definition: fifo_out.v:74
3232end_of_block_outputwire
Definition: fifo_out.v:56
3221cb_JPEG_bitstreamwire[31:0]
Definition: fifo_out.v:51
3280y_out_enable_1reg
Definition: fifo_out.v:67
3266jpeg_delayreg[31:0]
Definition: fifo_out.v:64
3341data_readyreg
Definition: fifo_out.v:80
3271jpeg_4reg[31:0]
Definition: fifo_out.v:65
3325br_2reg
Definition: fifo_out.v:77
3242sorc_regreg[4:0]
Definition: fifo_out.v:59
3243roll_orc_regreg[4:0]
Definition: fifo_out.v:59
[23:0] 3217data_in
Definition: fifo_out.v:44
3340rollover_7reg
Definition: fifo_out.v:79
3250static_orc_1reg[4:0]
Definition: fifo_out.v:61
3316enable_32reg
Definition: fifo_out.v:75
3231y_data_readywire
Definition: fifo_out.v:55
3304enable_20reg
Definition: fifo_out.v:72
3237orcreg[4:0]
Definition: fifo_out.v:59
3369cr_bits_outwire[31:0]
Definition: fifo_out.v:94
3353cr_fifo_empty2wire
Definition: fifo_out.v:83
3272jpeg_5reg[31:0]
Definition: fifo_out.v:65
3363cr_read_req1wire
Definition: fifo_out.v:88
u17 sync_fifo_32
Definition: fifo_out.v:137
3249orc_reg_delayreg[4:0]
Definition: fifo_out.v:60
3380cb_out_enablewire
Definition: fifo_out.v:105
3418cr_eob_empty
Definition: pre_fifo.v:56
3234cb_eob_emptywire
Definition: fifo_out.v:57
3276cb_orc_1reg[4:0]
Definition: fifo_out.v:66
3333rollover_1reg
Definition: fifo_out.v:78
3229cb_data_readywire
Definition: fifo_out.v:55
u14 pre_fifo
Definition: fifo_out.v:108
3356cr_out_enable1wire
Definition: fifo_out.v:84
3265jpeg_ro_5reg[31:0]
Definition: fifo_out.v:64
3278cr_out_enable_1reg
Definition: fifo_out.v:67
3290enable_6reg
Definition: fifo_out.v:70
3223y_JPEG_bitstreamwire[31:0]
Definition: fifo_out.v:51
3244orc_1reg[4:0]
Definition: fifo_out.v:60
3246orc_3reg[4:0]
Definition: fifo_out.v:60
3417cb_eob_empty
Definition: pre_fifo.v:56
3310enable_26reg
Definition: fifo_out.v:74
3330br_7reg
Definition: fifo_out.v:77
3309enable_25reg
Definition: fifo_out.v:73
3312enable_28reg
Definition: fifo_out.v:74
3245orc_2reg[4:0]
Definition: fifo_out.v:60
3291enable_7reg
Definition: fifo_out.v:70
[4:0] 3414y_orc
Definition: pre_fifo.v:54
3247orc_4reg[4:0]
Definition: fifo_out.v:60
3224cr_orcwire[4:0]
Definition: fifo_out.v:52
3230cr_data_readywire
Definition: fifo_out.v:55
3254static_orc_5reg[4:0]
Definition: fifo_out.v:61
3345y_read_reqreg
Definition: fifo_out.v:80
3415y_eob_output
Definition: pre_fifo.v:55
[31:0] 3458write_data
Definition: sync_fifo_32.v:41
3355cb_fifo_empty2wire
Definition: fifo_out.v:83
3288enable_4reg
Definition: fifo_out.v:69
3329br_6reg
Definition: fifo_out.v:77
3349cr_bits_out2wire[31:0]
Definition: fifo_out.v:82
3466read_datareg[31:0]
Definition: sync_fifo_32.v:50
3308enable_24reg
Definition: fifo_out.v:73
[31:0] 3409cb_JPEG_bitstream
Definition: pre_fifo.v:49
3348cr_bits_out1wire[31:0]
Definition: fifo_out.v:82
3240orc_crreg[4:0]
Definition: fifo_out.v:59
3368cr_write_enable2wire
Definition: fifo_out.v:93
3257edge_ro_2reg[4:0]
Definition: fifo_out.v:63
3372cb_read_req1wire
Definition: fifo_out.v:97
3306enable_22reg
Definition: fifo_out.v:73
3359cb_out_enable2wire
Definition: fifo_out.v:84
3374cb_JPEG_bitstream1wire[31:0]
Definition: fifo_out.v:99
3379cb_fifo_emptywire
Definition: fifo_out.v:104
3324br_1reg
Definition: fifo_out.v:77
3370cr_fifo_emptywire
Definition: fifo_out.v:95
3284eob_4reg
Definition: fifo_out.v:68
3282eob_2reg
Definition: fifo_out.v:68
3253static_orc_4reg[4:0]
Definition: fifo_out.v:61
3335rollover_3reg
Definition: fifo_out.v:78
3279cb_out_enable_1reg
Definition: fifo_out.v:67
3269jpeg_2reg[31:0]
Definition: fifo_out.v:65
3326br_3reg
Definition: fifo_out.v:77
3292enable_8reg
Definition: fifo_out.v:70
3339rollover_6reg
Definition: fifo_out.v:79
3352cr_fifo_empty1wire
Definition: fifo_out.v:83
3275cr_orc_1reg[4:0]
Definition: fifo_out.v:66
3301enable_17reg
Definition: fifo_out.v:72
3255static_orc_6reg[4:0]
Definition: fifo_out.v:62
3259edge_ro_4reg[4:0]
Definition: fifo_out.v:63
3216enable
Definition: fifo_out.v:43
3273jpeg_6reg[31:0]
Definition: fifo_out.v:65
3323bits_readyreg
Definition: fifo_out.v:77
3317enable_33reg
Definition: fifo_out.v:75
3321old_orc_muxreg[2:0]
Definition: fifo_out.v:76
3376cb_write_enable1wire
Definition: fifo_out.v:101
3338rollover_5reg
Definition: fifo_out.v:79
3365cr_JPEG_bitstream1wire[31:0]
Definition: fifo_out.v:90
3285enable_1reg
Definition: fifo_out.v:69
3264jpeg_ro_4reg[31:0]
Definition: fifo_out.v:64
3222cr_JPEG_bitstreamwire[31:0]
Definition: fifo_out.v:51
3289enable_5reg
Definition: fifo_out.v:69
3241old_orc_regreg[4:0]
Definition: fifo_out.v:59
3410cb_data_ready
Definition: pre_fifo.v:50
3371cr_out_enablewire
Definition: fifo_out.v:96
3404enable
Definition: pre_fifo.v:44
3350cb_bits_out1wire[31:0]
Definition: fifo_out.v:82
3346eob_early_out_enablereg
Definition: fifo_out.v:81
3373cb_read_req2wire
Definition: fifo_out.v:98
3236y_fifo_emptywire
Definition: fifo_out.v:58
3313enable_29reg
Definition: fifo_out.v:74
3347fifo_muxreg
Definition: fifo_out.v:81
3357cr_out_enable2wire
Definition: fifo_out.v:84
3287enable_3reg
Definition: fifo_out.v:69
3343cb_read_reqreg
Definition: fifo_out.v:80
3263jpeg_ro_3reg[31:0]
Definition: fifo_out.v:64
3293enable_9reg
Definition: fifo_out.v:70
3337rollover_4reg
Definition: fifo_out.v:79
3416y_eob_empty
Definition: pre_fifo.v:56
3260edge_ro_5reg[4:0]
Definition: fifo_out.v:63
3299enable_15reg
Definition: fifo_out.v:71
3252static_orc_3reg[4:0]
Definition: fifo_out.v:61
3342eobe_1reg
Definition: fifo_out.v:80
3327br_4reg
Definition: fifo_out.v:77
3251static_orc_2reg[4:0]
Definition: fifo_out.v:61
3262jpeg_ro_2reg[31:0]
Definition: fifo_out.v:64
3320bits_muxreg[2:0]
Definition: fifo_out.v:76
3296enable_12reg
Definition: fifo_out.v:71
3300enable_16reg
Definition: fifo_out.v:72
3274JPEG_bitstreamreg[31:0]
Definition: fifo_out.v:65
3281eob_1reg
Definition: fifo_out.v:67
3239orc_cbreg[4:0]
Definition: fifo_out.v:59
3364cr_read_req2wire
Definition: fifo_out.v:89
3336rollover_eobreg
Definition: fifo_out.v:78
3228y_out_enablewire
Definition: fifo_out.v:54
3298enable_14reg
Definition: fifo_out.v:71
3328br_5reg
Definition: fifo_out.v:77
3354cb_fifo_empty1wire
Definition: fifo_out.v:83
3302enable_18reg
Definition: fifo_out.v:72
3294enable_10reg
Definition: fifo_out.v:70
3344cr_read_reqreg
Definition: fifo_out.v:80
3361cr_write_enablewire
Definition: fifo_out.v:86
3307enable_23reg
Definition: fifo_out.v:73
3467rdata_validreg
Definition: sync_fifo_32.v:51
3375cb_JPEG_bitstream2wire[31:0]
Definition: fifo_out.v:100
3233y_eob_emptywire
Definition: fifo_out.v:56
3332rolloverreg
Definition: fifo_out.v:78
3261jpeg_ro_1reg[31:0]
Definition: fifo_out.v:64
[23:0] 3405data_in
Definition: pre_fifo.v:45
3358cb_out_enable1wire
Definition: fifo_out.v:84
3270jpeg_3reg[31:0]
Definition: fifo_out.v:65
[31:0] 3412y_JPEG_bitstream
Definition: pre_fifo.v:52
3315enable_31reg
Definition: fifo_out.v:75
3378cb_bits_outwire[31:0]
Definition: fifo_out.v:103
3413y_data_ready
Definition: pre_fifo.v:53
3305enable_21reg
Definition: fifo_out.v:73
3238orc_regreg[4:0]
Definition: fifo_out.v:59
[31:0] 3406cr_JPEG_bitstream
Definition: pre_fifo.v:46
3258edge_ro_3reg[4:0]
Definition: fifo_out.v:63
[4:0] 3411cb_orc
Definition: pre_fifo.v:51
3283eob_3reg
Definition: fifo_out.v:68
3377cb_write_enable2wire
Definition: fifo_out.v:102
3267jpegreg[31:0]
Definition: fifo_out.v:65
3318enable_34reg
Definition: fifo_out.v:75
3225cb_orcwire[4:0]
Definition: fifo_out.v:52
[4:0] 3408cr_orc
Definition: pre_fifo.v:48
3297enable_13reg
Definition: fifo_out.v:71
3331br_8reg
Definition: fifo_out.v:77
3367cr_write_enable1wire
Definition: fifo_out.v:92
3407cr_data_ready
Definition: pre_fifo.v:47
3303enable_19reg
Definition: fifo_out.v:72
3226y_orcwire[4:0]
Definition: fifo_out.v:52
3360cb_write_enablewire
Definition: fifo_out.v:85
3248orc_5reg[4:0]
Definition: fifo_out.v:60
3314enable_30reg
Definition: fifo_out.v:74
3256edge_ro_1reg[4:0]
Definition: fifo_out.v:63