cr_dct.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Core - Verilog ////
//// ////
//// Author: David Lundgren ////
//// davidklun@gmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// davidklun@gmail.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/* This module converts the incoming Cr data.
The incoming data is unsigned 8 bits, so the data is in the range of 0-255
Unlike a typical DCT, the data is not subtracted by 128 to center it around 0.
It is only required for the first row, and instead of subtracting 128 from each
pixel value, a total value can be subtracted at the end of the first row/column multiply,
involving the 8 pixel values and the 8 DCT matrix values.
For the other 7 rows of the DCT matrix, the values in each row add up to 0,
so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value.
Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values
by the 8x8 DCT matrix. **/
`timescale 1ns / 100ps
module cr_dct(clk, rst, enable, data_in,
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final,
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final,
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final,
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final,
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final,
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final,
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final,
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final,
output_enable);
input clk;
input rst;
input enable;
input [7:0] data_in;
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
output output_enable;
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52;
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52;
reg [24:0] Cb_temp_11;
reg [24:0] Cb11, Cb21, Cb31, Cb41, Cb51, Cb61, Cb71, Cb81, Cb11_final;
reg [31:0] Cb_temp_21, Cb_temp_31, Cb_temp_41, Cb_temp_51;
reg [31:0] Cb_temp_61, Cb_temp_71, Cb_temp_81;
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14;
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18;
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24;
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28;
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34;
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38;
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44;
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48;
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54;
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58;
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64;
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68;
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74;
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78;
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84;
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88;
reg [24:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18;
reg [24:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28;
reg [24:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
reg [24:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48;
reg [24:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58;
reg [24:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
reg [24:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78;
reg [24:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88;
reg [31:0] Cb11_final_2, Cb21_final_2, Cb11_final_3, Cb11_final_4, Cb31_final_2, Cb41_final_2;
reg [31:0] Cb51_final_2, Cb61_final_2, Cb71_final_2, Cb81_final_2;
reg [10:0] Cb11_final_1, Cb21_final_1, Cb31_final_1, Cb41_final_1;
reg [10:0] Cb51_final_1, Cb61_final_1, Cb71_final_1, Cb81_final_1;
reg [24:0] Cb21_final, Cb31_final, Cb41_final, Cb51_final;
reg [24:0] Cb61_final, Cb71_final, Cb81_final;
reg [24:0] Cb21_final_prev, Cb21_final_diff;
reg [24:0] Cb31_final_prev, Cb31_final_diff;
reg [24:0] Cb41_final_prev, Cb41_final_diff;
reg [24:0] Cb51_final_prev, Cb51_final_diff;
reg [24:0] Cb61_final_prev, Cb61_final_diff;
reg [24:0] Cb71_final_prev, Cb71_final_diff;
reg [24:0] Cb81_final_prev, Cb81_final_diff;
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
reg [2:0] count;
reg [2:0] count_of, count_of_copy;
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable;
reg count_9, count_10;
reg [7:0] data_1;
integer Cb2_mul_input, Cb3_mul_input, Cb4_mul_input, Cb5_mul_input;
integer Cb6_mul_input, Cb7_mul_input, Cb8_mul_input;
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input;
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input;
always @(posedge clk)
begin // DCT matrix entries
T1 = 5793; // .3536
T21 = 8035; // .4904
T22 = 6811; // .4157
T23 = 4551; // .2778
T24 = 1598; // .0975
T25 = -1598; // -.0975
T26 = -4551; // -.2778
T27 = -6811; // -.4157
T28 = -8035; // -.4904
T31 = 7568; // .4619
T32 = 3135; // .1913
T33 = -3135; // -.1913
T34 = -7568; // -.4619
T52 = -5793; // -.3536
end
always @(posedge clk)
begin // The inverse DCT matrix entries
Ti1 = 5793; // .3536
Ti21 = 8035; // .4904
Ti22 = 6811; // .4157
Ti23 = 4551; // .2778
Ti24 = 1598; // .0975
Ti25 = -1598; // -.0975
Ti26 = -4551; // -.2778
Ti27 = -6811; // -.4157
Ti28 = -8035; // -.4904
Ti31 = 7568; // .4619
Ti32 = 3135; // .1913
Ti33 = -3135; // -.1913
Ti34 = -7568; // -.4619
Ti52 = -5793; // -.3536
end
always @(posedge clk)
begin
if (rst) begin
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0;
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0;
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0;
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0;
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0;
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0;
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0;
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0;
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0;
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0;
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0;
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0;
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0;
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0;
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0;
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0;
end
else if (enable_1 & count_8) begin
Z_temp_11 <= Cb11_final_4 * Ti1; Z_temp_12 <= Cb11_final_4 * Ti2_mul_input;
Z_temp_13 <= Cb11_final_4 * Ti3_mul_input; Z_temp_14 <= Cb11_final_4 * Ti4_mul_input;
Z_temp_15 <= Cb11_final_4 * Ti5_mul_input; Z_temp_16 <= Cb11_final_4 * Ti6_mul_input;
Z_temp_17 <= Cb11_final_4 * Ti7_mul_input; Z_temp_18 <= Cb11_final_4 * Ti8_mul_input;
Z_temp_21 <= Cb21_final_2 * Ti1; Z_temp_22 <= Cb21_final_2 * Ti2_mul_input;
Z_temp_23 <= Cb21_final_2 * Ti3_mul_input; Z_temp_24 <= Cb21_final_2 * Ti4_mul_input;
Z_temp_25 <= Cb21_final_2 * Ti5_mul_input; Z_temp_26 <= Cb21_final_2 * Ti6_mul_input;
Z_temp_27 <= Cb21_final_2 * Ti7_mul_input; Z_temp_28 <= Cb21_final_2 * Ti8_mul_input;
Z_temp_31 <= Cb31_final_2 * Ti1; Z_temp_32 <= Cb31_final_2 * Ti2_mul_input;
Z_temp_33 <= Cb31_final_2 * Ti3_mul_input; Z_temp_34 <= Cb31_final_2 * Ti4_mul_input;
Z_temp_35 <= Cb31_final_2 * Ti5_mul_input; Z_temp_36 <= Cb31_final_2 * Ti6_mul_input;
Z_temp_37 <= Cb31_final_2 * Ti7_mul_input; Z_temp_38 <= Cb31_final_2 * Ti8_mul_input;
Z_temp_41 <= Cb41_final_2 * Ti1; Z_temp_42 <= Cb41_final_2 * Ti2_mul_input;
Z_temp_43 <= Cb41_final_2 * Ti3_mul_input; Z_temp_44 <= Cb41_final_2 * Ti4_mul_input;
Z_temp_45 <= Cb41_final_2 * Ti5_mul_input; Z_temp_46 <= Cb41_final_2 * Ti6_mul_input;
Z_temp_47 <= Cb41_final_2 * Ti7_mul_input; Z_temp_48 <= Cb41_final_2 * Ti8_mul_input;
Z_temp_51 <= Cb51_final_2 * Ti1; Z_temp_52 <= Cb51_final_2 * Ti2_mul_input;
Z_temp_53 <= Cb51_final_2 * Ti3_mul_input; Z_temp_54 <= Cb51_final_2 * Ti4_mul_input;
Z_temp_55 <= Cb51_final_2 * Ti5_mul_input; Z_temp_56 <= Cb51_final_2 * Ti6_mul_input;
Z_temp_57 <= Cb51_final_2 * Ti7_mul_input; Z_temp_58 <= Cb51_final_2 * Ti8_mul_input;
Z_temp_61 <= Cb61_final_2 * Ti1; Z_temp_62 <= Cb61_final_2 * Ti2_mul_input;
Z_temp_63 <= Cb61_final_2 * Ti3_mul_input; Z_temp_64 <= Cb61_final_2 * Ti4_mul_input;
Z_temp_65 <= Cb61_final_2 * Ti5_mul_input; Z_temp_66 <= Cb61_final_2 * Ti6_mul_input;
Z_temp_67 <= Cb61_final_2 * Ti7_mul_input; Z_temp_68 <= Cb61_final_2 * Ti8_mul_input;
Z_temp_71 <= Cb71_final_2 * Ti1; Z_temp_72 <= Cb71_final_2 * Ti2_mul_input;
Z_temp_73 <= Cb71_final_2 * Ti3_mul_input; Z_temp_74 <= Cb71_final_2 * Ti4_mul_input;
Z_temp_75 <= Cb71_final_2 * Ti5_mul_input; Z_temp_76 <= Cb71_final_2 * Ti6_mul_input;
Z_temp_77 <= Cb71_final_2 * Ti7_mul_input; Z_temp_78 <= Cb71_final_2 * Ti8_mul_input;
Z_temp_81 <= Cb81_final_2 * Ti1; Z_temp_82 <= Cb81_final_2 * Ti2_mul_input;
Z_temp_83 <= Cb81_final_2 * Ti3_mul_input; Z_temp_84 <= Cb81_final_2 * Ti4_mul_input;
Z_temp_85 <= Cb81_final_2 * Ti5_mul_input; Z_temp_86 <= Cb81_final_2 * Ti6_mul_input;
Z_temp_87 <= Cb81_final_2 * Ti7_mul_input; Z_temp_88 <= Cb81_final_2 * Ti8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (count_8 & count_of == 1) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0;
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0;
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0;
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0;
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0;
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0;
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0;
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0;
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (enable & count_9) begin
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14;
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18;
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24;
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28;
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34;
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38;
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44;
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48;
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54;
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58;
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64;
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68;
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74;
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78;
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84;
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0;
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0;
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0;
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0;
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0;
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0;
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0;
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0;
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0;
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0;
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0;
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0;
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0;
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0;
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0;
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0;
end
else if (count_10 & count_of == 0) begin
Z11_final <= Z11[13] ? Z11[24:14] + 1 : Z11[24:14];
Z12_final <= Z12[13] ? Z12[24:14] + 1 : Z12[24:14];
Z13_final <= Z13[13] ? Z13[24:14] + 1 : Z13[24:14];
Z14_final <= Z14[13] ? Z14[24:14] + 1 : Z14[24:14];
Z15_final <= Z15[13] ? Z15[24:14] + 1 : Z15[24:14];
Z16_final <= Z16[13] ? Z16[24:14] + 1 : Z16[24:14];
Z17_final <= Z17[13] ? Z17[24:14] + 1 : Z17[24:14];
Z18_final <= Z18[13] ? Z18[24:14] + 1 : Z18[24:14];
Z21_final <= Z21[13] ? Z21[24:14] + 1 : Z21[24:14];
Z22_final <= Z22[13] ? Z22[24:14] + 1 : Z22[24:14];
Z23_final <= Z23[13] ? Z23[24:14] + 1 : Z23[24:14];
Z24_final <= Z24[13] ? Z24[24:14] + 1 : Z24[24:14];
Z25_final <= Z25[13] ? Z25[24:14] + 1 : Z25[24:14];
Z26_final <= Z26[13] ? Z26[24:14] + 1 : Z26[24:14];
Z27_final <= Z27[13] ? Z27[24:14] + 1 : Z27[24:14];
Z28_final <= Z28[13] ? Z28[24:14] + 1 : Z28[24:14];
Z31_final <= Z31[13] ? Z31[24:14] + 1 : Z31[24:14];
Z32_final <= Z32[13] ? Z32[24:14] + 1 : Z32[24:14];
Z33_final <= Z33[13] ? Z33[24:14] + 1 : Z33[24:14];
Z34_final <= Z34[13] ? Z34[24:14] + 1 : Z34[24:14];
Z35_final <= Z35[13] ? Z35[24:14] + 1 : Z35[24:14];
Z36_final <= Z36[13] ? Z36[24:14] + 1 : Z36[24:14];
Z37_final <= Z37[13] ? Z37[24:14] + 1 : Z37[24:14];
Z38_final <= Z38[13] ? Z38[24:14] + 1 : Z38[24:14];
Z41_final <= Z41[13] ? Z41[24:14] + 1 : Z41[24:14];
Z42_final <= Z42[13] ? Z42[24:14] + 1 : Z42[24:14];
Z43_final <= Z43[13] ? Z43[24:14] + 1 : Z43[24:14];
Z44_final <= Z44[13] ? Z44[24:14] + 1 : Z44[24:14];
Z45_final <= Z45[13] ? Z45[24:14] + 1 : Z45[24:14];
Z46_final <= Z46[13] ? Z46[24:14] + 1 : Z46[24:14];
Z47_final <= Z47[13] ? Z47[24:14] + 1 : Z47[24:14];
Z48_final <= Z48[13] ? Z48[24:14] + 1 : Z48[24:14];
Z51_final <= Z51[13] ? Z51[24:14] + 1 : Z51[24:14];
Z52_final <= Z52[13] ? Z52[24:14] + 1 : Z52[24:14];
Z53_final <= Z53[13] ? Z53[24:14] + 1 : Z53[24:14];
Z54_final <= Z54[13] ? Z54[24:14] + 1 : Z54[24:14];
Z55_final <= Z55[13] ? Z55[24:14] + 1 : Z55[24:14];
Z56_final <= Z56[13] ? Z56[24:14] + 1 : Z56[24:14];
Z57_final <= Z57[13] ? Z57[24:14] + 1 : Z57[24:14];
Z58_final <= Z58[13] ? Z58[24:14] + 1 : Z58[24:14];
Z61_final <= Z61[13] ? Z61[24:14] + 1 : Z61[24:14];
Z62_final <= Z62[13] ? Z62[24:14] + 1 : Z62[24:14];
Z63_final <= Z63[13] ? Z63[24:14] + 1 : Z63[24:14];
Z64_final <= Z64[13] ? Z64[24:14] + 1 : Z64[24:14];
Z65_final <= Z65[13] ? Z65[24:14] + 1 : Z65[24:14];
Z66_final <= Z66[13] ? Z66[24:14] + 1 : Z66[24:14];
Z67_final <= Z67[13] ? Z67[24:14] + 1 : Z67[24:14];
Z68_final <= Z68[13] ? Z68[24:14] + 1 : Z68[24:14];
Z71_final <= Z71[13] ? Z71[24:14] + 1 : Z71[24:14];
Z72_final <= Z72[13] ? Z72[24:14] + 1 : Z72[24:14];
Z73_final <= Z73[13] ? Z73[24:14] + 1 : Z73[24:14];
Z74_final <= Z74[13] ? Z74[24:14] + 1 : Z74[24:14];
Z75_final <= Z75[13] ? Z75[24:14] + 1 : Z75[24:14];
Z76_final <= Z76[13] ? Z76[24:14] + 1 : Z76[24:14];
Z77_final <= Z77[13] ? Z77[24:14] + 1 : Z77[24:14];
Z78_final <= Z78[13] ? Z78[24:14] + 1 : Z78[24:14];
Z81_final <= Z81[13] ? Z81[24:14] + 1 : Z81[24:14];
Z82_final <= Z82[13] ? Z82[24:14] + 1 : Z82[24:14];
Z83_final <= Z83[13] ? Z83[24:14] + 1 : Z83[24:14];
Z84_final <= Z84[13] ? Z84[24:14] + 1 : Z84[24:14];
Z85_final <= Z85[13] ? Z85[24:14] + 1 : Z85[24:14];
Z86_final <= Z86[13] ? Z86[24:14] + 1 : Z86[24:14];
Z87_final <= Z87[13] ? Z87[24:14] + 1 : Z87[24:14];
Z88_final <= Z88[13] ? Z88[24:14] + 1 : Z88[24:14];
end
end
// output_enable signals the next block, the quantizer, that the input data is ready
always @(posedge clk)
begin
if (rst)
output_enable <= 0;
else if (!enable_1)
output_enable <= 0;
else if (count_10 == 0 | count_of)
output_enable <= 0;
else if (count_10 & count_of == 0)
output_enable <= 1;
end
always @(posedge clk)
begin
if (rst)
Cb_temp_11 <= 0;
else if (enable)
Cb_temp_11 <= data_in * T1;
end
always @(posedge clk)
begin
if (rst)
Cb11 <= 0;
else if (count == 1 & enable == 1)
Cb11 <= Cb_temp_11;
else if (enable)
Cb11 <= Cb_temp_11 + Cb11;
end
always @(posedge clk)
begin
if (rst) begin
Cb_temp_21 <= 0;
Cb_temp_31 <= 0;
Cb_temp_41 <= 0;
Cb_temp_51 <= 0;
Cb_temp_61 <= 0;
Cb_temp_71 <= 0;
Cb_temp_81 <= 0;
end
else if (!enable_1) begin
Cb_temp_21 <= 0;
Cb_temp_31 <= 0;
Cb_temp_41 <= 0;
Cb_temp_51 <= 0;
Cb_temp_61 <= 0;
Cb_temp_71 <= 0;
Cb_temp_81 <= 0;
end
else if (enable_1) begin
Cb_temp_21 <= data_1 * Cb2_mul_input;
Cb_temp_31 <= data_1 * Cb3_mul_input;
Cb_temp_41 <= data_1 * Cb4_mul_input;
Cb_temp_51 <= data_1 * Cb5_mul_input;
Cb_temp_61 <= data_1 * Cb6_mul_input;
Cb_temp_71 <= data_1 * Cb7_mul_input;
Cb_temp_81 <= data_1 * Cb8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Cb21 <= 0;
Cb31 <= 0;
Cb41 <= 0;
Cb51 <= 0;
Cb61 <= 0;
Cb71 <= 0;
Cb81 <= 0;
end
else if (!enable_1) begin
Cb21 <= 0;
Cb31 <= 0;
Cb41 <= 0;
Cb51 <= 0;
Cb61 <= 0;
Cb71 <= 0;
Cb81 <= 0;
end
else if (enable_1) begin
Cb21 <= Cb_temp_21 + Cb21;
Cb31 <= Cb_temp_31 + Cb31;
Cb41 <= Cb_temp_41 + Cb41;
Cb51 <= Cb_temp_51 + Cb51;
Cb61 <= Cb_temp_61 + Cb61;
Cb71 <= Cb_temp_71 + Cb71;
Cb81 <= Cb_temp_81 + Cb81;
end
end
always @(posedge clk)
begin
if (rst) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (!enable) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (enable) begin
count <= count + 1; count_3 <= count_1; count_4 <= count_3;
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6;
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9;
end
end
always @(posedge clk)
begin
if (rst) begin
count_1 <= 0;
end
else if (count != 7 | !enable) begin
count_1 <= 0;
end
else if (count == 7) begin
count_1 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (!enable) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (count_1 == 1) begin
count_of <= count_of + 1;
count_of_copy <= count_of_copy + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
Cb11_final <= 0;
end
else if (count_3 & enable_1) begin
Cb11_final <= Cb11 - 25'd5932032;
/* The Cb values weren't centered on 0 before doing the DCT
128 needs to be subtracted from each Cb value before, or in this
case, 362 is subtracted from the total, because this is the
total obtained by subtracting 128 from each element
and then multiplying by the weight
assigned by the DCT matrix : 128*8*5793 = 5932032
This is only needed for the first row, the values in the rest of
the rows add up to 0 **/
end
end
always @(posedge clk)
begin
if (rst) begin
Cb21_final <= 0; Cb21_final_prev <= 0;
Cb31_final <= 0; Cb31_final_prev <= 0;
Cb41_final <= 0; Cb41_final_prev <= 0;
Cb51_final <= 0; Cb51_final_prev <= 0;
Cb61_final <= 0; Cb61_final_prev <= 0;
Cb71_final <= 0; Cb71_final_prev <= 0;
Cb81_final <= 0; Cb81_final_prev <= 0;
end
else if (!enable_1) begin
Cb21_final <= 0; Cb21_final_prev <= 0;
Cb31_final <= 0; Cb31_final_prev <= 0;
Cb41_final <= 0; Cb41_final_prev <= 0;
Cb51_final <= 0; Cb51_final_prev <= 0;
Cb61_final <= 0; Cb61_final_prev <= 0;
Cb71_final <= 0; Cb71_final_prev <= 0;
Cb81_final <= 0; Cb81_final_prev <= 0;
end
else if (count_4 & enable_1) begin
Cb21_final <= Cb21; Cb21_final_prev <= Cb21_final;
Cb31_final <= Cb31; Cb31_final_prev <= Cb31_final;
Cb41_final <= Cb41; Cb41_final_prev <= Cb41_final;
Cb51_final <= Cb51; Cb51_final_prev <= Cb51_final;
Cb61_final <= Cb61; Cb61_final_prev <= Cb61_final;
Cb71_final <= Cb71; Cb71_final_prev <= Cb71_final;
Cb81_final <= Cb81; Cb81_final_prev <= Cb81_final;
end
end
always @(posedge clk)
begin
if (rst) begin
Cb21_final_diff <= 0; Cb31_final_diff <= 0;
Cb41_final_diff <= 0; Cb51_final_diff <= 0;
Cb61_final_diff <= 0; Cb71_final_diff <= 0;
Cb81_final_diff <= 0;
end
else if (count_5 & enable_1) begin
Cb21_final_diff <= Cb21_final - Cb21_final_prev;
Cb31_final_diff <= Cb31_final - Cb31_final_prev;
Cb41_final_diff <= Cb41_final - Cb41_final_prev;
Cb51_final_diff <= Cb51_final - Cb51_final_prev;
Cb61_final_diff <= Cb61_final - Cb61_final_prev;
Cb71_final_diff <= Cb71_final - Cb71_final_prev;
Cb81_final_diff <= Cb81_final - Cb81_final_prev;
end
end
always @(posedge clk)
begin
case (count)
3'b000: Cb2_mul_input <= T21;
3'b001: Cb2_mul_input <= T22;
3'b010: Cb2_mul_input <= T23;
3'b011: Cb2_mul_input <= T24;
3'b100: Cb2_mul_input <= T25;
3'b101: Cb2_mul_input <= T26;
3'b110: Cb2_mul_input <= T27;
3'b111: Cb2_mul_input <= T28;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb3_mul_input <= T31;
3'b001: Cb3_mul_input <= T32;
3'b010: Cb3_mul_input <= T33;
3'b011: Cb3_mul_input <= T34;
3'b100: Cb3_mul_input <= T34;
3'b101: Cb3_mul_input <= T33;
3'b110: Cb3_mul_input <= T32;
3'b111: Cb3_mul_input <= T31;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb4_mul_input <= T22;
3'b001: Cb4_mul_input <= T25;
3'b010: Cb4_mul_input <= T28;
3'b011: Cb4_mul_input <= T26;
3'b100: Cb4_mul_input <= T23;
3'b101: Cb4_mul_input <= T21;
3'b110: Cb4_mul_input <= T24;
3'b111: Cb4_mul_input <= T27;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb5_mul_input <= T1;
3'b001: Cb5_mul_input <= T52;
3'b010: Cb5_mul_input <= T52;
3'b011: Cb5_mul_input <= T1;
3'b100: Cb5_mul_input <= T1;
3'b101: Cb5_mul_input <= T52;
3'b110: Cb5_mul_input <= T52;
3'b111: Cb5_mul_input <= T1;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb6_mul_input <= T23;
3'b001: Cb6_mul_input <= T28;
3'b010: Cb6_mul_input <= T24;
3'b011: Cb6_mul_input <= T22;
3'b100: Cb6_mul_input <= T27;
3'b101: Cb6_mul_input <= T25;
3'b110: Cb6_mul_input <= T21;
3'b111: Cb6_mul_input <= T26;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb7_mul_input <= T32;
3'b001: Cb7_mul_input <= T34;
3'b010: Cb7_mul_input <= T31;
3'b011: Cb7_mul_input <= T33;
3'b100: Cb7_mul_input <= T33;
3'b101: Cb7_mul_input <= T31;
3'b110: Cb7_mul_input <= T34;
3'b111: Cb7_mul_input <= T32;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Cb8_mul_input <= T24;
3'b001: Cb8_mul_input <= T26;
3'b010: Cb8_mul_input <= T22;
3'b011: Cb8_mul_input <= T28;
3'b100: Cb8_mul_input <= T21;
3'b101: Cb8_mul_input <= T27;
3'b110: Cb8_mul_input <= T23;
3'b111: Cb8_mul_input <= T25;
endcase
end
// Inverse DCT matrix entries
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti2_mul_input <= Ti28;
3'b001: Ti2_mul_input <= Ti21;
3'b010: Ti2_mul_input <= Ti22;
3'b011: Ti2_mul_input <= Ti23;
3'b100: Ti2_mul_input <= Ti24;
3'b101: Ti2_mul_input <= Ti25;
3'b110: Ti2_mul_input <= Ti26;
3'b111: Ti2_mul_input <= Ti27;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti3_mul_input <= Ti31;
3'b001: Ti3_mul_input <= Ti31;
3'b010: Ti3_mul_input <= Ti32;
3'b011: Ti3_mul_input <= Ti33;
3'b100: Ti3_mul_input <= Ti34;
3'b101: Ti3_mul_input <= Ti34;
3'b110: Ti3_mul_input <= Ti33;
3'b111: Ti3_mul_input <= Ti32;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti4_mul_input <= Ti27;
3'b001: Ti4_mul_input <= Ti22;
3'b010: Ti4_mul_input <= Ti25;
3'b011: Ti4_mul_input <= Ti28;
3'b100: Ti4_mul_input <= Ti26;
3'b101: Ti4_mul_input <= Ti23;
3'b110: Ti4_mul_input <= Ti21;
3'b111: Ti4_mul_input <= Ti24;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti5_mul_input <= Ti1;
3'b001: Ti5_mul_input <= Ti1;
3'b010: Ti5_mul_input <= Ti52;
3'b011: Ti5_mul_input <= Ti52;
3'b100: Ti5_mul_input <= Ti1;
3'b101: Ti5_mul_input <= Ti1;
3'b110: Ti5_mul_input <= Ti52;
3'b111: Ti5_mul_input <= Ti52;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti6_mul_input <= Ti26;
3'b001: Ti6_mul_input <= Ti23;
3'b010: Ti6_mul_input <= Ti28;
3'b011: Ti6_mul_input <= Ti24;
3'b100: Ti6_mul_input <= Ti22;
3'b101: Ti6_mul_input <= Ti27;
3'b110: Ti6_mul_input <= Ti25;
3'b111: Ti6_mul_input <= Ti21;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti7_mul_input <= Ti32;
3'b001: Ti7_mul_input <= Ti32;
3'b010: Ti7_mul_input <= Ti34;
3'b011: Ti7_mul_input <= Ti31;
3'b100: Ti7_mul_input <= Ti33;
3'b101: Ti7_mul_input <= Ti33;
3'b110: Ti7_mul_input <= Ti31;
3'b111: Ti7_mul_input <= Ti34;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti8_mul_input <= Ti25;
3'b001: Ti8_mul_input <= Ti24;
3'b010: Ti8_mul_input <= Ti26;
3'b011: Ti8_mul_input <= Ti22;
3'b100: Ti8_mul_input <= Ti28;
3'b101: Ti8_mul_input <= Ti21;
3'b110: Ti8_mul_input <= Ti27;
3'b111: Ti8_mul_input <= Ti23;
endcase
end
// Rounding stage
always @(posedge clk)
begin
if (rst) begin
data_1 <= 0;
Cb11_final_1 <= 0; Cb21_final_1 <= 0; Cb31_final_1 <= 0; Cb41_final_1 <= 0;
Cb51_final_1 <= 0; Cb61_final_1 <= 0; Cb71_final_1 <= 0; Cb81_final_1 <= 0;
Cb11_final_2 <= 0; Cb21_final_2 <= 0; Cb31_final_2 <= 0; Cb41_final_2 <= 0;
Cb51_final_2 <= 0; Cb61_final_2 <= 0; Cb71_final_2 <= 0; Cb81_final_2 <= 0;
Cb11_final_3 <= 0; Cb11_final_4 <= 0;
end
else if (enable) begin
data_1 <= data_in;
Cb11_final_1 <= Cb11_final[13] ? Cb11_final[24:14] + 1 : Cb11_final[24:14];
Cb11_final_2[31:11] <= Cb11_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb11_final_2[10:0] <= Cb11_final_1;
// Need to sign extend Cb11_final_1 and the other registers to store a negative
// number as a twos complement number. If you don't sign extend, then a negative number
// will be stored incorrectly as a positive number. For example, -215 would be stored
// as 1833 without sign extending
Cb11_final_3 <= Cb11_final_2;
Cb11_final_4 <= Cb11_final_3;
Cb21_final_1 <= Cb21_final_diff[13] ? Cb21_final_diff[24:14] + 1 : Cb21_final_diff[24:14];
Cb21_final_2[31:11] <= Cb21_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb21_final_2[10:0] <= Cb21_final_1;
Cb31_final_1 <= Cb31_final_diff[13] ? Cb31_final_diff[24:14] + 1 : Cb31_final_diff[24:14];
Cb31_final_2[31:11] <= Cb31_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb31_final_2[10:0] <= Cb31_final_1;
Cb41_final_1 <= Cb41_final_diff[13] ? Cb41_final_diff[24:14] + 1 : Cb41_final_diff[24:14];
Cb41_final_2[31:11] <= Cb41_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb41_final_2[10:0] <= Cb41_final_1;
Cb51_final_1 <= Cb51_final_diff[13] ? Cb51_final_diff[24:14] + 1 : Cb51_final_diff[24:14];
Cb51_final_2[31:11] <= Cb51_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb51_final_2[10:0] <= Cb51_final_1;
Cb61_final_1 <= Cb61_final_diff[13] ? Cb61_final_diff[24:14] + 1 : Cb61_final_diff[24:14];
Cb61_final_2[31:11] <= Cb61_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb61_final_2[10:0] <= Cb61_final_1;
Cb71_final_1 <= Cb71_final_diff[13] ? Cb71_final_diff[24:14] + 1 : Cb71_final_diff[24:14];
Cb71_final_2[31:11] <= Cb71_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb71_final_2[10:0] <= Cb71_final_1;
Cb81_final_1 <= Cb81_final_diff[13] ? Cb81_final_diff[24:14] + 1 : Cb81_final_diff[24:14];
Cb81_final_2[31:11] <= Cb81_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Cb81_final_2[10:0] <= Cb81_final_1;
// The bit in place 13 is the fraction part, for rounding purposes
// if it is 1, then you need to add 1 to the bits in 22-14,
// if bit 13 is 0, then the bits in 22-14 won't change
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0;
end
else begin
enable_1 <= enable;
end
end
endmodule
cr_dct.1897Z85_final
1897Z85_finalreg[10:0]
Definition: cr_dct.v:140
cr_dct.1644Ti25
1644Ti25integer
Definition: cr_dct.v:82
cr_dct.1819Cb51_final
1819Cb51_finalreg[24:0]
Definition: cr_dct.v:116
cr_dct.1817Cb31_final
1817Cb31_finalreg[24:0]
Definition: cr_dct.v:116
cr_dct.1699Z_temp_46
1699Z_temp_46reg[31:0]
Definition: cr_dct.v:95
cr_dct.1677Z_temp_18
1677Z_temp_18reg[31:0]
Definition: cr_dct.v:89
cr_dct.1679Z_temp_22
1679Z_temp_22reg[31:0]
Definition: cr_dct.v:90
cr_dct.1756Z37
1756Z37reg[24:0]
Definition: cr_dct.v:106
cr_dct.1882Z66_final
1882Z66_finalreg[10:0]
Definition: cr_dct.v:136
cr_dct.1659Cb61
1659Cb61reg[24:0]
Definition: cr_dct.v:85
cr_dct.1841Z15_final
1841Z15_finalreg[10:0]
Definition: cr_dct.v:126
cr_dct.1814Cb71_final_1
1814Cb71_final_1reg[10:0]
Definition: cr_dct.v:115
cr_dct.1723Z_temp_76
1723Z_temp_76reg[31:0]
Definition: cr_dct.v:101
cr_dct.1895Z83_final
1895Z83_finalreg[10:0]
Definition: cr_dct.v:139
cr_dct.1708Z_temp_57
1708Z_temp_57reg[31:0]
Definition: cr_dct.v:97
cr_dct.1709Z_temp_58
1709Z_temp_58reg[31:0]
Definition: cr_dct.v:97
cr_dct.1811Cb41_final_1
1811Cb41_final_1reg[10:0]
Definition: cr_dct.v:114
cr_dct.1685Z_temp_28
1685Z_temp_28reg[31:0]
Definition: cr_dct.v:91
cr_dct.1917Cb3_mul_input
1917Cb3_mul_inputinteger
Definition: cr_dct.v:146
cr_dct.1789Z78
1789Z78reg[24:0]
Definition: cr_dct.v:110
cr_dct.1693Z_temp_38
1693Z_temp_38reg[31:0]
Definition: cr_dct.v:93
cr_dct.1742Z21
1742Z21reg[24:0]
Definition: cr_dct.v:105
cr_dct.1928Ti7_mul_input
1928Ti7_mul_inputinteger
Definition: cr_dct.v:149
cr_dct.1692Z_temp_37
1692Z_temp_37reg[31:0]
Definition: cr_dct.v:93
cr_dct.1653Cb_temp_11
1653Cb_temp_11reg[24:0]
Definition: cr_dct.v:84
cr_dct.1929Ti8_mul_input
1929Ti8_mul_inputinteger
Definition: cr_dct.v:149
cr_dct.1671Z_temp_12
1671Z_temp_12reg[31:0]
Definition: cr_dct.v:88
cr_dct.1625T1
1625T1integer
Definition: cr_dct.v:81
cr_dct.1818Cb41_final
1818Cb41_finalreg[24:0]
Definition: cr_dct.v:116
cr_dct.1556clk
1556clk
Definition: cr_dct.v:58
cr_dct.1767Z52
1767Z52reg[24:0]
Definition: cr_dct.v:108
cr_dct.1705Z_temp_54
1705Z_temp_54reg[31:0]
Definition: cr_dct.v:96
cr_dct.1626T21
1626T21integer
Definition: cr_dct.v:81
cr_dct.1920Cb6_mul_input
1920Cb6_mul_inputinteger
Definition: cr_dct.v:147
cr_dct.1694Z_temp_41
1694Z_temp_41reg[31:0]
Definition: cr_dct.v:94
cr_dct.1853Z31_final
1853Z31_finalreg[10:0]
Definition: cr_dct.v:129
cr_dct.1784Z73
1784Z73reg[24:0]
Definition: cr_dct.v:110
cr_dct.1728Z_temp_83
1728Z_temp_83reg[31:0]
Definition: cr_dct.v:102
cr_dct.1786Z75
1786Z75reg[24:0]
Definition: cr_dct.v:110
cr_dct.1654Cb11
1654Cb11reg[24:0]
Definition: cr_dct.v:85
cr_dct.1673Z_temp_14
1673Z_temp_14reg[31:0]
Definition: cr_dct.v:88
cr_dct.1852Z28_final
1852Z28_finalreg[10:0]
Definition: cr_dct.v:128
cr_dct.1927Ti6_mul_input
1927Ti6_mul_inputinteger
Definition: cr_dct.v:149
cr_dct.1794Z85
1794Z85reg[24:0]
Definition: cr_dct.v:111
cr_dct.1706Z_temp_55
1706Z_temp_55reg[31:0]
Definition: cr_dct.v:97
cr_dct.1805Cb61_final_2
1805Cb61_final_2reg[31:0]
Definition: cr_dct.v:113
cr_dct.1923Ti2_mul_input
1923Ti2_mul_inputinteger
Definition: cr_dct.v:148
cr_dct.1701Z_temp_48
1701Z_temp_48reg[31:0]
Definition: cr_dct.v:95
cr_dct.1686Z_temp_31
1686Z_temp_31reg[31:0]
Definition: cr_dct.v:92
cr_dct.1822Cb81_final
1822Cb81_finalreg[24:0]
Definition: cr_dct.v:117
cr_dct.1632T27
1632T27integer
Definition: cr_dct.v:81
cr_dct.1684Z_temp_27
1684Z_temp_27reg[31:0]
Definition: cr_dct.v:91
cr_dct.1670Z_temp_11
1670Z_temp_11reg[31:0]
Definition: cr_dct.v:88
cr_dct.1734Z11
1734Z11reg[24:0]
Definition: cr_dct.v:104
cr_dct.1665Cb_temp_41
1665Cb_temp_41reg[31:0]
Definition: cr_dct.v:86
cr_dct.1674Z_temp_15
1674Z_temp_15reg[31:0]
Definition: cr_dct.v:89
cr_dct.1763Z46
1763Z46reg[24:0]
Definition: cr_dct.v:107
cr_dct.1905count_3
1905count_3reg
Definition: cr_dct.v:143
cr_dct.1893Z81_final
1893Z81_finalreg[10:0]
Definition: cr_dct.v:139
cr_dct.1698Z_temp_45
1698Z_temp_45reg[31:0]
Definition: cr_dct.v:95
cr_dct.1918Cb4_mul_input
1918Cb4_mul_inputinteger
Definition: cr_dct.v:146
cr_dct.1887Z73_final
1887Z73_finalreg[10:0]
Definition: cr_dct.v:137
cr_dct.1886Z72_final
1886Z72_finalreg[10:0]
Definition: cr_dct.v:137
cr_dct.1658Cb51
1658Cb51reg[24:0]
Definition: cr_dct.v:85
cr_dct.1849Z25_final
1849Z25_finalreg[10:0]
Definition: cr_dct.v:128
cr_dct.1750Z31
1750Z31reg[24:0]
Definition: cr_dct.v:106
cr_dct.1845Z21_final
1845Z21_finalreg[10:0]
Definition: cr_dct.v:127
cr_dct.1860Z38_final
1860Z38_finalreg[10:0]
Definition: cr_dct.v:130
cr_dct.1851Z27_final
1851Z27_finalreg[10:0]
Definition: cr_dct.v:128
cr_dct.1799Cb21_final_2
1799Cb21_final_2reg[31:0]
Definition: cr_dct.v:112
cr_dct.1737Z14
1737Z14reg[24:0]
Definition: cr_dct.v:104
cr_dct.1738Z15
1738Z15reg[24:0]
Definition: cr_dct.v:104
cr_dct.1636T33
1636T33integer
Definition: cr_dct.v:81
cr_dct.1821Cb71_final
1821Cb71_finalreg[24:0]
Definition: cr_dct.v:117
cr_dct.1656Cb31
1656Cb31reg[24:0]
Definition: cr_dct.v:85
cr_dct.1691Z_temp_36
1691Z_temp_36reg[31:0]
Definition: cr_dct.v:93
cr_dct.1633T28
1633T28integer
Definition: cr_dct.v:81
cr_dct.1787Z76
1787Z76reg[24:0]
Definition: cr_dct.v:110
cr_dct.1791Z82
1791Z82reg[24:0]
Definition: cr_dct.v:111
cr_dct.1721Z_temp_74
1721Z_temp_74reg[31:0]
Definition: cr_dct.v:100
cr_dct.1873Z55_final
1873Z55_finalreg[10:0]
Definition: cr_dct.v:134
cr_dct.1793Z84
1793Z84reg[24:0]
Definition: cr_dct.v:111
cr_dct.1836Cb81_final_diff
1836Cb81_final_diffreg[24:0]
Definition: cr_dct.v:124
cr_dct.1809Cb21_final_1
1809Cb21_final_1reg[10:0]
Definition: cr_dct.v:114
cr_dct.1759Z42
1759Z42reg[24:0]
Definition: cr_dct.v:107
cr_dct.1863Z43_final
1863Z43_finalreg[10:0]
Definition: cr_dct.v:131
cr_dct.1726Z_temp_81
1726Z_temp_81reg[31:0]
Definition: cr_dct.v:102
cr_dct.1689Z_temp_34
1689Z_temp_34reg[31:0]
Definition: cr_dct.v:92
cr_dct.1823Cb21_final_prev
1823Cb21_final_prevreg[24:0]
Definition: cr_dct.v:118
cr_dct.1651Ti34
1651Ti34integer
Definition: cr_dct.v:82
cr_dct.1744Z23
1744Z23reg[24:0]
Definition: cr_dct.v:105
cr_dct.1900Z88_final
1900Z88_finalreg[10:0]
Definition: cr_dct.v:140
cr_dct.1702Z_temp_51
1702Z_temp_51reg[31:0]
Definition: cr_dct.v:96
cr_dct.1745Z24
1745Z24reg[24:0]
Definition: cr_dct.v:105
cr_dct.1901count
1901countreg[2:0]
Definition: cr_dct.v:141
cr_dct.1833Cb71_final_prev
1833Cb71_final_prevreg[24:0]
Definition: cr_dct.v:123
cr_dct.1862Z42_final
1862Z42_finalreg[10:0]
Definition: cr_dct.v:131
cr_dct.1634T31
1634T31integer
Definition: cr_dct.v:81
cr_dct.1777Z64
1777Z64reg[24:0]
Definition: cr_dct.v:109
cr_dct.1835Cb81_final_prev
1835Cb81_final_prevreg[24:0]
Definition: cr_dct.v:124
cr_dct.1629T24
1629T24integer
Definition: cr_dct.v:81
cr_dct.1866Z46_final
1866Z46_finalreg[10:0]
Definition: cr_dct.v:132
cr_dct.1792Z83
1792Z83reg[24:0]
Definition: cr_dct.v:111
cr_dct.1666Cb_temp_51
1666Cb_temp_51reg[31:0]
Definition: cr_dct.v:86
cr_dct.1757Z38
1757Z38reg[24:0]
Definition: cr_dct.v:106
cr_dct.1864Z44_final
1864Z44_finalreg[10:0]
Definition: cr_dct.v:131
cr_dct.1785Z74
1785Z74reg[24:0]
Definition: cr_dct.v:110
cr_dct.1716Z_temp_67
1716Z_temp_67reg[31:0]
Definition: cr_dct.v:99
cr_dct.1778Z65
1778Z65reg[24:0]
Definition: cr_dct.v:109
cr_dct.1790Z81
1790Z81reg[24:0]
Definition: cr_dct.v:111
cr_dct.1898Z86_final
1898Z86_finalreg[10:0]
Definition: cr_dct.v:140
cr_dct.1766Z51
1766Z51reg[24:0]
Definition: cr_dct.v:108
cr_dct.1661Cb81
1661Cb81reg[24:0]
Definition: cr_dct.v:85
cr_dct.1760Z43
1760Z43reg[24:0]
Definition: cr_dct.v:107
cr_dct.1907count_5
1907count_5reg
Definition: cr_dct.v:143
cr_dct.1739Z16
1739Z16reg[24:0]
Definition: cr_dct.v:104
cr_dct.1826Cb31_final_diff
1826Cb31_final_diffreg[24:0]
Definition: cr_dct.v:119
cr_dct.1662Cb11_final
1662Cb11_finalreg[24:0]
Definition: cr_dct.v:85
cr_dct.1761Z44
1761Z44reg[24:0]
Definition: cr_dct.v:107
cr_dct.1710Z_temp_61
1710Z_temp_61reg[31:0]
Definition: cr_dct.v:98
cr_dct.1899Z87_final
1899Z87_finalreg[10:0]
Definition: cr_dct.v:140
cr_dct.1774Z61
1774Z61reg[24:0]
Definition: cr_dct.v:109
cr_dct.1736Z13
1736Z13reg[24:0]
Definition: cr_dct.v:104
cr_dct.1828Cb41_final_diff
1828Cb41_final_diffreg[24:0]
Definition: cr_dct.v:120
cr_dct.1906count_4
1906count_4reg
Definition: cr_dct.v:143
cr_dct.1820Cb61_final
1820Cb61_finalreg[24:0]
Definition: cr_dct.v:117
cr_dct.1715Z_temp_66
1715Z_temp_66reg[31:0]
Definition: cr_dct.v:99
cr_dct.1770Z55
1770Z55reg[24:0]
Definition: cr_dct.v:108
cr_dct.1743Z22
1743Z22reg[24:0]
Definition: cr_dct.v:105
cr_dct.1735Z12
1735Z12reg[24:0]
Definition: cr_dct.v:104
cr_dct.1782Z71
1782Z71reg[24:0]
Definition: cr_dct.v:110
cr_dct.1642Ti23
1642Ti23integer
Definition: cr_dct.v:82
cr_dct.1748Z27
1748Z27reg[24:0]
Definition: cr_dct.v:105
cr_dct.1803Cb41_final_2
1803Cb41_final_2reg[31:0]
Definition: cr_dct.v:112
cr_dct.1911enable_1
1911enable_1reg
Definition: cr_dct.v:143
cr_dct.1857Z35_final
1857Z35_finalreg[10:0]
Definition: cr_dct.v:130
cr_dct.1796Z87
1796Z87reg[24:0]
Definition: cr_dct.v:111
cr_dct.1683Z_temp_26
1683Z_temp_26reg[31:0]
Definition: cr_dct.v:91
cr_dct.1557rst
1557rst
Definition: cr_dct.v:59
cr_dct.1813Cb61_final_1
1813Cb61_final_1reg[10:0]
Definition: cr_dct.v:115
cr_dct.1839Z13_final
1839Z13_finalreg[10:0]
Definition: cr_dct.v:125
cr_dct.1764Z47
1764Z47reg[24:0]
Definition: cr_dct.v:107
cr_dct.1825Cb31_final_prev
1825Cb31_final_prevreg[24:0]
Definition: cr_dct.v:119
cr_dct.1922Cb8_mul_input
1922Cb8_mul_inputinteger
Definition: cr_dct.v:147
cr_dct.1652Ti52
1652Ti52integer
Definition: cr_dct.v:82
cr_dct.1703Z_temp_52
1703Z_temp_52reg[31:0]
Definition: cr_dct.v:96
cr_dct.1861Z41_final
1861Z41_finalreg[10:0]
Definition: cr_dct.v:131
cr_dct.1829Cb51_final_prev
1829Cb51_final_prevreg[24:0]
Definition: cr_dct.v:121
cr_dct.1795Z86
1795Z86reg[24:0]
Definition: cr_dct.v:111
cr_dct.1558enable
1558enable
Definition: cr_dct.v:60
cr_dct.1628T23
1628T23integer
Definition: cr_dct.v:81
cr_dct.1874Z56_final
1874Z56_finalreg[10:0]
Definition: cr_dct.v:134
cr_dct.1902count_of
1902count_ofreg[2:0]
Definition: cr_dct.v:142
cr_dct.1801Cb11_final_4
1801Cb11_final_4reg[31:0]
Definition: cr_dct.v:112
cr_dct.1773Z58
1773Z58reg[24:0]
Definition: cr_dct.v:108
cr_dct.1704Z_temp_53
1704Z_temp_53reg[31:0]
Definition: cr_dct.v:96
cr_dct.1908count_6
1908count_6reg
Definition: cr_dct.v:143
cr_dct.1847Z23_final
1847Z23_finalreg[10:0]
Definition: cr_dct.v:127
cr_dct.1884Z68_final
1884Z68_finalreg[10:0]
Definition: cr_dct.v:136
cr_dct.1762Z45
1762Z45reg[24:0]
Definition: cr_dct.v:107
cr_dct.1648Ti31
1648Ti31integer
Definition: cr_dct.v:82
cr_dct.1834Cb71_final_diff
1834Cb71_final_diffreg[24:0]
Definition: cr_dct.v:123
cr_dct.1752Z33
1752Z33reg[24:0]
Definition: cr_dct.v:106
cr_dct.1725Z_temp_78
1725Z_temp_78reg[31:0]
Definition: cr_dct.v:101
cr_dct.1731Z_temp_86
1731Z_temp_86reg[31:0]
Definition: cr_dct.v:103
cr_dct.1755Z36
1755Z36reg[24:0]
Definition: cr_dct.v:106
cr_dct.1914count_10
1914count_10reg
Definition: cr_dct.v:144
cr_dct.1676Z_temp_17
1676Z_temp_17reg[31:0]
Definition: cr_dct.v:89
cr_dct.1675Z_temp_16
1675Z_temp_16reg[31:0]
Definition: cr_dct.v:89
cr_dct.1765Z48
1765Z48reg[24:0]
Definition: cr_dct.v:107
cr_dct.1880Z64_final
1880Z64_finalreg[10:0]
Definition: cr_dct.v:135
cr_dct.1891Z77_final
1891Z77_finalreg[10:0]
Definition: cr_dct.v:138
cr_dct.1832Cb61_final_diff
1832Cb61_final_diffreg[24:0]
Definition: cr_dct.v:122
cr_dct.1909count_7
1909count_7reg
Definition: cr_dct.v:143
cr_dct.1877Z61_final
1877Z61_finalreg[10:0]
Definition: cr_dct.v:135
cr_dct.1669Cb_temp_81
1669Cb_temp_81reg[31:0]
Definition: cr_dct.v:87
cr_dct.1875Z57_final
1875Z57_finalreg[10:0]
Definition: cr_dct.v:134
cr_dct.1788Z77
1788Z77reg[24:0]
Definition: cr_dct.v:110
cr_dct.1631T26
1631T26integer
Definition: cr_dct.v:81
cr_dct.1776Z63
1776Z63reg[24:0]
Definition: cr_dct.v:109
cr_dct.1697Z_temp_44
1697Z_temp_44reg[31:0]
Definition: cr_dct.v:94
cr_dct.1641Ti22
1641Ti22integer
Definition: cr_dct.v:82
cr_dct.1695Z_temp_42
1695Z_temp_42reg[31:0]
Definition: cr_dct.v:94
cr_dct.1559data_in
[7:0] 1559data_in
Definition: cr_dct.v:61
cr_dct.1913count_9
1913count_9reg
Definition: cr_dct.v:144
cr_dct.1637T34
1637T34integer
Definition: cr_dct.v:81
cr_dct.1727Z_temp_82
1727Z_temp_82reg[31:0]
Definition: cr_dct.v:102
cr_dct.1844Z18_final
1844Z18_finalreg[10:0]
Definition: cr_dct.v:126
cr_dct.1643Ti24
1643Ti24integer
Definition: cr_dct.v:82
cr_dct.1896Z84_final
1896Z84_finalreg[10:0]
Definition: cr_dct.v:139
cr_dct.1868Z48_final
1868Z48_finalreg[10:0]
Definition: cr_dct.v:132
cr_dct.1824Cb21_final_diff
1824Cb21_final_diffreg[24:0]
Definition: cr_dct.v:118
cr_dct.1713Z_temp_64
1713Z_temp_64reg[31:0]
Definition: cr_dct.v:98
cr_dct.1878Z62_final
1878Z62_finalreg[10:0]
Definition: cr_dct.v:135
cr_dct.1800Cb11_final_3
1800Cb11_final_3reg[31:0]
Definition: cr_dct.v:112
cr_dct.1657Cb41
1657Cb41reg[24:0]
Definition: cr_dct.v:85
cr_dct.1712Z_temp_63
1712Z_temp_63reg[31:0]
Definition: cr_dct.v:98
cr_dct.1707Z_temp_56
1707Z_temp_56reg[31:0]
Definition: cr_dct.v:97
cr_dct.1751Z32
1751Z32reg[24:0]
Definition: cr_dct.v:106
cr_dct.1859Z37_final
1859Z37_finalreg[10:0]
Definition: cr_dct.v:130
cr_dct.1746Z25
1746Z25reg[24:0]
Definition: cr_dct.v:105
cr_dct.1856Z34_final
1856Z34_finalreg[10:0]
Definition: cr_dct.v:129
cr_dct.1779Z66
1779Z66reg[24:0]
Definition: cr_dct.v:109
cr_dct.1810Cb31_final_1
1810Cb31_final_1reg[10:0]
Definition: cr_dct.v:114
cr_dct.1843Z17_final
1843Z17_finalreg[10:0]
Definition: cr_dct.v:126
cr_dct.1630T25
1630T25integer
Definition: cr_dct.v:81
cr_dct.1919Cb5_mul_input
1919Cb5_mul_inputinteger
Definition: cr_dct.v:146
cr_dct
Definition: cr_dct.v:48
cr_dct.1646Ti27
1646Ti27integer
Definition: cr_dct.v:82
cr_dct.1890Z76_final
1890Z76_finalreg[10:0]
Definition: cr_dct.v:138
cr_dct.1827Cb41_final_prev
1827Cb41_final_prevreg[24:0]
Definition: cr_dct.v:120
cr_dct.1888Z74_final
1888Z74_finalreg[10:0]
Definition: cr_dct.v:137
cr_dct.1797Z88
1797Z88reg[24:0]
Definition: cr_dct.v:111
cr_dct.1871Z53_final
1871Z53_finalreg[10:0]
Definition: cr_dct.v:133
cr_dct.1730Z_temp_85
1730Z_temp_85reg[31:0]
Definition: cr_dct.v:103
cr_dct.1838Z12_final
1838Z12_finalreg[10:0]
Definition: cr_dct.v:125
cr_dct.1719Z_temp_72
1719Z_temp_72reg[31:0]
Definition: cr_dct.v:100
cr_dct.1870Z52_final
1870Z52_finalreg[10:0]
Definition: cr_dct.v:133
cr_dct.1876Z58_final
1876Z58_finalreg[10:0]
Definition: cr_dct.v:134
cr_dct.1753Z34
1753Z34reg[24:0]
Definition: cr_dct.v:106
cr_dct.1660Cb71
1660Cb71reg[24:0]
Definition: cr_dct.v:85
cr_dct.1924Ti3_mul_input
1924Ti3_mul_inputinteger
Definition: cr_dct.v:148
cr_dct.1816Cb21_final
1816Cb21_finalreg[24:0]
Definition: cr_dct.v:116
cr_dct.1846Z22_final
1846Z22_finalreg[10:0]
Definition: cr_dct.v:127
cr_dct.1921Cb7_mul_input
1921Cb7_mul_inputinteger
Definition: cr_dct.v:147
cr_dct.1808Cb11_final_1
1808Cb11_final_1reg[10:0]
Definition: cr_dct.v:114
cr_dct.1889Z75_final
1889Z75_finalreg[10:0]
Definition: cr_dct.v:138
cr_dct.1872Z54_final
1872Z54_finalreg[10:0]
Definition: cr_dct.v:133
cr_dct.1892Z78_final
1892Z78_finalreg[10:0]
Definition: cr_dct.v:138
cr_dct.1807Cb81_final_2
1807Cb81_final_2reg[31:0]
Definition: cr_dct.v:113
cr_dct.1802Cb31_final_2
1802Cb31_final_2reg[31:0]
Definition: cr_dct.v:112
cr_dct.1768Z53
1768Z53reg[24:0]
Definition: cr_dct.v:108
cr_dct.1655Cb21
1655Cb21reg[24:0]
Definition: cr_dct.v:85
cr_dct.1855Z33_final
1855Z33_finalreg[10:0]
Definition: cr_dct.v:129
cr_dct.1687Z_temp_32
1687Z_temp_32reg[31:0]
Definition: cr_dct.v:92
cr_dct.1775Z62
1775Z62reg[24:0]
Definition: cr_dct.v:109
cr_dct.1894Z82_final
1894Z82_finalreg[10:0]
Definition: cr_dct.v:139
cr_dct.1740Z17
1740Z17reg[24:0]
Definition: cr_dct.v:104
cr_dct.1854Z32_final
1854Z32_finalreg[10:0]
Definition: cr_dct.v:129
cr_dct.1858Z36_final
1858Z36_finalreg[10:0]
Definition: cr_dct.v:130
cr_dct.1812Cb51_final_1
1812Cb51_final_1reg[10:0]
Definition: cr_dct.v:115
cr_dct.1754Z35
1754Z35reg[24:0]
Definition: cr_dct.v:106
cr_dct.1780Z67
1780Z67reg[24:0]
Definition: cr_dct.v:109
cr_dct.1700Z_temp_47
1700Z_temp_47reg[31:0]
Definition: cr_dct.v:95
cr_dct.1733Z_temp_88
1733Z_temp_88reg[31:0]
Definition: cr_dct.v:103
cr_dct.1649Ti32
1649Ti32integer
Definition: cr_dct.v:82
cr_dct.1879Z63_final
1879Z63_finalreg[10:0]
Definition: cr_dct.v:135
cr_dct.1682Z_temp_25
1682Z_temp_25reg[31:0]
Definition: cr_dct.v:91
cr_dct.1717Z_temp_68
1717Z_temp_68reg[31:0]
Definition: cr_dct.v:99
cr_dct.1885Z71_final
1885Z71_finalreg[10:0]
Definition: cr_dct.v:137
cr_dct.1830Cb51_final_diff
1830Cb51_final_diffreg[24:0]
Definition: cr_dct.v:121
cr_dct.1771Z56
1771Z56reg[24:0]
Definition: cr_dct.v:108
cr_dct.1664Cb_temp_31
1664Cb_temp_31reg[31:0]
Definition: cr_dct.v:86
cr_dct.1910count_8
1910count_8reg
Definition: cr_dct.v:143
cr_dct.1772Z57
1772Z57reg[24:0]
Definition: cr_dct.v:108
cr_dct.1749Z28
1749Z28reg[24:0]
Definition: cr_dct.v:105
cr_dct.1912output_enable
1912output_enablereg
Definition: cr_dct.v:143
cr_dct.1720Z_temp_73
1720Z_temp_73reg[31:0]
Definition: cr_dct.v:100
cr_dct.1758Z41
1758Z41reg[24:0]
Definition: cr_dct.v:107
cr_dct.1638T52
1638T52integer
Definition: cr_dct.v:81
cr_dct.1729Z_temp_84
1729Z_temp_84reg[31:0]
Definition: cr_dct.v:102
cr_dct.1635T32
1635T32integer
Definition: cr_dct.v:81
cr_dct.1840Z14_final
1840Z14_finalreg[10:0]
Definition: cr_dct.v:125
cr_dct.1678Z_temp_21
1678Z_temp_21reg[31:0]
Definition: cr_dct.v:90
cr_dct.1926Ti5_mul_input
1926Ti5_mul_inputinteger
Definition: cr_dct.v:148
cr_dct.1837Z11_final
1837Z11_finalreg[10:0]
Definition: cr_dct.v:125
cr_dct.1904count_1
1904count_1reg
Definition: cr_dct.v:143
cr_dct.1696Z_temp_43
1696Z_temp_43reg[31:0]
Definition: cr_dct.v:94
cr_dct.1798Cb11_final_2
1798Cb11_final_2reg[31:0]
Definition: cr_dct.v:112
cr_dct.1681Z_temp_24
1681Z_temp_24reg[31:0]
Definition: cr_dct.v:90
cr_dct.1722Z_temp_75
1722Z_temp_75reg[31:0]
Definition: cr_dct.v:101
cr_dct.1881Z65_final
1881Z65_finalreg[10:0]
Definition: cr_dct.v:136
cr_dct.1668Cb_temp_71
1668Cb_temp_71reg[31:0]
Definition: cr_dct.v:87
cr_dct.1647Ti28
1647Ti28integer
Definition: cr_dct.v:82
cr_dct.1831Cb61_final_prev
1831Cb61_final_prevreg[24:0]
Definition: cr_dct.v:122
cr_dct.1718Z_temp_71
1718Z_temp_71reg[31:0]
Definition: cr_dct.v:100
cr_dct.1869Z51_final
1869Z51_finalreg[10:0]
Definition: cr_dct.v:133
cr_dct.1925Ti4_mul_input
1925Ti4_mul_inputinteger
Definition: cr_dct.v:148
cr_dct.1663Cb_temp_21
1663Cb_temp_21reg[31:0]
Definition: cr_dct.v:86
cr_dct.1815Cb81_final_1
1815Cb81_final_1reg[10:0]
Definition: cr_dct.v:115
cr_dct.1724Z_temp_77
1724Z_temp_77reg[31:0]
Definition: cr_dct.v:101
cr_dct.1650Ti33
1650Ti33integer
Definition: cr_dct.v:82
cr_dct.1667Cb_temp_61
1667Cb_temp_61reg[31:0]
Definition: cr_dct.v:87
cr_dct.1714Z_temp_65
1714Z_temp_65reg[31:0]
Definition: cr_dct.v:99
cr_dct.1783Z72
1783Z72reg[24:0]
Definition: cr_dct.v:110
cr_dct.1741Z18
1741Z18reg[24:0]
Definition: cr_dct.v:104
cr_dct.1732Z_temp_87
1732Z_temp_87reg[31:0]
Definition: cr_dct.v:103
cr_dct.1916Cb2_mul_input
1916Cb2_mul_inputinteger
Definition: cr_dct.v:146
cr_dct.1915data_1
1915data_1reg[7:0]
Definition: cr_dct.v:145
cr_dct.1672Z_temp_13
1672Z_temp_13reg[31:0]
Definition: cr_dct.v:88
cr_dct.1867Z47_final
1867Z47_finalreg[10:0]
Definition: cr_dct.v:132
cr_dct.1883Z67_final
1883Z67_finalreg[10:0]
Definition: cr_dct.v:136
cr_dct.1769Z54
1769Z54reg[24:0]
Definition: cr_dct.v:108
cr_dct.1640Ti21
1640Ti21integer
Definition: cr_dct.v:82
cr_dct.1711Z_temp_62
1711Z_temp_62reg[31:0]
Definition: cr_dct.v:98
cr_dct.1747Z26
1747Z26reg[24:0]
Definition: cr_dct.v:105
cr_dct.1865Z45_final
1865Z45_finalreg[10:0]
Definition: cr_dct.v:132
cr_dct.1903count_of_copy
1903count_of_copyreg[2:0]
Definition: cr_dct.v:142
cr_dct.1639Ti1
1639Ti1integer
Definition: cr_dct.v:82
cr_dct.1850Z26_final
1850Z26_finalreg[10:0]
Definition: cr_dct.v:128
cr_dct.1806Cb71_final_2
1806Cb71_final_2reg[31:0]
Definition: cr_dct.v:113
cr_dct.1690Z_temp_35
1690Z_temp_35reg[31:0]
Definition: cr_dct.v:93
cr_dct.1645Ti26
1645Ti26integer
Definition: cr_dct.v:82
cr_dct.1781Z68
1781Z68reg[24:0]
Definition: cr_dct.v:109
cr_dct.1688Z_temp_33
1688Z_temp_33reg[31:0]
Definition: cr_dct.v:92
cr_dct.1627T22
1627T22integer
Definition: cr_dct.v:81
cr_dct.1842Z16_final
1842Z16_finalreg[10:0]
Definition: cr_dct.v:126
cr_dct.1680Z_temp_23
1680Z_temp_23reg[31:0]
Definition: cr_dct.v:90
cr_dct.1848Z24_final
1848Z24_finalreg[10:0]
Definition: cr_dct.v:127
cr_dct.1804Cb51_final_2
1804Cb51_final_2reg[31:0]
Definition: cr_dct.v:113