oc_jpegencode
1.0
JPEGencoder
rgb2ycbcr.v
Go to the documentation of this file.
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// JPEG Encoder Core - Verilog ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/* This module converts the incoming Red, Green, and Blue 8-bit pixel data
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into Y, Cb, and Cr 8-bit values. The output values will be unsigned
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in the range of 0 to 255.
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data_in contains the Red pixel value in bits [7:0], Green in bits [15:8],
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and Blue in bits [23:16].
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data_out contains the Y value in bits [7:0], Cb value in bits [15:8],
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and Cr balue in bits [23:16].**/
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`timescale 1ns / 100ps
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module
RGB2YCBCR
(
clk
,
rst
,
enable
,
data_in
,
data_out
,
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enable_out
);
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input
clk
;
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input
rst
;
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input
enable
;
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input
[
23
:
0
]
data_in
;
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output
[
23
:
0
]
data_out
;
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output
enable_out
;
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wire
[
13
:
0
]
Y1
=
14'd4899
;
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wire
[
13
:
0
]
Y2
=
14'd9617
;
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wire
[
13
:
0
]
Y3
=
14'd1868
;
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wire
[
13
:
0
]
CB1
=
14'd2764
;
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wire
[
13
:
0
]
CB2
=
14'd5428
;
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wire
[
13
:
0
]
CB3
=
14'd8192
;
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wire
[
13
:
0
]
CR1
=
14'd8192
;
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wire
[
13
:
0
]
CR2
=
14'd6860
;
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wire
[
13
:
0
]
CR3
=
14'd1332
;
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reg
[
21
:
0
]
Y_temp
,
CB_temp
,
CR_temp
;
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reg
[
21
:
0
]
Y1_product
,
Y2_product
,
Y3_product
;
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reg
[
21
:
0
]
CB1_product
,
CB2_product
,
CB3_product
;
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reg
[
21
:
0
]
CR1_product
,
CR2_product
,
CR3_product
;
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reg
[
7
:
0
]
Y
,
CB
,
CR
;
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reg
enable_1
,
enable_2
,
enable_out
;
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wire
[
23
:
0
]
data_out
= {
CR
,
CB
,
Y
};
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
begin
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Y1_product
<=
0
;
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Y2_product
<=
0
;
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Y3_product
<=
0
;
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CB1_product
<=
0
;
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CB2_product
<=
0
;
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CB3_product
<=
0
;
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CR1_product
<=
0
;
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CR2_product
<=
0
;
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CR3_product
<=
0
;
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Y_temp
<=
0
;
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CB_temp
<=
0
;
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CR_temp
<=
0
;
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end
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else
if
(
enable
)
begin
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Y1_product
<=
Y1
*
data_in
[
7
:
0
];
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Y2_product
<=
Y2
*
data_in
[
15
:
8
];
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Y3_product
<=
Y3
*
data_in
[
23
:
16
];
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CB1_product
<=
CB1
*
data_in
[
7
:
0
];
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CB2_product
<=
CB2
*
data_in
[
15
:
8
];
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CB3_product
<=
CB3
*
data_in
[
23
:
16
];
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CR1_product
<=
CR1
*
data_in
[
7
:
0
];
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CR2_product
<=
CR2
*
data_in
[
15
:
8
];
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CR3_product
<=
CR3
*
data_in
[
23
:
16
];
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Y_temp
<=
Y1_product
+
Y2_product
+
Y3_product
;
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CB_temp
<=
22'd2097152
-
CB1_product
-
CB2_product
+
CB3_product
;
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CR_temp
<=
22'd2097152
+
CR1_product
-
CR2_product
-
CR3_product
;
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end
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end
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/* Rounding of Y, CB, CR requires looking at bit 13. If there is a '1' in bit 13,
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then the value in bits [21:14] needs to be rounded up by adding 1 to the value
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in those bits **/
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
begin
110
Y
<=
0
;
111
CB
<=
0
;
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CR
<=
0
;
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end
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else
if
(
enable
)
begin
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Y
<=
Y_temp
[
13
] ?
Y_temp
[
21
:
14
] +
1
:
Y_temp
[
21
:
14
];
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CB
<=
CB_temp
[
13
] & (
CB_temp
[
21
:
14
] !=
8'd255
) ?
CB_temp
[
21
:
14
] +
1
:
CB_temp
[
21
:
14
];
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CR
<=
CR_temp
[
13
] & (
CR_temp
[
21
:
14
] !=
8'd255
) ?
CR_temp
[
21
:
14
] +
1
:
CR_temp
[
21
:
14
];
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// Need to avoid rounding if the value in the top 8 bits is 255, otherwise
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// the value would rollover from 255 to 0
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end
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end
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always
@(
posedge
clk
)
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begin
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if
(
rst
)
begin
127
enable_1
<=
0
;
128
enable_2
<=
0
;
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enable_out
<=
0
;
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end
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else
begin
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enable_1
<=
enable
;
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enable_2
<=
enable_1
;
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enable_out
<=
enable_2
;
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end
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end
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endmodule
RGB2YCBCR.3433CR1
3433CR1wire[13:0]
Definition:
rgb2ycbcr.v:60
RGB2YCBCR.3451enable_1
3451enable_1reg
Definition:
rgb2ycbcr.v:68
RGB2YCBCR.3424data_in
[23:0] 3424data_in
Definition:
rgb2ycbcr.v:49
RGB2YCBCR.3438CR_temp
3438CR_tempreg[21:0]
Definition:
rgb2ycbcr.v:63
RGB2YCBCR.3447CR3_product
3447CR3_productreg[21:0]
Definition:
rgb2ycbcr.v:66
RGB2YCBCR.3448Y
3448Yreg[7:0]
Definition:
rgb2ycbcr.v:67
RGB2YCBCR.3439Y1_product
3439Y1_productreg[21:0]
Definition:
rgb2ycbcr.v:64
RGB2YCBCR.3444CB3_product
3444CB3_productreg[21:0]
Definition:
rgb2ycbcr.v:65
RGB2YCBCR.3437CB_temp
3437CB_tempreg[21:0]
Definition:
rgb2ycbcr.v:63
RGB2YCBCR.3436Y_temp
3436Y_tempreg[21:0]
Definition:
rgb2ycbcr.v:63
RGB2YCBCR.3428Y2
3428Y2wire[13:0]
Definition:
rgb2ycbcr.v:55
RGB2YCBCR.3440Y2_product
3440Y2_productreg[21:0]
Definition:
rgb2ycbcr.v:64
RGB2YCBCR.3445CR1_product
3445CR1_productreg[21:0]
Definition:
rgb2ycbcr.v:66
RGB2YCBCR.3441Y3_product
3441Y3_productreg[21:0]
Definition:
rgb2ycbcr.v:64
RGB2YCBCR.3432CB3
3432CB3wire[13:0]
Definition:
rgb2ycbcr.v:59
RGB2YCBCR
Definition:
rgb2ycbcr.v:44
RGB2YCBCR.3422rst
3422rst
Definition:
rgb2ycbcr.v:47
RGB2YCBCR.3442CB1_product
3442CB1_productreg[21:0]
Definition:
rgb2ycbcr.v:65
RGB2YCBCR.3429Y3
3429Y3wire[13:0]
Definition:
rgb2ycbcr.v:56
RGB2YCBCR.3446CR2_product
3446CR2_productreg[21:0]
Definition:
rgb2ycbcr.v:66
RGB2YCBCR.3434CR2
3434CR2wire[13:0]
Definition:
rgb2ycbcr.v:61
RGB2YCBCR.3427Y1
3427Y1wire[13:0]
Definition:
rgb2ycbcr.v:54
RGB2YCBCR.3431CB2
3431CB2wire[13:0]
Definition:
rgb2ycbcr.v:58
RGB2YCBCR.3430CB1
3430CB1wire[13:0]
Definition:
rgb2ycbcr.v:57
RGB2YCBCR.3452enable_2
3452enable_2reg
Definition:
rgb2ycbcr.v:68
RGB2YCBCR.3454data_out
3454data_outwire[23:0]
Definition:
rgb2ycbcr.v:69
RGB2YCBCR.3435CR3
3435CR3wire[13:0]
Definition:
rgb2ycbcr.v:62
RGB2YCBCR.3421clk
3421clk
Definition:
rgb2ycbcr.v:46
RGB2YCBCR.3423enable
3423enable
Definition:
rgb2ycbcr.v:48
RGB2YCBCR.3450CR
3450CRreg[7:0]
Definition:
rgb2ycbcr.v:67
RGB2YCBCR.3449CB
3449CBreg[7:0]
Definition:
rgb2ycbcr.v:67
RGB2YCBCR.3443CB2_product
3443CB2_productreg[21:0]
Definition:
rgb2ycbcr.v:65
RGB2YCBCR.3453enable_out
3453enable_outreg
Definition:
rgb2ycbcr.v:68
code
rgb2ycbcr.v
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