oc_jpegencode  1.0
JPEGencoder
y_dct.v
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1 /////////////////////////////////////////////////////////////////////
2 //// ////
3 //// JPEG Encoder Core - Verilog ////
4 //// ////
5 //// Author: David Lundgren ////
6 //// davidklun@gmail.com ////
7 //// ////
8 /////////////////////////////////////////////////////////////////////
9 //// ////
10 //// Copyright (C) 2009 David Lundgren ////
11 //// davidklun@gmail.com ////
12 //// ////
13 //// This source file may be used and distributed without ////
14 //// restriction provided that this copyright statement is not ////
15 //// removed from the file and that any derivative work contains ////
16 //// the original copyright notice and the associated disclaimer.////
17 //// ////
18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
30 //// POSSIBILITY OF SUCH DAMAGE. ////
31 //// ////
32 /////////////////////////////////////////////////////////////////////
33 
34 /* This module converts the incoming Y data.
35 The incoming data is unsigned 8 bits, so the data is in the range of 0-255
36 Unlike a typical DCT, the data is not subtracted by 128 to center it around 0.
37 It is only required for the first row, and instead of subtracting 128 from each
38 pixel value, a total value can be subtracted at the end of the first row/column multiply,
39 involving the 8 pixel values and the 8 DCT matrix values.
40 For the other 7 rows of the DCT matrix, the values in each row add up to 0,
41 so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value.
42 Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values
43 by the 8x8 DCT matrix. **/
44 
45 `timescale 1ns / 100ps
46 
57 input clk;
58 input rst;
59 input enable;
60 input [7:0] data_in;
78 
79 
80 integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52;
82 
83 reg [24:0] Y_temp_11;
84 reg [24:0] Y11, Y21, Y31, Y41, Y51, Y61, Y71, Y81, Y11_final;
103 reg [26:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18;
104 reg [26:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28;
105 reg [26:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
106 reg [26:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48;
107 reg [26:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58;
108 reg [26:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
109 reg [26:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78;
110 reg [26:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88;
140 reg [2:0] count;
144 reg [7:0] data_1;
149 
150 always @(posedge clk)
151 begin // DCT matrix entries
152  T1 = 5793; // .3536
153  T21 = 8035; // .4904
154  T22 = 6811; // .4157
155  T23 = 4551; // .2778
156  T24 = 1598; // .0975
157  T25 = -1598; // -.0975
158  T26 = -4551; // -.2778
159  T27 = -6811; // -.4157
160  T28 = -8035; // -.4904
161  T31 = 7568; // .4619
162  T32 = 3135; // .1913
163  T33 = -3135; // -.1913
164  T34 = -7568; // -.4619
165  T52 = -5793; // -.3536
166 end
167 
168 always @(posedge clk)
169 begin // The inverse DCT matrix entries
170  Ti1 = 5793; // .3536
171  Ti21 = 8035; // .4904
172  Ti22 = 6811; // .4157
173  Ti23 = 4551; // .2778
174  Ti24 = 1598; // .0975
175  Ti25 = -1598; // -.0975
176  Ti26 = -4551; // -.2778
177  Ti27 = -6811; // -.4157
178  Ti28 = -8035; // -.4904
179  Ti31 = 7568; // .4619
180  Ti32 = 3135; // .1913
181  Ti33 = -3135; // -.1913
182  Ti34 = -7568; // -.4619
183  Ti52 = -5793; // -.3536
184 end
185 
186 always @(posedge clk)
187 begin
188  if (rst) begin
189  Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0;
190  Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0;
191  Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0;
192  Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0;
193  Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0;
194  Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0;
195  Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0;
196  Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0;
197  Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0;
198  Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0;
199  Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0;
200  Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0;
201  Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0;
202  Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0;
203  Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0;
204  Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0;
205  end
206  else if (enable_1 & count_8) begin
239  end
240 end
241 
242 always @(posedge clk)
243 begin
244  if (rst) begin
245  Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
246  Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
247  Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
248  Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
249  Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
250  Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
251  Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
252  Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
253  end
254  else if (count_8 & count_of == 1) begin
255  Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0;
256  Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
257  Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0;
258  Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
259  Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0;
260  Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
261  Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0;
262  Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
263  Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0;
264  Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
265  Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0;
266  Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
267  Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0;
268  Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
269  Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0;
270  Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
271  end
272  else if (enable & count_9) begin
273  Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14;
274  Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18;
275  Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24;
276  Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28;
277  Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34;
278  Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38;
279  Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44;
280  Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48;
281  Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54;
282  Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58;
283  Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64;
284  Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68;
285  Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74;
286  Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78;
287  Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84;
288  Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88;
289  end
290 end
291 
292 always @(posedge clk)
293 begin
294  if (rst) begin
295  Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0;
296  Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0;
297  Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0;
298  Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0;
299  Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0;
300  Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0;
301  Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0;
302  Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0;
303  Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0;
304  Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0;
305  Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0;
306  Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0;
307  Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0;
308  Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0;
309  Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0;
310  Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0;
311  end
312  else if (count_10 & count_of == 0) begin
313  Z11_final <= Z11[15] ? Z11[26:16] + 1 : Z11[26:16];
314  Z12_final <= Z12[15] ? Z12[26:16] + 1 : Z12[26:16];
315  Z13_final <= Z13[15] ? Z13[26:16] + 1 : Z13[26:16];
316  Z14_final <= Z14[15] ? Z14[26:16] + 1 : Z14[26:16];
317  Z15_final <= Z15[15] ? Z15[26:16] + 1 : Z15[26:16];
318  Z16_final <= Z16[15] ? Z16[26:16] + 1 : Z16[26:16];
319  Z17_final <= Z17[15] ? Z17[26:16] + 1 : Z17[26:16];
320  Z18_final <= Z18[15] ? Z18[26:16] + 1 : Z18[26:16];
321  Z21_final <= Z21[15] ? Z21[26:16] + 1 : Z21[26:16];
322  Z22_final <= Z22[15] ? Z22[26:16] + 1 : Z22[26:16];
323  Z23_final <= Z23[15] ? Z23[26:16] + 1 : Z23[26:16];
324  Z24_final <= Z24[15] ? Z24[26:16] + 1 : Z24[26:16];
325  Z25_final <= Z25[15] ? Z25[26:16] + 1 : Z25[26:16];
326  Z26_final <= Z26[15] ? Z26[26:16] + 1 : Z26[26:16];
327  Z27_final <= Z27[15] ? Z27[26:16] + 1 : Z27[26:16];
328  Z28_final <= Z28[15] ? Z28[26:16] + 1 : Z28[26:16];
329  Z31_final <= Z31[15] ? Z31[26:16] + 1 : Z31[26:16];
330  Z32_final <= Z32[15] ? Z32[26:16] + 1 : Z32[26:16];
331  Z33_final <= Z33[15] ? Z33[26:16] + 1 : Z33[26:16];
332  Z34_final <= Z34[15] ? Z34[26:16] + 1 : Z34[26:16];
333  Z35_final <= Z35[15] ? Z35[26:16] + 1 : Z35[26:16];
334  Z36_final <= Z36[15] ? Z36[26:16] + 1 : Z36[26:16];
335  Z37_final <= Z37[15] ? Z37[26:16] + 1 : Z37[26:16];
336  Z38_final <= Z38[15] ? Z38[26:16] + 1 : Z38[26:16];
337  Z41_final <= Z41[15] ? Z41[26:16] + 1 : Z41[26:16];
338  Z42_final <= Z42[15] ? Z42[26:16] + 1 : Z42[26:16];
339  Z43_final <= Z43[15] ? Z43[26:16] + 1 : Z43[26:16];
340  Z44_final <= Z44[15] ? Z44[26:16] + 1 : Z44[26:16];
341  Z45_final <= Z45[15] ? Z45[26:16] + 1 : Z45[26:16];
342  Z46_final <= Z46[15] ? Z46[26:16] + 1 : Z46[26:16];
343  Z47_final <= Z47[15] ? Z47[26:16] + 1 : Z47[26:16];
344  Z48_final <= Z48[15] ? Z48[26:16] + 1 : Z48[26:16];
345  Z51_final <= Z51[15] ? Z51[26:16] + 1 : Z51[26:16];
346  Z52_final <= Z52[15] ? Z52[26:16] + 1 : Z52[26:16];
347  Z53_final <= Z53[15] ? Z53[26:16] + 1 : Z53[26:16];
348  Z54_final <= Z54[15] ? Z54[26:16] + 1 : Z54[26:16];
349  Z55_final <= Z55[15] ? Z55[26:16] + 1 : Z55[26:16];
350  Z56_final <= Z56[15] ? Z56[26:16] + 1 : Z56[26:16];
351  Z57_final <= Z57[15] ? Z57[26:16] + 1 : Z57[26:16];
352  Z58_final <= Z58[15] ? Z58[26:16] + 1 : Z58[26:16];
353  Z61_final <= Z61[15] ? Z61[26:16] + 1 : Z61[26:16];
354  Z62_final <= Z62[15] ? Z62[26:16] + 1 : Z62[26:16];
355  Z63_final <= Z63[15] ? Z63[26:16] + 1 : Z63[26:16];
356  Z64_final <= Z64[15] ? Z64[26:16] + 1 : Z64[26:16];
357  Z65_final <= Z65[15] ? Z65[26:16] + 1 : Z65[26:16];
358  Z66_final <= Z66[15] ? Z66[26:16] + 1 : Z66[26:16];
359  Z67_final <= Z67[15] ? Z67[26:16] + 1 : Z67[26:16];
360  Z68_final <= Z68[15] ? Z68[26:16] + 1 : Z68[26:16];
361  Z71_final <= Z71[15] ? Z71[26:16] + 1 : Z71[26:16];
362  Z72_final <= Z72[15] ? Z72[26:16] + 1 : Z72[26:16];
363  Z73_final <= Z73[15] ? Z73[26:16] + 1 : Z73[26:16];
364  Z74_final <= Z74[15] ? Z74[26:16] + 1 : Z74[26:16];
365  Z75_final <= Z75[15] ? Z75[26:16] + 1 : Z75[26:16];
366  Z76_final <= Z76[15] ? Z76[26:16] + 1 : Z76[26:16];
367  Z77_final <= Z77[15] ? Z77[26:16] + 1 : Z77[26:16];
368  Z78_final <= Z78[15] ? Z78[26:16] + 1 : Z78[26:16];
369  Z81_final <= Z81[15] ? Z81[26:16] + 1 : Z81[26:16];
370  Z82_final <= Z82[15] ? Z82[26:16] + 1 : Z82[26:16];
371  Z83_final <= Z83[15] ? Z83[26:16] + 1 : Z83[26:16];
372  Z84_final <= Z84[15] ? Z84[26:16] + 1 : Z84[26:16];
373  Z85_final <= Z85[15] ? Z85[26:16] + 1 : Z85[26:16];
374  Z86_final <= Z86[15] ? Z86[26:16] + 1 : Z86[26:16];
375  Z87_final <= Z87[15] ? Z87[26:16] + 1 : Z87[26:16];
376  Z88_final <= Z88[15] ? Z88[26:16] + 1 : Z88[26:16];
377  end
378 end
379 
380 // output_enable signals the next block, the quantizer, that the input data is ready
381 always @(posedge clk)
382 begin
383  if (rst)
384  output_enable <= 0;
385  else if (!enable_1)
386  output_enable <= 0;
387  else if (count_10 == 0 | count_of)
388  output_enable <= 0;
389  else if (count_10 & count_of == 0)
390  output_enable <= 1;
391 end
392 always @(posedge clk)
393 begin
394  if (rst)
395  Y_temp_11 <= 0;
396  else if (enable)
397  Y_temp_11 <= data_in * T1;
398 end
399 
400 always @(posedge clk)
401 begin
402  if (rst)
403  Y11 <= 0;
404  else if (count == 1 & enable == 1)
405  Y11 <= Y_temp_11;
406  else if (enable)
407  Y11 <= Y_temp_11 + Y11;
408 end
409 
410 always @(posedge clk)
411 begin
412  if (rst) begin
413  Y_temp_21 <= 0;
414  Y_temp_31 <= 0;
415  Y_temp_41 <= 0;
416  Y_temp_51 <= 0;
417  Y_temp_61 <= 0;
418  Y_temp_71 <= 0;
419  Y_temp_81 <= 0;
420  end
421  else if (!enable_1) begin
422  Y_temp_21 <= 0;
423  Y_temp_31 <= 0;
424  Y_temp_41 <= 0;
425  Y_temp_51 <= 0;
426  Y_temp_61 <= 0;
427  Y_temp_71 <= 0;
428  Y_temp_81 <= 0;
429  end
430  else if (enable_1) begin
438  end
439 end
440 
441 always @(posedge clk)
442 begin
443  if (rst) begin
444  Y21 <= 0;
445  Y31 <= 0;
446  Y41 <= 0;
447  Y51 <= 0;
448  Y61 <= 0;
449  Y71 <= 0;
450  Y81 <= 0;
451  end
452  else if (!enable_1) begin
453  Y21 <= 0;
454  Y31 <= 0;
455  Y41 <= 0;
456  Y51 <= 0;
457  Y61 <= 0;
458  Y71 <= 0;
459  Y81 <= 0;
460  end
461  else if (enable_1) begin
462  Y21 <= Y_temp_21 + Y21;
463  Y31 <= Y_temp_31 + Y31;
464  Y41 <= Y_temp_41 + Y41;
465  Y51 <= Y_temp_51 + Y51;
466  Y61 <= Y_temp_61 + Y61;
467  Y71 <= Y_temp_71 + Y71;
468  Y81 <= Y_temp_81 + Y81;
469  end
470 end
471 
472 always @(posedge clk)
473 begin
474  if (rst) begin
475  count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
476  count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
477  count_10 <= 0;
478  end
479  else if (!enable) begin
480  count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
481  count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
482  count_10 <= 0;
483  end
484  else if (enable) begin
485  count <= count + 1; count_3 <= count_1; count_4 <= count_3;
488  end
489 end
490 
491 always @(posedge clk)
492 begin
493  if (rst) begin
494  count_1 <= 0;
495  end
496  else if (count != 7 | !enable) begin
497  count_1 <= 0;
498  end
499  else if (count == 7) begin
500  count_1 <= 1;
501  end
502 end
503 
504 always @(posedge clk)
505 begin
506  if (rst) begin
507  count_of <= 0;
508  count_of_copy <= 0;
509  end
510  else if (!enable) begin
511  count_of <= 0;
512  count_of_copy <= 0;
513  end
514  else if (count_1 == 1) begin
515  count_of <= count_of + 1;
517  end
518 end
519 
520 always @(posedge clk)
521 begin
522  if (rst) begin
523  Y11_final <= 0;
524  end
525  else if (count_3 & enable_1) begin
526  Y11_final <= Y11 - 25'd5932032;
527  /* The Y values weren't centered on 0 before doing the DCT
528  128 needs to be subtracted from each Y value before, or in this
529  case, 362 is subtracted from the total, because this is the
530  total obtained by subtracting 128 from each element
531  and then multiplying by the weight
532  assigned by the DCT matrix : 128*8*5793 = 5932032
533  This is only needed for the first row, the values in the rest of
534  the rows add up to 0 **/
535  end
536 end
537 
538 
539 always @(posedge clk)
540 begin
541  if (rst) begin
542  Y21_final <= 0; Y21_final_prev <= 0;
543  Y31_final <= 0; Y31_final_prev <= 0;
544  Y41_final <= 0; Y41_final_prev <= 0;
545  Y51_final <= 0; Y51_final_prev <= 0;
546  Y61_final <= 0; Y61_final_prev <= 0;
547  Y71_final <= 0; Y71_final_prev <= 0;
548  Y81_final <= 0; Y81_final_prev <= 0;
549  end
550  else if (!enable_1) begin
551  Y21_final <= 0; Y21_final_prev <= 0;
552  Y31_final <= 0; Y31_final_prev <= 0;
553  Y41_final <= 0; Y41_final_prev <= 0;
554  Y51_final <= 0; Y51_final_prev <= 0;
555  Y61_final <= 0; Y61_final_prev <= 0;
556  Y71_final <= 0; Y71_final_prev <= 0;
557  Y81_final <= 0; Y81_final_prev <= 0;
558  end
559  else if (count_4 & enable_1) begin
567  end
568 end
569 
570 always @(posedge clk)
571 begin
572  if (rst) begin
573  Y21_final_diff <= 0; Y31_final_diff <= 0;
574  Y41_final_diff <= 0; Y51_final_diff <= 0;
575  Y61_final_diff <= 0; Y71_final_diff <= 0;
576  Y81_final_diff <= 0;
577  end
578  else if (count_5 & enable_1) begin
586  end
587 end
588 always @(posedge clk)
589 begin
590  case (count)
591  3'b000: Y2_mul_input <= T21;
592  3'b001: Y2_mul_input <= T22;
593  3'b010: Y2_mul_input <= T23;
594  3'b011: Y2_mul_input <= T24;
595  3'b100: Y2_mul_input <= T25;
596  3'b101: Y2_mul_input <= T26;
597  3'b110: Y2_mul_input <= T27;
598  3'b111: Y2_mul_input <= T28;
599  endcase
600 end
601 
602 always @(posedge clk)
603 begin
604  case (count)
605  3'b000: Y3_mul_input <= T31;
606  3'b001: Y3_mul_input <= T32;
607  3'b010: Y3_mul_input <= T33;
608  3'b011: Y3_mul_input <= T34;
609  3'b100: Y3_mul_input <= T34;
610  3'b101: Y3_mul_input <= T33;
611  3'b110: Y3_mul_input <= T32;
612  3'b111: Y3_mul_input <= T31;
613  endcase
614 end
615 
616 always @(posedge clk)
617 begin
618  case (count)
619  3'b000: Y4_mul_input <= T22;
620  3'b001: Y4_mul_input <= T25;
621  3'b010: Y4_mul_input <= T28;
622  3'b011: Y4_mul_input <= T26;
623  3'b100: Y4_mul_input <= T23;
624  3'b101: Y4_mul_input <= T21;
625  3'b110: Y4_mul_input <= T24;
626  3'b111: Y4_mul_input <= T27;
627  endcase
628 end
629 
630 always @(posedge clk)
631 begin
632  case (count)
633  3'b000: Y5_mul_input <= T1;
634  3'b001: Y5_mul_input <= T52;
635  3'b010: Y5_mul_input <= T52;
636  3'b011: Y5_mul_input <= T1;
637  3'b100: Y5_mul_input <= T1;
638  3'b101: Y5_mul_input <= T52;
639  3'b110: Y5_mul_input <= T52;
640  3'b111: Y5_mul_input <= T1;
641  endcase
642 end
643 
644 always @(posedge clk)
645 begin
646  case (count)
647  3'b000: Y6_mul_input <= T23;
648  3'b001: Y6_mul_input <= T28;
649  3'b010: Y6_mul_input <= T24;
650  3'b011: Y6_mul_input <= T22;
651  3'b100: Y6_mul_input <= T27;
652  3'b101: Y6_mul_input <= T25;
653  3'b110: Y6_mul_input <= T21;
654  3'b111: Y6_mul_input <= T26;
655  endcase
656 end
657 
658 always @(posedge clk)
659 begin
660  case (count)
661  3'b000: Y7_mul_input <= T32;
662  3'b001: Y7_mul_input <= T34;
663  3'b010: Y7_mul_input <= T31;
664  3'b011: Y7_mul_input <= T33;
665  3'b100: Y7_mul_input <= T33;
666  3'b101: Y7_mul_input <= T31;
667  3'b110: Y7_mul_input <= T34;
668  3'b111: Y7_mul_input <= T32;
669  endcase
670 end
671 
672 always @(posedge clk)
673 begin
674  case (count)
675  3'b000: Y8_mul_input <= T24;
676  3'b001: Y8_mul_input <= T26;
677  3'b010: Y8_mul_input <= T22;
678  3'b011: Y8_mul_input <= T28;
679  3'b100: Y8_mul_input <= T21;
680  3'b101: Y8_mul_input <= T27;
681  3'b110: Y8_mul_input <= T23;
682  3'b111: Y8_mul_input <= T25;
683  endcase
684 end
685 
686 // Inverse DCT matrix entries
687 always @(posedge clk)
688 begin
689  case (count_of_copy)
690  3'b000: Ti2_mul_input <= Ti28;
691  3'b001: Ti2_mul_input <= Ti21;
692  3'b010: Ti2_mul_input <= Ti22;
693  3'b011: Ti2_mul_input <= Ti23;
694  3'b100: Ti2_mul_input <= Ti24;
695  3'b101: Ti2_mul_input <= Ti25;
696  3'b110: Ti2_mul_input <= Ti26;
697  3'b111: Ti2_mul_input <= Ti27;
698  endcase
699 end
700 
701 always @(posedge clk)
702 begin
703  case (count_of_copy)
704  3'b000: Ti3_mul_input <= Ti31;
705  3'b001: Ti3_mul_input <= Ti31;
706  3'b010: Ti3_mul_input <= Ti32;
707  3'b011: Ti3_mul_input <= Ti33;
708  3'b100: Ti3_mul_input <= Ti34;
709  3'b101: Ti3_mul_input <= Ti34;
710  3'b110: Ti3_mul_input <= Ti33;
711  3'b111: Ti3_mul_input <= Ti32;
712  endcase
713 end
714 
715 always @(posedge clk)
716 begin
717  case (count_of_copy)
718  3'b000: Ti4_mul_input <= Ti27;
719  3'b001: Ti4_mul_input <= Ti22;
720  3'b010: Ti4_mul_input <= Ti25;
721  3'b011: Ti4_mul_input <= Ti28;
722  3'b100: Ti4_mul_input <= Ti26;
723  3'b101: Ti4_mul_input <= Ti23;
724  3'b110: Ti4_mul_input <= Ti21;
725  3'b111: Ti4_mul_input <= Ti24;
726  endcase
727 end
728 
729 always @(posedge clk)
730 begin
731  case (count_of_copy)
732  3'b000: Ti5_mul_input <= Ti1;
733  3'b001: Ti5_mul_input <= Ti1;
734  3'b010: Ti5_mul_input <= Ti52;
735  3'b011: Ti5_mul_input <= Ti52;
736  3'b100: Ti5_mul_input <= Ti1;
737  3'b101: Ti5_mul_input <= Ti1;
738  3'b110: Ti5_mul_input <= Ti52;
739  3'b111: Ti5_mul_input <= Ti52;
740  endcase
741 end
742 
743 always @(posedge clk)
744 begin
745  case (count_of_copy)
746  3'b000: Ti6_mul_input <= Ti26;
747  3'b001: Ti6_mul_input <= Ti23;
748  3'b010: Ti6_mul_input <= Ti28;
749  3'b011: Ti6_mul_input <= Ti24;
750  3'b100: Ti6_mul_input <= Ti22;
751  3'b101: Ti6_mul_input <= Ti27;
752  3'b110: Ti6_mul_input <= Ti25;
753  3'b111: Ti6_mul_input <= Ti21;
754  endcase
755 end
756 
757 always @(posedge clk)
758 begin
759  case (count_of_copy)
760  3'b000: Ti7_mul_input <= Ti32;
761  3'b001: Ti7_mul_input <= Ti32;
762  3'b010: Ti7_mul_input <= Ti34;
763  3'b011: Ti7_mul_input <= Ti31;
764  3'b100: Ti7_mul_input <= Ti33;
765  3'b101: Ti7_mul_input <= Ti33;
766  3'b110: Ti7_mul_input <= Ti31;
767  3'b111: Ti7_mul_input <= Ti34;
768  endcase
769 end
770 
771 always @(posedge clk)
772 begin
773  case (count_of_copy)
774  3'b000: Ti8_mul_input <= Ti25;
775  3'b001: Ti8_mul_input <= Ti24;
776  3'b010: Ti8_mul_input <= Ti26;
777  3'b011: Ti8_mul_input <= Ti22;
778  3'b100: Ti8_mul_input <= Ti28;
779  3'b101: Ti8_mul_input <= Ti21;
780  3'b110: Ti8_mul_input <= Ti27;
781  3'b111: Ti8_mul_input <= Ti23;
782  endcase
783 end
784 
785 // Rounding stage
786 always @(posedge clk)
787 begin
788  if (rst) begin
789  data_1 <= 0;
790  Y11_final_1 <= 0; Y21_final_1 <= 0; Y31_final_1 <= 0; Y41_final_1 <= 0;
791  Y51_final_1 <= 0; Y61_final_1 <= 0; Y71_final_1 <= 0; Y81_final_1 <= 0;
792  Y11_final_2 <= 0; Y21_final_2 <= 0; Y31_final_2 <= 0; Y41_final_2 <= 0;
793  Y51_final_2 <= 0; Y61_final_2 <= 0; Y71_final_2 <= 0; Y81_final_2 <= 0;
794  Y11_final_3 <= 0; Y11_final_4 <= 0;
795  end
796  else if (enable) begin
797  data_1 <= data_in;
798  Y11_final_1 <= Y11_final[11] ? Y11_final[24:12] + 1 : Y11_final[24:12];
799  Y11_final_2[31:13] <= Y11_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
800  Y11_final_2[12:0] <= Y11_final_1;
801  // Need to sign extend Y11_final_1 and the other registers to store a negative
802  // number as a twos complement number. If you don't sign extend, then a negative number
803  // will be stored incorrectly as a positive number. For example, -215 would be stored
804  // as 1833 without sign extending
807  Y21_final_1 <= Y21_final_diff[11] ? Y21_final_diff[24:12] + 1 : Y21_final_diff[24:12];
808  Y21_final_2[31:13] <= Y21_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
809  Y21_final_2[12:0] <= Y21_final_1;
810  Y31_final_1 <= Y31_final_diff[11] ? Y31_final_diff[24:12] + 1 : Y31_final_diff[24:12];
811  Y31_final_2[31:13] <= Y31_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
812  Y31_final_2[12:0] <= Y31_final_1;
813  Y41_final_1 <= Y41_final_diff[11] ? Y41_final_diff[24:12] + 1 : Y41_final_diff[24:12];
814  Y41_final_2[31:13] <= Y41_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
815  Y41_final_2[12:0] <= Y41_final_1;
816  Y51_final_1 <= Y51_final_diff[11] ? Y51_final_diff[24:12] + 1 : Y51_final_diff[24:12];
817  Y51_final_2[31:13] <= Y51_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
818  Y51_final_2[12:0] <= Y51_final_1;
819  Y61_final_1 <= Y61_final_diff[11] ? Y61_final_diff[24:12] + 1 : Y61_final_diff[24:12];
820  Y61_final_2[31:13] <= Y61_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
821  Y61_final_2[12:0] <= Y61_final_1;
822  Y71_final_1 <= Y71_final_diff[11] ? Y71_final_diff[24:12] + 1 : Y71_final_diff[24:12];
823  Y71_final_2[31:13] <= Y71_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
824  Y71_final_2[12:0] <= Y71_final_1;
825  Y81_final_1 <= Y81_final_diff[11] ? Y81_final_diff[24:12] + 1 : Y81_final_diff[24:12];
826  Y81_final_2[31:13] <= Y81_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
827  Y81_final_2[12:0] <= Y81_final_1;
828  // The bit in place 11 is the fraction part, for rounding purposes
829  // if it is 1, then you need to add 1 to the bits in 24-12,
830  // if bit 11 is 0, then the bits in 24-12 won't change
831  end
832 end
833 
834 always @(posedge clk)
835 begin
836  if (rst) begin
837  enable_1 <= 0;
838  end
839  else begin
840  enable_1 <= enable;
841  end
842 end
843 
844 endmodule
3761Y51_final_prevreg[24:0]
Definition: y_dct.v:120
3588Y31reg[24:0]
Definition: y_dct.v:84
3858Ti5_mul_inputinteger
Definition: y_dct.v:147
3701Z54reg[26:0]
Definition: y_dct.v:107
3682Z31reg[26:0]
Definition: y_dct.v:105
3783Z27_finalreg[10:0]
Definition: y_dct.v:127
3693Z44reg[26:0]
Definition: y_dct.v:106
3824Z78_finalreg[10:0]
Definition: y_dct.v:137
3753Y71_finalreg[24:0]
Definition: y_dct.v:116
3631Z_temp_46reg[31:0]
Definition: y_dct.v:94
3490enable
Definition: y_dct.v:59
3828Z84_finalreg[10:0]
Definition: y_dct.v:138
3687Z36reg[26:0]
Definition: y_dct.v:105
3636Z_temp_53reg[31:0]
Definition: y_dct.v:95
3785Z31_finalreg[10:0]
Definition: y_dct.v:128
3678Z25reg[26:0]
Definition: y_dct.v:104
3671Z16reg[26:0]
Definition: y_dct.v:103
3557T1integer
Definition: y_dct.v:80
3592Y71reg[24:0]
Definition: y_dct.v:84
3794Z42_finalreg[10:0]
Definition: y_dct.v:130
3720Z77reg[26:0]
Definition: y_dct.v:109
3805Z55_finalreg[10:0]
Definition: y_dct.v:133
3674Z21reg[26:0]
Definition: y_dct.v:104
3816Z68_finalreg[10:0]
Definition: y_dct.v:135
3667Z12reg[26:0]
Definition: y_dct.v:103
3611Z_temp_22reg[31:0]
Definition: y_dct.v:89
3634Z_temp_51reg[31:0]
Definition: y_dct.v:95
3747Y81_final_1reg[12:0]
Definition: y_dct.v:114
3778Z22_finalreg[10:0]
Definition: y_dct.v:126
3650Z_temp_71reg[31:0]
Definition: y_dct.v:99
3638Z_temp_55reg[31:0]
Definition: y_dct.v:96
3725Z84reg[26:0]
Definition: y_dct.v:110
3577Ti26integer
Definition: y_dct.v:81
3647Z_temp_66reg[31:0]
Definition: y_dct.v:98
3690Z41reg[26:0]
Definition: y_dct.v:106
3575Ti24integer
Definition: y_dct.v:81
3630Z_temp_45reg[31:0]
Definition: y_dct.v:94
3729Z88reg[26:0]
Definition: y_dct.v:110
3719Z76reg[26:0]
Definition: y_dct.v:109
3561T24integer
Definition: y_dct.v:80
3608Z_temp_17reg[31:0]
Definition: y_dct.v:88
3591Y61reg[24:0]
Definition: y_dct.v:84
3704Z57reg[26:0]
Definition: y_dct.v:107
3857Ti4_mul_inputinteger
Definition: y_dct.v:147
3751Y51_finalreg[24:0]
Definition: y_dct.v:115
3845count_9reg
Definition: y_dct.v:143
3809Z61_finalreg[10:0]
Definition: y_dct.v:134
3609Z_temp_18reg[31:0]
Definition: y_dct.v:88
3604Z_temp_13reg[31:0]
Definition: y_dct.v:87
3815Z67_finalreg[10:0]
Definition: y_dct.v:135
3651Z_temp_72reg[31:0]
Definition: y_dct.v:99
3580Ti31integer
Definition: y_dct.v:81
3796Z44_finalreg[10:0]
Definition: y_dct.v:130
3713Z68reg[26:0]
Definition: y_dct.v:108
3768Y81_final_diffreg[24:0]
Definition: y_dct.v:123
3639Z_temp_56reg[31:0]
Definition: y_dct.v:96
3605Z_temp_14reg[31:0]
Definition: y_dct.v:87
3689Z38reg[26:0]
Definition: y_dct.v:105
3736Y51_final_2reg[31:0]
Definition: y_dct.v:112
3797Z45_finalreg[10:0]
Definition: y_dct.v:131
3610Z_temp_21reg[31:0]
Definition: y_dct.v:89
3603Z_temp_12reg[31:0]
Definition: y_dct.v:87
3755Y21_final_prevreg[24:0]
Definition: y_dct.v:117
3618Z_temp_31reg[31:0]
Definition: y_dct.v:91
3695Z46reg[26:0]
Definition: y_dct.v:106
3706Z61reg[26:0]
Definition: y_dct.v:108
3617Z_temp_28reg[31:0]
Definition: y_dct.v:90
3560T23integer
Definition: y_dct.v:80
3663Z_temp_86reg[31:0]
Definition: y_dct.v:102
3625Z_temp_38reg[31:0]
Definition: y_dct.v:92
3570T52integer
Definition: y_dct.v:80
3628Z_temp_43reg[31:0]
Definition: y_dct.v:93
3757Y31_final_prevreg[24:0]
Definition: y_dct.v:118
3764Y61_final_diffreg[24:0]
Definition: y_dct.v:121
3844output_enablereg
Definition: y_dct.v:142
3703Z56reg[26:0]
Definition: y_dct.v:107
3699Z52reg[26:0]
Definition: y_dct.v:107
3819Z73_finalreg[10:0]
Definition: y_dct.v:136
3744Y51_final_1reg[12:0]
Definition: y_dct.v:114
3633Z_temp_48reg[31:0]
Definition: y_dct.v:94
3730Y11_final_2reg[31:0]
Definition: y_dct.v:111
3586Y11reg[24:0]
Definition: y_dct.v:84
3769Z11_finalreg[10:0]
Definition: y_dct.v:124
3660Z_temp_83reg[31:0]
Definition: y_dct.v:101
3677Z24reg[26:0]
Definition: y_dct.v:104
3632Z_temp_47reg[31:0]
Definition: y_dct.v:94
3795Z43_finalreg[10:0]
Definition: y_dct.v:130
3803Z53_finalreg[10:0]
Definition: y_dct.v:132
3615Z_temp_26reg[31:0]
Definition: y_dct.v:90
3793Z41_finalreg[10:0]
Definition: y_dct.v:130
3748Y21_finalreg[24:0]
Definition: y_dct.v:115
3581Ti32integer
Definition: y_dct.v:81
3488clk
Definition: y_dct.v:57
3837count_3reg
Definition: y_dct.v:142
3766Y71_final_diffreg[24:0]
Definition: y_dct.v:122
3817Z71_finalreg[10:0]
Definition: y_dct.v:136
3653Z_temp_74reg[31:0]
Definition: y_dct.v:99
3661Z_temp_84reg[31:0]
Definition: y_dct.v:101
3733Y11_final_4reg[31:0]
Definition: y_dct.v:111
3731Y21_final_2reg[31:0]
Definition: y_dct.v:111
3832Z88_finalreg[10:0]
Definition: y_dct.v:139
3573Ti22integer
Definition: y_dct.v:81
3813Z65_finalreg[10:0]
Definition: y_dct.v:135
3566T31integer
Definition: y_dct.v:80
3626Z_temp_41reg[31:0]
Definition: y_dct.v:93
3718Z75reg[26:0]
Definition: y_dct.v:109
3726Z85reg[26:0]
Definition: y_dct.v:110
3593Y81reg[24:0]
Definition: y_dct.v:84
3820Z74_finalreg[10:0]
Definition: y_dct.v:136
3597Y_temp_41reg[31:0]
Definition: y_dct.v:85
3567T32integer
Definition: y_dct.v:80
3721Z78reg[26:0]
Definition: y_dct.v:109
3684Z33reg[26:0]
Definition: y_dct.v:105
3594Y11_finalreg[24:0]
Definition: y_dct.v:84
3723Z82reg[26:0]
Definition: y_dct.v:110
3637Z_temp_54reg[31:0]
Definition: y_dct.v:95
3772Z14_finalreg[10:0]
Definition: y_dct.v:124
[7:0] 3491data_in
Definition: y_dct.v:60
3710Z65reg[26:0]
Definition: y_dct.v:108
3741Y21_final_1reg[12:0]
Definition: y_dct.v:113
3831Z87_finalreg[10:0]
Definition: y_dct.v:139
3666Z11reg[26:0]
Definition: y_dct.v:103
3750Y41_finalreg[24:0]
Definition: y_dct.v:115
3582Ti33integer
Definition: y_dct.v:81
3800Z48_finalreg[10:0]
Definition: y_dct.v:131
3771Z13_finalreg[10:0]
Definition: y_dct.v:124
3607Z_temp_16reg[31:0]
Definition: y_dct.v:88
3839count_5reg
Definition: y_dct.v:142
3834count_ofreg[2:0]
Definition: y_dct.v:141
3602Z_temp_11reg[31:0]
Definition: y_dct.v:87
3727Z86reg[26:0]
Definition: y_dct.v:110
3763Y61_final_prevreg[24:0]
Definition: y_dct.v:121
3846count_10reg
Definition: y_dct.v:143
3680Z27reg[26:0]
Definition: y_dct.v:104
3850Y4_mul_inputinteger
Definition: y_dct.v:145
3853Y7_mul_inputinteger
Definition: y_dct.v:146
3564T27integer
Definition: y_dct.v:80
3685Z34reg[26:0]
Definition: y_dct.v:105
3762Y51_final_diffreg[24:0]
Definition: y_dct.v:120
3601Y_temp_81reg[31:0]
Definition: y_dct.v:86
3810Z62_finalreg[10:0]
Definition: y_dct.v:134
3829Z85_finalreg[10:0]
Definition: y_dct.v:139
3673Z18reg[26:0]
Definition: y_dct.v:103
3656Z_temp_77reg[31:0]
Definition: y_dct.v:100
3732Y11_final_3reg[31:0]
Definition: y_dct.v:111
3746Y71_final_1reg[12:0]
Definition: y_dct.v:114
3861Ti8_mul_inputinteger
Definition: y_dct.v:148
3804Z54_finalreg[10:0]
Definition: y_dct.v:132
3579Ti28integer
Definition: y_dct.v:81
3692Z43reg[26:0]
Definition: y_dct.v:106
3668Z13reg[26:0]
Definition: y_dct.v:103
3760Y41_final_diffreg[24:0]
Definition: y_dct.v:119
3676Z23reg[26:0]
Definition: y_dct.v:104
3825Z81_finalreg[10:0]
Definition: y_dct.v:138
3799Z47_finalreg[10:0]
Definition: y_dct.v:131
3571Ti1integer
Definition: y_dct.v:81
3745Y61_final_1reg[12:0]
Definition: y_dct.v:114
3711Z66reg[26:0]
Definition: y_dct.v:108
3623Z_temp_36reg[31:0]
Definition: y_dct.v:92
3854Y8_mul_inputinteger
Definition: y_dct.v:146
3644Z_temp_63reg[31:0]
Definition: y_dct.v:97
3621Z_temp_34reg[31:0]
Definition: y_dct.v:91
3836count_1reg
Definition: y_dct.v:142
3613Z_temp_24reg[31:0]
Definition: y_dct.v:89
3585Y_temp_11reg[24:0]
Definition: y_dct.v:83
3696Z47reg[26:0]
Definition: y_dct.v:106
3563T26integer
Definition: y_dct.v:80
3489rst
Definition: y_dct.v:58
3728Z87reg[26:0]
Definition: y_dct.v:110
3620Z_temp_33reg[31:0]
Definition: y_dct.v:91
3847data_1reg[7:0]
Definition: y_dct.v:144
3700Z53reg[26:0]
Definition: y_dct.v:107
3738Y71_final_2reg[31:0]
Definition: y_dct.v:112
3724Z83reg[26:0]
Definition: y_dct.v:110
3848Y2_mul_inputinteger
Definition: y_dct.v:145
3835count_of_copyreg[2:0]
Definition: y_dct.v:141
3675Z22reg[26:0]
Definition: y_dct.v:104
3788Z34_finalreg[10:0]
Definition: y_dct.v:128
3739Y81_final_2reg[31:0]
Definition: y_dct.v:112
3812Z64_finalreg[10:0]
Definition: y_dct.v:134
3808Z58_finalreg[10:0]
Definition: y_dct.v:133
3712Z67reg[26:0]
Definition: y_dct.v:108
3572Ti21integer
Definition: y_dct.v:81
3702Z55reg[26:0]
Definition: y_dct.v:107
3627Z_temp_42reg[31:0]
Definition: y_dct.v:93
3688Z37reg[26:0]
Definition: y_dct.v:105
3787Z33_finalreg[10:0]
Definition: y_dct.v:128
3759Y41_final_prevreg[24:0]
Definition: y_dct.v:119
3622Z_temp_35reg[31:0]
Definition: y_dct.v:92
3658Z_temp_81reg[31:0]
Definition: y_dct.v:101
3641Z_temp_58reg[31:0]
Definition: y_dct.v:96
3697Z48reg[26:0]
Definition: y_dct.v:106
3614Z_temp_25reg[31:0]
Definition: y_dct.v:90
3558T21integer
Definition: y_dct.v:80
3743Y41_final_1reg[12:0]
Definition: y_dct.v:113
3740Y11_final_1reg[12:0]
Definition: y_dct.v:113
3649Z_temp_68reg[31:0]
Definition: y_dct.v:98
3645Z_temp_64reg[31:0]
Definition: y_dct.v:97
3811Z63_finalreg[10:0]
Definition: y_dct.v:134
3643Z_temp_62reg[31:0]
Definition: y_dct.v:97
3646Z_temp_65reg[31:0]
Definition: y_dct.v:98
3691Z42reg[26:0]
Definition: y_dct.v:106
3596Y_temp_31reg[31:0]
Definition: y_dct.v:85
3705Z58reg[26:0]
Definition: y_dct.v:107
3792Z38_finalreg[10:0]
Definition: y_dct.v:129
3576Ti25integer
Definition: y_dct.v:81
3802Z52_finalreg[10:0]
Definition: y_dct.v:132
3595Y_temp_21reg[31:0]
Definition: y_dct.v:85
3814Z66_finalreg[10:0]
Definition: y_dct.v:135
3859Ti6_mul_inputinteger
Definition: y_dct.v:148
3791Z37_finalreg[10:0]
Definition: y_dct.v:129
3587Y21reg[24:0]
Definition: y_dct.v:84
3657Z_temp_78reg[31:0]
Definition: y_dct.v:100
3672Z17reg[26:0]
Definition: y_dct.v:103
3600Y_temp_71reg[31:0]
Definition: y_dct.v:86
3642Z_temp_61reg[31:0]
Definition: y_dct.v:97
3851Y5_mul_inputinteger
Definition: y_dct.v:145
3780Z24_finalreg[10:0]
Definition: y_dct.v:126
3578Ti27integer
Definition: y_dct.v:81
3707Z62reg[26:0]
Definition: y_dct.v:108
3598Y_temp_51reg[31:0]
Definition: y_dct.v:85
3559T22integer
Definition: y_dct.v:80
3624Z_temp_37reg[31:0]
Definition: y_dct.v:92
3574Ti23integer
Definition: y_dct.v:81
3735Y41_final_2reg[31:0]
Definition: y_dct.v:111
3822Z76_finalreg[10:0]
Definition: y_dct.v:137
3670Z15reg[26:0]
Definition: y_dct.v:103
3562T25integer
Definition: y_dct.v:80
3749Y31_finalreg[24:0]
Definition: y_dct.v:115
3777Z21_finalreg[10:0]
Definition: y_dct.v:126
3659Z_temp_82reg[31:0]
Definition: y_dct.v:101
3855Ti2_mul_inputinteger
Definition: y_dct.v:147
3681Z28reg[26:0]
Definition: y_dct.v:104
3679Z26reg[26:0]
Definition: y_dct.v:104
3648Z_temp_67reg[31:0]
Definition: y_dct.v:98
3654Z_temp_75reg[31:0]
Definition: y_dct.v:100
3776Z18_finalreg[10:0]
Definition: y_dct.v:125
3734Y31_final_2reg[31:0]
Definition: y_dct.v:111
3569T34integer
Definition: y_dct.v:80
3589Y41reg[24:0]
Definition: y_dct.v:84
3606Z_temp_15reg[31:0]
Definition: y_dct.v:88
3860Ti7_mul_inputinteger
Definition: y_dct.v:148
3807Z57_finalreg[10:0]
Definition: y_dct.v:133
3770Z12_finalreg[10:0]
Definition: y_dct.v:124
3716Z73reg[26:0]
Definition: y_dct.v:109
3790Z36_finalreg[10:0]
Definition: y_dct.v:129
Definition: y_dct.v:47
3789Z35_finalreg[10:0]
Definition: y_dct.v:129
3665Z_temp_88reg[31:0]
Definition: y_dct.v:102
3782Z26_finalreg[10:0]
Definition: y_dct.v:127
3840count_6reg
Definition: y_dct.v:142
3849Y3_mul_inputinteger
Definition: y_dct.v:145
3826Z82_finalreg[10:0]
Definition: y_dct.v:138
3635Z_temp_52reg[31:0]
Definition: y_dct.v:95
3752Y61_finalreg[24:0]
Definition: y_dct.v:116
3781Z25_finalreg[10:0]
Definition: y_dct.v:127
3655Z_temp_76reg[31:0]
Definition: y_dct.v:100
3818Z72_finalreg[10:0]
Definition: y_dct.v:136
3737Y61_final_2reg[31:0]
Definition: y_dct.v:112
3823Z77_finalreg[10:0]
Definition: y_dct.v:137
3722Z81reg[26:0]
Definition: y_dct.v:110
3583Ti34integer
Definition: y_dct.v:81
3742Y31_final_1reg[12:0]
Definition: y_dct.v:113
3856Ti3_mul_inputinteger
Definition: y_dct.v:147
3714Z71reg[26:0]
Definition: y_dct.v:109
3852Y6_mul_inputinteger
Definition: y_dct.v:146
3821Z75_finalreg[10:0]
Definition: y_dct.v:137
3709Z64reg[26:0]
Definition: y_dct.v:108
3841count_7reg
Definition: y_dct.v:142
3774Z16_finalreg[10:0]
Definition: y_dct.v:125
3619Z_temp_32reg[31:0]
Definition: y_dct.v:91
3843enable_1reg
Definition: y_dct.v:142
3806Z56_finalreg[10:0]
Definition: y_dct.v:133
3698Z51reg[26:0]
Definition: y_dct.v:107
3773Z15_finalreg[10:0]
Definition: y_dct.v:125
3786Z32_finalreg[10:0]
Definition: y_dct.v:128
3754Y81_finalreg[24:0]
Definition: y_dct.v:116
3775Z17_finalreg[10:0]
Definition: y_dct.v:125
3568T33integer
Definition: y_dct.v:80
3629Z_temp_44reg[31:0]
Definition: y_dct.v:93
3664Z_temp_87reg[31:0]
Definition: y_dct.v:102
3708Z63reg[26:0]
Definition: y_dct.v:108
3758Y31_final_diffreg[24:0]
Definition: y_dct.v:118
3694Z45reg[26:0]
Definition: y_dct.v:106
3616Z_temp_27reg[31:0]
Definition: y_dct.v:90
3612Z_temp_23reg[31:0]
Definition: y_dct.v:89
3798Z46_finalreg[10:0]
Definition: y_dct.v:131
3779Z23_finalreg[10:0]
Definition: y_dct.v:126
3827Z83_finalreg[10:0]
Definition: y_dct.v:138
3565T28integer
Definition: y_dct.v:80
3640Z_temp_57reg[31:0]
Definition: y_dct.v:96
3590Y51reg[24:0]
Definition: y_dct.v:84
3784Z28_finalreg[10:0]
Definition: y_dct.v:127
3715Z72reg[26:0]
Definition: y_dct.v:109
3838count_4reg
Definition: y_dct.v:142
3767Y81_final_prevreg[24:0]
Definition: y_dct.v:123
3717Z74reg[26:0]
Definition: y_dct.v:109
3842count_8reg
Definition: y_dct.v:142
3599Y_temp_61reg[31:0]
Definition: y_dct.v:86
3765Y71_final_prevreg[24:0]
Definition: y_dct.v:122
3756Y21_final_diffreg[24:0]
Definition: y_dct.v:117
3686Z35reg[26:0]
Definition: y_dct.v:105
3801Z51_finalreg[10:0]
Definition: y_dct.v:132
3683Z32reg[26:0]
Definition: y_dct.v:105
3830Z86_finalreg[10:0]
Definition: y_dct.v:139
3662Z_temp_85reg[31:0]
Definition: y_dct.v:102
3833countreg[2:0]
Definition: y_dct.v:140
3584Ti52integer
Definition: y_dct.v:81
3669Z14reg[26:0]
Definition: y_dct.v:103
3652Z_temp_73reg[31:0]
Definition: y_dct.v:99