1 ///////////////////////////////////////////////////////////////////// 3 //// JPEG Encoder Core - Verilog //// 5 //// Author: David Lundgren //// 6 //// davidklun@gmail.com //// 8 ///////////////////////////////////////////////////////////////////// 10 //// Copyright (C) 2009 David Lundgren //// 11 //// davidklun@gmail.com //// 13 //// This source file may be used and distributed without //// 14 //// restriction provided that this copyright statement is not //// 15 //// removed from the file and that any derivative work contains //// 16 //// the original copyright notice and the associated disclaimer.//// 18 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 19 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 20 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 21 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 22 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 23 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 24 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 25 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 26 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 27 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 28 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 29 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 30 //// POSSIBILITY OF SUCH DAMAGE. //// 32 ///////////////////////////////////////////////////////////////////// 34 /* This module takes the y, cb, and cr inputs from the pre_fifo module, 35 and it combines the bits into the jpeg_bitstream. It uses 3 FIFO's to 36 write the y, cb, and cr data while it's processing the data. The output 37 of this module goes to the input of the ff_checker module, to check for 38 any FF's in the bitstream. 40 `timescale 1ns / 100ps
3351cb_bits_out2wire[31:0]
3366cr_JPEG_bitstream2wire[31:0]
3232end_of_block_outputwire
3221cb_JPEG_bitstreamwire[31:0]
3369cr_bits_outwire[31:0]
3249orc_reg_delayreg[4:0]
3223y_JPEG_bitstreamwire[31:0]
3349cr_bits_out2wire[31:0]
[31:0] 3409cb_JPEG_bitstream
3348cr_bits_out1wire[31:0]
3374cb_JPEG_bitstream1wire[31:0]
3365cr_JPEG_bitstream1wire[31:0]
3222cr_JPEG_bitstreamwire[31:0]
3350cb_bits_out1wire[31:0]
3346eob_early_out_enablereg
3274JPEG_bitstreamreg[31:0]
3375cb_JPEG_bitstream2wire[31:0]
[31:0] 3412y_JPEG_bitstream
3378cb_bits_outwire[31:0]
[31:0] 3406cr_JPEG_bitstream