oc_jpegencode
1.0
JPEGencoder
|
Static Public Member Functions |
Public Attributes |
Inputs | |
clk | |
rst | |
enable | |
Cb11 | [ 10 : 0 ] |
Cb12 | [ 10 : 0 ] |
Cb13 | [ 10 : 0 ] |
Cb14 | [ 10 : 0 ] |
Cb15 | [ 10 : 0 ] |
Cb16 | [ 10 : 0 ] |
Cb17 | [ 10 : 0 ] |
Cb18 | [ 10 : 0 ] |
Cb21 | [ 10 : 0 ] |
Cb22 | [ 10 : 0 ] |
Cb23 | [ 10 : 0 ] |
Cb24 | [ 10 : 0 ] |
Cb25 | [ 10 : 0 ] |
Cb26 | [ 10 : 0 ] |
Cb27 | [ 10 : 0 ] |
Cb28 | [ 10 : 0 ] |
Cb31 | [ 10 : 0 ] |
Cb32 | [ 10 : 0 ] |
Cb33 | [ 10 : 0 ] |
Cb34 | [ 10 : 0 ] |
Cb35 | [ 10 : 0 ] |
Cb36 | [ 10 : 0 ] |
Cb37 | [ 10 : 0 ] |
Cb38 | [ 10 : 0 ] |
Cb41 | [ 10 : 0 ] |
Cb42 | [ 10 : 0 ] |
Cb43 | [ 10 : 0 ] |
Cb44 | [ 10 : 0 ] |
Cb45 | [ 10 : 0 ] |
Cb46 | [ 10 : 0 ] |
Cb47 | [ 10 : 0 ] |
Cb48 | [ 10 : 0 ] |
Cb51 | [ 10 : 0 ] |
Cb52 | [ 10 : 0 ] |
Cb53 | [ 10 : 0 ] |
Cb54 | [ 10 : 0 ] |
Cb55 | [ 10 : 0 ] |
Cb56 | [ 10 : 0 ] |
Cb57 | [ 10 : 0 ] |
Cb58 | [ 10 : 0 ] |
Cb61 | [ 10 : 0 ] |
Cb62 | [ 10 : 0 ] |
Cb63 | [ 10 : 0 ] |
Cb64 | [ 10 : 0 ] |
Cb65 | [ 10 : 0 ] |
Cb66 | [ 10 : 0 ] |
Cb67 | [ 10 : 0 ] |
Cb68 | [ 10 : 0 ] |
Cb71 | [ 10 : 0 ] |
Cb72 | [ 10 : 0 ] |
Cb73 | [ 10 : 0 ] |
Cb74 | [ 10 : 0 ] |
Cb75 | [ 10 : 0 ] |
Cb76 | [ 10 : 0 ] |
Cb77 | [ 10 : 0 ] |
Cb78 | [ 10 : 0 ] |
Cb81 | [ 10 : 0 ] |
Cb82 | [ 10 : 0 ] |
Cb83 | [ 10 : 0 ] |
Cb84 | [ 10 : 0 ] |
Cb85 | [ 10 : 0 ] |
Cb86 | [ 10 : 0 ] |
Cb87 | [ 10 : 0 ] |
Cb88 | [ 10 : 0 ] |
Outputs | |
JPEG_bitstream | [ 31 : 0 ] |
data_ready | |
output_reg_count | [ 4 : 0 ] |
end_of_block_empty |
Signals | |
reg[ 7 : 0 ] | block_counter |
reg[ 11 : 0 ] | Cb11_amp |
reg[ 11 : 0 ] | Cb11_1_pos |
reg[ 11 : 0 ] | Cb11_1_neg |
reg[ 11 : 0 ] | Cb11_diff |
reg[ 11 : 0 ] | Cb11_previous |
reg[ 11 : 0 ] | Cb11_1 |
reg[ 10 : 0 ] | Cb12_amp |
reg[ 10 : 0 ] | Cb12_pos |
reg[ 10 : 0 ] | Cb12_neg |
reg[ 10 : 0 ] | Cb21_pos |
reg[ 10 : 0 ] | Cb21_neg |
reg[ 10 : 0 ] | Cb31_pos |
reg[ 10 : 0 ] | Cb31_neg |
reg[ 10 : 0 ] | Cb22_pos |
reg[ 10 : 0 ] | Cb22_neg |
reg[ 10 : 0 ] | Cb13_pos |
reg[ 10 : 0 ] | Cb13_neg |
reg[ 10 : 0 ] | Cb14_pos |
reg[ 10 : 0 ] | Cb14_neg |
reg[ 10 : 0 ] | Cb15_pos |
reg[ 10 : 0 ] | Cb15_neg |
reg[ 10 : 0 ] | Cb16_pos |
reg[ 10 : 0 ] | Cb16_neg |
reg[ 10 : 0 ] | Cb17_pos |
reg[ 10 : 0 ] | Cb17_neg |
reg[ 10 : 0 ] | Cb18_pos |
reg[ 10 : 0 ] | Cb18_neg |
reg[ 10 : 0 ] | Cb23_pos |
reg[ 10 : 0 ] | Cb23_neg |
reg[ 10 : 0 ] | Cb24_pos |
reg[ 10 : 0 ] | Cb24_neg |
reg[ 10 : 0 ] | Cb25_pos |
reg[ 10 : 0 ] | Cb25_neg |
reg[ 10 : 0 ] | Cb26_pos |
reg[ 10 : 0 ] | Cb26_neg |
reg[ 10 : 0 ] | Cb27_pos |
reg[ 10 : 0 ] | Cb27_neg |
reg[ 10 : 0 ] | Cb28_pos |
reg[ 10 : 0 ] | Cb28_neg |
reg[ 10 : 0 ] | Cb32_pos |
reg[ 10 : 0 ] | Cb32_neg |
reg[ 10 : 0 ] | Cb33_pos |
reg[ 10 : 0 ] | Cb33_neg |
reg[ 10 : 0 ] | Cb34_pos |
reg[ 10 : 0 ] | Cb34_neg |
reg[ 10 : 0 ] | Cb35_pos |
reg[ 10 : 0 ] | Cb35_neg |
reg[ 10 : 0 ] | Cb36_pos |
reg[ 10 : 0 ] | Cb36_neg |
reg[ 10 : 0 ] | Cb37_pos |
reg[ 10 : 0 ] | Cb37_neg |
reg[ 10 : 0 ] | Cb38_pos |
reg[ 10 : 0 ] | Cb38_neg |
reg[ 10 : 0 ] | Cb41_pos |
reg[ 10 : 0 ] | Cb41_neg |
reg[ 10 : 0 ] | Cb42_pos |
reg[ 10 : 0 ] | Cb42_neg |
reg[ 10 : 0 ] | Cb43_pos |
reg[ 10 : 0 ] | Cb43_neg |
reg[ 10 : 0 ] | Cb44_pos |
reg[ 10 : 0 ] | Cb44_neg |
reg[ 10 : 0 ] | Cb45_pos |
reg[ 10 : 0 ] | Cb45_neg |
reg[ 10 : 0 ] | Cb46_pos |
reg[ 10 : 0 ] | Cb46_neg |
reg[ 10 : 0 ] | Cb47_pos |
reg[ 10 : 0 ] | Cb47_neg |
reg[ 10 : 0 ] | Cb48_pos |
reg[ 10 : 0 ] | Cb48_neg |
reg[ 10 : 0 ] | Cb51_pos |
reg[ 10 : 0 ] | Cb51_neg |
reg[ 10 : 0 ] | Cb52_pos |
reg[ 10 : 0 ] | Cb52_neg |
reg[ 10 : 0 ] | Cb53_pos |
reg[ 10 : 0 ] | Cb53_neg |
reg[ 10 : 0 ] | Cb54_pos |
reg[ 10 : 0 ] | Cb54_neg |
reg[ 10 : 0 ] | Cb55_pos |
reg[ 10 : 0 ] | Cb55_neg |
reg[ 10 : 0 ] | Cb56_pos |
reg[ 10 : 0 ] | Cb56_neg |
reg[ 10 : 0 ] | Cb57_pos |
reg[ 10 : 0 ] | Cb57_neg |
reg[ 10 : 0 ] | Cb58_pos |
reg[ 10 : 0 ] | Cb58_neg |
reg[ 10 : 0 ] | Cb61_pos |
reg[ 10 : 0 ] | Cb61_neg |
reg[ 10 : 0 ] | Cb62_pos |
reg[ 10 : 0 ] | Cb62_neg |
reg[ 10 : 0 ] | Cb63_pos |
reg[ 10 : 0 ] | Cb63_neg |
reg[ 10 : 0 ] | Cb64_pos |
reg[ 10 : 0 ] | Cb64_neg |
reg[ 10 : 0 ] | Cb65_pos |
reg[ 10 : 0 ] | Cb65_neg |
reg[ 10 : 0 ] | Cb66_pos |
reg[ 10 : 0 ] | Cb66_neg |
reg[ 10 : 0 ] | Cb67_pos |
reg[ 10 : 0 ] | Cb67_neg |
reg[ 10 : 0 ] | Cb68_pos |
reg[ 10 : 0 ] | Cb68_neg |
reg[ 10 : 0 ] | Cb71_pos |
reg[ 10 : 0 ] | Cb71_neg |
reg[ 10 : 0 ] | Cb72_pos |
reg[ 10 : 0 ] | Cb72_neg |
reg[ 10 : 0 ] | Cb73_pos |
reg[ 10 : 0 ] | Cb73_neg |
reg[ 10 : 0 ] | Cb74_pos |
reg[ 10 : 0 ] | Cb74_neg |
reg[ 10 : 0 ] | Cb75_pos |
reg[ 10 : 0 ] | Cb75_neg |
reg[ 10 : 0 ] | Cb76_pos |
reg[ 10 : 0 ] | Cb76_neg |
reg[ 10 : 0 ] | Cb77_pos |
reg[ 10 : 0 ] | Cb77_neg |
reg[ 10 : 0 ] | Cb78_pos |
reg[ 10 : 0 ] | Cb78_neg |
reg[ 10 : 0 ] | Cb81_pos |
reg[ 10 : 0 ] | Cb81_neg |
reg[ 10 : 0 ] | Cb82_pos |
reg[ 10 : 0 ] | Cb82_neg |
reg[ 10 : 0 ] | Cb83_pos |
reg[ 10 : 0 ] | Cb83_neg |
reg[ 10 : 0 ] | Cb84_pos |
reg[ 10 : 0 ] | Cb84_neg |
reg[ 10 : 0 ] | Cb85_pos |
reg[ 10 : 0 ] | Cb85_neg |
reg[ 10 : 0 ] | Cb86_pos |
reg[ 10 : 0 ] | Cb86_neg |
reg[ 10 : 0 ] | Cb87_pos |
reg[ 10 : 0 ] | Cb87_neg |
reg[ 10 : 0 ] | Cb88_pos |
reg[ 10 : 0 ] | Cb88_neg |
reg[ 3 : 0 ] | Cb11_bits_pos |
reg[ 3 : 0 ] | Cb11_bits_neg |
reg[ 3 : 0 ] | Cb11_bits |
reg[ 3 : 0 ] | Cb11_bits_1 |
reg[ 3 : 0 ] | Cb12_bits_pos |
reg[ 3 : 0 ] | Cb12_bits_neg |
reg[ 3 : 0 ] | Cb12_bits |
reg[ 3 : 0 ] | Cb12_bits_1 |
reg[ 3 : 0 ] | Cb12_bits_2 |
reg[ 3 : 0 ] | Cb12_bits_3 |
reg | Cb11_msb |
reg | Cb12_msb |
reg | Cb12_msb_1 |
reg | data_ready |
reg | enable_1 |
reg | enable_2 |
reg | enable_3 |
reg | enable_4 |
reg | enable_5 |
reg | enable_6 |
reg | enable_7 |
reg | enable_8 |
reg | enable_9 |
reg | enable_10 |
reg | enable_11 |
reg | enable_12 |
reg | enable_13 |
reg | enable_module |
reg | enable_latch_7 |
reg | enable_latch_8 |
reg | Cb12_et_zero |
reg | rollover |
reg | rollover_1 |
reg | rollover_2 |
reg | rollover_3 |
reg | rollover_4 |
reg | rollover_5 |
reg | rollover_6 |
reg | rollover_7 |
reg | Cb21_et_zero |
reg | Cb21_msb |
reg | Cb31_et_zero |
reg | Cb31_msb |
reg | Cb22_et_zero |
reg | Cb22_msb |
reg | Cb13_et_zero |
reg | Cb13_msb |
reg | Cb14_et_zero |
reg | Cb14_msb |
reg | Cb15_et_zero |
reg | Cb15_msb |
reg | Cb16_et_zero |
reg | Cb16_msb |
reg | Cb17_et_zero |
reg | Cb17_msb |
reg | Cb18_et_zero |
reg | Cb18_msb |
reg | Cb23_et_zero |
reg | Cb23_msb |
reg | Cb24_et_zero |
reg | Cb24_msb |
reg | Cb25_et_zero |
reg | Cb25_msb |
reg | Cb26_et_zero |
reg | Cb26_msb |
reg | Cb27_et_zero |
reg | Cb27_msb |
reg | Cb28_et_zero |
reg | Cb28_msb |
reg | Cb32_et_zero |
reg | Cb32_msb |
reg | Cb33_et_zero |
reg | Cb33_msb |
reg | Cb34_et_zero |
reg | Cb34_msb |
reg | Cb35_et_zero |
reg | Cb35_msb |
reg | Cb36_et_zero |
reg | Cb36_msb |
reg | Cb37_et_zero |
reg | Cb37_msb |
reg | Cb38_et_zero |
reg | Cb38_msb |
reg | Cb41_et_zero |
reg | Cb41_msb |
reg | Cb42_et_zero |
reg | Cb42_msb |
reg | Cb43_et_zero |
reg | Cb43_msb |
reg | Cb44_et_zero |
reg | Cb44_msb |
reg | Cb45_et_zero |
reg | Cb45_msb |
reg | Cb46_et_zero |
reg | Cb46_msb |
reg | Cb47_et_zero |
reg | Cb47_msb |
reg | Cb48_et_zero |
reg | Cb48_msb |
reg | Cb51_et_zero |
reg | Cb51_msb |
reg | Cb52_et_zero |
reg | Cb52_msb |
reg | Cb53_et_zero |
reg | Cb53_msb |
reg | Cb54_et_zero |
reg | Cb54_msb |
reg | Cb55_et_zero |
reg | Cb55_msb |
reg | Cb56_et_zero |
reg | Cb56_msb |
reg | Cb57_et_zero |
reg | Cb57_msb |
reg | Cb58_et_zero |
reg | Cb58_msb |
reg | Cb61_et_zero |
reg | Cb61_msb |
reg | Cb62_et_zero |
reg | Cb62_msb |
reg | Cb63_et_zero |
reg | Cb63_msb |
reg | Cb64_et_zero |
reg | Cb64_msb |
reg | Cb65_et_zero |
reg | Cb65_msb |
reg | Cb66_et_zero |
reg | Cb66_msb |
reg | Cb67_et_zero |
reg | Cb67_msb |
reg | Cb68_et_zero |
reg | Cb68_msb |
reg | Cb71_et_zero |
reg | Cb71_msb |
reg | Cb72_et_zero |
reg | Cb72_msb |
reg | Cb73_et_zero |
reg | Cb73_msb |
reg | Cb74_et_zero |
reg | Cb74_msb |
reg | Cb75_et_zero |
reg | Cb75_msb |
reg | Cb76_et_zero |
reg | Cb76_msb |
reg | Cb77_et_zero |
reg | Cb77_msb |
reg | Cb78_et_zero |
reg | Cb78_msb |
reg | Cb81_et_zero |
reg | Cb81_msb |
reg | Cb82_et_zero |
reg | Cb82_msb |
reg | Cb83_et_zero |
reg | Cb83_msb |
reg | Cb84_et_zero |
reg | Cb84_msb |
reg | Cb85_et_zero |
reg | Cb85_msb |
reg | Cb86_et_zero |
reg | Cb86_msb |
reg | Cb87_et_zero |
reg | Cb87_msb |
reg | Cb88_et_zero |
reg | Cb88_msb |
reg | Cb12_et_zero_1 |
reg | Cb12_et_zero_2 |
reg | Cb12_et_zero_3 |
reg | Cb12_et_zero_4 |
reg | Cb12_et_zero_5 |
reg[ 10 : 0 ] | Cb_DC [ 11 : 0 ] |
reg[ 3 : 0 ] | Cb_DC_code_length [ 11 : 0 ] |
reg[ 15 : 0 ] | Cb_AC [ 161 : 0 ] |
reg[ 4 : 0 ] | Cb_AC_code_length [ 161 : 0 ] |
reg[ 7 : 0 ] | Cb_AC_run_code [ 250 : 0 ] |
reg[ 10 : 0 ] | Cb11_Huff |
reg[ 10 : 0 ] | Cb11_Huff_1 |
reg[ 10 : 0 ] | Cb11_Huff_2 |
reg[ 15 : 0 ] | Cb12_Huff |
reg[ 15 : 0 ] | Cb12_Huff_1 |
reg[ 15 : 0 ] | Cb12_Huff_2 |
reg[ 3 : 0 ] | Cb11_Huff_count |
reg[ 3 : 0 ] | Cb11_Huff_shift |
reg[ 3 : 0 ] | Cb11_Huff_shift_1 |
reg[ 3 : 0 ] | Cb11_amp_shift |
reg[ 3 : 0 ] | Cb12_amp_shift |
reg[ 3 : 0 ] | Cb12_Huff_shift |
reg[ 3 : 0 ] | Cb12_Huff_shift_1 |
reg[ 3 : 0 ] | zero_run_length |
reg[ 3 : 0 ] | zrl_1 |
reg[ 3 : 0 ] | zrl_2 |
reg[ 3 : 0 ] | zrl_3 |
reg[ 4 : 0 ] | Cb12_Huff_count |
reg[ 4 : 0 ] | Cb12_Huff_count_1 |
reg[ 4 : 0 ] | output_reg_count |
reg[ 4 : 0 ] | Cb11_output_count |
reg[ 4 : 0 ] | old_orc_1 |
reg[ 4 : 0 ] | old_orc_2 |
reg[ 4 : 0 ] | old_orc_3 |
reg[ 4 : 0 ] | old_orc_4 |
reg[ 4 : 0 ] | old_orc_5 |
reg[ 4 : 0 ] | old_orc_6 |
reg[ 4 : 0 ] | Cb12_oc_1 |
reg[ 4 : 0 ] | orc_3 |
reg[ 4 : 0 ] | orc_4 |
reg[ 4 : 0 ] | orc_5 |
reg[ 4 : 0 ] | orc_6 |
reg[ 4 : 0 ] | orc_7 |
reg[ 4 : 0 ] | orc_8 |
reg[ 4 : 0 ] | Cb12_output_count |
reg[ 4 : 0 ] | Cb12_edge |
reg[ 4 : 0 ] | Cb12_edge_1 |
reg[ 4 : 0 ] | Cb12_edge_2 |
reg[ 4 : 0 ] | Cb12_edge_3 |
reg[ 4 : 0 ] | Cb12_edge_4 |
reg[ 31 : 0 ] | JPEG_bitstream |
reg[ 31 : 0 ] | JPEG_bs |
reg[ 31 : 0 ] | JPEG_bs_1 |
reg[ 31 : 0 ] | JPEG_bs_2 |
reg[ 31 : 0 ] | JPEG_bs_3 |
reg[ 31 : 0 ] | JPEG_bs_4 |
reg[ 31 : 0 ] | JPEG_bs_5 |
reg[ 31 : 0 ] | JPEG_Cb12_bs |
reg[ 31 : 0 ] | JPEG_Cb12_bs_1 |
reg[ 31 : 0 ] | JPEG_Cb12_bs_2 |
reg[ 31 : 0 ] | JPEG_Cb12_bs_3 |
reg[ 31 : 0 ] | JPEG_Cb12_bs_4 |
reg[ 31 : 0 ] | JPEG_ro_bs |
reg[ 31 : 0 ] | JPEG_ro_bs_1 |
reg[ 31 : 0 ] | JPEG_ro_bs_2 |
reg[ 31 : 0 ] | JPEG_ro_bs_3 |
reg[ 31 : 0 ] | JPEG_ro_bs_4 |
reg[ 21 : 0 ] | Cb11_JPEG_LSBs_3 |
reg[ 10 : 0 ] | Cb11_JPEG_LSBs |
reg[ 10 : 0 ] | Cb11_JPEG_LSBs_1 |
reg[ 10 : 0 ] | Cb11_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Cb12_JPEG_LSBs |
reg[ 9 : 0 ] | Cb12_JPEG_LSBs_1 |
reg[ 9 : 0 ] | Cb12_JPEG_LSBs_2 |
reg[ 9 : 0 ] | Cb12_JPEG_LSBs_3 |
reg[ 25 : 0 ] | Cb11_JPEG_bits |
reg[ 25 : 0 ] | Cb11_JPEG_bits_1 |
reg[ 25 : 0 ] | Cb12_JPEG_bits |
reg[ 25 : 0 ] | Cb12_JPEG_LSBs_4 |
reg[ 7 : 0 ] | Cb12_code_entry |
reg | third_8_all_0s |
reg | fourth_8_all_0s |
reg | fifth_8_all_0s |
reg | sixth_8_all_0s |
reg | seventh_8_all_0s |
reg | eighth_8_all_0s |
reg | end_of_block |
reg | end_of_block_output |
reg | code_15_0 |
reg | zrl_et_15 |
reg | end_of_block_empty |
wire[ 7 : 0 ] | code_index |
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