Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
M
meta-elphel393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
meta-elphel393
Commits
4fd3a580
Commit
4fd3a580
authored
Dec 15, 2013
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
testing si5338 optional initialization
parent
a99b4e22
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
2 deletions
+2
-2
elphel393.dts
conf/machine/boards/elphel393/elphel393.dts
+2
-2
No files found.
conf/machine/boards/elphel393/elphel393.dts
View file @
4fd3a580
...
...
@@ -179,8 +179,8 @@
si5338
@
70
{
compatible
=
"sil,si5338"
;
reg
=
<
0x70
>;
si5338
,
init
=
"
always"
;
/*
initialize
PLL
,
wait
for
lock
.
Other
(
not
yet
implemented
)
option
is
'if off'
*/
/*
low
-
level
masked
register
writes
,
may
be
u
a
ed
to
load
frequency
plan
*/
si5338
,
init
=
"
if off"
;
/*
initialize
PLL
if
chip
was
not
programmed
,
wait
for
lock
.
Other
option
is
'always'
*/
/*
low
-
level
masked
register
writes
,
may
be
u
s
ed
to
load
frequency
plan
*/
/*
si5338
,
configuration_data
=<
0x1ffcf0
>;*/
/*
just
for
testing
:
write
data
0xfc
with
write
enable
mask
0xf0
to
register
0x01f
*/
si5338
,
in_frequency3
=
<
25000000
>;
/*
25
MHz
on
input
3
(
other
inputs
are
'12",'
4
','
56
' and '
12
xo
' */
/* PLL may be set either directly (pll_freq_fract,pll_freq_int) or to match some output (pll_by_out_fract, pll_by_out_int)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment