#define X313_TIMESTAMPLEN 28 // pixels used for timestamp (in linescan mode added after the line)
#define X3X3_RSTSENSDCM // FPGA DCM can fail after clock change, needs to be reset
#define X3X3_SENSDCM_CLK2X_RESET // reset pclk2x DCM also
#define I2C359_CLK_NUMBER 4
#define CCAM_NEGRST //set negative MRST polarity
#define CCAM_TRIG_INT
#define CCAM_MRST_OFF
#define CCAM_ARST_OFF
#define CCAM_ARST_ON
#define CCAM_RESET_MCONTR_ON // Set mode that resets memory controller pointers after each frame sync. TODO: Later - make it work without?
#define CCAM_ENDFRAMES_EN // Enable ending frame being compressed if no more data will be available (frame ended before specified number of blocks compressed)
#define CCAM_ARO_ON //set
#define CCAM_DCLK_ON
#define CCAM_CNVEN_OFF
#define CCAM_MRST_ON
#define CCAM_EXTERNALTS_EN // Maybe use default as enabled - yes, it will not be active if not available
#define DEMOS_MONO4 14 // monochrome, but the block scan order is still the same as in YCbCr 4:2:0 (macroblocks in scan order, block in 2x2 macroblock in scan order)
// [8:7] == 0,1 - NOP, 2 - disable, 3 - enable subtracting of average value (DC component), bypassing DCT
// #define X313_RA_HIST_DATA 0x45 /// use CSP4 with wait cycles to have a pulse
port_csp0_addr[X313_WA_HIST_ADDR]=addr;/// Write start address, read first word from the memory to the output buffer (will be read out during next read)
X3X3_AFTERWRITE;//! needed before reading from FPGA after writing to it (for the writes that influence reads only)
for(i=0;i<l;i++)data[i]=port_csp4_addr[X313_RA_HIST_DATA];/// will autoincrement FPGA table address)
