+device tree

/**/

/ {

	chosen {

		bootargs = "cma=336M console=ttyPS0,115200 root=/dev/mmcblk0p2 rw ip=192.168.0.8 earlyprintk rootwait rootfstype=ext4";

		linux,stdout-path = "/amba@0/serial@e0000000";

	};

};

/**/

/ {

	chosen {

		bootargs = "cma=336M console=ttyPS0,115200 root=ubi0:elphel393-rootfs rw ip=192.168.0.8 earlyprintk rootwait rootfstype=ubifs ubi.mtd=4,2048";

		linux,stdout-path = "/amba@0/serial@e0000000";

	};

};

/**/

/ {

	chosen {

		bootargs = "cma=336M console=ttyPS0,115200 root=/dev/ram rw ip=192.168.0.8 earlyprintk ramdisk_size=262144";

		linux,stdout-path = "/amba@0/serial@e0000000";

	};

};

/* */

/dts-v1/;

/ {

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "xlnx,zynq-7000";

	model = "Elphel 10393 original";

	aliases {

		ethernet0 = &ps7_ethernet_0;

		serial0 = &ps7_uart_0;

	} ;

	chosen {

/*		bootargs = "console=ttyPS0,115200 debug root=/dev/ram rw ip=192.168.0.9 earlyprintk ramdisk_size=262144";*/

		bootargs = "cma=128M console=ttyPS0,115200 root=/dev/mmcblk0p2 rw ip=192.168.0.8 earlyprintk rootwait rootfstype=ext4";

		linux,stdout-path = "/amba@0/serial@e0000000";

	} ;

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		ps7_cortexa9_0: cpu@0 {

			bus-handle = <&ps7_axi_interconnect_0>;

			clock-latency = <1000>;

			clocks = <&clkc 3>;

			compatible = "arm,cortex-a9";

			d-cache-line-size = <0x20>;

			d-cache-size = <0x8000>;

			device_type = "cpu";

			i-cache-line-size = <0x20>;

			i-cache-size = <0x8000>;

			interrupt-handle = <&ps7_scugic_0>;

			cpu0-supply = <&regulator_vccpint>;

			reg = <0x0>;

			operating-points = <

					666667 1000000

					333334 1000000

				>;

		} ;

		ps7_cortexa9_1: cpu@1 {

			bus-handle = <&ps7_axi_interconnect_0>;

			clocks = <&clkc 3>;

			compatible = "arm,cortex-a9";

			d-cache-line-size = <0x20>;

			d-cache-size = <0x8000>;

			device_type = "cpu";

			i-cache-line-size = <0x20>;

			i-cache-size = <0x8000>;

			interrupt-handle = <&ps7_scugic_0>;

			reg = <0x1>;

		} ;

	} ;

	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&ps7_scugic_0>;

		interrupts = <0 5 4>, <0 6 4>;

		reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>;

		reg-names = "cpu0", "cpu1";

	} ;

	regulator_vccpint: fixedregulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "VCCPINT";

		regulator-min-microvolt = <1000000>;

		regulator-max-microvolt = <1000000>;

		regulator-boot-on;

		regulator-always-on;

	} ;

	ps7_ddr_0: memory@0 {

		device_type = "memory";

		reg = <0x0 0x40000000>;

	} ;

	ps7_axi_interconnect_0: amba@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus";

		ranges ;

		ps7_afi_0: ps7-afi@f8008000 {

			compatible = "xlnx,ps7-afi-1.00.a";

			reg = <0xf8008000 0x1000>;

		} ;

		ps7_afi_1: ps7-afi@f8009000 {

			compatible = "xlnx,ps7-afi-1.00.a";

			reg = <0xf8009000 0x1000>;

		} ;

		ps7_afi_2: ps7-afi@f800a000 {

			compatible = "xlnx,ps7-afi-1.00.a";

			reg = <0xf800a000 0x1000>;

		} ;

		ps7_afi_3: ps7-afi@f800b000 {

			compatible = "xlnx,ps7-afi-1.00.a";

			reg = <0xf800b000 0x1000>;

		} ;

		ps7_ddrc_0: ps7-ddrc@f8006000 {

			compatible = "xlnx,zynq-ddrc-a05";

			reg = <0xf8006000 0x1000>;

			xlnx,has-ecc = <0x0>;

		} ;

		ps7_dev_cfg_0: ps7-dev-cfg@f8007000 {

			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";

			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;

			compatible = "xlnx,zynq-devcfg-1.0", "xlnx,ps7-dev-cfg-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 8 4>;

			reg = <0xf8007000 0x100>;

			syscon = <&ps7_slcr_0>;

		} ;

		ps7_dma_s: ps7-dma@f8003000 {

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <4>;

			arm,primecell-periphid = <0x41330>;

			clock-names = "apb_pclk";

			clocks = <&clkc 27>;

			compatible = "arm,pl330", "arm,primecell", "xlnx,ps7-dma-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";

			interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>;

			reg = <0xf8003000 0x1000>;

		} ;

		ps7_ethernet_0: ps7-ethernet@e000b000 {

			#address-cells = <1>;

			#size-cells = <0>;

			clock-names = "ref_clk", "aper_clk";

			clocks = <&clkc 13>, <&clkc 30>;

			compatible = "xlnx,ps7-ethernet-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 22 4>;

			phy-mode = "rgmii-id";

			reg = <0xe000b000 0x1000>;

			xlnx,enet-reset = <0xffffffff>;

			xlnx,eth-mode = <0x1>;

			xlnx,has-mdio = <0x1>;

			xlnx,ptp-enet-clock = <111111115>;

		} ;

		ps7_i2c_0: ps7-i2c@e0004000 {

			bus-id = <0>;

			clocks = <&clkc 38>;

			compatible = "cdns,i2c-r1p10", "xlnx,ps7-i2c-1.00.a";

			i2c-clk = <400000>;

			input-clk = <111111114>;

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = < 0 25 4 >;

			reg = < 0xe0004000 0x1000 >;

			xlnx,has-interrupt = <0x0>;

			xlnx,i2c-clk-freq-hz = <0x69f6bcb>;

			xlnx,i2c-reset = "";

			#address-cells = <1>;

			#size-cells = <0>;

		} ;

		ps7_gpio_0: ps7-gpio@e000a000 {

			#gpio-cells = <2>;

			#interrupt-cells = <2>;

			clocks = <&clkc 42>;

			compatible = "xlnx,zynq-gpio-1.0", "xlnx,ps7-gpio-1.00.a";

			emio-gpio-width = <64>;

			gpio-controller ;

			gpio-mask-high = <0x0>;

			gpio-mask-low = <0x0>;

			interrupt-controller;

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 20 4>;

			reg = <0xe000a000 0x1000>;

		} ;

		ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 {

			compatible = "xlnx,ps7-iop-bus-config-1.00.a";

			reg = <0xe0200000 0x1000>;

		} ;

		ps7_pl310_0: ps7-pl310@f8f02000 {

			arm,data-latency = <3 2 2>;

			arm,tag-latency = <2 2 2>;

			cache-level = <2>;

			cache-unified ;

			compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 2 4>;

			reg = <0xf8f02000 0x1000>;

		} ;

		ps7_ram_0: ps7-ram@0 {

			compatible = "xlnx,ps7-ram-1.00.a", "xlnx,ps7-ocm";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 3 4>;

			reg = <0xfffc0000 0x40000>;

		} ;

		ps7_scugic_0: ps7-scugic@f8f01000 {

			#address-cells = <2>;

			#interrupt-cells = <3>;

			#size-cells = <1>;

			compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic";

			interrupt-controller ;

			num_cpus = <2>;

			num_interrupts = <96>;

			reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>;

		} ;

		ps7_globaltimer_0: ps7-globaltimer@f8f00200 {

			clocks = <&clkc 4>;

			compatible = "arm,cortex-a9-global-timer", "xlnx,ps7-globaltimer-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <1 11 0x301>;

			reg = <0xf8f00200 0x100>;

		} ;

		ps7_scutimer_0: ps7-scutimer@f8f00600 {

			clocks = <&clkc 4>;

			compatible = "arm,cortex-a9-twd-timer", "xlnx,ps7-scutimer-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <1 13 0x301>;

			reg = <0xf8f00600 0x20>;

		} ;

		ps7_scuwdt_0: ps7-scuwdt@f8f00620 {

			clocks = <&clkc 4>;

			compatible = "xlnx,ps7-scuwdt-1.00.a";

			device_type = "watchdog";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <1 14 0x301>;

			reg = <0xf8f00620 0xe0>;

		} ;

		ps7_wdt_0: ps7-wdt@f8005000 {

			clocks = <&clkc 45>;

			compatible = "cdns,wdt-r1p2", "xlnx,zynq-wdt-r1p2";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 9 4>;

			reg = <0xf8005000 0x1000>;

			reset = <0>;

			timeout-sec = <10>;

		} ;

		ps7_sd_0: ps7-sdio@e0100000 {

			clock-frequency = <0x7735940>;

			clock-names = "clk_xin", "clk_ahb", "ref_clk", "aper_clk";

			clocks = <&clkc 21>, <&clkc 32>, <&clkc 21>, <&clkc 32>;

			compatible = "arasan,sdhci-8.9a", "arasan,sdhci", "generic-sdhci", "xlnx,ps7-sdio-1.00.a";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 24 4>;

			reg = <0xe0100000 0x1000>;

			xlnx,has-cd = <0x1>;

			xlnx,has-power = <0x0>;

			xlnx,has-wp = <0x1>;

			xlnx,sdio-clk-freq-hz = <0x3f93e10>;

			/*wp-inverted;*/

		} ;

		ps7_slcr_0: ps7-slcr@f8000000 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus", "xlnx,ps7-slcr-1.00.a";

			ranges ;

			reg = <0xf8000000 0x1000>;

			clkc: clkc@100 {

				#clock-cells = <1>;

				clock-output-names = "armpll", "ddrpll", "iopll",

					"cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",

					"ddr2x", "ddr3x", "dci",

					"lqspi", "smc", "pcap",

					"gem0", "gem1",

					"fclk0", "fclk1", "fclk2", "fclk3",

					"can0", "can1",

					"sdio0", "sdio1",

					"uart0", "uart1",

					"spi0", "spi1",

					"dma",

					"usb0_aper", "usb1_aper",

					"gem0_aper", "gem1_aper",

					"sdio0_aper", "sdio1_aper",

					"spi0_aper", "spi1_aper",

					"can0_aper", "can1_aper",

					"i2c0_aper", "i2c1_aper",

					"uart0_aper", "uart1_aper",

					"gpio_aper", "lqspi_aper", "smc_aper", "swdt",

					"dbg_trc", "dbg_apb";

				compatible = "xlnx,ps7-clkc";

				fclk-enable = <0xf>;

				ps-clk-frequency = <33333333>;

				reg = <0x100 0x100>;

			} ;

			rstc: rstc@200 {

				compatible = "xlnx,zynq-reset";

				reg = <0x200 0x48>;

				#reset-cells = <1>;

				syscon = <&ps7_slcr_0>;

			} ;

			pinctl0: pinctrl@700 {

				compatible = "xlnx,pinctrl-zynq";

				reg = <0x700 0x200>;

				syscon = <&ps7_slcr_0>;

			} ;

		} ;

		ps7_ttc_0: ps7-ttc@f8001000 {

			clocks = <&clkc 6>;

			compatible = "cdns,ttc", "xlnx,ps7-ttc-1.00.a";

			interrupt-names = "ttc0", "ttc1", "ttc2";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;

			reg = <0xf8001000 0x1000>;

		} ;

		ps7_smcc_0: ps7-smcc@e000e000 {

			#address-cells = <1>;

			#size-cells = <1>;

		  	clock-names = "memclk", "aclk";

			clocks = <&clkc 11>, <&clkc 44>;

			compatible = "arm,pl353-smc-r2p1";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = < 0 18 4 >;

			ranges ;

			reg = < 0xe000e000 0x1000 >;

			arm,addr25 = <0x0>;

			arm,nor-chip-sel0 = <0x0>;

			arm,nor-chip-sel1 = <0x0>;

			arm,sram-chip-sel0 = <0x0>;

			arm,sram-chip-sel1 = <0x0>;

			ps7_nand_0: ps7-nand@e1000000 {

				compatible = "arm,pl353-nand-r2p1";

				reg = < 0xe1000000 0x1000000 >;

				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/

				arm,nand-width = <0x8>;

				arm,nand-cycle-t0 = <0x4>;

				arm,nand-cycle-t1 = <0x4>;

				arm,nand-cycle-t2 = <0x1>;

				arm,nand-cycle-t3 = <0x2>;

				arm,nand-cycle-t4 = <0x2>;

				arm,nand-cycle-t5 = <0x2>;

				arm,nand-cycle-t6 = <0x4>;

				#address-cells = <0x1>;

				#size-cells = <0x1>;

			} ;

		} ;

		ps7_uart_0: serial@e0000000 {

			clock-names = "uart_clk", "pclk", "ref_clk", "aper_clk";

			clocks = <&clkc 23>, <&clkc 40>, <&clkc 23>, <&clkc 40>;

			compatible = "xlnx,xuartps", "cdns,uart-r1p8", "xlnx,ps7-uart-1.00.a";

			device_type = "serial";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 27 4>;

			reg = <0xe0000000 0x1000>;

			port-number = <1>;

			current-speed = <115200>;

			xlnx,has-modem = <0x0>;

		} ;

		ps7_usb_0: ps7-usb@e0002000 {

			clocks = <&clkc 28>;

			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";

			reg = <0xe0002000 0x1000>;

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 21 4>;

			dr_mode = "host";

			phy_type = "ulpi";

			usb-phy = <&usb_phy0>;

		} ;

		ps7_xadc: ps7-xadc@f8007100 {

			clocks = <&clkc 12>;

			compatible = "xlnx,zynq-xadc-1.00.a", "xlnx,ps7-xadc-1.00.a";

			reg = <0xf8007100 0x20>;

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0 7 4>;

		} ;

	} ;

	usb_phy0: phy0{

		compatible = "ulpi-phy";

		#phy-cells = <0>;

		reg = <0xe0002000 0x1000>;

		view-port = <0x170>;

	} ;

} ;

/* welcome to elphel393 device tree */

/include/ "elphel393-zynq-base.dtsi"

/include/ "elphel393-bootargs.dtsi"

/ {

	model = "Elphel 10393";

	ps7_axi_interconnect_0: amba@0 {

		ps7_i2c_0: ps7-i2c@e0004000 {

			bus-id = <0>;

			i2c-clk = <400000>;

			rtc@68 {

				compatible = "stm,m41t62";

				reg = <0x68>;

			};

			vsc330x@1 {

				compatible = "vsc,vsc3304";

				reg = <0x01>;

				vsc330x,configuration_name = "elphel393: from external";

				/* configuration below is for external eSATA host accessing SSD. Will chnage

					* when the SATA controller code will be operational

					* TODO: specify optimal drive strength, pre-emphasis, etc.

					* All parameters are exported to sysfs for run-time modification

					*/

				vsc330x,configuration_data=<

				0x11080101 /*page 0x11, register 0x08, data=0x1 (inverted input), write enabled mask=0x1 */

				0x11090001

				0x110a0101

				0x110b0101

				0x110e0001

				0x110f0101

				0x230a0b1f /* set output mode for port 10 as non-inverted, forwarding OOB enabled */

				0x230b151f /* set output mode for port 11 as     inverted, forwarding OOB enabled */

				0x230c151f

				0x230d0b1f

				0x230e151f

				0x230f151f

				0xff750101 /* freeze configuration to enable simultaneous modification */

				0x110e0002 /* enable channel 14 input */

				0x11090002 /* enable channel  9 input */

				0x000b091f /* connect port 11 output to input 9 */

				0x000c0e1f /* connect port 12 output to input 14 */

				0xff750001 /* un-freeze configuration to apply connection modifications */

				>;

			};

			si5338@70 {

				compatible = "sil,si5338";

				reg = <0x70>;

				si5338,init="always"; /* initialize PLL if chip was not programmed, wait for lock. Other option is 'if off' */

				/* low-level masked register writes, may be used to load frequency plan */

				/*si5338,configuration_data=< 0x1ffcf0 >;*/ /* just for testing: write data 0xfc with write enable mask 0xf0 to register 0x01f */

				si5338,in_frequency3= < 25000000>; /* 25MHz on input 3 (other inputs are '12",'4','56' and '12xo' */

				/* PLL may be set either directly (pll_freq_fract,pll_freq_int) or to match some output (pll_by_out_fract, pll_by_out_int)

					* _int suffix forces to find integer divisors, _fract - allows fractional ones */

				si5338,pll_by_out_int=<150000000>;  /* 150Mhz May have 3 values: integer, nominator and denominator */

				si5338,out3_freq_int= <150000000>;  /* 150Mhz. May have 3 values: integer, nominator and denominator */

				si5338,out2_select= "in3/2/32";  /* connect out2 to IN3, divided by 2 (input stage) and then by 32 (output stage)*/

				si5338,2V5_LVPECL=  <1 2>; /* set output standard for channels 1 and 2 */

				si5338,1V5_HSTL_A+= <0>;   /* set output standard for channel 0, only A output is used (noninverted) */

				si5338,1V8_LVDS=    <3>;

				/* Disabled state for outputs:  */

				si5338,dis_hi-z=    <0 1 2 3>; /* Disabled state for listed outputs, also possible: "dis_hi-z","dis_low","dis_high","dis_always_on" */

				si5338,output_en=   < 3>; /* Which outputs should be initially enabled */

				si5338,spread_spectrum_3= <1 50 31500>; /* Set spread spectrum for channel3 : enabled, 0.5%, 31.5KHz */

				si5338,out0_freq_int= <15000000>;  /* 15Mhz to output 0 */

				si5338,spread_spectrum_0= <1 500 31500>; /* Set spread spectrum for channel0 : enabled, 5%, 31.5KHz - high value, for testing */

			};

			ltc3589@34 {

				compatible = "ltc,ltc3589";

				reg = <0x34>;

			};

			gpio@20{

				compatible = "ti,tca6408";

				reg = <0x20>;

			};

			gpio@21{

				compatible = "ti,tca6408";

				reg = <0x21>;

			};

			gpio@25{

				compatible = "nxp,pca8574";

				reg = <0x25>;

			};

			/* Use 'spd' instead of '24c02' for read only access*/

			stts2002@31 {

				compatible = "at,24c02";

				reg = <0x31>;

			};

			hwmon@1a { /*hwmon@19*/

				compatible = "stm,jc42";

				reg = <0x1a>;

			};

		};

		ps7_ethernet_0: ps7-ethernet@e000b000 {

			local-mac-address = [00 0e 64 10 00 00];

			phy-handle = <&phy3>;

			phy-mode = "rgmii-id";

			mdio {

				#address-cells = <1>;

				#size-cells = <0>;

				phy3: phy@3 {

					compatible = "atheros,8035";

					device_type = "ethernet-phy";

					reg = <0x3>;

				};

			};

		};

		ps7_smcc_0: ps7-smcc@e000e000 {

			ps7_nand_0: ps7-nand@e1000000 {

				compatible = "arm,pl353-nand-r2p1";

				reg = < 0xe1000000 0x1000000 >;

				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/

				arm,nand-width = <0x8>;

				arm,nand-cycle-t0 = <0x4>;

				arm,nand-cycle-t1 = <0x4>;

				arm,nand-cycle-t2 = <0x1>;

				arm,nand-cycle-t3 = <0x2>;

				arm,nand-cycle-t4 = <0x2>;

				arm,nand-cycle-t5 = <0x2>;

				arm,nand-cycle-t6 = <0x4>;

				#address-cells = <0x1>;

				#size-cells = <0x1>;

				partition@0 {

					label = "u-boot-spl";

					reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/

				};

				partition@1 {

					label = "u-boot";

					reg = <0x100000 0x400000>;/*4MB*/

				};

				partition@2 {

					label = "device-tree";

					reg = <0x500000 0x100000>;/*1MB*/

				};

				partition@3 {

					label = "kernel";

					reg = <0x600000 0x1000000>;/*16MB*/

				};

				partition@4 {

					label = "rootfs";

					reg = <0x1600000 0x10000000>;/*256MB*/

				};

			} ;

		} ;

		elphel_ahci: elphel-ahci@80000000 {

			compatible = "elphel,elphel-ahci";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = <0x0 0x1d 0x4>; /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */

			reg = <0x80000000 0x1000>;

			clb_offs = <0x800>;

			fb_offs = <0xc00>;

		};

	};

	elphel393_pwr: elphel393-pwr@0 {

		compatible = "elphel,elphel393-pwr-1.00";

		elphel393_pwr,simulate=          <0>;

		elphel393_pwr,i2c_chips=         <0x20 0x21 0x25 0x34>;

		elphel393_pwr,vp15.r1=           <357000>;

		elphel393_pwr,vp15.r2=           <287000>;

		elphel393_pwr,vcc_sens01.r1=     <787000>;

		elphel393_pwr,vcc_sens01.r2=     <287000>;

		elphel393_pwr,vcc_sens23.r1=     <787000>;

		elphel393_pwr,vcc_sens23.r2=     <287000>;

		elphel393_pwr,vp5.r1=            <523000>;

		elphel393_pwr,vp5.r2=            <100000>;

		elphel393_pwr,vldo18.r1=         <357000>;

		elphel393_pwr,vldo18.r2=         <287000>;

		elphel393_pwr,channels_disable= "vcc_sens23 vp33sens23 vcc_sens01 vp33sens01";

		elphel393_pwr,pinstrapped_oven=  <1>;

		elphel393_pwr,vcc_sens01_mv=     <2800>; /* set sensor intreface voltage to 2.8V */

		elphel393_pwr,channels_enable=  "vp5";

/*		elphel393_pwr,channels_enable=  "vcc_sens01 vp33sens01"; */

	} ;

	elphel393_mem: elphel393-mem@0 {

		compatible = "elphel,elphel393-mem-1.00";

		/*memsize = <25600>;*/

		memsize = <76800>;

	} ;

	elphel393_init: elphel393-init {

		compatible = "elphel,elphel393-init-1.00";

	} ;

	elphel393_circbuf: elphel393-circbuf@0 {

		compatible = "elphel,elphel393-circbuf-1.00";

		/* set this to "disable" to disable drivers */

		status = "okay";

		interrupt-parent = <&ps7_scugic_0>;

		 /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */

		interrupts =      <0x0 0x34 0x4>, <0x0 0x35 0x4>, <0x0 0x36 0x4>, <0x0 0x37 0x4>,

		                  <0x0 0x38 0x4>, <0x0 0x39 0x4>, <0x0 0x3A 0x4>, <0x0 0x3B 0x4>;

/*        reg = <0x80000000 0x1000>; */

		interrupt-names = "frame_sync_irq_0", "frame_sync_irq_1", "frame_sync_irq_2", "frame_sync_irq_3",

		                  "compr_irq_0", "compr_irq_1", "compr_irq_2", "compr_irq_3";

	};

    elphel393_logger: elphel393-logger@0 {

        compatible = "elphel,elphel393-logger-1.00";

        /* set this to "disable" to disable drivers */

        status = "okay";

        interrupt-parent = <&ps7_scugic_0>;

         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */

        interrupts =      <0x0 0x21 0x4>, <0x0 0x22 0x4>, <0x0 0x23 0x4>, <0x0 0x24 0x4>;

/*        reg = <0x80000000 0x1000>; */

        interrupt-names = "mult_saxi_0", "mult_saxi_1", "mult_saxi_2", "mult_saxi_3";

    };

    elphel393_videomem: elphel393-videomem@0 {

        compatible = "elphel,elphel393-videomem-1.00";

        /* set this to "disable" to disable drivers */

        status = "okay";

        interrupt-parent = <&ps7_scugic_0>;

         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */

        interrupts =      <0x0 0x20 0x4>;

/*        reg = <0x80000000 0x1000>; */

        interrupt-names = "membridge_irq";

        /* maximal dimesions that use all 512M memory for 4 channels. May be changed when doing processing*/

        frame_full_width = <8192>; /* in bytes, will be transformed to bursts (16 bytes). 1 memory page is 2048 bytes (128 bursts) */

        frame_height     = <8192>; /* in pixel lines */

        frames_in_buffer = <2>;    /* Each channel has this number of frames in buffer */

        frame_start_chn0 =     <0x00000000>;      /* Channel 0 frame start (in bytes) */

        frame_start_chn1 =     <0x08000000>;      /* Channel 1 frame start (in bytes) */

        frame_start_chn2 =     <0x10000000>;      /* Channel 2 frame start (in bytes) */

        frame_start_chn3 =     <0x18000000>;      /* Channel 3 frame start (in bytes) */

        frame_full_width_chn0 =      <8192>;      /* Channel 0 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */

        frame_full_width_chn1 =      <8192>;      /* Channel 1 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */

        frame_full_width_chn2 =      <8192>;      /* Channel 2 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */

        frame_full_width_chn3 =      <8192>;      /* Channel 3 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */

        frame_height_chn0 =          <8192>;      /* Channel 0 maximal frame height in pixel lines */

        frame_height_chn1 =          <8192>;      /* Channel 1 maximal frame height in pixel lines */

        frame_height_chn2 =          <8192>;      /* Channel 2 maximal frame height in pixel lines */

        frame_height_chn3 =          <8192>;      /* Channel 3 maximal frame height in pixel lines */

        frames_in_buffer_chn0 =         <2>;      /* Number of frames in channel 0 buffer */

        frames_in_buffer_chn1 =         <2>;      /* Number of frames in channel 1 buffer */

        frames_in_buffer_chn2 =         <2>;      /* Number of frames in channel 2 buffer */

        frames_in_buffer_chn3 =         <2>;      /* Number of frames in channel 3 buffer */

    };

    elphel393_detect_sensors: elphel393-detect_sensors@0 {

        compatible = "elphel,elphel393-detect_sensors-1.00";

        elphel393-detect_sensors,port-mux = "none none none none"; /* "none", "detect" or "mux10359" */

        elphel393-detect_sensors,sensors =  "mt9p006", // Line per port, may contain up to 4 sensors (3 with 10359)

                                            "mt9p006",

                                            "mt9p006",

                                            "mt9p006";

    };

    elphel393_sensor_i2c: elphel393-sensor-i2c@0 {

                compatible = "elphel,elphel393-sensor-i2c-1.00";

                /* Add known devices: name, slave address (7-bit), number of address bytes, number of data bytes, SCL frequency (kHz) */

                elphel393-sensor-i2c,i2c_devices = "mt9f002 0x10 2 2 500",

                                                   "mt9p006 0x48 1 2 500",

                                                   "el10359 0x08 1 2 500",

                                                   "pca9500_eeprom 0x50 1 1 100",

                                                   "cy22393 0x69 1 1 100";

    } ;

    framepars_operations: elphel393-framepars@0 {

        compatible = "elphel,elphel393-framepars-1.00";

    };

    histograms_operations: elphel393-histograms@0 {

        compatible = "elphel,elphel393-histograms-1.00";

    };

    gamma_tables_operations: elphel393-gamma_tables@0 {

        compatible = "elphel,elphel393-gamma_tables-1.00";

    };

    elphel393_mt9x001: elphel393-mt9x001@0 {

        compatible = "elphel,elphel393-mt9x001-1.00";

    };

    klogger_393: klogger-393@0 {

        compatible = "elphel,klogger-393-1.00";

        klogger-393,buffer_size = <1048576>; 

    } ;

};

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