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linux-elphel
Commit 71913108 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
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initial changes to dynamic page registering and sensors with 16 bit register addresses

parent bdc874a6
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Showing with 907 additions and 441 deletions
src/drivers/elphel/detect_sensors.c
View file @ 71913108
......@@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
#define DEBUG
//#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
......@@ -39,19 +39,17 @@
#define DETECT_SENSORS_MODULE_DESCRIPTION "Detect sensor type(s) attached to each of the ports"
#define OF_PREFIX_NAME "elphel393-detect_sensors"
struct sensor_port_config_t
{
u32 mux; ///< sensor multiplexer, currently 0 (SENSOR_DETECT, SENSOR_MUX_10359 or SENSOR_NONE)
u32 sensor[MAX_SENSORS]; ///< Without mux only [0] is used, with 10359 - 0..2 are used (i2c addressing is shifted so 0 is broadcast)
};
struct sensor_port_config_t *pSensorPortConfig;
// removed static to export
static struct sensor_port_config_t sensorPortConfig[] = {
{.mux=SENSOR_NONE,.sensor={SENSOR_NONE,SENSOR_NONE,SENSOR_NONE,SENSOR_NONE}},
{.mux=SENSOR_NONE,.sensor={SENSOR_NONE,SENSOR_NONE,SENSOR_NONE,SENSOR_NONE}},
{.mux=SENSOR_NONE,.sensor={SENSOR_NONE,SENSOR_NONE,SENSOR_NONE,SENSOR_NONE}},
{.mux=SENSOR_NONE,.sensor={SENSOR_NONE,SENSOR_NONE,SENSOR_NONE,SENSOR_NONE}}
};
//struct sensor_port_config_t *pSensorPortConfig;
static const struct of_device_id elphel393_detect_sensors_of_match[];
static struct device *g_dev_ptr; ///< Global pointer to basic device structure. This pointer is used in debugfs output functions
struct sensor_name_t {
......@@ -393,17 +391,111 @@ static int elphel393_detect_sensors_sysfs_register(struct platform_device *pdev)
}
}
/**
* Fills the tables in sensorPortConfig with key-value pairs
* @param par2addr - pointer to the look-up table
* @param table - pointer to the global struct
* @return 0
*/
static int par2addr_fill(const unsigned short *par2addr, u16 *table){
int i=0;
int key;
unsigned short value;
// reset
for(i=0;i<MAX_SENSOR_REGS;i++){
table[i] = 0;
}
i=0;
// fill with key-value pairs
while(true){
key = par2addr[2*i];
value = par2addr[2*i+1];
if ((key==0xffff)||(i>255)){
break;
}
table[key] = value;
i++;
}
return 0;
}
/**
* Based on sensorPortConfig[i].sensor[j], filled from DT,
* gets SENSOR_REGS to true register addresses table for
* the specified sensor
* @return 0
*/
static int par2addr_init(void){
int port;
int sub_chn;
const unsigned short *par2addr;
const unsigned short *pages;
/*
struct sensor_port_config_t {
u32 mux; ///< Sensor multiplexer, currently 0 (SENSOR_DETECT, SENSOR_MUX_10359 or SENSOR_NONE)
u32 sensor[MAX_SENSORS]; ///< Without mux only [0] is used, with 10359 - 0..2 are used (i2c addressing is shifted so 0 is broadcast)
u16 par2addr[MAX_SENSORS][MAX_SENSOR_REGS]; ///< Big LUT. SENSOR_REGSxxx par to sensor reg 'yyy' internal address: haddr+laddr for 16 bit
u16 haddr2rec[MAX_SENSORS][MAX_FPGA_RECS]; ///< Big LUT (but almost empty). Sensor's page address (haddr of reg addr) to fpga i2c record number (fpga line#)
};
*/
// all .mux and .sensor are already filled out
for (port = 0; port < SENSOR_PORTS; port++){
// that's from device tree, fpga is not programmed yet
dev_dbg(g_dev_ptr,"port: %d mux: %d sensors: %d %d %d %d\n",
port,
sensorPortConfig[port].mux,
sensorPortConfig[port].sensor[0],
sensorPortConfig[port].sensor[1],
sensorPortConfig[port].sensor[2],
sensorPortConfig[port].sensor[3]
);
// sub_chn = 3 is never used
for (sub_chn = 0; sub_chn < 4; sub_chn++){
//sensorPortConfig[port].sensor[sub_chn];
switch (sensorPortConfig[port].sensor[sub_chn]) {
case SENSOR_MT9P006:
// get sensor table
par2addr = mt9x001_par2addr;
pages = mt9x001_pages;
break;
case SENSOR_MT9F002:
// get sensor table
break;
}
if (par2addr){
// convert to key-value
par2addr_fill(par2addr,sensorPortConfig[port].par2addr[sub_chn]);
// save pointer to static LUT
sensorPortConfig[port].pages_ptr[sub_chn] = pages;
}
}
}
return 0;
}
static int detect_sensors_probe(struct platform_device *pdev)
{
unsigned int irq;
int res;
//unsigned int irq;
//int res;
struct device *dev = &pdev->dev;
const struct of_device_id *match;
const __be32 *bufsize_be;
struct device_node *node;
// pSensorPortConfig = sensorPortConfig;
//const __be32 *bufsize_be;
//struct device_node *node;
g_dev_ptr = dev; // for debugfs
pSensorPortConfig = sensorPortConfig;
elphel393_detect_sensors_sysfs_register(pdev);
pr_info ("Registered sysfs for detect_sensors");
......@@ -415,6 +507,7 @@ static int elphel393_detect_sensors_sysfs_register(struct platform_device *pdev)
detect_sensors_init_of(pdev);
par2addr_init();
// dev_dbg(dev, "Registering character device with name "DEV393_NAME(DEV393_DETECT_SENSORS));
// res = register_chrdev(DETECT_SENSORS_MAJOR, DEV393_NAME(DEV393_DETECT_SENSORS), &detect_sensors_fops);
......@@ -422,7 +515,7 @@ static int elphel393_detect_sensors_sysfs_register(struct platform_device *pdev)
// dev_err(dev, "\nlogger_init: couldn't get a major number %d.\n ",DETECT_SENSORS_MAJOR);
// return res;
// }
g_dev_ptr = dev; // for debugfs
return 0;
}
......
src/drivers/elphel/detect_sensors.h
View file @ 71913108
......@@ -16,10 +16,25 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
#ifndef DETECT_SENSORS_H
#define DETECT_SENSORS_H
#define DETECT_SENSOR 1 ///< Include sensors, May be OR-ed when looking for sensor/multiplexer code/name
#define DETECT_MUX 2 ///< Include multiplexers, May be OR-ed when looking for sensor/multiplexer code/name
#define MAX_SENSOR_REGS 256
#define MAX_FPGA_RECS 256
struct sensor_port_config_t {
u32 mux; ///< Sensor multiplexer, currently 0 (SENSOR_DETECT, SENSOR_MUX_10359 or SENSOR_NONE)
u32 sensor[MAX_SENSORS]; ///< Without mux only [0] is used, with 10359 - 0..2 are used (i2c addressing is shifted so 0 is broadcast)
u16 par2addr[MAX_SENSORS][MAX_SENSOR_REGS]; ///< Big LUT. SENSOR_REGSxxx par to sensor reg 'yyy' internal address: haddr+laddr for 16 bit
u8 haddr2rec[MAX_SENSORS][MAX_FPGA_RECS]; ///< Big LUT (but almost empty). Sensor's page address (haddr of reg addr) to fpga i2c record number (fpga line#)
unsigned short *pages_ptr[MAX_SENSORS];
};
extern struct sensor_port_config_t *pSensorPortConfig;
typedef enum {NONE,PARALLEL12,HISPI4} sens_iface_t; ///< Sensor port interface type
int get_code_by_name(const char * name, int type);
......@@ -32,3 +47,5 @@ int get_subchannels(int port);
int set_detected_mux_code(int port, int mux_type);
int set_detected_sensor_code(int port, int sub_chn, int mux_type);
sens_iface_t get_port_interface(int port);
#endif
src/drivers/elphel/mt9f002.h
View file @ 71913108
......@@ -19,429 +19,515 @@
/* ON Semi MT9F002 i2c register addresses */
// #define P_MT9F002_NAME ADDR ///< Bits, Default value, RW, Frame Sync'd, Bad Frame
// ///< Description
/*
## FOR INIT, one time?
0x31c0 8db6 # HiSPI timing
0x31c0 8492 # HiSPI timing
0x31c0 8fff # HiSPI timing
0x31c0 8db6 # HiSPI timing
0x0306 00b4 # SMIA_PLL_MULTIPLIER
0x31c6 8400 # HiSPI control status
0x306e 9280 # DataPath select
0x301a 001c # RESET register
## FOR WORK,
0x3028 000a # Analog gain code global
0x302c 000d # Analog gain code red
0x302e 0010 # Analog gain code blue
0x3012 0060 # Coarse integration time
0x3002 - (0x0020) The first row of visible pixels to be read out (not counting any dark rows that may be read). To move the image
window, set this register to the starting Y value.
0x3004 - (0x0090) The first column of visible pixels to be read out (not counting any dark columns that may be read). To move the
image window, set this register to the starting X value.
0x3006 - (0x0CF7) The last row of visible pixels to be read out.
0x3008 - (0x11AF) The last column of visible pixels to be read out.
0x300A - (0x0D6A) The number of complete lines (rows) in the output frame. This includes visible lines and vertical blanking lines.
0x300C - (0x2350) The number of pixel clock periods in one line (row) time. This includes visible pixels and horizontal blanking time.
0x3010 - (0x0128) Fine integration time correction factor. This is an offset that is applied to the programmed value of
fine_integration_time such that the actual integration time matches the integration time equation.
This register should not be modified under normal operation, but must be modified when binning is enabled or the
internal pixel clock divider (pc_speed[2:0]) is used.
0x3012 - (0x0010) Integration time specified in multiples of line_length_pck_.
0x3014 - (0x0524) Integration time specified as a number of pixel clocks.
0x3016 - (0x0111) row speed
0x3018 - extra delay (blanking to get more exact frame rate)
0x301A - reset register
0x301E - Constant offset that is added to the ADC output for all visible pixels in order to set the black level to than 0.
Read-only. Can be made read/write by clearing R0x301A-B[3].
0x3024 - (0x0) Pixel order: 00 - GRBG, 01 - RGGB, 02 - BGGR, 03 - GBRG. Read only, changes a function of R0x3040[1:0]
0x3028 - (0x000A) gain code global
0x302A - analog gain Gr
0x302C - analog gain R
0x302E - analog gain B
0x3030 - analog gain Gb
0x3032 - digital gain Gr
0x3034 - digital gain R
0x3036 - digital gain B
0x3038 - digital gain Gb
0x303A - SMIA version, 0xA = 1.0
0x303B - frame count
0x3040 - (0x0041) read_mode
0x3046 - flash?!
0x3056 - green1_gain
0x3058 - blue_gain
0x305A - red gain
0x305C - green2 gain
0x305E - global gain
0x306A - datapath status
0x306E - datapath select
0x3070 xxxx # test pattern mode
0002 - stripes
0000 - off
0x3072 - The value for red pixels in the Bayer data used for the solid color test pattern and the test cursors.
0x3074 - The value for green pixels in red/green rows of the Bayer data used for the solid color test pattern and the test cursors.
0x3076 - The value for blue pixels in the Bayer data used for the solid color test pattern and the test cursors.
0x3078 - The value for green pixels in blue/green rows of the Bayer data used for the solid color test pattern and the test
cursors.
0x307A - test_raw_mode
0x31c0 - for phases: 4 data lanes, 1 clock lane
*/
// #define P_MT9F002_NAME ADDR ///< Bits, Default value, RW, Frame Sync'd, Bad Frame
///< Description
/* SMIA Configuration Register List */
#define P_MT9F002_SMIA_MODEL_ID 0x0000 ///< [15:0],0x2E01,RW,N,N,
#define P_REG_MT9F002_SMIA_MODEL_ID 0x0000 ///< [15:0],0x2E01,RW,N,N,
///< This register is an alias of R0x3000-1. Read-only. Can be made read/write by clearing R0x301A-B[3].
#define P_MT9F002_SMIA_REVISION_NUMBER 0x0002 ///< [ 7:0], 0x00,RW,N,N,
#define P_REG_MT9F002_SMIA_REVISION_NUMBER 0x0002 ///< [ 7:0], 0x00,RW,N,N,
///< Aptina-assigned revision number. Read-only. Can be made read/write by clearing R0x301A-B[3].
#define P_MT9F002_SMIA_MANUFACTURER_ID 0x0003 ///< [ 7:0], 0x06,RO,N,N
#define P_REG_MT9F002_SMIA_MANUFACTURER_ID 0x0003 ///< [ 7:0], 0x06,RO,N,N
///< Manufacturer ID assigned to Aptina. Read-only. Can be made read/write by clearing R0x301A-B[3].
#define P_MT9F002_SMIA_SMIA_VERSION 0x0004 ///< [ 7:0], 0x0A,RO,N,N
#define P_REG_MT9F002_SMIA_SMIA_VERSION 0x0004 ///< [ 7:0], 0x0A,RO,N,N
///< This register is an alias of R0x303A. Read-only.
#define P_MT9F002_SMIA_FRAME_COUNT 0x0005 ///< [ 7:0], 0xFF,RO,Y,N
#define P_REG_MT9F002_SMIA_FRAME_COUNT 0x0005 ///< [ 7:0], 0xFF,RO,Y,N
///< This register is an alias of R0x303B. Read-only.
#define P_MT9F002_SMIA_PIXEL_ORDER 0x0006 ///< [ 7:0], 0x00,RO,N,N
#define P_REG_MT9F002_SMIA_PIXEL_ORDER 0x0006 ///< [ 7:0], 0x00,RO,N,N
///< This register is an alias of R0x3024. Read-only.
#define P_MT9F002_SMIA_DATA_PEDESTAL 0x0008 ///< [15:0],0x00A8,RW,N,Y
#define P_REG_MT9F002_SMIA_DATA_PEDESTAL 0x0008 ///< [15:0],0x00A8,RW,N,Y
///< This register is an alias of R0x301E-F. Read-only. Can be made read/write by clearing R0x301A-B[3].
#define P_MT9F002_SMIA_FRAME_FORMAT_MODEL_TYPE 0x0040 ///< [ 7:0], 0x01,RO,N,N
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_MODEL_TYPE 0x0040 ///< [ 7:0], 0x01,RO,N,N
///< Type 1. 2-byte Generic Frame Format Description. Read-only.
#define P_MT9F002_SMIA_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_0 0x0042
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_1 0x0044
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_2 0x0046
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_3 0x0048
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_4 0x004A
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_5 0x004C
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_6 0x004E
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_7 0x0050
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_8 0x0052
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_9 0x0054
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_10 0x0056
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_11 0x0058
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_12 0x005A
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_13 0x005C
#define P_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_14 0x005E
#define P_MT9F002_SMIA_ANALOG_GAIN_CAPABILITY 0x0080
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_MIN 0x0084
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_MAX 0x0086
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_STEP 0x0088
#define P_MT9F002_SMIA_ANALOG_GAIN_TYPE 0x008A
#define P_MT9F002_SMIA_ANALOG_GAIN_M0 0x008C
#define P_MT9F002_SMIA_ANALOG_GAIN_C0 0x008E
#define P_MT9F002_SMIA_ANALOG_GAIN_M1 0x0090
#define P_MT9F002_SMIA_ANALOG_GAIN_C1 0x0092
#define P_MT9F002_SMIA_DATA_FORMAT_MODEL_TYPE 0x00C0
#define P_MT9F002_SMIA_DATA_FORMAT_MODEL_SUBTYPE 0x00C1
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_0 0x00C2
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_1 0x00C4
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_2 0x00C6
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_3 0x00C8
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_4 0x00CA
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_5 0x00CC
#define P_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_6 0x00CE
#define P_MT9F002_SMIA_MODE_SELECT 0x0100
#define P_MT9F002_SMIA_IMAGE_ORIENTATION 0x0101
#define P_MT9F002_SMIA_SOFTWARE_RESET 0x0103
#define P_MT9F002_SMIA_GROUPED_PARAMETER_HOLD 0x0104
#define P_MT9F002_SMIA_MASK_CORRUPTED_FRAMES 0x0105
#define P_MT9F002_SMIA_CCP2_CHANNEL_IDENTIFIER 0x0110
#define P_MT9F002_SMIA_CCP2_SIGNALLING_MODE 0x0111
#define P_MT9F002_SMIA_CCP_DATA_FORMAT 0x0112
#define P_MT9F002_SMIA_GAIN_MODE 0x0120
#define P_MT9F002_SMIA_FINE_INTEGRATION_TIME 0x0200
#define P_MT9F002_SMIA_COARSE_INTEGRATION_TIME 0x0202
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_GLOBAL 0x0204
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_GREENR 0x0206
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_RED 0x0208
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_BLUE 0x020A
#define P_MT9F002_SMIA_ANALOG_GAIN_CODE_GREENB 0x020C
#define P_MT9F002_SMIA_DIGITAL_GAIN_GREENR 0x020E
#define P_MT9F002_SMIA_DIGITAL_GAIN_RED 0x0210
#define P_MT9F002_SMIA_DIGITAL_GAIN_BLUE 0x0212
#define P_MT9F002_SMIA_DIGITAL_GAIN_GREENB 0x0214
#define P_MT9F002_SMIA_VT_PIX_CLK_DIV 0x0300
#define P_MT9F002_SMIA_VT_SYS_CLK_DIV 0x0302
#define P_MT9F002_SMIA_PRE_PLL_CLK_DIV 0x0304
#define P_MT9F002_SMIA_PLL_MULTIPLIER 0x0306
#define P_MT9F002_SMIA_OP_PIX_CLK_DIV 0x0308
#define P_MT9F002_SMIA_OP_SYS_CLK_DIV 0x030A
#define P_MT9F002_SMIA_FRAME_LENGTH_LINES 0x0340
#define P_MT9F002_SMIA_LINE_LENGTH_PCK 0x0342
#define P_MT9F002_SMIA_X_ADDR_START 0x0344
#define P_MT9F002_SMIA_Y_ADDR_START 0x0346
#define P_MT9F002_SMIA_X_ADDR_END 0x0348
#define P_MT9F002_SMIA_Y_ADDR_END 0x034A
#define P_MT9F002_SMIA_X_OUTPUT_SIZE 0x034C
#define P_MT9F002_SMIA_Y_OUTPUT_SIZE 0x034E
#define P_MT9F002_SMIA_X_EVEN_INC 0x0380
#define P_MT9F002_SMIA_X_ODD_INC 0x0382
#define P_MT9F002_SMIA_Y_EVEN_INC 0x0384
#define P_MT9F002_SMIA_Y_ODD_INC 0x0386
#define P_MT9F002_SMIA_SCALING_MODE 0x0400
#define P_MT9F002_SMIA_SPATIAL_SAMPLING 0x0402
#define P_MT9F002_SMIA_SCALE_M 0x0404
#define P_MT9F002_SMIA_SCALE_N 0x0406
#define P_MT9F002_SMIA_COMPRESSION_MODE 0x0500
#define P_MT9F002_SMIA_TEST_PATTERN_MODE 0x0600
#define P_MT9F002_SMIA_TEST_DATA_RED 0x0602
#define P_MT9F002_SMIA_TEST_DATA_GREENR 0x0604
#define P_MT9F002_SMIA_TEST_DATA_BLUE 0x0606
#define P_MT9F002_SMIA_TEST_DATA_GREENB 0x0608
#define P_MT9F002_SMIA_HORIZONTAL_CURSOR_WIDTH 0x060A
#define P_MT9F002_SMIA_HORIZONTAL_CURSOR_POSITION 0x060C
#define P_MT9F002_SMIA_VERTICAL_CURSOR_WIDTH 0x060E
#define P_MT9F002_SMIA_VERTICAL_CURSOR_POSITION 0x0610
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_0 0x0042
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_1 0x0044
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_2 0x0046
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_3 0x0048
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_4 0x004A
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_5 0x004C
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_6 0x004E
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_7 0x0050
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_8 0x0052
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_9 0x0054
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_10 0x0056
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_11 0x0058
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_12 0x005A
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_13 0x005C
#define P_REG_MT9F002_SMIA_FRAME_FORMAT_DESCRIPTOR_14 0x005E
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CAPABILITY 0x0080
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_MIN 0x0084
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_MAX 0x0086
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_STEP 0x0088
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_TYPE 0x008A
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_M0 0x008C
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_C0 0x008E
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_M1 0x0090
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_C1 0x0092
#define P_REG_MT9F002_SMIA_DATA_FORMAT_MODEL_TYPE 0x00C0
#define P_REG_MT9F002_SMIA_DATA_FORMAT_MODEL_SUBTYPE 0x00C1
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_0 0x00C2
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_1 0x00C4
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_2 0x00C6
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_3 0x00C8
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_4 0x00CA
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_5 0x00CC
#define P_REG_MT9F002_SMIA_DATA_FORMAT_DESCRIPTOR_6 0x00CE
#define P_REG_MT9F002_SMIA_MODE_SELECT 0x0100
#define P_REG_MT9F002_SMIA_IMAGE_ORIENTATION 0x0101
#define P_REG_MT9F002_SMIA_SOFTWARE_RESET 0x0103
#define P_REG_MT9F002_SMIA_GROUPED_PARAMETER_HOLD 0x0104
#define P_REG_MT9F002_SMIA_MASK_CORRUPTED_FRAMES 0x0105
#define P_REG_MT9F002_SMIA_CCP2_CHANNEL_IDENTIFIER 0x0110
#define P_REG_MT9F002_SMIA_CCP2_SIGNALLING_MODE 0x0111
#define P_REG_MT9F002_SMIA_CCP_DATA_FORMAT 0x0112
#define P_REG_MT9F002_SMIA_GAIN_MODE 0x0120
#define P_REG_MT9F002_SMIA_FINE_INTEGRATION_TIME 0x0200
#define P_REG_MT9F002_SMIA_COARSE_INTEGRATION_TIME 0x0202
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_GLOBAL 0x0204
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_GREENR 0x0206
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_RED 0x0208
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_BLUE 0x020A
#define P_REG_MT9F002_SMIA_ANALOG_GAIN_CODE_GREENB 0x020C
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_GREENR 0x020E
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_RED 0x0210
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_BLUE 0x0212
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_GREENB 0x0214
#define P_REG_MT9F002_SMIA_VT_PIX_CLK_DIV 0x0300
#define P_REG_MT9F002_SMIA_VT_SYS_CLK_DIV 0x0302
#define P_REG_MT9F002_SMIA_PRE_PLL_CLK_DIV 0x0304
#define P_REG_MT9F002_SMIA_PLL_MULTIPLIER 0x0306
#define P_REG_MT9F002_SMIA_OP_PIX_CLK_DIV 0x0308
#define P_REG_MT9F002_SMIA_OP_SYS_CLK_DIV 0x030A
#define P_REG_MT9F002_SMIA_FRAME_LENGTH_LINES 0x0340
#define P_REG_MT9F002_SMIA_LINE_LENGTH_PCK 0x0342
#define P_REG_MT9F002_SMIA_X_ADDR_START 0x0344
#define P_REG_MT9F002_SMIA_Y_ADDR_START 0x0346
#define P_REG_MT9F002_SMIA_X_ADDR_END 0x0348
#define P_REG_MT9F002_SMIA_Y_ADDR_END 0x034A
#define P_REG_MT9F002_SMIA_X_OUTPUT_SIZE 0x034C
#define P_REG_MT9F002_SMIA_Y_OUTPUT_SIZE 0x034E
#define P_REG_MT9F002_SMIA_X_EVEN_INC 0x0380
#define P_REG_MT9F002_SMIA_X_ODD_INC 0x0382
#define P_REG_MT9F002_SMIA_Y_EVEN_INC 0x0384
#define P_REG_MT9F002_SMIA_Y_ODD_INC 0x0386
#define P_REG_MT9F002_SMIA_SCALING_MODE 0x0400
#define P_REG_MT9F002_SMIA_SPATIAL_SAMPLING 0x0402
#define P_REG_MT9F002_SMIA_SCALE_M 0x0404
#define P_REG_MT9F002_SMIA_SCALE_N 0x0406
#define P_REG_MT9F002_SMIA_COMPRESSION_MODE 0x0500
#define P_REG_MT9F002_SMIA_TEST_PATTERN_MODE 0x0600
#define P_REG_MT9F002_SMIA_TEST_DATA_RED 0x0602
#define P_REG_MT9F002_SMIA_TEST_DATA_GREENR 0x0604
#define P_REG_MT9F002_SMIA_TEST_DATA_BLUE 0x0606
#define P_REG_MT9F002_SMIA_TEST_DATA_GREENB 0x0608
#define P_REG_MT9F002_SMIA_HORIZONTAL_CURSOR_WIDTH 0x060A
#define P_REG_MT9F002_SMIA_HORIZONTAL_CURSOR_POSITION 0x060C
#define P_REG_MT9F002_SMIA_VERTICAL_CURSOR_WIDTH 0x060E
#define P_REG_MT9F002_SMIA_VERTICAL_CURSOR_POSITION 0x0610
/* SMIA Parameter Limit Register List */
#define P_MT9F002_SMIA_INTEGRATION_TIME_CAPABILITY 0x1000
#define P_MT9F002_SMIA_COARSE_INTEGRATION_TIME_MIN 0x1004
#define P_MT9F002_SMIA_COARSE_INTEGRATION_TIME_MAX_MARGIN 0x1006
#define P_MT9F002_SMIA_FINE_INTEGRATION_TIME_MIN 0x1008
#define P_MT9F002_SMIA_FINE_INTEGRATION_TIME_MAX_MARGIN 0x100A
#define P_MT9F002_SMIA_DIGITAL_GAIN_CAPABILITY 0x1080
#define P_MT9F002_SMIA_DIGITAL_GAIN_MIN 0x1084
#define P_MT9F002_SMIA_DIGITAL_GAIN_MAX 0x1086
#define P_MT9F002_SMIA_DIGITAL_GAIN_STEP_SIZE 0x1088
#define P_MT9F002_SMIA_MIN_EXT_CLK_FREQ_MHZ 0x1100
#define P_MT9F002_SMIA_MAX_EXT_CLK_FREQ_MHZ 0x1104
#define P_MT9F002_SMIA_MIN_PRE_PLL_CLK_DIV 0x1108
#define P_MT9F002_SMIA_MAX_PRE_PLL_CLK_DIV 0x110A
#define P_MT9F002_SMIA_MIN_PLL_IP_FREQ_MHZ 0x110C
#define P_MT9F002_SMIA_MAX_PLL_IP_FREQ_MHZ 0x1110
#define P_MT9F002_SMIA_MIN_PLL_MULTIPLIER 0x1114
#define P_MT9F002_SMIA_MAX_PLL_MULTIPLIER 0x1116
#define P_MT9F002_SMIA_MIN_PLL_OP_FREQ_MHZ 0x1118
#define P_MT9F002_SMIA_MAX_PLL_OP_FREQ_MHZ 0x111C
#define P_MT9F002_SMIA_MIN_VT_SYS_CLK_DIV 0x1120
#define P_MT9F002_SMIA_MAX_VT_SYS_CLK_DIV 0x1122
#define P_MT9F002_SMIA_MIN_VT_SYS_CLK_FREQ_MHZ 0x1124
#define P_MT9F002_SMIA_MAX_VT_SYS_CLK_FREQ_MHZ 0x1128
#define P_MT9F002_SMIA_MIN_VT_PIX_CLK_FREQ_MHZ 0x112C
#define P_MT9F002_SMIA_MAX_VT_PIX_CLK_FREQ_MHZ 0x1130
#define P_MT9F002_SMIA_MIN_VT_PIX_CLK_DIV 0x1134
#define P_MT9F002_SMIA_MAX_VT_PIX_CLK_DIV 0x1136
#define P_MT9F002_SMIA_MIN_FRAME_LENGTH_LINES 0x1140
#define P_MT9F002_SMIA_MAX_FRAME_LENGTH_LINES 0x1142
#define P_MT9F002_SMIA_MIN_LINE_LENGTH_PCK 0x1144
#define P_MT9F002_SMIA_MAX_LINE_LENGTH_PCK 0x1146
#define P_MT9F002_SMIA_MIN_LINE_BLANKING_PCK 0x1148
#define P_MT9F002_SMIA_MIN_FRAME_BLANKING_LINES 0x114A
#define P_MT9F002_SMIA_MIN_OP_SYS_CLK_DIV 0x1160
#define P_MT9F002_SMIA_MAX_OP_SYS_CLK_DIV 0x1162
#define P_MT9F002_SMIA_MIN_OP_SYS_CLK_FREQ_MHZ 0x1164
#define P_MT9F002_SMIA_MAX_OP_SYS_CLK_FREQ_MHZ 0x1168
#define P_MT9F002_SMIA_MIN_OP_PIX_CLK_DIV 0x116C
#define P_MT9F002_SMIA_MAX_OP_PIX_CLK_DIV 0x116E
#define P_MT9F002_SMIA_MIN_OP_PIX_CLK_FREQ_MHZ 0x1170
#define P_MT9F002_SMIA_MAX_OP_PIX_CLK_FREQ_MHZ 0x1174
#define P_MT9F002_SMIA_X_ADDR_MIN 0x1180
#define P_MT9F002_SMIA_Y_ADDR_MIN 0x1182
#define P_MT9F002_SMIA_X_ADDR_MAX 0x1184
#define P_MT9F002_SMIA_Y_ADDR_MAX 0x1186
#define P_MT9F002_SMIA_MIN_EVEN_INC 0x11C0
#define P_MT9F002_SMIA_MAX_EVEN_INC 0x11C2
#define P_MT9F002_SMIA_MIN_ODD_INC 0x11C4
#define P_MT9F002_SMIA_MAX_ODD_INC 0x11C6
#define P_MT9F002_SMIA_SCALING_CAPABILITY 0x1200
#define P_MT9F002_SMIA_SCALER_M_MIN 0x1204
#define P_MT9F002_SMIA_SCALER_M_MAX 0x1206
#define P_MT9F002_SMIA_SCALER_N_MIN 0x1208
#define P_MT9F002_SMIA_SCALER_N_MAX 0x120A
#define P_MT9F002_SMIA_COMPRESSION_CAPABILITY 0x1300
#define P_MT9F002_SMIA_MATRIX_ELEMENT_REDINRED 0x1400
#define P_MT9F002_SMIA_MATRIX_ELEMENT_GREENINRED 0x1402
#define P_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINRED 0x1404
#define P_MT9F002_SMIA_MATRIX_ELEMENT_REDINGREEN 0x1406
#define P_MT9F002_SMIA_MATRIX_ELEMENT_GREENINGREEN 0x1408
#define P_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINGREEN 0x140A
#define P_MT9F002_SMIA_MATRIX_ELEMENT_REDINBLUE 0x140C
#define P_MT9F002_SMIA_MATRIX_ELEMENT_GREENINBLUE 0x140E
#define P_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINBLUE 0x1410
#define P_REG_MT9F002_SMIA_INTEGRATION_TIME_CAPABILITY 0x1000
#define P_REG_MT9F002_SMIA_COARSE_INTEGRATION_TIME_MIN 0x1004
#define P_REG_MT9F002_SMIA_COARSE_INTEGRATION_TIME_MAX_MARGIN 0x1006
#define P_REG_MT9F002_SMIA_FINE_INTEGRATION_TIME_MIN 0x1008
#define P_REG_MT9F002_SMIA_FINE_INTEGRATION_TIME_MAX_MARGIN 0x100A
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_CAPABILITY 0x1080
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_MIN 0x1084
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_MAX 0x1086
#define P_REG_MT9F002_SMIA_DIGITAL_GAIN_STEP_SIZE 0x1088
#define P_REG_MT9F002_SMIA_MIN_EXT_CLK_FREQ_MHZ 0x1100
#define P_REG_MT9F002_SMIA_MAX_EXT_CLK_FREQ_MHZ 0x1104
#define P_REG_MT9F002_SMIA_MIN_PRE_PLL_CLK_DIV 0x1108
#define P_REG_MT9F002_SMIA_MAX_PRE_PLL_CLK_DIV 0x110A
#define P_REG_MT9F002_SMIA_MIN_PLL_IP_FREQ_MHZ 0x110C
#define P_REG_MT9F002_SMIA_MAX_PLL_IP_FREQ_MHZ 0x1110
#define P_REG_MT9F002_SMIA_MIN_PLL_MULTIPLIER 0x1114
#define P_REG_MT9F002_SMIA_MAX_PLL_MULTIPLIER 0x1116
#define P_REG_MT9F002_SMIA_MIN_PLL_OP_FREQ_MHZ 0x1118
#define P_REG_MT9F002_SMIA_MAX_PLL_OP_FREQ_MHZ 0x111C
#define P_REG_MT9F002_SMIA_MIN_VT_SYS_CLK_DIV 0x1120
#define P_REG_MT9F002_SMIA_MAX_VT_SYS_CLK_DIV 0x1122
#define P_REG_MT9F002_SMIA_MIN_VT_SYS_CLK_FREQ_MHZ 0x1124
#define P_REG_MT9F002_SMIA_MAX_VT_SYS_CLK_FREQ_MHZ 0x1128
#define P_REG_MT9F002_SMIA_MIN_VT_PIX_CLK_FREQ_MHZ 0x112C
#define P_REG_MT9F002_SMIA_MAX_VT_PIX_CLK_FREQ_MHZ 0x1130
#define P_REG_MT9F002_SMIA_MIN_VT_PIX_CLK_DIV 0x1134
#define P_REG_MT9F002_SMIA_MAX_VT_PIX_CLK_DIV 0x1136
#define P_REG_MT9F002_SMIA_MIN_FRAME_LENGTH_LINES 0x1140
#define P_REG_MT9F002_SMIA_MAX_FRAME_LENGTH_LINES 0x1142
#define P_REG_MT9F002_SMIA_MIN_LINE_LENGTH_PCK 0x1144
#define P_REG_MT9F002_SMIA_MAX_LINE_LENGTH_PCK 0x1146
#define P_REG_MT9F002_SMIA_MIN_LINE_BLANKING_PCK 0x1148
#define P_REG_MT9F002_SMIA_MIN_FRAME_BLANKING_LINES 0x114A
#define P_REG_MT9F002_SMIA_MIN_OP_SYS_CLK_DIV 0x1160
#define P_REG_MT9F002_SMIA_MAX_OP_SYS_CLK_DIV 0x1162
#define P_REG_MT9F002_SMIA_MIN_OP_SYS_CLK_FREQ_MHZ 0x1164
#define P_REG_MT9F002_SMIA_MAX_OP_SYS_CLK_FREQ_MHZ 0x1168
#define P_REG_MT9F002_SMIA_MIN_OP_PIX_CLK_DIV 0x116C
#define P_REG_MT9F002_SMIA_MAX_OP_PIX_CLK_DIV 0x116E
#define P_REG_MT9F002_SMIA_MIN_OP_PIX_CLK_FREQ_MHZ 0x1170
#define P_REG_MT9F002_SMIA_MAX_OP_PIX_CLK_FREQ_MHZ 0x1174
#define P_REG_MT9F002_SMIA_X_ADDR_MIN 0x1180
#define P_REG_MT9F002_SMIA_Y_ADDR_MIN 0x1182
#define P_REG_MT9F002_SMIA_X_ADDR_MAX 0x1184
#define P_REG_MT9F002_SMIA_Y_ADDR_MAX 0x1186
#define P_REG_MT9F002_SMIA_MIN_EVEN_INC 0x11C0
#define P_REG_MT9F002_SMIA_MAX_EVEN_INC 0x11C2
#define P_REG_MT9F002_SMIA_MIN_ODD_INC 0x11C4
#define P_REG_MT9F002_SMIA_MAX_ODD_INC 0x11C6
#define P_REG_MT9F002_SMIA_SCALING_CAPABILITY 0x1200
#define P_REG_MT9F002_SMIA_SCALER_M_MIN 0x1204
#define P_REG_MT9F002_SMIA_SCALER_M_MAX 0x1206
#define P_REG_MT9F002_SMIA_SCALER_N_MIN 0x1208
#define P_REG_MT9F002_SMIA_SCALER_N_MAX 0x120A
#define P_REG_MT9F002_SMIA_COMPRESSION_CAPABILITY 0x1300
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_REDINRED 0x1400
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_GREENINRED 0x1402
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINRED 0x1404
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_REDINGREEN 0x1406
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_GREENINGREEN 0x1408
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINGREEN 0x140A
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_REDINBLUE 0x140C
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_GREENINBLUE 0x140E
#define P_REG_MT9F002_SMIA_MATRIX_ELEMENT_BLUEINBLUE 0x1410
/* Manufacturer Specific Register List */
#define P_MT9F002_MODEL_ID 0x3000
#define P_MT9F002_Y_ADDR_START 0x3002
#define P_MT9F002_X_ADDR_START 0x3004
#define P_MT9F002_Y_ADDR_END 0x3006
#define P_MT9F002_X_ADDR_END 0x3008
#define P_MT9F002_FRAME_LENGTH_LINES 0x300A
#define P_MT9F002_LINE_LENGTH_PCK 0x300C
#define P_MT9F002_FINE_CORRECTION 0x3010
#define P_MT9F002_COARSE_INTEGRATION_TIME 0x3012
#define P_MT9F002_FINE_INTEGRATION_TIME 0x3014
#define P_MT9F002_ROW_SPEED 0x3016
#define P_MT9F002_EXTRA_DELAY 0x3018
#define P_MT9F002_RESET_REGISTER 0x301A
#define P_MT9F002_MODE_SELECT 0x301C
#define P_MT9F002_IMAGE_ORIENTATION 0x301D
#define P_MT9F002_DATA_PEDESTAL 0x301E
#define P_MT9F002_SOFTWARE_RESET 0x3021
#define P_MT9F002_GROUPED_PARAMETER_HOLD 0x3022
#define P_MT9F002_MASK_CORRUPTED_FRAMES 0x3023
#define P_MT9F002_PIXEL_ORDER 0x3024
#define P_MT9F002_GPI_STATUS 0x3026
#define P_MT9F002_ANALOG_GAIN_CODE_GLOBAL 0x3028
#define P_MT9F002_ANALOG_GAIN_CODE_GREENR 0x302A
#define P_MT9F002_ANALOG_GAIN_CODE_RED 0x302C
#define P_MT9F002_ANALOG_GAIN_CODE_BLUE 0x302E
#define P_MT9F002_ANALOG_GAIN_CODE_GREENB 0x3030
#define P_MT9F002_DIGITAL_GAIN_GREENR 0x3032
#define P_MT9F002_DIGITAL_GAIN_RED 0x3034
#define P_MT9F002_DIGITAL_GAIN_BLUE 0x3036
#define P_MT9F002_DIGITAL_GAIN_GREENB 0x3038
#define P_MT9F002_SMIA_VERSION 0x303A
#define P_MT9F002_FRAME_COUNT 0x303B
#define P_MT9F002_FRAME_STATUS 0x303C
#define P_MT9F002_READ_MODE 0x3040
#define P_MT9F002_FLASH 0x3046
#define P_MT9F002_FLASH_COUNT 0x3048
#define P_MT9F002_GREEN1_GAIN 0x3056
#define P_MT9F002_BLUE_GAIN 0x3058
#define P_MT9F002_RED_GAIN 0x305A
#define P_MT9F002_GREEN2_GAIN 0x305C
#define P_MT9F002_GLOBAL_GAIN 0x305E
#define P_MT9F002_DATAPATH_STATUS 0x306A
#define P_MT9F002_DATAPATH_SELECT 0x306E
#define P_MT9F002_TEST_PATTERN_MODE 0x3070
#define P_MT9F002_TEST_DATA_RED 0x3072
#define P_MT9F002_TEST_DATA_GREENR 0x3074
#define P_MT9F002_TEST_DATA_BLUE 0x3076
#define P_MT9F002_TEST_DATA_GREENB 0x3078
#define P_MT9F002_TEST_RAW_MODE 0x307A
#define P_MT9F002_X_EVEN_INC 0x30A0
#define P_MT9F002_X_ODD_INC 0x30A2
#define P_MT9F002_Y_EVEN_INC 0x30A4
#define P_MT9F002_Y_ODD_INC 0x30A6
#define P_MT9F002_CALIB_GREEN1_ASC1 0x30A8
#define P_MT9F002_CALIB_BLUE_ASC1 0x30AA
#define P_MT9F002_CALIB_RED_ASC1 0x30AC
#define P_MT9F002_CALIB_GREEN2_ASC1 0x30AE
#define P_MT9F002_CALIB_GLOBAL 0x30BC
#define P_MT9F002_CALIB_CONTROL 0x30C0
#define P_MT9F002_CALIB_GREEN1 0x30C2
#define P_MT9F002_CALIB_BLUE 0x30C4
#define P_MT9F002_CALIB_RED 0x30C6
#define P_MT9F002_CALIB_GREEN2 0x30C8
#define P_MT9F002_CTX_CONTROL_REG 0x30E8
#define P_MT9F002_CTX_WR_DATA_REG 0x30EA
#define P_MT9F002_CTX_RD_DATA_REG 0x30EC
#define P_MT9F002_DARK_CONTROL3 0x30EE
#define P_MT9F002_OTPM_TCFG_READ_4B 0x3138
#define P_MT9F002_OTPM_CFG 0x3140
#define P_MT9F002_GLOBAL_FLASH_START 0x315A
#define P_MT9F002_GLOBAL_SEQ_TRIGGER 0x315E
#define P_MT9F002_GLOBAL_RST_END 0x3160
#define P_MT9F002_GLOBAL_SHUTTER_START 0x3162
#define P_MT9F002_GLOBAL_SHUTTER_START2 0x3164
#define P_MT9F002_GLOBAL_READ_START 0x3166
#define P_MT9F002_GLOBAL_READ_START2 0x3168
#define P_MT9F002_DAC_RSTLO 0x316A
#define P_MT9F002_ANALOG_CONTROL5 0x3178
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_0 0x31A0
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_1 0x31A2
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_2 0x31A4
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_3 0x31A6
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_4 0x31A8
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_5 0x31AA
#define P_MT9F002_SERIAL_FORMAT_DESCRIPTOR_6 0x31AC
#define P_MT9F002_SERIAL_FORMAT 0x31AE
#define P_MT9F002_FRAME_PREAMBLE 0x31B0
#define P_MT9F002_LINE_PREAMBLE 0x31B2
#define P_MT9F002_MIPI_TIMING_0 0x31B4
#define P_MT9F002_MIPI_TIMING_1 0x31B6
#define P_MT9F002_MIPI_TIMING_2 0x31B8
#define P_MT9F002_MIPI_TIMING_3 0x31BA
#define P_MT9F002_MIPI_TIMING_4 0x31BC
#define P_MT9F002_HISPI_TIMING 0x31C0
#define P_MT9F002_HISPI_CONTROL_STATUS 0x31C6
#define P_MT9F002_HORIZONTAL_CURSOR_POSITION 0x31E8
#define P_MT9F002_VERTICAL_CURSOR_POSITION 0x31EA
#define P_MT9F002_HORIZONTAL_CURSOR_WIDTH 0x31EC
#define P_MT9F002_VERTICAL_CURSOR_WIDTH 0x31EE
#define P_MT9F002_I2C_IDS_MIPI_DEFAULT 0x31F2
#define P_MT9F002_I2C_IDS 0x31FC
#define P_MT9F002_P_GR_P0Q0 0x3600
#define P_MT9F002_P_GR_P0Q1 0x3602
#define P_MT9F002_P_GR_P0Q2 0x3604
#define P_MT9F002_P_GR_P0Q3 0x3606
#define P_MT9F002_P_GR_P0Q4 0x3608
#define P_MT9F002_P_RD_P0Q0 0x360A
#define P_MT9F002_P_RD_P0Q1 0x360C
#define P_MT9F002_P_RD_P0Q2 0x360E
#define P_MT9F002_P_RD_P0Q3 0x3610
#define P_MT9F002_P_RD_P0Q4 0x3612
#define P_MT9F002_P_BL_P0Q0 0x3614
#define P_MT9F002_P_BL_P0Q1 0x3616
#define P_MT9F002_P_BL_P0Q2 0x3618
#define P_MT9F002_P_BL_P0Q3 0x361A
#define P_MT9F002_P_BL_P0Q4 0x361C
#define P_MT9F002_P_GB_P0Q0 0x361E
#define P_MT9F002_P_GB_P0Q1 0x3620
#define P_MT9F002_P_GB_P0Q2 0x3622
#define P_MT9F002_P_GB_P0Q3 0x3624
#define P_MT9F002_P_GB_P0Q4 0x3626
#define P_MT9F002_P_GR_P1Q0 0x3640
#define P_MT9F002_P_GR_P1Q1 0x3642
#define P_MT9F002_P_GR_P1Q2 0x3644
#define P_MT9F002_P_GR_P1Q3 0x3646
#define P_MT9F002_P_GR_P1Q4 0x3648
#define P_MT9F002_P_RD_P1Q0 0x364A
#define P_MT9F002_P_RD_P1Q1 0x364C
#define P_MT9F002_P_RD_P1Q2 0x364E
#define P_MT9F002_P_RD_P1Q3 0x3650
#define P_MT9F002_P_RD_P1Q4 0x3652
#define P_MT9F002_P_BL_P1Q0 0x3654
#define P_MT9F002_P_BL_P1Q1 0x3656
#define P_MT9F002_P_BL_P1Q2 0x3658
#define P_MT9F002_P_BL_P1Q3 0x365A
#define P_MT9F002_P_BL_P1Q4 0x365C
#define P_MT9F002_P_GB_P1Q0 0x365E
#define P_MT9F002_P_GB_P1Q1 0x3660
#define P_MT9F002_P_GB_P1Q2 0x3662
#define P_MT9F002_P_GB_P1Q3 0x3664
#define P_MT9F002_P_GB_P1Q4 0x3666
#define P_MT9F002_P_GR_P2Q0 0x3680
#define P_MT9F002_P_GR_P2Q1 0x3682
#define P_MT9F002_P_GR_P2Q2 0x3684
#define P_MT9F002_P_GR_P2Q3 0x3686
#define P_MT9F002_P_GR_P2Q4 0x3688
#define P_MT9F002_P_RD_P2Q0 0x368A
#define P_MT9F002_P_RD_P2Q1 0x368C
#define P_MT9F002_P_RD_P2Q2 0x368E
#define P_MT9F002_P_RD_P2Q3 0x3690
#define P_MT9F002_P_RD_P2Q4 0x3692
#define P_MT9F002_P_BL_P2Q0 0x3694
#define P_MT9F002_P_BL_P2Q1 0x3696
#define P_MT9F002_P_BL_P2Q2 0x3698
#define P_MT9F002_P_BL_P2Q3 0x369A
#define P_MT9F002_P_BL_P2Q4 0x369C
#define P_MT9F002_P_GB_P2Q0 0x369E
#define P_MT9F002_P_GB_P2Q1 0x36A0
#define P_MT9F002_P_GB_P2Q2 0x36A2
#define P_MT9F002_P_GB_P2Q3 0x36A4
#define P_MT9F002_P_GB_P2Q4 0x36A6
#define P_MT9F002_P_GR_P3Q0 0x36C0
#define P_MT9F002_P_GR_P3Q1 0x36C2
#define P_MT9F002_P_GR_P3Q2 0x36C4
#define P_MT9F002_P_GR_P3Q3 0x36C6
#define P_MT9F002_P_GR_P3Q4 0x36C8
#define P_MT9F002_P_RD_P3Q0 0x36CA
#define P_MT9F002_P_RD_P3Q1 0x36CC
#define P_MT9F002_P_RD_P3Q2 0x36CE
#define P_MT9F002_P_RD_P3Q3 0x36D0
#define P_MT9F002_P_RD_P3Q4 0x36D2
#define P_MT9F002_P_BL_P3Q0 0x36D4
#define P_MT9F002_P_BL_P3Q1 0x36D6
#define P_MT9F002_P_BL_P3Q2 0x36D8
#define P_MT9F002_P_BL_P3Q3 0x36DA
#define P_MT9F002_P_BL_P3Q4 0x36DC
#define P_MT9F002_P_GB_P3Q0 0x36DE
#define P_MT9F002_P_GB_P3Q1 0x36E0
#define P_MT9F002_P_GB_P3Q2 0x36E2
#define P_MT9F002_P_GB_P3Q3 0x36E4
#define P_MT9F002_P_GB_P3Q4 0x36E6
#define P_MT9F002_P_GR_P4Q0 0x3700
#define P_MT9F002_P_GR_P4Q1 0x3702
#define P_MT9F002_P_GR_P4Q2 0x3704
#define P_MT9F002_P_GR_P4Q3 0x3706
#define P_MT9F002_P_GR_P4Q4 0x3708
#define P_MT9F002_P_RD_P4Q0 0x370A
#define P_MT9F002_P_RD_P4Q1 0x370C
#define P_MT9F002_P_RD_P4Q2 0x370E
#define P_MT9F002_P_RD_P4Q3 0x3710
#define P_MT9F002_P_RD_P4Q4 0x3712
#define P_MT9F002_P_BL_P4Q0 0x3714
#define P_MT9F002_P_BL_P4Q1 0x3716
#define P_MT9F002_P_BL_P4Q2 0x3718
#define P_MT9F002_P_BL_P4Q3 0x371A
#define P_MT9F002_P_BL_P4Q4 0x371C
#define P_MT9F002_P_GB_P4Q0 0x371E
#define P_MT9F002_P_GB_P4Q1 0x3720
#define P_MT9F002_P_GB_P4Q2 0x3722
#define P_MT9F002_P_GB_P4Q3 0x3724
#define P_MT9F002_P_GB_P4Q4 0x3726
#define P_MT9F002_POLY_SC_ENABLE 0x3780
#define P_MT9F002_POLY_ORIGIN_C 0x3782
#define P_MT9F002_POLY_ORIGIN_R 0x3784
#define P_MT9F002_P_GR_Q5 0x37C0
#define P_MT9F002_P_RD_Q5 0x37C2
#define P_MT9F002_P_BL_Q5 0x37C4
#define P_MT9F002_P_GB_Q5 0x37C6
#define P_MT9F002_DAC_LD_FBIAS 0x3EF8
#define P_REG_MT9F002_MODEL_ID 0x3000
#define P_REG_MT9F002_Y_ADDR_START 0x3002
#define P_REG_MT9F002_X_ADDR_START 0x3004
#define P_REG_MT9F002_Y_ADDR_END 0x3006
#define P_REG_MT9F002_X_ADDR_END 0x3008
#define P_REG_MT9F002_FRAME_LENGTH_LINES 0x300A
#define P_REG_MT9F002_LINE_LENGTH_PCK 0x300C
#define P_REG_MT9F002_FINE_CORRECTION 0x3010
#define P_REG_MT9F002_COARSE_INTEGRATION_TIME 0x3012
#define P_REG_MT9F002_FINE_INTEGRATION_TIME 0x3014
#define P_REG_MT9F002_ROW_SPEED 0x3016
#define P_REG_MT9F002_EXTRA_DELAY 0x3018
#define P_REG_MT9F002_RESET_REGISTER 0x301A
#define P_REG_MT9F002_MODE_SELECT 0x301C
#define P_REG_MT9F002_IMAGE_ORIENTATION 0x301D
#define P_REG_MT9F002_DATA_PEDESTAL 0x301E
#define P_REG_MT9F002_SOFTWARE_RESET 0x3021
#define P_REG_MT9F002_GROUPED_PARAMETER_HOLD 0x3022
#define P_REG_MT9F002_MASK_CORRUPTED_FRAMES 0x3023
#define P_REG_MT9F002_PIXEL_ORDER 0x3024
#define P_REG_MT9F002_GPI_STATUS 0x3026
#define P_REG_MT9F002_ANALOG_GAIN_CODE_GLOBAL 0x3028
#define P_REG_MT9F002_ANALOG_GAIN_CODE_GREENR 0x302A
#define P_REG_MT9F002_ANALOG_GAIN_CODE_RED 0x302C
#define P_REG_MT9F002_ANALOG_GAIN_CODE_BLUE 0x302E
#define P_REG_MT9F002_ANALOG_GAIN_CODE_GREENB 0x3030
#define P_REG_MT9F002_DIGITAL_GAIN_GREENR 0x3032
#define P_REG_MT9F002_DIGITAL_GAIN_RED 0x3034
#define P_REG_MT9F002_DIGITAL_GAIN_BLUE 0x3036
#define P_REG_MT9F002_DIGITAL_GAIN_GREENB 0x3038
#define P_REG_MT9F002_SMIA_VERSION 0x303A
#define P_REG_MT9F002_FRAME_COUNT 0x303B
#define P_REG_MT9F002_FRAME_STATUS 0x303C
#define P_REG_MT9F002_READ_MODE 0x3040
#define P_REG_MT9F002_FLASH 0x3046
#define P_REG_MT9F002_FLASH_COUNT 0x3048
#define P_REG_MT9F002_GREEN1_GAIN 0x3056
#define P_REG_MT9F002_BLUE_GAIN 0x3058
#define P_REG_MT9F002_RED_GAIN 0x305A
#define P_REG_MT9F002_GREEN2_GAIN 0x305C
#define P_REG_MT9F002_GLOBAL_GAIN 0x305E
#define P_REG_MT9F002_DATAPATH_STATUS 0x306A
#define P_REG_MT9F002_DATAPATH_SELECT 0x306E
#define P_REG_MT9F002_TEST_PATTERN_MODE 0x3070
#define P_REG_MT9F002_TEST_DATA_RED 0x3072
#define P_REG_MT9F002_TEST_DATA_GREENR 0x3074
#define P_REG_MT9F002_TEST_DATA_BLUE 0x3076
#define P_REG_MT9F002_TEST_DATA_GREENB 0x3078
#define P_REG_MT9F002_TEST_RAW_MODE 0x307A
#define P_REG_MT9F002_X_EVEN_INC 0x30A0
#define P_REG_MT9F002_X_ODD_INC 0x30A2
#define P_REG_MT9F002_Y_EVEN_INC 0x30A4
#define P_REG_MT9F002_Y_ODD_INC 0x30A6
#define P_REG_MT9F002_CALIB_GREEN1_ASC1 0x30A8
#define P_REG_MT9F002_CALIB_BLUE_ASC1 0x30AA
#define P_REG_MT9F002_CALIB_RED_ASC1 0x30AC
#define P_REG_MT9F002_CALIB_GREEN2_ASC1 0x30AE
#define P_REG_MT9F002_CALIB_GLOBAL 0x30BC
#define P_REG_MT9F002_CALIB_CONTROL 0x30C0
#define P_REG_MT9F002_CALIB_GREEN1 0x30C2
#define P_REG_MT9F002_CALIB_BLUE 0x30C4
#define P_REG_MT9F002_CALIB_RED 0x30C6
#define P_REG_MT9F002_CALIB_GREEN2 0x30C8
#define P_REG_MT9F002_CTX_CONTROL_REG 0x30E8
#define P_REG_MT9F002_CTX_WR_DATA_REG 0x30EA
#define P_REG_MT9F002_CTX_RD_DATA_REG 0x30EC
#define P_REG_MT9F002_DARK_CONTROL3 0x30EE
#define P_REG_MT9F002_OTPM_TCFG_READ_4B 0x3138
#define P_REG_MT9F002_OTPM_CFG 0x3140
#define P_REG_MT9F002_GLOBAL_FLASH_START 0x315A
#define P_REG_MT9F002_GLOBAL_SEQ_TRIGGER 0x315E
#define P_REG_MT9F002_GLOBAL_RST_END 0x3160
#define P_REG_MT9F002_GLOBAL_SHUTTER_START 0x3162
#define P_REG_MT9F002_GLOBAL_SHUTTER_START2 0x3164
#define P_REG_MT9F002_GLOBAL_READ_START 0x3166
#define P_REG_MT9F002_GLOBAL_READ_START2 0x3168
#define P_REG_MT9F002_DAC_RSTLO 0x316A
#define P_REG_MT9F002_ANALOG_CONTROL5 0x3178
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_0 0x31A0
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_1 0x31A2
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_2 0x31A4
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_3 0x31A6
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_4 0x31A8
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_5 0x31AA
#define P_REG_MT9F002_SERIAL_FORMAT_DESCRIPTOR_6 0x31AC
#define P_REG_MT9F002_SERIAL_FORMAT 0x31AE
#define P_REG_MT9F002_FRAME_PREAMBLE 0x31B0
#define P_REG_MT9F002_LINE_PREAMBLE 0x31B2
#define P_REG_MT9F002_MIPI_TIMING_0 0x31B4
#define P_REG_MT9F002_MIPI_TIMING_1 0x31B6
#define P_REG_MT9F002_MIPI_TIMING_2 0x31B8
#define P_REG_MT9F002_MIPI_TIMING_3 0x31BA
#define P_REG_MT9F002_MIPI_TIMING_4 0x31BC
#define P_REG_MT9F002_HISPI_TIMING 0x31C0
#define P_REG_MT9F002_HISPI_CONTROL_STATUS 0x31C6
#define P_REG_MT9F002_HORIZONTAL_CURSOR_POSITION 0x31E8
#define P_REG_MT9F002_VERTICAL_CURSOR_POSITION 0x31EA
#define P_REG_MT9F002_HORIZONTAL_CURSOR_WIDTH 0x31EC
#define P_REG_MT9F002_VERTICAL_CURSOR_WIDTH 0x31EE
#define P_REG_MT9F002_I2C_IDS_MIPI_DEFAULT 0x31F2
#define P_REG_MT9F002_I2C_IDS 0x31FC
#define P_REG_MT9F002_P_GR_P0Q0 0x3600
#define P_REG_MT9F002_P_GR_P0Q1 0x3602
#define P_REG_MT9F002_P_GR_P0Q2 0x3604
#define P_REG_MT9F002_P_GR_P0Q3 0x3606
#define P_REG_MT9F002_P_GR_P0Q4 0x3608
#define P_REG_MT9F002_P_RD_P0Q0 0x360A
#define P_REG_MT9F002_P_RD_P0Q1 0x360C
#define P_REG_MT9F002_P_RD_P0Q2 0x360E
#define P_REG_MT9F002_P_RD_P0Q3 0x3610
#define P_REG_MT9F002_P_RD_P0Q4 0x3612
#define P_REG_MT9F002_P_BL_P0Q0 0x3614
#define P_REG_MT9F002_P_BL_P0Q1 0x3616
#define P_REG_MT9F002_P_BL_P0Q2 0x3618
#define P_REG_MT9F002_P_BL_P0Q3 0x361A
#define P_REG_MT9F002_P_BL_P0Q4 0x361C
#define P_REG_MT9F002_P_GB_P0Q0 0x361E
#define P_REG_MT9F002_P_GB_P0Q1 0x3620
#define P_REG_MT9F002_P_GB_P0Q2 0x3622
#define P_REG_MT9F002_P_GB_P0Q3 0x3624
#define P_REG_MT9F002_P_GB_P0Q4 0x3626
#define P_REG_MT9F002_P_GR_P1Q0 0x3640
#define P_REG_MT9F002_P_GR_P1Q1 0x3642
#define P_REG_MT9F002_P_GR_P1Q2 0x3644
#define P_REG_MT9F002_P_GR_P1Q3 0x3646
#define P_REG_MT9F002_P_GR_P1Q4 0x3648
#define P_REG_MT9F002_P_RD_P1Q0 0x364A
#define P_REG_MT9F002_P_RD_P1Q1 0x364C
#define P_REG_MT9F002_P_RD_P1Q2 0x364E
#define P_REG_MT9F002_P_RD_P1Q3 0x3650
#define P_REG_MT9F002_P_RD_P1Q4 0x3652
#define P_REG_MT9F002_P_BL_P1Q0 0x3654
#define P_REG_MT9F002_P_BL_P1Q1 0x3656
#define P_REG_MT9F002_P_BL_P1Q2 0x3658
#define P_REG_MT9F002_P_BL_P1Q3 0x365A
#define P_REG_MT9F002_P_BL_P1Q4 0x365C
#define P_REG_MT9F002_P_GB_P1Q0 0x365E
#define P_REG_MT9F002_P_GB_P1Q1 0x3660
#define P_REG_MT9F002_P_GB_P1Q2 0x3662
#define P_REG_MT9F002_P_GB_P1Q3 0x3664
#define P_REG_MT9F002_P_GB_P1Q4 0x3666
#define P_REG_MT9F002_P_GR_P2Q0 0x3680
#define P_REG_MT9F002_P_GR_P2Q1 0x3682
#define P_REG_MT9F002_P_GR_P2Q2 0x3684
#define P_REG_MT9F002_P_GR_P2Q3 0x3686
#define P_REG_MT9F002_P_GR_P2Q4 0x3688
#define P_REG_MT9F002_P_RD_P2Q0 0x368A
#define P_REG_MT9F002_P_RD_P2Q1 0x368C
#define P_REG_MT9F002_P_RD_P2Q2 0x368E
#define P_REG_MT9F002_P_RD_P2Q3 0x3690
#define P_REG_MT9F002_P_RD_P2Q4 0x3692
#define P_REG_MT9F002_P_BL_P2Q0 0x3694
#define P_REG_MT9F002_P_BL_P2Q1 0x3696
#define P_REG_MT9F002_P_BL_P2Q2 0x3698
#define P_REG_MT9F002_P_BL_P2Q3 0x369A
#define P_REG_MT9F002_P_BL_P2Q4 0x369C
#define P_REG_MT9F002_P_GB_P2Q0 0x369E
#define P_REG_MT9F002_P_GB_P2Q1 0x36A0
#define P_REG_MT9F002_P_GB_P2Q2 0x36A2
#define P_REG_MT9F002_P_GB_P2Q3 0x36A4
#define P_REG_MT9F002_P_GB_P2Q4 0x36A6
#define P_REG_MT9F002_P_GR_P3Q0 0x36C0
#define P_REG_MT9F002_P_GR_P3Q1 0x36C2
#define P_REG_MT9F002_P_GR_P3Q2 0x36C4
#define P_REG_MT9F002_P_GR_P3Q3 0x36C6
#define P_REG_MT9F002_P_GR_P3Q4 0x36C8
#define P_REG_MT9F002_P_RD_P3Q0 0x36CA
#define P_REG_MT9F002_P_RD_P3Q1 0x36CC
#define P_REG_MT9F002_P_RD_P3Q2 0x36CE
#define P_REG_MT9F002_P_RD_P3Q3 0x36D0
#define P_REG_MT9F002_P_RD_P3Q4 0x36D2
#define P_REG_MT9F002_P_BL_P3Q0 0x36D4
#define P_REG_MT9F002_P_BL_P3Q1 0x36D6
#define P_REG_MT9F002_P_BL_P3Q2 0x36D8
#define P_REG_MT9F002_P_BL_P3Q3 0x36DA
#define P_REG_MT9F002_P_BL_P3Q4 0x36DC
#define P_REG_MT9F002_P_GB_P3Q0 0x36DE
#define P_REG_MT9F002_P_GB_P3Q1 0x36E0
#define P_REG_MT9F002_P_GB_P3Q2 0x36E2
#define P_REG_MT9F002_P_GB_P3Q3 0x36E4
#define P_REG_MT9F002_P_GB_P3Q4 0x36E6
#define P_REG_MT9F002_P_GR_P4Q0 0x3700
#define P_REG_MT9F002_P_GR_P4Q1 0x3702
#define P_REG_MT9F002_P_GR_P4Q2 0x3704
#define P_REG_MT9F002_P_GR_P4Q3 0x3706
#define P_REG_MT9F002_P_GR_P4Q4 0x3708
#define P_REG_MT9F002_P_RD_P4Q0 0x370A
#define P_REG_MT9F002_P_RD_P4Q1 0x370C
#define P_REG_MT9F002_P_RD_P4Q2 0x370E
#define P_REG_MT9F002_P_RD_P4Q3 0x3710
#define P_REG_MT9F002_P_RD_P4Q4 0x3712
#define P_REG_MT9F002_P_BL_P4Q0 0x3714
#define P_REG_MT9F002_P_BL_P4Q1 0x3716
#define P_REG_MT9F002_P_BL_P4Q2 0x3718
#define P_REG_MT9F002_P_BL_P4Q3 0x371A
#define P_REG_MT9F002_P_BL_P4Q4 0x371C
#define P_REG_MT9F002_P_GB_P4Q0 0x371E
#define P_REG_MT9F002_P_GB_P4Q1 0x3720
#define P_REG_MT9F002_P_GB_P4Q2 0x3722
#define P_REG_MT9F002_P_GB_P4Q3 0x3724
#define P_REG_MT9F002_P_GB_P4Q4 0x3726
#define P_REG_MT9F002_POLY_SC_ENABLE 0x3780
#define P_REG_MT9F002_POLY_ORIGIN_C 0x3782
#define P_REG_MT9F002_POLY_ORIGIN_R 0x3784
#define P_REG_MT9F002_P_GR_Q5 0x37C0
#define P_REG_MT9F002_P_RD_Q5 0x37C2
#define P_REG_MT9F002_P_BL_Q5 0x37C4
#define P_REG_MT9F002_P_GB_Q5 0x37C6
#define P_REG_MT9F002_DAC_LD_FBIAS 0x3EF8
//#define P_REG(x) x
//#define P_MT9F002_MODEL_ID 4
//#define P_MT9F002_FINE_CORRECTION 5
//#define P_REG_HADDR(x) pi2a[2*(x)+1]>>8 & 0xff
//#define P_REG_LADDR(x) pi2a[2*(x)+1] & 0xff
/** Detect one of Micron/Aptina/On Semiconductor sensors MT9M*, MT9D*,MT9T*, andMT9P* with parallel interface */
int mt9f002_pgm_detectsensor (int sensor_port, ///< sensor port number (0..3)
......
src/drivers/elphel/mt9x001.c
View file @ 71913108
......@@ -390,6 +390,69 @@
#define MD9(x)
#endif
/**
LUT to map SENSOR_REGSxxx to internal sensor register addresses
* needed for any sensor
* For better manual mapping:
- even elements are SENSOR_REGSxxx,
- odd elements are sensor's register addresses.
* has to be at least 16-bit/entry for 16 bit addresses
* (for MT9X001 it's a 1-to-1 mapping)
*/
const unsigned short mt9x001_par2addr[] = {
P_MT9X001_CHIPVER, P_MT9X001_CHIPVER,
P_MT9X001_ROWSTART, P_MT9X001_ROWSTART,
P_MT9X001_COLSTART, P_MT9X001_COLSTART,
P_MT9X001_HEIGHT, P_MT9X001_HEIGHT,
P_MT9X001_WIDTH, P_MT9X001_WIDTH,
P_MT9X001_HORBLANK, P_MT9X001_HORBLANK,
P_MT9X001_VERTBLANK, P_MT9X001_VERTBLANK,
P_MT9X001_OUTCTRL, P_MT9X001_OUTCTRL,
P_MT9X001_SHTRWDTHU, P_MT9X001_SHTRWDTHU,
P_MT9X001_SHTRWDTH, P_MT9X001_SHTRWDTH,
P_MT9X001_PXLCTL, P_MT9X001_PXLCTL,
P_MT9X001_RESTART, P_MT9X001_RESTART,
P_MT9X001_SHTRDLY, P_MT9X001_SHTRDLY,
P_MT9X001_RESET, P_MT9X001_RESET,
P_MT9X001_PLL1, P_MT9X001_PLL1,
P_MT9X001_PLL2, P_MT9X001_PLL2,
P_MT9X001_PLL3, P_MT9X001_PLL3,
P_MT9X001_RMODE1, P_MT9X001_RMODE1,
P_MT9X001_RMODE2, P_MT9X001_RMODE2,
P_MT9X001_RMODE3, P_MT9X001_RMODE3,
P_MT9X001_RAM, P_MT9X001_RAM,
P_MT9X001_CAM, P_MT9X001_CAM,
P_MT9X001_GREEN1, P_MT9X001_GREEN1,
P_MT9X001_BLUE, P_MT9X001_BLUE,
P_MT9X001_RED, P_MT9X001_RED,
P_MT9X001_GREEN2, P_MT9X001_GREEN2,
P_MT9X001_ALLGAINS, P_MT9X001_ALLGAINS,
P_MT9X001_DESIRBLACK, P_MT9X001_DESIRBLACK,
P_MT9X001_ROWRBLACKOFFS, P_MT9X001_ROWRBLACKOFFS,
P_MT9X001_COARSETHRSH, P_MT9X001_COARSETHRSH,
P_MT9X001_CALTHRESH, P_MT9X001_CALTHRESH,
P_MT9X001_CALGREEN1, P_MT9X001_CALGREEN1,
P_MT9X001_CALGREEN2, P_MT9X001_CALGREEN2,
P_MT9X001_CALCTRL, P_MT9X001_CALCTRL,
P_MT9X001_CALRED, P_MT9X001_CALRED,
P_MT9X001_CALBLUE, P_MT9X001_CALBLUE,
P_MT9X001_7F, P_MT9X001_7F,
P_MT9X001_TEST, P_MT9X001_TEST,
P_MT9X001_CHIPEN, P_MT9X001_CHIPEN,
P_MT9X001_CHIPEN1, P_MT9X001_CHIPEN1,
0xffff // END indicator
};
/**
* get at least one parameter for a page
*/
const unsigned short mt9x001_pages[] = {
P_MT9X001_CHIPVER,
P_MT9X001_ROWSTART, // for testing
0x3102, // for testing (page 0x31)
0xffff // END indicator
};
static struct device *g_dev_ptr=NULL; ///< Global pointer to basic device structure. This pointer is used in debugfs output functions
void mt9x001_set_device(struct device *dev) // do nothing, now it has it's own device
{
......
src/drivers/elphel/mt9x001.h
View file @ 71913108
......@@ -15,6 +15,10 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
#ifndef _MT9X001_H
#define _MT9X001_H
#define MT9M001_PARTID 0x8411 ///< MT9M00* PartID register value
#define MT9D001_PARTID 0x8511 ///< MT9D00* PartID register value
#define MT9T001_PARTID 0x1601 ///< MT9T00* PartID register value
......@@ -186,6 +190,19 @@
///< <li> --+bit 0 - 1 - normal operation, 0 - stop readout (same as reg 0x07, bit 1)
///< <li> --+bit 1 - 0 - normal, appropriate changes are made at frame boudary. 1 - do not update (same as reg 7 bit 0)</ul>
/** Detect one of Micron/Aptina/On Semiconductor sensors MT9M*, MT9D*,MT9T*, andMT9P* with parallel interface */
/**
LUT to map SENSOR_REGSxxx to internal sensor register addresses
* needed for any sensor
* For better manual mapping:
- even elements are SENSOR_REGSxxx,
- odd elements are sensor's register addresses.
* has to be at least 16-bit/entry for 16 bit addresses
* (for MT9X001 it's a 1-to-1 mapping)
*/
extern const unsigned short mt9x001_par2addr[];
extern const unsigned short mt9x001_pages[];
int mt9x001_pgm_detectsensor (int sensor_port, ///< sensor port number (0..3)
struct sensor_t * sensor, ///< sensor static parameters (capabilities)
struct framepars_t * thispars, ///< sensor current parameters
......@@ -201,3 +218,5 @@ int program_woi_mt9x001(int nonstop);
int program_gains_mt9x001(void);
int program_exposure_mt9x001(void);
#endif
#endif
src/drivers/elphel/pgm_functions.c
View file @ 71913108
......@@ -215,7 +215,7 @@
#include "x393.h"
#include "sensor_i2c.h"
#include "x393_videomem.h"
#include "detect_sensors.h"
//#include "detect_sensors.h"
#include "x393_fpga_functions.h"
// NC393 debug macros
......@@ -422,7 +422,8 @@ int pgm_detectsensor (int sensor_port, ///< sensor port number (
i2c_stop_run_reset (sensor_port, I2C_CMD_RUN); // also programs status update
// TODO: move to specific sensor driver
legacy_i2c(1<<sensor_port); // Setup i2c pages for legacy i2c commands. TODO NC393: update for compatibility with 14MPix
//legacy_i2c(1<<sensor_port); // Setup i2c pages for legacy i2c commands. TODO NC393: update for compatibility with 14MPix
register_i2c_sensor(1<<sensor_port);
#ifdef INIT_IN_TRIGGERED
camsync_mode.trig = 1; // start in stopped triggered mode
......
src/drivers/elphel/pgm_functions.h
View file @ 71913108
......@@ -16,7 +16,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
#ifndef PGM_FUNCTIONS_H
#define PGM_FUNCTIONS_H
#include "sensor_i2c.h"
#include "detect_sensors.h"
#define COLOR_MARGINS 2 // add this many pixels each side
#define X313_TIMESTAMPLEN 28 // pixels used for timestamp (in linescan mode added after the line)
#define X393_TILEHOR 16
......@@ -63,6 +68,17 @@ unsigned long sensor_to_camsync(unsigned long pixel_time, unsigned long sensor_c
#define SETFRAMEPARS_COND(p,v) { if (unlikely((v)!=thispars->pars[(p) & 0xffff])) { pars_to_update[nupdate ].num= (p) ; pars_to_update[nupdate++].val=(v);} }
//#define SETFRAMEPARS_COND(p,v) { if (unlikely((v)!=thispars->pars[p])) { pars_to_update[nupdate ].num= (p) ; pars_to_update[nupdate++].val=(v);} }
/*
struct sensor_port_config_t {
u32 mux; ///< Sensor multiplexer, currently 0 (SENSOR_DETECT, SENSOR_MUX_10359 or SENSOR_NONE)
u32 sensor[MAX_SENSORS]; ///< Without mux only [0] is used, with 10359 - 0..2 are used (i2c addressing is shifted so 0 is broadcast)
u16 par2addr[MAX_SENSORS][MAX_SENSOR_REGS]; ///< Big LUT. SENSOR_REGSxxx par to sensor reg 'yyy' internal address: haddr+laddr for 16 bit
u8 haddr2rec[MAX_SENSORS][MAX_FPGA_RECS]; ///< Big LUT (but almost empty). Sensor's page address (haddr of reg addr) to fpga i2c record number (fpga line#)
unsigned short *pages_ptr[MAX_SENSORS];
};
extern struct sensor_port_config_t *pSensorPortConfig;
*/
/**Set parameter for the sensor register and send to hardware i2c sequencer
* @param port Sensor port number
......@@ -70,10 +86,10 @@ unsigned long sensor_to_camsync(unsigned long pixel_time, unsigned long sensor_c
* @param sa7 I2C slave address, 7 bit
* @param reg sensor register address (8-bit)
* @param data value to set (16 bits) */
#define SET_SENSOR_PAR(port,frame,sa7,reg,data) { pars_to_update[nupdate ].num= P_SENSOR_REGS+(reg) ;\
pars_to_update[nupdate++].val=(data);\
X3X3_I2C_SEND2((port),(frame), (sa7), (reg), (data)); \
}
#define SET_SENSOR_PAR(port,frame,sa7,reg,data) { pars_to_update[nupdate ].num= P_SENSOR_REGS+(reg);\
pars_to_update[nupdate++].val=(data);\
X3X3_I2C_SEND2((port),(frame), (sa7), (reg), (data));\
}
/**Set parameter for the same register in multiple multiplexed sensors and send to hardware i2c sequencer
* Similar to SET_SENSOR_PAR, but broadcast set for parameters with individual values.
* Updates both "parent" parameter (used without multiplexer) and the individual ones
......@@ -238,3 +254,4 @@ unsigned long sensor_to_camsync(unsigned long pixel_time, unsigned long sensor_c
} \
}
#endif
src/drivers/elphel/sensor_common.c
View file @ 71913108
......@@ -23,7 +23,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define DEBUG
//copied from cxi2c.c - TODO:remove unneeded
#include <linux/sched.h>
#include <linux/kernel.h>
......@@ -31,11 +31,13 @@
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/platform_device.h>
#include <asm/outercache.h>
#include <asm/cacheflush.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <asm/outercache.h>
#include <asm/cacheflush.h>
#include <uapi/elphel/c313a.h>
#include <uapi/elphel/exifa.h>
......@@ -51,6 +53,7 @@
#include "quantization_tables.h"
#include "x393_macro.h"
#include "x393.h"
#include "detect_sensors.h"
//#include "x393_helpers.h"
#include <asm/delay.h> // just for usleep1000()
......@@ -1142,6 +1145,159 @@ int image_acq_stop(struct platform_device *pdev)
{
return 0;
}
/**
* Register i2c pages equal to slave address
* @param port
* @param sub_chn
* @param i2c_dev
* @return
*/
int fpga_register_i2c_pages(int port, int sub_chn, x393_i2c_device_t i2c_dev){
int i;
int line_num;
int haddr;
u16 *table = pSensorPortConfig[port].pages_ptr[sub_chn];
u8 *h2r = pSensorPortConfig[port].haddr2rec[sub_chn];
bool used_page[256];
// init
for(i=0;i<256;i++){
used_page[i] = false;
}
// loop through pages table
i=0;
while(true){
haddr = (table[i]>>8)&0xff;
if ((table[i]==0xffff)||(i>255)){
dev_dbg(g_dev_ptr,"haddr2rec table registered (number of entries: %d)\n",i);
break;
}
if(!used_page[haddr]){
used_page[haddr] = true;
line_num = i2c_page_alloc(port);
if (line_num<0){
return line_num;
}
dev_dbg(g_dev_ptr,"Registering page %d for haddr=0x%02x. slave7= 0x%02x\n",line_num, haddr, i2c_dev.slave7);
//line_num = i2c_dev.slave7;
//haddr = 0;
h2r[haddr] = line_num;
i2c_page_register(port,line_num);
set_xi2c_wrc(&i2c_dev,port,line_num,haddr);
}
i++;
}
return 0;
}
/**
* Takes care of a single/multiple ports - registers all required 'write' and 'read' pages for
* muxes and sensors
* @param ports_mask
* @return
*/
int register_i2c_sensor(int ports_mask) ///< bitmask of the sensor ports to use
///< @return 0 (may add errors)
{
int port, subchn;
x393_i2c_device_t *class_mux, *class_sensor;
x393_i2c_device_t dev_sensor;
struct sensor_port_config_t pcfg;
const char *name;
const char *name10359;
bool mux;
for(port=0;port<SENSOR_PORTS;port++) if ((1<<port)&ports_mask) {
i2c_page_alloc_init(port); // reset all pages allocation
pcfg = pSensorPortConfig[port];
// pcfg.mux==0 equals 'DETECT'
//mux = (pcfg.mux!=SENSOR_NONE)&&(pcfg.mux!=0);
mux = (pcfg.mux!=SENSOR_NONE);
// 'write' recs for mux
if (mux){
// returns 'mux10359', need 'el10359'
name = get_name_by_code(pcfg.mux,DETECT_MUX);
// get reference name 'mux10359'
name10359 = get_name_by_code(SENSOR_MUX_10359,DETECT_MUX);
dev_dbg(g_dev_ptr,"Comparing %s to reference %s\n",name,name10359);
if (name!=NULL){
// compare in case pcfg.mux was something else
if (strncmp(name,name10359,strlen(name10359))==0){
name = name_10359;
}
}
class_mux = xi2c_dev_get(name);
// TODO: request a line# from fpga table and register it (not class_mux->slave7)
dev_dbg(g_dev_ptr,"Registering page %d for haddr=0x%02x. slave7= 0x%02x\n",class_mux->slave7, 0, class_mux->slave7);
i2c_page_register(port, class_mux->slave7);
set_xi2c_wrc(class_mux, port, class_mux->slave7, 0);
}
// 'write' recs for sensors
for(subchn=0;subchn<4;subchn++){
if (pcfg.sensor[subchn]!=SENSOR_NONE){
name = get_name_by_code(pcfg.sensor[subchn],DETECT_SENSOR);
class_sensor = xi2c_dev_get(name);
// copy reference data
memcpy(&dev_sensor, class_sensor, sizeof(x393_i2c_device_t));
// i2c address rule for MUX ports
dev_sensor.slave7 = class_sensor->slave7 + I2C359_INC * subchn;
// register line#s for available sensors (w or w/o mux)
fpga_register_i2c_pages(port,subchn,dev_sensor);
}
}
// Now register one page for reading 10359 and the sensor using sensor speed data
// 'read' recs for sensors,
// TODO: request the # from fpga, do not use LEGACY_READ_PAGE2, check read functions
name = get_name_by_code(pcfg.sensor[0],1);
class_sensor = xi2c_dev_get(name);
memcpy(&dev_sensor, class_sensor, sizeof(x393_i2c_device_t));
i2c_page_register(port, LEGACY_READ_PAGE2);
set_xi2c_rdc(&dev_sensor, port, LEGACY_READ_PAGE2);
if (mux){
// 'read' recs for 10359
// use 'el10359_32' - in DT?
// TODO: request the # from fpga, do not use LEGACY_READ_PAGE4, check read functions
i2c_page_register(port, LEGACY_READ_PAGE4);
dev_sensor.data_bytes=4; // for reading 10359 in 32-bit mode
set_xi2c_rdc(&dev_sensor, port, LEGACY_READ_PAGE4);
}
}
return 0;
}
//#define I2C359_INC 2 ///< slave address increment between sensors in 10359A board (broadcast, 1,2,3)
/** Register i2c pages equal to slave address,
* Use to convert 353 code */
......@@ -1170,7 +1326,7 @@ int legacy_i2c(int ports) ///< bitmask of the sensor ports to use
}
// Now register one page for reading 10359 and the sensor using sensor speed data
memcpy(&dev_sensor, class_sensor, sizeof(x393_i2c_device_t)); // dev_sensor));
dev_dbg(g_dev_ptr, "Registering page to read senors 16-bit on port %d, page= 0x%x\n",sensor_port,LEGACY_READ_PAGE2);
dev_dbg(g_dev_ptr, "Registering page to read sensors 16-bit on port %d, page= 0x%x\n",sensor_port,LEGACY_READ_PAGE2);
i2c_page_register(sensor_port, LEGACY_READ_PAGE2);
set_xi2c_rdc(&dev_sensor, sensor_port, LEGACY_READ_PAGE2);
dev_dbg(g_dev_ptr, "Registering page to read 32-bit data for 10359 on port %d, page= 0x%x\n",sensor_port,LEGACY_READ_PAGE4);
......
src/drivers/elphel/sensor_common.h
View file @ 71913108
......@@ -5,6 +5,8 @@
#ifndef _SENSOR_COMMON_H
#define _SENSOR_COMMON_H
#include "detect_sensors.h"
//extern struct sensor_t sensor; // current sensor (will be copied to by sensor driver), made external for the cc353.c to read/write i2c
extern struct sensorproc_t * asensorproc;
//extern struct sensorproc_t * sensorproc;
......@@ -90,8 +92,11 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
#define LEGACY_READ_PAGE2 0xff
#define LEGACY_READ_PAGE4 0xfe
#define name_10359 "el10359" // Get name from DT (together with port mask)
#define name_sensor "mt9p006" // Get name from DT (together with port mask)
#define name_10359 "el10359" // Get name from DT (together with port mask)
#define name_sensor "mt9p006" // Get name from DT (together with port mask)
#define name_mt9p006 "mt9p006" // Get name from DT (together with port mask)
#define name_mt9f002 "mt9f002" // Get name from DT (together with port mask)
#define I2C359_INC 2 ///< slave address increment between sensors in 10359A board (broadcast, 1,2,3) (7 bits SA)
/** Perform I2C write (8 bits address, 16 bits data in "legacy" mode,
......@@ -104,7 +109,11 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
* @param sa7 I2C slave address, 7 bit
* @param reg sensor register address (8-bit)
* @param data value to set (16 bits) */
#define X3X3_I2C_SEND2(port,frame,sa7,reg,data) write_xi2c_reg16_abs_asap((port),(sa7),(frame),(reg),(data))
#define X3X3_I2C_SEND2(port,frame,sa7,reg,data) {\
int _ADDR = pSensorPortConfig[(port)].par2addr[0][(reg)];\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[0][(_ADDR>>8)&0xff];\
write_xi2c_reg16_abs_asap((port),_PAGE,(frame),_ADDR&0xff,(data));\
}
/** Perform I2C write in immediate mode (8 bits address, 16 bits data in "legacy" mode,
* pages matching slave address should be registered.
......@@ -114,7 +123,11 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
* @param sa7 I2C slave address, 7 bit
* @param reg sensor register address (8-bit)
* @param data value to set (16 bits) */
#define X3X3_I2C_SEND2_ASAP(port,sa7,reg,data) write_xi2c_reg16((port),(sa7),(reg),(data))
#define X3X3_I2C_SEND2_ASAP(port,sa7,reg,data) {\
int _ADDR = pSensorPortConfig[(port)].par2addr[0][(reg)];\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[0][(_ADDR>>8)&0xff];\
write_xi2c_reg16((port),(sa7),(reg),(data));\
}
/** Perform I2C read (8 bits address, 16 bits data in "legacy" mode (sensors and 10359),
* page LEGACY_READ_PAGE2 (==0xff) should be registered - legacy_i2c.
......@@ -139,6 +152,8 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
#define X3X3_I2C_RCV4(port,sa7,reg,datap) legacy_read_i2c_reg((port),(LEGACY_READ_PAGE4),(sa7),(reg),4,(int*)(datap))
int legacy_i2c (int ports);
int register_i2c_sensor(int ports_mask);
void udelay1000(int ms);
#endif
src/drivers/elphel/sensor_i2c.c
View file @ 71913108
......@@ -911,7 +911,7 @@ int x393_xi2c_wait_wr(int chn) ///< sensor port number
int rdy;
unsigned long timeout_end;
dev_dbg(sdev, "Waitoing i2c sequencer ready for channel %d\n",chn);
dev_dbg(sdev, "Waiting i2c sequencer ready for channel %d\n",chn);
timeout_end = jiffies + tenth_sec;
while (jiffies < timeout_end){
if ((rdy=x393_xi2c_ready_wr( chn)))
......
src/drivers/elphel/sensor_i2c.h
View file @ 71913108
......@@ -17,15 +17,14 @@
#ifndef SENSOR_I2C_H
#define SENSOR_I2C_H
#define I2C_CMD_STOP 0
#define I2C_CMD_RUN 1
#define I2C_CMD_RESET 2
#define SDA_DRIVE_HIGH 1
#define SDA_RELEASE 1
/** I2C device description to be used with i2c sequencer*/
/** I2C device description to be used with i2c sequencer */
typedef struct{
char name[32]; ///< Device class name (up to 31 characters)
u8 slave7; ///< Device class base slave address (7-bit). Instances may have it
......@@ -34,7 +33,7 @@ typedef struct{
u8 data_bytes; ///< Number of data bytes (1..10), for writes it includes register address bytes
int scl_khz; ///< maximal SCL frequency in KHz (currently limited by 200KHz slowest)
} x393_i2c_device_t;
void i2c_page_alloc_init( int chn); // reset page allocation for selscted channel
void i2c_page_alloc_init( int chn); // reset page allocation for selected channel
int i2c_stop_run_reset(int chn, int cmd);
int i2c_drive_mode (int chn, int sda_drive_high, int sda_release);
int read_xi2c_frame (int chn);
......
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