Updated and moved to a patch to make it easier updating next time

src/patches/macb_main.c.patch

+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index 401a6c5..1244b75 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -80,6 +80,10 @@
+ #define MACB_HALT_TIMEOUT	1230
+ #define MACB_PM_TIMEOUT  100 /* ms */
+ 
++/* Elphel */
++#define AT803X_PHY_ID          0x004dd072 /*Particular one, AR8035 but we'll use a broad mask */
++#define AT803X_PHY_ID_MASK     0xffffffe0
++
+ /* DMA buffer descriptor might be different size
+  * depends on hardware configuration:
+  *
+@@ -609,12 +613,62 @@ static int macb_mii_probe(struct net_device *dev)
+ 	return 0;
+ }
+ 
++// Elphel BEGIN
++/* http://www.spinics.net/lists/devicetree/msg06322.html */
++static int ar8035_phy_fixup(struct phy_device *dev)
++{
++	u16 val;
++
++	pr_debug("fixup start");
++
++	/* Ar803x phy SmartEEE feature cause link status generates glitch,
++	* which cause ethernet link down/up issue, so disable SmartEEE
++	*/
++	phy_write(dev, 0xd, 0x3);
++	phy_write(dev, 0xe, 0x805d);
++	phy_write(dev, 0xd, 0x4003);
++
++	val = phy_read(dev, 0xe);
++	phy_write(dev, 0xe, val & ~(1 << 8));
++	/*Enable if needed */
++#if 0
++	/* To enable AR8031 output a 125MHz clk from CLK_25M */
++	phy_write(dev, 0xd, 0x7);
++	phy_write(dev, 0xe, 0x8016);
++	phy_write(dev, 0xd, 0x4007);
++
++	val = phy_read(dev, 0xe);
++	val &= 0xffe3;
++	val |= 0x18;
++	phy_write(dev, 0xe, val);
++#endif
++/* Next one what is really needed for Elphel 393 */
++	/* introduce tx clock delay */
++	phy_write(dev, 0x1d, 0x5);
++	val = phy_read(dev, 0x1e);
++	val |= 0x0100;
++	phy_write(dev, 0x1e, val);
++
++	/*check phy power*/
++	val = phy_read(dev, 0x0);
++	if (val & BMCR_PDOWN)
++		phy_write(dev, 0x0, val & ~BMCR_PDOWN);
++
++	pr_debug("fixup end");
++
++	return 0;
++}
++// Elphel END
++
+ static int macb_mii_init(struct macb *bp)
+ {
+ 	struct macb_platform_data *pdata;
+ 	struct device_node *np, *mdio_np;
+ 	int err = -ENXIO, i;
+ 
++	// Elphel, fixup for Atheros 8035
++	phy_register_fixup_for_uid(AT803X_PHY_ID,  AT803X_PHY_ID_MASK,  ar8035_phy_fixup);
++
+ 	/* Enable management port */
+ 	macb_writel(bp, NCR, MACB_BIT(MPE));
+