merged with framepars, several dts files

eclipse_project_setup/.externalToolBuilders/bitbake deploy [Builder].launch

 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <launchConfiguration type="org.eclipse.ui.externaltools.ProgramBuilderLaunchConfigurationType">
 <booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
-<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
-<listEntry value="org.eclipse.ui.externaltools.launchGroup"/>
-</listAttribute>
 <booleanAttribute key="org.eclipse.ui.externaltools.ATTR_BUILDER_ENABLED" value="false"/>
 <stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/>
 <stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="${workspace_loc:/linux-elphel/run_bitbake.sh}"/>

src/arch/arm/boot/dts/elphel393_4_mt9p006.dts

+/* welcome to elphel393 device tree */
+/include/ "elphel393-zynq-base.dtsi"
+/include/ "elphel393-bootargs.dtsi"
+
+/ {
+	model = "Elphel 10393";
+	
+	ps7_axi_interconnect_0: amba@0 {
+		
+		ps7_i2c_0: ps7-i2c@e0004000 {
+			bus-id = <0>;
+			i2c-clk = <400000>;
+			rtc@68 {
+				compatible = "stm,m41t62";
+				reg = <0x68>;
+			};
+			
+			vsc330x@1 {
+				compatible = "vsc,vsc3304";
+				reg = <0x01>;
+				vsc330x,configuration_name = "elphel393: from external";
+				/* configuration below is for external eSATA host accessing SSD. Will chnage
+					* when the SATA controller code will be operational
+					* TODO: specify optimal drive strength, pre-emphasis, etc.
+					* All parameters are exported to sysfs for run-time modification
+					*/
+				vsc330x,configuration_data=<
+				0x11080101 /*page 0x11, register 0x08, data=0x1 (inverted input), write enabled mask=0x1 */
+				0x11090001
+				0x110a0101
+				0x110b0101
+				0x110e0001
+				0x110f0101
+
+				0x230a0b1f /* set output mode for port 10 as non-inverted, forwarding OOB enabled */
+				0x230b151f /* set output mode for port 11 as     inverted, forwarding OOB enabled */
+				0x230c151f
+				0x230d0b1f
+				0x230e151f
+				0x230f151f
+
+				0xff750101 /* freeze configuration to enable simultaneous modification */
+				0x110e0002 /* enable channel 14 input */
+				0x11090002 /* enable channel  9 input */
+
+				0x000b091f /* connect port 11 output to input 9 */
+				0x000c0e1f /* connect port 12 output to input 14 */
+				0xff750001 /* un-freeze configuration to apply connection modifications */
+				>;
+			};
+
+			si5338@70 {
+				compatible = "sil,si5338";
+				reg = <0x70>;
+				si5338,init="always"; /* initialize PLL if chip was not programmed, wait for lock. Other option is 'if off' */
+				/* low-level masked register writes, may be used to load frequency plan */
+				/*si5338,configuration_data=< 0x1ffcf0 >;*/ /* just for testing: write data 0xfc with write enable mask 0xf0 to register 0x01f */
+				si5338,in_frequency3= < 25000000>; /* 25MHz on input 3 (other inputs are '12",'4','56' and '12xo' */
+				/* PLL may be set either directly (pll_freq_fract,pll_freq_int) or to match some output (pll_by_out_fract, pll_by_out_int)
+					* _int suffix forces to find integer divisors, _fract - allows fractional ones */
+				si5338,pll_by_out_int=<150000000>;  /* 150Mhz May have 3 values: integer, nominator and denominator */
+				si5338,out3_freq_int= <150000000>;  /* 150Mhz. May have 3 values: integer, nominator and denominator */
+				si5338,out2_select= "in3/2/32";  /* connect out2 to IN3, divided by 2 (input stage) and then by 32 (output stage)*/
+				si5338,2V5_LVPECL=  <1 2>; /* set output standard for channels 1 and 2 */
+				si5338,1V5_HSTL_A+= <0>;   /* set output standard for channel 0, only A output is used (noninverted) */
+				si5338,1V8_LVDS=    <3>;
+				/* Disabled state for outputs:  */
+				si5338,dis_hi-z=    <0 1 2 3>; /* Disabled state for listed outputs, also possible: "dis_hi-z","dis_low","dis_high","dis_always_on" */
+				si5338,output_en=   < 3>; /* Which outputs should be initially enabled */
+				si5338,spread_spectrum_3= <1 50 31500>; /* Set spread spectrum for channel3 : enabled, 0.5%, 31.5KHz */
+				si5338,out0_freq_int= <15000000>;  /* 15Mhz to output 0 */
+				si5338,spread_spectrum_0= <1 500 31500>; /* Set spread spectrum for channel0 : enabled, 5%, 31.5KHz - high value, for testing */
+			};
+			
+			ltc3589@34 {
+				compatible = "ltc,ltc3589";
+				reg = <0x34>;
+			};
+
+			gpio@20{
+				compatible = "ti,tca6408";
+				reg = <0x20>;
+			};
+			gpio@21{
+				compatible = "ti,tca6408";
+				reg = <0x21>;
+			};
+			gpio@25{
+				compatible = "nxp,pca8574";
+				reg = <0x25>;
+			};
+			/* Use 'spd' instead of '24c02' for read only access*/
+			stts2002@31 {
+				compatible = "at,24c02";
+				reg = <0x31>;
+			};
+			hwmon@1a { /*hwmon@19*/
+				compatible = "stm,jc42";
+				reg = <0x1a>;
+			};
+		};
+		
+		ps7_ethernet_0: ps7-ethernet@e000b000 {
+			local-mac-address = [00 0e 64 10 00 00];
+			phy-handle = <&phy3>;
+			phy-mode = "rgmii-id";
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy3: phy@3 {
+					compatible = "atheros,8035";
+					device_type = "ethernet-phy";
+					reg = <0x3>;
+				};
+			};
+		};
+		
+		ps7_smcc_0: ps7-smcc@e000e000 {
+			ps7_nand_0: ps7-nand@e1000000 {
+				compatible = "arm,pl353-nand-r2p1";
+				reg = < 0xe1000000 0x1000000 >;
+				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
+				arm,nand-width = <0x8>;
+				arm,nand-cycle-t0 = <0x4>;
+				arm,nand-cycle-t1 = <0x4>;
+				arm,nand-cycle-t2 = <0x1>;
+				arm,nand-cycle-t3 = <0x2>;
+				arm,nand-cycle-t4 = <0x2>;
+				arm,nand-cycle-t5 = <0x2>;
+				arm,nand-cycle-t6 = <0x4>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				partition@0 {
+					label = "u-boot-spl";
+					reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/
+				};
+				partition@1 {
+					label = "u-boot";
+					reg = <0x100000 0x400000>;/*4MB*/
+				};
+				partition@2 {
+					label = "device-tree";
+					reg = <0x500000 0x100000>;/*1MB*/
+				};
+				partition@3 {
+					label = "kernel";
+					reg = <0x600000 0x1000000>;/*16MB*/
+				};
+				partition@4 {
+					label = "rootfs";
+					reg = <0x1600000 0x10000000>;/*256MB*/
+				};
+			} ;
+		} ;
+		
+		elphel_ahci: elphel-ahci@80000000 {
+			compatible = "elphel,elphel-ahci";
+			interrupt-parent = <&ps7_scugic_0>;
+			interrupts = <0x0 0x1d 0x4>; /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+			reg = <0x80000000 0x1000>;
+			clb_offs = <0x800>;
+			fb_offs = <0xc00>;
+		};
+	};
+	
+	elphel393_pwr: elphel393-pwr@0 {
+		compatible = "elphel,elphel393-pwr-1.00";
+		elphel393_pwr,simulate=          <0>;
+		elphel393_pwr,i2c_chips=         <0x20 0x21 0x25 0x34>;
+		elphel393_pwr,vp15.r1=           <357000>;
+		elphel393_pwr,vp15.r2=           <287000>;
+		elphel393_pwr,vcc_sens01.r1=     <787000>;
+		elphel393_pwr,vcc_sens01.r2=     <287000>;
+		elphel393_pwr,vcc_sens23.r1=     <787000>;
+		elphel393_pwr,vcc_sens23.r2=     <287000>;
+		elphel393_pwr,vp5.r1=            <523000>;
+		elphel393_pwr,vp5.r2=            <100000>;
+		elphel393_pwr,vldo18.r1=         <357000>;
+		elphel393_pwr,vldo18.r2=         <287000>;
+		elphel393_pwr,channels_disable= "vcc_sens23 vp33sens23 vcc_sens01 vp33sens01";
+		elphel393_pwr,pinstrapped_oven=  <1>;
+		elphel393_pwr,vcc_sens01_mv=     <2800>; /* set sensor intreface voltage to 2.8V */
+		elphel393_pwr,channels_enable=  "vp5";
+/*		elphel393_pwr,channels_enable=  "vcc_sens01 vp33sens01"; */
+	} ;
+	
+	elphel393_mem: elphel393-mem@0 {
+		compatible = "elphel,elphel393-mem-1.00";
+		/*memsize = <25600>;*/
+		memsize = <76800>;
+	} ;
+	
+	elphel393_init: elphel393-init {
+		compatible = "elphel,elphel393-init-1.00";
+	} ;
+	
+	elphel393_circbuf: elphel393-circbuf@0 {
+		compatible = "elphel,elphel393-circbuf-1.00";
+		/* set this to "disable" to disable drivers */
+		status = "okay";
+		interrupt-parent = <&ps7_scugic_0>;
+		 /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+		interrupts =      <0x0 0x34 0x4>, <0x0 0x35 0x4>, <0x0 0x36 0x4>, <0x0 0x37 0x4>,
+		                  <0x0 0x38 0x4>, <0x0 0x39 0x4>, <0x0 0x3A 0x4>, <0x0 0x3B 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+		interrupt-names = "frame_sync_irq_0", "frame_sync_irq_1", "frame_sync_irq_2", "frame_sync_irq_3",
+		                  "compr_irq_0", "compr_irq_1", "compr_irq_2", "compr_irq_3";
+	};
+
+    elphel393_logger: elphel393-logger@0 {
+        compatible = "elphel,elphel393-logger-1.00";
+        /* set this to "disable" to disable drivers */
+        status = "okay";
+        interrupt-parent = <&ps7_scugic_0>;
+         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+        interrupts =      <0x0 0x21 0x4>, <0x0 0x22 0x4>, <0x0 0x23 0x4>, <0x0 0x24 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+        interrupt-names = "mult_saxi_0", "mult_saxi_1", "mult_saxi_2", "mult_saxi_3";
+    };
+	
+    elphel393_videomem: elphel393-videomem@0 {
+        compatible = "elphel,elphel393-videomem-1.00";
+        /* set this to "disable" to disable drivers */
+        status = "okay";
+        interrupt-parent = <&ps7_scugic_0>;
+         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+        interrupts =      <0x0 0x20 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+        interrupt-names = "membridge_irq";
+        /* maximal dimesions that use all 512M memory for 4 channels. May be changed when doing processing*/
+        frame_full_width = <8192>; /* in bytes, will be transformed to bursts (16 bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_height     = <8192>; /* in pixel lines */
+        frames_in_buffer = <2>;    /* Each channel has this number of frames in buffer */
+        
+        frame_start_chn0 =     <0x00000000>;      /* Channel 0 frame start (in bytes) */
+        frame_start_chn1 =     <0x08000000>;      /* Channel 1 frame start (in bytes) */
+        frame_start_chn2 =     <0x10000000>;      /* Channel 2 frame start (in bytes) */
+        frame_start_chn3 =     <0x18000000>;      /* Channel 3 frame start (in bytes) */
+        frame_full_width_chn0 =      <8192>;      /* Channel 0 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn1 =      <8192>;      /* Channel 1 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn2 =      <8192>;      /* Channel 2 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn3 =      <8192>;      /* Channel 3 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_height_chn0 =          <8192>;      /* Channel 0 maximal frame height in pixel lines */
+        frame_height_chn1 =          <8192>;      /* Channel 1 maximal frame height in pixel lines */
+        frame_height_chn2 =          <8192>;      /* Channel 2 maximal frame height in pixel lines */
+        frame_height_chn3 =          <8192>;      /* Channel 3 maximal frame height in pixel lines */
+        frames_in_buffer_chn0 =         <2>;      /* Number of frames in channel 0 buffer */
+        frames_in_buffer_chn1 =         <2>;      /* Number of frames in channel 1 buffer */
+        frames_in_buffer_chn2 =         <2>;      /* Number of frames in channel 2 buffer */
+        frames_in_buffer_chn3 =         <2>;      /* Number of frames in channel 3 buffer */
+    };
+
+    elphel393_detect_sensors: elphel393-detect_sensors@0 {
+        compatible = "elphel,elphel393-detect_sensors-1.00";
+        elphel393-detect_sensors,port-mux = "none none none none"; /* "none", "detect" or "mux10359" */
+        elphel393-detect_sensors,sensors =  "mt9p006", // Line per port, may contain up to 4 sensors (3 with 10359)
+                                            "mt9p006",
+                                            "mt9p006",
+                                            "mt9p006";
+    };
+    
+    elphel393_sensor_i2c: elphel393-sensor-i2c@0 {
+                compatible = "elphel,elphel393-sensor-i2c-1.00";
+                /* Add known devices: name, slave address (7-bit), number of address bytes, number of data bytes, SCL frequency (kHz) */
+                elphel393-sensor-i2c,i2c_devices = "mt9f002 0x10 2 2 500",
+                                                   "mt9p006 0x48 1 2 500",
+                                                   "el10359 0x08 1 2 500",
+                                                   "pca9500_eeprom 0x50 1 1 100",
+                                                   "cy22393 0x69 1 1 100";
+    } ;
+
+    framepars_operations: elphel393-framepars@0 {
+        compatible = "elphel,elphel393-framepars-1.00";
+    };
+    
+    histograms_operations: elphel393-histograms@0 {
+        compatible = "elphel,elphel393-histograms-1.00";
+    };
+
+    gamma_tables_operations: elphel393-gamma_tables@0 {
+        compatible = "elphel,elphel393-gamma_tables-1.00";
+    };
+
+    elphel393_mt9x001: elphel393-mt9x001@0 {
+        compatible = "elphel,elphel393-mt9x001-1.00";
+    };
+
+    klogger_393: klogger-393@0 {
+        compatible = "elphel,klogger-393-1.00";
+        klogger-393,buffer_size = <1048576>; 
+    } ;
+    
+    
+};
\ No newline at end of file

src/arch/arm/boot/dts/elphel393_eyesis.dts

+/* welcome to elphel393 device tree */
+/include/ "elphel393-zynq-base.dtsi"
+/include/ "elphel393-bootargs.dtsi"
+
+/ {
+	model = "Elphel 10393";
+	
+	ps7_axi_interconnect_0: amba@0 {
+		
+		ps7_i2c_0: ps7-i2c@e0004000 {
+			bus-id = <0>;
+			i2c-clk = <400000>;
+			rtc@68 {
+				compatible = "stm,m41t62";
+				reg = <0x68>;
+			};
+			
+			vsc330x@1 {
+				compatible = "vsc,vsc3304";
+				reg = <0x01>;
+				vsc330x,configuration_name = "elphel393: from external";
+				/* configuration below is for external eSATA host accessing SSD. Will chnage
+					* when the SATA controller code will be operational
+					* TODO: specify optimal drive strength, pre-emphasis, etc.
+					* All parameters are exported to sysfs for run-time modification
+					*/
+				vsc330x,configuration_data=<
+				0x11080101 /*page 0x11, register 0x08, data=0x1 (inverted input), write enabled mask=0x1 */
+				0x11090001
+				0x110a0101
+				0x110b0101
+				0x110e0001
+				0x110f0101
+
+				0x230a0b1f /* set output mode for port 10 as non-inverted, forwarding OOB enabled */
+				0x230b151f /* set output mode for port 11 as     inverted, forwarding OOB enabled */
+				0x230c151f
+				0x230d0b1f
+				0x230e151f
+				0x230f151f
+
+				0xff750101 /* freeze configuration to enable simultaneous modification */
+				0x110e0002 /* enable channel 14 input */
+				0x11090002 /* enable channel  9 input */
+
+				0x000b091f /* connect port 11 output to input 9 */
+				0x000c0e1f /* connect port 12 output to input 14 */
+				0xff750001 /* un-freeze configuration to apply connection modifications */
+				>;
+			};
+
+			si5338@70 {
+				compatible = "sil,si5338";
+				reg = <0x70>;
+				si5338,init="always"; /* initialize PLL if chip was not programmed, wait for lock. Other option is 'if off' */
+				/* low-level masked register writes, may be used to load frequency plan */
+				/*si5338,configuration_data=< 0x1ffcf0 >;*/ /* just for testing: write data 0xfc with write enable mask 0xf0 to register 0x01f */
+				si5338,in_frequency3= < 25000000>; /* 25MHz on input 3 (other inputs are '12",'4','56' and '12xo' */
+				/* PLL may be set either directly (pll_freq_fract,pll_freq_int) or to match some output (pll_by_out_fract, pll_by_out_int)
+					* _int suffix forces to find integer divisors, _fract - allows fractional ones */
+				si5338,pll_by_out_int=<150000000>;  /* 150Mhz May have 3 values: integer, nominator and denominator */
+				si5338,out3_freq_int= <150000000>;  /* 150Mhz. May have 3 values: integer, nominator and denominator */
+				si5338,out2_select= "in3/2/32";  /* connect out2 to IN3, divided by 2 (input stage) and then by 32 (output stage)*/
+				si5338,2V5_LVPECL=  <1 2>; /* set output standard for channels 1 and 2 */
+				si5338,1V5_HSTL_A+= <0>;   /* set output standard for channel 0, only A output is used (noninverted) */
+				si5338,1V8_LVDS=    <3>;
+				/* Disabled state for outputs:  */
+				si5338,dis_hi-z=    <0 1 2 3>; /* Disabled state for listed outputs, also possible: "dis_hi-z","dis_low","dis_high","dis_always_on" */
+				si5338,output_en=   < 3>; /* Which outputs should be initially enabled */
+				si5338,spread_spectrum_3= <1 50 31500>; /* Set spread spectrum for channel3 : enabled, 0.5%, 31.5KHz */
+				si5338,out0_freq_int= <15000000>;  /* 15Mhz to output 0 */
+				si5338,spread_spectrum_0= <1 500 31500>; /* Set spread spectrum for channel0 : enabled, 5%, 31.5KHz - high value, for testing */
+			};
+			
+			ltc3589@34 {
+				compatible = "ltc,ltc3589";
+				reg = <0x34>;
+			};
+
+			gpio@20{
+				compatible = "ti,tca6408";
+				reg = <0x20>;
+			};
+			gpio@21{
+				compatible = "ti,tca6408";
+				reg = <0x21>;
+			};
+			gpio@25{
+				compatible = "nxp,pca8574";
+				reg = <0x25>;
+			};
+			/* Use 'spd' instead of '24c02' for read only access*/
+			stts2002@31 {
+				compatible = "at,24c02";
+				reg = <0x31>;
+			};
+			hwmon@1a { /*hwmon@19*/
+				compatible = "stm,jc42";
+				reg = <0x1a>;
+			};
+		};
+		
+		ps7_ethernet_0: ps7-ethernet@e000b000 {
+			local-mac-address = [00 0e 64 10 00 00];
+			phy-handle = <&phy3>;
+			phy-mode = "rgmii-id";
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy3: phy@3 {
+					compatible = "atheros,8035";
+					device_type = "ethernet-phy";
+					reg = <0x3>;
+				};
+			};
+		};
+		
+		ps7_smcc_0: ps7-smcc@e000e000 {
+			ps7_nand_0: ps7-nand@e1000000 {
+				compatible = "arm,pl353-nand-r2p1";
+				reg = < 0xe1000000 0x1000000 >;
+				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
+				arm,nand-width = <0x8>;
+				arm,nand-cycle-t0 = <0x4>;
+				arm,nand-cycle-t1 = <0x4>;
+				arm,nand-cycle-t2 = <0x1>;
+				arm,nand-cycle-t3 = <0x2>;
+				arm,nand-cycle-t4 = <0x2>;
+				arm,nand-cycle-t5 = <0x2>;
+				arm,nand-cycle-t6 = <0x4>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				partition@0 {
+					label = "u-boot-spl";
+					reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/
+				};
+				partition@1 {
+					label = "u-boot";
+					reg = <0x100000 0x400000>;/*4MB*/
+				};
+				partition@2 {
+					label = "device-tree";
+					reg = <0x500000 0x100000>;/*1MB*/
+				};
+				partition@3 {
+					label = "kernel";
+					reg = <0x600000 0x1000000>;/*16MB*/
+				};
+				partition@4 {
+					label = "rootfs";
+					reg = <0x1600000 0x10000000>;/*256MB*/
+				};
+			} ;
+		} ;
+		
+		elphel_ahci: elphel-ahci@80000000 {
+			compatible = "elphel,elphel-ahci";
+			interrupt-parent = <&ps7_scugic_0>;
+			interrupts = <0x0 0x1d 0x4>; /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+			reg = <0x80000000 0x1000>;
+			clb_offs = <0x800>;
+			fb_offs = <0xc00>;
+		};
+	};
+	
+	elphel393_pwr: elphel393-pwr@0 {
+		compatible = "elphel,elphel393-pwr-1.00";
+		elphel393_pwr,simulate=          <0>;
+		elphel393_pwr,i2c_chips=         <0x20 0x21 0x25 0x34>;
+		elphel393_pwr,vp15.r1=           <357000>;
+		elphel393_pwr,vp15.r2=           <287000>;
+		elphel393_pwr,vcc_sens01.r1=     <787000>;
+		elphel393_pwr,vcc_sens01.r2=     <287000>;
+		elphel393_pwr,vcc_sens23.r1=     <787000>;
+		elphel393_pwr,vcc_sens23.r2=     <287000>;
+		elphel393_pwr,vp5.r1=            <523000>;
+		elphel393_pwr,vp5.r2=            <100000>;
+		elphel393_pwr,vldo18.r1=         <357000>;
+		elphel393_pwr,vldo18.r2=         <287000>;
+		elphel393_pwr,channels_disable= "vcc_sens23 vp33sens23 vcc_sens01 vp33sens01";
+		elphel393_pwr,pinstrapped_oven=  <1>;
+		elphel393_pwr,vcc_sens01_mv=     <2800>; /* set sensor intreface voltage to 2.8V */
+		elphel393_pwr,channels_enable=  "vp5";
+/*		elphel393_pwr,channels_enable=  "vcc_sens01 vp33sens01"; */
+	} ;
+	
+	elphel393_mem: elphel393-mem@0 {
+		compatible = "elphel,elphel393-mem-1.00";
+		/*memsize = <25600>;*/
+		memsize = <76800>;
+	} ;
+	
+	elphel393_init: elphel393-init {
+		compatible = "elphel,elphel393-init-1.00";
+	} ;
+	
+	elphel393_circbuf: elphel393-circbuf@0 {
+		compatible = "elphel,elphel393-circbuf-1.00";
+		/* set this to "disable" to disable drivers */
+		status = "okay";
+		interrupt-parent = <&ps7_scugic_0>;
+		 /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+		interrupts =      <0x0 0x34 0x4>, <0x0 0x35 0x4>, <0x0 0x36 0x4>, <0x0 0x37 0x4>,
+		                  <0x0 0x38 0x4>, <0x0 0x39 0x4>, <0x0 0x3A 0x4>, <0x0 0x3B 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+		interrupt-names = "frame_sync_irq_0", "frame_sync_irq_1", "frame_sync_irq_2", "frame_sync_irq_3",
+		                  "compr_irq_0", "compr_irq_1", "compr_irq_2", "compr_irq_3";
+	};
+
+    elphel393_logger: elphel393-logger@0 {
+        compatible = "elphel,elphel393-logger-1.00";
+        /* set this to "disable" to disable drivers */
+        status = "okay";
+        interrupt-parent = <&ps7_scugic_0>;
+         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+        interrupts =      <0x0 0x21 0x4>, <0x0 0x22 0x4>, <0x0 0x23 0x4>, <0x0 0x24 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+        interrupt-names = "mult_saxi_0", "mult_saxi_1", "mult_saxi_2", "mult_saxi_3";
+    };
+	
+    elphel393_videomem: elphel393-videomem@0 {
+        compatible = "elphel,elphel393-videomem-1.00";
+        /* set this to "disable" to disable drivers */
+        status = "okay";
+        interrupt-parent = <&ps7_scugic_0>;
+         /* interrupt number (middle of 3) is by 0x20 less, than shown as ID in TRM */
+        interrupts =      <0x0 0x20 0x4>;
+/*        reg = <0x80000000 0x1000>; */
+        interrupt-names = "membridge_irq";
+        /* maximal dimesions that use all 512M memory for 4 channels. May be changed when doing processing*/
+        frame_full_width = <8192>; /* in bytes, will be transformed to bursts (16 bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_height     = <8192>; /* in pixel lines */
+        frames_in_buffer = <2>;    /* Each channel has this number of frames in buffer */
+        
+        frame_start_chn0 =     <0x00000000>;      /* Channel 0 frame start (in bytes) */
+        frame_start_chn1 =     <0x08000000>;      /* Channel 1 frame start (in bytes) */
+        frame_start_chn2 =     <0x10000000>;      /* Channel 2 frame start (in bytes) */
+        frame_start_chn3 =     <0x18000000>;      /* Channel 3 frame start (in bytes) */
+        frame_full_width_chn0 =      <8192>;      /* Channel 0 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn1 =      <8192>;      /* Channel 1 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn2 =      <8192>;      /* Channel 2 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_full_width_chn3 =      <8192>;      /* Channel 3 frame full width (in bytes). 1 memory page is 2048 bytes (128 bursts) */
+        frame_height_chn0 =          <8192>;      /* Channel 0 maximal frame height in pixel lines */
+        frame_height_chn1 =          <8192>;      /* Channel 1 maximal frame height in pixel lines */
+        frame_height_chn2 =          <8192>;      /* Channel 2 maximal frame height in pixel lines */
+        frame_height_chn3 =          <8192>;      /* Channel 3 maximal frame height in pixel lines */
+        frames_in_buffer_chn0 =         <2>;      /* Number of frames in channel 0 buffer */
+        frames_in_buffer_chn1 =         <2>;      /* Number of frames in channel 1 buffer */
+        frames_in_buffer_chn2 =         <2>;      /* Number of frames in channel 2 buffer */
+        frames_in_buffer_chn3 =         <2>;      /* Number of frames in channel 3 buffer */
+    };
+
+    elphel393_detect_sensors: elphel393-detect_sensors@0 {
+        compatible = "elphel,elphel393-detect_sensors-1.00";
+        elphel393-detect_sensors,port-mux = "mux10359 mux10359 mux10359 mux10359"; /* "none", "detect" or "mux10359" */
+        elphel393-detect_sensors,sensors =  "mt9p006 mt9p006 mt9p006", // Line per port, may contain up to 4 sensors (3 with 10359)
+                                            "mt9p006 mt9p006 mt9p006",
+                                            "mt9p006 mt9p006 mt9p006",
+                                            "mt9p006 mt9p006 mt9p006";
+    };
+    
+    elphel393_sensor_i2c: elphel393-sensor-i2c@0 {
+                compatible = "elphel,elphel393-sensor-i2c-1.00";
+                /* Add known devices: name, slave address (7-bit), number of address bytes, number of data bytes, SCL frequency (kHz) */
+                elphel393-sensor-i2c,i2c_devices = "mt9f002 0x10 2 2 500",
+                                                   "mt9p006 0x48 1 2 500",
+                                                   "el10359 0x08 1 2 500",
+                                                   "pca9500_eeprom 0x50 1 1 100",
+                                                   "cy22393 0x69 1 1 100";
+    } ;
+
+    framepars_operations: elphel393-framepars@0 {
+        compatible = "elphel,elphel393-framepars-1.00";
+    };
+    
+    histograms_operations: elphel393-histograms@0 {
+        compatible = "elphel,elphel393-histograms-1.00";
+    };
+
+    gamma_tables_operations: elphel393-gamma_tables@0 {
+        compatible = "elphel,elphel393-gamma_tables-1.00";
+    };
+
+    elphel393_mt9x001: elphel393-mt9x001@0 {
+        compatible = "elphel,elphel393-mt9x001-1.00";
+    };
+
+    klogger_393: klogger-393@0 {
+        compatible = "elphel,klogger-393-1.00";
+        klogger-393,buffer_size = <1048576>; 
+    } ;
+    
+    
+};
\ No newline at end of file

src/drivers/elphel/fpgajtag353.c

@@ -422,6 +422,10 @@ static int fpga_jtag_release(struct inode *inode, struct file *filp) {
     if (JTAG_channels[chn].wp > 0) { // anything written?
         res=JTAG_configure (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].wp);
         JTAG_resetChannel (chn);
+        if (res <0) {
+            dev_dbg(NULL, "fpga_jtag_release:  failure, returned %d\n",res);
+        }
+
         if ((res >=0) & (chn == JTAG_MAIN_FPGA)) {
             // read FPGA model number/revision and OR it with current state
             //fpga_state =  (fpga_state & ~0xffff) | (port_csp0_addr[X313__RA__MODEL] & 0xffff);
@@ -641,8 +645,8 @@ static loff_t  fpga_jtag_lseek(struct file * file, loff_t offset, int orig) {
 // Initialize GPIOs of the CPU to access JTAG/programming of the main FPGA
 void initPortC(void) {
     // connect 8 lower bits of port C to GPIO, disconnect from IOP
-    unsigned long tmp;
 #ifdef TEST_DISABLE_CODE
+    unsigned long tmp;
     reg_pinmux_rw_pc_iop    pinmux_c_iop;
     reg_pinmux_rw_pc_gio    pinmux_c_gio;
     reg_gio_rw_pc_oe        pc_oe;
@@ -758,7 +762,7 @@ inline u32 read_tdo_byte(int sens_num)
 // set FPGA in programming/JTAG mode (only for sensor board)
 // NOP for the main board FPGA configuration
 void set_pgm_mode (int chn, int en) {
-    u32 seq_num;
+//    u32 seq_num;
     x393_sensio_jtag_t data;
     dev_dbg(NULL, "set_pgm_mode (%d,%d)\n",chn,en);
 
@@ -782,7 +786,7 @@ void set_pgm_mode (int chn, int en) {
 }
 
 void set_pgm (int chn, int pgmon) {
-    u32 seq_num;
+//    u32 seq_num;
     x393_sensio_jtag_t data;
     dev_dbg(NULL, "set_pgm (%d,%d)\n",chn,pgmon);
 
@@ -809,8 +813,7 @@ void set_pgm (int chn, int pgmon) {
 
 int read_done (int chn) {
     x393_status_sens_io_t stat;
-    x393_sensio_jtag_t data;
-
+//    x393_sensio_jtag_t data;
     switch (chn >> 2) {
 #ifdef TEST_DISABLE_CODE
     case JTAG_MAIN_FPGA:
@@ -833,7 +836,7 @@ int read_done (int chn) {
 int jtag_send (int chn, int tms, int len, int d) {
     int sens_num = chn & 3;
     x393_sensio_jtag_t data;
-    x393_status_sens_io_t stat;
+//    x393_status_sens_io_t stat;
     //	u32 seq_num;
     int i, bm = 0; //,m;
     int r=0;
@@ -941,7 +944,7 @@ int jtag_write_bits (int chn,
     int bm = 0;
     int d,d0;
     //	u32 seq_num;
-    x393_status_sens_io_t stat;
+//    x393_status_sens_io_t stat;
     x393_sensio_jtag_t data;
 
     dev_dbg(NULL, "jtag_write_bits(0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\r\n", (int) chn, (int) buf, len, check, last);
@@ -1356,7 +1359,7 @@ int JTAG_EXTEST (int chn, unsigned char * buf, int len) {
 #ifdef JTAG_DISABLE_IRQ
     unsigned long flags;
 #endif
-    int i; // only in debug
+//    int i; // only in debug
 #ifdef JTAG_DISABLE_IRQ
     local_irq_save(flags);
     //local_irq_disable();

src/drivers/elphel/mt9x001.c

@@ -1988,9 +1988,11 @@ int mt9x001_pgm_triggermode        (int sensor_port,               ///< sensor p
     unsigned long newreg;
     dev_dbg(g_dev_ptr,"{%d}  frame16=%d\n",sensor_port,frame16);
     if (frame16 >= PARS_FRAMES) return -1; // wrong frame
-    newreg= (thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE1] & 0xfeff) | ((thispars->pars[P_TRIG] & 4)?0x100:0);
+    newreg= (thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE1] & 0xfe7f) | // old value without snamshot and GRR bits
+            ((thispars->pars[P_TRIG] & 4)?0x100:0) |                    // snapshot mode for P_TRIG==4 or 5
+            ((thispars->pars[P_TRIG] & 1)?0x80:0);                      // GRR mode for P_TRIG==5 (no effect for 1
     if (newreg != thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE1]) {
-        // turn off triggered mode immediately, turn on later (or should made at leas before changing camsync parameters)
+        // turn off triggered mode immediately, turn on later (or should made at least before changing camsync parameters)
         if (!(thispars->pars[P_TRIG] & 4)){
             frame16 = -1;
         }

src/drivers/elphel/multi10359.c

@@ -92,7 +92,7 @@
 #include <linux/fs.h>
 #include <linux/string.h>
 #include <linux/init.h>
-//#include <linux/platform_device.h>
+#include <linux/platform_device.h>
 #include <linux/device.h> // for dev_dbg, platform_device.h is OK too
 
 //#include <linux/autoconf.h>
@@ -227,15 +227,15 @@ int setup_i2c_pages(int ports) ///< bitmask of the sensor ports to use
 // using new access in immediate mode by class name
 #define MULTISENSOR_WRITE_I2C(port,name,offs,ra,v) \
     {rslt |= multisensor_write_i2c((port),(name),(offs),(ra),(v)) ; \
-     dev_dbg(g_dev_ptr,"%s  multisensor_write_i2c(%d, %s, 0x%x, 0x%x, 0x%x) -> %d\n",__func__,(int)(port),name,int(offs),(int)(ra),(int)(v),rslt);}
+     dev_dbg(g_dev_ptr,"multisensor_write_i2c(%d, %s, 0x%x, 0x%x, 0x%x) -> %d\n",(int)(port),name,int(offs),(int)(ra),(int)(v),rslt);}
 #define MULTISENSOR_WRITE_I2C16(port,ra,v) \
     {rslt |= multisensor_write_i2c((port),(name_10359),0,(ra),(v)) ; \
-     dev_dbg(g_dev_ptr,"%s  multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n",__func__,(int)(port),name_10359,(int)(ra),(int)(v),rslt);}
+     dev_dbg(g_dev_ptr,"multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n", (int)(port),name_10359,(int)(ra),(int)(v),rslt);}
 #define MULTISENSOR_WRITE_I2C32(port,ra,v) \
     {rslt |= multisensor_write_i2c((port),(name_10359),0,(I2C359_MSW),(v)>>16) ; \
-     dev_dbg(g_dev_ptr,"%s  multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n",__func__,(int)(port),name_10359,I2C359_MSW,(int)(v)>>16,rslt); \
+     dev_dbg(g_dev_ptr,"multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n", (int)(port),name_10359,I2C359_MSW,(int)(v)>>16,rslt); \
      rslt |= multisensor_write_i2c((port),(name_10359),0,(ra),        (v) & 0xffff) ; \
-     dev_dbg(g_dev_ptr,"%s  multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n",__func__,(int)(port),name_10359,(int)(ra),(int)(v)&0xffff,2,rslt); \
+     dev_dbg(g_dev_ptr,"multisensor_write_i2c(%d, %s, 0x%x, 0x%x) -> %d\n", (int)(port),name_10359,(int)(ra),(int)(v)&0xffff,rslt); \
 }
 #endif
 //pars_to_update - local variable
@@ -261,9 +261,9 @@ int setup_i2c_pages(int ports) ///< bitmask of the sensor ports to use
     }
 
 #define SET_10359_PAR32(p,f,r,v) \
-    { pars_to_update[nupdate  ].num= P_M10359_REGS+(r) ;\
+    { unsigned long flags; \
+      pars_to_update[nupdate  ].num= P_M10359_REGS+(r) ;\
       pars_to_update[nupdate++].val=(v);\
-      unsigned long flags; \
       local_irq_save(flags); \
       X3X3_I2C_SEND2((p), (f), (I2C359_SLAVEADDR), (I2C359_MSW), (v)>>16); \
       X3X3_I2C_SEND2((p), (f), (I2C359_SLAVEADDR), (r), (v) & 0xffff); \
@@ -458,14 +458,11 @@ int multisensor_pgm_window_common  (int sensor_port,               ///< sensor p
 {
   struct frameparspair_t  pars_to_update[50];  // 11 for 10359,sensor: 3 - broadcast (can be x4) and 4 individual (x3), 11+3*4+4*3+1+1 = 37
   int nupdate=0;
-  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
-  if (frame16 >= PARS_FRAMES) return -1; // wrong frame
 //  int fpga_addr=   (frame16 <0) ? X313_I2C_ASAP : (X313_I2C_FRAME0+frame16);
-  int fpga_addr=   frame16 <0;
-
+//  int fpga_addr=   frame16 <0;
 //  int fpga_addr359= (frame16 <0) ? X313_I2C_ASAP : (X313_I2C_FRAME0+((frame16 + ((GLOBALPARS(G_MULTI_CFG)>>G_MULTI_CFG_DLYI2C) & 1)) & PARS_FRAMES_MASK)); // will point to one i2c frame later than fpga_addr
-  int fpga_addr359= frame16 + ((GLOBALPARS(sensor_port, G_MULTI_CFG)>>G_MULTI_CFG_DLYI2C) & 1); // will point to one i2c frame later than fpga_addr
 
+  int fpga_addr359= frame16 + ((GLOBALPARS(sensor_port, G_MULTI_CFG)>>G_MULTI_CFG_DLYI2C) & 1); // will point to one i2c frame later than fpga_addr
   int height1,height2,height3,vblank2,vblank3;
   unsigned long wois[12];
   int i,dv,dh,bv,bh,ww,w359,wh,wl,wt,flip,flipX,flipY,d, v;
@@ -481,6 +478,12 @@ int multisensor_pgm_window_common  (int sensor_port,               ///< sensor p
   int composite=     (thispars->pars[P_MULTI_MODE])?1:0;
   int async=        (thispars->pars[P_TRIG] & 4)?1:0;
   int selected =     thispars->pars[P_MULTI_SELECTED]; // 1..3 - selected in single frame mode
+  int sequence;
+  int active; // sensors to program
+  int styp;
+  int multi_mode_flips;
+  if (frame16 >= PARS_FRAMES) return -1; // wrong frame
+  dev_dbg(g_dev_ptr,"frame16=%d\n",frame16);
 
   if (composite && (!async)) {
     printk("*** ERROR (Should be disabled in multisensor_pgm_multisens() ) CANNOT USE COMPOSITE MODE WITH FREE RUNNING SENSOR ***\n");
@@ -488,8 +491,8 @@ int multisensor_pgm_window_common  (int sensor_port,               ///< sensor p
     SETFRAMEPARS_SET(P_MULTI_MODE,0); // Do we need to force anything here? If it was async->free transition? Or just TRIG mode should have all the dependencies of P_MULTI_MODE
   }
 
-  int sequence=thispars->pars[P_MULTI_SEQUENCE];
-  int active=0; // sensors to program
+  sequence=thispars->pars[P_MULTI_SEQUENCE];
+  active=0; // sensors to program
 //  int sensor_mask=(thispars->pars[P_MULTISENS_EN]) & GLOBALPARS(G_SENS_AVAIL);  // sensor mask should already be applied to sequence in afterinit
   flip=((thispars->pars[P_FLIPH] & 1) | ((thispars->pars[P_FLIPV] & 1) << 1 )) ^ sensor->init_flips; // 10338 is _not_ flipped (as the ther boards, but for legacy compatibility....)
   flipX =  flip & 1;
@@ -501,7 +504,7 @@ int multisensor_pgm_window_common  (int sensor_port,               ///< sensor p
 //sFlip* are now per-sensor absolute flips
   dev_dbg(g_dev_ptr,"%s selected=%x flipX=%x flipY=%x sFlipX[0]=%x sFlipY[0]=%x sFlipX[1]=%x sFlipY[1]=%x sFlipX[2]=%x sFlipY[2]=%x\n",__func__, selected, flipX,flipY,sFlipX[0],sFlipY[0],sFlipX[1],sFlipY[1],sFlipX[2],sFlipY[2]);
 // calculations valid for individual and composite frames
-  int styp = sensor->sensorType & 7;
+  styp = sensor->sensorType & 7;
   dh=  thispars->pars[P_DCM_HOR];
   dv=  thispars->pars[P_DCM_VERT];
   bh=  thispars->pars[P_BIN_HOR];
@@ -691,7 +694,7 @@ int multisensor_pgm_window_common  (int sensor_port,               ///< sensor p
 // horBlank
 
 // Set P_MULTI_MODE_FLIPS, P_MULTI_HEIGHT_BLANK1, P_MULTI_HEIGHT_BLANK2 to be used in MakerNote data
-    int multi_mode_flips= ( multiFlipX & 1)     | ((multiFlipX & 2) << 1)  | ((multiFlipX & 4) << 2) |
+    multi_mode_flips=     ( multiFlipX & 1)     | ((multiFlipX & 2) << 1)  | ((multiFlipX & 4) << 2) |
                           ((multiFlipY & 1)<<1) | ((multiFlipY & 2) << 2)  | ((multiFlipY & 4) << 3) | 0x40; // 0x40 as a composite frame mark (test with &0xc0!=0 - future)
     if (flipX)  multi_mode_flips ^= 0x15;
     if (flipY)  multi_mode_flips ^= 0x2a;
@@ -742,23 +745,23 @@ if (GLOBALPARS(sensor_port, G_MULTI_CFG) & (1 <<G_MULTI_CFG_BEFORE)) {
 // comparisons are only valid if there are no individual parameters that were changed
 // program sensors width (same for all sensors, use broadcast mode)
   ww=wois[(P_MULTI_WIDTH1- P_MULTI_WOI)+(composite?SENSOR_IN_SEQ(0,sequence):(selected-1))];
-  dev_dbg(g_dev_ptr,"%s  selected=%x, thispars->pars[P_MULTI_SELECTED]=%x composite=%x sequence=%x\n",__func__,    selected, (int) thispars->pars[P_MULTI_SELECTED], composite, sequence);
+  dev_dbg(g_dev_ptr,"selected=%x, thispars->pars[P_MULTI_SELECTED]=%x composite=%x sequence=%x\n", selected, (int) thispars->pars[P_MULTI_SELECTED], composite, sequence);
 
   if ((ww-1) != thispars->pars[P_SENSOR_REGS+P_MT9X001_WIDTH]) {
-     SET_SENSOR_MBPAR(sensor_port, fpga_addr, sensor->i2c_addr, P_MT9X001_WIDTH, ww-1);
-     dev_dbg(g_dev_ptr,"%s   SET_SENSOR_MBPAR(0x%x,0x%x, 0x%x, 0x%x)\n",__func__, fpga_addr,  (int) sensor->i2c_addr, (int) P_MT9X001_WIDTH, (int) ww-1);
+     SET_SENSOR_MBPAR(sensor_port, frame16, sensor->i2c_addr, P_MT9X001_WIDTH, ww-1);
+     dev_dbg(g_dev_ptr,"SET_SENSOR_MBPAR(0x%x,0x%x, 0x%x, 0x%x)\n", frame16,  (int) sensor->i2c_addr, (int) P_MT9X001_WIDTH, (int) ww-1);
   }
 // Program binning/decimation (also common but some older sensors)
   if((styp == MT9T_TYP) || (styp == MT9P_TYP)) { // 3MPix and 5MPix sensors
      v= (thispars->pars[P_SENSOR_REGS+P_MT9X001_RAM] & 0xff88) | ((bv - 1) << 4) | (dv - 1) ;
      if (v != thispars->pars[P_SENSOR_REGS+P_MT9X001_RAM]) {
-        SET_SENSOR_PAR(sensor_port, fpga_addr,sensor->i2c_addr, P_MT9X001_RAM, v);
-        dev_dbg(g_dev_ptr,"%s   SET_SENSOR_PAR(0x%x,0x%x, 0x%x, 0x%x)\n",__func__, fpga_addr,  (int) sensor->i2c_addr, (int) P_MT9X001_RAM, (int) v);
+        SET_SENSOR_PAR(sensor_port, frame16,sensor->i2c_addr, P_MT9X001_RAM, v);
+        dev_dbg(g_dev_ptr,"SET_SENSOR_PAR(0x%x,0x%x, 0x%x, 0x%x)\n", frame16,  (int) sensor->i2c_addr, (int) P_MT9X001_RAM, (int) v);
      }
      v=(thispars->pars[P_SENSOR_REGS+P_MT9X001_CAM] & 0xff88) | ((bh - 1) << 4) | (dh - 1);
      if (v != thispars->pars[P_SENSOR_REGS+P_MT9X001_CAM]) {
-        SET_SENSOR_PAR(sensor_port, fpga_addr,sensor->i2c_addr, P_MT9X001_CAM, v);
-        dev_dbg(g_dev_ptr,"%s   SET_SENSOR_PAR(0x%x,0x%x, 0x%x, 0x%x)\n",__func__, fpga_addr,  (int) sensor->i2c_addr, (int) P_MT9X001_CAM, (int) v);
+        SET_SENSOR_PAR(sensor_port, frame16,sensor->i2c_addr, P_MT9X001_CAM, v);
+        dev_dbg(g_dev_ptr,"SET_SENSOR_PAR(0x%x,0x%x, 0x%x, 0x%x)\n", frame16,  (int) sensor->i2c_addr, (int) P_MT9X001_CAM, (int) v);
      }
   } else { // 1.3 and 2 MPix sensors
      v=  (thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE1] & 0xffc3) | // preserve other bits from shadows (trigger mode moved to other function)
@@ -767,8 +770,8 @@ if (GLOBALPARS(sensor_port, G_MULTI_CFG) & (1 <<G_MULTI_CFG_BEFORE)) {
          ((dh == 8) ? (1 << 4) : 0) | // Column skip 8
          ((dv == 8) ? (1 << 5) : 0) ; // Row skip    8
      if (v != thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE1]) {
-        SET_SENSOR_MBPAR(sensor_port,fpga_addr,sensor->i2c_addr, P_MT9X001_RMODE1, v);
-        dev_dbg(g_dev_ptr,"%s   SET_SENSOR_MBPAR(0x%x,0x%x, 0x%x, 0x%x)\n",__func__, fpga_addr,  (int) sensor->i2c_addr, (int) P_MT9X001_RMODE1, (int) v);
+        SET_SENSOR_MBPAR(sensor_port,frame16,sensor->i2c_addr, P_MT9X001_RMODE1, v);
+        dev_dbg(g_dev_ptr,"SET_SENSOR_MBPAR(0x%x,0x%x, 0x%x, 0x%x)\n", frame16,  (int) sensor->i2c_addr, (int) P_MT9X001_RMODE1, (int) v);
      }
    }
 // Other registers are programmed individually
@@ -779,24 +782,24 @@ if (GLOBALPARS(sensor_port, G_MULTI_CFG) & (1 <<G_MULTI_CFG_BEFORE)) {
      wt=sensor_wt(wois[(P_MULTI_TOP1-   P_MULTI_WOI)+SENSOR_IN_SEQ(i,sequence)], wh, sFlipY[i], dv,     thispars->pars[P_OVERSIZE], sensor);
 
 // program sensor height
-     SET_SENSOR_MIBPAR_COND(sensor_port,fpga_addr,sensor->i2c_addr, i, P_MT9X001_HEIGHT, wh-1);
+     SET_SENSOR_MIBPAR_COND(sensor_port,frame16,sensor->i2c_addr, i, P_MT9X001_HEIGHT, wh-1);
 // Program sensor left margin
-     SET_SENSOR_MIBPAR_COND(sensor_port,fpga_addr,sensor->i2c_addr, i, P_MT9X001_COLSTART, wl);
+     SET_SENSOR_MIBPAR_COND(sensor_port,frame16,sensor->i2c_addr, i, P_MT9X001_COLSTART, wl);
 // Program sensor top margin
-       SET_SENSOR_MIBPAR_COND(sensor_port,fpga_addr,sensor->i2c_addr, i, P_MT9X001_ROWSTART, wt);
+       SET_SENSOR_MIBPAR_COND(sensor_port,frame16,sensor->i2c_addr, i, P_MT9X001_ROWSTART, wt);
 
      if((styp == MT9T_TYP) || (styp == MT9P_TYP)) { // 3MPix and 5MPix sensors
        v= (thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE2] & 0x3fff) | // preserve other bits from shadows
            (sFlipX[i] ? (1 << 14) : 0) | // FLIPH - will control just alternative rows
            (sFlipY[i] ? (1 << 15) : 0) ; // FLIPV
-       SET_SENSOR_MIBPAR_COND(sensor_port,fpga_addr,sensor->i2c_addr, i, P_MT9X001_RMODE2, v);
+       SET_SENSOR_MIBPAR_COND(sensor_port,frame16,sensor->i2c_addr, i, P_MT9X001_RMODE2, v);
      } else { // 1.3 and 2 MPix sensors
        v=  (thispars->pars[P_SENSOR_REGS+P_MT9X001_RMODE2] & 0x3fe7) | // preserve other bits from shadows
            ((dh == 2) ? (1 << 3) : 0) | // Column skip 2
            ((dv == 2) ? (1 << 4) : 0) | // Row skip    2
            (sFlipX[i] ? (1 << 14) : 0) | // FLIPH - will control just alternative rows
            (sFlipY[i] ? (1 << 15) : 0) ; // FLIPV
-       SET_SENSOR_MIBPAR_COND(sensor_port,fpga_addr,sensor->i2c_addr, i, P_MT9X001_RMODE2, v);
+       SET_SENSOR_MIBPAR_COND(sensor_port,frame16,sensor->i2c_addr, i, P_MT9X001_RMODE2, v);
      }
    }
   if (!(GLOBALPARS(sensor_port, G_MULTI_CFG) & (1 <<G_MULTI_CFG_BEFORE))) {  // try after sensors
@@ -950,6 +953,8 @@ int multisensor_pgm_detectsensor   (int sensor_port,               ///< sensor p
   int rslt=0; // or-ed by MULTISENSOR_WRITE_I2C(sa,ra,v,sz)
   int i;
   int this_sensor_type;
+
+  long * multiOutDelay;
 //   .hact_delay  = -2500,    // -2.5ns delay in ps
 //   .sensorDelay = 2460,     // Delay from sensor clock at FPGA output to pixel data transition (FPGA input), short cable (ps)
   multi_unitialized=0; // reset this static variable - it will prevent copying individual flips to multiple until composite mode is used
@@ -1076,7 +1081,7 @@ int multisensor_pgm_detectsensor   (int sensor_port,               ///< sensor p
 //  dev_dbg(g_dev_ptr,"%s  after: sensorproc_phys->sensor.sensorDelay=0x%x\n",__func__, sensorproc_phys->sensor.sensorDelay);
 
   // Now calculate phases, swap ones from the sensor
-  long * multiOutDelay= (long *) &GLOBALPARS(sensor_port, G_DLY359_OUT);
+  multiOutDelay= (long *) &GLOBALPARS(sensor_port, G_DLY359_OUT);
 // these two will be used to calulate sensor/hact phase in 10353
 
   sensor->hact_delay=0; // No hact delay on 10359 output
@@ -1189,19 +1194,34 @@ int multisensor_pgm_multisens (int sensor_port,               ///< sensor port n
   int i,j,sh;
   unsigned long wois[12];
   int dv=  thispars->pars[P_DCM_VERT];
-  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
 // Handling sensor mask - which sensors (of the available) to use
   int sensor_mask=(thispars->pars[P_MULTISENS_EN]) & GLOBALPARS(sensor_port, G_SENS_AVAIL);
-  if (!sensor_mask) sensor_mask=GLOBALPARS(sensor_port, G_SENS_AVAIL) ;// if none sensors were enabled - enable all what is available (same as with WOI size)
 // handling P_MULTI_SEQUENCE
   int sequence=       thispars->pars[P_MULTI_SEQUENCE];
-//  int prev_sequence=  prevpars->pars[P_MULTI_SEQUENCE];
   int async=          (thispars->pars[P_TRIG] & 4)?1:0;
   int composite=      (thispars->pars[P_MULTI_MODE])?1:0;
   int prev_composite= (prevpars->pars[P_MULTI_MODE])?1:0;
   int selected =      thispars->pars[P_MULTI_SELECTED];
   int prev_selected = prevpars->pars[P_MULTI_SELECTED];
 
+  int oversize;
+  int height1;
+  int height2;
+  int height3;
+  int vblank;
+  int total_height;
+  int multi_frame;
+
+  int multi_fliph=thispars->pars[P_MULTI_FLIPH];
+  int multi_flipv=thispars->pars[P_MULTI_FLIPV];
+  int old_sensor=prev_selected-1; // may be <0
+  int new_sensor=selected-1;     // >=0
+
+
+  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
+
+  if (!sensor_mask) sensor_mask=GLOBALPARS(sensor_port, G_SENS_AVAIL) ;// if none sensors were enabled - enable all what is available (same as with WOI size)
+
   if (composite && (!async)) {
     printk("*** CANNOT USE COMPOSITE MODE WITH FREE RUNNING SENSOR ***\n");
     composite=0;
@@ -1249,10 +1269,10 @@ int multisensor_pgm_multisens (int sensor_port,               ///< sensor port n
   SETFRAMEPARS_COND(P_MULTI_SEQUENCE, sequence);
   SETFRAMEPARS_COND(P_MULTISENS_EN,   sensor_mask);
   memcpy(wois, &(thispars->pars[P_MULTI_WOI]), sizeof(wois)); // copy WOI parameters for 3 sensors
-  int multi_fliph=thispars->pars[P_MULTI_FLIPH];
-  int multi_flipv=thispars->pars[P_MULTI_FLIPV];
-  int old_sensor=prev_selected-1; // may be <0
-  int new_sensor=selected-1;     // >=0
+//  int multi_fliph=thispars->pars[P_MULTI_FLIPH];
+//  int multi_flipv=thispars->pars[P_MULTI_FLIPV];
+//  int old_sensor=prev_selected-1; // may be <0
+//  int new_sensor=selected-1;     // >=0
   if (multi_unitialized && (!prev_composite) && (old_sensor>=0)) { // was single-sensor mode, copy P_WOI_* to individual sensor WOI and FLIPS
     dev_dbg(g_dev_ptr,"%s  multi_unitialized=%d  old_sensor=%x, multi_fliph=%x multi_flipv=%x\n",__func__,  multi_unitialized,  old_sensor, multi_fliph,multi_flipv);
     wois[(P_MULTI_WIDTH1- P_MULTI_WOI)+old_sensor]= prevpars->pars[P_WOI_WIDTH];
@@ -1297,13 +1317,13 @@ int multisensor_pgm_multisens (int sensor_port,               ///< sensor port n
     dev_dbg(g_dev_ptr,"%s  new_sensor=%x old_sensor=%x, multi_fliph=%x multi_flipv=%x\n",__func__,  new_sensor,  old_sensor, multi_fliph,multi_flipv);
   }
 // Validate hights for all enabled channels (OK to skip disabled here)
-  int oversize=thispars->pars[P_OVERSIZE];
+  oversize=thispars->pars[P_OVERSIZE];
 // some may be garbage if the channel is disabled, but it will not be used
-  int height1= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(0,sequence)];
-  int height2= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(1,sequence)];
-  int height3= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(2,sequence)];
-  int vblank=  (thispars->pars[P_MULTI_VBLANK]) & ~1; // even
-  int total_height=0;
+  height1= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(0,sequence)];
+  height2= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(1,sequence)];
+  height3= wois[(P_MULTI_HEIGHT1-P_MULTI_WOI)+SENSOR_IN_SEQ(2,sequence)];
+  vblank=  (thispars->pars[P_MULTI_VBLANK]) & ~1; // even
+  total_height=0;
   if      (!height1)                      height1=sensor->imageHeight;
   if      (height1 < sensor->minHeight)   height1=sensor->minHeight;
   else if (height1 > sensor->arrayHeight) height1=sensor->arrayHeight; // Includes black pixels
@@ -1312,7 +1332,7 @@ int multisensor_pgm_multisens (int sensor_port,               ///< sensor port n
   total_height=height1;
   dev_dbg(g_dev_ptr,"%s  total_height=0x%x\n",__func__,total_height);
 // is there frame 2 enabled?
-  int multi_frame=0;
+  multi_frame=0;
   if (composite && SENSOR_IN_SEQ_EN(1,sequence,sensor_mask)) {  // specified in sequence is enabled
     multi_frame=1;
     total_height+=(vblank+(2 * COLOR_MARGINS))*dv;
@@ -1392,10 +1412,10 @@ int calcThisPhase(int clk_period,   ///< cklock period (Hz)
 				                    ///< <90-degree-delay> << 16 |
 				                    ///< <finedelay>
 {
-    MDF16(printk ("cableDelay1=%ld, FPGADelay1=%ld, clk_period=%d\r\n",cableDelay, FPGADelay, clk_period));
     int px_delay=-(clk_period/2 - FPGADelay- cableDelay - sensorDelay) ; // static int sensorDelay
-    MDF16(printk ("px_delay1=%d\r\n",px_delay));
     int px_delay90=(4*px_delay+clk_period/2)/clk_period;
+    MDF16(printk ("cableDelay1=%ld, FPGADelay1=%ld, clk_period=%d\r\n",cableDelay, FPGADelay, clk_period));
+    MDF16(printk ("px_delay1=%d\r\n",px_delay));
     px_delay -= (px_delay90*clk_period)/4; // -clk_period/8<= now px_delay <= +clk_period/8
     MDF16(printk ("px_delay=%d, px_delay90=%d\r\n",px_delay,px_delay90));
     px_delay/= FPGA_DCM_STEP; // in DCM steps
@@ -1418,7 +1438,6 @@ int multisensor_pgm_sensorphase(int sensor_port,               ///< sensor port
   long * cableDelay;
   long * FPGADelay;
   int clk_period;
-  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
   long sdram_chen=thispars->pars[P_M10359_REGS+I2C359_SDRAM_CHEN];
   int adjustSDRAMNeed=0;
   int thisPhaseSDRAM=thispars->pars[P_MULTI_PHASE_SDRAM];
@@ -1426,6 +1445,7 @@ int multisensor_pgm_sensorphase(int sensor_port,               ///< sensor port
   int thisPhase2=    thispars->pars[P_MULTI_PHASE2];
   int thisPhase3=    thispars->pars[P_MULTI_PHASE3];
   uint64_t ull_result = 1000000000000LL;
+  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
   if (frame16 >= 0) return -1; // can only work in ASAP mode
  //changed (just set) clock frequency initiates calculation of phase settings
   if (!multi_phases_initialized || (thispars->pars[P_CLK_SENSOR] != prevpars->pars[P_CLK_SENSOR]))  { // system clock is already set to the new frequency
@@ -1744,14 +1764,14 @@ int  multisensor_adjustSDRAM (int sensor_port, ///< sensor_port Sensor port (0..
   int results90 [4];
   int i;
   int oldPhase=0;
-  oldPhase=  multisensor_set_phase_verify (sensor_port, I2C359_DCM_SDRAM, 1, 0, oldPhase); // reset SDRAM phase
-  if (oldPhase<0) return oldPhase; // failed to reset
   int needReset=0;
   int ok90=0;
   int oks90=0;
   int low90=-1;
   int high90=-1;
   int low_l, low_h, high_l,high_h;
+  oldPhase=multisensor_set_phase_verify (sensor_port, I2C359_DCM_SDRAM, 1, 0, oldPhase); // reset SDRAM phase
+  if (oldPhase<0) return oldPhase; // failed to reset
   for (i=0; i<4; i++) {
     oldPhase= multisensor_set_phase_verify (sensor_port, I2C359_DCM_SDRAM, needReset, i<<16, oldPhase); // do not reset SDRAM phase - no fine tuning
     if (oldPhase<0) return oldPhase; // any error is fatal here
@@ -1938,6 +1958,7 @@ int multisensor_memphase (int sensor_port,          ///< Sensor port
     int s=0;
     int sx=0;
     int rslt=0;
+    int OK;
     MULTISENSOR_WRITE_I2C32(sensor_port, I2C359_SDRAM_CHEN,  I2C359_SDRAM_STOP(4) | I2C359_SDRAM_STOP(5)); // initialize write and read channels, reset SDRAM and buffer addresses
     MULTISENSOR_WRITE_I2C32(sensor_port, I2C359_SDRAM_CHEN,  I2C359_SDRAM_RUN(4)  | I2C359_SDRAM_RUN(5));  // enable write and read channels
     for (i=0; i<64;i++) {
@@ -1965,7 +1986,7 @@ int multisensor_memphase (int sensor_port,          ///< Sensor port
             d>>=1;
         }
     }
-    int OK=(setbits[0]==0) && (setbits[1]==0) && (setbits[2]==0) && (setbits[3]==0x80) && (setbits[4]==0x80) && (setbits[5]==0x80) && (setbits[6]==0) && (setbits[7]==0);
+    OK=(setbits[0]==0) && (setbits[1]==0) && (setbits[2]==0) && (setbits[3]==0x80) && (setbits[4]==0x80) && (setbits[5]==0x80) && (setbits[6]==0) && (setbits[7]==0);
     //    for (i=0; i<8;i++)    printk (" %03x ",setbits[i]); printk("\n");
     n=(0x10000*sx)/s;
     if (centroid0x10000) centroid0x10000[0]=n;
@@ -1984,6 +2005,7 @@ int multisensor_memphase_debug (int sensor_port, ///< Sesnor port number (0..3)
     int s=0;
     int sx=0;
     int rslt=0;
+    int OK;
     if (write >=0) {
         MULTISENSOR_WRITE_I2C32(sensor_port, I2C359_SDRAM_CHEN,  I2C359_SDRAM_STOP(4) | I2C359_SDRAM_STOP(5)); // initialize write and read channels, reset SDRAM and buffer addresses
         MULTISENSOR_WRITE_I2C32(sensor_port, I2C359_SDRAM_CHEN,  I2C359_SDRAM_RUN(4)  | I2C359_SDRAM_RUN(5));  // enable write and read channels
@@ -2019,7 +2041,7 @@ int multisensor_memphase_debug (int sensor_port, ///< Sesnor port number (0..3)
             d>>=1;
         }
     }
-    int OK=(setbits[0]==0) && (setbits[1]==0) && (setbits[2]==0) && (setbits[3]==0x80) && (setbits[4]==0x80) && (setbits[5]==0x80) && (setbits[6]==0) && (setbits[7]==0);
+    OK=(setbits[0]==0) && (setbits[1]==0) && (setbits[2]==0) && (setbits[3]==0x80) && (setbits[4]==0x80) && (setbits[5]==0x80) && (setbits[6]==0) && (setbits[7]==0);
     for (i=0; i<8;i++)    printk (" %03x ",setbits[i]); printk("\n");
     n=(0x10000*sx)/s;
     printk ("Centroid - 0x%x, sx=0x%x, s=0x%x. OK=%d\n",n, sx,s,OK);
@@ -2039,8 +2061,6 @@ int multisensor_pgm_sensorregs (int sensor_port,               ///< sensor port
 															   ///< @return always 0
 
 {
-  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
-  if (frame16 >= PARS_FRAMES) return -1; // wrong frame
 //  int fpga_addr=(frame16 <0) ? X313_I2C_ASAP : (X313_I2C_FRAME0+frame16);
   int fpga_addr=frame16;
 // do whatever is needed for 10359 registers, then call sesnor function (if available)
@@ -2052,9 +2072,12 @@ int multisensor_pgm_sensorregs (int sensor_port,               ///< sensor port
 // It will be the first for the frame (before automatic sensor changes).
 // Add testing for programmed sensor and move vbalues to later frames (not here but in the pgm_functions)
   unsigned long bmask32= ((thispars->mod32) >> (P_M10359_REGS>>5)) & (( 1 << (P_M10359_NUMREGS >> 5))-1) ;
-  dev_dbg(g_dev_ptr,"%s  bmask32=0x%lx, thispars->mod32=0x%lx, P_M10359_REGS=0x%x, P_M10359_NUMREGS=0x%x\n",__func__,bmask32,thispars->mod32,P_M10359_REGS,P_M10359_NUMREGS);
   unsigned long mask;
   int index,index32;
+  dev_dbg(g_dev_ptr,"%s  frame16=%d\n",__func__,frame16);
+  if (frame16 >= PARS_FRAMES) return -1; // wrong frame
+  dev_dbg(g_dev_ptr,"%s  bmask32=0x%lx, thispars->mod32=0x%lx, P_M10359_REGS=0x%x, P_M10359_NUMREGS=0x%x\n",__func__,bmask32,thispars->mod32,P_M10359_REGS,P_M10359_NUMREGS);
+
   if (bmask32) {
     for (index32=(P_M10359_REGS>>5); bmask32; index32++, bmask32 >>= 1) {
        dev_dbg(g_dev_ptr,"%s  index32=0x%x, bmask32=0x%lx\n",__func__,index32,bmask32);

src/drivers/elphel/sensor_common.h

@@ -123,7 +123,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
  * @param reg sensor register address (8-bit)
  * @param datap pointer to receive data
  * @return  0 on success, < 0 - error (ETIMEDOUT) */
-#define X3X3_I2C_RCV2(port,sa7,reg,datap) legacy_read_i2c_reg((port),(LEGACY_READ_PAGE2),(sa7),(reg),2,(datap))
+#define X3X3_I2C_RCV2(port,sa7,reg,datap) legacy_read_i2c_reg((port),(LEGACY_READ_PAGE2),(sa7),(reg),2, (int*)(datap))
 
 /** Perform I2C read (8  bits address, 32 bits data in "legacy" mode (10359 in 32-bit mode),
  * page LEGACY_READ_PAGE2 (==0xff) should be registered - legacy_i2c.
@@ -134,7 +134,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
  * @param reg sensor register address (8-bit)
  * @param datap pointer to receive data
  * @return  0 on success, < 0 - error (ETIMEDOUT) */
-#define X3X3_I2C_RCV4(port,sa7,reg,datap) legacy_read_i2c_reg((port),(LEGACY_READ_PAGE4),(sa7),(reg),4,(datap))
+#define X3X3_I2C_RCV4(port,sa7,reg,datap) legacy_read_i2c_reg((port),(LEGACY_READ_PAGE4),(sa7),(reg),4,(int*)(datap))
 
 int legacy_i2c  (int ports);
 void udelay1000(int ms);