fixed: accidentally used dts'es from rocko branch during DT optimization for various builds

src/arch/arm/boot/dts/elphel393-common.dtsi

@@ -118,21 +118,12 @@
 			};
 		};
 
-		ps7_smcc_0: ps7-smcc@e000e000 {
-			ps7_nand_0: ps7-nand@e1000000 {
-				compatible = "arm,pl353-nand-r2p1";
-				reg = < 0xe1000000 0x1000000 >;
-				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
-				arm,nand-width = <0x8>;
-				arm,nand-cycle-t0 = <0x4>;
-				arm,nand-cycle-t1 = <0x4>;
-				arm,nand-cycle-t2 = <0x1>;
-				arm,nand-cycle-t3 = <0x2>;
-				arm,nand-cycle-t4 = <0x2>;
-				arm,nand-cycle-t5 = <0x2>;
-				arm,nand-cycle-t6 = <0x4>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
+		smcc: memory-controller@e000e000 {
+			nand0: flash@e1000000 {
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
 					partition@0 {
 						label = "u-boot-spl";
 						reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/
@@ -154,7 +145,8 @@
 						/*reg = <0x1600000 0x10000000>;*/ /*256MB*/
 						reg = <0x1600000 0x14000000>; /*320MB*/
 					};
-			} ;
+				};
+                        };
 		} ;
 
 		elphel_ahci: elphel-ahci@80000000 {

src/arch/arm/boot/dts/elphel393-zynq-base.dtsi

@@ -296,24 +296,23 @@
 			reg = <0xf8001000 0x1000>;
 		} ;
 
-		ps7_smcc_0: ps7-smcc@e000e000 {
-			#address-cells = <1>;
+		smcc: memory-controller@e000e000 {
+			#address-cells = <2>;
 			#size-cells = <1>;
-		  	clock-names = "memclk", "aclk";
+		  	clock-names = "memclk", "apb_pclk";
 			clocks = <&clkc 11>, <&clkc 44>;
-			compatible = "arm,pl353-smc-r2p1";
+			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
 			interrupt-parent = <&ps7_scugic_0>;
 			interrupts = < 0 18 4 >;
-			ranges ;
-			reg = < 0xe000e000 0x1000 >;
-			arm,addr25 = <0x0>;
-			arm,nor-chip-sel0 = <0x0>;
-			arm,nor-chip-sel1 = <0x0>;
-			arm,sram-chip-sel0 = <0x0>;
-			arm,sram-chip-sel1 = <0x0>;
-			ps7_nand_0: ps7-nand@e1000000 {
+			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
+				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
+				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
+
+			reg = <0xe000e000 0x1000>;
+			nand0: flash@e1000000 {
 				compatible = "arm,pl353-nand-r2p1";
-				reg = < 0xe1000000 0x1000000 >;
+				reg = <0 0 0x1000000>;
+                                nand-ecc-mode = "on-die";
 				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
 				arm,nand-width = <0x8>;
 				arm,nand-cycle-t0 = <0x4>;