updated nand driver from linux-xlnx 4.14 to 4.19

src/arch/arm/boot/dts/elphel393-zynq-base.dtsi

@@ -296,24 +296,24 @@
 			reg = <0xf8001000 0x1000>;
 		} ;
 
-		ps7_smcc_0: ps7-smcc@e000e000 {
-			#address-cells = <1>;
+		smcc: memory-controller@e000e000 {
+			#address-cells = <2>;
 			#size-cells = <1>;
-		  	clock-names = "memclk", "aclk";
+		  	clock-names = "memclk", "apb_pclk";
 			clocks = <&clkc 11>, <&clkc 44>;
-			compatible = "arm,pl353-smc-r2p1";
+			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
 			interrupt-parent = <&ps7_scugic_0>;
 			interrupts = < 0 18 4 >;
-			ranges ;
-			reg = < 0xe000e000 0x1000 >;
-			arm,addr25 = <0x0>;
-			arm,nor-chip-sel0 = <0x0>;
-			arm,nor-chip-sel1 = <0x0>;
-			arm,sram-chip-sel0 = <0x0>;
-			arm,sram-chip-sel1 = <0x0>;
-			ps7_nand_0: ps7-nand@e1000000 {
+			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
+				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
+				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
+
+			reg = <0xe000e000 0x1000>;
+			nand0: flash@e1000000 {
 				compatible = "arm,pl353-nand-r2p1";
-				reg = < 0xe1000000 0x1000000 >;
+				reg = <0 0 0x1000000>;
+                                nand-ecc-mode = "on-die";
+                                nand-ecc-step-size = <2048>;
 				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
 				arm,nand-width = <0x8>;
 				arm,nand-cycle-t0 = <0x4>;

src/arch/arm/boot/dts/elphel393_4_mt9p006.dts

@@ -119,21 +119,12 @@
 			};
 		};
 
-		ps7_smcc_0: ps7-smcc@e000e000 {
-			ps7_nand_0: ps7-nand@e1000000 {
-				compatible = "arm,pl353-nand-r2p1";
-				reg = < 0xe1000000 0x1000000 >;
-				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
-				arm,nand-width = <0x8>;
-				arm,nand-cycle-t0 = <0x4>;
-				arm,nand-cycle-t1 = <0x4>;
-				arm,nand-cycle-t2 = <0x1>;
-				arm,nand-cycle-t3 = <0x2>;
-				arm,nand-cycle-t4 = <0x2>;
-				arm,nand-cycle-t5 = <0x2>;
-				arm,nand-cycle-t6 = <0x4>;
-				#address-cells = <0x1>;
-				#size-cells = <0x1>;
+		smcc: memory-controller@e000e000 {
+			nand0: flash@e1000000 {
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
 					partition@0 {
 						label = "u-boot-spl";
 						reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/
@@ -154,6 +145,7 @@
 						label = "rootfs";
 						reg = <0x1600000 0x10000000>;/*256MB*/
 					};
+				};
 			} ;
 		} ;
 

src/drivers/mtd/nand/Makefile → src/drivers/mtd/nand/raw/Makefile

 # SPDX-License-Identifier: GPL-2.0
-#
-# linux/drivers/nand/Makefile
-#
 
 obj-$(CONFIG_MTD_NAND)			+= nand.o
 obj-$(CONFIG_MTD_NAND_ECC)		+= nand_ecc.o
@@ -14,7 +11,6 @@ obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
 obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
 obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
 obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
-obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
 obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o
 obj-$(CONFIG_MTD_NAND_TANGO)		+= tango_nand.o
 obj-$(CONFIG_MTD_NAND_DAVINCI)		+= davinci_nand.o
@@ -31,7 +27,7 @@ omap2_nand-objs := omap2.o
 obj-$(CONFIG_MTD_NAND_OMAP2) 		+= omap2_nand.o
 obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD)	+= omap_elm.o
 obj-$(CONFIG_MTD_NAND_CM_X270)		+= cmx270_nand.o
-obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx_nand.o
+obj-$(CONFIG_MTD_NAND_MARVELL)		+= marvell_nand.o
 obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
 obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
 obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
@@ -56,17 +52,18 @@ obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
 obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
 obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_nand.o
-obj-$(CONFIG_MTD_NAND_PL35X)		+= pl35x_nand.o
-obj-$(CONFIG_MTD_NAND_ARASAN)		+= arasan_nand.o
 obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
-obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o mtk_ecc.o
+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
+obj-$(CONFIG_MTD_NAND_ARASAN)		+= arasan_nand.o
+obj-$(CONFIG_MTD_NAND_PL353)		+= pl353_nand.o
 
-nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o nandchip-micron.o
+nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
 nand-objs += nand_hynix.o
 nand-objs += nand_macronix.o
-nand-objs += nand_micron.o
+nand-objs += nand_micron.o nand_micron_mt29f.o
 nand-objs += nand_samsung.o
 nand-objs += nand_toshiba.o

src/drivers/mtd/nand/nand.h → src/drivers/mtd/nand/raw/nand.h

@@ -2,12 +2,11 @@
 
 #define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
 
+int nand_check_wp(struct mtd_info *mtd);
+int check_offs_len(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 int nand_get_device(struct mtd_info *mtd, int new_state);
 void nand_release_device(struct mtd_info *mtd);
+int nand_do_read_ops(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+int nand_do_write_ops(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops);
 
-int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
-			    struct mtd_oob_ops *ops);
-int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
-			     struct mtd_oob_ops *ops);
-
-void nandchip_micron_init(struct mtd_info *mtd, int dev_id);
+void nand_micron_mt29f_init(struct mtd_info *mtd, int dev_id);

src/drivers/mtd/nand/nandchip-micron.c → src/drivers/mtd/nand/raw/nand_micron_mt29f.c

@@ -48,7 +48,6 @@ static int mt29f_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
 	struct nand_chip *chip = mtd->priv;
 	struct mtd_oob_ops ops;
 	int ret;
-	u8 get_feature;
 
 	/* Valid pages in otp are 02h-1Fh. */
 	if (from > MICRON_NUM_OTP_PAGES << chip->page_shift)
@@ -63,19 +62,18 @@ static int mt29f_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
 	nand_get_device(mtd, FL_READING);
 	chip->select_chip(mtd, 0);
 
-	ret = chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,MICRON_SETFEATURE_ARRAYOP_OTP);
-	ndelay(1000);
-	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, MICRON_SETFEATURE_ARRAYOP, -1);
-	get_feature = readb(chip->IO_ADDR_R);
-	pr_debug("Feature on: 0x%02x\n",get_feature);
-
+	ret = nand_set_features(chip, MICRON_SETFEATURE_ARRAYOP, MICRON_SETFEATURE_ARRAYOP_OTP);
 	if (ret)
 		goto out;
 
 	ops.len = len;
 	ops.datbuf = buf;
 	ops.oobbuf = NULL;
-	ops.mode = 0;
+	// old, triggers chip->ecc.read_page() which enables/disables ondie ECC at each call
+	//ops.mode = 0;
+	// new, triggers chip->ecc.read_page_raw()
+	ops.mode = MTD_OPS_RAW;
+
 	/*
 	 * XXX: some things in nand_do_read_ops might be wrong for OTP. e.g.
 	 * chip->pagemask, chip->pagebuf handling, caching
@@ -86,11 +84,7 @@ static int mt29f_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
 	/* nand_do_read_ops deselects the chip so reselect here */
 	chip->select_chip(mtd, 0);
 
-	chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,MICRON_SETFEATURE_ARRAYOP_NORMAL);
-	ndelay(1000);
-	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, MICRON_SETFEATURE_ARRAYOP, -1);
-	get_feature = readb(chip->IO_ADDR_R);
-	pr_debug("Feature off: 0x%02x\n",get_feature);
+	ret = nand_set_features(chip, MICRON_SETFEATURE_ARRAYOP, MICRON_SETFEATURE_ARRAYOP_NORMAL);
 
 out:
 	nand_release_device(mtd);
@@ -118,17 +112,19 @@ static int mt29f_write_user_prot_reg(struct mtd_info *mtd, loff_t to,
 	nand_get_device(mtd, FL_WRITING);
 
 	chip->select_chip(mtd, 0);
-
-	ret = chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
-			MICRON_SETFEATURE_ARRAYOP_OTP);
-
+	ret = nand_set_features(chip, MICRON_SETFEATURE_ARRAYOP, MICRON_SETFEATURE_ARRAYOP_OTP);
 	if (ret)
 		goto out;
 
 	ops.len = len;
 	ops.datbuf = buf;
 	ops.oobbuf = NULL;
-	ops.mode = 0;
+
+	// old
+	//ops.mode = 0;
+	// need raw mode
+	ops.mode = MTD_OPS_RAW;
+
 	/*
 	 * some things in nand_do_write_ops might be wrong for OTP. e.g.
 	 * chip->pagemask, chip->pagebuf handling
@@ -138,9 +134,7 @@ static int mt29f_write_user_prot_reg(struct mtd_info *mtd, loff_t to,
 
 	/* nand_do_write_ops deselects the chip so reselect here */
 	chip->select_chip(mtd, 0);
-
-	chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
-			MICRON_SETFEATURE_ARRAYOP_NORMAL);
+	ret = nand_set_features(chip, MICRON_SETFEATURE_ARRAYOP, MICRON_SETFEATURE_ARRAYOP_NORMAL);
 
 out:
 	nand_release_device(mtd);
@@ -153,6 +147,7 @@ static int mt29f_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
 	struct nand_chip *chip = mtd->priv;
 	int ret;
 	int i;
+	uint8_t zerobuf = 0;
 
 	/* assert from and len are aligned */
 	if (NOTALIGNED(from) || NOTALIGNED(len)) {
@@ -175,29 +170,36 @@ static int mt29f_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
 	nand_get_device(mtd, FL_WRITING);
 
 	chip->select_chip(mtd, 0);
-
-	ret = chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
+	ret = chip->set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
 			MICRON_SETFEATURE_ARRAYOP_OTPPROTECT);
 	if (ret)
 		goto out;
 
+	// old
+	/*
 	for (i = 0; i < len << chip->page_shift; ++i) {
 		chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0,
 				(from << chip->page_shift) + i);
-
 		chip->write_byte(mtd, 0);
-
 		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 	}
+	*/
+
+	// new
+	// TODO: Test this? Not critical. It's doubtful locking OTP will ever be needed.
+	for (i = 0; i < len << chip->page_shift; ++i) {
+		nand_prog_page_op(chip,(from << chip->page_shift)+i, 0, &zerobuf, 1);
+	}
 
-	chip->onfi_set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
+	chip->set_features(mtd, chip, MICRON_SETFEATURE_ARRAYOP,
 			MICRON_SETFEATURE_ARRAYOP_NORMAL);
+
 out:
 	nand_release_device(mtd);
 	return ret;
 }
 
-void nandchip_micron_init(struct mtd_info *mtd, int dev_id)
+void nand_micron_mt29f_init(struct mtd_info *mtd, int dev_id)
 {
 	/*
 	 * OTP is available on (at least) Micron's MT29F2G{08,16}AB[AB]EA,