ahci_elphel.c 60.5 KB
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/*
 * Elphel AHCI SATA platform driver for elphel393 camera
 *
 * Based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ahci_platform.h>
#include <linux/of.h>
#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
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#include <linux/sysfs.h>
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#include <linux/uio.h>
//#include <asm/uaccess.h>

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#include "ahci.h"
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#include "ahci_elphel.h"
#include "../elphel/exif393.h"
#include "../elphel/exifa.h"
#include "../elphel/jpeghead.h"
//#include "../elphel/circbuf.h"
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#include <elphel/elphel393-mem.h>

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#define DRV_NAME "elphel-ahci"
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/*
 * FPGA bitstream control address and bit mask. These are used to check whether
 * bitstream is loaded or not.
 */
#define BITSTREAM_CTRL_ADDR	0xf800700c
#define BITSTREAM_CTRL_BIT	0x4
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/* Property names from device tree, these are specific for the controller */
#define PROP_NAME_CLB_OFFS "clb_offs"
#define PROP_NAME_FB_OFFS "fb_offs"
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/** Maximum number of sectors for READ DMA or WRITE DMA commands */
#define MAX_LBA_COUNT             0xff
/** Maximum number of sectors for READ DMA EXT or WRITE_DMA EXT commands */
#define MAX_LBA_COUNT_EXT         0xffff
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static struct ata_port_operations ahci_elphel_ops;
static const struct ata_port_info ahci_elphel_port_info;
static struct scsi_host_template ahci_platform_sht;
static const struct of_device_id ahci_elphel_of_match[];
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static const struct attribute_group dev_attr_root_group;

static bool load_driver = false;
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static void elphel_cmd_issue(struct ata_port *ap, uint64_t start, uint16_t count, struct fvec *sgl, unsigned int elem, uint8_t cmd);
static int init_buffers(struct device *dev, struct frame_buffers *buffs);
static void init_vectors(struct elphel_ahci_priv *dpriv);
static void deinit_buffers(struct device *dev, struct frame_buffers *buffs);
static inline struct elphel_ahci_priv *dev_get_dpriv(struct device *dev);
static void finish_cmd(struct device *dev, struct elphel_ahci_priv *dpriv);
static int process_cmd(struct device *dev, struct elphel_ahci_priv *dpriv, struct ata_port *port);
//static void start_cmd(struct device *dev, struct elphel_ahci_priv *dpriv, struct ata_port *port);
static inline size_t get_size_from(const struct fvec *vects, int index, size_t offset, int all);
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static ssize_t set_load_flag(struct device *dev, struct device_attribute *attr,
		const char *buff, size_t buff_sz)
{
	load_driver = true;

	return buff_sz;
}

static int bitstream_loaded(u32 *ptr)
{
	u32 val = ioread32(ptr);

	if (val & BITSTREAM_CTRL_BIT)
		return 1;
	else
		return 0;
}

static void elphel_defer_load(struct device *dev)
{
	bool check_flag = true;
	u32 *ctrl_ptr = ioremap_nocache(BITSTREAM_CTRL_ADDR, 4);

	dev_info(dev, "AHCI driver loading is deferred. Load bitstream and write 1 into "
			"/sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module to continue\n");
	while (check_flag) {
		if (load_driver) {
			if (bitstream_loaded(ctrl_ptr)) {
				check_flag = false;
			} else {
				dev_err(dev, "FPGA bitstream is not loaded or bitstream "
						"does not contain AHCI controller\n");
				load_driver = false;
			}
		} else {
			msleep(1000);
		}
	}
	load_driver = false;
	iounmap(ctrl_ptr);
}

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static irqreturn_t elphel_irq_handler(int irq, void * dev_instance)
{
	irqreturn_t handled;
	struct ata_host *host = dev_instance;
	struct ahci_host_priv *hpriv = host->private_data;
	struct ata_port *port = host->ports[DEFAULT_PORT_NUM];
	void __iomem *port_mmio = ahci_port_base(port);
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;
	uint32_t irq_stat, host_irq_stat;


	if (dpriv->flags & IRQ_SIMPLE) {
		/* handle interrupt */
		host_irq_stat = readl(hpriv->mmio + HOST_IRQ_STAT);
		if (!host_irq_stat)
			return IRQ_NONE;
		dpriv->flags &= ~IRQ_SIMPLE;
		irq_stat = readl(port_mmio + PORT_IRQ_STAT);

		printk(KERN_DEBUG "irq_stat = 0x%x, host irq_stat = 0x%x\n", irq_stat, host_irq_stat);

//		writel(irq_stat, port_mmio + PORT_IRQ_STAT);
		writel(0xffffffff, port_mmio + PORT_IRQ_STAT);

		writel(host_irq_stat, hpriv->mmio + HOST_IRQ_STAT);
		handled = IRQ_HANDLED;

//		if (proc_cmd(host->dev, dpriv, host->ports[0]) == 0)
//			finish_cmd(host->dev, dpriv);
	} else {
		/* pass handling to AHCI level */
		handled = ahci_single_irq_intr(irq, dev_instance);
	}

	return handled;
}

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// What about port_stop and freeing/unmapping ?
// Or at least check if it is re-started and memory is already allocated/mapped
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static int elphel_port_start(struct ata_port *ap)
{
	void *mem;
	dma_addr_t mem_dma;
	struct device *dev = ap->host->dev;
	struct ahci_port_priv *pp;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	const struct elphel_ahci_priv *dpriv = hpriv->plat_data;

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	dev_dbg(dev, "starting port %d", ap->port_no);
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	pp = devm_kzalloc(dev, sizeof(struct ahci_port_priv), GFP_KERNEL);
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	if (!pp)
		return -ENOMEM;

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	mem = devm_kmalloc(dev, 0x100000, GFP_KERNEL); // AHCI_CMD_TBL_AR_SZ = 0x16000
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	if (!mem)
		return -ENOMEM;
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	mem_dma = dma_map_single(dev, mem, AHCI_CMD_TBL_AR_SZ, DMA_TO_DEVICE); // maybe DMA_BIDIRECTIONAL, but currently we do not use DMA for received FISes

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	pp->cmd_tbl = mem;
	pp->cmd_tbl_dma = mem_dma;
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	/*
	 * Set predefined addresses
	 */
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	pp->cmd_slot = hpriv->mmio + dpriv->clb_offs;
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	pp->cmd_slot_dma = dpriv->base_addr + dpriv->clb_offs;
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	pp->rx_fis = hpriv->mmio + dpriv->fb_offs;
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	pp->rx_fis_dma = dpriv->base_addr + dpriv->fb_offs;
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	/*
	 * Save off initial list of interrupts to be enabled.
	 * This could be changed later
	 */
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	pp->intr_mask = DEF_PORT_IRQ;
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	ap->private_data = pp;

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	return ahci_port_resume(ap);
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}

static int elphel_parse_prop(const struct device_node *devn,
		struct device *dev,
		struct elphel_ahci_priv *dpriv)
{
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	int rc = 0;
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	const __be32 *val;
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	struct resource res;
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	if (!devn) {
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		dev_err(dev, "elphel-ahci device tree node is not found");
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		return -EINVAL;
	}

	val = of_get_property(devn, PROP_NAME_CLB_OFFS, NULL);
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	if (!val) {
		dev_err(dev, "can not find clb_offs in device tree");
		return -EINVAL;
	}
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	dpriv->clb_offs = be32_to_cpup(val);
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	val = of_get_property(devn, PROP_NAME_FB_OFFS, NULL);
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	if (!val) {
		dev_err(dev, "can not find fb_offs in device tree");
		return -EINVAL;
	}
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	dpriv->fb_offs = be32_to_cpup(val);
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	rc = of_address_to_resource((struct device_node *)devn, 0, &res);
	if (rc < 0) {
		dev_err(dev, "can not find address in device tree");
		return -EINVAL;
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	}
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	dpriv->base_addr = (u32)res.start;
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	return 0;
}

static int elphel_drv_probe(struct platform_device *pdev)
{
	int ret;
	struct ahci_host_priv *hpriv;
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	struct elphel_ahci_priv *dpriv;
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	struct device *dev = &pdev->dev;
	const struct of_device_id *match;

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	if (&dev->kobj) {
		ret = sysfs_create_group(&dev->kobj, &dev_attr_root_group);
		if (ret < 0)
			return ret;
	}
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//	elphel_defer_load(dev);
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	dev_info(&pdev->dev, "probing Elphel AHCI driver");
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	dpriv = devm_kzalloc(dev, sizeof(struct elphel_ahci_priv), GFP_KERNEL);
	if (!dpriv)
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		return -ENOMEM;

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	ret = init_buffers(dev, &dpriv->fbuffs);
	if (ret != 0)
		return ret;
//	sg_init_table(dpriv->sgl, MAX_DATA_CHUNKS);
	init_vectors(dpriv);

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	match = of_match_device(ahci_elphel_of_match, &pdev->dev);
	if (!match)
		return -EINVAL;

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	ret = elphel_parse_prop(dev->of_node, dev, dpriv);
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	if (ret != 0)
		return ret;

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	hpriv = ahci_platform_get_resources(pdev);
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	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

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	hpriv->plat_data = dpriv;
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	ret = ahci_platform_init_host(pdev, hpriv, &ahci_elphel_port_info,
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			&ahci_platform_sht);
	if (ret) {
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		dev_err(dev, "can not initialize platform host");
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		ahci_platform_disable_resources(hpriv);
		return ret;
	}
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	/* reassign interrupt handler*/
	int rc;
	unsigned int irq_flags = IRQF_SHARED;
	int irq = platform_get_irq(pdev, 0);
	struct ata_host *ahost = platform_get_drvdata(pdev);
	printk(KERN_DEBUG ">>> removing automatically assigned irq handler\n");
	devm_free_irq(dev, irq, ahost);
	rc = devm_request_irq(dev, irq, elphel_irq_handler, irq_flags, dev_name(dev), ahost);
	if (rc) {
		printk(KERN_DEBUG ">>> failed to request irq\n");
		return rc;
	}
	printk(KERN_DEBUG ">>> irq handler reassigned\n");
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	return 0;
}

static int elphel_drv_remove(struct platform_device *pdev)
{
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	struct elphel_ahci_priv *dpriv = dev_get_dpriv(&pdev->dev);

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	dev_info(&pdev->dev, "removing Elphel AHCI driver");
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	deinit_buffers(&pdev->dev, &dpriv->fbuffs);
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	sysfs_remove_group(&pdev->dev.kobj, &dev_attr_root_group);
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	ata_platform_remove_one(pdev);

	return 0;
}

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void dump_tf_addr(struct ata_taskfile *tf)
{
	printk(KERN_DEBUG ">>> taskfile dump: lbal = 0x%x, lbam = 0x%x, lbah = 0x%x, "
			"hob_lbal = 0x%x, hod_lbam = 0x%x, hob_lbah = 0x%x\n",
			tf->lbal, tf->lbam, tf->lbah,
			tf->hob_lbal, tf->hob_lbam, tf->hob_lbah);
}
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static void elphel_qc_prep(struct ata_queued_cmd *qc)
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{
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	struct ata_port *ap = qc->ap;
	struct ahci_port_priv *pp = ap->private_data;
	int is_atapi = ata_is_atapi(qc->tf.protocol);
	void *cmd_tbl;
	u32 opts;
	const u32 cmd_fis_len = 5; /* five dwords */
	unsigned int n_elem;
	struct scatterlist *sg;
	struct ahci_sg *ahci_sg;

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	/* There is only one slot in controller thus we need to change tag*/
	qc->tag = 0;

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	/*
	 * Fill in command table information.  First, the header,
	 * a SATA Register - Host to Device command FIS.
	 */
	dma_sync_single_for_cpu(&qc->dev->tdev, pp->cmd_tbl_dma,
			AHCI_CMD_TBL_AR_SZ, DMA_TO_DEVICE);
	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;

	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);

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	dev_dbg(ap->dev, ">>> CFIS dump, data from libahci, phys addr = 0x%x:\n", pp->cmd_tbl_dma);
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	print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, cmd_tbl, 20);

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	if (is_atapi) {
		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
	}

	/*
	 * Next, the S/G list.
	 */
	n_elem = 0;
	ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
	if (qc->flags & ATA_QCFLAG_DMAMAP) {
		for_each_sg(qc->sg, sg, qc->n_elem, n_elem) {
			dma_addr_t addr = sg_dma_address(sg);
			u32 sg_len = sg_dma_len(sg);

			ahci_sg[n_elem].addr = cpu_to_le32(addr & 0xffffffff);
			ahci_sg[n_elem].addr_hi = cpu_to_le32((addr >> 16) >> 16);
			ahci_sg[n_elem].flags_size = cpu_to_le32(sg_len - 1);
		}
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	}
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	/*
	 * Fill in command slot information.
	 */
	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		opts |= AHCI_CMD_WRITE;
	if (is_atapi)
		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;

	ahci_fill_cmd_slot(pp, qc->tag, opts);
	dma_sync_single_for_device(&qc->dev->tdev, pp->cmd_tbl_dma,
			AHCI_CMD_TBL_AR_SZ, DMA_TO_DEVICE);
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}

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/* ============================================== */
#define TEST_BUFF_SZ              512
#define MAX_IOVECTORS             10
/** The position of size field in copy buffer */
#define VECTOR_SZ_POS             0
/** The position of vector pointer field in copy buffer */
#define POINTER_POS               1
/** Physical disk block size */
#define PHY_BLOCK_SIZE            512
//#define PHY_BLOCK_SIZE            4096
#define JPEG_MARKER_LEN           2
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/** The size in bytes of JPEG marker length field */
#define JPEG_SIZE_LEN             2
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#define SG_TBL_SZ                 256
/** Include REM buffer to total size calculation */
#define INCLUDE_REM               1
/** Exclude REM buffer from total size calculation */
#define EXCLUDE_REM               0

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//#define DEBUG_DONT_WRITE
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unsigned char app15[ALIGNMENT_SIZE] = {0xff, 0xef};

/* this should be placed to system includes directory*/
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#define DRV_CMD_WRITE             0
#define DRV_CMD_FINISH            1
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struct frame_data {
	unsigned int sensor_port;
	int cirbuf_ptr;
	int jpeg_len;
	int meta_index;
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	int cmd;
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};
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/* end of system includes */

/* Debug functions */
#define DATA_BUFF_SIZE            500000
unsigned char *g_jpg_data_0;
unsigned char *g_jpg_data_1;
int use_preset;
size_t g_jpg_0_sz;
size_t g_jpg_1_sz;
ssize_t g_exif_sz;
ssize_t g_jpg_hdr_sz;
static size_t exif_get_data_tst(int sensor_port, unsigned short meta_index, void *buff, size_t buff_sz, int enable)
{
	int i;
	const int default_exif_sz = 774;
	int exif_sz;
	unsigned char *dest = buff;
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	if (g_exif_sz >= 0 && g_exif_sz < MAX_EXIF_SIZE)
		exif_sz = g_exif_sz;
	else
		exif_sz = default_exif_sz;
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	if (buff_sz < exif_sz || enable == 0)
		return 0;
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	dest[0] = 0xff;
	dest[1] = 0xe1;
	for (i = 2; i < exif_sz; i++) {
		dest[i] = 0xa1;
	}
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	return exif_sz;
}
static size_t jpeghead_get_data_tst(int sensor_port, void *buff, size_t buff_sz, size_t offs)
{
	int i;
	const int default_jpeghdr_sz = 623;
	int jpeghdr_sz;
	unsigned char *dest = buff;
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	if (g_jpg_hdr_sz >=0 && g_jpg_hdr_sz < JPEG_HEADER_MAXSIZE)
		jpeghdr_sz = g_jpg_hdr_sz;
	else
		jpeghdr_sz = default_jpeghdr_sz;
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	if (buff_sz < jpeghdr_sz)
		return 0;

	dest[0] = 0xff;
	dest[1] = 0xd8;
	dest[2] = 0xff;
	dest[3] = 0xe0;
	for (i = 4; i < jpeghdr_sz; i++) {
		dest[i] = 0xb2;
	}

	return jpeghdr_sz;
}
#include <linux/random.h>
static int circbuf_get_ptr_tst(int sensor_port, size_t offset, size_t len, struct fvec *vect_0, struct fvec *vect_1)
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{
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	int ret = 1;
	size_t jpg_0_sz;
	size_t jpg_1_sz;

	get_random_bytes(&jpg_0_sz, sizeof(size_t));
	get_random_bytes(&jpg_1_sz, sizeof(size_t));
	if (use_preset == 0) {
		if (jpg_0_sz != 0)
			jpg_0_sz = jpg_0_sz % (DATA_BUFF_SIZE - 1);
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		if (jpg_1_sz != 0) {
			jpg_0_sz -= (jpg_0_sz % ALIGNMENT_SIZE);
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			jpg_1_sz = jpg_1_sz % (DATA_BUFF_SIZE - 1);
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		}
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	} else if (use_preset == 1) {
		if (g_jpg_0_sz != 0)
			jpg_0_sz = jpg_0_sz % g_jpg_0_sz;
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		if (g_jpg_1_sz != 0) {
			jpg_0_sz -= (jpg_0_sz % ALIGNMENT_SIZE);
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			jpg_1_sz = jpg_1_sz % g_jpg_1_sz;
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		}
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	} else if (use_preset == 2) {
		jpg_0_sz = g_jpg_0_sz;
		jpg_1_sz = g_jpg_1_sz;
	}
	if (g_jpg_0_sz != 0)
		memset(g_jpg_data_0, 0xc3, jpg_0_sz);
	if (g_jpg_1_sz != 0)
		memset(g_jpg_data_1, 0xd4, jpg_1_sz);

	if (g_jpg_0_sz != 0) {
		vect_0->iov_base = g_jpg_data_0;
//		vect_0->iov_dma = 0;
		vect_0->iov_len = jpg_0_sz;
	} else {
		vect_0->iov_base = NULL;
		vect_0->iov_dma = 0;
		vect_0->iov_len = 0;
	}
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	if (g_jpg_1_sz != 0) {
		vect_1->iov_base = g_jpg_data_1;
//		vect_1->iov_dma = 0;
		vect_1->iov_len = jpg_1_sz;
		ret = 2;
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	} else {
521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
		vect_1->iov_base = NULL;
		vect_1->iov_dma = 0;
		vect_1->iov_len = 0;
	}

	return ret;
}
static void dump_frame(struct fvec *vects)
{
	int i;
	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
		printk(KERN_DEBUG ">>> dump data chunk %d, size %u\n", i, vects[i].iov_len);
		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, vects[i].iov_base, vects[i].iov_len);
	}
}
static int check_chunks(struct fvec *vects)
{
	int i;
	int ret = 0;
	size_t sz = 0;
	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
		if (i != CHUNK_REM) {
			sz += vects[i].iov_len;
			if ((vects[i].iov_len % ALIGNMENT_SIZE) != 0) {
				dev_err(NULL, "ERROR: unaligned write from slot %d, length %u\n", i, vects[i].iov_len);
				ret = -1;
			}
		}
	}
	if ((sz % PHY_BLOCK_SIZE) != 0) {
		dev_err(NULL, "ERROR: total length of the transaction is not aligned to sector boundary, total length %u\n", sz);
		ret = -1;
	} else {
		dev_err(NULL, ">>> +++ frame is OK +++\n");
	}
	return ret;
}
static ssize_t data_0_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	if (kstrtoul(buff, 10, &g_jpg_0_sz) != 0)
		return -EINVAL;
	printk(KERN_DEBUG ">>> preset DATA_0 length: %u\n", g_jpg_0_sz);
	return buff_sz;
}
static ssize_t data_1_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	if (kstrtoul(buff, 10, &g_jpg_1_sz) != 0)
		return -EINVAL;
	printk(KERN_DEBUG ">>> preset DATA_1 length: %u\n", g_jpg_1_sz);
	return buff_sz;
}
static ssize_t data_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	if (kstrtoul(buff, 10, &use_preset) != 0)
		return -EINVAL;

	return buff_sz;
}
static ssize_t exif_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	if (kstrtol(buff, 10, &g_exif_sz) != 0)
		return -EINVAL;
	printk(KERN_DEBUG ">>> preset EXIF length: %u\n", g_exif_sz);

	return buff_sz;
}
static ssize_t hdr_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	if (kstrtol(buff, 10, &g_jpg_hdr_sz) != 0)
		return -EINVAL;
	printk(KERN_DEBUG ">>> preset JPEGHEADER length: %u\n", g_jpg_hdr_sz);

	return buff_sz;
}
static DEVICE_ATTR(data_0_sz, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, NULL, data_0_write);
static DEVICE_ATTR(data_1_sz, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, NULL, data_1_write);
static DEVICE_ATTR(data_proc, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, NULL, data_write);
static DEVICE_ATTR(exif_sz, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, NULL, exif_write);
static DEVICE_ATTR(jpg_hdr_sz, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, NULL, hdr_write);
/* End of debug functions*/

/** Map buffer vectors to S/G list and return the number of vectors mapped */
static int map_vectors(struct elphel_ahci_priv *dpriv)
{
	int i;
	int index = 0;
	int finish = 0;
	size_t total_sz = 0;
	size_t tail;
	struct fvec *chunks = dpriv->data_chunks;
	struct fvec vect;

	for (i = dpriv->curr_data_chunk; i < MAX_DATA_CHUNKS; i++) {
		if (i == CHUNK_REM)
			/* remainder should never be processed */
			continue;
		if (i == dpriv->curr_data_chunk) {
			total_sz = chunks[i].iov_len - dpriv->curr_data_offset;
			vect.iov_base = (unsigned char *)chunks[i].iov_base + dpriv->curr_data_offset;
			vect.iov_dma = chunks[i].iov_dma + dpriv->curr_data_offset;
			vect.iov_len = chunks[i].iov_len - dpriv->curr_data_offset;
		} else {
			total_sz += chunks[i].iov_len;
//			vect.iov_base = chunks[i].iov_base;
//			vect.iov_len = chunks[i].iov_len;
			vect = chunks[i];
		}
		if (total_sz > dpriv->max_data_sz) {
			// truncate current buffer and finish mapping
			tail = total_sz - dpriv->max_data_sz;
			vect.iov_len -= tail;
			dpriv->curr_data_chunk = i;
			dpriv->curr_data_offset = chunks[i].iov_len - tail;
			finish = 1;
		} else if (unlikely(total_sz == dpriv->max_data_sz)) {
			dpriv->curr_data_chunk = i;
			dpriv->curr_data_offset = chunks[i].iov_len;
			finish = 1;
		}
		printk(KERN_DEBUG "mapping data chunk number %d: total_sz = %u, vect.iov_len = %u\n", i, total_sz, vect.iov_len);
		if (vect.iov_len != 0) {
//			sg_set_buf(&dpriv->sgl[index++], vect.iov_base, vect.iov_len);
			dpriv->sgl[index++] = vect;
		}
		if (finish)
			break;
	}
	if (finish == 0) {
		// frame vectors have been fully processed, stop calling me
		dpriv->curr_data_chunk = MAX_DATA_CHUNKS;
		dpriv->curr_data_offset = 0;
	}

	return index;
}

static inline void vectcpy(struct fvec *dest, void *src, size_t len)
{
	unsigned char *d = (unsigned char *)dest->iov_base;

	memcpy(d + dest->iov_len, src, len);
	dest->iov_len += len;
}
static inline void vectmov(struct fvec *vec, size_t len)
{
	if (vec->iov_len >= len) {
		vec->iov_base = (unsigned char *)vec->iov_base + len;
		vec->iov_dma += len;
		vec->iov_len -= len;
	}
}
static inline void vectshrink(struct fvec *vec, size_t len)
{
	if (vec->iov_len >= len) {
		vec->iov_len -= len;
	}
}
static inline size_t align_bytes_num(size_t data_len, size_t align_len)
{
	size_t rem = data_len % align_len;
	if (rem == 0)
		return 0;
	else
		return align_len - rem;
}
/** This helper function is used to position a pointer @e offset bytes from the end
 * of a buffer. DMA handle is not updated intentionally as it is not needed during copying */
static inline unsigned char *vectrpos(struct fvec *vec, size_t offset)
{
	return (unsigned char *)vec->iov_base + (vec->iov_len - offset);
}
static void align_frame(struct device *dev, struct elphel_ahci_priv *dpriv)
{
694
	int i;
695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753
	int is_delayed = 0;
	unsigned char *src;
	size_t len, total_sz, data_len;
	size_t max_len = dpriv->fbuffs.common_buff.iov_len;
	struct frame_buffers *fbuffs = &dpriv->fbuffs;
	struct fvec *chunks = dpriv->data_chunks;
	struct fvec *cbuff = &chunks[CHUNK_COMMON];

	total_sz = get_size_from(chunks, 0, 0, INCLUDE_REM);
	if (total_sz < PHY_BLOCK_SIZE) {
		/* the frame length is less than sector size, delay this frame */
		dev_dbg(dev, "frame size is less than sector size: %u bytes; delay recording\n", total_sz);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_LEADER].iov_base, chunks[CHUNK_LEADER].iov_len);
		vectshrink(&chunks[CHUNK_LEADER], chunks[CHUNK_LEADER].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_EXIF].iov_base, chunks[CHUNK_EXIF].iov_len);
		vectshrink(&chunks[CHUNK_EXIF], chunks[CHUNK_EXIF].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_HEADER].iov_base, chunks[CHUNK_HEADER].iov_len);
		vectshrink(&chunks[CHUNK_HEADER], chunks[CHUNK_HEADER].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_0].iov_base, chunks[CHUNK_DATA_0].iov_len);
		vectshrink(&chunks[CHUNK_DATA_0], chunks[CHUNK_DATA_0].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len);
		vectshrink(&chunks[CHUNK_DATA_1], chunks[CHUNK_DATA_1].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
		vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
		return;
	}

	dma_sync_single_for_cpu(dev, fbuffs->common_buff.iov_dma, fbuffs->common_buff.iov_len, DMA_TO_DEVICE);
	dma_sync_single_for_cpu(dev, chunks[CHUNK_DATA_0].iov_dma, chunks[CHUNK_DATA_0].iov_len, DMA_TO_DEVICE);
	dma_sync_single_for_cpu(dev, chunks[CHUNK_DATA_1].iov_dma, chunks[CHUNK_DATA_1].iov_len, DMA_TO_DEVICE);

	/* copy remainder of previous frame to the beginning of common buffer */
	if (likely(chunks[CHUNK_REM].iov_len != 0)) {
		len = chunks[CHUNK_REM].iov_len;
	printk(KERN_DEBUG ">>> copy %u bytes from REM to common buffer\n", len);
		vectcpy(cbuff, chunks[CHUNK_REM].iov_base, len);
		vectshrink(&chunks[CHUNK_REM], chunks[CHUNK_REM].iov_len);
	}

	/* copy JPEG marker */
	len = chunks[CHUNK_LEADER].iov_len;
	printk(KERN_DEBUG ">>> copy %u bytes from LEADER to common buffer\n", len);
	vectcpy(cbuff, chunks[CHUNK_LEADER].iov_base, len);
	vectshrink(&chunks[CHUNK_LEADER], chunks[CHUNK_LEADER].iov_len);

	/* copy Exif if present */
	if (chunks[CHUNK_EXIF].iov_len != 0) {
		len = chunks[CHUNK_EXIF].iov_len;
	printk(KERN_DEBUG ">>> copy %u bytes from EXIF to common buffer\n", len);
		vectcpy(cbuff, chunks[CHUNK_EXIF].iov_base, len);
		vectshrink(&chunks[CHUNK_EXIF], chunks[CHUNK_EXIF].iov_len);
	}

	/* copy JPEG header */
	len = chunks[CHUNK_HEADER].iov_len;
	printk(KERN_DEBUG ">>> copy %u bytes from HEADER to common buffer\n", len);
	vectcpy(cbuff, chunks[CHUNK_HEADER].iov_base, len);
	vectshrink(&chunks[CHUNK_HEADER], chunks[CHUNK_HEADER].iov_len);

754 755
	/* check if there is enough data to continue - JPEG data length can be too short */
	len = get_size_from(chunks, CHUNK_DATA_0, 0, EXCLUDE_REM);
756
	if (len < PHY_BLOCK_SIZE) {
757 758 759 760 761
		size_t num = align_bytes_num(cbuff->iov_len, PHY_BLOCK_SIZE);
		if (len >= num) {
			/* there is enough data to align common buffer to sector boundary */
			if (num >= chunks[CHUNK_DATA_0].iov_len) {
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_0 to common buffer\n", chunks[CHUNK_DATA_0].iov_len);
762
				vectcpy(cbuff, chunks[CHUNK_DATA_0].iov_base, chunks[CHUNK_DATA_0].iov_len);
763
				num -= chunks[CHUNK_DATA_0].iov_len;
764 765
				vectshrink(&chunks[CHUNK_DATA_0], chunks[CHUNK_DATA_0].iov_len);
			} else {
766 767 768 769 770
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_0 to common buffer\n", num);
				src = vectrpos(&chunks[CHUNK_DATA_0], num);
				vectcpy(cbuff, chunks[CHUNK_DATA_0].iov_base, num);
				vectshrink(&chunks[CHUNK_DATA_0], num);
				num = 0;
771
			}
772 773 774 775
			if (num >= chunks[CHUNK_DATA_1].iov_len) {
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_1 to common buffer\n", chunks[CHUNK_DATA_1].iov_len);
				vectcpy(cbuff, chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len);
				num -= chunks[CHUNK_DATA_1].iov_len;
776
				vectshrink(&chunks[CHUNK_DATA_1], chunks[CHUNK_DATA_1].iov_len);
777 778 779 780 781 782
			} else {
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_1 to common buffer\n", num);
				src = vectrpos(&chunks[CHUNK_DATA_1], num);
				vectcpy(cbuff, chunks[CHUNK_DATA_1].iov_base, num);
				vectshrink(&chunks[CHUNK_DATA_1], num);
				num = 0;
783
			}
784 785 786 787
			if (num >= chunks[CHUNK_TRAILER].iov_len) {
	printk(KERN_DEBUG ">>> copy %u bytes from TRAILER to common buffer\n", chunks[CHUNK_TRAILER].iov_len);
				vectcpy(cbuff, chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
				num -= chunks[CHUNK_TRAILER].iov_len;
788
				vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
789 790 791 792 793 794
			} else {
	printk(KERN_DEBUG ">>> copy %u bytes from TRAILER to common buffer\n", num);
				src = vectrpos(&chunks[CHUNK_TRAILER], num);
				vectcpy(cbuff, chunks[CHUNK_TRAILER].iov_base, num);
				vectshrink(&chunks[CHUNK_TRAILER], num);
				num = 0;
795
			}
796 797 798 799 800 801 802
		} else {
			/* there is not enough data to align common buffer to sector boundary, truncate common buffer */
			data_len = cbuff->iov_len % PHY_BLOCK_SIZE;
			src = vectrpos(cbuff, data_len);
	printk(KERN_DEBUG ">>> copy %u bytes from COMMON to REM buffer\n", data_len);
			vectcpy(&chunks[CHUNK_REM], src, data_len);
			vectshrink(cbuff, data_len);
803
		}
804 805 806 807 808 809 810 811 812
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_0 to REM buffer\n", chunks[CHUNK_DATA_0].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_0].iov_base, chunks[CHUNK_DATA_0].iov_len);
		vectshrink(&chunks[CHUNK_DATA_0], chunks[CHUNK_DATA_0].iov_len);
	printk(KERN_DEBUG ">>> copy %u bytes from DATA_1 to REM buffer\n", chunks[CHUNK_DATA_1].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len);
		vectshrink(&chunks[CHUNK_DATA_1], chunks[CHUNK_DATA_1].iov_len);
	printk(KERN_DEBUG ">>> copy %u bytes from TRAILER to REM buffer\n", chunks[CHUNK_TRAILER].iov_len);
		vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
		vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
813 814 815 816

		return;
	}

817
	/* align common buffer to ALIGNMENT boundary */
818
	len = align_bytes_num(cbuff->iov_len, ALIGNMENT_SIZE);
819
	if (len < JPEG_MARKER_LEN + JPEG_SIZE_LEN && len != 0) {
820 821
		/* the number of bytes needed for alignment is less than the length of the marker itself, increase the number of stuffing bytes */
		len += ALIGNMENT_SIZE;
822
	}
823 824 825
	dev_dbg(dev, "total number of stuffing bytes in APP15 marker: %u\n", len);
	app15[3] = len - JPEG_MARKER_LEN;
	vectcpy(cbuff, app15, len);
826

827
	/* align frame to sector size boundary; total size could have changed by the moment - recalculate */
828 829
	total_sz = get_size_from(chunks, 0, 0, INCLUDE_REM);
	len = total_sz % PHY_BLOCK_SIZE;
830 831 832 833 834 835 836 837 838 839
	dev_dbg(dev, "number of bytes crossing sector boundary: %u\n", len);
	if (len != 0) {
		if (len >= (chunks[CHUNK_DATA_1].iov_len + chunks[CHUNK_TRAILER].iov_len)) {
			/* current frame is not split or the second part of JPEG data is too short */
			data_len = len - chunks[CHUNK_DATA_1].iov_len - chunks[CHUNK_TRAILER].iov_len;
			src = vectrpos(&chunks[CHUNK_DATA_0], data_len);
	printk(KERN_DEBUG ">>> 5.1 copy %u bytes from DATA_0 to REM buffer\n", data_len);
			vectcpy(&chunks[CHUNK_REM], src, data_len);
			vectshrink(&chunks[CHUNK_DATA_0], data_len);
	printk(KERN_DEBUG ">>> 5.1 copy %u bytes from DATA_1 to REM buffer\n", chunks[CHUNK_DATA_1].iov_len);
840 841
			vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len);
			vectshrink(&chunks[CHUNK_DATA_1], chunks[CHUNK_DATA_1].iov_len);
842
	printk(KERN_DEBUG ">>> 5.1 copy %u bytes from TRAILER to REM buffer\n", chunks[CHUNK_TRAILER].iov_len);
843 844
			vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
			vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868
		} else if (len >= chunks[CHUNK_TRAILER].iov_len) {
			/* there is enough data in second part to align the frame */
			data_len = len - chunks[CHUNK_TRAILER].iov_len;
			src = vectrpos(&chunks[CHUNK_DATA_1], data_len);
	printk(KERN_DEBUG ">>> 5.2 copy %u bytes from DATA_1 to REM buffer\n", data_len);
			vectcpy(&chunks[CHUNK_REM], src, data_len);
			vectshrink(&chunks[CHUNK_DATA_1], data_len);
	printk(KERN_DEBUG ">>> 5.2 copy %u bytes from TRAILER to REM buffer\n", chunks[CHUNK_TRAILER].iov_len);
			vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
			vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
		} else {
			/* the trailing marker is split by sector boundary, copy (PHY_BLOCK_SIZE - 1) bytes from
			 * JPEG data block(s) to remainder buffer and then add trailing marker */
			data_len = PHY_BLOCK_SIZE - (chunks[CHUNK_TRAILER].iov_len - len);
			if (data_len >= chunks[CHUNK_DATA_1].iov_len) {
				size_t cut_len = data_len - chunks[CHUNK_DATA_1].iov_len;
				src = vectrpos(&chunks[CHUNK_DATA_0], cut_len);
	printk(KERN_DEBUG ">>> 5.3 copy %u bytes from DATA_0 to REM buffer\n", cut_len);
				vectcpy(&chunks[CHUNK_REM], src, cut_len);
				vectshrink(&chunks[CHUNK_DATA_0], cut_len);
	printk(KERN_DEBUG ">>> 5.3 copy %u bytes from DATA_1 to REM buffer\n", chunks[CHUNK_DATA_1].iov_len);
				vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len);
				vectshrink(&chunks[CHUNK_DATA_1], chunks[CHUNK_DATA_1].iov_len);
	printk(KERN_DEBUG ">>> 5.3 copy %u bytes from TRAILER to REM buffer\n", chunks[CHUNK_TRAILER].iov_len);
869 870
				vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
				vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
871
			} else {
872
				src = vectrpos(&chunks[CHUNK_DATA_1], data_len);
873 874
	printk(KERN_DEBUG ">>> 5.3 copy %u bytes from DATA_1 to REM buffer\n", data_len);
				vectcpy(&chunks[CHUNK_REM], src, data_len);
875
				vectshrink(&chunks[CHUNK_DATA_1], data_len);
876
	printk(KERN_DEBUG ">>> 5.3 copy %u bytes from TRAILER to REM buffer\n", chunks[CHUNK_TRAILER].iov_len);
877 878 879 880
				vectcpy(&chunks[CHUNK_REM], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
				vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
			}
		}
881 882 883
	} else {
		/* the frame is aligned to sector boundary but some buffers may be not */
		chunks[CHUNK_ALIGN].iov_base = vectrpos(cbuff, 0);
884
		chunks[CHUNK_ALIGN].iov_dma = cbuff->iov_dma + cbuff->iov_len;
885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901
		chunks[CHUNK_ALIGN].iov_len = 0;
		if (chunks[CHUNK_DATA_1].iov_len == 0) {
			data_len = chunks[CHUNK_DATA_0].iov_len % ALIGNMENT_SIZE;
			src = vectrpos(&chunks[CHUNK_DATA_0], data_len);
	printk(KERN_DEBUG ">>> 5.4 copy %u bytes from DATA_0 to ALIGN buffer\n", data_len);
			vectcpy(&chunks[CHUNK_ALIGN], src, data_len);
			vectshrink(&chunks[CHUNK_DATA_0], data_len);
		} else {
			data_len = chunks[CHUNK_DATA_1].iov_len % ALIGNMENT_SIZE;
			src = vectrpos(&chunks[CHUNK_DATA_1], data_len);
	printk(KERN_DEBUG ">>> 5.4 copy %u bytes from DATA_1 to ALIGN buffer\n", data_len);
			vectcpy(&chunks[CHUNK_ALIGN], src, data_len);
			vectshrink(&chunks[CHUNK_DATA_1], data_len);
		}
	printk(KERN_DEBUG ">>> 5.4 copy %u bytes from TRAILER to ALIGN buffer\n", chunks[CHUNK_TRAILER].iov_len);
		vectcpy(&chunks[CHUNK_ALIGN], chunks[CHUNK_TRAILER].iov_base, chunks[CHUNK_TRAILER].iov_len);
		vectshrink(&chunks[CHUNK_TRAILER], chunks[CHUNK_TRAILER].iov_len);
902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940
	}

	/* debug sanity check, should not happen */
	if (cbuff->iov_len >= max_len) {
		dev_err(NULL, "ERROR: the number of bytes copied to common buffer exceeds its size\n");
	}
}

/** TEST FUNCTION: stuff frame data to align the frame to disk block boundary */
//static void stuff_frame(struct fvec *vects)
//{
//	int i;
//	size_t total = 0;
//	size_t stuffing = 0;
//
//	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
//		total += vects[i].iov_len;
//	}
//
//	stuffing = PHY_BLOCK_SIZE - total % PHY_BLOCK_SIZE;
//
//	printk(KERN_DEBUG "%s: total = %u, stuffing = %u\n", __func__, total, stuffing);
//	if (stuffing == PHY_BLOCK_SIZE)
//		return;
//
//	if (stuffing < 3) {
//		// the number of stuffing bytes is less then marker plus one byte, add one more sector
//		stuffing += PHY_BLOCK_SIZE;
//	}
//	vects[CHUNK_STUFFING].iov_len = stuffing;
//}

static void dump_sg_list(const struct fvec *sgl, size_t elems)
{
	int i;

	printk(KERN_DEBUG "dump S/G list, %u elements:\n", elems);
	for (i = 0; i < elems; i++) {
		printk(KERN_DEBUG "dma address: 0x%x, len: %u\n", sgl[i].iov_dma, sgl[i].iov_len);
941
	}
942 943
	printk(KERN_DEBUG "===== end of S/G list =====\n");
}
944

945 946 947 948 949
/** Calculate the number of blocks this frame will occupy. The frame must be aligned to block size */
static inline size_t get_blocks_num(struct fvec *sgl, size_t n_elem)
{
	int num;
	size_t total = 0;
950

951 952
	for (num = 0; num < n_elem; num++) {
		total += sgl[num].iov_len;
953 954
	}

955 956
	return total / PHY_BLOCK_SIZE;
}
957

958 959 960 961 962
/** Calculate the size of current frame in bytes starting from vector and offset given */
static inline size_t get_size_from(const struct fvec *vects, int index, size_t offset, int all)
{
	int i;
	size_t total = 0;
963

964 965 966 967
	if (index >= MAX_DATA_CHUNKS || offset > vects[index].iov_len) {
		dev_dbg(NULL, "nothing to process, index or offset is out of vector range: vector %d, offset %u\n", index, offset);
		return 0;
	}
968

969 970 971 972 973 974 975 976
	for (i = index; i < MAX_DATA_CHUNKS; i++) {
		if (i == CHUNK_REM && all == EXCLUDE_REM)
			/* remainder should not be processed */
			continue;
		if (i == index)
			total += vects[i].iov_len - offset;
		else
			total += vects[i].iov_len;
977 978
	}

979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039
	return total;
}

/** Set vectors pointing to data buffers except for JPEG data - those are set in circbuf driver */
static void init_vectors(struct elphel_ahci_priv *dpriv)
{
	struct frame_buffers *buffs = &dpriv->fbuffs;
	struct fvec *chunks = dpriv->data_chunks;

	chunks[CHUNK_EXIF].iov_base = buffs->exif_buff.iov_base;
	chunks[CHUNK_EXIF].iov_len = 0;

	chunks[CHUNK_LEADER].iov_base = buffs->jpheader_buff.iov_base;
	chunks[CHUNK_LEADER].iov_len = JPEG_MARKER_LEN;
	chunks[CHUNK_HEADER].iov_base = (unsigned char *)chunks[CHUNK_LEADER].iov_base + chunks[CHUNK_LEADER].iov_len;
	chunks[CHUNK_HEADER].iov_len = 0;

	chunks[CHUNK_TRAILER].iov_base = buffs->trailer_buff.iov_base;
	chunks[CHUNK_TRAILER].iov_len = JPEG_MARKER_LEN;

	chunks[CHUNK_REM].iov_base = buffs->rem_buff.iov_base;
	chunks[CHUNK_REM].iov_len = 0;

	/* this is the only DMA mapped buffer and its DMA address should be set */
	chunks[CHUNK_COMMON].iov_base = buffs->common_buff.iov_base;
	chunks[CHUNK_COMMON].iov_dma = buffs->common_buff.iov_dma;
	chunks[CHUNK_COMMON].iov_len = 0;
}

static int init_buffers(struct device *dev, struct frame_buffers *buffs)
{
	int mult;
	int total_sz;
	unsigned char *ptr;

	buffs->exif_buff.iov_base = kmalloc(MAX_EXIF_SIZE, GFP_KERNEL);
	if (!buffs->exif_buff.iov_base)
		return -ENOMEM;
	buffs->exif_buff.iov_len = MAX_EXIF_SIZE;

	buffs->jpheader_buff.iov_base = kmalloc(JPEG_HEADER_MAXSIZE, GFP_KERNEL);
	if (!buffs->jpheader_buff.iov_base)
		goto err_header;
	buffs->jpheader_buff.iov_len = JPEG_HEADER_MAXSIZE;

	buffs->trailer_buff.iov_base = kmalloc(JPEG_MARKER_LEN, GFP_KERNEL);
	if (!buffs->trailer_buff.iov_base)
		goto err_trailer;
	buffs->trailer_buff.iov_len = JPEG_MARKER_LEN;
	ptr = buffs->trailer_buff.iov_base;
	ptr[0] = 0xff;
	ptr[1] = 0xd9;

	/* 3 * ALIGMENT_SIZE here means 2 buffers for JPEG data alignment plus one buffer for
	 * DATA_0 address alignment - this one is padded with APP15 marker */
	total_sz = MAX_EXIF_SIZE + JPEG_HEADER_MAXSIZE + 4 * ALIGNMENT_SIZE + PHY_BLOCK_SIZE;
	if (total_sz > PAGE_SIZE) {
		mult = total_sz / PAGE_SIZE + 1;
		total_sz = mult * PAGE_SIZE;
	} else {
		total_sz = PAGE_SIZE;
1040
	}
1041 1042 1043 1044 1045 1046 1047 1048 1049
	buffs->common_buff.iov_base = kmalloc(total_sz, GFP_KERNEL);
	if (!buffs->common_buff.iov_base)
		goto err_common;
	buffs->common_buff.iov_len = total_sz;
	/* this is the only buffer which needs DMA mapping as all other data will be collected in it */
	buffs->common_buff.iov_dma = dma_map_single(dev, buffs->common_buff.iov_base, buffs->common_buff.iov_len, DMA_TO_DEVICE);
	if (dma_mapping_error(dev, buffs->common_buff.iov_dma))
		goto err_common_dma;

1050
	buffs->rem_buff.iov_base = kmalloc(2 * PHY_BLOCK_SIZE, GFP_KERNEL);
1051 1052
	if (!buffs->rem_buff.iov_base)
		goto err_remainder;
1053
	buffs->rem_buff.iov_len = 2 * PHY_BLOCK_SIZE;
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085

	/* debug code follows */
	g_jpg_data_0 = kzalloc(DATA_BUFF_SIZE, GFP_KERNEL);
	g_jpg_data_1 = kzalloc(DATA_BUFF_SIZE, GFP_KERNEL);
	if (!g_jpg_data_0 || !g_jpg_data_1)
		return -ENOMEM;
	/* end of debug code */

	return 0;

err_remainder:
	dma_unmap_single(dev, buffs->common_buff.iov_dma, buffs->common_buff.iov_len, DMA_TO_DEVICE);
err_common_dma:
	kfree(buffs->common_buff.iov_base);
err_common:
	kfree(buffs->trailer_buff.iov_base);
err_trailer:
	kfree(buffs->jpheader_buff.iov_base);
err_header:
	kfree(buffs->exif_buff.iov_base);
	return -ENOMEM;
}

static void deinit_buffers(struct device *dev, struct frame_buffers *buffs)
{
	kfree(buffs->jpheader_buff.iov_base);
	kfree(buffs->exif_buff.iov_base);
	kfree(buffs->trailer_buff.iov_base);
	dma_unmap_single(dev, buffs->common_buff.iov_dma, buffs->common_buff.iov_len, DMA_TO_DEVICE);
	kfree(buffs->common_buff.iov_base);
	kfree(buffs->rem_buff.iov_base);
}
1086

1087 1088 1089
static inline void reset_chunks(struct fvec *vects, int all)
{
	int i;
1090

1091 1092 1093 1094 1095 1096
	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
		if (i != CHUNK_REM)
			vects[i].iov_len = 0;
	}
	if (all) {
		vects[CHUNK_REM].iov_len = 0;
1097
	}
1098
}
1099

1100 1101 1102 1103 1104 1105 1106 1107
static inline struct elphel_ahci_priv *dev_get_dpriv(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;

	return dpriv;
}
1108

1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
//static void start_cmd(struct device *dev, struct elphel_ahci_priv *dpriv, struct ata_port *port)
//{
//	int num;
//	size_t max_sz = (MAX_LBA_COUNT + 1) * PHY_BLOCK_SIZE;
//	size_t total_sz = get_total_size(dpriv->data_chunks);
//
//	if ((dpriv->lba_ptr.lba_write & ~ADDR_MASK_28_BIT) || total_sz > max_sz) {
////	if (dpriv->lba_ptr.lba_write & ~ADDR_MASK_28_BIT) {
//		dpriv->curr_cmd = ATA_CMD_WRITE_EXT;
//		dpriv->max_data_sz = (MAX_LBA_COUNT_EXT + 1) * PHY_BLOCK_SIZE;
//	} else {
//		dpriv->curr_cmd = ATA_CMD_WRITE;
//		dpriv->max_data_sz = (MAX_LBA_COUNT + 1) * PHY_BLOCK_SIZE;
//	}
//	dpriv->flags |= PROC_CMD;
//	dpriv->sg_elems = map_vectors(dpriv);
//
//	num = dma_map_sg(dev, dpriv->sgl, dpriv->sg_elems, DMA_TO_DEVICE);
//	printk(KERN_DEBUG ">>> %d entries dma mapped\n", num);
//	dump_sg_list(dpriv->sgl, dpriv->sg_elems);
//
//	dpriv->lba_ptr.wr_count = get_blocks_num(dpriv->sgl, dpriv->sg_elems);
//	printk(KERN_DEBUG ">>> trying to write data from sg list %u blocks, LBA: %llu\n", dpriv->lba_ptr.wr_count, dpriv->lba_ptr.lba_write);
//	elphel_cmd_issue(port, dpriv->lba_ptr.lba_write, dpriv->lba_ptr.wr_count, dpriv->sgl, dpriv->sg_elems, dpriv->curr_cmd);
//}

/** Process command and return the number of S/G entries mapped */
static int process_cmd(struct device *dev, struct elphel_ahci_priv *dpriv, struct ata_port *port)
{
	int num;
1139
	struct fvec *cbuff = &dpriv->fbuffs.common_buff;
1140 1141 1142 1143 1144 1145 1146 1147 1148 1149
	size_t max_sz = (MAX_LBA_COUNT + 1) * PHY_BLOCK_SIZE;
	size_t rem_sz = get_size_from(dpriv->data_chunks, dpriv->curr_data_chunk, dpriv->curr_data_offset, EXCLUDE_REM);

	/* define ATA command to use for current transaction */
	if ((dpriv->lba_ptr.lba_write & ~ADDR_MASK_28_BIT) || rem_sz > max_sz) {
		dpriv->curr_cmd = ATA_CMD_WRITE_EXT;
		dpriv->max_data_sz = (MAX_LBA_COUNT_EXT + 1) * PHY_BLOCK_SIZE;
	} else {
		dpriv->curr_cmd = ATA_CMD_WRITE;
		dpriv->max_data_sz = (MAX_LBA_COUNT + 1) * PHY_BLOCK_SIZE;
1150 1151
	}

1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166
	if (dpriv->flags & PROC_CMD)
		dpriv->lba_ptr.lba_write += dpriv->lba_ptr.wr_count;
	dpriv->flags |= PROC_CMD;
	dpriv->sg_elems = map_vectors(dpriv);
	if (dpriv->sg_elems != 0) {
		dump_sg_list(dpriv->sgl, dpriv->sg_elems);

		dpriv->lba_ptr.wr_count = get_blocks_num(dpriv->sgl, dpriv->sg_elems);
		printk(KERN_DEBUG ">>> trying to write data from sg list %u blocks, LBA: %llu\n", dpriv->lba_ptr.wr_count, dpriv->lba_ptr.lba_write);
		dma_sync_single_for_device(dev, cbuff->iov_dma, cbuff->iov_len, DMA_TO_DEVICE);
		if (dpriv->data_chunks[CHUNK_DATA_0].iov_len != 0)
			dma_sync_single_for_device(dev, dpriv->data_chunks[CHUNK_DATA_0].iov_dma, dpriv->data_chunks[CHUNK_DATA_0].iov_len, DMA_TO_DEVICE);
		if (dpriv->data_chunks[CHUNK_DATA_1].iov_len != 0)
			dma_sync_single_for_device(dev, dpriv->data_chunks[CHUNK_DATA_1].iov_dma, dpriv->data_chunks[CHUNK_DATA_1].iov_len, DMA_TO_DEVICE);
		elphel_cmd_issue(port, dpriv->lba_ptr.lba_write, dpriv->lba_ptr.wr_count, dpriv->sgl, dpriv->sg_elems, dpriv->curr_cmd);
1167
	}
1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195

	return dpriv->sg_elems;
}

static void finish_cmd(struct device *dev, struct elphel_ahci_priv *dpriv)
{
	int all;

	dpriv->lba_ptr.wr_count = 0;
	if ((dpriv->flags & LAST_BLOCK) == 0) {
		all = 0;
	} else {
		all = 1;
		dpriv->flags &= ~LAST_BLOCK;
	}
	reset_chunks(dpriv->data_chunks, all);
	dpriv->flags &= ~PROC_CMD;
	dpriv->curr_cmd = 0;
	dpriv->max_data_sz = 0;
	dpriv->curr_data_chunk = 0;
	dpriv->curr_data_offset = 0;
}

/** Fill free space in REM buffer with 0 and save the reaming data chunk */
static void finish_rec(struct device *dev, struct elphel_ahci_priv *dpriv, struct ata_port *port)
{
	size_t stuff_len;
	struct fvec *src;
1196 1197
	struct fvec *cvect = &dpriv->data_chunks[CHUNK_COMMON];
	struct fvec *rvect = &dpriv->data_chunks[CHUNK_REM];
1198

1199
	if (rvect->iov_len == 0)
1200 1201
		return;

1202 1203 1204
	dev_dbg(dev, "write last chunk of data, size: %u\n", rvect->iov_len);
	stuff_len = PHY_BLOCK_SIZE - rvect->iov_len;
	src = vectrpos(rvect, stuff_len);
1205
	memset(src->iov_base, 0, stuff_len);
1206 1207 1208
	rvect->iov_len += stuff_len;
	vectcpy(cvect, rvect->iov_base, rvect->iov_len);
	vectshrink(rvect, rvect->iov_len);
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241

	dpriv->flags |= LAST_BLOCK;
	process_cmd(dev, dpriv, port);
}

static ssize_t rawdev_write(struct device *dev,  ///<
		struct device_attribute *attr,           ///<
		const char *buff,                        ///<
		size_t buff_sz)                          ///<
{
	int i, n_elem;
	int sg_elems = 0;
	struct ata_host *host = dev_get_drvdata(dev);
	struct ata_port *port = host->ports[DEFAULT_PORT_NUM];
	struct elphel_ahci_priv *dpriv = dev_get_dpriv(dev);
	struct scatterlist *sgl;
	struct scatterlist *sg_ptr;
//	u8 *test_buff = pElphel_buf->d2h_vaddr;
	u8 *test_buff;
	uint8_t *buffers[SG_TBL_SZ] = {0};
	uint64_t lba_addr;
	struct frame_data fdata;
	size_t rcvd = 0;
	struct frame_buffers *buffs = &dpriv->fbuffs;
	struct fvec *chunks = dpriv->data_chunks;
	size_t blocks_num;
	static int dont_process = 0;

	if ((dpriv->flags & PROC_CMD) || dont_process)
		// we are not ready yet
		return -EAGAIN;

	if (buff_sz != sizeof(struct frame_data)) {
1242
		dev_err(dev, "the size of the data buffer is incorrect, should be equal to sizeof(struct frame_data)\n");
1243 1244 1245
		return -EINVAL;
	}
	memcpy(&fdata, buff, sizeof(struct frame_data));
1246 1247 1248 1249
	if (fdata.cmd == DRV_CMD_FINISH) {
		finish_rec(dev, dpriv, port);
		return buff_sz;
	}
1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484

	/* debug code follows */
	printk(KERN_DEBUG ">>> data pointers received:\n");
	printk(KERN_DEBUG ">>> sensor port: %u\n", fdata.sensor_port);
	printk(KERN_DEBUG ">>> cirbuf ptr: %d, cirbuf data len: %d\n", fdata.cirbuf_ptr, fdata.jpeg_len);
	printk(KERN_DEBUG ">>> meta_index: %d\n", fdata.meta_index);
	printk(KERN_DEBUG "\n");

//	rcvd = exif_get_data(fdata.sensor_port, fdata.meta_index, buffs->exif_buff.iov_base, buffs->exif_buff.iov_len);
	rcvd = exif_get_data_tst(fdata.sensor_port, fdata.meta_index, buffs->exif_buff.iov_base, buffs->exif_buff.iov_len, 1);
	printk(KERN_DEBUG ">>> bytes received from exif driver: %u\n", rcvd);
	if (rcvd > 0 && rcvd < buffs->exif_buff.iov_len)
//		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buffs->exif_buff.iov_base, rcvd);
	chunks[CHUNK_EXIF].iov_len = rcvd;

//	rcvd = jpeghead_get_data(fdata.sensor_port, buffs->jpheader_buff.iov_base, buffs->jpheader_buff.iov_len, 0);
	rcvd = jpeghead_get_data_tst(fdata.sensor_port, buffs->jpheader_buff.iov_base, buffs->jpheader_buff.iov_len, 0);
	printk(KERN_DEBUG ">>> bytes received from jpeghead driver: %u\n", rcvd);
	if (rcvd > 0 && rcvd < buffs->jpheader_buff.iov_len) {
//		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buffs->jpheader_buff.iov_base, rcvd);
		chunks[CHUNK_LEADER].iov_len = JPEG_MARKER_LEN;
		chunks[CHUNK_TRAILER].iov_len = JPEG_MARKER_LEN;
		chunks[CHUNK_HEADER].iov_len = rcvd - chunks[CHUNK_LEADER].iov_len;
	} else {
		// we don't want these buffers for test purposes
		chunks[CHUNK_LEADER].iov_len = 0;
		chunks[CHUNK_TRAILER].iov_len = 0;
		chunks[CHUNK_HEADER].iov_len = 0;
	}

	rcvd = 0;
//	rcvd = circbuf_get_ptr(fdata.sensor_port, fdata.cirbuf_ptr, fdata.jpeg_len, &chunks[CHUNK_DATA_0], &chunks[CHUNK_DATA_1]);
	rcvd = circbuf_get_ptr_tst(fdata.sensor_port, fdata.cirbuf_ptr, fdata.jpeg_len, &chunks[CHUNK_DATA_0], &chunks[CHUNK_DATA_1]);
	if (rcvd > 0) {
		printk(KERN_DEBUG ">>> number of jpeg data pointers: %d\n", rcvd);
		printk(KERN_DEBUG ">>> bytes received from circbuf driver, chunk 0: %u\n", chunks[CHUNK_DATA_0].iov_len);
		if (rcvd == 2)
			printk(KERN_DEBUG ">>> bytes received from circbuf driver, chunk 1: %u\n", chunks[CHUNK_DATA_1].iov_len);
	}
	if (chunks[CHUNK_DATA_0].iov_len != 0)
		chunks[CHUNK_DATA_0].iov_dma = dma_map_single(dev, chunks[CHUNK_DATA_0].iov_base, chunks[CHUNK_DATA_0].iov_len, DMA_TO_DEVICE);
	if (chunks[CHUNK_DATA_1].iov_len != 0)
		chunks[CHUNK_DATA_1].iov_dma = dma_map_single(dev, chunks[CHUNK_DATA_1].iov_base, chunks[CHUNK_DATA_1].iov_len, DMA_TO_DEVICE);

	printk(KERN_DEBUG ">>> unaligned frame dump:\n");
	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
		printk(KERN_DEBUG ">>>\tslot: %i; len: %u\n", i, dpriv->data_chunks[i].iov_len);
	}
	align_frame(dev, dpriv);
	printk(KERN_DEBUG ">>> aligned frame dump:\n");
	for (i = 0; i < MAX_DATA_CHUNKS; i++) {
		printk(KERN_DEBUG ">>>\tslot: %i; len: %u\n", i, dpriv->data_chunks[i].iov_len);
	}
	if (check_chunks(dpriv->data_chunks) != 0) {
		dont_process = 1;
		return -EINVAL;
	}

	process_cmd(dev, dpriv, port);
	while (dpriv->flags & PROC_CMD) {
#ifndef DEBUG_DONT_WRITE
		while (dpriv->flags & IRQ_SIMPLE) {
			printk_once(KERN_DEBUG ">>> waiting for interrupt\n");
			msleep_interruptible(1);
		}
#endif
		printk(KERN_DEBUG ">>> proceeding to next cmd chunk\n");
		sg_elems = process_cmd(dev, dpriv, port);
		if (sg_elems == 0)
			finish_cmd(dev, dpriv);
	}
	if (chunks[CHUNK_DATA_0].iov_len != 0)
		dma_unmap_single(dev, chunks[CHUNK_DATA_0].iov_dma, chunks[CHUNK_DATA_0].iov_len, DMA_TO_DEVICE);
	if (chunks[CHUNK_DATA_1].iov_len != 0)
		dma_unmap_single(dev, chunks[CHUNK_DATA_1].iov_dma, chunks[CHUNK_DATA_1].iov_len, DMA_TO_DEVICE);

//	chunks[CHUNK_STUFFING].iov_base = buffs->stuff_buff.iov_base;
//	stuff_frame(chunks);
//
//	/* copy data to common buffer */
//	struct fvec vec = {0};
//	vec.iov_base = buffs->common_buff.iov_base;
//	memcpy(vec.iov_base, chunks[CHUNK_LEADER].iov_base, chunks[CHUNK_LEADER].iov_len);
//	vec.iov_len += chunks[CHUNK_LEADER].iov_len;
//	chunks[CHUNK_LEADER].iov_len = 0;
//
//	memcpy(vec.iov_base + vec.iov_len, chunks[CHUNK_EXIF].iov_base, chunks[CHUNK_EXIF].iov_len);
//	vec.iov_len += chunks[CHUNK_EXIF].iov_len;
//	chunks[CHUNK_EXIF].iov_len = 0;
//
//	memcpy(vec.iov_base + vec.iov_len, chunks[CHUNK_HEADER].iov_base, chunks[CHUNK_HEADER].iov_len);
//	vec.iov_len += chunks[CHUNK_HEADER].iov_len;
//	chunks[CHUNK_HEADER].iov_len = 0;
//
//	memcpy(vec.iov_base + vec.iov_len, chunks[CHUNK_STUFFING].iov_base, chunks[CHUNK_STUFFING].iov_len);
//	vec.iov_len += chunks[CHUNK_STUFFING].iov_len;
//	chunks[CHUNK_STUFFING].iov_len = 0;
//
//	chunks[CHUNK_HEADER] = vec;

	/* end of debug code */

//	start_cmd(dev, dpriv, port);
//	while (dpriv->flags & PROC_CMD) {
//		while (dpriv->flags & IRQ_SIMPLE) {
//			printk_once(KERN_DEBUG ">>> waiting for interrupt\n");
//			msleep_interruptible(1);
//		}
//		printk(KERN_DEBUG ">>> proceeding to next cmd chunk\n");
////		if (proc_cmd(dev, dpriv, port) == 0)
//			finish_cmd(dev, dpriv);
//	}



//	/* prepare buffer and fill it with markers */
//	sgl = kmalloc(sizeof(struct scatterlist) * SG_TBL_SZ, GFP_KERNEL);
//	if (!sgl)
//		return ENOMEM;
//	sg_init_table(sgl, SG_TBL_SZ);
//	for_each_sg(sgl, sg_ptr, SG_TBL_SZ, n_elem) {
//		test_buff = kmalloc(TEST_BUFF_SZ, GFP_KERNEL);
//		if (!test_buff)
//			return ENOMEM;
//		buffers[n_elem] = test_buff;
//		memset(test_buff, 0xa5, TEST_BUFF_SZ);
//		sg_set_buf(sg_ptr, (void *)test_buff, TEST_BUFF_SZ);
//		sg_elems++;
//	}
//
//	printk(KERN_DEBUG ">>> mapped %d SG elemets\n", sg_elems);
//	printk(KERN_DEBUG ">>>\n");
//
//	/* write test #2 */
//	if (dpriv->lba_ptr.lba_write & ~ADDR_MASK_28_BIT) {
//		dpriv->curr_cmd = ATA_CMD_WRITE_EXT;
//		dpriv->max_data_sz = (0xffff + 1) * PHY_BLOCK_SIZE;
//	} else {
//		dpriv->curr_cmd = ATA_CMD_WRITE;
//		dpriv->max_data_sz = (0xff + 1) * PHY_BLOCK_SIZE;
//	}
//	dpriv->flags |= PROC_CMD;
//	blocks_num = get_blocks_num(sgl, sg_elems);
//	i = dma_map_sg(dev, sgl, sg_elems, DMA_TO_DEVICE);
//	printk(KERN_DEBUG ">>> dma mapped %d elements\n", i);
//	printk(KERN_DEBUG ">>> trying to write data from sg list, %u blocks, LBA: %llu\n", blocks_num, dpriv->lba_ptr.lba_write);
//	elphel_cmd_issue(port, dpriv->lba_ptr.lba_write, blocks_num, sgl, sg_elems, dpriv->curr_cmd);
//
//	while (dpriv->flags & IRQ_SIMPLE) {
//		printk_once(KERN_DEBUG ">>> waiting for interrupt\n");
//		msleep_interruptible(1);
//	}
//	dma_unmap_sg(dev, sgl, sg_elems, DMA_TO_DEVICE);
//	dpriv->lba_ptr.lba_write += blocks_num;
//	dpriv->flags &= ~PROC_CMD;
//	/* end of write test #2 */
//
//	for (i = 0; i < sg_elems; i++) {
//		kfree(buffers[i]);
//	}
//	kfree(sgl);


//
//	/* read test */
//	dma_map_sg(dev, sgl, sg_elems, DMA_FROM_DEVICE);
//
//	printk(KERN_DEBUG ">>> trying to read data to sg list\n");
//	if (lba_addr & ~ADDR_MASK_28_BIT)
//		cmd = ATA_CMD_READ_EXT;
//	else
//		cmd = ATA_CMD_READ;
//	elphel_cmd_issue(port, lba_addr, sg_elems, sgl, sg_elems, cmd);
//	printk(KERN_DEBUG ">>> command has been issued\n");
//
//	while (dpriv->flags & IRQ_SIMPLE) {
//		printk_once(KERN_DEBUG ">>> waiting for interrupt\n");
//		msleep(1);
//	}
//
//	printk(KERN_DEBUG ">>> dump test buffer after reading: %d bytes\n", TEST_BUFF_SZ);
//	dma_unmap_sg(dev, sgl, sg_elems, DMA_FROM_DEVICE);
//	for (i = 0; i < sg_elems; i++) {
//		dev_dbg(dev, ">>> sector %i\n", i);
//		u8 buff[TEST_BUFF_SZ];
//		sg_copy_to_buffer(&sgl[i], 1, buff, TEST_BUFF_SZ);
//		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buff, TEST_BUFF_SZ);
//	}
//	/* end of read test */
//
//	printk(KERN_DEBUG ">>> *** proceeding to write test *** <<<\n");
//
//	/* write test */
//	for_each_sg(sgl, sg_ptr, SG_TBL_SZ, n_elem) {
//		uint8_t pattern_buff[TEST_BUFF_SZ];
//		memset(pattern_buff, 0xb6, TEST_BUFF_SZ);
//		sg_copy_from_buffer(sg_ptr, 1, pattern_buff, TEST_BUFF_SZ);
//	}

//	if (lba_addr & ~ADDR_MASK_28_BIT) {
//		dpriv->curr_cmd = ATA_CMD_WRITE_EXT;
//		dpriv->max_data_sz = (0xffff + 1) * PHY_BLOCK_SIZE;
//	} else {
//		dpriv->curr_cmd = ATA_CMD_WRITE;
//		dpriv->max_data_sz = (0xff + 1) * PHY_BLOCK_SIZE;
//	}
//	sg_elems = map_vectors(sgl, dpriv, dpriv->max_data_sz);
//	dump_sg_list(sgl, sg_elems);
//	while (sg_elems != 0) {
//		dma_map_sg(dev, sgl, sg_elems, DMA_TO_DEVICE);
//		lba_addr = dpriv->lba_ptr.lba_write;
//		blocks_num = get_blocks_num(sgl, sg_elems);
//		printk(KERN_DEBUG ">>> trying to write data from sg list %u blocks, LBA: %llu\n", blocks_num, lba_addr);
//		elphel_cmd_issue(port, lba_addr, blocks_num, sgl, sg_elems, cmd);
//		printk(KERN_DEBUG ">>> command has been issued, wrting %u LBAs\n", blocks_num);
//
//		while (dpriv->flags & IRQ_SIMPLE) {
//			printk_once(KERN_DEBUG ">>> waiting for interrupt\n");
//			msleep(1);
//		}
//		dma_unmap_sg(dev, sgl, sg_elems, DMA_TO_DEVICE);
//		dpriv->lba_ptr.lba_write += blocks_num;
//
//		sg_elems = map_vectors(sgl, dpriv, dpriv->max_data_sz);
//		dump_sg_list(sgl, sg_elems);
//	}
//	finish_cmd(dpriv);

//	printk(KERN_DEBUG ">>> dump test buffer after writing: %d bytes\n", TEST_BUFF_SZ);
//	for (i = 0; i < sg_elems; i++) {
//		dev_dbg(dev, ">>> sector %i\n", i);
//		u8 buff[TEST_BUFF_SZ];
//		sg_copy_to_buffer(&sgl[i], 1, buff, TEST_BUFF_SZ);
//		print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buff, TEST_BUFF_SZ);
//	}
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	/* end of write test */
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	return buff_sz;
}

/** Prepare software constructed command FIS in command table area. The structure of the
 * command FIS is described in Transport Layer chapter of Serial ATA revision 3.1 documentation.
 */
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static inline void prep_cfis(uint8_t *cmd_tbl,   ///< pointer to the beginning of command table
		uint8_t cmd,                             ///< ATA command as described in ATA/ATAPI command set
		uint64_t start_addr,                     ///< LBA start address
		uint16_t count)                          ///< sector count, the number of 512 byte sectors to read or write
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		                                         ///< @return None
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{
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	uint8_t device, ctrl;
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	/* select the content of Device and Control registers based on command, read the description of
	 * a command in ATA/ATAPI command set documentation
	 */
	switch (cmd) {
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	case ATA_CMD_WRITE:
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	case ATA_CMD_READ:
		device = 0xe0 | ((start_addr >> 24) & 0x0f);
		ctrl = 0x08;
		/* this is 28-bit command; 4 bits of the address have already been
		 * placed to Device register, invalidate the remaining (if any) upper
		 * bits of the address and leave only 24 significant bits (just in case)
		 */
		start_addr &= 0xffffff;
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		count &= 0xff;
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		break;
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	case ATA_CMD_WRITE_EXT:
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	case ATA_CMD_READ_EXT:
		device = 0xe0;
		ctrl = 0x08;
		break;
	default:
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		device = 0xe0;
		ctrl = 0x08;
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	}

	cmd_tbl[0] = 0x27;                       // H2D register FIS
	cmd_tbl[1] = 0x80;                       // set C = 1
	cmd_tbl[2] = cmd;                        // ATA READ or WRITE DMA command as described in ATA/ATAPI command set
	cmd_tbl[3] = 0;                          // features(7:0)
	cmd_tbl[4] = start_addr & 0xff;          // LBA(7:0)
	cmd_tbl[5] = (start_addr >> 8)  & 0xff;  // LBA(15:8)
	cmd_tbl[6] = (start_addr >> 16) & 0xff;  // LBA(23:16)
	cmd_tbl[7] = device;                     // device
	cmd_tbl[8] = (start_addr >> 24)  & 0xff; // LBA(31:24)
	cmd_tbl[9] = (start_addr >> 32)  & 0xff; // LBA(39:32)
	cmd_tbl[10] = (start_addr >> 40) & 0xff; // LBA(47:40)
	cmd_tbl[11] = 0;                         // features(15:8)
	cmd_tbl[12] = count & 0xff;              // count(7:0)
	cmd_tbl[13] = (count >> 8) & 0xff;       // count(15:8)
	cmd_tbl[14] = 0;                         // ICC (isochronous command completion)
	cmd_tbl[15] = ctrl;                      // control
}

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/** Map S/G list to physical region descriptor table in AHCI controller command table */
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static inline void prep_prdt(struct fvec *sgl,   ///< pointer to S/G list which should be mapped to physical
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		                                         ///< region description table
		unsigned int n_elem,                     ///< the number of elements in @e sgl
		struct ahci_sg *ahci_sgl)                ///< pointer to physical region description table
		                                         ///< @return None
{
	unsigned int num = 0;

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	for (num = 0; num < n_elem; num++) {
		ahci_sgl[num].addr = cpu_to_le32(sgl[num].iov_dma & 0xffffffff);
		ahci_sgl[num].addr_hi = cpu_to_le32((sgl[num].iov_dma >> 16) >> 16);
		ahci_sgl[num].flags_size = cpu_to_le32(sgl[num].iov_len - 1);
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	}
}

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/** Prepare and issue read or write command */
static void elphel_cmd_issue(struct ata_port *ap,///< device port for which the command should be issued
		uint64_t start,                          ///< LBA start address
		uint16_t count,                          ///< the number of sectors to read or write
		struct fvec *sgl,                 ///< S/G list pointing to data buffers
		unsigned int elem,                       ///< the number of elements in @e sgl
		uint8_t cmd)                             ///< the command to be issued; should be ATA_CMD_READ, ATA_CMD_READ_EXT,
		                                         ///< ATA_CMD_WRITE or ATA_CMD_WRITE_EXT, other commands are not tested
		                                         ///< @return None
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{
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	uint32_t opts;
	uint8_t *cmd_tbl;
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	unsigned int slot_num = 0;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;
	struct ahci_sg *ahci_sg;
	void __iomem *port_mmio = ahci_port_base(ap);

	dpriv->flags |= IRQ_SIMPLE;

	/* prepare command FIS */
	dma_sync_single_for_cpu(ap->dev, pp->cmd_tbl_dma, AHCI_CMD_TBL_AR_SZ, DMA_TO_DEVICE);
	cmd_tbl = pp->cmd_tbl + slot_num * AHCI_CMD_TBL_SZ;
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	prep_cfis(cmd_tbl, cmd, start, count);
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	/* prepare physical region descriptor table */
	ahci_sg = pp->cmd_tbl + slot_num * AHCI_CMD_TBL_SZ + AHCI_CMD_TBL_HDR_SZ;
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	prep_prdt(sgl, elem, ahci_sg);
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	/* prepare command header */
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	opts = CMD_FIS_LEN | (elem << 16) | AHCI_CMD_PREFETCH | AHCI_CMD_CLR_BUSY;
	if (cmd == ATA_CMD_WRITE || cmd == ATA_CMD_WRITE_EXT)
		opts |= AHCI_CMD_WRITE;
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	ahci_fill_cmd_slot(pp, slot_num, opts);
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	dev_dbg(ap->dev, ">>> dump command table content, first %d bytes, phys addr = 0x%x:\n", 20, pp->cmd_tbl_dma);
	print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, pp->cmd_tbl, 20);
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	dma_sync_single_for_device(ap->dev, pp->cmd_tbl_dma, AHCI_CMD_TBL_AR_SZ, DMA_TO_DEVICE);

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	/* debug code follows */
#ifdef DEBUG_DONT_WRITE
	return;
#endif
	/* end of debug code */

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	/* issue command */
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	writel(0x11, port_mmio + PORT_CMD);
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	writel(1 << slot_num, port_mmio + PORT_CMD_ISSUE);
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}
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static ssize_t lba_start_read(struct device *dev, struct device_attribute *attr, char *buff)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;

	return snprintf(buff, 20, "%llu\n", dpriv->lba_ptr.lba_start);
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}

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static ssize_t lba_start_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
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{
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	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
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	struct elphel_ahci_priv *dpriv = hpriv->plat_data;

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	if (kstrtoull(buff, 10, &dpriv->lba_ptr.lba_start) != 0)
		return -EINVAL;
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	if (dpriv->lba_ptr.lba_write < dpriv->lba_ptr.lba_start)
		dpriv->lba_ptr.lba_write = dpriv->lba_ptr.lba_start;
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	return buff_sz;
}
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static ssize_t lba_end_read(struct device *dev, struct device_attribute *attr, char *buff)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;
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	return snprintf(buff, 20, "%llu\n", dpriv->lba_ptr.lba_end);
}
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static ssize_t lba_end_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;
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	if (kstrtoull(buff, 10, &dpriv->lba_ptr.lba_end) != 0)
		return -EINVAL;
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	if (dpriv->lba_ptr.lba_write > dpriv->lba_ptr.lba_end)
		dpriv->lba_ptr.lba_write = dpriv->lba_ptr.lba_end;

	return buff_sz;
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}

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static ssize_t lba_current_read(struct device *dev, struct device_attribute *attr, char *buff)
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{
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	struct ata_host *host = dev_get_drvdata(dev);
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	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;

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	return snprintf(buff, 20, "%llu\n", dpriv->lba_ptr.lba_write);
}
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static ssize_t lba_current_write(struct device *dev, struct device_attribute *attr, const char *buff, size_t buff_sz)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct elphel_ahci_priv *dpriv = hpriv->plat_data;

	if (kstrtoull(buff, 10, &dpriv->lba_ptr.lba_write) != 0)
		return -EINVAL;

	return buff_sz;
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}

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static DEVICE_ATTR(load_module, S_IWUSR | S_IWGRP, NULL, set_load_flag);
static DEVICE_ATTR(write, S_IWUSR | S_IWGRP, NULL, rawdev_write);
static DEVICE_ATTR(lba_start, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, lba_start_read, lba_start_write);
static DEVICE_ATTR(lba_end, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP, lba_end_read, lba_end_write);
static DEVICE_ATTR(lba_current, S_IRUSR | S_IRGRP | S_IWUSR | S_IRGRP, lba_current_read, lba_current_write);
static struct attribute *root_dev_attrs[] = {
		&dev_attr_load_module.attr,
		&dev_attr_write.attr,
		&dev_attr_lba_start.attr,
		&dev_attr_lba_end.attr,
		&dev_attr_lba_current.attr,
		&dev_attr_data_0_sz.attr,
		&dev_attr_data_1_sz.attr,
		&dev_attr_data_proc.attr,
		&dev_attr_exif_sz.attr,
		&dev_attr_jpg_hdr_sz.attr,
		NULL
};
static const struct attribute_group dev_attr_root_group = {
		.attrs			= root_dev_attrs,
		.name			= NULL,
};

static struct ata_port_operations ahci_elphel_ops = {
		.inherits		= &ahci_ops,
		.port_start		= elphel_port_start,
		.qc_prep		= elphel_qc_prep,
};

static const struct ata_port_info ahci_elphel_port_info = {
		AHCI_HFLAGS(AHCI_HFLAG_NO_NCQ),
		.flags			= AHCI_FLAG_COMMON,
		.pio_mask		= ATA_PIO4,
		.udma_mask		= ATA_UDMA6,
		.port_ops		= &ahci_elphel_ops,
};

static struct scsi_host_template ahci_platform_sht = {
		AHCI_SHT(DRV_NAME),
		.can_queue		= 1,
		.sg_tablesize	= AHCI_MAX_SG,
		.dma_boundary	= AHCI_DMA_BOUNDARY,
		.shost_attrs	= ahci_shost_attrs,
		.sdev_attrs		= ahci_sdev_attrs,
};

static const struct of_device_id ahci_elphel_of_match[] = {
		{ .compatible = "elphel,elphel-ahci", },
		{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, ahci_elphel_of_match);

static struct platform_driver ahci_elphel_driver = {
		.probe			= elphel_drv_probe,
		.remove			= elphel_drv_remove,
		.driver	= {
				.name	= DRV_NAME,
				.owner	= THIS_MODULE,
				.of_match_table	= ahci_elphel_of_match,
		},
};
module_platform_driver(ahci_elphel_driver);

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Mikhail Karpenko committed
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MODULE_LICENSE("GPL");
MODULE_AUTHOR("Elphel, Inc.");
MODULE_DESCRIPTION("Elphel AHCI SATA platform driver for elphel393 camera");