Fix bug in IDF export (plus minor cleaning up of IDF/VRML export)

pcbnew/exporters/export_idf.cpp

@@ -443,6 +443,9 @@ static void idf_export_module( BOARD* aPcb, MODULE* aModule,
                     comp->SetPosition( aModule->GetPosition().x * scale + dx,
                                        -aModule->GetPosition().y * scale + dy,
                                        rotz, IDF3::LYR_BOTTOM );
+
+                comp->SetPlacement( IDF3::PS_ECAD );
+
             }
             else
             {

utils/idftools/idf_parser.cpp

@@ -728,7 +728,8 @@ void IDF3_COMP_OUTLINE_DATA::writePlaceData( std::ofstream& aBoardFile,
 
     if( aPlacement == PS_INVALID )
     {
-        ERROR_IDF << "placement invalid; defaulting to PLACED\n";
+        ERROR_IDF << "placement invalid (" << aRefDes << ":";
+        std::cerr << aPlacement << "); defaulting to PLACED\n";
         aPlacement = PS_PLACED;
     }
 

utils/idftools/vrml_layer.cpp

@@ -30,7 +30,7 @@
 //    a closed loop as assumed for all other outlines.
 // 3. a scheme is needed to tell a castellated edge from a plain board edge
 
-#include <iostream>
+
 #include <sstream>
 #include <string>
 #include <iomanip>