pcbnew: More about work on color selection and items visibility:

removed global variables and a lot of redundancies

3d-viewer/3d_draw.cpp

@@ -114,11 +114,11 @@ GLuint Pcb3D_GLCanvas::CreateDrawGL_List()
     m_gllist = glGenLists( 1 );
 
     pcb->ComputeBoundaryBox();
-    g_Parm_3D_Visu.m_BoardSettings = pcb->m_BoardSettings;
+    g_Parm_3D_Visu.m_BoardSettings = pcb->GetBoardDesignSettings();
     g_Parm_3D_Visu.m_BoardSize     = pcb->m_BoundaryBox.GetSize();
     g_Parm_3D_Visu.m_BoardPos   = pcb->m_BoundaryBox.Centre();
     g_Parm_3D_Visu.m_BoardPos.y = -g_Parm_3D_Visu.m_BoardPos.y;
-    g_Parm_3D_Visu.m_Layers     = pcb->m_BoardSettings->GetCopperLayerCount();
+    g_Parm_3D_Visu.m_Layers     = pcb->GetCopperLayerCount();
 
     // Ensure the board has 2 sides for 3D views, because it is hard to find
     // a *really* single side board in the true life...
@@ -132,7 +132,7 @@ GLuint Pcb3D_GLCanvas::CreateDrawGL_List()
     // because all boards thickness no not match with this setup:
     // double epoxy_width = 1.6;    // epoxy width in mm
 
-    g_Parm_3D_Visu.m_Epoxy_Width = pcb->m_BoardSettings->m_LayerThickness
+    g_Parm_3D_Visu.m_Epoxy_Width = pcb->GetBoardDesignSettings()->m_BoardThickness
                                    * g_Parm_3D_Visu.m_BoardScale;
 
     /* calculate z position for each layer */

3d-viewer/3d_viewer.h

@@ -115,7 +115,7 @@ public:
     wxPoint   m_BoardPos;
     wxSize    m_BoardSize;
     int       m_Layers;
-    EDA_BoardDesignSettings* m_BoardSettings;   // Link to current board design
+    BOARD_DESIGN_SETTINGS* m_BoardSettings;   // Link to current board design
                                                 // settings
     double    m_Epoxy_Width;                    /* Epoxy thickness (normalized)
                                                  **/

CHANGELOG.txt

@@ -4,6 +4,16 @@ KiCad ChangeLog 2010
 Please add newer entries at the top, list the date and your name with
 email address.
 
+2010-Jan-31 UPDATE Jean-Pierre Charras <jean-pierre.charras@gipsa-lab.inpg.fr>
+================================================================================
+++ pcbnew:
+    More about work on color selection and items visibility:
+    removed global variables and a lot of redundancies
+    Now Modedit does not uses the visiblity options of the board editor
+    (That can create a problem id hide modules is activated)
+    work in progress but almost finished
+
+
 2010-Jan-30 UPDATE Jean-Pierre Charras <jean-pierre.charras@gipsa-lab.inpg.fr>
 ================================================================================
 ++ pcbnew:

common/class_colors_design_settings.cpp

@@ -93,7 +93,7 @@ int COLORS_DESIGN_SETTINGS::GetLayerColor( int aLayer )
  * sets the color for aLayer which is one of the layer indices given
  * in pcbstruct.h or in schematic
  */
-void COLORS_DESIGN_SETTINGS:: SetLayerColor( int aLayer, int aColor )
+void COLORS_DESIGN_SETTINGS::SetLayerColor( int aLayer, int aColor )
 {
     if( (unsigned) aLayer < DIM(m_LayersColors) )
     {
@@ -107,7 +107,7 @@ void COLORS_DESIGN_SETTINGS:: SetLayerColor( int aLayer, int aColor )
  * @return the color for an item which is one of the item indices given
  * in pcbstruct.h, enum PCB_VISIBLE or in schematic
  */
-int COLORS_DESIGN_SETTINGS:: GetItemColor( int aItemIdx )
+int COLORS_DESIGN_SETTINGS::GetItemColor( int aItemIdx )
 {
     if( (unsigned) aItemIdx < DIM(m_ItemsColors) )
     {
@@ -122,10 +122,25 @@ int COLORS_DESIGN_SETTINGS:: GetItemColor( int aItemIdx )
  * sets the color for an item which is one of the item indices given
  * in pcbstruct.h, enum PCB_VISIBLE or in schematic
  */
-void COLORS_DESIGN_SETTINGS:: SetItemColor( int aItemIdx, int aColor )
+void COLORS_DESIGN_SETTINGS::SetItemColor( int aItemIdx, int aColor )
 {
     if( (unsigned) aItemIdx < DIM(m_ItemsColors) )
     {
         m_ItemsColors[aItemIdx] = aColor;
     }
 }
+
+
+/**
+ * Function SetAllColorsAs
+ * sets alls colors to aColor
+ * Usefull to create a monochrome color selection for printing purpose
+ */
+void COLORS_DESIGN_SETTINGS::SetAllColorsAs( int aColor)
+{
+    for( unsigned ii = 0; ii < DIM(m_LayersColors); ii++ )
+        m_LayersColors[ii] = aColor;
+
+    for( unsigned ii = 0; ii < DIM(m_ItemsColors); ii++ )
+        m_ItemsColors[ii] = aColor;
+}

common/pcbcommon.cpp

@@ -100,7 +100,7 @@ int    g_PadCMPColor        = RED;
 
 
 // Current design settings:
-class EDA_BoardDesignSettings g_DesignSettings;
+class BOARD_DESIGN_SETTINGS g_DesignSettings;
 
 /**
  * Used in track creation, a list of track segments currently being created,

gerbview/deltrack.cpp

@@ -79,7 +79,7 @@ TRACK* WinEDA_GerberFrame::Delete_Segment( wxDC* DC, TRACK* Track )
         return NULL;
     }
 
-    Trace_Segment( DrawPanel, DC, Track, GR_XOR );
+    Trace_Segment( GetBoard(), DrawPanel, DC, Track, GR_XOR );
 
     DLIST<TRACK>* container = (DLIST<TRACK>*)Track->GetList();
     wxASSERT( container );

gerbview/dialog_print_using_printer.cpp

@@ -191,7 +191,7 @@ void DIALOG_PRINT_USING_PRINTER::InitValues( )
     BOARD* board = ((WinEDA_BasePcbFrame*)m_Parent)->GetBoard();
     for( int layer = 0; layer<NB_LAYERS; layer++, mask <<= 1 )
     {
-       if( ! board->m_BoardSettings->IsLayerEnabled( layer ) )
+       if( ! board->IsLayerEnabled( layer ) )
         {
             m_BoxSelectLayer[layer]->Enable( false );
             m_BoxSelectLayer[layer]->SetValue( false );

gerbview/export_to_pcbnew.cpp

@@ -90,9 +90,7 @@ static int WriteSetup( FILE* File, BOARD* Pcb )
     sprintf( text, "InternalUnit %f INCH\n", 1.0 / PCB_INTERNAL_UNIT );
     fprintf( File, "%s", text );
 
-    Pcb->m_BoardSettings->SetCopperLayerCount(
-         g_DesignSettings.GetCopperLayerCount() );
-    fprintf( File, "Layers %d\n", g_DesignSettings.GetCopperLayerCount() );
+    fprintf( File, "Layers %d\n", Pcb->GetCopperLayerCount() );
 
     fprintf( File, "$EndSETUP\n\n" );
     return 1;
@@ -104,7 +102,7 @@ static bool WriteGeneralDescrPcb( BOARD* Pcb, FILE* File )
     int NbLayers;
 
     /* Print the copper layer count */
-    NbLayers = Pcb->m_BoardSettings->GetCopperLayerCount();
+    NbLayers = Pcb->GetCopperLayerCount();
     fprintf( File, "$GENERAL\n" );
     fprintf( File, "LayerCount %d\n", NbLayers );
 

gerbview/gerbview.cpp

@@ -76,8 +76,6 @@ bool WinEDA_App::OnInit()
     ScreenPcb = new PCB_SCREEN();
     ScreenPcb->m_CurrentSheetDesc = &g_Sheet_GERBER;
 
-    g_DesignSettings.SetEnabledLayers( FULL_LAYERS );     // All 32 layers enabled at first.
-
     ActiveScreen = ScreenPcb;
 
     // read current setup and reopen last directory if no filename to open in
@@ -108,6 +106,8 @@ bool WinEDA_App::OnInit()
     /* Gerbview mainframe title */
     frame->SetTitle( GetTitle() + wxT( " " ) + GetBuildVersion() );
     frame->SetBoard( new BOARD( NULL, frame ) );
+    frame->GetBoard()->SetEnabledLayers( FULL_LAYERS );     // All 32 layers enabled at first.
+
 
     // Initialize some display options
     DisplayOpt.DisplayPadIsol = false;      // Pad clearance has no meaning

gerbview/gerbview_config.h

@@ -13,7 +13,7 @@
 /* Useful macro : */
 #define LOC_COLOR(numlayer) &g_ColorsSettings.m_LayersColors[numlayer]
 
-/* Liste des parametres */
+/* Config parameters list */
 
 static PARAM_CFG_WXSTRING PhotoExtBufCfg
 (
@@ -342,8 +342,7 @@ static PARAM_CFG_SETCOLOR ColorpcbGrilleCfg
 (
     INSETUP,
     wxT("CoPcbGr"),
-//@@IMB: Wrong object    &g_DesignSettings.m_PcbGridColor, /* Adresse du parametre */
-    &g_GridColor,       //@@IMB: This is the real variable.
+    &g_GridColor,
     DARKGRAY
 );
 
@@ -363,22 +362,6 @@ static PARAM_CFG_INT GERBERSpotMiniCfg
     2,0xFFFF
 );
 
-static PARAM_CFG_INT DrawSegmLargeurCfg
-(
-    wxT("DrawLar"),
-    &g_DesignSettings.m_DrawSegmentWidth,
-    120,
-    0,10000
-);
-
-static PARAM_CFG_INT EdgeSegmLargeurCfg
-(
-    wxT("EdgeLar"),
-    &g_DesignSettings.m_EdgeSegmentWidth,
-    120,
-    0,10000
-);
-
 static PARAM_CFG_INT TimeOutCfg
 (
     wxT("TimeOut"),
@@ -441,8 +424,6 @@ PARAM_CFG_BASE * ParamCfgList[] =
     & ColorpcbGrilleCfg,
     & ColorDCodesCfg,
     & GERBERSpotMiniCfg,
-    & DrawSegmLargeurCfg,
-    & EdgeSegmLargeurCfg,
     & TimeOutCfg,
     & DisplPolairCfg,
     NULL

gerbview/lay2plot.cpp

@@ -30,7 +30,7 @@ void Print_PcbItems(BOARD * Pcb, wxDC *DC, int drawmode, int printmasklayer)
     for( ; pt_piste != NULL ; pt_piste = pt_piste->Next() )
     {
 //      if( (printmasklayer & ReturnMaskLayer(pt_piste) ) == 0 ) continue;
-        Trace_Segment(NULL, DC, pt_piste, drawmode);
+        Trace_Segment(Pcb, NULL, DC, pt_piste, drawmode);
     }
 
     DisplayOpt = save_opt;

gerbview/protos.h

 /* declarations prototype */
 
-/***************************/
-/* select_layers_to_pcb.cpp*/
-/***************************/
 int* InstallDialogLayerPairChoice( WinEDA_GerberFrame* parent );
 
-/***********************/
-/* gerbview_config.cpp */
-/***********************/
 bool Read_Config();
 bool Read_Hotkey_Config( WinEDA_DrawFrame* frame, bool verbose );
 
 
-/****************/
-/* lay2plot.cpp */
-
 void Print_PcbItems( BOARD* Pcb, wxDC* DC, int drawmode, int printmasklayer );
 
-/*****************/
-/* set_color.cpp */
-/*****************/
-void DisplayColorSetupFrame( WinEDA_DrawFrame* parent, const wxPoint& framepos );
-
-
-/***************/
-/* trpiste.cpp */
-/***************/
-void Trace_Segment( WinEDA_DrawPanel* panel,
+void DisplayColorSetupFrame( WinEDA_GerberFrame* parent, const wxPoint& framepos );
+void Trace_Segment( BOARD* aBrd, WinEDA_DrawPanel* panel,
                     wxDC*             DC,
                     TRACK*            pt_piste,
                     int               draw_mode );
 
+

gerbview/select_layers_to_pcb.cpp

@@ -129,7 +129,7 @@ WinEDA_SwapLayerFrame::WinEDA_SwapLayerFrame( WinEDA_GerberFrame* parent ) :
         ButtonTable[ii] = -1;
         LayerLookUpTable[ii] = LAYER_UNSELECTED;
     }
-    g_DesignSettings.SetCopperLayerCount(pcb_layer_number);
+    m_Parent->GetBoard()->SetCopperLayerCount(pcb_layer_number);
 
     pcb_layer_number = 0;
     for( nb_items = 0, ii = 0; ii < 32; ii++ )
@@ -137,8 +137,8 @@ WinEDA_SwapLayerFrame::WinEDA_SwapLayerFrame( WinEDA_GerberFrame* parent ) :
         if( g_GERBER_List[ii] == NULL )
             continue;
 
-        if( (pcb_layer_number == g_DesignSettings.GetCopperLayerCount() - 1)
-           && (g_DesignSettings.GetCopperLayerCount() > 1) )
+        if( (pcb_layer_number == m_Parent->GetBoard()->GetCopperLayerCount() - 1)
+           && (m_Parent->GetBoard()->GetCopperLayerCount() > 1) )
             pcb_layer_number = LAYER_N_FRONT;
 
         ButtonTable[nb_items] = ii;
@@ -399,7 +399,7 @@ void WinEDA_SwapLayerFrame::OnOkClick( wxCommandEvent& event )
     if( layers_count > NB_COPPER_LAYERS ) // should not occur.
         layers_count = NB_COPPER_LAYERS;
 
-    g_DesignSettings.SetCopperLayerCount( layers_count );
+    m_Parent->GetBoard()->SetCopperLayerCount( layers_count );
 
     EndModal( 1 );
 }

gerbview/set_color.cpp

@@ -41,7 +41,7 @@ END_EVENT_TABLE()
 
 
 /*****************************************************/
-void DisplayColorSetupFrame( WinEDA_DrawFrame* parent,
+void DisplayColorSetupFrame( WinEDA_GerberFrame* parent,
                              const wxPoint&    framepos )
 /*****************************************************/
 {
@@ -62,7 +62,7 @@ WinEDA_SetColorsFrame::WinEDA_SetColorsFrame()
 
 
 // Standard Constructor
-WinEDA_SetColorsFrame::WinEDA_SetColorsFrame( WinEDA_DrawFrame* parent,
+WinEDA_SetColorsFrame::WinEDA_SetColorsFrame( WinEDA_GerberFrame* parent,
                                               const wxPoint& framepos )
 {
     m_Parent = parent;
@@ -210,7 +210,7 @@ void WinEDA_SetColorsFrame::CreateControls()
 
         if( laytool_list[lyr]->m_NoDisplayIsColor )
         {
-            if( g_DesignSettings.IsLayerVisible( lyr ))
+            if( m_Parent->GetBoard()->IsLayerVisible( lyr ))
                 CheckBox->SetValue( TRUE );
             else
                 CheckBox->SetValue( FALSE );
@@ -426,7 +426,7 @@ void WinEDA_SetColorsFrame::UpdateLayerSettings()
 {
     for( int lyr = 0; lyr < NB_BUTT - 2; lyr++ )
     {
-        g_DesignSettings.SetLayerVisibility( lyr, laytool_list[lyr]->m_CheckBox->GetValue() );
+        m_Parent->GetBoard()->GetBoardDesignSettings()->SetLayerVisibility( lyr, laytool_list[lyr]->m_CheckBox->GetValue() );
         *laytool_list[lyr]->m_Color = CurrentColor[lyr];
     }
 

gerbview/set_color.h

@@ -390,7 +390,7 @@ private:
     DECLARE_DYNAMIC_CLASS( WinEDA_SetColorsFrame )
     DECLARE_EVENT_TABLE()
 
-    WinEDA_DrawFrame*       m_Parent;
+    WinEDA_GerberFrame*       m_Parent;
     wxBoxSizer*             OuterBoxSizer;
     wxBoxSizer*             MainBoxSizer;
     wxFlexGridSizer*        FlexColumnBoxSizer;
@@ -430,7 +430,7 @@ private:
 public:
     // Constructors and destructor
     WinEDA_SetColorsFrame();
-    WinEDA_SetColorsFrame( WinEDA_DrawFrame* parent, const wxPoint& framepos );
+    WinEDA_SetColorsFrame( WinEDA_GerberFrame* parent, const wxPoint& framepos );
     ~WinEDA_SetColorsFrame();
 };
 

gerbview/tracepcb.cpp

@@ -18,6 +18,10 @@
 #include "class_board_design_settings.h"
 #include "colors_selection.h"
 
+/***************/
+/* tracepcb.cpp */
+/***************/
+
 static void Draw_Track_Buffer( WinEDA_DrawPanel* panel,
                         wxDC*             DC,
                         BOARD*            Pcb,
@@ -127,7 +131,7 @@ void WinEDA_GerberFrame::Trace_Gerber( wxDC* DC, int draw_mode, int printmasklay
     {
         if( !(track->ReturnMaskLayer() & printmasklayer) )
             continue;
-        if( g_DesignSettings.IsLayerVisible( track->GetLayer() ) == false )
+        if( GetBoard()->IsLayerVisible( track->GetLayer() ) == false )
             continue;
 
 //        D(printf("D:%p\n", track );)
@@ -219,9 +223,9 @@ void Draw_Track_Buffer( WinEDA_DrawPanel* panel, wxDC* DC, BOARD* Pcb, int draw_
 //        D(printf("D:%p\n", track );)
 
         if( dcode_hightlight == track->GetNet() && track->GetLayer()==layer )
-            Trace_Segment( panel, DC, track, draw_mode | GR_SURBRILL );
+            Trace_Segment( Pcb, panel, DC, track, draw_mode | GR_SURBRILL );
         else
-            Trace_Segment( panel, DC, track, draw_mode );
+            Trace_Segment( Pcb, panel, DC, track, draw_mode );
     }
 }
 
@@ -229,7 +233,7 @@ void Draw_Track_Buffer( WinEDA_DrawPanel* panel, wxDC* DC, BOARD* Pcb, int draw_
 #if 1
 
 /***********************************************************************************/
-void Trace_Segment( WinEDA_DrawPanel* panel, wxDC* DC, TRACK* track, int draw_mode )
+void Trace_Segment( BOARD* aBrd, WinEDA_DrawPanel* panel, wxDC* DC, TRACK* track, int draw_mode )
 /***********************************************************************************/
 
 /* Trace 1 segment of track (segment, spot...).
@@ -251,10 +255,10 @@ void Trace_Segment( WinEDA_DrawPanel* panel, wxDC* DC, TRACK* track, int draw_mo
     }
     else
     {
-        if( g_DesignSettings.IsLayerVisible( track->GetLayer() ) == false )
+        if( aBrd->IsLayerVisible( track->GetLayer() ) == false )
             return;
 
-        color = g_ColorsSettings.GetLayerColor( track->GetLayer() );
+        color = aBrd->GetLayerColor( track->GetLayer() );
 
         if( draw_mode & GR_SURBRILL )
         {
@@ -420,7 +424,7 @@ void Affiche_DCodes_Pistes( WinEDA_DrawPanel* panel, wxDC* DC, BOARD* Pcb, int d
     track = Pcb->m_Track;
     for( ; track != NULL; track = track->Next() )
     {
-        if( g_DesignSettings.IsLayerVisible( track->GetLayer() ) == false )
+        if( Pcb->IsLayerVisible( track->GetLayer() ) == false )
             continue;
 
         if( (track->m_Shape == S_ARC)

include/class_board_design_settings.h

@@ -8,7 +8,7 @@
 #include "pcbstruct.h"      // NB_COLORS
 
 // Class for handle current printed board design settings
-class EDA_BoardDesignSettings
+class BOARD_DESIGN_SETTINGS
 {
 protected:
     int    m_CopperLayerCount;                          // Number of copper layers for this design
@@ -30,7 +30,7 @@ public:
     int    m_SolderPasteMargin;                         // Solder paste margin absolute value
     double m_SolderPasteMarginRatio;                    // Solder pask margin ratio value of pad size
                                                         // The final margin is the sum of these 2 values
-    int    m_LayerThickness;                            // Layer Thickness for 3D viewer
+    int    m_BoardThickness;                            // Board Thickness for 3D viewer
 
 protected:
     int    m_EnabledLayers;                         // Bit-mask for layer enabling
@@ -38,7 +38,7 @@ protected:
     int    m_VisibleElements;                       // Bit-mask for element category visibility
 
 public:
-    EDA_BoardDesignSettings();
+    BOARD_DESIGN_SETTINGS();
 
     /**
      * Function GetVisibleLayers
@@ -150,7 +150,7 @@ public:
      * @param aLayerIndex = The index of the layer to be tested
      * @return bool - true if the layer is enabled
      */
-    bool IsLayerEnabled( int aLayerIndex )
+    bool IsLayerEnabled( int aLayerIndex ) const
     {
         return bool( m_EnabledLayers & (1 << aLayerIndex) );
     }

include/class_colors_design_settings.h

@@ -53,6 +53,13 @@ public:
      * in pcbstruct.h, enum PCB_VISIBLE or in schematic
      */
     void SetItemColor(  int aItemIdx, int aColor );
+
+    /**
+     * Function SetAllColorsAs
+     * sets alls colors to aColor
+     * Usefull to create a monochrome color selection for printing purpose
+     */
+    void SetAllColorsAs( int aColor);
 };
 
 #endif  //  _COLORS_DESIGN_SETTING_H

include/class_pcb_screen.h

@@ -44,14 +44,6 @@ public:
     void SetCurItem( BOARD_ITEM* aItem ) { BASE_SCREEN::SetCurItem( aItem ); }
 
 
-    /* Return true if a microvia can be put on board
-     * A microvia is a small via restricted to 2 near neighbor layers
-     * because its is hole is made by laser which can penetrate only one layer
-     * It is mainly used to connect BGA to the first inner layer
-     * And it is allowed from an external layer to the first inner layer
-     */
-    bool IsMicroViaAcceptable( void );
-
     /* full undo redo management : */
 
     // use BASE_SCREEN::ClearUndoRedoList()

include/pcbcommon.h

@@ -11,7 +11,6 @@ class DPAD;
 class BOARD_ITEM;
 class PCB_SCREEN;
 class DISPLAY_OPTIONS;
-class EDA_BoardDesignSettings;
 
 /* Look up Table for conversion one layer number -> one bit layer mask: */
 extern int g_TabOneLayerMask[LAYER_COUNT];
@@ -41,9 +40,6 @@ extern int g_CurrentVersionPCB;
 extern int    g_TimeOut;            // Timer for automatic saving
 extern int    g_SaveTime;           // Time for next saving
 
-// Current design settings:
-extern class EDA_BoardDesignSettings g_DesignSettings;
-
 extern DLIST<TRACK> g_CurrentTrackList;
 
 #define g_CurrentTrackSegment    \

include/wxPcbStruct.h

@@ -538,6 +538,14 @@ public:
     // Track and via edition:
     void   Via_Edit_Control( wxCommandEvent& event );
 
+    /* Return true if a microvia can be put on board
+     * A microvia is a small via restricted to 2 near neighbor layers
+     * because its is hole is made by laser which can penetrate only one layer
+     * It is mainly used to connect BGA to the first inner layer
+     * And it is allowed from an external layer to the first inner layer
+     */
+    bool IsMicroViaAcceptable( void );
+
     /**
      * Function Other_Layer_Route
      * operates in one of two ways.  If argument track is NULL, then swap the
@@ -630,7 +638,7 @@ public:
      * @param aItemsListPicker = the list picker to use for an undo command
      *                           (can be NULL)
      * @param aUseNetclassValue = true to use NetClass value, false to use
-     *                            g_DesignSettings value
+     *                            current designSettings value
      * @return  true if done, false if no not change (because DRC error)
      */
     bool SetTrackSegmentWidth( TRACK*             aTrackItem,

pcbnew/autorout.cpp

@@ -39,7 +39,7 @@ void WinEDA_PcbFrame::Autoroute( wxDC* DC, int mode )
     int      autoroute_net_code = -1;
     wxString msg;
 
-    if( g_DesignSettings.GetCopperLayerCount() > 1 )
+    if( GetBoard()->GetCopperLayerCount() > 1 )
     {
         Route_Layer_TOP    = ((PCB_SCREEN*)GetScreen())->m_Route_Layer_TOP;
         Route_Layer_BOTTOM = ((PCB_SCREEN*)GetScreen())->m_Route_Layer_BOTTOM;

pcbnew/basepcbframe.cpp

@@ -178,7 +178,7 @@ void WinEDA_BasePcbFrame::SwitchLayer( wxDC* DC, int layer )
         // If only one copper layer is enabled, the only such layer
         // that can be selected to is the "Copper" layer (so the
         // selection of any other copper layer is disregarded).
-        if( m_Pcb->m_BoardSettings->GetCopperLayerCount() < 2 )
+        if( m_Pcb->GetCopperLayerCount() < 2 )
         {
             if( layer != LAYER_N_BACK )
             {
@@ -193,7 +193,7 @@ void WinEDA_BasePcbFrame::SwitchLayer( wxDC* DC, int layer )
         else
         {
             if( ( layer != LAYER_N_BACK ) && ( layer != LAYER_N_FRONT )
-                && ( layer >= m_Pcb->m_BoardSettings->GetCopperLayerCount() - 1 ) )
+                && ( layer >= m_Pcb->GetCopperLayerCount() - 1 ) )
             {
                 return;
             }
@@ -273,15 +273,15 @@ BOARD_ITEM* WinEDA_BasePcbFrame::GetCurItem()
 
 GENERAL_COLLECTORS_GUIDE WinEDA_BasePcbFrame::GetCollectorsGuide()
 {
-    GENERAL_COLLECTORS_GUIDE guide( m_Pcb->m_BoardSettings->GetVisibleLayers(),
+    GENERAL_COLLECTORS_GUIDE guide( m_Pcb->GetVisibleLayers(),
                                     ( (PCB_SCREEN*)GetScreen())->m_Active_Layer );
 
     // account for the globals
-    guide.SetIgnoreMTextsMarkedNoShow( ! g_DesignSettings.IsElementVisible( MOD_TEXT_INVISIBLE ));
-    guide.SetIgnoreMTextsOnCopper( ! g_DesignSettings.IsElementVisible( MOD_TEXT_BK_VISIBLE ));
-    guide.SetIgnoreMTextsOnCmp( ! g_DesignSettings.IsElementVisible( MOD_TEXT_FR_VISIBLE ));
-    guide.SetIgnoreModulesOnCu( !g_DesignSettings.IsElementVisible( MOD_BK_VISIBLE ) );
-    guide.SetIgnoreModulesOnCmp( !g_DesignSettings.IsElementVisible( MOD_FR_VISIBLE ) );
+    guide.SetIgnoreMTextsMarkedNoShow( ! m_Pcb->IsElementVisible( MOD_TEXT_INVISIBLE ));
+    guide.SetIgnoreMTextsOnCopper( ! m_Pcb->IsElementVisible( MOD_TEXT_BK_VISIBLE ));
+    guide.SetIgnoreMTextsOnCmp( ! m_Pcb->IsElementVisible( MOD_TEXT_FR_VISIBLE ));
+    guide.SetIgnoreModulesOnCu( ! m_Pcb->IsElementVisible( MOD_BK_VISIBLE ) );
+    guide.SetIgnoreModulesOnCmp( ! m_Pcb->IsElementVisible( MOD_FR_VISIBLE ) );
 
     return guide;
 }

pcbnew/class_board.cpp

@@ -14,6 +14,9 @@
  */
 wxPoint BOARD_ITEM::ZeroOffset( 0, 0 );
 
+// Current design settings (used also to read configs):
+BOARD_DESIGN_SETTINGS boardDesignSettings;
+
 
 /*****************/
 /* Class BOARD: */
@@ -25,7 +28,8 @@ BOARD::BOARD( EDA_BaseStruct* parent, WinEDA_BasePcbFrame* frame ) :
 {
     m_PcbFrame = frame;
     m_Status_Pcb    = 0;                    // Status word: bit 1 = calculate.
-    m_BoardSettings = &g_DesignSettings;
+    SetBoardDesignSettings(&boardDesignSettings);
+    SetColorsSettings(&g_ColorsSettings);
     m_NbNodes     = 0;                      // Number of connected pads.
     m_NbNoconnect = 0;                      // Number of unconnected nets.
 
@@ -181,15 +185,13 @@ int BOARD::GetCurrentMicroViaDrill()
 }
 
 
-
 wxString BOARD::GetLayerName( int aLayerIndex ) const
 {
     if( !IsValidLayerIndex( aLayerIndex ) )
         return wxEmptyString;
 
     // copper layer names are stored in the BOARD.
-    if( IsValidCopperLayerIndex( aLayerIndex )
-       && m_BoardSettings->IsLayerEnabled( aLayerIndex ) )
+    if( IsValidCopperLayerIndex( aLayerIndex ) && IsLayerEnabled( aLayerIndex ) )
     {
         // default names were set in BOARD::BOARD() but they may be
         // over-ridden by BOARD::SetLayerName()
@@ -263,11 +265,11 @@ bool BOARD::SetLayerName( int aLayerIndex, const wxString& aLayerName )
     // replace any spaces with underscores before we do any comparing
     NameTemp.Replace( wxT( " " ), wxT( "_" ) );
 
-    if( m_BoardSettings->IsLayerEnabled( aLayerIndex ) )
+    if( IsLayerEnabled( aLayerIndex ) )
     {
         for( int i = 0; i < NB_COPPER_LAYERS; i++ )
         {
-            if( i != aLayerIndex && m_BoardSettings->IsLayerEnabled( i )
+            if( i != aLayerIndex && IsLayerEnabled( i )
                 && NameTemp == m_Layer[i].m_Name )
                 return false;
         }
@@ -288,7 +290,7 @@ LAYER_T BOARD::GetLayerType( int aLayerIndex ) const
 
     //@@IMB: The original test was broken due to the discontinuity
     // in the layer sequence.
-    if( m_BoardSettings->IsLayerEnabled( aLayerIndex ) )
+    if( IsLayerEnabled( aLayerIndex ) )
         return m_Layer[aLayerIndex].m_Type;
     return LT_SIGNAL;
 }
@@ -301,7 +303,7 @@ bool BOARD::SetLayerType( int aLayerIndex, LAYER_T aLayerType )
 
     //@@IMB: The original test was broken due to the discontinuity
     // in the layer sequence.
-    if( m_BoardSettings->IsLayerEnabled( aLayerIndex ) )
+    if( IsLayerEnabled( aLayerIndex ) )
     {
         m_Layer[aLayerIndex].m_Type = aLayerType;
         return true;
@@ -354,35 +356,36 @@ LAYER_T LAYER::ParseType( const char* aType )
 
 int BOARD::GetCopperLayerCount() const
 {
-    return m_BoardSettings->GetCopperLayerCount();
+    return GetBoardDesignSettings()->GetCopperLayerCount();
 }
+
 void BOARD::SetCopperLayerCount( int aCount )
 {
-    m_BoardSettings->SetCopperLayerCount( aCount );
+    GetBoardDesignSettings()->SetCopperLayerCount( aCount );
 }
 
 
 int BOARD::GetEnabledLayers() const
 {
-    return m_BoardSettings->GetEnabledLayers();
+    return GetBoardDesignSettings()->GetEnabledLayers();
 }
 
 
 int BOARD::GetVisibleLayers() const
 {
-    return m_BoardSettings->GetVisibleLayers();
+    return GetBoardDesignSettings()->GetVisibleLayers();
 }
 
 
 void BOARD::SetEnabledLayers( int aLayerMask )
 {
-    m_BoardSettings->SetEnabledLayers( aLayerMask );
+    GetBoardDesignSettings()->SetEnabledLayers( aLayerMask );
 }
 
 
 void BOARD::SetVisibleLayers( int aLayerMask )
 {
-    m_BoardSettings->SetVisibleLayers( aLayerMask );
+    GetBoardDesignSettings()->SetVisibleLayers( aLayerMask );
 }
 
 
@@ -415,23 +418,13 @@ void BOARD::SetVisibleAlls(  )
 
 int BOARD::GetVisibleElements() const
 {
-    return m_BoardSettings->GetVisibleElements();
+    return GetBoardDesignSettings()->GetVisibleElements();
 }
 
 
 bool BOARD::IsElementVisible( int aPCB_VISIBLE ) const
 {
-    // @todo move these special cases into default, by moving globals into the board.
-    switch( aPCB_VISIBLE )
-    {
-/*
-    case GRID_VISIBLE:
-        myframe->m_Draw_Grid = isEnabled;
-        break;
-*/
-    default:
-        return m_BoardSettings->IsElementVisible( aPCB_VISIBLE );
-    }
+    return GetBoardDesignSettings()->IsElementVisible( aPCB_VISIBLE );
 }
 
 
@@ -441,12 +434,12 @@ void BOARD::SetElementVisibility( int aPCB_VISIBLE, bool isEnabled )
     {
     case GRID_VISIBLE:
         m_PcbFrame->m_Draw_Grid = isEnabled;
-        m_BoardSettings->SetElementVisibility( aPCB_VISIBLE, isEnabled );
+        GetBoardDesignSettings()->SetElementVisibility( aPCB_VISIBLE, isEnabled );
         break;
 
 
     case RATSNEST_VISIBLE:
-        m_BoardSettings->SetElementVisibility( aPCB_VISIBLE, isEnabled );
+        GetBoardDesignSettings()->SetElementVisibility( aPCB_VISIBLE, isEnabled );
         // we must clear or set the CH_VISIBLE flags to hide/show ratsnet
         // because we have a tool to show hide ratsnest relative to a pad or a module
         // so the hide/show option is a per item selection
@@ -464,7 +457,7 @@ void BOARD::SetElementVisibility( int aPCB_VISIBLE, bool isEnabled )
 
 
     default:
-        m_BoardSettings->SetElementVisibility( aPCB_VISIBLE, isEnabled );
+        GetBoardDesignSettings()->SetElementVisibility( aPCB_VISIBLE, isEnabled );
     }
 }
 
@@ -485,7 +478,7 @@ int BOARD::GetVisibleElementColor( int aPCB_VISIBLE )
     case PAD_FR_VISIBLE:
     case PAD_BK_VISIBLE:
     case RATSNEST_VISIBLE:
-        color = g_ColorsSettings.GetItemColor( aPCB_VISIBLE );
+        color = GetColorsSettings()->GetItemColor( aPCB_VISIBLE );
         break;
     case GRID_VISIBLE:
         color = g_GridColor;
@@ -512,10 +505,10 @@ void BOARD::SetVisibleElementColor( int aPCB_VISIBLE, int aColor )
     case ANCHOR_VISIBLE:
     case PAD_FR_VISIBLE:
     case PAD_BK_VISIBLE:
-        g_ColorsSettings.SetItemColor( aPCB_VISIBLE, aColor );
+        GetColorsSettings()->SetItemColor( aPCB_VISIBLE, aColor );
         break;
     case RATSNEST_VISIBLE:
-        g_ColorsSettings.SetItemColor( aPCB_VISIBLE, aColor );
+        GetColorsSettings()->SetItemColor( aPCB_VISIBLE, aColor );
         break;
 
     case GRID_VISIBLE:
@@ -530,15 +523,35 @@ void BOARD::SetVisibleElementColor( int aPCB_VISIBLE, int aColor )
 
 void BOARD::SetLayerColor( int aLayer, int aColor )
 {
-    g_ColorsSettings.SetLayerColor( aLayer, aColor );
+    GetColorsSettings()->SetLayerColor( aLayer, aColor );
 }
 
 
 int BOARD::GetLayerColor( int aLayer )
 {
-    return g_ColorsSettings.GetLayerColor( aLayer );
+    return GetColorsSettings()->GetLayerColor( aLayer );
 }
 
+/**
+ * Function IsModuleLayerVisible
+ * expects either of the two layers on which a module can reside, and returns
+ * whether that layer is visible.
+ * @param layer One of the two allowed layers for modules: LAYER_N_FRONT or LAYER_N_BACK
+ * @return bool - true if the layer is visible, else false.
+ */
+bool BOARD::IsModuleLayerVisible( int layer )
+{
+    if( layer==LAYER_N_FRONT )
+        return IsElementVisible( PCB_VISIBLE(MOD_FR_VISIBLE) );
+
+    else if( layer==LAYER_N_BACK )
+        return IsElementVisible( PCB_VISIBLE(MOD_BK_VISIBLE) );
+
+    else
+        return true;
+}
+
+
 
 wxPoint& BOARD::GetPosition()
 {

pcbnew/class_board.h

@@ -7,10 +7,11 @@
 
 #include "dlist.h"
 #include "class_netinfo.h"
+#include "class_colors_design_settings.h"
+#include "class_board_design_settings.h"
 
 
 class ZONE_CONTAINER;
-class EDA_BoardDesignSettings;
 
 
 /**
@@ -62,7 +63,7 @@ struct LAYER
 
 /** a small helper class to handle a stock of specific vias diameter and drill pair
  * in the BOARD class
-*/
+ */
 class VIA_DIMENSION
 {
 public:
@@ -74,15 +75,18 @@ public:
         m_Diameter = 0; m_Drill = 0;
     }
 
-    bool operator == (const VIA_DIMENSION& other) const
+
+    bool operator ==( const VIA_DIMENSION& other ) const
     {
-        return (m_Diameter == other.m_Diameter) &&
-                (m_Drill == other.m_Drill);
+        return (m_Diameter == other.m_Diameter)
+               && (m_Drill == other.m_Drill);
     }
-    bool operator < (const VIA_DIMENSION& other) const
+
+
+    bool operator <( const VIA_DIMENSION& other ) const
     {
-        if (m_Diameter != other.m_Diameter)
-            return (m_Diameter < other.m_Diameter);
+        if( m_Diameter != other.m_Diameter )
+            return m_Diameter < other.m_Diameter;
         return m_Drill < other.m_Drill;
     }
 };
@@ -110,7 +114,6 @@ public:
     WinEDA_BasePcbFrame* m_PcbFrame;                        // Window of visualization
     EDA_Rect             m_BoundaryBox;                     // Board size and position
     int m_Status_Pcb;                                       // Flags used in ratsnet calculation and update
-    EDA_BoardDesignSettings* m_BoardSettings;               // Link to current design settings
     int m_NbNodes;                                          // Active pads (pads attached to a net ) count
     int m_NbNoconnect;                                      // Active ratsnet count (rastnests not already connected by tracks)
 
@@ -144,6 +147,10 @@ public:
                                                         // 0 is the index selection of the default value Netclass
     unsigned m_TrackWidthSelector;                      // index for m_TrackWidthList to select the value
 
+private:
+    BOARD_DESIGN_SETTINGS*  m_boardDesignSettings;  // Link to current design settings
+    COLORS_DESIGN_SETTINGS* m_colorsSettings;       // Link to current colors settings
+
     /**********************************/
 public:
     BOARD( EDA_BaseStruct* aParent, WinEDA_BasePcbFrame* frame );
@@ -267,6 +274,30 @@ public:
      */
     void SetEnabledLayers( int aLayerMask );
 
+    /**
+     * Function IsLayerEnabled
+     * is a proxy function that calls the correspondent function in m_BoardSettings
+     * tests whether a given layer is enabled
+     * @param aLayerIndex = The index of the layer to be tested
+     * @return bool - true if the layer is visible.
+     */
+    bool IsLayerEnabled( int aLayer ) const
+    {
+        return GetBoardDesignSettings()->IsLayerEnabled( aLayer );
+    }
+
+    /**
+     * Function IsLayerVisible
+     * is a proxy function that calls the correspondent function in m_BoardSettings
+     * tests whether a given layer is visible
+     * @param aLayerIndex = The index of the layer to be tested
+     * @return bool - true if the layer is visible.
+     */
+    bool IsLayerVisible( int aLayerIndex ) const
+    {
+        return GetBoardDesignSettings()->IsLayerVisible( aLayerIndex );
+    }
+
     /**
      * Function GetVisibleLayers
      * is a proxy function that calls the correspondent function in m_BoardSettings
@@ -309,7 +340,7 @@ public:
      * changes the bit-mask of visible element categories and layers
      * @see enum PCB_VISIBLE
      */
-    void SetVisibleAlls( );
+    void SetVisibleAlls();
 
     /**
      * Function IsElementVisible
@@ -330,6 +361,15 @@ public:
      */
     void SetElementVisibility( int aPCB_VISIBLE, bool aNewState );
 
+    /**
+     * Function IsModuleLayerVisible
+     * expects either of the two layers on which a module can reside, and returns
+     * whether that layer is visible.
+     * @param layer One of the two allowed layers for modules: LAYER_N_FRONT or LAYER_N_BACK
+     * @return bool - true if the layer is visible, else false.
+     */
+    bool IsModuleLayerVisible( int layer );
+
     /**
      * Function GetVisibleElementColor
      * returns the color of a pcb visible element.
@@ -339,6 +379,40 @@ public:
     void SetVisibleElementColor( int aPCB_VISIBLE, int aColor );
 
 
+    /** Function GetBoardDesignSettings
+     * @return the current BOARD_DESIGN_SETTINGS in use
+     */
+    BOARD_DESIGN_SETTINGS* GetBoardDesignSettings() const
+    {
+        return m_boardDesignSettings;
+    }
+
+
+    /** Function SetBoardDesignSettings
+     * @param aDesignSettings = the new BOARD_DESIGN_SETTINGS to use
+     */
+    void SetBoardDesignSettings( BOARD_DESIGN_SETTINGS* aDesignSettings)
+    {
+        m_boardDesignSettings = aDesignSettings;
+    }
+
+    /** Function SetBoardSettings
+     * @return the current COLORS_DESIGN_SETTINGS in use
+     */
+    COLORS_DESIGN_SETTINGS* GetColorsSettings() const
+    {
+        return m_colorsSettings;
+    }
+
+    /** Function SetColorsSettings
+     * @param aColorsSettings = the new COLORS_DESIGN_SETTINGS to use
+     */
+    void SetColorsSettings(COLORS_DESIGN_SETTINGS* aColorsSettings)
+    {
+        m_colorsSettings = aColorsSettings;
+    }
+
+
     /**
      * Function GetLayerName
      * returns the name of the layer given by aLayerIndex.
@@ -391,7 +465,6 @@ public:
      */
     int      GetLayerColor( int aLayer );
 
-
     /* Functions to get some items count */
     int      GetNumSegmTrack();
     int      GetNumSegmZone();
@@ -501,6 +574,7 @@ public:
     /**************************************/
     /** function relative to NetClasses: **/
     /**************************************/
+
     /**
      * Function SynchronizeNetsAndNetClasses
      * copies NETCLASS info to each NET, based on NET membership in a NETCLASS.
@@ -537,6 +611,7 @@ public:
         return m_TrackWidthList[m_TrackWidthSelector];
     }
 
+
     /** function GetCurrentViaSize
      * @return the current via size, according to the selected options
      * ( using the default netclass value or a preset value )
@@ -547,6 +622,7 @@ public:
         return m_ViasDimensionsList[m_ViaSizeSelector].m_Diameter;
     }
 
+
     /** function GetCurrentViaDrill
      * @return the current via size, according to the selected options
      * ( using the default netclass value or a preset value )
@@ -558,6 +634,7 @@ public:
                m_ViasDimensionsList[m_ViaSizeSelector].m_Drill : -1;
     }
 
+
     /** function GetCurrentMicroViaSize
      * @return the current micro via size,
      * that is the current netclass value
@@ -571,6 +648,7 @@ public:
     int  GetCurrentMicroViaDrill();
 
     /***************************************************************************/
+
     /**
      * Function Save
      * writes the data structures for this object out to a FILE in "*.brd" format.
@@ -860,7 +938,6 @@ public:
      * @param aNetcode = netcode to analyze. if -1, analyze all nets
      */
     void Test_Connections_To_Copper_Areas( int aNetcode = -1 );
-
 };
 
 #endif      // #ifndef CLASS_BOARD_H

pcbnew/class_board_design_settings.cpp

 /***************************************************************************/
-/* class_board_design_settings.cpp - EDA_BoardDesignSettings class functions */
+/* class_board_design_settings.cpp - BOARD_DESIGN_SETTINGS class functions */
 /***************************************************************************/
 #include "fctsys.h"
 #include "common.h"
@@ -9,7 +9,7 @@
 
 
 /*****************************************************/
-EDA_BoardDesignSettings::EDA_BoardDesignSettings()
+BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS()
 /*****************************************************/
 
 // Default values for designing boards
@@ -40,11 +40,13 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
                                                         // The final margin is the sum of these 2 values
                                                         // Usually < 0 because the mask is smaller than pad
 
+    m_BoardThickness = 1.6 * PCB_INTERNAL_UNIT / 25.4;  // Epoxy thickness for 3D view (and microwave calculations)                               // Layer Thickness for 3D viewer
+
 }
 
 
 // see pcbstruct.h
-int EDA_BoardDesignSettings::GetVisibleLayers() const
+int BOARD_DESIGN_SETTINGS::GetVisibleLayers() const
 {
     return m_VisibleLayers;
 }
@@ -55,20 +57,20 @@ int EDA_BoardDesignSettings::GetVisibleLayers() const
  * Set the bit-mask of all visible elements categories,
  * including enabled layers
  */
-void EDA_BoardDesignSettings::SetVisibleAlls( )
+void BOARD_DESIGN_SETTINGS::SetVisibleAlls( )
 {
     SetVisibleLayers( FULL_LAYERS );
     m_VisibleElements = 0xFFFFFFFF;
 }
 
-void EDA_BoardDesignSettings::SetVisibleLayers( int aMask )
+void BOARD_DESIGN_SETTINGS::SetVisibleLayers( int aMask )
 {
     // Although Pcbnew uses only 29, Gerbview uses all 32 layers
     m_VisibleLayers = aMask & m_EnabledLayers & FULL_LAYERS;
 }
 
 
-void EDA_BoardDesignSettings::SetLayerVisibility( int aLayerIndex, bool aNewState )
+void BOARD_DESIGN_SETTINGS::SetLayerVisibility( int aLayerIndex, bool aNewState )
 {
     // Altough Pcbnew uses only 29, Gerbview uses all 32 layers
     if( aLayerIndex < 0 || aLayerIndex >= 32 )
@@ -80,7 +82,7 @@ void EDA_BoardDesignSettings::SetLayerVisibility( int aLayerIndex, bool aNewStat
 }
 
 
-void EDA_BoardDesignSettings::SetElementVisibility( int aElementCategory, bool aNewState )
+void BOARD_DESIGN_SETTINGS::SetElementVisibility( int aElementCategory, bool aNewState )
 {
     if( aElementCategory < 0 || aElementCategory >= END_PCB_VISIBLE_LIST )
         return;
@@ -91,7 +93,7 @@ void EDA_BoardDesignSettings::SetElementVisibility( int aElementCategory, bool a
 }
 
 
-void EDA_BoardDesignSettings::SetCopperLayerCount( int aNewLayerCount )
+void BOARD_DESIGN_SETTINGS::SetCopperLayerCount( int aNewLayerCount )
 {
     // if( aNewLayerCount < 2 ) aNewLayerCount = 2;
 
@@ -113,7 +115,7 @@ void EDA_BoardDesignSettings::SetCopperLayerCount( int aNewLayerCount )
  * changes the bit-mask of enabled layers
  * @param aMask = The new bit-mask of enabled layers
  */
-void EDA_BoardDesignSettings::SetEnabledLayers( int aMask )
+void BOARD_DESIGN_SETTINGS::SetEnabledLayers( int aMask )
 {
     // Back and front layers are always enabled.
     aMask |= LAYER_BACK | LAYER_FRONT;

pcbnew/class_dimension.cpp

@@ -33,7 +33,7 @@ COTATION::~COTATION()
 
 
 /* Setup the dimension text */
-void COTATION:: SetText( const wxString& NewText )
+void COTATION::SetText( const wxString& NewText )
 {
     m_Text->m_Text = NewText;
 }
@@ -421,10 +421,11 @@ void COTATION::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
 
     m_Text->Draw( panel, DC, mode_color, offset );
 
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false )
+    BOARD * brd =  GetBoard( );
+    if( brd->IsLayerVisible( m_Layer ) == false )
         return;
 
-    gcolor = g_ColorsSettings.GetLayerColor(m_Layer);
+    gcolor = brd->GetLayerColor(m_Layer);
 
     GRSetDrawMode( DC, mode_color );
     typeaff = DisplayOpt.DisplayDrawItems;

pcbnew/class_dimension.h

@@ -28,15 +28,11 @@ public:
     COTATION( BOARD_ITEM* aParent );
     ~COTATION();
 
-    COTATION* Next() const { return (COTATION*) Pnext; }
-    COTATION* Back() const { return (COTATION*) Pback; }
-
     wxPoint& GetPosition()
     {
         return m_Pos;
     }
 
-
     /**
      * Function SetLayer
      * sets the layer this item is on.

pcbnew/class_drawsegment.cpp

@@ -236,10 +236,11 @@ void DRAWSEGMENT::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
     int color, mode;
     int rayon;
 
-    if( g_DesignSettings.IsLayerVisible( GetLayer() ) == false )
+    BOARD * brd =  GetBoard( );
+    if( brd->IsLayerVisible( GetLayer() ) == false )
         return;
 
-    color = g_ColorsSettings.GetLayerColor(GetLayer());
+    color = brd->GetLayerColor(GetLayer());
 
     GRSetDrawMode( DC, draw_mode );
     l_piste = m_Width >> 1;  /* half trace width */

pcbnew/class_edge_mod.cpp

@@ -160,15 +160,16 @@ void EDGE_MODULE::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
     int                  typeaff;
     PCB_SCREEN*          screen;
     WinEDA_BasePcbFrame* frame;
-    MODULE*              Module = NULL;
+    MODULE* module = (MODULE*) m_Parent;
 
-    if( m_Parent && ( m_Parent->Type() == TYPE_MODULE ) )
-        Module = (MODULE*) m_Parent;
+    if( module == NULL )
+        return;
 
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false )
+    BOARD * brd = GetBoard( );
+    if( brd->IsLayerVisible( m_Layer ) == false )
         return;
 
-    color = g_ColorsSettings.GetLayerColor(m_Layer);
+    color = brd->GetLayerColor(m_Layer);
 
     frame = (WinEDA_BasePcbFrame*) panel->GetParent();
 
@@ -264,15 +265,9 @@ void EDGE_MODULE::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
         {
             wxPoint& pt = points[ii];
 
-            if( Module )
-            {
-                RotatePoint( &pt.x, &pt.y, Module->m_Orient );
-                pt.x += Module->m_Pos.x;
-                pt.y += Module->m_Pos.y;
-            }
-
-            pt.x += m_Start0.x - offset.x;
-            pt.y += m_Start0.y - offset.y;
+            RotatePoint( &pt.x, &pt.y, module->m_Orient );
+            pt += module->m_Pos;
+            pt += m_Start0 - offset;
         }
 
         GRPoly( &panel->m_ClipBox, DC, points.size(), &points[0],

pcbnew/class_mire.cpp

@@ -107,10 +107,11 @@ void MIREPCB::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
     ox = m_Pos.x + offset.x;
     oy = m_Pos.y + offset.y;
 
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false )
+    BOARD * brd =  GetBoard( );
+    if( brd->IsLayerVisible( m_Layer ) == false )
         return;
 
-    gcolor = g_ColorsSettings.GetLayerColor(m_Layer);
+    gcolor = brd->GetLayerColor(m_Layer);
 
     GRSetDrawMode( DC, mode_color );
     typeaff = DisplayOpt.DisplayDrawItems;

pcbnew/class_module.cpp

@@ -59,7 +59,6 @@ MODULE::~MODULE()
     delete m_Value;
 }
 
-
 /* Draw the anchor cross (vertical)
  * Must be done after the pads, because drawing the hole will erase overwrite
  * every thing already drawn.
@@ -71,7 +70,7 @@ void MODULE::DrawAncre( WinEDA_DrawPanel* panel, wxDC* DC, const wxPoint& offset
 
     GRSetDrawMode( DC, draw_mode );
 
-    if( ((BOARD*)m_Parent)->IsElementVisible( ANCHOR_VISIBLE ) )
+    if( GetBoard()->IsElementVisible( ANCHOR_VISIBLE ) )
     {
         int color = g_ColorsSettings.GetItemColor(ANCHOR_VISIBLE);
         GRLine( &panel->m_ClipBox, DC,
@@ -192,18 +191,19 @@ void MODULE::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
         pad->Draw( panel, DC, draw_mode, offset );
     }
 
+    BOARD * brd = GetBoard();
 
     // Draws footprint anchor
     DrawAncre( panel, DC, offset, DIM_ANCRE_MODULE, draw_mode );
 
     /* Draw graphic items */
-    if( ((BOARD*)m_Parent)->IsElementVisible( MOD_REFERENCES_VISIBLE ) )
+    if( brd->IsElementVisible( MOD_REFERENCES_VISIBLE ) )
     {
         if( !(m_Reference->m_Flags & IS_MOVED) )
             m_Reference->Draw( panel, DC, draw_mode, offset );
     }
 
-    if( ((BOARD*)m_Parent)->IsElementVisible( MOD_VALUES_VISIBLE ) )
+    if( brd->IsElementVisible( MOD_VALUES_VISIBLE ) )
     {
         if( !(m_Value->m_Flags & IS_MOVED) )
             m_Value->Draw( panel, DC, draw_mode, offset );
@@ -826,7 +826,7 @@ void MODULE::DisplayInfo( WinEDA_DrawFrame* frame )
     char     bufcar[512], Line[512];
     bool     flag = FALSE;
     wxString msg;
-    BOARD*   board = (BOARD*) m_Parent;
+    BOARD*   board = GetBoard();
 
     frame->EraseMsgBox();
     if( frame->m_Ident != PCB_FRAME )
@@ -1043,7 +1043,7 @@ SEARCH_RESULT MODULE::Visit( INSPECTOR* inspector, const void* testData,
  */
 void MODULE::Show( int nestLevel, std::ostream& os )
 {
-    BOARD* board = (BOARD*) m_Parent;
+    BOARD* board = GetBoard();
 
     // for now, make it look like XML, expand on this later.
     NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() <<

pcbnew/class_module.h

@@ -140,7 +140,6 @@ public:
         return m_Pos;
     }
 
-
     // Moves
     void         SetPosition( const wxPoint& newpos );
     void         SetOrientation( int newangle );

pcbnew/class_netclass.cpp

@@ -31,6 +31,8 @@
 #include "pcbnew.h"
 #include "class_board_design_settings.h"
 
+// Current design settings (used also to read configs):
+extern BOARD_DESIGN_SETTINGS boardDesignSettings;
 
 // This will get mapped to "kicad_default" in the specctra_export.
 const wxString NETCLASS::Default = wxT("Default");
@@ -45,7 +47,7 @@ NETCLASS::NETCLASS( BOARD* aParent, const wxString& aName, const NETCLASS* initi
     m_Name( aName )
 {
     // use initialParameters if not NULL, else set the initial
-    // parameters from g_DesignSettings
+    // parameters from boardDesignSettings (try to change this)
     SetParams( initialParameters );
 }
 
@@ -62,8 +64,12 @@ void NETCLASS::SetParams( const NETCLASS* defaults )
         SetuViaDrill( defaults->GetuViaDrill() );
     }
     else
-    {
-        const EDA_BoardDesignSettings& g = g_DesignSettings;
+    {   // We should use m_Parent->GetBoardDesignSettings()
+        // But when the NETCLASSES constructor is called
+        // (it call NETCLASS constructor), the m_Parent constructor (see BOARD::BOARD)
+        // is not run, and GetBoardDesignSettings() return a bad value
+        // TODO: see how change that.
+        const BOARD_DESIGN_SETTINGS& g = boardDesignSettings;
 
         SetTrackWidth(  g.m_TrackMinWidth );
         SetViaDiameter( g.m_ViasMinSize );
@@ -401,27 +407,27 @@ bool NETCLASS::ReadDescr( FILE* aFile, int* aLineNum )
 
 int NETCLASS::GetTrackMinWidth() const
 {
-    return m_Parent->m_BoardSettings->m_TrackMinWidth;
+    return m_Parent->GetBoardDesignSettings()->m_TrackMinWidth;
 }
 
 int NETCLASS::GetViaMinDiameter() const
 {
-    return m_Parent->m_BoardSettings->m_ViasMinSize;
+    return m_Parent->GetBoardDesignSettings()->m_ViasMinSize;
 }
 
 int NETCLASS::GetViaMinDrill() const
 {
-    return m_Parent->m_BoardSettings->m_ViasMinDrill;
+    return m_Parent->GetBoardDesignSettings()->m_ViasMinDrill;
 }
 
 int NETCLASS::GetuViaMinDiameter() const
 {
-    return m_Parent->m_BoardSettings->m_MicroViasMinSize;
+    return m_Parent->GetBoardDesignSettings()->m_MicroViasMinSize;
 }
 
 int NETCLASS::GetuViaMinDrill() const
 {
-    return m_Parent->m_BoardSettings->m_MicroViasMinDrill;
+    return m_Parent->GetBoardDesignSettings()->m_MicroViasMinDrill;
 }
 
 

pcbnew/class_netclass.h

@@ -75,7 +75,8 @@ public:
      * Name of identifier within BOARD file.
      * 08-Sept-2009: changed the name from "NETCLASS" to this so we can
      * toss any previous NETCLASSes in migratory BOARD files which will not have
-     * the proper parameters in the default netclass (from g_DesignSettings) in them.
+     * the proper parameters in the default netclass
+     * (from m_Parent->m_designSettings) in them.
      * Spare the user from having to enter those defaults manually.
      */
 #define BRD_NETCLASS  "NCLASS"

pcbnew/class_netinfo.h

@@ -237,21 +237,6 @@ public:
         return m_NetClass->GetTrackWidth();
     }
 
-
-#if 0
-
-    /**
-     * Function GetTrackMinWidth
-     * returns the Minimum value for tracks thickness (used in DRC)
-     */
-    int GetTrackMinWidth()
-    {
-        return g_DesignSettings.m_TrackMinWidth;
-    }
-
-
-#endif
-
     /**
      * Function GetViaSize
      * returns the size of vias used to route this net

pcbnew/class_pad.cpp

@@ -247,14 +247,20 @@ int D_PAD::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const
 int D_PAD::GetSolderMaskMargin()
 {
     int margin = m_LocalSolderMaskMargin;
-
+    MODULE * module = (MODULE*) GetParent();
+    if( module )
+    {
         if( margin == 0 )
         {
-        if( GetParent() && ( (MODULE*) GetParent() )->m_LocalSolderMaskMargin )
-            margin = ( (MODULE*) GetParent() )->m_LocalSolderMaskMargin;
+            if( module->m_LocalSolderMaskMargin )
+                margin = module->m_LocalSolderMaskMargin;
         }
         if( margin == 0 )
-        margin = g_DesignSettings.m_SolderMaskMargin;
+        {
+            BOARD * brd = GetBoard();
+            margin = brd->GetBoardDesignSettings()->m_SolderMaskMargin;
+        }
+    }
 
     // ensure mask have a size always >= 0
     if( margin < 0 )
@@ -278,17 +284,25 @@ int D_PAD::GetSolderMaskMargin()
 wxSize D_PAD::GetSolderPasteMargin()
 {
     int margin = m_LocalSolderPasteMargin;
+    double mratio = m_LocalSolderPasteMarginRatio;
+    MODULE * module = (MODULE*) GetParent();
 
-    if( margin == 0  && GetParent() )
-        margin = ( (MODULE*) GetParent() )->m_LocalSolderPasteMargin;
-    if( margin == 0  && GetParent() )
-        margin = g_DesignSettings.m_SolderPasteMargin;
+    if( module )
+    {
+        if( margin == 0  )
+            margin = module->m_LocalSolderPasteMargin;
+
+        BOARD * brd = GetBoard();
+        if( margin == 0  )
+            margin = brd->GetBoardDesignSettings()->m_SolderPasteMargin;
 
-    double mratio = m_LocalSolderPasteMarginRatio;
-    if( mratio == 0.0 && GetParent() )
-        mratio = ( (MODULE*) GetParent() )->m_LocalSolderPasteMarginRatio;
         if( mratio == 0.0 )
-        mratio = g_DesignSettings.m_SolderPasteMarginRatio;
+            mratio = module->m_LocalSolderPasteMarginRatio;
+        if( mratio == 0.0 )
+        {
+           mratio = brd->GetBoardDesignSettings()->m_SolderPasteMarginRatio;
+        }
+    }
 
     wxSize pad_margin;
     pad_margin.x = margin + wxRound( m_Size.x * mratio );

pcbnew/class_pad_draw_functions.cpp

@@ -59,8 +59,9 @@ void D_PAD::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
     (LAYER_FRONT | ADHESIVE_LAYER_FRONT | SOLDERPASTE_LAYER_FRONT\
     | SILKSCREEN_LAYER_FRONT | SOLDERMASK_LAYER_FRONT)
 
-    bool frontVisible = g_DesignSettings.IsElementVisible( PCB_VISIBLE(PAD_FR_VISIBLE) );
-    bool backVisible = g_DesignSettings.IsElementVisible( PCB_VISIBLE(PAD_BK_VISIBLE) );
+    BOARD * brd =  GetBoard( );
+    bool frontVisible = brd->IsElementVisible( PCB_VISIBLE(PAD_FR_VISIBLE) );
+    bool backVisible = brd->IsElementVisible( PCB_VISIBLE(PAD_BK_VISIBLE) );
 
     if( !frontVisible && !backVisible )
         return;
@@ -90,12 +91,12 @@ void D_PAD::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
 
     if( m_Masque_Layer & LAYER_FRONT )
     {
-            color = g_ColorsSettings.GetItemColor(PAD_FR_VISIBLE);
+            color = brd->GetVisibleElementColor(PAD_FR_VISIBLE);
     }
 
     if( m_Masque_Layer & LAYER_BACK )
     {
-        color |= g_ColorsSettings.GetItemColor(PAD_BK_VISIBLE);
+        color |= brd->GetVisibleElementColor(PAD_BK_VISIBLE);
     }
 
     if( color == 0 ) /* Not on copper layer */
@@ -105,55 +106,55 @@ void D_PAD::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
         switch( m_Masque_Layer & ~ALL_CU_LAYERS )
         {
         case ADHESIVE_LAYER_BACK:
-            color = g_ColorsSettings.GetLayerColor(ADHESIVE_N_BACK);
+            color = brd->GetLayerColor(ADHESIVE_N_BACK);
             break;
 
         case ADHESIVE_LAYER_FRONT:
-            color = g_ColorsSettings.GetLayerColor(ADHESIVE_N_FRONT);
+            color = brd->GetLayerColor(ADHESIVE_N_FRONT);
             break;
 
         case SOLDERPASTE_LAYER_BACK:
-            color = g_ColorsSettings.GetLayerColor(SOLDERPASTE_N_BACK);
+            color = brd->GetLayerColor(SOLDERPASTE_N_BACK);
             break;
 
         case SOLDERPASTE_LAYER_FRONT:
-            color = g_ColorsSettings.GetLayerColor(SOLDERPASTE_N_FRONT);
+            color = brd->GetLayerColor(SOLDERPASTE_N_FRONT);
             break;
 
         case SILKSCREEN_LAYER_BACK:
-            color = g_ColorsSettings.GetLayerColor(SILKSCREEN_N_BACK);
+            color = brd->GetLayerColor(SILKSCREEN_N_BACK);
             break;
 
         case SILKSCREEN_LAYER_FRONT:
-            color = g_ColorsSettings.GetLayerColor(SILKSCREEN_N_FRONT);
+            color = brd->GetLayerColor(SILKSCREEN_N_FRONT);
             break;
 
         case SOLDERMASK_LAYER_BACK:
-            color = g_ColorsSettings.GetLayerColor(SOLDERMASK_N_BACK);
+            color = brd->GetLayerColor(SOLDERMASK_N_BACK);
             break;
 
         case SOLDERMASK_LAYER_FRONT:
-            color = g_ColorsSettings.GetLayerColor(SOLDERMASK_N_FRONT);
+            color = brd->GetLayerColor(SOLDERMASK_N_FRONT);
             break;
 
         case DRAW_LAYER:
-            color = g_ColorsSettings.GetLayerColor(DRAW_N);
+            color = brd->GetLayerColor(DRAW_N);
             break;
 
         case COMMENT_LAYER:
-            color = g_ColorsSettings.GetLayerColor(COMMENT_N);
+            color = brd->GetLayerColor(COMMENT_N);
             break;
 
         case ECO1_LAYER:
-            color = g_ColorsSettings.GetLayerColor(ECO1_N);
+            color = brd->GetLayerColor(ECO1_N);
             break;
 
         case ECO2_LAYER:
-            color = g_ColorsSettings.GetLayerColor(ECO2_N);
+            color = brd->GetLayerColor(ECO2_N);
             break;
 
         case EDGE_LAYER:
-            color = g_ColorsSettings.GetLayerColor(EDGE_N);
+            color = brd->GetLayerColor(EDGE_N);
             break;
 
         default:
@@ -218,7 +219,7 @@ void D_PAD::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
     {
         if( IsOnLayer( screen->m_Active_Layer ) )
         {
-            color = g_ColorsSettings.GetLayerColor(screen->m_Active_Layer);
+            color = brd->GetLayerColor(screen->m_Active_Layer);
 
             // In hight contrast mode, and if the active layer is the mask
             // layer shows the pad size with the mask clearance
@@ -470,7 +471,7 @@ void D_PAD::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
     GRSetDrawMode( DC, draw_mode );
 
     /* Draw "No connect" ( / or \ or cross X ) if necessary. : */
-    if( m_Netname.IsEmpty() && g_DesignSettings.IsElementVisible( PCB_VISIBLE(NO_CONNECTS_VISIBLE) ) )
+    if( m_Netname.IsEmpty() && brd->IsElementVisible( PCB_VISIBLE(NO_CONNECTS_VISIBLE) ) )
     {
         dx0 = MIN( dx0, dy0 );
         int nc_color = BLUE;

pcbnew/class_pcb_text.cpp

@@ -188,18 +188,20 @@ bool TEXTE_PCB::Save( FILE* aFile ) const
 void TEXTE_PCB::Draw( WinEDA_DrawPanel* panel, wxDC* DC,
                       int DrawMode, const wxPoint& offset )
 {
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false )
+    BOARD * brd =  GetBoard( );
+
+    if( brd->IsLayerVisible( m_Layer ) == false )
         return;
 
-    int color = g_ColorsSettings.GetLayerColor(m_Layer);
+    int color = brd->GetLayerColor(m_Layer);
 
     GRTraceMode fillmode = FILLED;
     if ( DisplayOpt.DisplayDrawItems == SKETCH)
         fillmode = SKETCH;
 
     int anchor_color = UNSPECIFIED_COLOR;
-    if( g_DesignSettings.IsElementVisible( ANCHOR_VISIBLE ) )
-        anchor_color = g_ColorsSettings.GetItemColor(ANCHOR_VISIBLE);
+    if( brd->IsElementVisible( ANCHOR_VISIBLE ) )
+        anchor_color = brd->GetVisibleElementColor(ANCHOR_VISIBLE);
 
     EDA_TextStruct::Draw( panel, DC, offset, (EDA_Colors) color,
                           DrawMode, fillmode, (EDA_Colors) anchor_color );

pcbnew/class_text_mod.cpp

@@ -363,9 +363,10 @@ void TEXTE_MODULE::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
 
     GRSetDrawMode( DC, draw_mode );
 
-    if( g_DesignSettings.IsElementVisible( ANCHOR_VISIBLE ) )
+    BOARD * brd =  GetBoard( );
+    if( brd->IsElementVisible( ANCHOR_VISIBLE ) )
     {
-        color = g_ColorsSettings.GetItemColor(ANCHOR_VISIBLE);
+        color = brd->GetVisibleElementColor(ANCHOR_VISIBLE);
         int anchor_size = screen->Unscale( 2 );
         GRLine( &panel->m_ClipBox, DC,
                 pos.x - anchor_size, pos.y,
@@ -375,27 +376,27 @@ void TEXTE_MODULE::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode,
                 pos.x, pos.y + anchor_size, 0, color );
     }
 
-    color = g_ColorsSettings.GetLayerColor(Module->GetLayer());
+    color = brd->GetLayerColor(Module->GetLayer());
 
 
     if( Module->GetLayer() == LAYER_N_BACK )
     {
-        if( g_DesignSettings.IsElementVisible( MOD_TEXT_BK_VISIBLE ) == false )
+        if( brd->IsElementVisible( MOD_TEXT_BK_VISIBLE ) == false )
             return;
-        color = g_ColorsSettings.GetItemColor(MOD_TEXT_BK_VISIBLE);
+        color = brd->GetVisibleElementColor(MOD_TEXT_BK_VISIBLE);
     }
     else if( Module->GetLayer() == LAYER_N_FRONT )
     {
-        if( g_DesignSettings.IsElementVisible( MOD_TEXT_FR_VISIBLE ) == false )
+        if( brd->IsElementVisible( MOD_TEXT_FR_VISIBLE ) == false )
             return;
-        color = g_ColorsSettings.GetItemColor(MOD_TEXT_FR_VISIBLE);
+        color = brd->GetVisibleElementColor(MOD_TEXT_FR_VISIBLE);
     }
 
     if( m_NoShow )
     {
-        if( g_DesignSettings.IsElementVisible( MOD_TEXT_INVISIBLE ) == false )
+        if( brd->IsElementVisible( MOD_TEXT_INVISIBLE ) == false )
             return;
-        color = g_ColorsSettings.GetItemColor(MOD_TEXT_INVISIBLE);
+        color = brd->GetVisibleElementColor(MOD_TEXT_INVISIBLE);
     }
 
     /* If the text is mirrored : negate size.x (mirror / Y axis) */

pcbnew/class_track.cpp

@@ -550,6 +550,7 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode, const wxPoin
     if( Type() == TYPE_ZONE && DisplayOpt.DisplayZonesMode != 0 )
         return;
 
+    BOARD * brd =  GetBoard( );
     if( m_Flags & DRAW_ERASED )   // draw in background color, used by classs TRACK in gerbview
     {
         color = g_DrawBgColor;
@@ -558,9 +559,9 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode, const wxPoin
     }
     else
     {
-        color = g_ColorsSettings.GetLayerColor(m_Layer);
+        color = brd->GetLayerColor(m_Layer);
 
-        if( g_DesignSettings.IsLayerVisible( m_Layer ) == false && ( color & HIGHT_LIGHT_FLAG ) !=
+        if( brd->IsLayerVisible( m_Layer ) == false && ( color & HIGHT_LIGHT_FLAG ) !=
             HIGHT_LIGHT_FLAG )
             return;
 
@@ -724,9 +725,10 @@ void SEGVIA::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode, const wxPoi
 
     GRSetDrawMode( DC, draw_mode );
 
-    color = g_ColorsSettings.GetItemColor(VIAS_VISIBLE + m_Shape);
+    BOARD * brd =  GetBoard( );
+    color = brd->GetVisibleElementColor(VIAS_VISIBLE + m_Shape);
 
-    if( g_DesignSettings.IsElementVisible( PCB_VISIBLE(VIAS_VISIBLE + m_Shape) ) == false
+    if( brd->IsElementVisible( PCB_VISIBLE(VIAS_VISIBLE + m_Shape) ) == false
         && ( color & HIGHT_LIGHT_FLAG ) != HIGHT_LIGHT_FLAG )
         return;
 
@@ -864,15 +866,15 @@ void SEGVIA::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode, const wxPoi
         ( (SEGVIA*) this )->ReturnLayerPair( &layer_top, &layer_bottom );
 
         /* lines for the top layer */
-        RotatePoint( &ax, &ay, layer_top * 3600 / g_DesignSettings.GetCopperLayerCount( ) );
-        RotatePoint( &bx, &by, layer_top * 3600 / g_DesignSettings.GetCopperLayerCount( ) );
+        RotatePoint( &ax, &ay, layer_top * 3600 / brd->GetCopperLayerCount( ) );
+        RotatePoint( &bx, &by, layer_top * 3600 / brd->GetCopperLayerCount( ) );
         GRLine( &panel->m_ClipBox, DC, m_Start.x - ax, m_Start.y - ay,
                 m_Start.x - bx, m_Start.y - by, 0, color );
 
         /* lines for the bottom layer */
         ax = 0; ay = rayon; bx = 0; by = drill_rayon;
-        RotatePoint( &ax, &ay, layer_bottom * 3600 / g_DesignSettings.GetCopperLayerCount( ) );
-        RotatePoint( &bx, &by, layer_bottom * 3600 / g_DesignSettings.GetCopperLayerCount( ) );
+        RotatePoint( &ax, &ay, layer_bottom * 3600 / brd->GetCopperLayerCount( ) );
+        RotatePoint( &bx, &by, layer_bottom * 3600 / brd->GetCopperLayerCount( ) );
         GRLine( &panel->m_ClipBox, DC, m_Start.x - ax, m_Start.y - ay,
                 m_Start.x - bx, m_Start.y - by, 0, color );
     }

pcbnew/class_zone.cpp

@@ -444,9 +444,11 @@ void ZONE_CONTAINER::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode, con
 
     wxPoint seg_start, seg_end;
     int     curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
-    int     color = g_ColorsSettings.GetLayerColor(m_Layer);
 
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false &&
+    BOARD * brd =  GetBoard( );
+    int     color = brd->GetLayerColor(m_Layer);
+
+    if( brd->IsLayerVisible( m_Layer ) == false &&
         ( color & HIGHT_LIGHT_FLAG ) != HIGHT_LIGHT_FLAG )
         return;
 
@@ -532,10 +534,11 @@ void ZONE_CONTAINER::DrawFilledArea( WinEDA_DrawPanel* panel,
     if( m_FilledPolysList.size() == 0 )  // Nothing to draw
         return;
 
+    BOARD * brd =  GetBoard( );
     int curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
-    int color = g_ColorsSettings.GetLayerColor(m_Layer);
+    int color = brd->GetLayerColor(m_Layer);
 
-    if( g_DesignSettings.IsLayerVisible( m_Layer ) == false && ( color & HIGHT_LIGHT_FLAG ) != HIGHT_LIGHT_FLAG )
+    if( brd->IsLayerVisible( m_Layer ) == false && ( color & HIGHT_LIGHT_FLAG ) != HIGHT_LIGHT_FLAG )
         return;
 
     GRSetDrawMode( DC, aDrawMode );
@@ -687,7 +690,8 @@ void ZONE_CONTAINER::DrawWhileCreateOutline( WinEDA_DrawPanel* panel, wxDC* DC,
     if( DC == NULL )
         return;
     int     curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
-    int     color = g_ColorsSettings.GetLayerColor(m_Layer) & MASKCOLOR;
+    BOARD * brd =  GetBoard( );
+    int     color = brd->GetLayerColor(m_Layer) & MASKCOLOR;
 
     if( DisplayOpt.ContrastModeDisplay )
     {

pcbnew/classpcb.cpp

@@ -109,30 +109,6 @@ int PCB_SCREEN::GetInternalUnits( void )
 }
 
 
-/* Return true if a microvia can be put on board
- * A microvia ia a small via restricted to 2 near neighbour layers
- * because its is hole is made by laser which can penetrate only one layer
- * It is mainly used to connect BGA to the first inner layer
- * And it is allowed from an external layer to the first inner layer
- */
-bool PCB_SCREEN::IsMicroViaAcceptable( void )
-{
-    int copperlayercnt = g_DesignSettings.GetCopperLayerCount( );
-
-    if( !g_DesignSettings.m_MicroViasAllowed )
-        return false;   // Obvious..
-    if( copperlayercnt < 4 )
-        return false;   // Only on multilayer boards..
-    if( ( m_Active_Layer == LAYER_N_BACK )
-       || ( m_Active_Layer == LAYER_N_FRONT )
-       || ( m_Active_Layer == g_DesignSettings.GetCopperLayerCount( ) - 2 )
-       || ( m_Active_Layer == LAYER_N_2 ) )
-        return true;
-
-    return false;
-}
-
-
 /*************************/
 /* class DISPLAY_OPTIONS */
 /*************************/

pcbnew/collectors.h

@@ -356,7 +356,7 @@ public:
      * Constructor GENERAL_COLLECTORS_GUIDE
      * grabs stuff from global preferences and uses reasonable defaults.
      * Add more constructors as needed.
-     * @param settings The EDA_BoardDesignSettings to reference.
+     * @param settings The BOARD_DESIGN_SETTINGS to reference.
      */
     GENERAL_COLLECTORS_GUIDE( int aVisibleLayerMask, int aPreferredLayer )
     {

pcbnew/dialog_design_rules.cpp

@@ -156,15 +156,15 @@ void DIALOG_DESIGN_RULES::PrintCurrentSettings( )
     m_MessagesList->AppendToPage(_("<b>Current general settings:</b><br>") );
 
     // Display min values:
-    value = ReturnStringFromValue( g_UnitMetric, g_DesignSettings.m_TrackMinWidth, internal_units, true );
+    value = ReturnStringFromValue( g_UnitMetric, m_BrdSettings->m_TrackMinWidth, internal_units, true );
     msg.Printf(_("Minimum value for tracks width: <b>%s</b><br>\n"), GetChars( value ) );
     m_MessagesList->AppendToPage(msg);
 
-    value = ReturnStringFromValue( g_UnitMetric, g_DesignSettings.m_ViasMinSize, internal_units, true );
+    value = ReturnStringFromValue( g_UnitMetric,  m_BrdSettings->m_ViasMinSize, internal_units, true );
     msg.Printf(_("Minimum value for vias diameter: <b>%s</b><br>\n"), GetChars( value ) );
     m_MessagesList->AppendToPage(msg);
 
-    value = ReturnStringFromValue( g_UnitMetric, g_DesignSettings.m_MicroViasMinSize, internal_units, true );
+    value = ReturnStringFromValue( g_UnitMetric,  m_BrdSettings->m_MicroViasMinSize, internal_units, true );
     msg.Printf(_("Minimum value for microvias diameter: <b>%s</b><br>\n"), GetChars( value ) );
     m_MessagesList->AppendToPage(msg);
 
@@ -178,8 +178,8 @@ void DIALOG_DESIGN_RULES::InitDialogRules()
     SetFocus();
     SetReturnCode( 0 );
 
-    // Initialize the layers grid:
     m_Pcb = m_Parent->GetBoard();
+    m_BrdSettings = m_Pcb->GetBoardDesignSettings();
 
     // Initialize the Rules List
     InitRulesList();
@@ -229,17 +229,17 @@ void DIALOG_DESIGN_RULES::InitGlobalRules()
     AddUnitSymbol( *m_TrackMinWidthTitle );
 
     int Internal_Unit = m_Parent->m_InternalUnits;
-    PutValueInLocalUnits( *m_SetViasMinSizeCtrl, g_DesignSettings.m_ViasMinSize, Internal_Unit );
-    PutValueInLocalUnits( *m_SetViasMinDrillCtrl, g_DesignSettings.m_ViasMinDrill, Internal_Unit );
+    PutValueInLocalUnits( *m_SetViasMinSizeCtrl,  m_BrdSettings->m_ViasMinSize, Internal_Unit );
+    PutValueInLocalUnits( *m_SetViasMinDrillCtrl,  m_BrdSettings->m_ViasMinDrill, Internal_Unit );
 
-    if( g_DesignSettings.m_CurrentViaType != VIA_THROUGH )
+    if(  m_BrdSettings->m_CurrentViaType != VIA_THROUGH )
         m_OptViaType->SetSelection( 1 );
 
-    m_AllowMicroViaCtrl->SetSelection( g_DesignSettings.m_MicroViasAllowed ? 1 : 0);
-    PutValueInLocalUnits( *m_SetMicroViasMinSizeCtrl, g_DesignSettings.m_MicroViasMinSize, Internal_Unit );
-    PutValueInLocalUnits( *m_SetMicroViasMinDrillCtrl, g_DesignSettings.m_MicroViasMinDrill, Internal_Unit );
+    m_AllowMicroViaCtrl->SetSelection(  m_BrdSettings->m_MicroViasAllowed ? 1 : 0);
+    PutValueInLocalUnits( *m_SetMicroViasMinSizeCtrl,  m_BrdSettings->m_MicroViasMinSize, Internal_Unit );
+    PutValueInLocalUnits( *m_SetMicroViasMinDrillCtrl,  m_BrdSettings->m_MicroViasMinDrill, Internal_Unit );
 
-    PutValueInLocalUnits( *m_SetTrackMinWidthCtrl, g_DesignSettings.m_TrackMinWidth, Internal_Unit );
+    PutValueInLocalUnits( *m_SetTrackMinWidthCtrl,  m_BrdSettings->m_TrackMinWidth, Internal_Unit );
 
     // Initialize Vias and Tracks sizes lists.
     // note we display only extra values, never the current netclass value.
@@ -529,26 +529,26 @@ void DIALOG_DESIGN_RULES::CopyRulesListToBoard()
 void DIALOG_DESIGN_RULES::CopyGlobalRulesToBoard()
 /*************************************************/
 {
-    g_DesignSettings.m_CurrentViaType = VIA_THROUGH;
+     m_BrdSettings->m_CurrentViaType = VIA_THROUGH;
     if( m_OptViaType->GetSelection() > 0 )
-        g_DesignSettings.m_CurrentViaType = VIA_BLIND_BURIED;
+         m_BrdSettings->m_CurrentViaType = VIA_BLIND_BURIED;
 
     // Update vias minimum values for DRC
-    g_DesignSettings.m_ViasMinSize =
+     m_BrdSettings->m_ViasMinSize =
         ReturnValueFromTextCtrl( *m_SetViasMinSizeCtrl, m_Parent->m_InternalUnits );
-    g_DesignSettings.m_ViasMinDrill =
+     m_BrdSettings->m_ViasMinDrill =
         ReturnValueFromTextCtrl( *m_SetViasMinDrillCtrl, m_Parent->m_InternalUnits );
 
-    g_DesignSettings.m_MicroViasAllowed = m_AllowMicroViaCtrl->GetSelection() == 1;
+     m_BrdSettings->m_MicroViasAllowed = m_AllowMicroViaCtrl->GetSelection() == 1;
 
     // Update microvias minimum values for DRC
-    g_DesignSettings.m_MicroViasMinSize =
+     m_BrdSettings->m_MicroViasMinSize =
         ReturnValueFromTextCtrl( *m_SetMicroViasMinSizeCtrl, m_Parent->m_InternalUnits );
-    g_DesignSettings.m_MicroViasMinDrill =
+     m_BrdSettings->m_MicroViasMinDrill =
         ReturnValueFromTextCtrl( *m_SetMicroViasMinDrillCtrl, m_Parent->m_InternalUnits );
 
     // Update tracks minimum values for DRC
-    g_DesignSettings.m_TrackMinWidth =
+     m_BrdSettings->m_TrackMinWidth =
         ReturnValueFromTextCtrl( *m_SetTrackMinWidthCtrl, m_Parent->m_InternalUnits );
 }
 

pcbnew/dialog_design_rules.h

@@ -33,6 +33,7 @@ private:
 
     WinEDA_PcbFrame*        m_Parent;
     BOARD*                  m_Pcb;
+    BOARD_DESIGN_SETTINGS*  m_BrdSettings;
 
     static int              s_LastTabSelection;     ///< which tab user had open last
 

pcbnew/dialog_drc.cpp

@@ -28,6 +28,7 @@ DIALOG_DRC_CONTROL::DIALOG_DRC_CONTROL( DRC* aTester, WinEDA_PcbFrame* parent )
 {
     m_tester = aTester;
     m_Parent = parent;
+    m_BrdSettings = m_Parent->GetBoard()->GetBoardDesignSettings();
 
     InitValues();
     if( GetSizer() )
@@ -118,11 +119,11 @@ void DIALOG_DRC_CONTROL::InitValues()
 */
 void DIALOG_DRC_CONTROL::SetDrcParmeters( )
 {
-    g_DesignSettings.m_TrackMinWidth =
+     m_BrdSettings->m_TrackMinWidth =
         ReturnValueFromTextCtrl( *m_SetTrackMinWidthCtrl, m_Parent->m_InternalUnits );
-    g_DesignSettings.m_ViasMinSize =
+     m_BrdSettings->m_ViasMinSize =
         ReturnValueFromTextCtrl( *m_SetViaMinSizeCtrl, m_Parent->m_InternalUnits );
-    g_DesignSettings.m_MicroViasMinSize =
+     m_BrdSettings->m_MicroViasMinSize =
         ReturnValueFromTextCtrl( *m_SetMicroViakMinSizeCtrl, m_Parent->m_InternalUnits );
 }
 

pcbnew/dialog_drc.h

@@ -38,6 +38,8 @@ class DRCLISTBOX;
 class DIALOG_DRC_CONTROL: public DIALOG_DRC_CONTROL_BASE
 {
 public:
+    BOARD_DESIGN_SETTINGS*  m_BrdSettings;
+
     /// Constructors
     DIALOG_DRC_CONTROL( DRC* aTester, WinEDA_PcbFrame* parent );
     ~DIALOG_DRC_CONTROL(){};

pcbnew/dialog_edit_module_for_BoardEditor.cpp

@@ -119,12 +119,12 @@ void DIALOG_MODULE_BOARD_EDITOR::InitBoardProperties()
     if( m_CurrentModule->m_LocalSolderPasteMargin == 0 )
         m_SolderPasteMarginCtrl->SetValue( wxT( "-" ) +
                                            m_SolderPasteMarginCtrl->GetValue() );
-    if( m_CurrentModule->m_LocalSolderPasteMarginRatio == 0.0 )
-        msg.Printf( wxT( "-%.1f" ),
-                    m_CurrentModule->m_LocalSolderPasteMarginRatio * 100.0 );
-    else
     msg.Printf( wxT( "%.1f" ),
                     m_CurrentModule->m_LocalSolderPasteMarginRatio * 100.0 );
+    if( m_CurrentModule->m_LocalSolderPasteMarginRatio == 0.0 &&
+        msg[0] == '0')  // Sometimes Printf add a sign if the value is small
+        m_SolderPasteMarginRatioCtrl->SetValue( wxT("-") + msg );
+    else
         m_SolderPasteMarginRatioCtrl->SetValue( msg );
 }
 
@@ -460,14 +460,15 @@ void DIALOG_MODULE_BOARD_EDITOR::OnOkClick( wxCommandEvent& event )
     m_CurrentModule->m_LocalSolderPasteMargin =
         ReturnValueFromTextCtrl( *m_SolderPasteMarginCtrl,
                                  m_Parent->m_InternalUnits );
-    double dtmp;
+    double dtmp = 0.0;
     msg = m_SolderPasteMarginRatioCtrl->GetValue();
     msg.ToDouble( &dtmp );
 
-    // A margin ratio de -50% means no paste on a pad, the ratio must be >= 50
-    // %
+    // A margin ratio de -50% means no paste on a pad, the ratio must be >= 50%
     if( dtmp < -50 )
         dtmp = -50;
+    if( dtmp > +100 )
+        dtmp = +100;
     m_CurrentModule->m_LocalSolderPasteMarginRatio = dtmp / 100;
 
     // Set Module Position

pcbnew/dialog_graphic_item_properties.cpp

@@ -29,6 +29,7 @@ private:
     WinEDA_PcbFrame* m_Parent;
     wxDC* m_DC;
     DRAWSEGMENT* m_Item;
+    BOARD_DESIGN_SETTINGS*  m_BrdSettings;
 
 public:
     DialogGraphicItemProperties( WinEDA_PcbFrame* aParent, DRAWSEGMENT * aItem, wxDC * aDC);
@@ -47,6 +48,7 @@ DialogGraphicItemProperties::DialogGraphicItemProperties( WinEDA_PcbFrame* aPare
     m_Parent = aParent;
     m_DC = aDC;
     m_Item = aItem;
+    m_BrdSettings = m_Parent->GetBoard()->GetBoardDesignSettings();
     Init();
     Layout();
     GetSizer()->SetSizeHints( this );
@@ -130,9 +132,9 @@ void DialogGraphicItemProperties::Init( )
     AddUnitSymbol( *m_DefaultThicknessText );
     int thickness;
     if( m_Item->GetLayer() == EDGE_N )
-        thickness = g_DesignSettings.m_EdgeSegmentWidth;
+        thickness =  m_BrdSettings->m_EdgeSegmentWidth;
     else
-        thickness = g_DesignSettings.m_DrawSegmentWidth;
+        thickness =  m_BrdSettings->m_DrawSegmentWidth;
     PutValueInLocalUnits( *m_DefaultThicknessCtrl, thickness,
         m_Parent->m_InternalUnits );
 
@@ -159,9 +161,9 @@ void DialogGraphicItemProperties::OnLayerChoice( wxCommandEvent& event )
 {
     int thickness;
     if( (m_LayerSelection->GetCurrentSelection() + FIRST_NO_COPPER_LAYER) == EDGE_N )
-        thickness = g_DesignSettings.m_EdgeSegmentWidth;
+        thickness =  m_BrdSettings->m_EdgeSegmentWidth;
     else
-        thickness = g_DesignSettings.m_DrawSegmentWidth;
+        thickness =  m_BrdSettings->m_DrawSegmentWidth;
     PutValueInLocalUnits( *m_DefaultThicknessCtrl, thickness,
         m_Parent->m_InternalUnits );
 }
@@ -205,9 +207,9 @@ void DialogGraphicItemProperties::OnOkClick( wxCommandEvent& event )
     m_Item->SetLayer( m_LayerSelection->GetCurrentSelection() + FIRST_NO_COPPER_LAYER);
 
     if( m_Item->GetLayer() == EDGE_N )
-        g_DesignSettings.m_EdgeSegmentWidth = thickness;
+         m_BrdSettings->m_EdgeSegmentWidth = thickness;
     else
-        g_DesignSettings.m_DrawSegmentWidth = thickness;
+         m_BrdSettings->m_DrawSegmentWidth = thickness;
 
     if ( m_Item->m_Shape == S_ARC )
     {

pcbnew/dialog_graphic_items_options.cpp

@@ -25,26 +25,26 @@ void WinEDA_GraphicItemsOptionsDialog::SetDisplayValue()
     /* Drawings width */
     AddUnitSymbol( *m_GraphicSegmWidthTitle );
     PutValueInLocalUnits( *m_OptPcbSegmWidth,
-                          g_DesignSettings.m_DrawSegmentWidth,
+                           m_BrdSettings->m_DrawSegmentWidth,
                           PCB_INTERNAL_UNIT );
     /* Edges width */
     AddUnitSymbol( *m_BoardEdgesWidthTitle );
     PutValueInLocalUnits( *m_OptPcbEdgesWidth,
-                          g_DesignSettings.m_EdgeSegmentWidth,
+                           m_BrdSettings->m_EdgeSegmentWidth,
                           PCB_INTERNAL_UNIT );
 
     /* Pcb Textes (Size & Width) */
     AddUnitSymbol( *m_CopperTextWidthTitle );
     PutValueInLocalUnits( *m_OptPcbTextWidth,
-                          g_DesignSettings.m_PcbTextWidth, PCB_INTERNAL_UNIT );
+                           m_BrdSettings->m_PcbTextWidth, PCB_INTERNAL_UNIT );
 
     AddUnitSymbol( *m_TextSizeVTitle );
     PutValueInLocalUnits( *m_OptPcbTextVSize,
-                          g_DesignSettings.m_PcbTextSize.y, PCB_INTERNAL_UNIT );
+                           m_BrdSettings->m_PcbTextSize.y, PCB_INTERNAL_UNIT );
 
     AddUnitSymbol( *m_TextSizeHTitle );
     PutValueInLocalUnits( *m_OptPcbTextHSize,
-                          g_DesignSettings.m_PcbTextSize.x, PCB_INTERNAL_UNIT );
+                           m_BrdSettings->m_PcbTextSize.x, PCB_INTERNAL_UNIT );
 
 
     /* Modules: Edges width */
@@ -69,15 +69,15 @@ void WinEDA_GraphicItemsOptionsDialog::SetDisplayValue()
 
 void WinEDA_GraphicItemsOptionsDialog::AcceptOptions( wxCommandEvent& event )
 {
-    g_DesignSettings.m_DrawSegmentWidth =
+     m_BrdSettings->m_DrawSegmentWidth =
         ReturnValueFromTextCtrl( *m_OptPcbSegmWidth, PCB_INTERNAL_UNIT );
-    g_DesignSettings.m_EdgeSegmentWidth =
+     m_BrdSettings->m_EdgeSegmentWidth =
         ReturnValueFromTextCtrl( *m_OptPcbEdgesWidth, PCB_INTERNAL_UNIT );
-    g_DesignSettings.m_PcbTextWidth =
+     m_BrdSettings->m_PcbTextWidth =
         ReturnValueFromTextCtrl( *m_OptPcbTextWidth, PCB_INTERNAL_UNIT );
-    g_DesignSettings.m_PcbTextSize.y =
+     m_BrdSettings->m_PcbTextSize.y =
         ReturnValueFromTextCtrl( *m_OptPcbTextVSize, PCB_INTERNAL_UNIT );
-    g_DesignSettings.m_PcbTextSize.x =
+     m_BrdSettings->m_PcbTextSize.x =
         ReturnValueFromTextCtrl( *m_OptPcbTextHSize, PCB_INTERNAL_UNIT );
 
     ModuleSegmentWidth =
@@ -119,6 +119,7 @@ END_EVENT_TABLE()
 
 WinEDA_GraphicItemsOptionsDialog::WinEDA_GraphicItemsOptionsDialog()
 {
+    m_BrdSettings = m_Parent->GetBoard()->GetBoardDesignSettings();
 }
 
 

pcbnew/dialog_graphic_items_options.h

@@ -68,6 +68,8 @@ class WinEDA_GraphicItemsOptionsDialog: public wxDialog
     DECLARE_EVENT_TABLE()
 
 public:
+    BOARD_DESIGN_SETTINGS*  m_BrdSettings;
+
     /// Constructors
     WinEDA_GraphicItemsOptionsDialog( );
     WinEDA_GraphicItemsOptionsDialog( WinEDA_BasePcbFrame* parent, wxWindowID id = SYMBOL_WINEDA_GRAPHICITEMSOPTIONSDIALOG_IDNAME, const wxString& caption = SYMBOL_WINEDA_GRAPHICITEMSOPTIONSDIALOG_TITLE, const wxPoint& pos = SYMBOL_WINEDA_GRAPHICITEMSOPTIONSDIALOG_POSITION, const wxSize& size = SYMBOL_WINEDA_GRAPHICITEMSOPTIONSDIALOG_SIZE, long style = SYMBOL_WINEDA_GRAPHICITEMSOPTIONSDIALOG_STYLE );

pcbnew/dialog_mask_clearance.cpp

@@ -26,6 +26,8 @@ DIALOG_PADS_MASK_CLEARANCE::DIALOG_PADS_MASK_CLEARANCE( WinEDA_PcbFrame* parent
     DIALOG_PADS_MASK_CLEARANCE_BASE( parent )
 {
     m_Parent = parent;
+    m_BrdSettings = m_Parent->GetBoard()->GetBoardDesignSettings();
+
     MyInit();
     GetSizer()->SetSizeHints( this );
     Centre();
@@ -41,22 +43,23 @@ void DIALOG_PADS_MASK_CLEARANCE::MyInit()
 
     int Internal_Unit = m_Parent->m_InternalUnits;
     PutValueInLocalUnits( *m_SolderMaskMarginCtrl,
-                          g_DesignSettings.m_SolderMaskMargin,
+                           m_BrdSettings->m_SolderMaskMargin,
                           Internal_Unit );
 
     // These 2 parameters are usually < 0, so prepare entering a negative
     // value, if current is 0
     PutValueInLocalUnits( *m_SolderPasteMarginCtrl,
-                          g_DesignSettings.m_SolderPasteMargin,
+                           m_BrdSettings->m_SolderPasteMargin,
                           Internal_Unit );
-    if( g_DesignSettings.m_SolderPasteMargin == 0 )
+    if(  m_BrdSettings->m_SolderPasteMargin == 0 )
         m_SolderPasteMarginCtrl->SetValue( wxT( "-" ) +
                                            m_SolderPasteMarginCtrl->GetValue() );
     wxString msg;
-    if( g_DesignSettings.m_SolderPasteMarginRatio == 0 )
-        msg.Printf( wxT( "-%f" ), g_DesignSettings.m_SolderPasteMarginRatio * 100.0 );
+    msg.Printf( wxT( "%f" ), m_BrdSettings->m_SolderPasteMarginRatio * 100.0 );
+    if(  m_BrdSettings->m_SolderPasteMarginRatio == 0.0 &&
+        msg[0] == '0')  // Sometimes Printf add a sign if the value is small
+        m_SolderPasteMarginRatioCtrl->SetValue( wxT( "-" ) + msg );
     else
-        msg.Printf( wxT( "%f" ), g_DesignSettings.m_SolderPasteMarginRatio * 100.0 );
         m_SolderPasteMarginRatioCtrl->SetValue( msg );
 }
 
@@ -65,18 +68,20 @@ void DIALOG_PADS_MASK_CLEARANCE::MyInit()
 void DIALOG_PADS_MASK_CLEARANCE::OnButtonOkClick( wxCommandEvent& event )
 /*******************************************************************/
 {
-    g_DesignSettings.m_SolderMaskMargin =
+     m_BrdSettings->m_SolderMaskMargin =
         ReturnValueFromTextCtrl( *m_SolderMaskMarginCtrl, m_Parent->m_InternalUnits );
-    g_DesignSettings.m_SolderPasteMargin =
+     m_BrdSettings->m_SolderPasteMargin =
         ReturnValueFromTextCtrl( *m_SolderPasteMarginCtrl, m_Parent->m_InternalUnits );
-    double   dtmp;
+    double   dtmp = 0;
     wxString msg = m_SolderPasteMarginRatioCtrl->GetValue();
     msg.ToDouble( &dtmp );
 
     // A margin ratio de -50% means no paste on a pad, the ratio must be >= 50 %
     if( dtmp < -50 )
         dtmp = -50;
-    g_DesignSettings.m_SolderPasteMarginRatio = dtmp / 100;
+    if( dtmp > +100 )
+        dtmp = +100;
+     m_BrdSettings->m_SolderPasteMarginRatio = dtmp / 100;
 
     EndModal( 1 );
 }

pcbnew/dialog_mask_clearance.h

@@ -20,6 +20,7 @@ class DIALOG_PADS_MASK_CLEARANCE : public DIALOG_PADS_MASK_CLEARANCE_BASE
 {
 private:
     WinEDA_PcbFrame*  m_Parent;
+    BOARD_DESIGN_SETTINGS*  m_BrdSettings;
 
 public:
     DIALOG_PADS_MASK_CLEARANCE( WinEDA_PcbFrame* parent );

pcbnew/dialog_pad_properties.cpp

@@ -159,10 +159,11 @@ void DIALOG_PAD_PROPERTIES::InitDialog( )
     PutValueInLocalUnits( *m_SolderPasteMarginCtrl, pad->m_LocalSolderPasteMargin, internalUnits );
     if( pad->m_LocalSolderPasteMargin == 0 )
         m_SolderPasteMarginCtrl->SetValue( wxT("-") + m_SolderPasteMarginCtrl->GetValue() );
-    if( pad->m_LocalSolderPasteMarginRatio == 0.0 )
-        msg.Printf( wxT( "-%.1f" ), pad->m_LocalSolderPasteMarginRatio * 100.0 );
-    else
     msg.Printf( wxT( "%.1f" ), pad->m_LocalSolderPasteMarginRatio * 100.0 );
+    if( pad->m_LocalSolderPasteMarginRatio == 0.0 &&
+        msg[0] == '0')  // Sometimes Printf add a sign if the value is small
+        m_SolderPasteMarginRatioCtrl->SetValue( wxT("-") + msg );
+    else
         m_SolderPasteMarginRatioCtrl->SetValue( msg );
 
     if( m_CurrentPad )
@@ -425,12 +426,14 @@ void DIALOG_PAD_PROPERTIES::PadPropertiesAccept( wxCommandEvent& event )
     g_Pad_Master.m_LocalClearance = ReturnValueFromTextCtrl( *m_NetClearanceValueCtrl, internalUnits );
     g_Pad_Master.m_LocalSolderMaskMargin = ReturnValueFromTextCtrl( *m_SolderMaskMarginCtrl, internalUnits );
     g_Pad_Master.m_LocalSolderPasteMargin = ReturnValueFromTextCtrl( *m_SolderPasteMarginCtrl, internalUnits );
-    double   dtmp;
+    double   dtmp = 0.0;
     msg = m_SolderPasteMarginRatioCtrl->GetValue();
     msg.ToDouble( &dtmp );
     // A margin ratio de -50% means no paste on a pad, the ratio must be >= 50 %
     if( dtmp < -50 )
         dtmp = -50;
+    if( dtmp > +100 )
+        dtmp = +100;
    g_Pad_Master.m_LocalSolderPasteMarginRatio = dtmp / 100;
 
     // Read pad position:

pcbnew/dialog_print_using_printer.cpp

@@ -141,7 +141,7 @@ void DIALOG_PRINT_USING_PRINTER::InitValues( )
     wxString layerKey;
     for( layer = 0; layer < NB_LAYERS; ++layer )
     {
-        if( !board->m_BoardSettings->IsLayerEnabled( layer ) )
+        if( !board->IsLayerEnabled( layer ) )
             m_BoxSelectLayer[layer] = NULL;
         else
         m_BoxSelectLayer[layer] =

pcbnew/dimension.cpp

@@ -226,8 +226,8 @@ COTATION* WinEDA_PcbFrame::Begin_Cotation( COTATION* Cotation, wxDC* DC )
         Cotation = new COTATION( GetBoard() );
         Cotation->m_Flags = IS_NEW;
 
-        Cotation->SetLayer( ((PCB_SCREEN*)GetScreen())->m_Active_Layer );
-        Cotation->m_Width = g_DesignSettings.m_DrawSegmentWidth;
+        Cotation->SetLayer( getActiveLayer() );
+        Cotation->m_Width = GetBoard()->GetBoardDesignSettings()->m_DrawSegmentWidth;
         Cotation->m_Text->m_Width = Cotation->m_Width;
 
         Cotation->Barre_ox = Cotation->Barre_fx = pos.x;
@@ -251,8 +251,8 @@ COTATION* WinEDA_PcbFrame::Begin_Cotation( COTATION* Cotation, wxDC* DC )
         Cotation->FlecheD2_ox = Cotation->FlecheD2_fx = pos.x;
         Cotation->FlecheD2_oy = Cotation->FlecheD2_fy = pos.y;
 
-        Cotation->m_Text->m_Size   = g_DesignSettings.m_PcbTextSize;
-        Cotation->m_Text->m_Width  = g_DesignSettings.m_PcbTextWidth;
+        Cotation->m_Text->m_Size   = GetBoard()->GetBoardDesignSettings()->m_PcbTextSize;
+        Cotation->m_Text->m_Width  = GetBoard()->GetBoardDesignSettings()->m_PcbTextWidth;
 
         Ajuste_Details_Cotation( Cotation );
 

pcbnew/drc.cpp

@@ -63,11 +63,11 @@ void DRC::ShowDialog()
 
         // copy data retained in this DRC object into the m_ui DrcPanel:
 
-        PutValueInLocalUnits( *m_ui->m_SetTrackMinWidthCtrl, g_DesignSettings.m_TrackMinWidth,
+        PutValueInLocalUnits( *m_ui->m_SetTrackMinWidthCtrl, m_pcb->GetBoardDesignSettings()->m_TrackMinWidth,
                               m_mainWindow->m_InternalUnits );;
-        PutValueInLocalUnits( *m_ui->m_SetViaMinSizeCtrl, g_DesignSettings.m_ViasMinSize,
+        PutValueInLocalUnits( *m_ui->m_SetViaMinSizeCtrl, m_pcb->GetBoardDesignSettings()->m_ViasMinSize,
                               m_mainWindow->m_InternalUnits );;
-        PutValueInLocalUnits( *m_ui->m_SetMicroViakMinSizeCtrl, g_DesignSettings.m_MicroViasMinSize,
+        PutValueInLocalUnits( *m_ui->m_SetMicroViakMinSizeCtrl, m_pcb->GetBoardDesignSettings()->m_MicroViasMinSize,
                               m_mainWindow->m_InternalUnits );;
 
         m_ui->m_CreateRptCtrl->SetValue( m_doCreateRptFile );
@@ -315,11 +315,11 @@ bool DRC::doNetClass( NETCLASS* nc, wxString& msg )
 {
     bool ret = true;
 
-    const EDA_BoardDesignSettings& g = g_DesignSettings;
+    const BOARD_DESIGN_SETTINGS& g = *m_pcb->GetBoardDesignSettings();
 
 #define FmtVal( x )   GetChars( ReturnStringFromValue( g_UnitMetric, x, PCB_INTERNAL_UNIT ) )
 
-#if 0   // set to 1 when (if...) EDA_BoardDesignSettings has a m_MinClearance value
+#if 0   // set to 1 when (if...) BOARD_DESIGN_SETTINGS has a m_MinClearance value
     if( nc->GetClearance() < g.m_MinClearance )
     {
         msg.Printf( _("NETCLASS: '%s' has Clearance:%s which is less than global:%s"),
@@ -772,7 +772,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
             // test:
             if( layer1 == LAYER_N_BACK && layer2 == LAYER_N_2 )
                 err = false;
-            if( layer1 == (g_DesignSettings.GetCopperLayerCount() - 2 ) && layer2 == LAYER_N_FRONT )
+            if( layer1 == (m_pcb->GetBoardDesignSettings()->GetCopperLayerCount() - 2 ) && layer2 == LAYER_N_FRONT )
                 err = false;
             if( err )
             {

pcbnew/drc_stuff.h

@@ -64,10 +64,10 @@
 #define DRCE_TOO_SMALL_TRACK_WIDTH          27  ///< Too small track width
 #define DRCE_TOO_SMALL_VIA                  28  ///< Too small via size
 #define DRCE_TOO_SMALL_MICROVIA             29  ///< Too small micro via size
-#define DRCE_NETCLASS_TRACKWIDTH            30  ///< netclass has TrackWidth < g_DesignSettings.m_TrackMinWidth
-#define DRCE_NETCLASS_CLEARANCE             31  ///< netclass has Clearance < g_DesignSettings.m_TrackClearance
-#define DRCE_NETCLASS_VIASIZE               32  ///< netclass has ViaSize < g_DesignSettings.m_ViasMinSize
-#define DRCE_NETCLASS_VIADRILLSIZE          33  ///< netclass has ViaDrillSize < g_DesignSettings.m_ViaDrill
+#define DRCE_NETCLASS_TRACKWIDTH            30  ///< netclass has TrackWidth < board.m_designSettings->m_TrackMinWidth
+#define DRCE_NETCLASS_CLEARANCE             31  ///< netclass has Clearance < board.m_designSettings->m_TrackClearance
+#define DRCE_NETCLASS_VIASIZE               32  ///< netclass has ViaSize < board.m_designSettings->m_ViasMinSize
+#define DRCE_NETCLASS_VIADRILLSIZE          33  ///< netclass has ViaDrillSize < board.m_designSettings->m_ViaDrill
 #define DRCE_NETCLASS_uVIASIZE              34
 #define DRCE_NETCLASS_uVIADRILLSIZE         35
 
@@ -229,7 +229,7 @@ private:
     /**
      * Function testNetClasses
      * goes through each NETCLASS and verifies that its clearance, via size,
-     * track width, and track clearance are larger than those in g_DesignSettings.
+     * track width, and track clearance are larger than those in board.m_designSettings.
      * This is necessary because the actual DRC checks are run against the NETCLASS
      * limits, so in order enforce global limits, we first check the NETCLASSes against
      * the global limits.

pcbnew/edit.cpp

@@ -340,7 +340,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
         break;
 
     case ID_POPUP_PCB_PLACE_MICROVIA:
-        if( !( (PCB_SCREEN*) GetScreen() )->IsMicroViaAcceptable() )
+        if( !IsMicroViaAcceptable() )
             break;
     case ID_POPUP_PCB_PLACE_VIA:
         DrawPanel->MouseToCursorSchema();
@@ -350,11 +350,11 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
         }
         else
         {
-            int v_type = g_DesignSettings.m_CurrentViaType;
+            int v_type = GetBoard()->GetBoardDesignSettings()->m_CurrentViaType;
             if( id == ID_POPUP_PCB_PLACE_MICROVIA )
-                g_DesignSettings.m_CurrentViaType = VIA_MICROVIA; // place micro via and switch layer
+                GetBoard()->GetBoardDesignSettings()->m_CurrentViaType = VIA_MICROVIA; // place micro via and switch layer
             Other_Layer_Route( (TRACK*) GetCurItem(), &dc );
-            g_DesignSettings.m_CurrentViaType = v_type;
+            GetBoard()->GetBoardDesignSettings()->m_CurrentViaType = v_type;
             if( DisplayOpt.ContrastModeDisplay )
                 ( (PCB_SCREEN*) GetScreen() )->SetRefreshReq();
         }
@@ -1077,7 +1077,7 @@ void WinEDA_PcbFrame::SwitchLayer( wxDC* DC, int layer )
         // If only one copper layer is enabled, the only such layer
         // that can be selected to is the "Back" layer (so the
         // selection of any other copper layer is disregarded).
-        if( GetBoard()->m_BoardSettings->GetCopperLayerCount() < 2 )
+        if( GetBoard()->GetCopperLayerCount() < 2 )
         {
             if( layer != LAYER_N_BACK )
             {
@@ -1096,7 +1096,7 @@ void WinEDA_PcbFrame::SwitchLayer( wxDC* DC, int layer )
         else
         {
             if( ( layer != LAYER_N_BACK ) && ( layer != LAYER_N_FRONT )
-               && ( layer >= GetBoard()->m_BoardSettings->GetCopperLayerCount() - 1 ) )
+               && ( layer >= GetBoard()->GetCopperLayerCount() - 1 ) )
             {
                 // Uncomment following command (and line 17) to beep
                 // the speaker. (Doing that would provide feedback to

pcbnew/edit_pcb_text.cpp

@@ -163,9 +163,9 @@ TEXTE_PCB* WinEDA_PcbFrame::Create_Texte_Pcb( wxDC* DC )
     if( TextePcb->GetLayer() == LAYER_N_BACK )
         TextePcb->m_Mirror = true;
 
-    TextePcb->m_Size  = g_DesignSettings.m_PcbTextSize;
+    TextePcb->m_Size  = GetBoard()->GetBoardDesignSettings()->m_PcbTextSize;
     TextePcb->m_Pos   = GetScreen()->m_Curseur;
-    TextePcb->m_Width = g_DesignSettings.m_PcbTextWidth;
+    TextePcb->m_Width = GetBoard()->GetBoardDesignSettings()->m_PcbTextWidth;
 
     InstallTextPCBOptionsFrame( TextePcb, DC );
     if( TextePcb->m_Text.IsEmpty() )

pcbnew/editedge.cpp

@@ -205,10 +205,10 @@ DRAWSEGMENT* WinEDA_PcbFrame::Begin_DrawSegment( DRAWSEGMENT* Segment,
     int          angle = 0;
     DRAWSEGMENT* DrawItem;
 
-    s_large = g_DesignSettings.m_DrawSegmentWidth;
-    if( ((PCB_SCREEN*)GetScreen())->m_Active_Layer == EDGE_N )
+    s_large = GetBoard()->GetBoardDesignSettings()->m_DrawSegmentWidth;
+    if( getActiveLayer() == EDGE_N )
     {
-        s_large = g_DesignSettings.m_EdgeSegmentWidth;
+        s_large = GetBoard()->GetBoardDesignSettings()->m_EdgeSegmentWidth;
     }
 
     if( shape == S_ARC )
@@ -218,7 +218,7 @@ DRAWSEGMENT* WinEDA_PcbFrame::Begin_DrawSegment( DRAWSEGMENT* Segment,
     {
         SetCurItem( Segment = new DRAWSEGMENT( GetBoard() ) );
         Segment->m_Flags = IS_NEW;
-        Segment->SetLayer( ((PCB_SCREEN*)GetScreen())->m_Active_Layer );
+        Segment->SetLayer( getActiveLayer() );
         Segment->m_Width = s_large;
         Segment->m_Shape = shape;
         Segment->m_Angle = 900;

pcbnew/editrack-part2.cpp

@@ -146,7 +146,7 @@ bool WinEDA_PcbFrame::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
     /* create the via */
     SEGVIA* via    = new SEGVIA( GetBoard() );
     via->m_Flags   = IS_NEW;
-    via->m_Shape   = g_DesignSettings.m_CurrentViaType;
+    via->m_Shape   = GetBoard()->GetBoardDesignSettings()->m_CurrentViaType;
     via->m_Width   = GetBoard()->GetCurrentViaSize();
     via->SetNet( g_HighLight_NetCode );
     via->m_Start   = via->m_End = g_CurrentTrackSegment->m_End;
@@ -172,7 +172,7 @@ bool WinEDA_PcbFrame::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
 
         case VIA_MICROVIA:  // from external to the near neighbor inner layer
         {
-            int last_inner_layer = GetBoard()->m_BoardSettings->GetCopperLayerCount() - 2;
+            int last_inner_layer = GetBoard()->GetCopperLayerCount() - 2;
             if ( first_layer == LAYER_N_BACK )
                 last_layer = LAYER_N_2;
             else if ( first_layer == LAYER_N_FRONT )
@@ -271,7 +271,7 @@ void WinEDA_PcbFrame::Affiche_Status_Net( wxDC* DC )
     TRACK* pt_segm;
     int    masquelayer = (1 << getActiveLayer());
 
-    pt_segm = Locate_Pistes( GetBoard()->m_Track, masquelayer,
+    pt_segm = Locate_Pistes( GetBoard(), GetBoard()->m_Track, masquelayer,
                              CURSEUR_OFF_GRILLE );
     if( pt_segm == NULL )
         GetBoard()->DisplayInfo( this );

pcbnew/editrack.cpp

@@ -161,7 +161,7 @@ TRACK* WinEDA_PcbFrame::Begin_Route( TRACK* aTrack, wxDC* DC )
         g_CurrentTrackSegment->SetLayer( GetScreen()->m_Active_Layer );
         g_CurrentTrackSegment->m_Width = GetBoard()->GetCurrentTrackWidth();
 
-        if( g_DesignSettings.m_UseConnectedTrackWidth )
+        if( GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
         {
             if( TrackOnStartPoint && TrackOnStartPoint->Type() == TYPE_TRACK )
                 g_CurrentTrackSegment->m_Width = TrackOnStartPoint->m_Width;
@@ -274,7 +274,7 @@ TRACK* WinEDA_PcbFrame::Begin_Route( TRACK* aTrack, wxDC* DC )
             newTrack->m_Start = newTrack->m_End;
 
             newTrack->SetLayer( ( (PCB_SCREEN*) GetScreen() )->m_Active_Layer );
-            if( !g_DesignSettings.m_UseConnectedTrackWidth )
+            if( !GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
             {
                 newTrack->m_Width = GetBoard()->GetCurrentTrackWidth();
             }
@@ -730,7 +730,7 @@ void ShowNewTrackWhenMovingCursor( WinEDA_DrawPanel* panel,
         {
             previous_track->SetLayer( screen->m_Active_Layer );
 
-            if( !g_DesignSettings.m_UseConnectedTrackWidth )
+            if( !frame->GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
                 previous_track->m_Width =
                     frame->GetBoard()->GetCurrentTrackWidth();
         }

pcbnew/event_handlers_tracks_vias_sizes.cpp

@@ -33,12 +33,12 @@ void WinEDA_PcbFrame::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
     switch( id )
     {
     case ID_AUX_TOOLBAR_PCB_SELECT_AUTO_WIDTH:
-        g_DesignSettings.m_UseConnectedTrackWidth = not g_DesignSettings.m_UseConnectedTrackWidth;
+        GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth = not GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth;
         AuxiliaryToolBar_Update_UI( );
         break;
 
     case ID_POPUP_PCB_SELECT_USE_NETCLASS_VALUES:
-        g_DesignSettings.m_UseConnectedTrackWidth = false;
+        GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth = false;
         GetBoard()->m_TrackWidthSelector = 0;
         GetBoard()->m_ViaSizeSelector = 0;
         AuxiliaryToolBar_Update_UI( );
@@ -46,7 +46,7 @@ void WinEDA_PcbFrame::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
 
     case ID_POPUP_PCB_SELECT_AUTO_WIDTH:
         DrawPanel->MouseToCursorSchema();
-        g_DesignSettings.m_UseConnectedTrackWidth = true;
+        GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth = true;
         AuxiliaryToolBar_Update_UI( );
         break;
 
@@ -59,7 +59,7 @@ void WinEDA_PcbFrame::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
     case ID_POPUP_PCB_SELECT_WIDTH7:
     case ID_POPUP_PCB_SELECT_WIDTH8:
         DrawPanel->MouseToCursorSchema();
-        g_DesignSettings.m_UseConnectedTrackWidth = false;
+        GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth = false;
         ii = id - ID_POPUP_PCB_SELECT_WIDTH1;
         GetBoard()->m_TrackWidthSelector = ii;
         AuxiliaryToolBar_Update_UI( );

pcbnew/gen_drill_report_files.cpp

@@ -388,7 +388,7 @@ void GenDrillReportFile( FILE* aFile, BOARD* aPcb,
         sprintf( line, "\ntotal holes count %d\n\n\n", TotalHoleCount );
         fputs( line, aFile );
 
-        if( g_DesignSettings.GetCopperLayerCount() <= 2 )
+        if( aPcb->GetCopperLayerCount() <= 2 )
             break;
 
         if(  gen_through_holes )
@@ -399,7 +399,7 @@ void GenDrillReportFile( FILE* aFile, BOARD* aPcb,
                 break;
             layer1++; layer2++;           // use next layer pair
 
-            if( layer2 == g_DesignSettings.GetCopperLayerCount() - 1 )
+            if( layer2 == aPcb->GetCopperLayerCount() - 1 )
                 layer2 = LAYER_N_FRONT;  // the last layer is always the
                                        // component layer
         }

pcbnew/gendrill.cpp

@@ -366,7 +366,7 @@ void WinEDA_DrillFrame::GenDrillFiles( wxCommandEvent& event )
             layer1++;
             layer2++;                      // use next layer pair
 
-            if( layer2 == g_DesignSettings.GetCopperLayerCount() - 1 )
+            if( layer2 == m_Parent->GetBoard()->GetCopperLayerCount() - 1 )
                 layer2 = LAYER_N_FRONT;      // the last layer is always the
                                            // component layer
         }

pcbnew/hotkeys.cpp

@@ -246,11 +246,11 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey, EDA_BaseStruct* DrawStruct
         if( (ll <= LAYER_N_BACK) || (ll > LAYER_N_FRONT) )
             break;
 
-        if( GetBoard()->m_BoardSettings->GetCopperLayerCount() < 2 ) // Single layer
+        if( GetBoard()->GetCopperLayerCount() < 2 ) // Single layer
             ll = LAYER_N_BACK;
         else if( ll == LAYER_N_FRONT )
             ll = MAX( LAYER_N_BACK,
-                      GetBoard()->m_BoardSettings->GetCopperLayerCount() - 2 );
+                      GetBoard()->GetCopperLayerCount() - 2 );
         else
             ll--;
         SwitchLayer( DC, ll );
@@ -260,9 +260,9 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey, EDA_BaseStruct* DrawStruct
         ll = GetScreen()->m_Active_Layer;
         if( (ll < LAYER_N_BACK) || (ll >= LAYER_N_FRONT) )
             break;
-        if( GetBoard()->m_BoardSettings->GetCopperLayerCount() < 2 ) // Single layer
+        if( GetBoard()->GetCopperLayerCount() < 2 ) // Single layer
             ll = LAYER_N_BACK;
-        else if( ll >= GetBoard()->m_BoardSettings->GetCopperLayerCount() - 2 )
+        else if( ll >= GetBoard()->GetCopperLayerCount() - 2 )
             ll = LAYER_N_FRONT;
         else
             ll++;
@@ -456,12 +456,12 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey, EDA_BaseStruct* DrawStruct
             return;
 
         // place micro via and switch layer
-        if( GetScreen()->IsMicroViaAcceptable() )
+        if( IsMicroViaAcceptable() )
         {
-            int v_type = g_DesignSettings.m_CurrentViaType;
-            g_DesignSettings.m_CurrentViaType = VIA_MICROVIA;
+            int v_type = GetBoard()->GetBoardDesignSettings()->m_CurrentViaType;
+            GetBoard()->GetBoardDesignSettings()->m_CurrentViaType = VIA_MICROVIA;
             Other_Layer_Route( (TRACK*) GetCurItem(), DC );
-            g_DesignSettings.m_CurrentViaType = v_type;
+            GetBoard()->GetBoardDesignSettings()->m_CurrentViaType = v_type;
             if( DisplayOpt.ContrastModeDisplay )
                 GetScreen()->SetRefreshReq();
         }

pcbnew/ioascii.cpp

@@ -214,14 +214,14 @@ int WinEDA_BasePcbFrame::ReadGeneralDescrPcb( FILE* File, int* LineNum )
                 Masque_Layer >>= 1;
             }
 
-            GetBoard()->m_BoardSettings->SetCopperLayerCount( layer_count );
+            GetBoard()->SetCopperLayerCount( layer_count );
 
             continue;
         }
-        if( stricmp( data, "LayerThickness" ) == 0 )
+        if( stricmp( data, "BoardThickness" ) == 0 )
         {
             data = strtok( NULL, " =\n\r" );
-            GetBoard()->m_BoardSettings->m_LayerThickness = atoi( data );;
+            GetBoard()->GetBoardDesignSettings()->m_BoardThickness = atoi( data );;
             continue;
         }
 
@@ -345,7 +345,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
         {
             int tmp;
             sscanf( data, "%d", &tmp );
-            GetBoard()->m_BoardSettings->SetCopperLayerCount( tmp );
+            GetBoard()->SetCopperLayerCount( tmp );
             continue;
         }
 
@@ -394,7 +394,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 
         if( stricmp( Line, "TrackMinWidth" ) == 0 )
         {
-            g_DesignSettings.m_TrackMinWidth = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_TrackMinWidth = atoi( data );
             continue;
         }
 
@@ -406,13 +406,13 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 
         if( stricmp( Line, "DrawSegmWidth" ) == 0 )
         {
-            g_DesignSettings.m_DrawSegmentWidth = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_DrawSegmentWidth = atoi( data );
             continue;
         }
 
         if( stricmp( Line, "EdgeSegmWidth" ) == 0 )
         {
-            g_DesignSettings.m_EdgeSegmentWidth = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_EdgeSegmentWidth = atoi( data );
             continue;
         }
 
@@ -423,7 +423,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 
         if( stricmp( Line, "ViaMinSize" ) == 0 )
         {
-            g_DesignSettings.m_ViasMinSize = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_ViasMinSize = atoi( data );
             continue;
         }
 
@@ -434,7 +434,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 
         if( stricmp( Line, "MicroViaMinSize" ) == 0 )
         {
-            g_DesignSettings.m_MicroViasMinSize = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_MicroViasMinSize = atoi( data );
             continue;
         }
 
@@ -462,7 +462,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 
         if( stricmp( Line, "ViaMinDrill" ) == 0 )
         {
-            g_DesignSettings.m_ViasMinDrill = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_ViasMinDrill = atoi( data );
             continue;
         }
 
@@ -476,27 +476,27 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
         if( stricmp( Line, "MicroViaMinDrill" ) == 0 )
         {
             int diameter = atoi( data );
-            g_DesignSettings.m_MicroViasMinDrill = diameter;
+            GetBoard()->GetBoardDesignSettings()->m_MicroViasMinDrill = diameter;
             continue;
         }
 
         if( stricmp( Line, "MicroViasAllowed" ) == 0 )
         {
-            g_DesignSettings.m_MicroViasAllowed = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_MicroViasAllowed = atoi( data );
             continue;
         }
 
         if( stricmp( Line, "TextPcbWidth" ) == 0 )
         {
-            g_DesignSettings.m_PcbTextWidth = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_PcbTextWidth = atoi( data );
             continue;
         }
 
         if( stricmp( Line, "TextPcbSize" ) == 0 )
         {
-            g_DesignSettings.m_PcbTextSize.x = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_PcbTextSize.x = atoi( data );
             data = strtok( NULL, " =\n\r" );
-            g_DesignSettings.m_PcbTextSize.y = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_PcbTextSize.y = atoi( data );
             continue;
         }
 
@@ -536,17 +536,17 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
         }
         if( stricmp( Line, "Pad2MaskClearance" ) == 0 )
         {
-            g_DesignSettings.m_SolderMaskMargin = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_SolderMaskMargin = atoi( data );
             continue;
         }
         if( stricmp( Line, "Pad2PasteClearance" ) == 0 )
         {
-            g_DesignSettings.m_SolderPasteMargin = atoi( data );
+            GetBoard()->GetBoardDesignSettings()->m_SolderPasteMargin = atoi( data );
             continue;
         }
         if( stricmp( Line, "Pad2PasteClearanceRatio" ) == 0 )
         {
-            g_DesignSettings.m_SolderPasteMarginRatio = atof( data );
+            GetBoard()->GetBoardDesignSettings()->m_SolderPasteMarginRatio = atof( data );
             continue;
         }
 
@@ -592,7 +592,7 @@ int WinEDA_BasePcbFrame::ReadSetup( FILE* File, int* LineNum )
 #ifdef PCBNEW
 static int WriteSetup( FILE* aFile, WinEDA_BasePcbFrame* aFrame, BOARD* aBoard )
 {
-    NETCLASS* netclass_default = aFrame->GetBoard()->m_NetClasses.GetDefault();
+    NETCLASS* netclass_default = aBoard->m_NetClasses.GetDefault();
     char      text[1024];
 
     fprintf( aFile, "$SETUP\n" );
@@ -630,17 +630,17 @@ static int WriteSetup( FILE* aFile, WinEDA_BasePcbFrame* aFrame, BOARD* aBoard )
     fprintf( aFile,
              "ZoneClearence %d\n",
              g_Zone_Default_Setting.m_ZoneClearance );
-    fprintf( aFile, "TrackMinWidth %d\n", g_DesignSettings.m_TrackMinWidth );
+    fprintf( aFile, "TrackMinWidth %d\n", aBoard->GetBoardDesignSettings()->m_TrackMinWidth );
 
-    fprintf( aFile, "DrawSegmWidth %d\n", g_DesignSettings.m_DrawSegmentWidth );
-    fprintf( aFile, "EdgeSegmWidth %d\n", g_DesignSettings.m_EdgeSegmentWidth );
+    fprintf( aFile, "DrawSegmWidth %d\n", aBoard->GetBoardDesignSettings()->m_DrawSegmentWidth );
+    fprintf( aFile, "EdgeSegmWidth %d\n", aBoard->GetBoardDesignSettings()->m_EdgeSegmentWidth );
 
     // Save current default via size, for compatibility with older pcbnew
     // version;
     fprintf( aFile, "ViaSize %d\n", netclass_default->GetViaDiameter() );
     fprintf( aFile, "ViaDrill %d\n", netclass_default->GetViaDrill() );
-    fprintf( aFile, "ViaMinSize %d\n", g_DesignSettings.m_ViasMinSize );
-    fprintf( aFile, "ViaMinDrill %d\n", g_DesignSettings.m_ViasMinDrill );
+    fprintf( aFile, "ViaMinSize %d\n", aBoard->GetBoardDesignSettings()->m_ViasMinSize );
+    fprintf( aFile, "ViaMinDrill %d\n", aBoard->GetBoardDesignSettings()->m_ViasMinDrill );
 
     // Save custom vias diameters list (the first is not saved here: this is
     // the netclass value
@@ -654,19 +654,19 @@ static int WriteSetup( FILE* aFile, WinEDA_BasePcbFrame* aFrame, BOARD* aBoard )
     fprintf( aFile, "MicroViaDrill %d\n", netclass_default->GetuViaDrill() );
     fprintf( aFile,
              "MicroViasAllowed %d\n",
-             g_DesignSettings.m_MicroViasAllowed );
+             aBoard->GetBoardDesignSettings()->m_MicroViasAllowed );
     fprintf( aFile,
              "MicroViaMinSize %d\n",
-             g_DesignSettings.m_MicroViasMinSize );
+             aBoard->GetBoardDesignSettings()->m_MicroViasMinSize );
     fprintf( aFile,
              "MicroViaMinDrill %d\n",
-             g_DesignSettings.m_MicroViasMinDrill );
+             aBoard->GetBoardDesignSettings()->m_MicroViasMinDrill );
 
-    fprintf( aFile, "TextPcbWidth %d\n", g_DesignSettings.m_PcbTextWidth );
+    fprintf( aFile, "TextPcbWidth %d\n", aBoard->GetBoardDesignSettings()->m_PcbTextWidth );
     fprintf( aFile,
              "TextPcbSize %d %d\n",
-             g_DesignSettings.m_PcbTextSize.x,
-             g_DesignSettings.m_PcbTextSize.y );
+             aBoard->GetBoardDesignSettings()->m_PcbTextSize.x,
+             aBoard->GetBoardDesignSettings()->m_PcbTextSize.y );
 
     fprintf( aFile, "EdgeModWidth %d\n", ModuleSegmentWidth );
     fprintf( aFile, "TextModSize %d %d\n", ModuleTextSize.x, ModuleTextSize.y );
@@ -678,15 +678,15 @@ static int WriteSetup( FILE* aFile, WinEDA_BasePcbFrame* aFrame, BOARD* aBoard )
     fprintf( aFile, "PadDrill %d\n", g_Pad_Master.m_Drill.x );
     fprintf( aFile,
              "Pad2MaskClearance %d\n",
-             g_DesignSettings.m_SolderMaskMargin );
-    if( g_DesignSettings.m_SolderPasteMargin != 0 )
+             aBoard->GetBoardDesignSettings()->m_SolderMaskMargin );
+    if( aBoard->GetBoardDesignSettings()->m_SolderPasteMargin != 0 )
         fprintf( aFile,
                  "Pad2PasteClearance %d\n",
-                 g_DesignSettings.m_SolderPasteMargin );
-    if( g_DesignSettings.m_SolderPasteMarginRatio != 0 )
+                 aBoard->GetBoardDesignSettings()->m_SolderPasteMargin );
+    if( aBoard->GetBoardDesignSettings()->m_SolderPasteMarginRatio != 0 )
         fprintf( aFile,
                  "Pad2PasteClearanceRatio %g\n",
-                 g_DesignSettings.m_SolderPasteMarginRatio );
+                 aBoard->GetBoardDesignSettings()->m_SolderPasteMarginRatio );
 
     fprintf( aFile,
              "AuxiliaryAxisOrg %d %d\n",
@@ -707,7 +707,7 @@ bool WinEDA_PcbFrame::WriteGeneralDescrPcb( FILE* File )
     int             NbModules, NbDrawItem, NbLayers;
 
     /* Write copper layer count */
-    NbLayers = GetBoard()->m_BoardSettings->GetCopperLayerCount();
+    NbLayers = GetBoard()->GetCopperLayerCount();
     fprintf( File, "$GENERAL\n" );
     fprintf( File, "LayerCount %d\n", NbLayers );
 
@@ -740,8 +740,8 @@ bool WinEDA_PcbFrame::WriteGeneralDescrPcb( FILE* File )
     fprintf( File, "Ndraw %d\n", NbDrawItem );
     fprintf( File, "Ntrack %d\n", GetBoard()->GetNumSegmTrack() );
     fprintf( File, "Nzone %d\n", GetBoard()->GetNumSegmZone() );
-    fprintf( File, "LayerThickness %d\n",
-             GetBoard()->m_BoardSettings->m_LayerThickness );
+    fprintf( File, "BoardThickness %d\n",
+             GetBoard()->GetBoardDesignSettings()->m_BoardThickness );
 
     fprintf( File, "Nmodule %d\n", NbModules );
     fprintf( File, "Nnets %d\n", GetBoard()->m_NetInfo->GetCount() );

pcbnew/locate.cpp

@@ -272,7 +272,7 @@ MODULE* Locate_Prefered_Module( BOARD* Pcb, int typeloc )
         }
         else if( !( typeloc & MATCH_LAYER )
             && ( !( typeloc & VISIBLE_ONLY )
-                 || IsModuleLayerVisible( layer ) ) )
+                 || Pcb->IsModuleLayerVisible( layer ) ) )
         {
             if( dist <= alt_min_dim )
             {
@@ -466,15 +466,15 @@ suite1:
  *
  * The search begins to address start_adresse
  */
-TRACK* Locate_Pistes( TRACK* start_adresse, int MasqueLayer, int typeloc )
+TRACK* Locate_Pistes(BOARD* aPcb, TRACK* start_adresse, int MasqueLayer, int typeloc )
 {
     wxPoint ref_pos = RefPos( typeloc );
 
-    return Locate_Pistes( start_adresse, ref_pos, MasqueLayer );
+    return Locate_Pistes( aPcb, start_adresse, ref_pos, MasqueLayer );
 }
 
 
-TRACK* Locate_Pistes( TRACK* start_adresse, const wxPoint& ref_pos,
+TRACK* Locate_Pistes(BOARD* aPcb, TRACK* start_adresse, const wxPoint& ref_pos,
                       int MasqueLayer )
 {
     for( TRACK* track = start_adresse;   track;  track =  track->Next() )
@@ -489,7 +489,7 @@ TRACK* Locate_Pistes( TRACK* start_adresse, const wxPoint& ref_pos,
             continue;
         }
 
-        if( g_DesignSettings.IsLayerVisible( layer ) == false )
+        if( aPcb->GetBoardDesignSettings()->IsLayerVisible( layer ) == false )
             continue;
 
         if( track->Type() == TYPE_VIA ) /* VIA encountered. */

pcbnew/magnetic_tracks_functions.cpp

@@ -184,7 +184,7 @@ bool Magnetize( BOARD* m_Pcb, WinEDA_PcbFrame* frame,
         {
             int layer_mask = g_TabOneLayerMask[layer];
 
-            TRACK* track = Locate_Pistes( m_Pcb->m_Track, layer_mask, CURSEUR_OFF_GRILLE );
+            TRACK* track = Locate_Pistes( m_Pcb, m_Pcb->m_Track, layer_mask, CURSEUR_OFF_GRILLE );
             if( !track || track->Type() != TYPE_TRACK )
             {
                 // D(printf("!currTrack and track=%p not found, layer_mask=0x%X\n", track, layer_mask );)
@@ -217,7 +217,7 @@ bool Magnetize( BOARD* m_Pcb, WinEDA_PcbFrame* frame,
             if( doCheckNet && currTrack && currTrack->GetNet() != track->GetNet() )
                 continue;
 
-            if( g_DesignSettings.IsLayerVisible( track->GetLayer() ) == false )
+            if( m_Pcb->IsLayerVisible( track->GetLayer() ) == false )
                 continue;
 
             // omit the layer check if moving a via

pcbnew/mirepcb.cpp

@@ -220,7 +220,7 @@ MIREPCB* WinEDA_PcbFrame::Create_Mire( wxDC* DC )
     GetBoard()->Add( MirePcb );
 
     MirePcb->SetLayer( EDGE_N );
-    MirePcb->m_Width = g_DesignSettings.m_EdgeSegmentWidth;
+    MirePcb->m_Width = GetBoard()->GetBoardDesignSettings()->m_EdgeSegmentWidth;
     MirePcb->m_Size  = MireDefaultSize;
     MirePcb->m_Pos  = DrawPanel->GetScreen()->m_Curseur;
 

pcbnew/moduleframe.cpp

@@ -23,6 +23,8 @@
 static PCB_SCREEN* s_screenModule = NULL;   // the PCB_SCREEN used by the
                                             // footprint editor
 
+// Design setting for the module editor:
+static BOARD_DESIGN_SETTINGS s_ModuleEditorDesignSetting;
 
 /********************************/
 /* class WinEDA_ModuleEditFrame */
@@ -170,6 +172,7 @@ WinEDA_ModuleEditFrame::WinEDA_ModuleEditFrame( wxWindow*       father,
         s_screenModule = new PCB_SCREEN();
     SetBaseScreen( s_screenModule );
     ActiveScreen = GetScreen();
+    GetBoard()->SetBoardDesignSettings( &s_ModuleEditorDesignSetting );
     GetScreen()->SetCurItem( NULL );
     LoadSettings();
 

pcbnew/move_or_drag_track.cpp

@@ -1049,7 +1049,7 @@ BOARD_ITEM* LocateLockPoint( BOARD* Pcb, wxPoint pos, int LayerMask )
     /* No pad has been located so check for a segment of the trace. */
     TRACK* ptsegm = Fast_Locate_Piste( Pcb->m_Track, NULL, pos, LayerMask );
     if( ptsegm == NULL )
-        ptsegm = Locate_Pistes( Pcb->m_Track, pos, LayerMask );
+        ptsegm = Locate_Pistes( Pcb, Pcb->m_Track, pos, LayerMask );
 
     return ptsegm;
 }

pcbnew/onrightclick.cpp

@@ -449,7 +449,7 @@ void WinEDA_PcbFrame::createPopupMenuForTracks( TRACK* Track, wxMenu* PopMenu )
         PopMenu->Append( ID_POPUP_PCB_PLACE_VIA, msg );
 
         // See if we can place a Micro Via (4 or more layers, and start from an external layer):
-        if( ( (PCB_SCREEN*) GetScreen() )->IsMicroViaAcceptable() )
+        if( IsMicroViaAcceptable() )
         {
             msg = AddHotkeyName( _(
                                      "Place Micro Via" ), s_Board_Editor_Hokeys_Descr,
@@ -813,12 +813,12 @@ static wxMenu* Append_Track_Width_List( BOARD* aBoard )
                                  "Use the track width when starting on a track, otherwise the current track width" ),
                              true );
 
-    if( g_DesignSettings.m_UseConnectedTrackWidth )
+    if( aBoard->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
         trackwidth_menu->Check( ID_POPUP_PCB_SELECT_AUTO_WIDTH, true );
 
     if( aBoard->m_ViaSizeSelector != 0
         || aBoard->m_TrackWidthSelector != 0
-        || g_DesignSettings.m_UseConnectedTrackWidth )
+        || aBoard->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
         trackwidth_menu->Append( ID_POPUP_PCB_SELECT_USE_NETCLASS_VALUES,
                                  _( "Use Netclass Values" ),
                                  _( "Use track and via sizes from their Netclass values" ),
@@ -834,7 +834,7 @@ static wxMenu* Append_Track_Width_List( BOARD* aBoard )
         trackwidth_menu->Append( ID_POPUP_PCB_SELECT_WIDTH1 + ii, msg, wxEmptyString, true );
     }
 
-    if( g_DesignSettings.m_UseConnectedTrackWidth )
+    if( aBoard->GetBoardDesignSettings()->m_UseConnectedTrackWidth )
         trackwidth_menu->Check( ID_POPUP_PCB_SELECT_AUTO_WIDTH, true );
     else
     {

pcbnew/pcbframe.cpp

@@ -872,6 +872,32 @@ void WinEDA_PcbFrame::SaveSettings()
 
 }
 
+/* Return true if a microvia can be put on board
+ * A microvia ia a small via restricted to 2 near neighbour layers
+ * because its is hole is made by laser which can penetrate only one layer
+ * It is mainly used to connect BGA to the first inner layer
+ * And it is allowed from an external layer to the first inner layer
+ */
+bool WinEDA_PcbFrame::IsMicroViaAcceptable( void )
+{
+    int copperlayercnt = GetBoard()->GetCopperLayerCount( );
+    int currLayer = getActiveLayer();
+
+    if( !GetBoard()->GetBoardDesignSettings()->m_MicroViasAllowed )
+        return false;   // Obvious..
+
+    if( copperlayercnt < 4 )
+        return false;   // Only on multilayer boards..
+
+    if( ( currLayer == LAYER_N_BACK )
+       || ( currLayer == LAYER_N_FRONT )
+       || ( currLayer == copperlayercnt - 2 )
+       || ( currLayer == LAYER_N_2 ) )
+        return true;
+
+    return false;
+}
+
 
 void WinEDA_PcbFrame::syncLayerWidget( )
 {

pcbnew/pcbnew.h

@@ -60,25 +60,6 @@ extern bool g_Raccord_45_Auto;
 
 extern const wxString g_FootprintLibFileWildcard;   // Wildcard for footprint libraries filesnames
 
-/**
- * Function IsModuleLayerVisible
- * expects either of the two layers on which a module can reside, and returns
- * whether that layer is visible.
- * @param layer One of the two allowed layers for modules: LAYER_N_FRONT or LAYER_N_BACK
- * @return bool - true if the layer is visible, else false.
- */
-bool inline IsModuleLayerVisible( int layer )
-{
-    if( layer==LAYER_N_FRONT )
-        return g_DesignSettings.IsElementVisible( PCB_VISIBLE(MOD_FR_VISIBLE) );
-
-    else if( layer==LAYER_N_BACK )
-        return g_DesignSettings.IsElementVisible( PCB_VISIBLE(MOD_BK_VISIBLE) );
-
-    else
-        return true;
-}
-
 
 extern bool        Track_45_Only;
 extern bool        Segments_45_Only;

pcbnew/pcbnew_config.h

@@ -21,6 +21,7 @@
 #define ITEM_COLOR(item_visible) &g_ColorsSettings.m_ItemsColors[item_visible]
 
 /* Configuration parameters. */
+extern BOARD_DESIGN_SETTINGS boardDesignSettings;
 
 static PARAM_CFG_WXSTRING UserLibDirBufCfg
 (
@@ -61,10 +62,10 @@ static PARAM_CFG_INT PadDimVCfg
 );
 
 
-static PARAM_CFG_INT LayerThicknessCfg
+static PARAM_CFG_INT BoardThicknessCfg
 (
-    wxT( "LayerThickness" ),
-    &g_DesignSettings.m_LayerThickness,
+    wxT( "BoardThickness" ),
+    &boardDesignSettings.m_BoardThickness,
     630,
     0, 0xFFFF
 );
@@ -213,7 +214,7 @@ static PARAM_CFG_BOOL SegmPcb45Cfg  // Force 45 degrees for segments
 static PARAM_CFG_INT PcbTextDimVCfg
 (
     wxT( "TxtPcbV" ),
-    &g_DesignSettings.m_PcbTextSize.y,
+    &boardDesignSettings.m_PcbTextSize.y,
     600,
     TEXTS_MIN_SIZE, TEXTS_MAX_SIZE
 );
@@ -221,7 +222,7 @@ static PARAM_CFG_INT PcbTextDimVCfg
 static PARAM_CFG_INT PcbTextDimHCfg
 (
     wxT( "TxtPcbH" ),
-    &g_DesignSettings.m_PcbTextSize.x,
+    &boardDesignSettings.m_PcbTextSize.x,
     600,
     TEXTS_MIN_SIZE, TEXTS_MAX_SIZE
 );
@@ -633,7 +634,7 @@ static PARAM_CFG_INT HPGLrecouvrementCfg
 static PARAM_CFG_INT VernisEpargneGardeCfg
 (
     wxT( "VEgarde" ),
-    &g_DesignSettings.m_SolderMaskMargin,
+    &boardDesignSettings.m_SolderMaskMargin,
     100,
     0, 10000
 );
@@ -641,7 +642,7 @@ static PARAM_CFG_INT VernisEpargneGardeCfg
 static PARAM_CFG_INT DrawSegmLargeurCfg
 (
     wxT( "DrawLar" ),
-    &g_DesignSettings.m_DrawSegmentWidth,
+    &boardDesignSettings.m_DrawSegmentWidth,
     120,
     0, 0xFFFF
 );
@@ -649,7 +650,7 @@ static PARAM_CFG_INT DrawSegmLargeurCfg
 static PARAM_CFG_INT EdgeSegmLargeurCfg
 (
     wxT( "EdgeLar" ),
-    &g_DesignSettings.m_EdgeSegmentWidth,
+    &boardDesignSettings.m_EdgeSegmentWidth,
     120,
     0, 0xFFFF
 );
@@ -657,7 +658,7 @@ static PARAM_CFG_INT EdgeSegmLargeurCfg
 static PARAM_CFG_INT TexteSegmLargeurCfg
 (
     wxT( "TxtLar" ),
-    &g_DesignSettings.m_PcbTextWidth,
+    &boardDesignSettings.m_PcbTextWidth,
     120,
     0, 0xFFFF
 );
@@ -732,7 +733,7 @@ PARAM_CFG_BASE* ParamCfgList[] =
     &PadDimVCfg,
     &ViaShowHoleCfg,
     &ShowNetNamesModeCfg,
-    &LayerThicknessCfg,
+    &BoardThicknessCfg,
     &RouteLayTopCfg,
     &RouteLayBotCfg,
     &Segm45Cfg,

pcbnew/pcbplot.cpp

@@ -194,7 +194,7 @@ void DIALOG_PLOT::Init_Dialog()
     wxString layerKey;
     for( layer = 0; layer < NB_LAYERS; ++layer )
     {
-        if( !board->m_BoardSettings->IsLayerEnabled( layer ) )
+        if( !board->IsLayerEnabled( layer ) )
             m_BoxSelectLayer[layer] = NULL;
         else
         m_BoxSelectLayer[layer] =

pcbnew/plot_rtn.cpp

@@ -923,7 +923,7 @@ void WinEDA_BasePcbFrame::Plot_Standard_Layer( PLOTTER*    aPlotter,
             // If the current layer is a solder mask, use the global mask
             // clearance for vias
             if( ( aLayerMask & ( SOLDERMASK_LAYER_BACK | SOLDERMASK_LAYER_FRONT ) ) )
-                via_margin = g_DesignSettings.m_SolderMaskMargin;
+                via_margin = GetBoard()->GetBoardDesignSettings()->m_SolderMaskMargin;
             pos    = Via->m_Start;
             size.x = size.y = Via->m_Width + 2 * via_margin;
 

pcbnew/protos.h

@@ -128,8 +128,8 @@ TRACK*       Locate_Piste_Connectee( TRACK* ptr_piste, TRACK* pt_base,
  *
  * The search begins to address start_adresse
  */
-TRACK*       Locate_Pistes( TRACK* start_adresse, int layer, int typeloc );
-TRACK*       Locate_Pistes( TRACK* start_adresse,
+TRACK*       Locate_Pistes( BOARD* aPcb, TRACK* start_adresse, int layer, int typeloc );
+TRACK*       Locate_Pistes( BOARD* aPcb, TRACK* start_adresse,
                             const wxPoint& ref_pos, int layer );
 
 /* Locate pad connected to the beginning or end of a segment
@@ -138,7 +138,7 @@ TRACK*       Locate_Pistes( TRACK* start_adresse,
  * A pointer to the description of the patch if pad was found.
  * NULL pointer if pad was not found.
  */
-D_PAD*       Locate_Pad_Connecte( BOARD* Pcb, TRACK* ptr_segment, int extr );
+D_PAD*       Locate_Pad_Connecte( BOARD* aPcb, TRACK* ptr_segment, int extr );
 
 
 /*
@@ -151,10 +151,10 @@ D_PAD*       Locate_Pad_Connecte( BOARD* Pcb, TRACK* ptr_segment, int extr );
  * Pointer to the pad if found
  * NULL pointer if pad not found
  */
-D_PAD*       Locate_Any_Pad( BOARD* Pcb,
+D_PAD*       Locate_Any_Pad( BOARD* aPcb,
                              int    typeloc,
                              bool   OnlyCurrentLayer = FALSE );
-D_PAD*       Locate_Any_Pad( BOARD*         Pcb,
+D_PAD*       Locate_Any_Pad( BOARD*         aPcb,
                              const wxPoint& ref_pos,
                              bool           OnlyCurrentLayer = FALSE );
 

pcbnew/sel_layer.cpp

@@ -107,7 +107,7 @@ WinEDA_SelLayerFrame::WinEDA_SelLayerFrame( WinEDA_BasePcbFrame* parent,
     /* Build the layer list */
     LayerCount = 0;
     int Masque_Layer =
-        g_TabAllCopperLayerMask[g_DesignSettings.GetCopperLayerCount() - 1];
+        g_TabAllCopperLayerMask[board->GetCopperLayerCount() - 1];
     Masque_Layer += ALL_NO_CU_LAYERS;
     for( ii = 0; ii < NB_LAYERS; ii++ )
     {
@@ -220,7 +220,7 @@ void WinEDA_BasePcbFrame::SelectLayerPair()
     // Check whether more than one copper layer has been enabled for the
     // current PCB file, as Layer Pairs can only meaningfully be defined
     // within PCB files which contain at least two copper layers.
-    if( GetBoard()->m_BoardSettings->GetCopperLayerCount() < 2 )
+    if( GetBoard()->GetCopperLayerCount() < 2 )
     {
         wxString InfoMsg;
         InfoMsg = _( "Less than two copper layers are being used." );
@@ -260,7 +260,7 @@ WinEDA_SelLayerPairFrame::WinEDA_SelLayerPairFrame( WinEDA_BasePcbFrame* parent
 
     PCB_SCREEN* screen = (PCB_SCREEN*) m_Parent->GetScreen();
     int         Masque_Layer =
-        g_TabAllCopperLayerMask[g_DesignSettings.GetCopperLayerCount() - 1];
+        g_TabAllCopperLayerMask[board->GetCopperLayerCount() - 1];
     Masque_Layer += ALL_NO_CU_LAYERS;
 
     for( ii = 0, LayerCount = 0; ii < NB_COPPER_LAYERS; ii++ )

pcbnew/solve.cpp

@@ -468,7 +468,7 @@ static int Autoroute_One_Track( WinEDA_PcbFrame* pcbframe,
     /* Test the trivial case: direct connection overlay pads. */
     if( ( row_source == row_target ) && ( col_source == col_target )
        && ( pad_masque_layer_e & pad_masque_layer_s &
-            g_TabAllCopperLayerMask[g_DesignSettings.GetCopperLayerCount() - 1] ) )
+            g_TabAllCopperLayerMask[pcbframe->GetBoard()->GetCopperLayerCount() - 1] ) )
     {
         result = TRIVIAL_SUCCESS;
         goto end_of_route;
@@ -1127,7 +1127,7 @@ static void OrCell_Trace( BOARD* pcb, int col, int row,
                                              ( g_GridRoutingSize * col );
 
         g_CurrentTrackSegment->m_Width = pcb->GetCurrentViaSize();
-        g_CurrentTrackSegment->m_Shape = g_DesignSettings.m_CurrentViaType;
+        g_CurrentTrackSegment->m_Shape = pcb->GetBoardDesignSettings()->m_CurrentViaType;
 
         g_CurrentTrackSegment->SetNet( current_net_code );
     }

pcbnew/tool_pcb.cpp

@@ -69,7 +69,7 @@ void WinEDA_PcbFrame::PrepareLayerIndicator()
                previous_Route_Layer_BOTTOM_color, previous_via_color;
 
     /* get colors, and redraw bitmap button only on changes */
-    active_layer_color = g_ColorsSettings.GetLayerColor(getActiveLayer());
+    active_layer_color = GetBoard()->GetLayerColor(getActiveLayer());
     if( previous_active_layer_color != active_layer_color )
     {
         previous_active_layer_color = active_layer_color;
@@ -87,7 +87,9 @@ void WinEDA_PcbFrame::PrepareLayerIndicator()
         previous_Route_Layer_BOTTOM_color = Route_Layer_BOTTOM_color;
         change = true;
     }
-    via_color = g_ColorsSettings.GetItemColor(VIAS_VISIBLE+g_DesignSettings.m_CurrentViaType);
+
+    int via_type = GetBoard()->GetBoardDesignSettings()->m_CurrentViaType;
+    via_color = GetBoard()->GetVisibleElementColor(VIAS_VISIBLE+via_type);
     if( previous_via_color != via_color )
     {
         previous_via_color = via_color;
@@ -707,7 +709,7 @@ WinEDAChoiceBox* WinEDA_PcbFrame::ReCreateLayerBox( WinEDA_Toolbar* parent )
 
         parent->AddControl( m_SelLayerBox );
     }
-    int      layer_mask = g_DesignSettings.GetEnabledLayers();
+    int      layer_mask = GetBoard()->GetEnabledLayers();
     unsigned length  = 0;
 
     m_SelLayerBox->Clear();

pcbnew/toolbars_update_user_interface.cpp

@@ -83,7 +83,7 @@ void WinEDA_PcbFrame::AuxiliaryToolBar_Update_UI()
     AuxiliaryToolBar_DesignRules_Update_UI();
 
     m_AuxiliaryToolBar->ToggleTool( ID_AUX_TOOLBAR_PCB_SELECT_AUTO_WIDTH,
-                                    g_DesignSettings.m_UseConnectedTrackWidth );
+                                    GetBoard()->GetBoardDesignSettings()->m_UseConnectedTrackWidth );
 
     if( m_SelTrackWidthBox && m_TrackAndViasSizesList_Changed )
     {

pcbnew/tracepcb.cpp

@@ -160,14 +160,14 @@ void BOARD::Draw( WinEDA_DrawPanel* aPanel, wxDC* DC,
         if( module->m_Flags & IS_MOVED )
             continue;
 
-        if( !g_DesignSettings.IsElementVisible( PCB_VISIBLE(MOD_FR_VISIBLE) ) )
+        if( !IsElementVisible( PCB_VISIBLE(MOD_FR_VISIBLE) ) )
         {
             if( module->GetLayer() == LAYER_N_FRONT )
                 display = FALSE;
             layerMask &= ~LAYER_FRONT;
         }
 
-        if( !g_DesignSettings.IsElementVisible( PCB_VISIBLE(MOD_BK_VISIBLE) ) )
+        if( !IsElementVisible( PCB_VISIBLE(MOD_BK_VISIBLE) ) )
         {
             if( module->GetLayer() == LAYER_N_BACK )
                 display = FALSE;