* Merge Trunk

eeschema/schframe.cpp

@@ -1053,7 +1053,8 @@ void SCH_EDIT_FRAME::OnPrint( wxCommandEvent& event )
     if( fn.GetName() != NAMELESS_PROJECT )
     {
         // was: wxGetApp().WriteProjectConfig( fn.GetFullPath(), GROUP, GetProjectFileParametersList() );
-        Prj().ConfigSave( Kiface().KifaceSearch(), GROUP_SCH, GetProjectFileParametersList() );
+        Prj().ConfigSave( Kiface().KifaceSearch(), GROUP_SCH_EDITOR,
+                          GetProjectFileParametersList() );
     }
 }
 

pcbnew/router/pns_line_placer.cpp

@@ -60,11 +60,12 @@ void PNS_LINE_PLACER::setWorld ( PNS_NODE* aWorld )
 }
 
 
-void PNS_LINE_PLACER::AddVia( bool aEnabled, int aDiameter, int aDrill )
+void PNS_LINE_PLACER::AddVia( bool aEnabled, int aDiameter, int aDrill, VIATYPE_T aType )
 {
     m_viaDiameter = aDiameter;
     m_viaDrill = aDrill;
     m_placingVia = aEnabled;
+    m_viaType = aType;
 }
 
 
@@ -73,7 +74,7 @@ void PNS_LINE_PLACER::startPlacement( const VECTOR2I& aStart, int aNet, int aWid
     assert( m_world != NULL );
     
     m_direction = m_initial_direction;
-    TRACE( 1, "world %p, intitial-direction %s layer %d\n",
+    TRACE( 1, "world %p, initial-direction %s layer %d\n",
             m_world % m_direction.Format().c_str() % aLayer );
     m_head.SetNet( aNet );
     m_tail.SetNet( aNet );
@@ -379,8 +380,8 @@ bool PNS_LINE_PLACER::handleViaPlacement( PNS_LINE& aHead )
     if( !m_placingVia )
         return true;
 
-    PNS_LAYERSET allLayers( 0, MAX_CU_LAYERS - 1 );
-    PNS_VIA v( aHead.CPoint( -1 ), allLayers, m_viaDiameter, m_viaDrill, aHead.Net() );
+    PNS_LAYERSET layers( Settings().GetLayerTop(), Settings().GetLayerBottom() );
+    PNS_VIA v( aHead.CPoint( -1 ), layers, m_viaDiameter, m_viaDrill, aHead.Net(), m_viaType );
 
     VECTOR2I force;
     VECTOR2I lead = aHead.CPoint( -1 ) - aHead.CPoint( 0 );
@@ -439,8 +440,8 @@ bool PNS_LINE_PLACER::rhWalkOnly( const VECTOR2I& aP, PNS_LINE& aNewHead )
     }
     else if( m_placingVia && viaOk )
     {
-        PNS_LAYERSET allLayers( 0, MAX_CU_LAYERS - 1 );
-        PNS_VIA v1( walkFull.CPoint( -1 ), allLayers, m_viaDiameter, m_viaDrill );
+        PNS_LAYERSET layers( Settings().GetLayerTop(), Settings().GetLayerBottom() );
+        PNS_VIA v1( walkFull.CPoint( -1 ), layers, m_viaDiameter, m_viaDrill, -1, m_viaType );
         walkFull.AppendVia( v1 );
     }
 
@@ -464,8 +465,8 @@ bool PNS_LINE_PLACER::rhMarkObstacles( const VECTOR2I& aP, PNS_LINE& aNewHead )
     
     if( m_placingVia )
     {
-        PNS_LAYERSET allLayers( 0, MAX_CU_LAYERS - 1 );
-        PNS_VIA v1( m_head.CPoint( -1 ), allLayers, m_viaDiameter, m_viaDrill );
+        PNS_LAYERSET layers( Settings().GetLayerTop(), Settings().GetLayerBottom() );
+        PNS_VIA v1( m_head.CPoint( -1 ), layers, m_viaDiameter, m_viaDrill, -1, m_viaType );
         m_head.AppendVia( v1 );
     }
 
@@ -507,9 +508,9 @@ bool PNS_LINE_PLACER::rhShoveOnly ( const VECTOR2I& aP, PNS_LINE& aNewHead )
 
     if( m_placingVia )
     {
-        PNS_LAYERSET allLayers( 0, MAX_CU_LAYERS - 1 );
-        PNS_VIA v1( l.CPoint( -1 ), allLayers, m_viaDiameter, m_viaDrill );
-        PNS_VIA v2( l2.CPoint( -1 ), allLayers, m_viaDiameter, m_viaDrill );
+        PNS_LAYERSET layers( Settings().GetLayerTop(), Settings().GetLayerBottom() );
+        PNS_VIA v1( l.CPoint( -1 ), layers, m_viaDiameter, m_viaDrill, -1, m_viaType );
+        PNS_VIA v2( l2.CPoint( -1 ), layers, m_viaDiameter, m_viaDrill, -1, m_viaType );
 
         l.AppendVia( v1 );
         l2.AppendVia( v2 );

pcbnew/router/pns_line_placer.h

@@ -84,8 +84,9 @@ public:
      * @param aEnabled if true, a via is attached during placement
      * @param aDiameter diameter of the via
      * @param aDrill drill of the via
+     * @param aType Type of the via
      */
-    void AddVia( bool aEnabled, int aDiameter, int aDrill );
+    void AddVia( bool aEnabled, int aDiameter, int aDrill, VIATYPE_T aType );
 
     /**
      * Function SetLayer()
@@ -386,6 +387,9 @@ private:
     ///> current via drill
     int m_viaDrill;
     
+    ///> current via type
+    VIATYPE_T m_viaType;
+
     ///> current track width
     int m_currentWidth;
 

pcbnew/router/pns_router.cpp

@@ -895,12 +895,32 @@ void PNS_ROUTER::SwitchLayer( int aLayer )
 }
 
 
-void PNS_ROUTER::ToggleViaPlacement()
+void PNS_ROUTER::ToggleViaPlacement(VIATYPE_T type)
 {
+    const int layercount = m_board->GetDesignSettings().GetCopperLayerCount();
+
+    // Cannot place microvias or blind vias if not allowed (obvious)
+    if( ( type == VIA_BLIND_BURIED ) && ( !m_board->GetDesignSettings().m_BlindBuriedViaAllowed ) )
+        return;
+    if( ( type == VIA_MICROVIA ) && ( !m_board->GetDesignSettings().m_MicroViasAllowed ) )
+        return;
+    
+    //Can only place through vias on 2-layer boards
+    if( ( type != VIA_THROUGH ) && ( layercount <= 2 ) )
+        return;
+    
+    //Can only place microvias if we're on an outer layer, or directly adjacent to one
+    if( ( type == VIA_MICROVIA ) && ( m_currentLayer > In1_Cu ) && ( m_currentLayer < layercount-2 ) )
+        return;
+    
+    //Cannot place blind vias with front/back as the layer pair, this doesn't make sense
+    if( ( type == VIA_BLIND_BURIED ) && ( Settings().GetLayerTop() == F_Cu ) && ( Settings().GetLayerBottom() == B_Cu ) )
+        return;
+    
     if( m_state == ROUTE_TRACK )
     {
         m_placingVia = !m_placingVia;
-        m_placer->AddVia( m_placingVia, m_settings.GetViaDiameter(), m_settings.GetViaDrill() );
+        m_placer->AddVia( m_placingVia, m_settings.GetViaDiameter(), m_settings.GetViaDrill(), type );
     }
 }
 

pcbnew/router/pns_router.h

@@ -112,7 +112,7 @@ public:
 
     void SwitchLayer( int layer );
 
-    void ToggleViaPlacement();
+    void ToggleViaPlacement( VIATYPE_T type = VIA_NOT_DEFINED );
 
     int GetCurrentLayer() const;
     int GetCurrentNet() const;

pcbnew/router/pns_routing_settings.h

@@ -129,7 +129,7 @@ public:
 
     void SetLayerPair( int aLayer1, int aLayer2 )
     {
-        if( aLayer1 > aLayer2 )
+        if( aLayer1 < aLayer2 )
         {
             m_layerTop = aLayer1;
             m_layerBottom = aLayer2;

pcbnew/router/pns_via.h

@@ -48,6 +48,13 @@ public:
         m_drill = aDrill;
         m_shape = SHAPE_CIRCLE( aPos, aDiameter / 2 );
         m_viaType = aViaType;
+        
+        //If we're a through-board via, use all layers regardless of the set passed
+        if( aViaType == VIA_THROUGH )
+        {
+            PNS_LAYERSET allLayers( 0, MAX_CU_LAYERS - 1 );
+            SetLayers( allLayers);
+        }
     }
 
 

pcbnew/router/router_tool.cpp

@@ -65,6 +65,12 @@ static TOOL_ACTION ACT_Drag( "pcbnew.InteractiveRouter.Drag",
 static TOOL_ACTION ACT_PlaceThroughVia( "pcbnew.InteractiveRouter.PlaceVia",
                                  AS_CONTEXT, 'V',
                                  "Place Through Via", "Adds a through-hole via at the end of currently routed track." );
+static TOOL_ACTION ACT_PlaceBlindVia( "pcbnew.InteractiveRouter.PlaceBlindVia",
+                                 AS_CONTEXT, 'Z',
+                                 "Place Blind/Buried Via", "Adds a blind or buried via at the end of currently routed track." );
+static TOOL_ACTION ACT_PlaceMicroVia( "pcbnew.InteractiveRouter.PlaceMicroVia",
+                                 AS_CONTEXT, 'Q',
+                                 "Place Microvia", "Adds a microvia at the end of currently routed track." );
 static TOOL_ACTION ACT_CustomTrackWidth( "pcbnew.InteractiveRouter.CustomTrackWidth",
                                       AS_CONTEXT, 'W',
                                       "Custom Track Width", "Shows a dialog for changing the track width and via size.");
@@ -209,6 +215,8 @@ public:
 //        Add( ACT_AutoEndRoute );  // fixme: not implemented yet. Sorry.
         Add( ACT_Drag );
         Add( ACT_PlaceThroughVia );
+        Add( ACT_PlaceBlindVia );
+        Add( ACT_PlaceMicroVia );
         Add( ACT_SwitchPosture );
 
         AppendSeparator();
@@ -580,7 +588,21 @@ void ROUTER_TOOL::performRouting()
         {
             m_router->Settings().SetLayerPair( frame->GetScreen()->m_Route_Layer_TOP,
                                                frame->GetScreen()->m_Route_Layer_BOTTOM );
-            m_router->ToggleViaPlacement();
+            m_router->ToggleViaPlacement( VIA_THROUGH );
+            m_router->Move( m_endSnapPoint, m_endItem );        // refresh
+        }
+        else if( evt->IsAction( &ACT_PlaceBlindVia ) )
+        {
+            m_router->Settings().SetLayerPair( frame->GetScreen()->m_Route_Layer_TOP,
+                                               frame->GetScreen()->m_Route_Layer_BOTTOM );
+            m_router->ToggleViaPlacement( VIA_BLIND_BURIED );
+            m_router->Move( m_endSnapPoint, m_endItem );        // refresh
+        }
+        else if( evt->IsAction( &ACT_PlaceMicroVia ) )
+        {
+            m_router->Settings().SetLayerPair( frame->GetScreen()->m_Route_Layer_TOP,
+                                               frame->GetScreen()->m_Route_Layer_BOTTOM );
+            m_router->ToggleViaPlacement( VIA_MICROVIA );
             m_router->Move( m_endSnapPoint, m_endItem );        // refresh
         }
         else if( evt->IsAction( &ACT_SwitchPosture ) )

pcbnew/scripting/board.i

@@ -35,22 +35,11 @@
     def GetModules(self):             return self.m_Modules
     def GetDrawings(self):            return self.m_Drawings
     def GetTracks(self):              return self.m_Track
-    def GetSegZones(self):            return self.m_Zone
     def GetFullRatsnest(self):        return self.m_FullRatsnest
-    def GetLocalRatsnest(self):       return self.m_LocalRatsnest
-    def GetNetClasses(self):          return self.m_NetClasses
-    def GetCurrentNetClassName(self): return self.m_CurrentNetClassName
-    def GetViasDimensionsList(self):  return self.m_ViasDimensionsList
-    def GetTrackWidthList(self):      return self.m_TrackWidthList
-
-    def Save(self,filename,format = None):
-      if format is None:
-        str_filename = str(filename)
-        if str_filename.endswith(".brd"):
-          format = IO_MGR.LEGACY
-        if str_filename.endswith(".kicad_pcb"):
-          format = IO_MGR.KICAD
-      return SaveBoard(filename,self,format)
+    def GetZones(self):               return self.m_ZoneDescriptorList
+
+    def Save(self,filename):
+        return SaveBoard(filename,self,IO_MGR.KICAD)
 
     #
     # add function, clears the thisown to avoid python from deleting
@@ -70,14 +59,12 @@
 %rename(Get) operator TRACK*;
 %rename(Get) operator D_PAD*;
 %rename(Get) operator MODULE*;
-%rename(Get) operator SEGZONE*;
 
 
 // we must translate C++ templates to scripting languages
 
 %template(BOARD_ITEM_List) DLIST<BOARD_ITEM>;
 %template(MODULE_List)     DLIST<MODULE>;
-%template(SEGZONE_List)    DLIST<SEGZONE>;
 %template(TRACK_List)      DLIST<TRACK>;
 %template(PAD_List)        DLIST<D_PAD>;
 
@@ -86,6 +73,25 @@
 %template(VIA_DIMENSION_Vector) std::vector<VIA_DIMENSION>;
 %template (RASTNET_Vector) std::vector<RATSNEST_ITEM>;
 
+%extend BOARD
+{
+        %pythoncode
+        {
+        def GetNetClasses(self):
+            return self.GetDesignSettings().m_NetClasses
+
+        def GetCurrentNetClassName(self):
+            return self.GetDesignSettings().m_CurrentNetClassName
+
+        def GetViasDimensionsList(self):
+            return self.GetDesignSettings().m_ViasDimensionsList
+
+        def GetTrackWidthList(self):
+            return self.GetDesignSettings().m_TrackWidthList
+        }
+}
+
+
 %extend DRAWSEGMENT
 {
 	%pythoncode

pcbnew/scripting/board_item.i

@@ -47,7 +47,7 @@
   EDGE_MODULE*      Cast_to_EDGE_MODULE()       {  return dynamic_cast<EDGE_MODULE*>(self);   }
   D_PAD*            Cast_to_D_PAD()             {  return dynamic_cast<D_PAD*>(self);         }
   TRACK*            Cast_to_TRACK()             {  return dynamic_cast<TRACK*>(self);         }
-  SEGZONE*      Cast_to_SEGZONE()       {  return dynamic_cast<SEGZONE*>(self);       }
+  ZONE_CONTAINER*   Cast_to_ZONE_CONTAINER()    {  return dynamic_cast<ZONE_CONTAINER*>(self);}
   VIA*              Cast_to_VIA()               {  return dynamic_cast<VIA*>(self);           }
 
 
@@ -73,12 +73,12 @@
         return self.Cast_to_D_PAD()
       elif ct=="MTEXT":
         return self.Cast_to_TEXTE_MODULE()
-      elif ct=="ZONE":
-        return self.Cast_to_SEGZONE()
       elif ct=="VIA":
         return self.Cast_to_VIA()
       elif ct=="TRACK":
         return self.Cast_to_TRACK()
+      elif ct=="ZONE_CONTAINER":
+        return self.Cast_to_ZONE_CONTAINER()
       else:
         return None
   }

pcbnew/scripting/examples/listPcb.py

@@ -6,15 +6,15 @@ filename=sys.argv[1]
 
 pcb = LoadBoard(filename)
 
-#ToUnits = ToMM 
-#FromUnits = FromMM 
-ToUnits=ToMils
-FromUnits=FromMils
+ToUnits = ToMM
+FromUnits = FromMM
+#ToUnits=ToMils
+#FromUnits=FromMils
 
 print "LISTING VIAS:"
 
 for item in pcb.GetTracks():
-	if type(item) is SEGVIA:
+	if type(item) is VIA:
 
 		pos = item.GetPosition()
 		drill = item.GetDrillValue()
@@ -33,7 +33,7 @@ for item in pcb.GetTracks():
 		print "Unknown type	%s" % type(item)
 
 print ""
-print "LISTING DRAWINGS:"
+print "LIST DRAWINGS:"
 
 for item in pcb.GetDrawings():
 	if type(item) is TEXTE_PCB:
@@ -50,14 +50,17 @@ for module in pcb.GetModules():
 	print "* Module: %s at %s"%(module.GetReference(),ToUnits(module.GetPosition()))
 
 print ""
-print "LIST ZONES:"
+print "Ratsnest cnt:",len(pcb.GetFullRatsnest())
+print "track w cnt:",len(pcb.GetTrackWidthList())
+print "via s cnt:",len(pcb.GetViasDimensionsList())
 
-for zone in pcb.GetSegZones():
-	print zone
+print ""
+print "LIST ZONES:"
 
+for idx in range(0, pcb.GetAreaCount()):
+    zone=pcb.GetArea(idx)
+    print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname()
 
 print ""
-print "RATSNEST:",len(pcb.GetFullRatsnest())
-
-print dir(pcb.GetNetClasses())
+print "NetClasses:", pcb.GetNetClasses().GetCount()
 

pcbnew/scripting/pcbnew.i

@@ -88,6 +88,7 @@
   #include <class_board.h>
   #include <class_module.h>
   #include <class_track.h>
+  #include <class_zone.h>
   #include <layers_id_colors_and_visibility.h>
   #include <class_pad.h>
   #include <pad_shapes.h>
@@ -123,6 +124,7 @@
 %include <class_board.h>
 %include <class_module.h>
 %include <class_track.h>
+%include <class_zone.h>
 %include <layers_id_colors_and_visibility.h>
 %include <class_pad.h>
 %include <pad_shapes.h>

pcbnew/scripting/units.i

@@ -27,8 +27,7 @@
  * @brief unit conversion code
  */
 
-// Unit conversion, must be conditionally adapter to the new 
-// nanometer mode that will be soon included in pcbnew
+// Unit conversion, between internal units and mm or mils
 
 %pythoncode
 {

pcbnew/tracepcb.cpp

@@ -255,14 +255,14 @@ void BOARD::DrawHighLight( EDA_DRAW_PANEL* am_canvas, wxDC* DC, int aNetCode )
     else
         draw_mode = GR_AND | GR_HIGHLIGHT;
 
-    // Redraw ZONE_CONTAINERS
-    BOARD::ZONE_CONTAINERS& zones = m_ZoneDescriptorList;
-
-    for( BOARD::ZONE_CONTAINERS::iterator zc = zones.begin(); zc!=zones.end(); ++zc )
+    // Redraw zones
+    for( int ii = 0; ii < GetAreaCount(); ii++ )
     {
-        if( (*zc)->GetNetCode() == aNetCode )
+        ZONE_CONTAINER* zone = GetArea( ii );
+
+        if( zone->GetNetCode() == aNetCode )
         {
-            (*zc)->Draw( am_canvas, DC, draw_mode );
+            zone->Draw( am_canvas, DC, draw_mode );
         }
     }