use LSET::any() whereever possible and avoid conversion to integral type

TODO.txt

@@ -60,6 +60,8 @@ PCBNew
 *)  Paste (module ...) from clipboard into module editor.
 
 
+
+
 Dick's Final TODO List:
 ======================
 *)  Get licensing cleaned up.
@@ -75,3 +77,10 @@ Dick's Final TODO List:
     *   Clear all/some? retained strings on project change.
     *   Clear the FP_LIB_TABLE when the last KIWAY_PLAYER using it is closed.
 
+
+Known Cu32 problems:
+
+*) layer combo box does not show the first layer numbered 0.
+*) ratsnest is broken
+
+

include/layers_id_colors_and_visibility.h

@@ -344,6 +344,7 @@ public:
     LAYER_ID ExtractLayer();
 
 private:
+
 };
 
 

pcbnew/class_track.cpp

@@ -398,6 +398,8 @@ LSET VIA::GetLayerSet() const
 
     LSET layermask;
 
+    wxASSERT( top_layer <= bottom_layer );
+
     // LAYER_IDs are numbered from front to back, this is top to bottom.
     for( LAYER_NUM id = top_layer;  id <= bottom_layer;  ++id )
     {
@@ -422,7 +424,7 @@ void VIA::SetLayerPair( LAYER_ID aTopLayer, LAYER_ID aBottomLayer )
         aBottomLayer = B_Cu;
     }
 
-    if( aBottomLayer > aTopLayer )
+    if( aBottomLayer < aTopLayer )
         EXCHG( aBottomLayer, aTopLayer );
 
     m_Layer = aTopLayer;
@@ -432,15 +434,15 @@ void VIA::SetLayerPair( LAYER_ID aTopLayer, LAYER_ID aBottomLayer )
 
 void VIA::LayerPair( LAYER_ID* top_layer, LAYER_ID* bottom_layer ) const
 {
-    LAYER_ID b_layer = B_Cu;
     LAYER_ID t_layer = F_Cu;
+    LAYER_ID b_layer = B_Cu;
 
     if( GetViaType() != VIA_THROUGH )
     {
         b_layer = m_BottomLayer;
         t_layer = m_Layer;
 
-        if( b_layer > t_layer )
+        if( b_layer < t_layer )
             EXCHG( b_layer, t_layer );
     }
 
@@ -615,6 +617,7 @@ void TRACK::DrawShortNetname( EDA_DRAW_PANEL* panel,
     }
 }
 
+
 void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
                   const wxPoint& aOffset )
 {
@@ -679,6 +682,7 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
     DrawShortNetname( panel, aDC, aDrawMode, color );
 }
 
+
 void SEGZONE::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
                     const wxPoint& aOffset )
 {

pcbnew/connect.cpp

@@ -75,7 +75,8 @@ void CONNECTIONS::SearchConnectionsPadsToIntersectingPads()
 
     for( unsigned ii = 0; ii < m_sortedPads.size(); ii++ )
     {
-        D_PAD * pad = m_sortedPads[ii];
+        D_PAD* pad = m_sortedPads[ii];
+
         pad->m_PadsConnected.clear();
         candidates.clear();
 
@@ -84,12 +85,14 @@ void CONNECTIONS::SearchConnectionsPadsToIntersectingPads()
         // add pads to pad.m_PadsConnected, if they are connected
         for( unsigned jj = 0; jj < candidates.size(); jj++ )
         {
-            CONNECTED_POINT * item = candidates[jj];
-            D_PAD * candidate_pad = item->GetPad();
+            CONNECTED_POINT* item = candidates[jj];
+
+            D_PAD* candidate_pad = item->GetPad();
+
             if( pad == candidate_pad )
                 continue;
 
-            if( (pad->GetLayerSet() & candidate_pad->GetLayerSet()) == 0 )
+            if( !( pad->GetLayerSet() & candidate_pad->GetLayerSet() ).any() )
                 continue;
             if( pad->HitTest( item->GetPoint() ) )
             {
@@ -122,7 +125,7 @@ void CONNECTIONS::SearchTracksConnectedToPads( bool add_to_padlist, bool add_to_
         {
             CONNECTED_POINT* cp_item = candidates[jj];
 
-            if( (pad->GetLayerSet() & cp_item->GetTrack()->GetLayerSet()) == 0 )
+            if( !( pad->GetLayerSet() & cp_item->GetTrack()->GetLayerSet() ).any() )
                 continue;
 
             if( pad->HitTest( cp_item->GetPoint() ) )
@@ -339,7 +342,7 @@ int CONNECTIONS::SearchConnectedTracks( const TRACK * aTrack )
         {
             TRACK * ctrack = tracks_candidates[ii]->GetTrack();
 
-            if( ( ctrack->GetLayerSet() & layerMask ) == 0 )
+            if( !( ctrack->GetLayerSet() & layerMask ).any() )
                 continue;
 
             if( ctrack == aTrack )

pcbnew/dragsegm.cpp

@@ -345,7 +345,7 @@ void Collect_TrackSegmentsToDrag( BOARD* aPcb, const wxPoint& aRefPos, LSET aLay
         if( track->GetNetCode() != aNetCode )   // not the same netcode: all candidates tested
             break;
 
-        if( ( aLayerMask & track->GetLayerSet() ) == 0 )
+        if( !( aLayerMask & track->GetLayerSet() ).any() )
             continue;                       // Cannot be connected, not on the same layer
 
         if( track->IsDragging() )

pcbnew/drc_clearance_test_functions.cpp

@@ -354,7 +354,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
             continue;
 
         // No problem if segment are on different layers :
-        if( ( layerMask & track->GetLayerSet() ) == 0 )
+        if( !( layerMask & track->GetLayerSet() ).any() )
             continue;
 
         // the minimum distance = clearance plus half the reference track

pcbnew/legacy_plugin.cpp

@@ -2356,7 +2356,6 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType )
         newTrack->SetEnd( wxPoint( end_x, end_y ) );
 
         newTrack->SetWidth( width );
-        newTrack->SetLayer( leg_layer2new( m_cu_count,  layer_num ) );
 
         if( makeType == PCB_VIA_T )     // Ensure layers are OK when possible:
         {
@@ -2370,6 +2369,17 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType )
 
             if( via->GetViaType() == VIA_THROUGH )
                 via->SetLayerPair( F_Cu, B_Cu );
+            else
+            {
+                LAYER_ID  back  = leg_layer2new( m_cu_count, (layer_num >> 4) & 0xf );
+                LAYER_ID  front = leg_layer2new( m_cu_count, layer_num & 0xf );
+
+                via->SetLayerPair( front, back );
+            }
+        }
+        else
+        {
+            newTrack->SetLayer( leg_layer2new( m_cu_count, layer_num ) );
         }
 
         newTrack->SetNetCode( getNetCode( net_code ) );