Commit 7693e34e authored by dickelbeck's avatar dickelbeck
Browse files

fixed compilation errors with VIA symbols

parent ab436f0a

gerbview/export_to_pcbnew.cpp

+3 −3
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File, 


                // A spot is found, and can be a via: change it to via, and delete other

                // spots at same location

                newtrack->m_Shape = VIA_NORMALE;

                newtrack->m_Shape = VIA_THROUGH;

                

                newtrack->SetLayer( 0x0F );  // Layers are 0 to 15 (Cu/Cmp)
@@ -205,7 +205,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File, 
    // delete redundant vias

    for( track = Pcb->m_Track; track != NULL; track = track->Next() )

    {

        if( track->m_Shape != VIA_NORMALE )

        if( track->m_Shape != VIA_THROUGH )

            continue;

        

        // Search and delete others vias
@@ -213,7 +213,7 @@ static int SavePcbFormatAscii( WinEDA_GerberFrame* frame, FILE* File, 
        for( ; alt_track != NULL; alt_track = next_track )

        {

            next_track = alt_track->Next();

            if( alt_track->m_Shape != VIA_NORMALE )

            if( alt_track->m_Shape != VIA_THROUGH )

                continue;



            if( alt_track->m_Start != track->m_Start )

pcbnew/class_board_item.cpp

+3 −3
Original line number Diff line number Diff line
@@ -170,9 +170,9 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const 
            text << _( "Via" ) << wxT( " " ) << via->ShowWidth();

            

            int shape = via->Shape(); 

            if( shape == BURIED_VIA )

            if( shape == VIA_BURIED )

                text << wxT(" ") << _( "Blind" );

            else if( shape == BLIND_VIA )

            else if( shape == VIA_BLIND )

                text << wxT(" ") << _("Buried");

            // else say nothing about normal vias
@@ -182,7 +182,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const 
                text << wxT( " [" ) << net->m_Netname << wxT( "]" );

            }

            

            if( shape != THROUGH_VIA )

            if( shape != VIA_THROUGH )

            {

                // say which layers, only two for now

                int topLayer;

pcbnew/class_track.cpp

+7 −6
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include "common.h"

#include "pcbnew.h"





#ifdef CVPCB

#include "cvpcb.h"

#endif
@@ -264,10 +265,10 @@ int TRACK::ReturnMaskLayer() 
    {

        int via_type = Shape();



        if( via_type == THROUGH_VIA )

        if( via_type == VIA_THROUGH )

            return ALL_CU_LAYERS;



        // BLIND_VIA ou  BURIED_VIA:

        // VIA_BLIND ou  VIA_BURIED:



        int bottom_layer, top_layer;
@@ -302,7 +303,7 @@ void SEGVIA::SetLayerPair( int top_layer, int bottom_layer ) 
{

    int via_type = Shape();



    if( via_type == THROUGH_VIA )

    if( via_type == VIA_THROUGH )

    {

        top_layer    = LAYER_CMP_N;

        bottom_layer = COPPER_LAYER_N;
@@ -903,15 +904,15 @@ void SEGVIA::Show( int nestLevel, std::ostream& os ) 


    switch( Shape() )

    {

    case THROUGH_VIA:

    case VIA_THROUGH:

        cp = "through";

        break;



    case BURIED_VIA:

    case VIA_BURIED:

        cp = "blind";

        break;



    case BLIND_VIA:

    case VIA_BLIND:

        cp = "buried";

        break;

pcbnew/class_track.h

+5 −5
Original line number Diff line number Diff line
@@ -9,11 +9,11 @@ 




// Via attributes (m_Shape parmeter)

#define THROUGH_VIA      3              /* Always a through hole via */

#define BURIED_VIA       2              /* this via can be on internal layers */

#define BLIND_VIA        1              /* this via which connect from internal layers to an external layer */

#define NOT_DEFINED_VIA  0              /* reserved (unused) */

#define SQUARE_VIA_SHAPE 0x80000000     /* Flag pour forme carree */

#define VIA_THROUGH      3              /* Always a through hole via */

#define VIA_BURIED       2              /* this via can be on internal layers */

#define VIA_BLIND        1              /* this via which connect from internal layers to an external layer */

#define VIA_NOT_DEFINED  0              /* reserved (unused) */

#define VIA_SQUARE_SHAPE 0x80000000     /* Flag pour forme carree */



/***/

pcbnew/classpcb.cpp

+4 −4
Original line number Diff line number Diff line
@@ -433,7 +433,7 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() 
    m_CopperLayerCount = 2;             // Default design is a double sided board

    m_ViaDrill = 250;                   // via drill (for the entire board)

    m_CurrentViaSize    = 450;          // Current via size

    m_CurrentViaType    = THROUGH_VIA;  /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/

    m_CurrentViaType    = VIA_THROUGH;  /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/

    m_CurrentTrackWidth = 170;          // current track width

    for( ii = 0; ii < HIST0RY_NUMBER; ii++ )

    {
@@ -454,9 +454,9 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() 
        m_LayerColor[ii] = default_layer_color[ii];



    // Layer colors (tracks and graphic items)

    m_ViaColor[BLIND_VIA]   = CYAN;

    m_ViaColor[BURIED_VIA] = BROWN;

    m_ViaColor[THROUGH_VIA]  = WHITE;

    m_ViaColor[VIA_BLIND]   = CYAN;

    m_ViaColor[VIA_BURIED] = BROWN;

    m_ViaColor[VIA_THROUGH]  = WHITE;

    m_ModuleTextCMPColor = LIGHTGRAY;   // Text module color for modules on the COMPONENT layer

    m_ModuleTextCUColor  = MAGENTA;     // Text module color for modules on the COPPER layer

    m_ModuleTextNOVColor = DARKGRAY;    // Text module color for "invisible" texts (must be BLACK if really not displayed)