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Commit 5c3f35c2 authored by dickelbeck's avatar dickelbeck
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beautification in preparation for netclass work.

parent 514de91e
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Showing with 84 additions and 54 deletions
include/wxPcbStruct.h
View file @ 5c3f35c2
......@@ -743,6 +743,16 @@ public:
void Load_Module_From_BOARD( MODULE* Module );
// functions to edit footprint edges
/**
* Function Edit_Edge_Width
* changes the width of module perimeter lines, EDGE_MODULEs.
* @param ModuleSegmentWidth (global) = new width
* @param Edge = edge to edit, or NULL. If Edge == NULL change
* the width of all the footprint's edges
* @param DC = current Device Context
*/
void Edit_Edge_Width( EDGE_MODULE* Edge );
void Edit_Edge_Layer( EDGE_MODULE* Edge );
void Delete_Edge_Module( EDGE_MODULE* Edge );
......
pcbnew/class_board.cpp
View file @ 5c3f35c2
......@@ -19,7 +19,8 @@ wxPoint BOARD_ITEM::ZeroOffset( 0, 0 );
/* Constructor */
BOARD::BOARD( EDA_BaseStruct* parent, WinEDA_BasePcbFrame* frame ) :
BOARD_ITEM( (BOARD_ITEM*)parent, TYPE_PCB )
BOARD_ITEM( (BOARD_ITEM*)parent, TYPE_PCB ),
m_NetClassesList(this)
{
m_PcbFrame = frame;
m_Status_Pcb = 0; // Mot d'etat: Bit 1 = Chevelu calcule
......@@ -38,7 +39,6 @@ BOARD::BOARD( EDA_BaseStruct* parent, WinEDA_BasePcbFrame* frame ) :
}
// Add the default Netclass to list
m_NetClassesList.m_Parent = this;
NETCLASS * default_netclass = new NETCLASS(this);
m_NetClassesList.AddNetclass( default_netclass );
}
......@@ -826,12 +826,14 @@ NETINFO_ITEM* BOARD::FindNet( int anetcode ) const
// zero is reserved for "no connection" and is not used.
// NULL is returned for non valid netcodes
NETINFO_ITEM* item = m_NetInfo->GetNetItem( anetcode );
#if defined(DEBUG)
if ( item ) // item can be NULL if not valid
if ( item ) // item can be NULL if anetcode is not valid
{
wxASSERT( anetcode == item->GetNet() );
}
#endif
return item;
}
......@@ -910,16 +912,18 @@ int BOARD::ReturnSortedNetnamesList( wxArrayString& aNames, bool aSortbyPadsCoun
if( m_NetInfo->GetNetsCount() == 0 )
return 0;
/* Build the list */
// Build the list
std::vector <NETINFO_ITEM*> netBuffer;
netBuffer.reserve( m_NetInfo->GetNetsCount() );
for( unsigned ii = 1; ii < m_NetInfo->GetNetsCount(); ii++ )
{
if( m_NetInfo->GetNetItem( ii )->GetNet() > 0 )
netBuffer.push_back( m_NetInfo->GetNetItem( ii ) );
}
/* sort the list */
// sort the list
if( aSortbyPadsCount )
sort( netBuffer.begin(), netBuffer.end(), s_SortByNodes );
......
pcbnew/class_board.h
View file @ 5c3f35c2
......@@ -98,6 +98,7 @@ public:
* (used while moving a footprint) */
NETCLASS_LIST m_NetClassesList; // List of current netclasses. There is always the default netclass
ZONE_CONTAINER* m_CurrentZoneContour; // zone contour currently in progress
BOARD( EDA_BaseStruct* aParent, WinEDA_BasePcbFrame* frame );
......@@ -338,14 +339,14 @@ public:
/**
* Function TransfertDesignRulesToNets
* Copy Netclass parameters to each net, corresponding to its net class
* copies Netclass parameters to each net, corresponding to its net class.
* Must be called after a Design Rules edition, or after reading a netlist (or editing the list of nets)
* Also this function remove the non existing nets in netclasses and add net nets in default netclass
* Also this function removes the non existing nets in netclasses and add net nets in default netclass
* (this happens after reading a netlist)
* @param none
* @return none
*/
void TransfertDesignRulesToNets( );
void TransfertDesignRulesToNets();
/**
* Function Save
......
pcbnew/class_netclass.cpp
View file @ 5c3f35c2
......@@ -77,15 +77,6 @@ bool NETCLASS_LIST::AddNetclass( NETCLASS* aNetclass )
}
/**
* Function TransfertDesignRulesToNets
* Copy Netclass parameters to each net, corresponding to its net class
* Must be called after a Design Rules edition, or after reading a netlist (or editing the list of nets)
* Also this function remove the non existing nets in netclasses and add net nets in default netclass
* (this happens after reading a netlist)
* @param none
* @return none
*/
void BOARD::TransfertDesignRulesToNets()
{
// Clear .m_Flag member of nets (used to detect not in netclass list nets)
......@@ -94,17 +85,20 @@ void BOARD::TransfertDesignRulesToNets()
NETINFO_ITEM* net = FindNet( ii );
if( net == NULL )
break;
net->m_Flag = 0;
}
for( unsigned ii = 0; ii < m_NetClassesList.m_Netclass_List.size(); ii++ )
for( unsigned ii = 0; ii < m_NetClassesList.GetNetClassCount(); ii++ )
{
//Transfert rules and netclass name to nets:
NETCLASS* netclass = m_NetClassesList.m_Netclass_List[ii];
// Transfert rules and netclass name to nets:
NETCLASS* netclass = m_NetClassesList.GetNetClass( ii );
for( unsigned jj = 0; jj < netclass->GetMembersCount(); jj++ )
{
wxString netname = netclass->GetMemberName( jj );
NETINFO_ITEM* net = FindNet( netname );
if( net == NULL ) // This net does not exists: remove it
{
netclass->m_MembersNetNames.RemoveAt( jj );
......@@ -119,12 +113,15 @@ void BOARD::TransfertDesignRulesToNets()
}
// Now, set nets that do not have yet a netclass to default netclass
NETCLASS* defaultnetclass = m_NetClassesList.m_Netclass_List[0];
NETCLASS* defaultnetclass = m_NetClassesList.GetNetClass( 0 );
for( unsigned ii = 1; ; ii++ )
{
NETINFO_ITEM* net = FindNet( ii );
if( net == NULL )
break;
if( net->m_Flag == 0 )
{
net->SetClass( *defaultnetclass );
......@@ -175,7 +172,6 @@ bool NETCLASS::Save( FILE* aFile ) const
for( unsigned ii = 0; ii < GetMembersCount(); ii++ )
fprintf( aFile, "AddNet \"%s\"\n", CONV_TO_UTF8( GetMemberName( ii ) ) );
fprintf( aFile, "$EndNETCLASS\n" );
return success;
......
pcbnew/class_netclass.h
View file @ 5c3f35c2
......@@ -2,12 +2,19 @@
/* class to Net Classes */
/**************************************/
#ifndef CLASS_NETCLASS_H
#define CLASS_NETCLASS_H
/* this small class NET_DESIGN_PARAMS handles netclass parameters.
/**
* Class NET_DESIGN_PARAMS
* handles netclass parameters.
*
* This is a separate class because these parameters are also duplicated
* (for calculation time consideration) in each NETINFO_ITEM when making tests DRC and routing
* (for calculation time consideration) in each NETINFO_ITEM when making
* tests DRC and routing
*/
class NET_DESIGN_PARAMS
{
......@@ -18,9 +25,11 @@ public:
int m_ViasMinSize; // Minimum value for vias sizes (used in DRC)
int m_Clearance; // "Default" clearance when routing
int m_MinClearance; // Minimum value for clearance (used in DRC)
public:
NET_DESIGN_PARAMS();
~NET_DESIGN_PARAMS() {}
// ~NET_DESIGN_PARAMS() {}
/**
* Function Save
......@@ -30,6 +39,7 @@ public:
*/
bool Save( FILE* aFile ) const;
/**
* Function ReadDescr
* reads the data structures for this object from a FILE in "*.brd" format.
......@@ -39,8 +49,10 @@ public:
bool ReadDescr( FILE* aFile, int* aLineNum );
};
/**
* @info A NETCLASS handles a list of nets and the parameters used to route or test these nets
* Class NETCLASS
* handles a list of nets and the parameters used to route or test these nets
*/
class NETCLASS
{
......@@ -50,12 +62,14 @@ public:
wxArrayString m_MembersNetNames; // List of nets members of this class
NET_DESIGN_PARAMS m_NetParams; // values of net classes parameters
public:
NETCLASS( BOARD* aParent, const wxString& aName = wxT( "default" ) );
~NETCLASS();
/** Function GetMembersCount
*@return the number of nets using this rule
/**
* Function GetMembersCount
* returns the number of nets using this rule
*/
unsigned GetMembersCount() const
{
......@@ -101,21 +115,27 @@ public:
bool ReadDescr( FILE* aFile, int* aLineNum );
};
/* This NETCLASS_LIST handles the list of NETCLASS for the board
/**
* Class NETCLASS_LIST handles the list of NETCLASS for the board
* Note: the NETCLASS_LIST is owner of all NETCLASS in list
*/
class NETCLASS_LIST
{
public:
protected:
BOARD* m_Parent;
std::vector <NETCLASS*> m_Netclass_List;
public:
NETCLASS_LIST( BOARD* aParent = NULL );
~NETCLASS_LIST();
void ClearList();
/** Function GetNetClassCount()
/**
* Function GetNetClassCount()
* @return the number of existing netclasses
*/
unsigned GetNetClassCount()
......@@ -153,4 +173,4 @@ public:
};
#endif // #ifndef CLASS_NETCLASS_H
#endif // CLASS_NETCLASS_H
pcbnew/class_netinfo.h
View file @ 5c3f35c2
......@@ -142,10 +142,11 @@ private:
void Build_Pads_Full_List();
};
/** class NETINFO_ITEM
* @info This class handle the data relative to a given net
*/
/**
* Class NETINFO_ITEM
* handles the data for a net
*/
class NETINFO_ITEM
{
private:
......@@ -153,9 +154,9 @@ private:
// Used for fast comparisons in rastnest and DRC computations.
wxString m_Netname; // Full net name like /mysheet/mysubsheet/vout used by eeschema
wxString m_ShortNetname; // short net name, like vout from /mysheet/mysubsheet/vout
wxString m_NetClassName; /* Net Class name. if void this is equivalent to "default" (the first
* item of the net classes list
*/
wxString m_NetClassName; // Net Class name. if void this is equivalent to "default" (the first
// item of the net classes list
NET_DESIGN_PARAMS m_NetParams; // values of net classes parameters
......@@ -164,10 +165,13 @@ public:
int m_NbLink; // Ratsnets count for this net
int m_NbNoconn; // Ratsnets remaining to route count
int m_Flag; // used in some calculations. Had no special meaning
std::vector <D_PAD*> m_ListPad; // List of pads connected to this net
unsigned m_RatsnestStartIdx; /* Starting point of ratsnests of this net (included)
* in a general buffer of ratsnest (a vector<RATSNEST_ITEM*> buffer)
*/
unsigned m_RatsnestEndIdx; // Ending point of ratsnests of this net (excluded) in this buffer
NETINFO_ITEM( BOARD_ITEM* aParent );
......
pcbnew/class_netinfo_item.cpp
View file @ 5c3f35c2
......@@ -60,7 +60,7 @@ int NETINFO_ITEM:: ReadDescr( FILE* File, int* LineNum )
continue;
}
if( strncmp( Line, "NetClass", 8 ) == 0 ) /* Net Class */
if( strncmp( Line, "NetClass", 8 ) == 0 )
{
ReadDelimitedText( Ltmp, Line + 8, sizeof(Ltmp) );
m_NetClassName = CONV_FROM_UTF8( Ltmp );
......
pcbnew/edgemod.cpp
View file @ 5c3f35c2
......@@ -139,13 +139,6 @@ static void ShowEdgeModule( WinEDA_DrawPanel* panel, wxDC* DC, bool erase )
/***************************************************************************/
void WinEDA_ModuleEditFrame::Edit_Edge_Width( EDGE_MODULE* Edge )
/***************************************************************************/
/* Change the EDGE_MODULE Edge width,
* if Edge == NULL change the width of the entire footprint edges
* @param ModuleSegmentWidth (global) = new width
* @param Edge = edge to edit, or NULL
* @param DC = current Device Context
*/
{
MODULE* Module = GetBoard()->m_Modules;
......
pcbnew/ioascii.cpp
View file @ 5c3f35c2
......@@ -837,8 +837,10 @@ int WinEDA_PcbFrame::ReadPcbFile( FILE* File, bool Append )
{
NETCLASS* netclass = new NETCLASS( GetBoard() );
netclass->ReadDescr( File, &LineNum );
if( ! GetBoard()->m_NetClassesList.AddNetclass( netclass ) )
delete netclass;
continue;
}
......
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