Showing net names on pads. (3841b0ac) · Commits · Elphel / kicad-source-mirror

include/layers_id_colors_and_visibility.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -216,8 +216,9 @@ enum PCB_VISIBLE
		TRACKS_VISIBLE,
		TRACKS_NETNAMES_VISIBLE,
		PADS_VISIBLE,
		VIA_HOLES_VISIBLE,
		PAD_HOLES_VISIBLE,
		PADS_NETNAMES_VISIBLE,
		PADS_HOLES_VISIBLE,
		VIAS_HOLES_VISIBLE,

		END_PCB_VISIBLE_LIST // sentinel
		};

pcbnew/basepcbframe.cpp

+3 −1

Original line number	Diff line number	Diff line
		@@ -94,7 +94,8 @@ const int m_galLayerOrder[] =
		ITEM_GAL_LAYER( MOD_REFERENCES_VISIBLE), ITEM_GAL_LAYER( MOD_VALUES_VISIBLE ),
		SILKSCREEN_N_FRONT, SOLDERPASTE_N_FRONT, ADHESIVE_N_FRONT, SOLDERMASK_N_FRONT,

		ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ), ITEM_GAL_LAYER( PAD_HOLES_VISIBLE ),
		ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
		ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),
		ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),

		ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ),
		@@ -227,6 +228,7 @@ void PCB_BASE_FRAME::SetBoard( BOARD* aBoard )
		// Netnames are drawn only when scale is sufficient (level of details)
		// so there is no point in caching them
		view->SetLayerCached( ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), false );
		view->SetLayerCached( ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ), false );

		// Load layer & elements visibility settings
		for( unsigned int i = 0; i < NB_LAYERS; ++i )

pcbnew/class_pad.cpp

+33 −11

Original line number	Diff line number	Diff line
		@@ -746,36 +746,36 @@ EDA_ITEM* D_PAD::Clone() const

		void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
		{
		aCount = 0;

		if( m_Attribute == PAD_SMD \|\| m_Attribute == PAD_CONN )
		{
		// Single layer pad (smd) without hole
		if( IsOnLayer( LAYER_N_FRONT ) )
		aLayers[0] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
		else if( IsOnLayer( LAYER_N_BACK ) )
		aLayers[0] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
		#ifdef __WXDEBUG__
		else // Should not occur
		{
		wxLogWarning( wxT("D_PAD::ViewGetLayers():PAD on layer different than FRONT/BACK") );
		}
		#endif

		aCount = 1;
		}
		else
		{
		if( IsOnLayer( LAYER_N_FRONT ) && IsOnLayer( LAYER_N_BACK ) )
		{
		// Multi layer pad
		aLayers[0] = ITEM_GAL_LAYER( PADS_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PADS_VISIBLE );
		}
		else if( IsOnLayer( LAYER_N_FRONT ) )
		{
		aLayers[0] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
		}
		else if( IsOnLayer( LAYER_N_BACK ) )
		{
		aLayers[0] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
		}
		#ifdef __WXDEBUG__
		else // Should not occur
		@@ -785,9 +785,31 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
		#endif

		// Draw a hole
		aLayers[1] = ITEM_GAL_LAYER( PAD_HOLES_VISIBLE );
		aLayers[aCount++] = ITEM_GAL_LAYER( PADS_HOLES_VISIBLE );
		}

		// Pad description layer (number & net)
		aLayers[aCount++] = ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE );
		}


		void D_PAD::ViewGetRequiredLayers( int aLayers[], int& aCount ) const
		{
		ViewGetLayers( aLayers, aCount );

		aCount = 2;
		// Remove pad description layer from the required layers group
		aCount--;
		}


		unsigned int D_PAD::ViewGetLOD( int aLayer ) const
		{
		// Netnames will be shown only if zoom is appropriate
		if( aLayer == ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ) )
		{
		return ( 100000000 / std::max( m_Size.x, m_Size.y ) );
		}

		// Other layers are shown without any conditions
		return 0;
		}

pcbnew/class_pad.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -433,6 +433,12 @@ public:
		/// @copydoc VIEW_ITEM::ViewGetLayers()
		virtual void ViewGetLayers( int aLayers[], int& aCount ) const;

		/// @copydoc VIEW_ITEM::ViewGetRequiredLayers()
		virtual void ViewGetRequiredLayers( int aLayers[], int& aCount ) const;

		/// @copydoc VIEW_ITEM::ViewGetLOD()
		virtual unsigned int ViewGetLOD( int aLayer ) const;

		/**
		* Function CopyNetlistSettings
		* copies the netlist settings to \a aPad.

pcbnew/class_track.cpp

+1 −1

Original line number	Diff line number	Diff line
		@@ -996,7 +996,7 @@ void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const
		{
		// Just show it on common via & via holes layers
		aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE );
		aLayers[1] = ITEM_GAL_LAYER( VIA_HOLES_VISIBLE );
		aLayers[1] = ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE );
		aCount = 2;
		}

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