Loading pcbnew/ratsnest_data.cpp +20 −6 Original line number Original line Diff line number Diff line Loading @@ -801,26 +801,40 @@ void RN_DATA::ProcessBoard() { { m_nets.clear(); m_nets.clear(); m_nets.resize( m_board->GetNetCount() ); m_nets.resize( m_board->GetNetCount() ); int netCode; // Iterate over all items that may need to be connected // Iterate over all items that may need to be connected for( MODULE* module = m_board->m_Modules; module; module = module->Next() ) for( MODULE* module = m_board->m_Modules; module; module = module->Next() ) { { for( D_PAD* pad = module->Pads().GetFirst(); pad; pad = pad->Next() ) for( D_PAD* pad = module->Pads().GetFirst(); pad; pad = pad->Next() ) m_nets[pad->GetNet()].AddItem( pad ); { netCode = pad->GetNet(); if( netCode > 0 ) m_nets[netCode].AddItem( pad ); } } } for( TRACK* track = m_board->m_Track; track; track = track->Next() ) for( TRACK* track = m_board->m_Track; track; track = track->Next() ) { netCode = track->GetNet(); if( netCode > 0 ) { { if( track->Type() == PCB_VIA_T ) if( track->Type() == PCB_VIA_T ) m_nets[track->GetNet()].AddItem( static_cast<SEGVIA*>( track ) ); m_nets[netCode].AddItem( static_cast<SEGVIA*>( track ) ); else if( track->Type() == PCB_TRACE_T ) else if( track->Type() == PCB_TRACE_T ) m_nets[track->GetNet()].AddItem( track ); m_nets[netCode].AddItem( track ); } } } for( int i = 0; i < m_board->GetAreaCount(); ++i ) for( int i = 0; i < m_board->GetAreaCount(); ++i ) { { ZONE_CONTAINER* zone = m_board->GetArea( i ); ZONE_CONTAINER* zone = m_board->GetArea( i ); m_nets[zone->GetNet()].AddItem( zone ); netCode = zone->GetNet(); if( netCode > 0 ) m_nets[netCode].AddItem( zone ); } } } } Loading Loading
pcbnew/ratsnest_data.cpp +20 −6 Original line number Original line Diff line number Diff line Loading @@ -801,26 +801,40 @@ void RN_DATA::ProcessBoard() { { m_nets.clear(); m_nets.clear(); m_nets.resize( m_board->GetNetCount() ); m_nets.resize( m_board->GetNetCount() ); int netCode; // Iterate over all items that may need to be connected // Iterate over all items that may need to be connected for( MODULE* module = m_board->m_Modules; module; module = module->Next() ) for( MODULE* module = m_board->m_Modules; module; module = module->Next() ) { { for( D_PAD* pad = module->Pads().GetFirst(); pad; pad = pad->Next() ) for( D_PAD* pad = module->Pads().GetFirst(); pad; pad = pad->Next() ) m_nets[pad->GetNet()].AddItem( pad ); { netCode = pad->GetNet(); if( netCode > 0 ) m_nets[netCode].AddItem( pad ); } } } for( TRACK* track = m_board->m_Track; track; track = track->Next() ) for( TRACK* track = m_board->m_Track; track; track = track->Next() ) { netCode = track->GetNet(); if( netCode > 0 ) { { if( track->Type() == PCB_VIA_T ) if( track->Type() == PCB_VIA_T ) m_nets[track->GetNet()].AddItem( static_cast<SEGVIA*>( track ) ); m_nets[netCode].AddItem( static_cast<SEGVIA*>( track ) ); else if( track->Type() == PCB_TRACE_T ) else if( track->Type() == PCB_TRACE_T ) m_nets[track->GetNet()].AddItem( track ); m_nets[netCode].AddItem( track ); } } } for( int i = 0; i < m_board->GetAreaCount(); ++i ) for( int i = 0; i < m_board->GetAreaCount(); ++i ) { { ZONE_CONTAINER* zone = m_board->GetArea( i ); ZONE_CONTAINER* zone = m_board->GetArea( i ); m_nets[zone->GetNet()].AddItem( zone ); netCode = zone->GetNet(); if( netCode > 0 ) m_nets[netCode].AddItem( zone ); } } } } Loading