Skip to content

G
gtxe2_gpl
Commit 9b371aa6 authored by Alexey Grebenkin's avatar Alexey Grebenkin
Browse files
Options

Initial files with license agreement

parent 886f1771
Show whitespace changes
Inline Side-by-side
Showing with 1609 additions and 1559 deletions
README.md
View file @ 9b371aa6
# gtxe2_nosecureip
GTXE2_CHANNEL_GPL.v is a non-synthesizable open-source replacement for a propriate xilinx's primitive GTXE2_CHANNEL.v
For now only basic features are implemented : OOB, comma aligment, 10-8 encoding/decoding, clocking scheme.
Still, that is enough to run SATA protocol implementation simulation.
gtxe2_channel/GTXE2_CHANNEL.v deleted 100644 → 0
View file @ 886f1771
`include "gtxe2_chnl.v"
module GTXE2_CHANNEL(
//------------------------------- CPLL Ports -------------------------------
output CPLLFBCLKLOST , //(cpllfbclklost_out),
output CPLLLOCK , //(cplllock_out),
input CPLLLOCKDETCLK , //(cplllockdetclk_in),
input CPLLLOCKEN , //(tied_to_vcc_i),
input CPLLPD , //(cpll_pd_i),
output CPLLREFCLKLOST , //(cpllrefclklost_out),
input [2:0] CPLLREFCLKSEL , //(3'b001),
input CPLLRESET , //(cpll_reset_i),
input [15:0] GTRSVD , //(16'b0000000000000000),
input [15:0] PCSRSVDIN , //(16'b0000000000000000),
input [4:0] PCSRSVDIN2 , //(5'b00000),
input [4:0] PMARSVDIN , //(5'b00000),
input [4:0] PMARSVDIN2 , //(5'b00000),
input [19:0] TSTIN , //(20'b11111111111111111111),
output [9:0] TSTOUT , //(),
//-------------------------------- Channel ---------------------------------
input [3:0] CLKRSVD , //(4'b0000),
//------------------------ Channel - Clocking Ports ------------------------
input GTGREFCLK , //(tied_to_ground_i),
input GTNORTHREFCLK0 , //(tied_to_ground_i),
input GTNORTHREFCLK1 , //(tied_to_ground_i),
input GTREFCLK0 , //(gtrefclk0_in),
input GTREFCLK1 , //(tied_to_ground_i),
input GTSOUTHREFCLK0 , //(tied_to_ground_i),
input GTSOUTHREFCLK1 , //(tied_to_ground_i),
//-------------------------- Channel - DRP Ports --------------------------
input [8:0] DRPADDR , //(drpaddr_in),
input DRPCLK , //(drpclk_in),
input [15:0] DRPDI , //(drpdi_in),
output [15:0] DRPDO , //(drpdo_out),
input DRPEN , //(drpen_in),
output DRPRDY , //(drprdy_out),
input DRPWE , //(drpwe_in),
//----------------------------- Clocking Ports -----------------------------
output GTREFCLKMONITOR , //(),
input QPLLCLK , //(qpllclk_in),
input QPLLREFCLK , //(qpllrefclk_in),
input [1:0] RXSYSCLKSEL , //(2'b00),
input [1:0] TXSYSCLKSEL , //(2'b00),
//------------------------- Digital Monitor Ports --------------------------
output [7:0] DMONITOROUT , //(dmonitorout_out),
//--------------- FPGA TX Interface Datapath Configuration ----------------
input TX8B10BEN , //(tied_to_vcc_i),
//----------------------------- Loopback Ports -----------------------------
input [2:0] LOOPBACK , //(tied_to_ground_vec_i[2:0]),
//--------------------------- PCI Express Ports ----------------------------
output PHYSTATUS , //(),
input [2:0] RXRATE , //(tied_to_ground_vec_i[2:0]),
output RXVALID , //(),
//---------------------------- Power-Down Ports ----------------------------
input [1:0] RXPD , //(2'b00),
input [1:0] TXPD , //(2'b00),
//------------------------ RX 8B/10B Decoder Ports -------------------------
input SETERRSTATUS , //(tied_to_ground_i),
//------------------- RX Initialization and Reset Ports --------------------
input EYESCANRESET , //(eyescanreset_in),
input RXUSERRDY , //(rxuserrdy_in),
//------------------------ RX Margin Analysis Ports ------------------------
output EYESCANDATAERROR , //(eyescandataerror_out),
input EYESCANMODE , //(tied_to_ground_i),
input EYESCANTRIGGER , //(eyescantrigger_in),
//----------------------- Receive Ports - CDR Ports ------------------------
input RXCDRFREQRESET , //(tied_to_ground_i),
input RXCDRHOLD , //(tied_to_ground_i),
output RXCDRLOCK , //(),
input RXCDROVRDEN , //(tied_to_ground_i),
input RXCDRRESET , //(tied_to_ground_i),
input RXCDRRESETRSV , //(tied_to_ground_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] RXCLKCORCNT , //(),
//-------- Receive Ports - FPGA RX Interface Datapath Configuration --------
input RX8B10BEN , //(tied_to_vcc_i),
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
input RXUSRCLK , //(rxusrclk_in),
input RXUSRCLK2 , //(rxusrclk2_in),
//---------------- Receive Ports - FPGA RX interface Ports -----------------
output [63:0] RXDATA , //(rxdata_i),
//----------------- Receive Ports - Pattern Checker Ports ------------------
output RXPRBSERR , //(),
input [2:0] RXPRBSSEL , //(tied_to_ground_vec_i[2:0]),
//----------------- Receive Ports - Pattern Checker ports ------------------
input RXPRBSCNTRESET , //(tied_to_ground_i),
//------------------ Receive Ports - RX Equalizer Ports -------------------
input RXDFEXYDEN , //(tied_to_vcc_i),
input RXDFEXYDHOLD , //(tied_to_ground_i),
input RXDFEXYDOVRDEN , //(tied_to_ground_i),
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
output [7:0] RXDISPERR , //({rxdisperr_float_i,rxdisperr_out}),
output [7:0] RXNOTINTABLE , //({rxnotintable_float_i,rxnotintable_out}),
//------------------------- Receive Ports - RX AFE -------------------------
input GTXRXP , //(gtxrxp_in),
//---------------------- Receive Ports - RX AFE Ports ----------------------
input GTXRXN , //(gtxrxn_in),
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
input RXBUFRESET , //(tied_to_ground_i),
output [2:0] RXBUFSTATUS , //(),
input RXDDIEN , //(tied_to_ground_i),
input RXDLYBYPASS , //(tied_to_vcc_i),
input RXDLYEN , //(tied_to_ground_i),
input RXDLYOVRDEN , //(tied_to_ground_i),
input RXDLYSRESET , //(tied_to_ground_i),
output RXDLYSRESETDONE , //(),
input RXPHALIGN , //(tied_to_ground_i),
output RXPHALIGNDONE , //(),
input RXPHALIGNEN , //(tied_to_ground_i),
input RXPHDLYPD , //(tied_to_ground_i),
input RXPHDLYRESET , //(tied_to_ground_i),
output [4:0] RXPHMONITOR , //(),
input RXPHOVRDEN , //(tied_to_ground_i),
output [4:0] RXPHSLIPMONITOR , //(),
output [2:0] RXSTATUS , //(rxstatus_out),
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
output RXBYTEISALIGNED , //(rxbyteisaligned_out),
output RXBYTEREALIGN , //(),
output RXCOMMADET , //(),
input RXCOMMADETEN , //(tied_to_vcc_i),
input RXMCOMMAALIGNEN , //(tied_to_vcc_i),
input RXPCOMMAALIGNEN , //(tied_to_vcc_i),
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
output RXCHANBONDSEQ , //(),
input RXCHBONDEN , //(tied_to_ground_i),
input [2:0] RXCHBONDLEVEL , //(tied_to_ground_vec_i[2:0]),
input RXCHBONDMASTER , //(tied_to_ground_i),
output [4:0] RXCHBONDO , //(),
input RXCHBONDSLAVE , //(tied_to_ground_i),
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
output RXCHANISALIGNED , //(),
output RXCHANREALIGN , //(),
//------------------ Receive Ports - RX Equailizer Ports -------------------
input RXLPMHFHOLD , //(tied_to_ground_i),
input RXLPMHFOVRDEN , //(tied_to_ground_i),
input RXLPMLFHOLD , //(tied_to_ground_i),
//------------------- Receive Ports - RX Equalizer Ports -------------------
input RXDFEAGCHOLD , //(rxdfeagchold_in),
input RXDFEAGCOVRDEN , //(tied_to_ground_i),
input RXDFECM1EN , //(tied_to_ground_i),
input RXDFELFHOLD , //(rxdfelfhold_in),
input RXDFELFOVRDEN , //(tied_to_vcc_i),
input RXDFELPMRESET , //(rxdfelpmreset_in),
input RXDFETAP2HOLD , //(tied_to_ground_i),
input RXDFETAP2OVRDEN , //(tied_to_ground_i),
input RXDFETAP3HOLD , //(tied_to_ground_i),
input RXDFETAP3OVRDEN , //(tied_to_ground_i),
input RXDFETAP4HOLD , //(tied_to_ground_i),
input RXDFETAP4OVRDEN , //(tied_to_ground_i),
input RXDFETAP5HOLD , //(tied_to_ground_i),
input RXDFETAP5OVRDEN , //(tied_to_ground_i),
input RXDFEUTHOLD , //(tied_to_ground_i),
input RXDFEUTOVRDEN , //(tied_to_ground_i),
input RXDFEVPHOLD , //(tied_to_ground_i),
input RXDFEVPOVRDEN , //(tied_to_ground_i),
input RXDFEVSEN , //(tied_to_ground_i),
input RXLPMLFKLOVRDEN , //(tied_to_ground_i),
output [6:0] RXMONITOROUT , //(rxmonitorout_out),
input [1:0] RXMONITORSEL , //(rxmonitorsel_in),
input RXOSHOLD , //(tied_to_ground_i),
input RXOSOVRDEN , //(tied_to_ground_i),
//---------- Receive Ports - RX Fabric ClocK Output Control Ports ----------
output RXRATEDONE , //(),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
output RXOUTCLK , //(rxoutclk_out),
output RXOUTCLKFABRIC , //(),
output RXOUTCLKPCS , //(),
input [2:0] RXOUTCLKSEL , //(3'b010),
//-------------------- Receive Ports - RX Gearbox Ports --------------------
output RXDATAVALID , //(),
output [2:0] RXHEADER , //(),
output RXHEADERVALID , //(),
output RXSTARTOFSEQ , //(),
//------------------- Receive Ports - RX Gearbox Ports --------------------
input RXGEARBOXSLIP , //(tied_to_ground_i),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
input GTRXRESET , //(gtrxreset_in),
input RXOOBRESET , //(tied_to_ground_i),
input RXPCSRESET , //(tied_to_ground_i),
input RXPMARESET , //(rxpmareset_in),
//---------------- Receive Ports - RX Margin Analysis ports ----------------
input RXLPMEN , //(tied_to_ground_i),
//----------------- Receive Ports - RX OOB Signaling ports -----------------
output RXCOMSASDET , //(),
output RXCOMWAKEDET , //(rxcomwakedet_out),
//---------------- Receive Ports - RX OOB Signaling ports -----------------
output RXCOMINITDET , //(rxcominitdet_out),
//---------------- Receive Ports - RX OOB signalling Ports -----------------
output RXELECIDLE , //(rxelecidle_out),
input [1:0] RXELECIDLEMODE , //(2'b00),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
input RXPOLARITY , //(tied_to_ground_i),
//-------------------- Receive Ports - RX gearbox ports --------------------
input RXSLIDE , //(tied_to_ground_i),
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
output [7:0] RXCHARISCOMMA , //(),
output [7:0] RXCHARISK , //({rxcharisk_float_i,rxcharisk_out}),
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
input [4:0] RXCHBONDI , //(5'b00000),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
output RXRESETDONE , //(rxresetdone_out),
//------------------------------ Rx AFE Ports ------------------------------
input RXQPIEN , //(tied_to_ground_i),
output RXQPISENN , //(),
output RXQPISENP , //(),
//------------------------- TX Buffer Bypass Ports -------------------------
input TXPHDLYTSTCLK , //(tied_to_ground_i),
//---------------------- TX Configurable Driver Ports ----------------------
input [4:0] TXPOSTCURSOR , //(5'b00000),
input TXPOSTCURSORINV , //(tied_to_ground_i),
input [4:0] TXPRECURSOR , //(tied_to_ground_vec_i[4:0]),
input TXPRECURSORINV , //(tied_to_ground_i),
input TXQPIBIASEN , //(tied_to_ground_i),
input TXQPISTRONGPDOWN , //(tied_to_ground_i),
input TXQPIWEAKPUP , //(tied_to_ground_i),
//------------------- TX Initialization and Reset Ports --------------------
input CFGRESET , //(tied_to_ground_i),
input GTTXRESET , //(gttxreset_in),
output [15:0] PCSRSVDOUT , //(),
input TXUSERRDY , //(txuserrdy_in),
//-------------------- Transceiver Reset Mode Operation --------------------
input GTRESETSEL , //(tied_to_ground_i),
input RESETOVRD , //(tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [7:0] TXCHARDISPMODE , //(tied_to_ground_vec_i[7:0]),
input [7:0] TXCHARDISPVAL , //(tied_to_ground_vec_i[7:0]),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
input TXUSRCLK , //(txusrclk_in),
input TXUSRCLK2 , //(txusrclk2_in),
//------------------- Transmit Ports - PCI Express Ports -------------------
input TXELECIDLE , //(txelecidle_in),
input [2:0] TXMARGIN , //(tied_to_ground_vec_i[2:0]),
input [2:0] TXRATE , //(tied_to_ground_vec_i[2:0]),
input TXSWING , //(tied_to_ground_i),
//---------------- Transmit Ports - Pattern Generator Ports ----------------
input TXPRBSFORCEERR , //(tied_to_ground_i),
//---------------- Transmit Ports - TX Buffer Bypass Ports -----------------
input TXDLYBYPASS , //(tied_to_vcc_i),
input TXDLYEN , //(tied_to_ground_i),
input TXDLYHOLD , //(tied_to_ground_i),
input TXDLYOVRDEN , //(tied_to_ground_i),
input TXDLYSRESET , //(tied_to_ground_i),
output TXDLYSRESETDONE , //(),
input TXDLYUPDOWN , //(tied_to_ground_i),
input TXPHALIGN , //(tied_to_ground_i),
output TXPHALIGNDONE , //(),
input TXPHALIGNEN , //(tied_to_ground_i),
input TXPHDLYPD , //(tied_to_ground_i),
input TXPHDLYRESET , //(tied_to_ground_i),
input TXPHINIT , //(tied_to_ground_i),
output TXPHINITDONE , //(),
input TXPHOVRDEN , //(tied_to_ground_i),
//-------------------- Transmit Ports - TX Buffer Ports --------------------
output [1:0] TXBUFSTATUS , //(),
//------------- Transmit Ports - TX Configurable Driver Ports --------------
input [2:0] TXBUFDIFFCTRL , //(3'b100),
input TXDEEMPH , //(tied_to_ground_i),
input [3:0] TXDIFFCTRL , //(4'b1000),
input TXDIFFPD , //(tied_to_ground_i),
input TXINHIBIT , //(tied_to_ground_i),
input [6:0] TXMAINCURSOR , //(7'b0000000),
input TXPISOPD , //(tied_to_ground_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
input [63:0] TXDATA , //(txdata_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output GTXTXN , //(gtxtxn_out),
output GTXTXP , //(gtxtxp_out),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
output TXOUTCLK , //(txoutclk_out),
output TXOUTCLKFABRIC , //(txoutclkfabric_out),
output TXOUTCLKPCS , //(txoutclkpcs_out),
input [2:0] TXOUTCLKSEL , //(3'b010),
output TXRATEDONE , //(),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
input [7:0] TXCHARISK , //({tied_to_ground_vec_i[5:0],txcharisk_in}),
output TXGEARBOXREADY , //(),
input [2:0] TXHEADER , //(tied_to_ground_vec_i[2:0]),
input [6:0] TXSEQUENCE , //(tied_to_ground_vec_i[6:0]),
input TXSTARTSEQ , //(tied_to_ground_i),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
input TXPCSRESET , //(tied_to_ground_i),
input TXPMARESET , //(tied_to_ground_i),
output TXRESETDONE , //(txresetdone_out),
//---------------- Transmit Ports - TX OOB signalling Ports ----------------
output TXCOMFINISH , //(txcomfinish_out),
input TXCOMINIT , //(tied_to_ground_i),
input TXCOMSAS , //(tied_to_ground_i),
input TXCOMWAKE , //(txcomwake_in),
input TXPDELECIDLEMODE , //(tied_to_ground_i),
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
input TXPOLARITY , //(tied_to_ground_i),
//------------- Transmit Ports - TX Receiver Detection Ports --------------
input TXDETECTRX , //(tied_to_ground_i),
//---------------- Transmit Ports - TX8b/10b Encoder Ports -----------------
input [7:0] TX8B10BBYPASS , //(tied_to_ground_vec_i[7:0]),
//---------------- Transmit Ports - pattern Generator Ports ----------------
input [2:0] TXPRBSSEL , //(tied_to_ground_vec_i[2:0]),
//--------------------- Tx Configurable Driver Ports ----------------------
output TXQPISENN , //(),
output TXQPISENP //()
);
//_______________________ Simulation-Only Attributes __________________
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_RESET_SPEEDUP = "FALSE";
parameter SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_VERSION = "4.0";
//----------------RX Byte and Word Alignment Attributes---------------
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter RX_SIG_VALID_DLY = 10;
//----------------RX 8B/10B Decoder Attributes---------------
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "FALSE";
//----------------------RX Clock Correction Attributes----------------------
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter CLK_COR_MAX_LAT = 9;
parameter CLK_COR_MIN_LAT = 7;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter CLK_COR_REPEAT_WAIT = 0;
parameter CLK_COR_SEQ_LEN = 1;
parameter CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_1_1 = 10'b0100000000;
parameter CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter CLK_COR_SEQ_2_2 = 10'b0000000000;
parameter CLK_COR_SEQ_2_3 = 10'b0000000000;
parameter CLK_COR_SEQ_2_4 = 10'b0000000000;
//----------------------RX Channel Bonding Attributes----------------------
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter CHAN_BOND_MAX_SKEW = 1;
parameter CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_SEQ_1_1 = 10'b0000000000;
parameter CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_1 = 10'b0000000000;
parameter CHAN_BOND_SEQ_2_2 = 10'b0000000000;
parameter CHAN_BOND_SEQ_2_3 = 10'b0000000000;
parameter CHAN_BOND_SEQ_2_4 = 10'b0000000000;
parameter CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
//-------------------------RX Margin Analysis Attributes----------------------------
parameter ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "TRUE";
parameter ES_HORZ_OFFSET = 12'h000;
parameter ES_PMA_CFG = 10'b0000000000;
parameter ES_PRESCALE = 5'b00000;
parameter ES_QUALIFIER = 80'h00000000000000000000;
parameter ES_QUAL_MASK = 80'h00000000000000000000;
parameter ES_SDATA_MASK = 80'h00000000000000000000;
parameter ES_VERT_OFFSET = 9'b000000000;
//-----------------------FPGA RX Interface Attributes-------------------------
parameter RX_DATA_WIDTH = 20;
//-------------------------PMA Attributes----------------------------
parameter OUTREFCLK_SEL_INV = 2'b11;
parameter PMA_RSV = 32'h00018480;
parameter PMA_RSV2 = 16'h2050;
parameter PMA_RSV3 = 2'b00;
parameter PMA_RSV4 = 32'h00000000;
parameter RX_BIAS_CFG = 12'b000000000100;
parameter DMONITOR_CFG = 24'h000A00;
parameter RX_CM_SEL = 2'b11;
parameter RX_CM_TRIM = 3'b010;
parameter RX_DEBUG_CFG = 12'b000000000000;
parameter RX_OS_CFG = 13'b0000010000000;
parameter TERM_RCAL_CFG = 5'b10000;
parameter TERM_RCAL_OVRD = 1'b0;
parameter TST_RSV = 32'h00000000;
parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6;
parameter UCODEER_CLR = 1'b0;
//-------------------------PCI Express Attributes----------------------------
parameter PCS_PCIE_EN = "FALSE";
//-------------------------PCS Attributes----------------------------
parameter PCS_RSVD_ATTR = 48'h0100;
//-----------RX Buffer Attributes------------
parameter RXBUF_ADDR_MODE = "FAST";
parameter RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RX_BUFFER_CFG = 6'b000000;
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter RXBUF_THRESH_UNDFLW = 4;
parameter RXDLY_CFG = 16'h001F;
parameter RXDLY_LCFG = 9'h030;
parameter RXDLY_TAP_CFG = 16'h0000;
parameter RXPH_CFG = 24'h000000;
parameter RXPHDLY_CFG = 24'h084020;
parameter RXPH_MONITOR_SEL = 5'b00000;
parameter RX_XCLK_SEL = "RXREC";
parameter RX_DDI_SEL = 6'b000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
//---------------------CDR Attributes-------------------------
//For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
//For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
//For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
//For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
//For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
//For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
//For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
//For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
parameter RXCDR_CFG = 72'h03000023ff10200020;
parameter RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_LOCK_CFG = 6'b010101;
//-----------------RX Initialization and Reset Attributes-------------------
parameter RXCDRFREQRESET_TIME = 5'b00001;
parameter RXCDRPHRESET_TIME = 5'b00001;
parameter RXISCANRESET_TIME = 5'b00001;
parameter RXPCSRESET_TIME = 5'b00001;
parameter RXPMARESET_TIME = 5'b00011;
//-----------------RX OOB Signaling Attributes-------------------
parameter RXOOB_CFG = 7'b0000110;
//-----------------------RX Gearbox Attributes---------------------------
parameter RXGEARBOX_EN = "FALSE";
parameter GEARBOX_MODE = 3'b000;
//-----------------------PRBS Detection Attribute-----------------------
parameter RXPRBS_ERR_LOOPBACK = 1'b0;
//-----------Power-Down Attributes----------
parameter PD_TRANS_TIME_FROM_P2 = 12'h03c;
parameter PD_TRANS_TIME_NONE_P2 = 8'h3c;
parameter PD_TRANS_TIME_TO_P2 = 8'h64;
//-----------RX OOB Signaling Attributes----------
parameter SAS_MAX_COM = 64;
parameter SAS_MIN_COM = 36;
parameter SATA_BURST_SEQ_LEN = 4'b0101;
parameter SATA_BURST_VAL = 3'b110;
parameter SATA_EIDLE_VAL = 3'b110;
parameter SATA_MAX_BURST = 8;
parameter SATA_MAX_INIT = 21;
parameter SATA_MAX_WAKE = 7;
parameter SATA_MIN_BURST = 4;
parameter SATA_MIN_INIT = 12;
parameter SATA_MIN_WAKE = 4;
//-----------RX Fabric Clock Output Control Attributes----------
parameter TRANS_TIME_RATE = 8'h0E;
//------------TX Buffer Attributes----------------
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter TXDLY_CFG = 16'h001F;
parameter TXDLY_LCFG = 9'h030;
parameter TXDLY_TAP_CFG = 16'h0000;
parameter TXPH_CFG = 16'h0780;
parameter TXPHDLY_CFG = 24'h084020;
parameter TXPH_MONITOR_SEL = 5'b00000;
parameter TX_XCLK_SEL = "TXOUT";
//-----------------------FPGA TX Interface Attributes-------------------------
parameter TX_DATA_WIDTH = 20;
//-----------------------TX Configurable Driver Attributes-------------------------
parameter TX_DEEMPH0 = 5'b00000;
parameter TX_DEEMPH1 = 5'b00000;
parameter TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter TX_MAINCURSOR_SEL = 1'b0;
parameter TX_DRIVE_MODE = "DIRECT";
parameter TX_MARGIN_FULL_0 = 7'b1001110;
parameter TX_MARGIN_FULL_1 = 7'b1001001;
parameter TX_MARGIN_FULL_2 = 7'b1000101;
parameter TX_MARGIN_FULL_3 = 7'b1000010;
parameter TX_MARGIN_FULL_4 = 7'b1000000;
parameter TX_MARGIN_LOW_0 = 7'b1000110;
parameter TX_MARGIN_LOW_1 = 7'b1000100;
parameter TX_MARGIN_LOW_2 = 7'b1000010;
parameter TX_MARGIN_LOW_3 = 7'b1000000;
parameter TX_MARGIN_LOW_4 = 7'b1000000;
//-----------------------TX Gearbox Attributes--------------------------
parameter TXGEARBOX_EN = "FALSE";
//-----------------------TX Initialization and Reset Attributes--------------------------
parameter TXPCSRESET_TIME = 5'b00001;
parameter TXPMARESET_TIME = 5'b00001;
//-----------------------TX Receiver Detection Attributes--------------------------
parameter TX_RXDETECT_CFG = 14'h1832;
parameter TX_RXDETECT_REF = 3'b100;
//--------------------------CPLL Attributes----------------------------
parameter CPLL_CFG = 24'hBC07DC;
parameter CPLL_FBDIV = 4;
parameter CPLL_FBDIV_45 = 5;
parameter CPLL_INIT_CFG = 24'h00001E;
parameter CPLL_LOCK_CFG = 16'h01E8;
parameter CPLL_REFCLK_DIV = 1;
parameter RXOUT_DIV = 2;
parameter TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
//------------RX Initialization and Reset Attributes-------------
parameter RXDFELPMRESET_TIME = 7'b0001111;
//------------RX Equalizer Attributes-------------
parameter RXLPM_HF_CFG = 14'b00000011110000;
parameter RXLPM_LF_CFG = 14'b00000011110000;
parameter RX_DFE_GAIN_CFG = 23'h020FEA;
parameter RX_DFE_H2_CFG = 12'b000000000000;
parameter RX_DFE_H3_CFG = 12'b000001000000;
parameter RX_DFE_H4_CFG = 11'b00011110000;
parameter RX_DFE_H5_CFG = 11'b00011100000;
parameter RX_DFE_KL_CFG = 13'b0000011111110;
parameter RX_DFE_LPM_CFG = 16'h0954;
parameter RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter RX_DFE_UT_CFG = 17'b10001111000000000;
parameter RX_DFE_VP_CFG = 17'b00011111100000011;
//-----------------------Power-Down Attributes-------------------------
parameter RX_CLKMUX_PD = 1'b1;
parameter TX_CLKMUX_PD = 1'b1;
//-----------------------FPGA RX Interface Attribute-------------------------
parameter RX_INT_DATAWIDTH = 0;
//-----------------------FPGA TX Interface Attribute-------------------------
parameter TX_INT_DATAWIDTH = 0;
//----------------TX Configurable Driver Attributes---------------
parameter TX_QPI_STATUS_EN = 1'b0;
//-----------------------RX Equalizer Attributes--------------------------
parameter RX_DFE_KL_CFG2 = 0;
parameter RX_DFE_XYD_CFG = 13'b0000000000000;
//-----------------------TX Configurable Driver Attributes--------------------------
parameter TX_PREDRIVER_MODE = 1'b0;
wire reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXDLYSRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
reg rx_rst_done = 1'b0;
reg tx_rst_done = 1'b0;
assign RXRESETDONE = rx_rst_done;
assign TXRESETDONE = tx_rst_done;
initial
forever @ (posedge reset)
begin
tx_rst_done <= 1'b0;
@ (negedge reset);
repeat (80)
@ (posedge GTREFCLK0);
tx_rst_done <= 1'b1;
end
initial
forever @ (posedge reset)
begin
rx_rst_done <= 1'b0;
@ (negedge reset);
repeat (100)
@ (posedge GTREFCLK0);
rx_rst_done <= 1'b1;
end
gtxe2_chnl #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
.TXOUT_DIV (TXOUT_DIV),
// .TXRATE (TXRATE),
.RXOUT_DIV (RXOUT_DIV),
// .RXRATE (RXRATE),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.PRX8B10BEN (1),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.PTX8B10BEN (1),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_CPLL_CFG (SATA_CPLL_CFG)
)
channel(
.reset (reset),
.TXP (GTXTXP),
.TXN (GTXTXN),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXBUFSTATUS (TXBUFSTATUS),
.TXPOLARITY (TXPOLARITY),
.TXRATE (TXRATE),
.RXRATE (RXRATE),
.TXRATEDONE (TXRATEDONE),
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.TXELECIDLE (TXELECIDLE),
.RXP (GTXRXP),
.RXN (GTXRXN),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.RXDATA (RXDATA),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXPOLARITY (RXPOLARITY),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.TXOUTCLKSEL (TXOUTCLKSEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK ),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TXOUTCLKPMA (TXOUTCLKPMA),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (),
.RXOUTCLKPMA (RXOUTCLKPMA),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk ()
);
endmodule
gtxe2_channel/GTXE2_CHANNEL_GPL.v 0 → 100644
View file @ 9b371aa6
/*******************************************************************************
* Module: GTXE2_CHANNEL
* Date: 2015-07-06
* Author: Alexey
* Description: A wrapper maintaining interface compability
*
* Copyright (c) 2015 Elphel, Inc.
* GTXE2_CHANNEL_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GTXE2_CHANNEL_GPL.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/**
* Original unisims primitive's interfaces, according to xilinx's user guide:
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
* referenced as ug476 or UG476
*
* Due to lack of functionality of gtxe2_gpl project as compared to the xilinx's primitive,
* not all of the inputs are used and not all of the outputs are driven.
**/
`include "gtxe2_chnl.v"
module GTXE2_CHANNEL(
// clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input [1:0] RXSYSCLKSEL,
input [1:0] TXSYSCLKSEL,
output GTREFCLKMONITOR,
// CPLL Ports, UG476 p.48
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input CPLLRESET,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output TSTOUT,
input GTRSVD,
input PCSRSVDIN,
input PCSRSVDIN2,
input PMARSVDIN,
input PMARSVDIN2,
input TSTIN,
// Reset Mode ports, ug476 p.62
input GTRESETSEL,
input RESETOVRD,
// TX Reset ports, ug476 p.65
input CFGRESET,
input GTTXRESET,
input TXPCSRESET,
input TXPMARESET,
output TXRESETDONE,
input TXUSERRDY,
output PCSRSVDOUT,
// RX Reset ports, UG476 p.73
input GTRXRESET,
input RXPMARESET,
input RXCDRRESET,
input RXCDRFREQRESET,
input RXDFELPMRESET,
input EYESCANRESET,
input RXPCSRESET,
input RXBUFRESET,
input RXUSERRDY,
output RXRESETDONE,
input RXOOBRESET,
// Power Down ports, ug476 p.88
input [1:0] RXPD,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHDLYPD,
input RXPHDLYPD,
// Loopback ports, ug476 p.91
input [2:0] LOOPBACK,
// Dynamic Reconfiguration Port, ug476 p.92
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
// Digital Monitor Ports, ug476 p.95
input [3:0] CLKRSVD,
input [7:0] DMONITOROUT,
// TX Interface Ports, ug476 p.110
input [7:0] TXCHARDISPMODE,
input [7:0] TXCHARDISPVAL,
input [63:0] TXDATA,
input TXUSRCLK,
input TXUSRCLK2,
// TX 8B/10B encoder ports, ug476 p.118
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [7:0] TXCHARISK,
// TX Gearbox ports, ug476 p.122
output TXGEARBOXREADY,
input [2:0] TXHEADER,
input [6:0] TXSEQUENCE,
input TXSTARTSEQ,
// TX BUffer Ports, ug476 p.134
input [1:0] TXBUFSTATUS,
// TX Buffer Bypass Ports, ug476 p.136
input TXDLYSRESET,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHINIT,
input TXPHOVRDEN,
input TXPHDLYRESET,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYOVRDEN,
input TXPHDLYTSTCLK,
input TXDLYHOLD,
input TXDLYUPDOWN,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXDLYSRESETDONE,
input TXSYNCMODE,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCOUT,
input TXSYNCDONE,
// TX Pattern Generator, ug476 p.147
input [2:0] TXPRBSSEL,
input TXPRBSFORCEERR,
// TX Polarity Control Ports, ug476 p.149
input TXPOLARITY,
// TX Fabric Clock Output Control Ports, ug476 p.152
input [2:0] TXOUTCLKSEL,
input [2:0] TXRATE,
output TXOUTCLKFABRIC,
output TXOUTCLK,
output TXOUTCLKPCS,
output TXRATEDONE,
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMSEL,
input TXPIPPMPD,
input [4:0] TXPIPPMSTEPSIZE,
// TX Configurable Driver Ports, ug476 p.156
input [2:0] TXBUFDIFFCTRL,
input TXDEEMPH,
input [3:0] TXDIFFCTRL,
input TXELECIDLE,
input TXINHIBIT,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXQPIBIASEN,
output TXQPISENN,
output TXQPISENP,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXSWING,
input TXDIFFPD,
input TXPISOPD,
// TX Receiver Detection Ports, ug476 p.165
input TXDETECTRX,
output PHYSTATUS,
input [2:0] RXSTATUS,
// TX OOB Signaling Ports, ug476 p.166
output TXCOMFINISH,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
// RX AFE Ports, ug476 p.171
output RXQPISENN,
output RXQPISENP,
input RXQPIEN,
// RX OOB Signaling Ports, ug476 p.178
input [1:0] RXELECIDLEMODE,
output RXELECIDLE,
output RXCOMINITDET,
output RXCOMSASDET,
output RXCOMWAKEDET,
// RX Equalizer Ports, ug476 p.189
input RXLPMEN,
input RXOSHOLD,
input RXOSOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFECM1EN,
input RXDFEXYDHOLD,
input RXDFEXYDOVRDEN,
input RXDFEXYDEN,
input [1:0] RXMONITORSEL,
input [6:0] RXMONITOROUT,
// CDR Ports, ug476 p.202
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESETRSV,
input [2:0] RXRATE,
output RXCDRLOCK,
// RX Fabric Clock Output Control Ports, ug476 p.213
input [2:0] RXOUTCLKSEL,
output RXOUTCLKFABRIC,
output RXOUTCLK,
output RXOUTCLKPCS,
output RXRATEDONE,
input RXDLYBYPASS,
// RX Margin Analysis Ports, ug476 p.220
output EYESCANDATAERROR,
input EYESCANTRIGGER,
input EYESCANMODE,
// RX Polarity Control Ports, ug476 p.224
input RXPOLARITY,
// Pattern Checker Ports, ug476 p.225
input RXPRBSCNTRESET,
input [2:0] RXPRBSSEL,
output RXPRBSERR,
// RX Byte and Word Alignment Ports, ug476 p.233
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCOMMADET,
input RXCOMMADETEN,
input RXPCOMMAALIGNEN,
input RXMCOMMAALIGNEN,
input RXSLIDE,
// RX 8B/10B Decoder Ports, ug476 p.241
input RX8B10BEN,
output [7:0] RXCHARISCOMMA,
output [7:0] RXCHARISK,
output [7:0] RXDISPERR,
output [7:0] RXNOTINTABLE,
input SETERRSTATUS,
// RX Buffer Bypass Ports, ug476 p.244
input RXPHDLYRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHOVRDEN,
input RXDLYSRESET,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDDIEN,
output RXPHALIGNDONE,
output RXPHMONITOR,
output RXPHSLIPMONITOR,
output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259
input [2:0] RXBUFSTATUS,
// RX Clock Correction Ports, ug476 p.263
input [1:0] RXCLKCORCNT,
// RX Channel Bonding Ports, ug476 p.274
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
input [4:0] RXCHBONDI,
output [4:0] RXCHBONDO,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCHBONDEN,
// RX Gearbox Ports, ug476 p.285
output RXDATAVALID,
input RXGEARBOXSLIP,
input [2:0] RXHEADER,
output RXHEADERVALID,
output RXSTARTOFSEQ,
// FPGA RX Interface Ports, ug476 p.299
output [63:0] RXDATA,
input RXUSRCLK,
input RXUSRCLK2,
// ug476, p.323
output RXVALID,
// for correct clocking scheme in case of multilane structure
input QPLLCLK,
input QPLLREFCLK,
// Diffpairs
input GTXRXP,
input GTXRXN,
output GTXTXN,
output GTXTXP
);
// simulation common attributes, UG476 p.28
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
// Clocking Atributes, UG476 p.38
parameter OUTREFCLK_SEL_INV = 1'b0;
// CPLL Attributes, UG476 p.49
parameter CPLL_CFG = 24'h0;
parameter CPLL_FBDIV = 4;
parameter CPLL_FBDIV_45 = 5;
parameter CPLL_INIT_CFG = 24'h0;
parameter CPLL_LOCK_CFG = 16'h0;
parameter CPLL_REFCLK_DIV = 1;
parameter RXOUT_DIV = 2;
parameter TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter PMA_RSV3 = 2'b00;
// TX Initialization and Reset Attributes, ug476 p.66
parameter TXPCSRESET_TIME = 5'b00001;
parameter TXPMARESET_TIME = 5'b00001;
// RX Initialization and Reset Attributes, UG476 p.75
parameter RXPMARESET_TIME = 5'h0;
parameter RXCDRPHRESET_TIME = 5'h0;
parameter RXCDRFREQRESET_TIME = 5'h0;
parameter RXDFELPMRESET_TIME = 7'h0;
parameter RXISCANRESET_TIME = 7'h0;
parameter RXPCSRESET_TIME = 5'h0;
parameter RXBUFRESET_TIME = 5'h0;
// Power Down attributes, ug476 p.88
parameter PD_TRANS_TIME_FROM_P2 = 12'h0;
parameter PD_TRANS_TIME_NONE_P2 = 8'h0;
parameter PD_TRANS_TIME_TO_P2 = 8'h0;
parameter TRANS_TIME_RATE = 8'h0;
parameter RX_CLKMUX_PD = 1'b0;
parameter TX_CLKMUX_PD = 1'b0;
// GTX Digital Monitor Attributes, ug476 p.96
parameter DMONITOR_CFG = 24'h008101;
// TX Interface attributes, ug476 p.111
parameter TX_DATA_WIDTH = 20;
parameter TX_INT_DATAWIDTH = 0;
// TX Gearbox Attributes, ug476 p.121
parameter GEARBOX_MODE = 3'h0;
parameter TXGEARBOX_EN = "FALSE";
// TX BUffer Attributes, ug476 p.134
parameter TXBUF_EN = "TRUE";
// TX Bypass buffer, ug476 p.138
parameter TX_XCLK_SEL = "TXOUT";
parameter TXPH_CFG = 16'h0;
parameter TXPH_MONITOR_SEL = 5'h0;
parameter TXPHDLY_CFG = 24'h0;
parameter TXDLY_CFG = 16'h0;
parameter TXDLY_LCFG = 9'h0;
parameter TXDLY_TAP_CFG = 16'h0;
parameter TXSYNC_MULTILANE = 1'b0;
parameter TXSYNC_SKIP_DA = 1'b0;
parameter TXSYNC_OVRD = 1'b1;
parameter LOOPBACK_CFG = 1'b0;
// TX Pattern Generator, ug476 p.147
parameter RXPRBS_ERR_LOOPBACK = 1'b0;
// TX Fabric Clock Output Control Attributes, ug476 p. 153
parameter TXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
parameter TXPI_SYNCFREQ_PPM = 3'b001;
parameter TXPI_PPM_CFG = 8'd0;
parameter TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_GREY_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "12345";
// TX Configurable Driver Attributes, ug476 p.162
parameter TX_DEEMPH0 = 5'b10100;
parameter TX_DEEMPH1 = 5'b01101;
parameter TX_DRIVE_MODE = "DIRECT";
parameter TX_MAINCURSOR_SEL = 1'b0;
parameter TX_MARGIN_FULL_0 = 7'b0;
parameter TX_MARGIN_FULL_1 = 7'b0;
parameter TX_MARGIN_FULL_2 = 7'b0;
parameter TX_MARGIN_FULL_3 = 7'b0;
parameter TX_MARGIN_FULL_4 = 7'b0;
parameter TX_MARGIN_LOW_0 = 7'b0;
parameter TX_MARGIN_LOW_1 = 7'b0;
parameter TX_MARGIN_LOW_2 = 7'b0;
parameter TX_MARGIN_LOW_3 = 7'b0;
parameter TX_MARGIN_LOW_4 = 7'b0;
parameter TX_PREDRIVER_MODE = 1'b0;
parameter TX_QPI_STATUS_EN = 1'b0;
parameter TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
// TX Receiver Detection Attributes, ug476 p.165
parameter TX_RXDETECT_CFG = 14'h0;
parameter TX_RXDETECT_REF = 3'h0;
// TX OOB Signaling Attributes
parameter SATA_BURST_SEQ_LEN = 4'b0101;
// RX AFE Attributes, ug476 p.171
parameter RX_CM_SEL = 2'b11;
parameter TERM_RCAL_CFG = 5'b0;
parameter TERM_RCAL_OVRD = 1'b0;
parameter RX_CM_TRIM = 3'b010;
// RX OOB Signaling Attributes, ug476 p.179
parameter PCS_RSVD_ATTR = 48'h0100; // oob is up
parameter RXOOB_CFG = 7'b0000110;
parameter SATA_BURST_VAL = 3'b110;
parameter SATA_EIDLE_VAL = 3'b110;
parameter SAS_MIN_COM = 36;
parameter SATA_MIN_INIT = 12;
parameter SATA_MIN_WAKE = 4;
parameter SATA_MAX_BURST = 8;
parameter SATA_MIN_BURST = 4;
parameter SAS_MAX_COM = 64;
parameter SATA_MAX_INIT = 21;
parameter SATA_MAX_WAKE = 7;
// RX Equalizer Attributes, ug476 p.193
parameter RX_OS_CFG = 13'h0080;
parameter RXLPM_LF_CFG = 14'h00f0;
parameter RXLPM_HF_CFG = 14'h00f0;
parameter RX_DFE_LPM_CFG = 16'h0;
parameter RX_DFE_GAIN_CFG = 23'h020FEA;
parameter RX_DFE_H2_CFG = 12'h0;
parameter RX_DFE_H3_CFG = 12'h040;
parameter RX_DFE_H4_CFG = 11'h0e0;
parameter RX_DFE_H5_CFG = 11'h0e0;
parameter PMA_RSV = 32'h00018480;
parameter RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter RX_DFE_XYD_CFG = 13'h0;
parameter PMA_RSV4 = 32'h0;
parameter PMA_RSV2 = 16'h0;
parameter RX_BIAS_CFG = 12'h040;
parameter RX_DEBUG_CFG = 12'h0;
parameter RX_DFE_KL_CFG = 13'h0;
parameter RX_DFE_KL_CFG2 = 32'h0;
parameter RX_DFE_UT_CFG = 17'h11e00;
parameter RX_DFE_VP_CFG = 17'h03f03;
// CDR Attributes, ug476 p.203
parameter RXCDR_CFG = 72'h0;
parameter RXCDR_LOCK_CFG = 6'h0;
parameter RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_PH_RESET_ON_EIDLE = 1'b0;
// RX Fabric Clock Output Control Attributes
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// RX Margin Analysis Attributes
parameter ES_VERT_OFFSET = 9'h0;
parameter ES_HORZ_OFFSET = 12'h0;
parameter ES_PRESCALE = 5'h0;
parameter ES_SDATA_MASK = 80'h0;
parameter ES_QUALIFIER = 80'h0;
parameter ES_QUAL_MASK = 80'h0;
parameter ES_EYE_SCAN_EN = 1'b1;
parameter ES_ERRDET_EN = 1'b0;
parameter ES_CONTROL = 6'h0;
parameter es_control_status = 4'b000;
parameter es_rdata = 80'h0;
parameter es_sdata = 80'h0;
parameter es_error_count = 16'h0;
parameter es_sample_count = 16'h0;
parameter RX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter ES_PMA_CFG = 10'h0;
// Pattern Checker Attributes, ug476 p.226
parameter RX_PRBS_ERR_CNT = 16'h15c;
// RX Byte and Word Alignment Attributes, ug476 p.235
parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_MODE = "OFF";
parameter RXSLIDE_AUTO_WAIT = 7;
parameter RX_SIG_VALID_DLY = 10;
parameter COMMA_ALIGN_LATENCY = 9'h14e;
// RX 8B/10B Decoder Attributes, ug476 p.242
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "FALSE";
parameter UCODEER_CLR = 1'b0;
// RX Buffer Bypass Attributes, ug476 p.247
parameter RXBUF_EN = "TRUE";
parameter RX_XCLK_SEL = "RXREC";
parameter RXPH_CFG = 24'h0;
parameter RXPH_MONITOR_SEL = 5'h0;
parameter RXPHDLY_CFG = 24'h0;
parameter RXDLY_CFG = 16'h0;
parameter RXDLY_LCFG = 9'h0;
parameter RXDLY_TAP_CFG = 16'h0;
parameter RX_DDI_SEL = 6'h0;
parameter TST_RSV = 32'h0;
// RX Buffer Attributes, ug476 p.259
parameter RX_BUFFER_CFG = 6'b0;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RXBUF_ADDR_MODE = "FAST";
parameter RXBUF_EIDLE_HI_CNT = 4'b0;
parameter RXBUF_EIDLE_LO_CNT = 4'b0;
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_THRESH_OVFLW = 0;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter RXBUF_THRESH_UNDFLW = 0;
// RX Clock Correction Attributes, ug476 p.265
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter CLK_COR_MAX_LAT = 9;
parameter CLK_COR_MIN_LAT = 7;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter CLK_COR_REPEAT_WAIT = 0;
parameter CLK_COR_SEQ_LEN = 1;
parameter CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_1_1 = 10'b0;
parameter CLK_COR_SEQ_1_2 = 10'b0;
parameter CLK_COR_SEQ_1_3 = 10'b0;
parameter CLK_COR_SEQ_1_4 = 10'b0;
parameter CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_1 = 10'b0;
parameter CLK_COR_SEQ_2_2 = 10'b0;
parameter CLK_COR_SEQ_2_3 = 10'b0;
parameter CLK_COR_SEQ_2_4 = 10'b0;
// RX Channel Bonding Attributes, ug476 p.276
parameter CHAN_BOND_MAX_SKEW = 1;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_SEQ_1_1 = 10'b0;
parameter CHAN_BOND_SEQ_1_2 = 10'b0;
parameter CHAN_BOND_SEQ_1_3 = 10'b0;
parameter CHAN_BOND_SEQ_1_4 = 10'b0;
parameter CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_1 = 10'b0;
parameter CHAN_BOND_SEQ_2_2 = 10'b0;
parameter CHAN_BOND_SEQ_2_3 = 10'b0;
parameter CHAN_BOND_SEQ_2_4 = 10'b0;
parameter CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter PCS_PCIE_EN = "FALSE";
// RX Gearbox Attributes, ug476 p.287
parameter RXGEARBOX_EN = "FALSE";
// ug476 table p.326 - undocumented parameters
parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6;
wire reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXDLYSRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
reg rx_rst_done = 1'b0;
reg tx_rst_done = 1'b0;
assign RXRESETDONE = rx_rst_done;
assign TXRESETDONE = tx_rst_done;
initial
forever @ (posedge reset)
begin
tx_rst_done <= 1'b0;
@ (negedge reset);
repeat (80)
@ (posedge GTREFCLK0);
tx_rst_done <= 1'b1;
end
initial
forever @ (posedge reset)
begin
rx_rst_done <= 1'b0;
@ (negedge reset);
repeat (100)
@ (posedge GTREFCLK0);
rx_rst_done <= 1'b1;
end
gtxe2_chnl #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
.TXOUT_DIV (TXOUT_DIV),
// .TXRATE (TXRATE),
.RXOUT_DIV (RXOUT_DIV),
// .RXRATE (RXRATE),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.PRX8B10BEN (1),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.PTX8B10BEN (1),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_CPLL_CFG (SATA_CPLL_CFG)
)
channel(
.reset (reset),
.TXP (GTXTXP),
.TXN (GTXTXN),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXBUFSTATUS (TXBUFSTATUS),
.TXPOLARITY (TXPOLARITY),
.TXRATE (TXRATE),
.RXRATE (RXRATE),
.TXRATEDONE (TXRATEDONE),
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.TXELECIDLE (TXELECIDLE),
.RXP (GTXRXP),
.RXN (GTXRXN),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.RXDATA (RXDATA),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXPOLARITY (RXPOLARITY),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.TXOUTCLKSEL (TXOUTCLKSEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK ),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TXOUTCLKPMA (TXOUTCLKPMA),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (),
.RXOUTCLKPMA (RXOUTCLKPMA),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk ()
);
endmodule
gtxe2_channel/clock_divider.v
View file @ 9b371aa6
/*******************************************************************************
* Module: clock_divider
* Date: 2015-07-06
* Author: Alexey
* Description: Non-sinthesizable clock divider
*
* Copyright (c) 2015 Elphel, Inc.
* clock_divider.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* clock_divider.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/**
* Divides input clock either by input 'div' or by parameter 'divide_by' if divide_by_param
* was set to 1
**/
`ifndef CLOCK_DIVIDER_V
`define CLOCK_DIVIDER_V
// non synthesisable!
......
gtxe2_channel/gtxe2_chnl.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl
* Date: 2015-07-06
* Author: Alexey
* Description: top-level module gtxe2_chnl = tx + rx + clocking
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_chnl_clocking.v"
`include "gtxe2_chnl_tx.v"
`include "gtxe2_chnl_rx.v"
......
gtxe2_channel/gtxe2_chnl_clocking.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_clocking
* Date: 2015-07-06
* Author: Alexey
* Description: channel's clocking top-level. Places muxes, plls, dividers,
* as they're depicted @ xilinx's ug476 p.36, p.46, p. 150, p. 211
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_clocking.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_clocking.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_chnl_cpll_inmux.v"
`include "gtxe2_chnl_outclk_mux.v"
`include "gtxe2_chnl_cpll.v"
......
gtxe2_channel/gtxe2_chnl_cpll.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_cpll
* Date: 2015-07-06
* Author: Alexey
* Description: non-synthesizable pll implementation
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_cpll.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_cpll.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_chnl_cpll_def.v"
module gtxe2_chnl_cpll(
// top-level interfaces
......
gtxe2_channel/gtxe2_chnl_cpll_inmux.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_cpll_inmux
* Date: 2015-07-06
* Author: Alexey
* Description: non-sinthesizable clock multiplexer, used in clocking scheme
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_cpll_inmux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_cpll_inmux.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// cpll reference clock mux
module gtxe2_chnl_cpll_inmux(
input wire [2:0] CPLLREFCLKSEL,
......
gtxe2_channel/gtxe2_chnl_outclk_mux.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_cpll_outmux
* Date: 2015-07-06
* Author: Alexey
* Description: non-sinthesizable clock multiplexer, used in clocking scheme
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_cpll_outmux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_cpll_outmux.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module gtxe2_chnl_outclk_mux(
input wire TXPLLREFCLK_DIV1,
input wire TXPLLREFCLK_DIV2,
......
gtxe2_channel/gtxe2_chnl_rx.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_rx
* Date: 2015-07-06
* Author: Alexey
* Description: reciever top-level. Also includes polarity-inversion logic
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_rx.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_rx.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/**
* For now contains only deserializer, oob, 10x8 decoder, aligner and polarity invertor blocks
**/
`include "gtxe2_chnl_rx_des.v"
`include "gtxe2_chnl_rx_oob.v"
`include "gtxe2_chnl_rx_10x8dec.v"
......@@ -144,6 +167,7 @@ aligner(
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN)
);
// 10x8 decoder
gtxe2_chnl_rx_10x8dec #(
.iwidth (internal_data_width),
.owidth (RX_DATA_WIDTH),
......
gtxe2_channel/gtxe2_chnl_rx_10x8dec.v
View file @ 9b371aa6
// always enabled
/*******************************************************************************
* Module: gtxe2_chnl_rx_10x8dec
* Date: 2015-07-06
* Author: Alexey
* Description: 10x8 decoder implementation, has reduced parameterization abilities
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_rx_10x8dec.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_rx_10x8dec.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// always enabled, wasnt tested with width parameters, disctinct from 20
module gtxe2_chnl_rx_10x8dec #(
parameter iwidth = 20,
parameter owidth = 20,
......
gtxe2_channel/gtxe2_chnl_rx_align.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_rx_align
* Date: 2015-07-06
* Author: Alexey
* Description: reciever's comma-aligner implementation
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_rx_align.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_rx_align.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module gtxe2_chnl_rx_align #(
parameter width = 20,
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
......@@ -30,6 +50,7 @@ localparam window_size = width;//comma_width + width;
reg [width - 1:0] indata_r;
wire [width*2 - 1:0] data;
// looking for matches in all related bit history - in 'data'
assign data = {indata, indata_r};//{indata_r, indata};
always @ (posedge clk)
indata_r <= indata;
......@@ -53,7 +74,7 @@ end
endgenerate
// so, comma_match indicates bits, from whose comma/doublecomma (or commas) occurs in the window buffer
// all we need from now is to get one of these bits = [x] and say [x+width-1:x] is an aligned data
// all we need from now is to get one of these bits, [x], and say [x+width-1:x] is an aligned data
// doing it in a hard way
generate
......@@ -63,6 +84,7 @@ begin: filter_comma_pos
end
endgenerate
assign comma_pos[0] = comma_match[0];
// so, comma_pos's '1' indicates the first comma occurence. there is only one '1' in the vector
function integer clogb2;
input [31:0] value;
......@@ -83,6 +105,7 @@ endfunction
localparam pwidth = clogb2(width * 2 -1);
// decoding (finding an index, representing '1' in comma_pos)
wire [pwidth - 1:0] pointer;
reg [pwidth - 1:0] pointer_latched;
wire pointer_set;
......
gtxe2_channel/gtxe2_chnl_rx_des.v
View file @ 9b371aa6
// 20-bit width only, for now
// assuming inclk and outclk are completely aligned (have the same source)
/*******************************************************************************
* Module: gtxe2_chnl_rx_des
* Date: 2015-07-06
* Author: Alexey
* Description: 1xwidth deserializer
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_rx_des.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_rx_des.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "resync_fifo_nonsynt.v"
module gtxe2_chnl_rx_des #(
parameter [31:0] width = 20
......@@ -9,9 +27,7 @@ module gtxe2_chnl_rx_des #(
input wire inclk,
input wire outclk,
input wire indata,
// input wire idle_in,
output wire [width - 1:0] outdata
// output wire idle_out
);
reg [31:0] bitcounter;
......
gtxe2_channel/gtxe2_chnl_rx_oob.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_rx_oob
* Date: 2015-07-06
* Author: Alexey
* Description: oob detector
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_rx_oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_rx_oob.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// doesnt support global parameters for now. instead uses localparams
// in case global parameters are needed, have to translate them in terms of localparams
module gtxe2_chnl_rx_oob #(
parameter width = 20,
// parameters are not used for now
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter SATA_MIN_INIT = 12,
......@@ -23,7 +46,6 @@ module gtxe2_chnl_rx_oob #(
output wire RXCOMWAKEDET
);
// parameters are not used for now
localparam burst_min_len = 150;
localparam burst_max_len = 340;
......
gtxe2_channel/gtxe2_chnl_tx.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_tx
* Date: 2015-07-06
* Author: Alexey
* Description: transmitter top-level, includes polarity-inversion, bit-reordering
* and elecidle logic
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_tx.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_tx.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_chnl_tx_ser.v"
`include "gtxe2_chnl_tx_8x10enc.v"
`include "gtxe2_chnl_tx_oob.v"
......
gtxe2_channel/gtxe2_chnl_tx_8x10enc.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_tx_8x10enc
* Date: 2015-07-06
* Author: Alexey
* Description: 8x10 encoder
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_tx_8x10enc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_tx_8x10enc.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// for some reason overall trasmitted disparity is tracked at the top level
module gtxe2_chnl_tx_8x10enc #(
parameter iwidth = 16,
parameter owidth = 20
......@@ -26,6 +47,9 @@ wire [owidth - 1:0] oword [word_count - 1:0];
wire [iwidth - 1:0] iword [word_count - 1:0];
wire [word_count - 1:0] is_control;
// typical approach: 8x10 = 5x6 + 3x4
// word disparity[i] = calculated disparity for the i-th 8-bit word
// interm_disparity[i] - disparity after 5x6 encoding for the i-th word
genvar ii;
generate
for (ii = 0; ii < 2; ii = ii + 1)
......
gtxe2_channel/gtxe2_chnl_tx_oob.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_chnl_tx_oob
* Date: 2015-07-06
* Author: Alexey
* Description: oob block implementation
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_tx_oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_tx_oob.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module gtxe2_chnl_tx_oob #(
parameter width = 20
)
......
gtxe2_channel/gtxe2_chnl_tx_ser.v
View file @ 9b371aa6
// 20-bit width only, for now
// assuming inclk and outclk are completely aligned (have the same source)
/*******************************************************************************
* Module: gtxe2_chnl_tx_ser
* Date: 2015-07-06
* Author: Alexey
* Description: widthx1 serializer
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_chnl_tx_ser.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_chnl_tx_ser.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "resync_fifo_nonsynt.v"
module gtxe2_chnl_tx_ser #(
parameter [31:0] width = 20
......
gtxe2_channel/resync_fifo_nonsynt.v
View file @ 9b371aa6
/*******************************************************************************
* Module: resync_fifo_nonsynt
* Date: 2015-07-06
* Author: Alexey
* Description: non-synthesizable resyncronization fifo
*
* Copyright (c) 2015 Elphel, Inc.
* resync_fifo_nonsynt.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* resync_fifo_nonsynt.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// simplified resynchronisation fifo, could cause metastability
// because of that shall not be syntesisable
// TODO add shift registers and gray code to fix that
......
gtxe2_common/gtxe2_comm_clocking.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_comm_clocking
* Date: 2015-07-06
* Author: Alexey
* Description: qpll top-level, for now
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_comm_clocking.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_comm_clocking.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_comm_qpll_inmux.v"
`include "gtxe2_comm_qpll.v"
module gtxe2_comm_clocking(
......
gtxe2_common/gtxe2_comm_qpll.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_comm_qpll
* Date: 2015-07-06
* Author: Alexey
* Description: qpll non-synthesizable implementation
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_comm_qpll.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_comm_qpll.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`include "gtxe2_comm_qpll_def.v"
module gtxe2_comm_qpll(
// top-level interfaces
......
gtxe2_common/gtxe2_comm_qpll_inmux.v
View file @ 9b371aa6
/*******************************************************************************
* Module: gtxe2_comm_qpll_inmux
* Date: 2015-07-06
* Author: Alexey
* Description: non-synthesizable clock multiplexer
*
* Copyright (c) 2015 Elphel, Inc.
* gtxe2_comm_qpll_inmux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtxe2_comm_qpll_inmux.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module gtxe2_comm_qpll_inmux(
input wire [2:0] QPLLREFCLKSEL,
input wire GTREFCLK0,
......
tb/tb.v
View file @ 9b371aa6
/*******************************************************************************
* Module: tb
* Date: 2015-07-06
* Author: Alexey
* Description: testbench module = gtx_channel as a DUT + test payload module
*
* Copyright (c) 2015 Elphel, Inc.
* tb.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tb.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ps/1ps
//`include "gtxe2_top.v"
//`include "gtx_sata_2.v"
`include "GTXE2_CHANNEL.v"
`include "GTXE2_CHANNEL_GPL.v"
`include "test.v"
module tb();
wire reset;
......@@ -184,109 +202,13 @@ test test(
.RXRESETDONE (RXRESETDONE)
);
/*
gtxe2_top dut(
.reset (reset),
.TXP (TXP),
.TXN (TXN),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXBUFSTATUS (TXBUFSTATUS),
.TXPOLARITY (TXPOLARITY),
.TXRATE (TXRATE),
.RXRATE (RXRATE),
.TXRATEDONE (TXRATEDONE),
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.TXELECIDLE (TXELECIDLE),
.RXP (RXP),
.RXN (RXN),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.RXDATA (RXDATA),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXPOLARITY (RXPOLARITY),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.TXOUTCLKSEL (TXOUTCLKSEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK ),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TXOUTCLKPMA (TXOUTCLKPMA),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (tx_serial_clk),
.RXOUTCLKPMA (RXOUTCLKPMA),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (rx_serial_clk),
.QPLLREFCLKSEL (QPLLREFCLKSEL),
.QPLLOUTCLK (QPLLOUTCLK),
.QPLLOUTREFCLK (QPLLOUTREFCLK),
.QPLLLOCKDETCLK (QPLLLOCKDETCLK ),
.QPLLLOCKEN (QPLLLOCKEN),
.QPLLPD (QPLLPD),
.QPLLRESET (QPLLRESET),
.QPLLFBCLKLOST (QPLLFBCLKLOST),
.QPLLLOCK (QPLLLOCK),
.QPLLREFCLKLOST (QPLLREFCLKLOST)
);
*/
wire tied_to_vcc_i = 1'b1;
wire tied_to_ground_i = 1'b0;
wire [31:0] tied_to_ground_vec_i = 32'h00000000;
GTXE2_CHANNEL #
(
//_______________________ Simulation-Only Attributes __________________
GTXE2_CHANNEL #
(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("FALSE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("4.0"),
//----------------RX Byte and Word Alignment Attributes---------------
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
......@@ -298,14 +220,10 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
//----------------RX 8B/10B Decoder Attributes---------------
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
//----------------------RX Clock Correction Attributes----------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
......@@ -325,8 +243,6 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
//----------------------RX Channel Bonding Attributes----------------------
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_LEN (1),
......@@ -344,8 +260,6 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
//-------------------------RX Margin Analysis Attributes----------------------------
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("FALSE"),
.ES_EYE_SCAN_EN ("TRUE"),
......@@ -356,11 +270,7 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.ES_QUAL_MASK (80'h00000000000000000000),
.ES_SDATA_MASK (80'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
//-----------------------FPGA RX Interface Attributes-------------------------
.RX_DATA_WIDTH (20),
//-------------------------PMA Attributes----------------------------
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (32'h00018480),
.PMA_RSV2 (16'h2050),
......@@ -378,14 +288,8 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.RX_CLK25_DIV (6),
.TX_CLK25_DIV (6),
.UCODEER_CLR (1'b0),
//-------------------------PCI Express Attributes----------------------------
.PCS_PCIE_EN ("FALSE"),
//-------------------------PCS Attributes----------------------------
.PCS_RSVD_ATTR (48'h0100),
//-----------RX Buffer Attributes------------
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
......@@ -408,53 +312,23 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
//---------------------CDR Attributes-------------------------
//For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
//For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
//For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
//For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
//For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
//For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
//For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
//For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
.RXCDR_CFG (72'h03000023ff10200020),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
//-----------------RX Initialization and Reset Attributes-------------------
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXISCANRESET_TIME (5'b00001),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (5'b00011),
//-----------------RX OOB Signaling Attributes-------------------
.RXOOB_CFG (7'b0000110),
//-----------------------RX Gearbox Attributes---------------------------
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
//-----------------------PRBS Detection Attribute-----------------------
.RXPRBS_ERR_LOOPBACK (1'b0),
//-----------Power-Down Attributes----------
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
//-----------RX OOB Signaling Attributes----------
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b0111),
......@@ -466,11 +340,7 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
//-----------RX Fabric Clock Output Control Attributes----------
.TRANS_TIME_RATE (8'h0E),
//------------TX Buffer Attributes----------------
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
......@@ -480,11 +350,7 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
//-----------------------FPGA TX Interface Attributes-------------------------
.TX_DATA_WIDTH (20),
//-----------------------TX Configurable Driver Attributes-------------------------
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
......@@ -502,19 +368,11 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
//-----------------------TX Gearbox Attributes--------------------------
.TXGEARBOX_EN ("FALSE"),
//-----------------------TX Initialization and Reset Attributes--------------------------
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (5'b00001),
//-----------------------TX Receiver Detection Attributes--------------------------
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
//--------------------------CPLL Attributes----------------------------
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (4),
.CPLL_FBDIV_45 (5),
......@@ -524,11 +382,7 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.RXOUT_DIV (2),
.TXOUT_DIV (2),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
//------------RX Initialization and Reset Attributes-------------
.RXDFELPMRESET_TIME (7'b0001111),
//------------RX Equalizer Attributes-------------
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RX_DFE_GAIN_CFG (23'h020FEA),
......@@ -541,441 +395,246 @@ wire [31:0] tied_to_ground_vec_i = 32'h00000000;
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
//-----------------------Power-Down Attributes-------------------------
.RX_CLKMUX_PD (1'b1),
.TX_CLKMUX_PD (1'b1),
//-----------------------FPGA RX Interface Attribute-------------------------
.RX_INT_DATAWIDTH (0),
//-----------------------FPGA TX Interface Attribute-------------------------
.TX_INT_DATAWIDTH (0),
//----------------TX Configurable Driver Attributes---------------
.TX_QPI_STATUS_EN (1'b0),
//-----------------------RX Equalizer Attributes--------------------------
.RX_DFE_KL_CFG2 (32'h301148AC),
.RX_DFE_XYD_CFG (13'b0000000000000),
//-----------------------TX Configurable Driver Attributes--------------------------
.TX_PREDRIVER_MODE (1'b0)
)
dut
(
//------------------------------- CPLL Ports -------------------------------
)
dut
(
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK),
.CPLLLOCKEN (tied_to_vcc_i),
.CPLLLOCKEN (1'b1),
.CPLLPD (CPLLPD),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.CPLLREFCLKSEL (3'b001),
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.CPLLRESET (CPLLRESET),
.GTRSVD (16'b0000000000000000),
.PCSRSVDIN (16'b0000000000000000),
.PCSRSVDIN2 (5'b00000),
.PMARSVDIN (5'b00000),
.PMARSVDIN2 (5'b00000),
.TSTIN (20'b11111111111111111111),
.GTRSVD (1'b0),
.PCSRSVDIN (1'b0),
.PCSRSVDIN2 (1'b0),
.PMARSVDIN (1'b0),
.PMARSVDIN2 (1'b0),
.TSTIN (1'b1),
.TSTOUT (),
//-------------------------------- Channel ---------------------------------
.CLKRSVD (4'b0000),
//------------------------ Channel - Clocking Ports ------------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTGREFCLK (1'b0),
.GTNORTHREFCLK0 (1'b0),
.GTNORTHREFCLK1 (1'b0),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//-------------------------- Channel - DRP Ports --------------------------
.DRPADDR (1'b0),
.GTREFCLK1 (1'b0),
.GTSOUTHREFCLK0 (1'b0),
.GTSOUTHREFCLK1 (1'b0),
.DRPADDR (9'b0),
.DRPCLK (CPLLLOCKDETCKL),
.DRPDI (1'b0),
.DRPDI (16'b0),
.DRPDO (),
.DRPEN (1'b0),
.DRPRDY (),
.DRPWE (1'b0),
//----------------------------- Clocking Ports -----------------------------
.GTREFCLKMONITOR (),
.QPLLCLK (GTREFCLK0),
.QPLLREFCLK (GTREFCLK0),
.RXSYSCLKSEL (2'b00),
.TXSYSCLKSEL (2'b00),
//------------------------- Digital Monitor Ports --------------------------
.DMONITOROUT (DMONITOROUT),
//--------------- FPGA TX Interface Datapath Configuration ----------------
.TX8B10BEN (tied_to_vcc_i),
//----------------------------- Loopback Ports -----------------------------
.LOOPBACK (tied_to_ground_vec_i[2:0]),
//--------------------------- PCI Express Ports ----------------------------
.DMONITOROUT (),
.TX8B10BEN (1'b1),
.LOOPBACK (3'd0),
.PHYSTATUS (),
.RXRATE (tied_to_ground_vec_i[2:0]),
.RXRATE (3'd0),
.RXVALID (),
//---------------------------- Power-Down Ports ----------------------------
.RXPD (2'b00),
.TXPD (2'b00),
//------------------------ RX 8B/10B Decoder Ports -------------------------
.SETERRSTATUS (tied_to_ground_i),
//------------------- RX Initialization and Reset Ports --------------------
.SETERRSTATUS (1'b0),
.EYESCANRESET (reset),
.RXUSERRDY (RXUSERRDY),
//------------------------ RX Margin Analysis Ports ------------------------
.EYESCANDATAERROR (EYESCANDATAERROR),
.EYESCANMODE (tied_to_ground_i),
.EYESCANMODE (1'b0),
.EYESCANTRIGGER (1'b0),
//----------------------- Receive Ports - CDR Ports ------------------------
.RXCDRFREQRESET (tied_to_ground_i),
.RXCDRHOLD (tied_to_ground_i),
.RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0),
.RXCDRLOCK (),
.RXCDROVRDEN (tied_to_ground_i),
.RXCDRRESET (tied_to_ground_i),
.RXCDRRESETRSV (tied_to_ground_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0),
.RXCDRRESETRSV (1'b0),
.RXCLKCORCNT (),
//-------- Receive Ports - FPGA RX Interface Datapath Configuration --------
.RX8B10BEN (tied_to_vcc_i),
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
.RX8B10BEN (1'b1),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.RXDATA (RXDATA),
//----------------- Receive Ports - Pattern Checker Ports ------------------
.RXPRBSERR (),
.RXPRBSSEL (tied_to_ground_vec_i[2:0]),
//----------------- Receive Ports - Pattern Checker ports ------------------
.RXPRBSCNTRESET (tied_to_ground_i),
//------------------ Receive Ports - RX Equalizer Ports -------------------
.RXDFEXYDEN (tied_to_vcc_i),
.RXDFEXYDHOLD (tied_to_ground_i),
.RXDFEXYDOVRDEN (tied_to_ground_i),
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.RXPRBSSEL (3'd0),
.RXPRBSCNTRESET (1'b0),
.RXDFEXYDEN (1'b1),
.RXDFEXYDHOLD (1'b0),
.RXDFEXYDOVRDEN (1'b0),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
//------------------------- Receive Ports - RX AFE -------------------------
.GTXRXP (RXP),
//---------------------- Receive Ports - RX AFE Ports ----------------------
.GTXRXN (RXN),
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.RXBUFRESET (tied_to_ground_i),
.RXBUFRESET (1'b0),
.RXBUFSTATUS (),
.RXDDIEN (tied_to_ground_i),
.RXDLYBYPASS (tied_to_vcc_i),
.RXDLYEN (tied_to_ground_i),
.RXDLYOVRDEN (tied_to_ground_i),
.RXDLYSRESET (tied_to_ground_i),
.RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0),
.RXDLYSRESETDONE (),
.RXPHALIGN (tied_to_ground_i),
.RXPHALIGN (1'b0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (tied_to_ground_i),
.RXPHDLYPD (tied_to_ground_i),
.RXPHDLYRESET (tied_to_ground_i),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0),
.RXPHMONITOR (),
.RXPHOVRDEN (tied_to_ground_i),
.RXPHOVRDEN (1'b0),
.RXPHSLIPMONITOR (),
.RXSTATUS (RXSTATUS),
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.RXSTATUS (),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (),
.RXCOMMADET (),
.RXCOMMADETEN (tied_to_vcc_i),
.RXMCOMMAALIGNEN (tied_to_vcc_i),
.RXPCOMMAALIGNEN (tied_to_vcc_i),
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
.RXCOMMADETEN (1'b1),
.RXMCOMMAALIGNEN (1'b1),
.RXPCOMMAALIGNEN (1'b1),
.RXCHANBONDSEQ (),
.RXCHBONDEN (tied_to_ground_i),
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
.RXCHBONDMASTER (tied_to_ground_i),
.RXCHBONDEN (1'b0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'b0),
.RXCHBONDO (),
.RXCHBONDSLAVE (tied_to_ground_i),
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
.RXCHBONDSLAVE (1'b0),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
//------------------ Receive Ports - RX Equailizer Ports -------------------
.RXLPMHFHOLD (tied_to_ground_i),
.RXLPMHFOVRDEN (tied_to_ground_i),
.RXLPMLFHOLD (tied_to_ground_i),
//------------------- Receive Ports - RX Equalizer Ports -------------------
.RXLPMHFHOLD (1'b0),
.RXLPMHFOVRDEN (1'b0),
.RXLPMLFHOLD (1'b0),
.RXDFEAGCHOLD (RXDFEAGCHOLD),
.RXDFEAGCOVRDEN (tied_to_ground_i),
.RXDFECM1EN (tied_to_ground_i),
.RXDFEAGCOVRDEN (1'b0),
.RXDFECM1EN (1'b0),
.RXDFELFHOLD (RXDFELFHOLD),
.RXDFELFOVRDEN (tied_to_vcc_i),
.RXDFELFOVRDEN (1'b1),
.RXDFELPMRESET (reset),
.RXDFETAP2HOLD (tied_to_ground_i),
.RXDFETAP2OVRDEN (tied_to_ground_i),
.RXDFETAP3HOLD (tied_to_ground_i),
.RXDFETAP3OVRDEN (tied_to_ground_i),
.RXDFETAP4HOLD (tied_to_ground_i),
.RXDFETAP4OVRDEN (tied_to_ground_i),
.RXDFETAP5HOLD (tied_to_ground_i),
.RXDFETAP5OVRDEN (tied_to_ground_i),
.RXDFEUTHOLD (tied_to_ground_i),
.RXDFEUTOVRDEN (tied_to_ground_i),
.RXDFEVPHOLD (tied_to_ground_i),
.RXDFEVPOVRDEN (tied_to_ground_i),
.RXDFEVSEN (tied_to_ground_i),
.RXLPMLFKLOVRDEN (tied_to_ground_i),
.RXMONITOROUT (RXMONITOROUT),
.RXMONITORSEL (RXMONITORSEL),
.RXOSHOLD (tied_to_ground_i),
.RXOSOVRDEN (tied_to_ground_i),
//---------- Receive Ports - RX Fabric ClocK Output Control Ports ----------
.RXDFETAP2HOLD (1'b0),
.RXDFETAP2OVRDEN (1'b0),
.RXDFETAP3HOLD (1'b0),
.RXDFETAP3OVRDEN (1'b0),
.RXDFETAP4HOLD (1'b0),
.RXDFETAP4OVRDEN (1'b0),
.RXDFETAP5HOLD (1'b0),
.RXDFETAP5OVRDEN (1'b0),
.RXDFEUTHOLD (1'b0),
.RXDFEUTOVRDEN (1'b0),
.RXDFEVPHOLD (1'b0),
.RXDFEVPOVRDEN (1'b0),
// .RXDFEVSEN (1'b0),
.RXLPMLFKLOVRDEN (1'b0),
.RXMONITOROUT (),
.RXMONITORSEL (),
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
.RXRATEDONE (),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (3'b010),
//-------------------- Receive Ports - RX Gearbox Ports --------------------
.RXDATAVALID (),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
//------------------- Receive Ports - RX Gearbox Ports --------------------
.RXGEARBOXSLIP (tied_to_ground_i),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.RXGEARBOXSLIP (1'b0),
.GTRXRESET (reset),
.RXOOBRESET (tied_to_ground_i),
.RXPCSRESET (tied_to_ground_i),
.RXOOBRESET (1'b0),
.RXPCSRESET (1'b0),
.RXPMARESET (reset),
//---------------- Receive Ports - RX Margin Analysis ports ----------------
.RXLPMEN (tied_to_ground_i),
//----------------- Receive Ports - RX OOB Signaling ports -----------------
.RXLPMEN (1'b0),
.RXCOMSASDET (),
.RXCOMWAKEDET (RXCOMWAKEDET),
//---------------- Receive Ports - RX OOB Signaling ports -----------------
.RXCOMINITDET (RXCOMINITDET),
//---------------- Receive Ports - RX OOB signalling Ports -----------------
.RXELECIDLE (RXELECIDLE),
.RXELECIDLEMODE (2'b00),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.RXPOLARITY (tied_to_ground_i),
//-------------------- Receive Ports - RX gearbox ports --------------------
.RXSLIDE (tied_to_ground_i),
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.RXPOLARITY (1'b0),
.RXSLIDE (1'b0),
.RXCHARISCOMMA (),
.RXCHARISK (RXCHARISK),
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
.RXCHBONDI (5'b00000),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.RXRESETDONE (RXRESETDONE),
//------------------------------ Rx AFE Ports ------------------------------
.RXQPIEN (tied_to_ground_i),
.RXQPIEN (1'b0),
.RXQPISENN (),
.RXQPISENP (),
//------------------------- TX Buffer Bypass Ports -------------------------
.TXPHDLYTSTCLK (tied_to_ground_i),
//---------------------- TX Configurable Driver Ports ----------------------
.TXPHDLYTSTCLK (1'b0),
.TXPOSTCURSOR (5'b00000),
.TXPOSTCURSORINV (tied_to_ground_i),
.TXPRECURSOR (tied_to_ground_vec_i[4:0]),
.TXPRECURSORINV (tied_to_ground_i),
.TXQPIBIASEN (tied_to_ground_i),
.TXQPISTRONGPDOWN (tied_to_ground_i),
.TXQPIWEAKPUP (tied_to_ground_i),
//------------------- TX Initialization and Reset Ports --------------------
.CFGRESET (tied_to_ground_i),
.TXPOSTCURSORINV (1'b0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'b0),
.TXQPIBIASEN (1'b0),
.TXQPISTRONGPDOWN (1'b0),
.TXQPIWEAKPUP (1'b0),
.CFGRESET (1'b0),
.GTTXRESET (reset),
.PCSRSVDOUT (),
.TXUSERRDY (TXUSERRDY),
//-------------------- Transceiver Reset Mode Operation --------------------
.GTRESETSEL (tied_to_ground_i),
.RESETOVRD (tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXCHARDISPMODE (tied_to_ground_vec_i[7:0]),
.TXCHARDISPVAL (tied_to_ground_vec_i[7:0]),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
.GTRESETSEL (1'b0),
.RESETOVRD (1'b0),
.TXCHARDISPMODE (8'd0),
.TXCHARDISPVAL (8'd0),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
//------------------- Transmit Ports - PCI Express Ports -------------------
.TXELECIDLE (TXELECIDLE),
.TXMARGIN (tied_to_ground_vec_i[2:0]),
.TXRATE (tied_to_ground_vec_i[2:0]),
.TXSWING (tied_to_ground_i),
//---------------- Transmit Ports - Pattern Generator Ports ----------------
.TXPRBSFORCEERR (tied_to_ground_i),
//---------------- Transmit Ports - TX Buffer Bypass Ports -----------------
.TXDLYBYPASS (tied_to_vcc_i),
.TXDLYEN (tied_to_ground_i),
.TXDLYHOLD (tied_to_ground_i),
.TXDLYOVRDEN (tied_to_ground_i),
.TXDLYSRESET (tied_to_ground_i),
.TXMARGIN (3'd0),
.TXRATE (3'd0),
.TXSWING (1'b0),
.TXPRBSFORCEERR (1'b0),
.TXDLYBYPASS (1'b1),
.TXDLYEN (1'b0),
.TXDLYHOLD (1'b0),
.TXDLYOVRDEN (1'b0),
.TXDLYSRESET (1'b0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (tied_to_ground_i),
.TXPHALIGN (tied_to_ground_i),
.TXDLYUPDOWN (1'b0),
.TXPHALIGN (1'b0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (tied_to_ground_i),
.TXPHDLYPD (tied_to_ground_i),
.TXPHDLYRESET (tied_to_ground_i),
.TXPHINIT (tied_to_ground_i),
.TXPHALIGNEN (1'b0),
.TXPHDLYPD (1'b0),
.TXPHDLYRESET (1'b0),
.TXPHINIT (1'b0),
.TXPHINITDONE (),
.TXPHOVRDEN (tied_to_ground_i),
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.TXPHOVRDEN (1'b0),
.TXBUFSTATUS (),
//------------- Transmit Ports - TX Configurable Driver Ports --------------
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (tied_to_ground_i),
.TXDEEMPH (1'b0),
.TXDIFFCTRL (4'b1000),
.TXDIFFPD (tied_to_ground_i),
.TXINHIBIT (tied_to_ground_i),
.TXDIFFPD (1'b0),
.TXINHIBIT (1'b0),
.TXMAINCURSOR (7'b0000000),
.TXPISOPD (tied_to_ground_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXPISOPD (1'b0),
.TXDATA (TXDATA),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GTXTXN (TXN),
.GTXTXP (TXP),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLKSEL (3'b010),
.TXRATEDONE (),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.TXCHARISK (TXCHARISK),
.TXGEARBOXREADY (),
.TXHEADER (tied_to_ground_vec_i[2:0]),
.TXSEQUENCE (tied_to_ground_vec_i[6:0]),
.TXSTARTSEQ (tied_to_ground_i),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.TXPCSRESET (tied_to_ground_i),
.TXPMARESET (tied_to_ground_i),
.TXHEADER (3'd0),
.TXSEQUENCE (7'd0),
.TXSTARTSEQ (1'b0),
.TXPCSRESET (1'b0),
.TXPMARESET (1'b0),
.TXRESETDONE (TXRESETDONE),
//---------------- Transmit Ports - TX OOB signalling Ports ----------------
.TXCOMFINISH (TXCOMFINISH),
.TXCOMINIT (TXCOMINIT),
.TXCOMSAS (tied_to_ground_i),
.TXCOMSAS (1'b0),
.TXCOMWAKE (TXCOMWAKE),
.TXPDELECIDLEMODE (tied_to_ground_i),
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
.TXPOLARITY (tied_to_ground_i),
//------------- Transmit Ports - TX Receiver Detection Ports --------------
.TXDETECTRX (tied_to_ground_i),
//---------------- Transmit Ports - TX8b/10b Encoder Ports -----------------
.TX8B10BBYPASS (tied_to_ground_vec_i[7:0]),
//---------------- Transmit Ports - pattern Generator Ports ----------------
.TXPRBSSEL (tied_to_ground_vec_i[2:0]),
//--------------------- Tx Configurable Driver Ports ----------------------
.TXPDELECIDLEMODE (1'b0),
.TXPOLARITY (1'b0),
.TXDETECTRX (1'b0),
.TX8B10BBYPASS (8'd0),
.TXPRBSSEL (3'd0),
.TXQPISENN (),
.TXQPISENP ()
);
/*
gtx_sata_2 dut
(
.sysclk_in (GTREFCLK0),
.soft_reset_in (reset),
.dont_reset_on_data_error_in (1'b1),
.gt0_tx_fsm_reset_done_out (),
.gt0_rx_fsm_reset_done_out (),
.gt0_data_valid_in (1'b1),
//_________________________________________________________________________
//GT0 (X1Y0)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt0_cpllfbclklost_out (CPLLFBCLKLOST),
.gt0_cplllock_out (CPLLLOCK),
.gt0_cplllockdetclk_in (CPLLLOCKDETCLK),
.gt0_cpllreset_in (CPLLRESET),
//------------------------ Channel - Clocking Ports ------------------------
.gt0_gtrefclk0_in (GTREFCLK0),
//-------------------------- Channel - DRP Ports --------------------------
.gt0_drpaddr_in (1'b0),
.gt0_drpclk_in (CPLLLOCKDETCLK),
.gt0_drpdi_in (1'b0),
.gt0_drpdo_out (),
.gt0_drpen_in (1'b0),
.gt0_drprdy_out (),
.gt0_drpwe_in (1'b0),
//------------------------- Digital Monitor Ports --------------------------
.gt0_dmonitorout_out (),
//--------------------------- PCI Express Ports ----------------------------
.gt0_rxrate_in (RXRATE),
//------------------- RX Initialization and Reset Ports --------------------
.gt0_eyescanreset_in (reset),
.gt0_rxuserrdy_in (RXUSERRDY),
//------------------------ RX Margin Analysis Ports ------------------------
.gt0_eyescandataerror_out (),
.gt0_eyescantrigger_in (1'b0),
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
.gt0_rxusrclk_in (RXUSRCLK),
.gt0_rxusrclk2_in (RXUSRCLK2),
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt0_rxdata_out (RXDATA),
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt0_rxdisperr_out (RXDISPERR),
.gt0_rxnotintable_out (RXNOTINTABLE),
//------------------------- Receive Ports - RX AFE -------------------------
.gt0_gtxrxp_in (RXP),
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt0_gtxrxn_in (RXN),
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt0_rxphmonitor_out (RXPHMONITOR),
.gt0_rxphslipmonitor_out (RXPHSLIPMONITOR),
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt0_rxbyteisaligned_out (RXBYTEISALIGNED),
.gt0_rxbyterealign_out (RXBYTEREALIGN),
.gt0_rxcommadet_out (RXCOMMADET),
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt0_rxdfelpmreset_in (reset),
.gt0_rxmonitorout_out (RXMONITOROUT),
.gt0_rxmonitorsel_in (1'b0),
//---------- Receive Ports - RX Fabric ClocK Output Control Ports ----------
.gt0_rxratedone_out (RXRATEDONE),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt0_rxoutclk_out (RXOUTCLK),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt0_gtrxreset_in (reset),
.gt0_rxpmareset_in (reset),
//----------------- Receive Ports - RX OOB Signaling ports -----------------
.gt0_rxcomwakedet_out (RXCOMWAKEDET),
//---------------- Receive Ports - RX OOB Signaling ports -----------------
.gt0_rxcominitdet_out (RXCOMINITDET),
//---------------- Receive Ports - RX OOB signalling Ports -----------------
.gt0_rxelecidle_out (RXELECIDLE),
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt0_rxchariscomma_out (RXCHARISCOMMA),
.gt0_rxcharisk_out (RXCHARISK),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt0_rxresetdone_out (RXRESETDONE),
//------------------- TX Initialization and Reset Ports --------------------
.gt0_gttxreset_in (reset),
.gt0_txuserrdy_in (TXUSERRDY),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
.gt0_txusrclk_in (TXUSRCLK),
.gt0_txusrclk2_in (TXUSRCLK2),
//------------------- Transmit Ports - PCI Express Ports -------------------
.gt0_txelecidle_in (TXELECIDLE),
.gt0_txrate_in (TXRATE),
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt0_txdata_in (TXDATA),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt0_gtxtxn_out (TXN),
.gt0_gtxtxp_out (TXP),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt0_txoutclk_out (TXOUTCLK),
.gt0_txoutclkfabric_out (TXOUTCLKFABRIC),
.gt0_txoutclkpcs_out (TXOUTCLKPCS),
.gt0_txratedone_out (TXRATEDONE),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt0_txcharisk_in (TXCHARISK),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt0_txresetdone_out (TXRESETDONE),
//---------------- Transmit Ports - TX OOB signalling Ports ----------------
.gt0_txcomfinish_out (TXCOMFINISH),
.gt0_txcominit_in (TXCOMINIT),
.gt0_txcomwake_in (TXCOMWAKE),
//____________________________COMMON PORTS________________________________
.gt0_qplloutclk_in (GTREFCLK0),
.gt0_qplloutrefclk_in (GTREFCLK0)
);*/
);
endmodule
tb/test.v
View file @ 9b371aa6
/*******************************************************************************
* Module: test
* Date: 2015-07-06
* Author: Alexey
* Description: Generates test payload for GTXE2_CHANNEL
*
* Copyright (c) 2015 Elphel, Inc.
* test.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
* simple align test
* simple aligner test + oob + checking for a corrent decoding
*/
module test(
output wire reset,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment