...
 
Commits (55)
......@@ -763,7 +763,7 @@ int arch_cpu_init(void)
self.cfile+='\tuart_wait_tx_fifo_empty(); /* Second time - for some reason 1 wait sometimes fails after LAST_PRINT_DEBUG */\n'
self.cfile+='''/* set up the CPU clk clock frequency in the global data struct */
zynq_clk_early_init();
//zynq_clk_early_init();
'''
#LOCK_SLCR
......@@ -785,4 +785,4 @@ int arch_cpu_init(void)
c_out_file=open(cname,'w')
c_out_file.write(self.cfile)
c_out_file.close()
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
if ARCH_ZYNQ
config ZYNQ_CUSTOM_INIT
bool "Use custom ps7_init provided by Xilinx tool"
help
U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
If you want to override them with customized ones
or ps7_init code for your board is missing, please say Y here
and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
config TARGET_ELPHEL393
bool "Elphel 10393 Zynq Board"
default y
choice
prompt "Xilinx Zynq board select"
default TARGET_ZYNQ_ZC702
config SPL_LDSCRIPT
default "arch/arm/mach-zynq/u-boot-spl.lds"
config TARGET_ZYNQ_ZED
bool "Zynq ZedBoard"
config SPL_FAT_SUPPORT
default y
config TARGET_ZYNQ_MICROZED
bool "Zynq MicroZed"
config SPL_LIBCOMMON_SUPPORT
default y
config TARGET_ZYNQ_PICOZED
bool "Zynq PicoZed"
config SPL_LIBDISK_SUPPORT
default y
config TARGET_ZYNQ_ZC702
bool "Zynq ZC702 Board"
config SPL_LIBGENERIC_SUPPORT
default y
config TARGET_ZYNQ_ZC706
bool "Zynq ZC706 Board"
config SPL_MMC_SUPPORT
default y if MMC_SDHCI_ZYNQ
config TARGET_ZYNQ_ZC770
bool "Zynq ZC770 Board"
select ZYNQ_CUSTOM_INIT
config SPL_SERIAL_SUPPORT
default y
config TARGET_ZYNQ_ZYBO
bool "Zynq Zybo Board"
config SPL_SPI_FLASH_SUPPORT
default y if ZYNQ_QSPI
config TARGET_ELPHEL393
bool "Zynq Elphel 10393 Board"
endchoice
config SPL_SPI_SUPPORT
default y if ZYNQ_QSPI
config ZYNQ_DDRC_INIT
bool "Zynq DDRC initialization"
default y
help
This option used to perform DDR specific initialization
if required. There might be cases like ddr less where we
want to skip ddr init and this option is useful for it.
config SYS_BOARD
string "Board name"
default "elphel393" if TARGET_ELPHEL393
default "zynq"
config SYS_VENDOR
string "Vendor name"
default "elphel" if TARGET_ELPHEL393
default "xilinx"
......@@ -51,13 +53,28 @@ config SYS_SOC
default "zynq"
config SYS_CONFIG_NAME
default "zynq_zed" if TARGET_ZYNQ_ZED
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
default "zynq_picozed" if TARGET_ZYNQ_PICOZED
default "zynq_zc70x" if TARGET_ZYNQ_ZC702
default "zynq_zc706" if TARGET_ZYNQ_ZC706
default "zynq_zc770" if TARGET_ZYNQ_ZC770
default "zynq_zybo" if TARGET_ZYNQ_ZYBO
string "Board configuration name"
default "elphel393" if TARGET_ELPHEL393
default "zynq-common"
help
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
config SYS_MALLOC_F_LEN
default 0x600
config SYS_MALLOC_LEN
default 0x1400000
config BOOT_INIT_FILE
string "boot.bin init register filename"
default ""
help
Add register writes to boot.bin format (max 256 pairs).
Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
config ZYNQ_SDHCI_MAX_FREQ
default 52000000
endif
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := timer.o
obj-y += cpu.o
......@@ -24,4 +22,4 @@ endif
obj-y += clk.o
obj-y += lowlevel_init.o
AFLAGS_lowlevel_init.o := -mfpu=neon
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <zynqpl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ps7_init_gpl.h>
#include <asm/arch/sys_proto.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
/* Added __weak because the function is overridden in ezynq.c */
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
};
#endif
static const struct {
u8 idcode;
#if defined(CONFIG_FPGA)
u32 fpga_size;
#endif
char *devicename;
} zynq_fpga_descs[] = {
ZYNQ_DESC(7Z007S),
ZYNQ_DESC(7Z010),
ZYNQ_DESC(7Z012S),
ZYNQ_DESC(7Z014S),
ZYNQ_DESC(7Z015),
ZYNQ_DESC(7Z020),
ZYNQ_DESC(7Z030),
ZYNQ_DESC(7Z035),
ZYNQ_DESC(7Z045),
ZYNQ_DESC(7Z100),
{ /* Sentinel */ },
};
/* ELPHEL: Added __weak because the function is overridden in ezynq.c */
__weak int arch_cpu_init(void)
{
zynq_slcr_unlock();
......@@ -36,7 +66,6 @@ __weak int arch_cpu_init(void)
writel(0xC, &slcr_base->ddr_urgent);
#endif
#endif
zynq_clk_early_init();
zynq_slcr_lock();
return 0;
......@@ -44,12 +73,8 @@ __weak int arch_cpu_init(void)
unsigned int zynq_get_silicon_version(void)
{
unsigned int ver;
ver = (readl(&devcfg_base->mctrl) &
ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
return ver;
return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
>> ZYNQ_SILICON_VER_SHIFT;
}
void reset_cpu(ulong addr)
......@@ -59,10 +84,62 @@ void reset_cpu(ulong addr)
;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif
static int __maybe_unused cpu_desc_id(void)
{
u32 idcode;
u8 i;
idcode = zynq_slcr_get_idcode();
for (i = 0; zynq_fpga_descs[i].idcode; i++) {
if (zynq_fpga_descs[i].idcode == idcode)
return i;
}
return -ENODEV;
}
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
int cpu_id = cpu_desc_id();
if (cpu_id < 0)
return 0;
fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
fpga.name = zynq_fpga_descs[cpu_id].devicename;
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
u32 version;
int cpu_id = cpu_desc_id();
if (cpu_id < 0)
return 0;
version = zynq_get_silicon_version() << 1;
if (version > (PCW_SILICON_VERSION_3 << 1))
version += 1;
printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
printf("Silicon: v%d.%d\n", version >> 1, version & 1);
return 0;
}
#endif
/*
* Copyright (c) 2013 Xilinx Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_QSPI_ENABLE 0x02
#define SLCR_QSPI_ENABLE_MASK 0x03
#define SLCR_NAND_L2_SEL 0x10
#define SLCR_NAND_L2_SEL_MASK 0x1F
#define SLCR_USB_L1_SEL 0x04
#define SLCR_IDCODE_MASK 0x1F000
#define SLCR_IDCODE_SHIFT 12
/*
* zynq_slcr_mio_get_status - Get the status of MIO peripheral.
*
* @peri_name: Name of the peripheral for checking MIO status
* @get_pins: Pointer to array of get pin for this peripheral
* @num_pins: Number of pins for this peripheral
* @mask: Mask value
* @check_val: Required check value to get the status of periph
*/
struct zynq_slcr_mio_get_status {
const char *peri_name;
const int *get_pins;
int num_pins;
u32 mask;
u32 check_val;
};
static const int qspi0_pins[] = {
1, 2, 3, 4, 5, 6
};
static const int qspi1_cs_pin[] = {
0
};
static const int qspi1_pins[] = {
9, 10, 11, 12, 13
};
static const int qspi0_dio_pins[] = {
1, 2, 3, 6
};
static const int qspi1_cs_dio_pin[] = {
0
};
static const int qspi1_dio_pins[] = {
9, 10, 11
};
static const int nand8_pins[] = {
0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
};
static const int nand16_pins[] = {
16, 17, 18, 19, 20, 21, 22, 23
};
static const int usb0_pins[] = {
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
};
static const int usb1_pins[] = {
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
};
static const struct zynq_slcr_mio_get_status mio_periphs[] = {
{
"qspi0",
qspi0_pins,
ARRAY_SIZE(qspi0_pins),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"qspi1_cs",
qspi1_cs_pin,
ARRAY_SIZE(qspi1_cs_pin),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"qspi1",
qspi1_pins,
ARRAY_SIZE(qspi1_pins),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"qspi0_dio",
qspi0_dio_pins,
ARRAY_SIZE(qspi0_dio_pins),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"qspi1_cs_dio",
qspi1_cs_dio_pin,
ARRAY_SIZE(qspi1_cs_dio_pin),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"qspi1_dio",
qspi1_dio_pins,
ARRAY_SIZE(qspi1_dio_pins),
SLCR_QSPI_ENABLE_MASK,
SLCR_QSPI_ENABLE,
},
{
"nand8",
nand8_pins,
ARRAY_SIZE(nand8_pins),
SLCR_NAND_L2_SEL_MASK,
SLCR_NAND_L2_SEL,
},
{
"nand16",
nand16_pins,
ARRAY_SIZE(nand16_pins),
SLCR_NAND_L2_SEL_MASK,
SLCR_NAND_L2_SEL,
},
{
"usb0",
usb0_pins,
ARRAY_SIZE(usb0_pins),
SLCR_USB_L1_SEL,
SLCR_USB_L1_SEL,
},
{
"usb1",
usb1_pins,
ARRAY_SIZE(usb1_pins),
SLCR_USB_L1_SEL,
SLCR_USB_L1_SEL,
},
};
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
{
if (!slcr_lock) {
writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
slcr_lock = 1;
}
}
void zynq_slcr_unlock(void)
{
if (slcr_lock) {
writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
slcr_lock = 0;
}
}
/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
/*
* Unlock the SLCR then reset the system.
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
zynq_slcr_unlock();
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
clrbits_le32(&slcr_base->reboot_status, 0xF000000);
writel(1, &slcr_base->pss_rst_ctrl);
}
/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
int ret;
zynq_slcr_unlock();
if (gem_id > 1) {
printf("Non existing GEM id %d\n", gem_id);
goto out;
}
ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
if (ret)
goto out;
if (gem_id) {
/* Configure GEM_RCLK_CTRL */
writel(1, &slcr_base->gem1_rclk_ctrl);
} else {
/* Configure GEM_RCLK_CTRL */
writel(1, &slcr_base->gem0_rclk_ctrl);
}
udelay(100000);
out:
zynq_slcr_lock();
}
void zynq_slcr_devcfg_disable(void)
{
u32 reg_val;
zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Disable Level shifters before setting PS-PL */
reg_val = readl(&slcr_base->lvl_shftr_en);
reg_val &= ~0xF;
writel(reg_val, &slcr_base->lvl_shftr_en);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);
zynq_slcr_lock();
}
void zynq_slcr_devcfg_enable(void)
{
zynq_slcr_unlock();
/* Set Level Shifters DT618760 */
writel(0xF, &slcr_base->lvl_shftr_en);
/* Enable AXI interface by de-asserting FPGA resets */
writel(0x0, &slcr_base->fpga_rst_ctrl);
zynq_slcr_lock();
}
u32 zynq_slcr_get_boot_mode(void)
{
/* Get the bootmode register value */
return readl(&slcr_base->boot_mode);
}
u32 zynq_slcr_get_idcode(void)
{
return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
SLCR_IDCODE_SHIFT;
}
/*
* zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
*
* @periph: Name of the peripheral
*
* Returns count to indicate the number of pins configured for the
* given @periph.
*/
int zynq_slcr_get_mio_pin_status(const char *periph)
{
const struct zynq_slcr_mio_get_status *mio_ptr;
int val, i, j;
int mio = 0;
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
mio_ptr = &mio_periphs[i];
for (j = 0; j < mio_ptr->num_pins; j++) {
val = readl(&slcr_base->mio_pin
[mio_ptr->get_pins[j]]);
if ((val & mio_ptr->mask) == mio_ptr->check_val)
mio++;
}
break;
}
}
return mio;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
* (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
*/
#include <common.h>
#include <debug_uart.h>
......@@ -11,39 +10,29 @@
#include <asm/spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#ifndef CONFIG_EZYNQ
__weak void ps7_init(void)
{
puts("Please copy ps7_init.c/h from hw project\n");
}
#endif
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/ps7_init_gpl.h>
void board_init_f(ulong dummy)
{
/* Clear the BSS. */
//memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
//gd = &gdata;
#ifndef CONFIG_EZYNQ
ps7_init();
#endif
arch_cpu_init();
#ifdef CONFIG_EZYNQ
puts("NOT REQUIRED: Copying ps7_init.c/h from hw project\n");
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
// board_init_r(NULL, 0);
}
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
preloader_console_init();
preloader_console_init();
#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
arch_early_init_r();
#endif
board_init();
}
#endif
......@@ -82,17 +71,26 @@ u32 spl_boot_device(void)
return mode;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(void)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
return MMCSD_MODE_FS;
/* boot linux */
return 0;
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
void spl_board_prepare_for_boot(void)
{
/* boot linux */
ps7_post_config();
debug("SPL bye\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
#source "board/elphel/elphel393/parts/MT41J128M16HA15E/Kconfig"
#source "board/elphel/elphel393/parts/MT41J256M8HX15E/Kconfig"
#source "board/elphel/parts/MT41K256M16HA107/Kconfig"
#source "board/elphel/elphel393/parts/MT41K256M16RE125/Kconfig"
#source "board/elphel/elphel393/parts/XC7Z010_1CLG400/Kconfig"
#source "board/elphel/elphel393/parts/XC7Z020_1CLG484/Kconfig"
#source "board/elphel/parts/XC7Z030_1FBG484C/Kconfig"
#source "board/elphel/elphel393/parts/XC7Z045_2FFG900C/Kconfig"
if TARGET_ELPHEL393
source "board/elphel/elphel393/Kconfig"
source "board/elphel/parts/MT41K256M16HA107/Kconfig"
source "board/elphel/parts/XC7Z030_1FBG484C/Kconfig"
config SPL_NAND_BBT
bool
default y
config SPL_NAND_IDS
bool
default y
config EZYNQ_SKIP_CLK
bool
default y
config SPL_NAND_ELPHEL393
bool
default y
#config SYS_NO_FLASH
# bool
# default y
#config ZYNQ_I2C0
# bool
# default y
#config CONFIG_ZYNQ_SERIAL_UART0
# bool
# default y
endif
This diff is collapsed.
......@@ -75,19 +75,19 @@ int board_late_init(void)
{
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
case ZYNQ_BM_NOR:
setenv("modeboot", "norboot");
env_set("modeboot", "norboot");
break;
case ZYNQ_BM_SD:
setenv("modeboot", "sdboot");
env_set("modeboot", "sdboot");
break;
case ZYNQ_BM_NAND:
setenv("modeboot", "nandboot");
env_set("modeboot", "nandboot");
break;
case ZYNQ_BM_JTAG:
setenv("modeboot", "jtagboot");
env_set("modeboot", "jtagboot");
break;
default:
setenv("modeboot", "");
env_set("modeboot", "");
break;
}
......
#
# (C) Copyright 2013 Elphel, Inc.
#
# Configuration for ezynq for Micron MT41K256M16HA107 DDR3L memory
# backward compatible to Micron MT41K256M16RE125 (used in
# microzed, will keep settings initially)
#
# This program is free software; you can redistribute it andor
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 3 of
# the License, or (at your option) any later version.
#
# You should have received a copy of the GNU General Public
# License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
config EZYNQ_DDR_DS_PARTNO
string
default 'mt41j128m16ha15e'
help
Memory part number (currently not used - derive some parameters
later)
config EZYNQ_DDR_DS_MEMORY_TYPE
string
default 'ddr3'
help
DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2
(1.2V)
config EZYNQ_DDR_DS_BANK_ADDR_COUNT
int
default 3
help
Number of DDR banks
config EZYNQ_DDR_DS_ROW_ADDR_COUNT
int
default 15
help
Number of DDR Row Address bits
config EZYNQ_DDR_DS_COL_ADDR_COUNT
int
default 10
help
Number of DDR Column address bits
config EZYNQ_DDR_DS_DRAM_WIDTH
int
default 16
help
Memory chip bus width (not yet used)
config EZYNQ_DDR_DS_RCD
int
default 7
help
DESCRIPTION':'RAS to CAS delay (in tCK)
config EZYNQ_DDR_DS_T_RCD
string
default '13.1'
help
Activate to internal Read or Write (ns). May be used to
calculate CONFIG_EZYNQ_DDR_DS_RCD automatically
config EZYNQ_DDR_DS_RP
int
default 7
help
Row Precharge time (in tCK)
config EZYNQ_DDR_DS_T_RP
string
default '13.1'
help
Precharge command period (ns). May be used to calculate
CONFIG_EZYNQ_DDR_DS_RP automatically,
config EZYNQ_DDR_DS_T_RC
string
default '48.75'
help
Activate to Activate or Refresh command period (ns)
config EZYNQ_DDR_DS_T_RAS_MIN
string
default '35.0'
help
Minimal Row Active time (ns)
config EZYNQ_DDR_DS_T_FAW
string
default '40.0'
help
Minimal running window for 4 page activates (ns)
config EZYNQ_DDR_DS_T_RFC
string
default '300.0'
help
Minimal Refresh-to-Activate or Refresh command period (ns)
config EZYNQ_DDR_DS_T_WR
string
default '15.0'
help
Write recovery time (ns)
config EZYNQ_DDR_DS_T_REFI_US
string
default '7.8'
help
Maximal average periodic refresh, microseconds. Will be
automatically reduced if high temperature option is selected
config EZYNQ_DDR_DS_RTP
int
default 4
help
Minimal Read-to-Precharge time (in tCK). Will use max of this
and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK
config EZYNQ_DDR_DS_T_RTP
string
default '7.5'
help
Minimal Read-to-Precharge time (ns). Will use max of this
divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP
config EZYNQ_DDR_DS_WTR
int
default 4
help
Minimal Write-to-Read time (in tCK). Will use max of this and
CONFIG_EZYNQ_DDR_DS_T_WTR/tCK
config EZYNQ_DDR_DS_T_WTR
string
default '7.5'
help
Minimal Write-to-Read time (ns). Will use max of this divided
by tCK and CONFIG_EZYNQ_DDR_DS_WTR
config EZYNQ_DDR_DS_XP
int
default 4
help
Minimal time from power down (DLL on) to any operation (in tCK)
config EZYNQ_DDR_DS_T_DQSCK_MAX
string
default '5.5'
help
LPDDR2 only. DQS output access time from CK (ns). Used for
LPDDR2
config EZYNQ_DDR_DS_CCD
int
default 5
help
DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS)
config EZYNQ_DDR_DS_RRD
int
default 6
help
ACTIVATE-to-ACTIVATE minimal command period (in tCK)
config EZYNQ_DDR_DS_T_RRD
string
default '10.0'
help
ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to
calculate CONFIG_EZYNQ_DDR_DS_RRD automatically
config EZYNQ_DDR_DS_MRD
int
default 4
help
MODE REGISTER SET command period (in tCK)
config EZYNQ_DDR_DS_MOD
int
default 12
help
MODE REGISTER SET update delay (in tCK)
config EZYNQ_DDR_DS_T_MOD
string
default '15.0'
help
MODE REGISTER SET update delay (ns).
config EZYNQ_DDR_DS_WLMRD
int
default 40
help
Write leveling : time to the first DQS rising edge (cycles).
config EZYNQ_DDR_DS_CKE
int
default 3
help
CKE min pulse width (in tCK)
config EZYNQ_DDR_DS_T_CKE
string
default '7.5'
help
CKE min pulse width (ns). 7.5
config EZYNQ_DDR_DS_CKSRE
int
default 5
help
Keep valid clock after self refresh/power down entry (in tCK)
config EZYNQ_DDR_DS_T_CKSRE
string
default '10.0'
help
Keep valid clock after self refresh/power down entry (ns).
config EZYNQ_DDR_DS_CKSRX
int
default 5
help
Valid clock before self refresh, power down or reset exit (in
tCK)
config EZYNQ_DDR_DS_T_CKSRX
string
default '10.0'
help
Valid clock before self refresh, power down or reset exit (ns).
config EZYNQ_DDR_DS_ZQCS
int
default 64
help
ZQCS command: short calibration time (in tCK)
config EZYNQ_DDR_DS_ZQCL
int
default 512
help
ZQCL command: long calibration time, including init (in tCK)
config EZYNQ_DDR_DS_INIT2
int
default 5
help
LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high
config EZYNQ_DDR_DS_T_INIT4_US
string
default '1.0'
help
LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET
command.
config EZYNQ_DDR_DS_T_INIT5_US
string
default '10.0'
help
LPDDR2 only: tINIT5 (in us)- maximal duration of device auto
initialization.
config EZYNQ_DDR_DS_T_ZQINIT_US
string
default '1.0'
help
LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time.
#
# (C) Copyright 2013 Elphel, Inc.
#
# Configuration for ezynq for Micron MT41J256M8HX15E DDR3 memory
#
# This program is free software; you can redistribute it andor
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 3 of
# the License, or (at your option) any later version.
#
# You should have received a copy of the GNU General Public
# License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
config EZYNQ_DDR_DS_PARTNO
string
default 'mt41j256m8hx15e'
help
Memory part number (currently not used - derive some parameters
later)
config EZYNQ_DDR_DS_MEMORY_TYPE
string
default 'ddr3'
help
DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2
(1.2V)
config EZYNQ_DDR_DS_BANK_ADDR_COUNT
int
default 3
help
Number of DDR banks
config EZYNQ_DDR_DS_ROW_ADDR_COUNT
int
default 15
help
Number of DDR Row Address bits
config EZYNQ_DDR_DS_COL_ADDR_COUNT
int
default 10
help
Number of DDR Column address bits
config EZYNQ_DDR_DS_DRAM_WIDTH
int
default 8
help
Memory chip bus width (not yet used)
config EZYNQ_DDR_DS_RCD
int
default 7
help
DESCRIPTION':'RAS to CAS delay (in tCK)
config EZYNQ_DDR_DS_T_RCD
string
default '13.125'
help
Activate to internal Read or Write (ns). May be used to
calculate CONFIG_EZYNQ_DDR_DS_RCD automatically
config EZYNQ_DDR_DS_RP
int
default 7
help
Row Precharge time (in tCK)
config EZYNQ_DDR_DS_T_RP
string
default '13.125'
help
Precharge command period (ns). May be used to calculate
CONFIG_EZYNQ_DDR_DS_RP automatically,
config EZYNQ_DDR_DS_T_RC
string
default '49.5'
help
Activate to Activate or Refresh command period (ns)
config EZYNQ_DDR_DS_T_RAS_MIN
string
default '36.0'
help
Minimal Row Active time (ns)
config EZYNQ_DDR_DS_T_FAW
string
default '30.0'
help
Minimal running window for 4 page activates (ns)
config EZYNQ_DDR_DS_T_RFC
string
default '300.0'
help
Minimal Refresh-to-Activate or Refresh command period (ns)
config EZYNQ_DDR_DS_T_WR
string
default '15.0'
help
Write recovery time (ns)
config EZYNQ_DDR_DS_T_REFI_US
string
default '7.8'
help
Maximal average periodic refresh, microseconds. Will be
automatically reduced if high temperature option is selected
config EZYNQ_DDR_DS_RTP
int
default 4
help
Minimal Read-to-Precharge time (in tCK). Will use max of this
and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK
config EZYNQ_DDR_DS_T_RTP
string
default '7.5'
help
Minimal Read-to-Precharge time (ns). Will use max of this
divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP
config EZYNQ_DDR_DS_WTR
int
default 4
help
Minimal Write-to-Read time (in tCK). Will use max of this and
CONFIG_EZYNQ_DDR_DS_T_WTR/tCK
config EZYNQ_DDR_DS_T_WTR
string
default '7.5'
help
Minimal Write-to-Read time (ns). Will use max of this divided
by tCK and CONFIG_EZYNQ_DDR_DS_WTR
config EZYNQ_DDR_DS_XP
int
default 4
help
Minimal time from power down (DLL on) to any operation (in tCK)
config EZYNQ_DDR_DS_T_DQSCK_MAX
string
default '5.5'
help
LPDDR2 only. DQS output access time from CK (ns). Used for
LPDDR2
config EZYNQ_DDR_DS_CCD
int
default 5
help
DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS)
config EZYNQ_DDR_DS_RRD
int
default 6
help
ACTIVATE-to-ACTIVATE minimal command period (in tCK)
config EZYNQ_DDR_DS_T_RRD
string
default '10.0'
help
ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to
calculate CONFIG_EZYNQ_DDR_DS_RRD automatically
config EZYNQ_DDR_DS_MRD
int
default 4
help
MODE REGISTER SET command period (in tCK)
config EZYNQ_DDR_DS_MOD
int
default 12
help
MODE REGISTER SET update delay (in tCK)
config EZYNQ_DDR_DS_T_MOD
string
default '15.0'
help
MODE REGISTER SET update delay (ns).
config EZYNQ_DDR_DS_T_WLMRD
string
default '40.0'
help
Write leveling : time to the first DQS rising edge (ns).
config EZYNQ_DDR_DS_CKE
int
default 3
help
CKE min pulse width (in tCK)
config EZYNQ_DDR_DS_T_CKE
string
default '7.5'
help
CKE min pulse width (ns). 5.625
config EZYNQ_DDR_DS_CKSRE
int
default 5
help
Keep valid clock after self refresh/power down entry (in tCK)
config EZYNQ_DDR_DS_T_CKSRE
string
default '10.0'
help
Keep valid clock after self refresh/power down entry (ns).
config EZYNQ_DDR_DS_CKSRX
int
default 5
help
Valid clock before self refresh, power down or reset exit (in
tCK)
config EZYNQ_DDR_DS_T_CKSRX
string
default '10.0'
help
Valid clock before self refresh, power down or reset exit (ns).
config EZYNQ_DDR_DS_ZQCS
int
default 64
help
ZQCS command: short calibration time (in tCK)
config EZYNQ_DDR_DS_ZQCL
int
default 512
help
ZQCL command: long calibration time, including init (in tCK)
config EZYNQ_DDR_DS_INIT2
int
default 5
help
LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high
config EZYNQ_DDR_DS_T_INIT4_US
string
default '1.0'
help
LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET
command.
config EZYNQ_DDR_DS_T_INIT5_US
string
default '10.0'
help
LPDDR2 only: tINIT5 (in us)- maximal duration of device auto
initialization.
config EZYNQ_DDR_DS_T_ZQINIT_US
string
default '1.0'
help
LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time.
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CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
# don't need this
CONFIG_TARGET_ELPHEL393=y
CONFIG_DEFAULT_DEVICE_TREE="elphel393"
# 3 lines below (CONFIG_SYS_*) remove the need for rewriting Kconfig
CONFIG_SYS_BOARD="elphel393"
CONFIG_SYS_VENDOR="elphel"
CONFIG_SYS_NAME="elphel393"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
#CONFIG_CMD_GPIO=y
CONFIG_CMD_GPIO=n
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=n
......@@ -32,3 +42,43 @@ CONFIG_CMD_BOOTEFI=n
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_CMD_UBI=y
# copied from microzed_defconfig
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL_NAND_IDENT=y
CONFIG_SPL_DOS_PARTITION=y
CONFIG_SPL_BLK=y
CONFIG_SPL_DM=y
CONFIG_SPL_FS_FAT=y
#CONFIG_BLK=y
# UART 1
#CONFIG_DEBUG_UART_BASE=0xe0001000
# UART 0
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run $modeboot"
# options for generator (ezynq) of SPL's header
CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE='ddr3'
CONFIG_EZYNQ_CLK_DDR_3X_MAX_MHZ='None'
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=n
CONFIG_SPI_FLASH_SPANSION=n
CONFIG_SPI_FLASH_STMICRO=n
CONFIG_SPI_FLASH_WINBOND=n
CONFIG_ZYNQ_GEM=n
CONFIG_ZYNQ_QSPI=n
CONFIG_OF_SEPARATE=y
\ No newline at end of file
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
......@@ -13,7 +11,6 @@ endif
obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
obj-$(CONFIG_SPL_NAND_ELPHEL393) += elphel393_nand_spl.o
obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
......@@ -21,8 +18,9 @@ obj-$(CONFIG_SPL_NAND_BBT) += nand_bbt.o
obj-$(CONFIG_SPL_NAND_IDS) += nand_ids.o
obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o
obj-$(CONFIG_SPL_NAND_INIT) += nand.o
obj-$(CONFIG_SPL_NAND_INIT) += ../mtdcore.o ../mtd_uboot.o
obj-$(CONFIG_SPL_NAND_INIT) += ../../mtdcore.o ../../mtd_uboot.o
ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
endif
......@@ -47,33 +45,32 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_NDFC) += ndfc.o
obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_DOCG4) += docg4.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
else # minimal SPL drivers
......
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