Added DDR Mode Registers configuration, address mapping calculation

ezynq_ddrc_defs.py

@@ -129,9 +129,9 @@ DDRC_DEFS={ #not all fields are defined currently
     'dram_addr_map_bank':      {'OFFS': 0x03C,'DFLT':0x00000F77,'RW':'RW','FIELDS':{ #0x777
                   'reg_ddrc_addrmap_col_b6':          {'r':(16,19),'d':0,'c':'Selects address bits for column address bit 7, half bus width - column address bits 8, int. base=9'},  
                   'reg_ddrc_addrmap_col_b5':          {'r':(12,15),'d':0,'c':'Selects address bits for column address bit 6, half bus width - column address bits 7, int. base=8'},  
-                  'reg_ddrc_addrmap_ba nk_b2':        {'r':( 8,11),'d':0xf,'c':'Selects AXI address bit for bank2. Valid 0..15. Int. base=7. If 15, bank2 is set to 0'},  #7
-                  'reg_ddrc_addrmap_ba nk_b2':        {'r':( 4, 7),'d':0x7,'c':'Selects AXI address bit for bank1. Valid 0..14. Int. base=6.'},  
-                  'reg_ddrc_addrmap_ba nk_b2':        {'r':( 0, 3),'d':0x7,'c':'Selects AXI address bit for bank0. Valid 0..14. Int. base=5.'}}},  
+                  'reg_ddrc_addrmap_bank_b2':         {'r':( 8,11),'d':0xf,'c':'Selects AXI address bit for bank2. Valid 0..15. Int. base=7. If 15, bank2 is set to 0'},  #7
+                  'reg_ddrc_addrmap_bank_b1':         {'r':( 4, 7),'d':0x7,'c':'Selects AXI address bit for bank1. Valid 0..14. Int. base=6.'},  
+                  'reg_ddrc_addrmap_bank_b0':         {'r':( 0, 3),'d':0x7,'c':'Selects AXI address bit for bank0. Valid 0..14. Int. base=5.'}}},  
     'dram_addr_map_col':       {'OFFS': 0x040,'DFLT':0xFFF00000,'RW':'RW','FIELDS':{ # 0xfff00000
                   'reg_ddrc_addrmap_col_b11':         {'r':(28,31),'d':0xF,'c':'Selects address bits for col. addr. bit 13 (LP - 12), Valid 0..7 and 15, half width - unused (LP-13), int. base=14'},  
                   'reg_ddrc_addrmap_col_b10':         {'r':(24,27),'d':0xF,'c':'Selects address bits for col. addr. bit 12 (LP - 11), Valid 0..7 and 15, half width - 13 (LP-12), int. base=13'},  

ezynq_ddrcfg_defs.py

@@ -57,12 +57,15 @@ DDR_CFG_DEFS=[
                 'DESCRIPTION':'Number of DDR banks'},              
     {'NAME':'COL_ADDR_COUNT',  'CONF_NAME':'CONFIG_EZYNQ_DDR_COL_ADDR_COUNT','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':10,
                 'DESCRIPTION':'Number of DDR banks'},              
+    {'NAME':'BANK_ADDR_MAP',  'CONF_NAME':'CONFIG_EZYNQ_DDR_BANK_ADDR_MAP','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':10,
+                'DESCRIPTION':'DRAM address mapping: number of combined column and row addresses lower than BA0'},              
+              
     {'NAME':'ECC',             'CONF_NAME':'CONFIG_EZYNQ_DDR_ECC','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
                 'DESCRIPTION':'Enable ECC for the DDR memory'},
     {'NAME':'BUS_WIDTH',       'CONF_NAME':'CONFIG_EZYNQ_DDR_BUS_WIDTH','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':32,
                 'DESCRIPTION':'SoC DDR bus width'},
-    {'NAME':'BL',              'CONF_NAME':'CONFIG_EZYNQ_DDR_BL','TYPE':(8,4),'MANDATORY':True,'DERIVED':False,'DEFAULT':8, # DDR2 may have different lengths?
-                'DESCRIPTION':'Burst length'},
+    {'NAME':'BL',              'CONF_NAME':'CONFIG_EZYNQ_DDR_BL','TYPE':(8,4,16),'MANDATORY':True,'DERIVED':False,'DEFAULT':8, # DDR2 may have different lengths?
+                'DESCRIPTION':'Burst length, 16 is only supported for LPDDR2'},
     {'NAME':'HIGH_TEMP',       'CONF_NAME':'CONFIG_EZYNQ_DDR_HIGH_TEMP','TYPE':'B','MANDATORY':True,'DERIVED':False,'DEFAULT':False,
                 'DESCRIPTION':'High temperature (influences refresh)'},
     {'NAME':'T_REFI_US',           'CONF_NAME':'CONFIG_EZYNQ_DDR_T_REFI_US','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':7.8,
@@ -124,8 +127,15 @@ DDR_CFG_DEFS=[
                 'DESCRIPTION':'ACTIVATE-to-ACTIVATE minimal command period (in tCK)'},              
     {'NAME':'T_RRD',          'CONF_NAME':'CONFIG_EZYNQ_DDR_T_RRD','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':10.0,
                 'DESCRIPTION':'ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_RRD automatically'},   
+    {'NAME':'MRD',            'CONF_NAME':'CONFIG_EZYNQ_DDR_MRD','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':4,
+                'DESCRIPTION':'MODE REGISTER SET command period (in tCK)'},              
+    {'NAME':'DDR2_RTT',      'CONF_NAME':'CONFIG_EZYNQ_DDR2_RTT','TYPE':('DISABLED','75','150','50'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'75',
+                'DESCRIPTION':'DDR2 on-chip termination, Ohm'},              
+    {'NAME':'DDR3_RTT',      'CONF_NAME':'CONFIG_EZYNQ_DDR3_RTT','TYPE':('DISABLED','60','120','40'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'60',
+                'DESCRIPTION':'DDR3 on-chip termination, Ohm'}, # Does not include 20 & 30 - not clear if DDRC can use them with auto write leveling               
 
-              
+# CONFIG_EZYNQ_DDR3_RTT = 60 # DISABLED, 60,120,40 - only used for DDR3              
+# CONFIG_EZYNQ_DDR2_RTT = 75 # DISABLED, 75,150,50 - only used for DDR2              
 # CONFIG_EZYNQ_DDR_T_RTP = 7.5
 # CONFIG_EZYNQ_DDR_WTR = 4
 # CONFIG_EZYNQ_DDR_T_WTR = 7.5
@@ -136,6 +146,7 @@ DDR_CFG_DEFS=[
 # CONFIG_EZYNQ_DDR_CCD = 4
 # CONFIG_EZYNQ_DDR_RRD = 4
 # CONFIG_EZYNQ_DDR_T_RRD = 10.0
+# CONFIG_EZYNQ_DDR_MRD = 4
               
 ]
 
@@ -161,6 +172,7 @@ DDR_CFG_DEFS=[
 # CONFIG_EZYNQ_DDR_BANK_ADDR_COUNT = 3 *
 # CONFIG_EZYNQ_DDR_ROW_ADDR_COUNT = 15 *
 # CONFIG_EZYNQ_DDR_COL_ADDR_COUNT = 10 *
+# CONFIG_EZYNQ_DDR_BANK_ADDR_MAP  = 10
 
 # CONFIG_EZYNQ_DDR_ENABLE = 1          *
 # CONFIG_EZYNQ_DDR_MEMORY_TYPE = DDR3  *

ezynq_feature_config.py

@@ -156,6 +156,12 @@ class EzynqFeatures:
 #        return [n for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]
         return [n[0] for n in sorted([(name,self.defs[name]['INDEX']) for name in self.pars], key = lambda l: l[1])]
 #TODO: Use SELECT for options?
+    def get_par_confname(self,name):
+        try:
+            return self.defs[name]['CONF_NAME']
+        except:
+            raise Exception (name+' not found in self.defs') # should not happen with wrong data, program bug
+
     def get_par_value(self,name):
         try:
             return self.pars[name]

ezynqcfg.py

@@ -1002,8 +1002,9 @@ else:
 #output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL    
 output_mio(registers,f,mio,MIO_HTML_MASK)
 ddr.calculate_dependent_pars()
-ddr.check_missing_features()
-ddr.html_list_features(f)
+ddr.pre_validate() # before applying default values (some timings should be undefined, not defaults)
+ddr.check_missing_features() #and apply defualt values
+ddr.html_list_features(f) #verify /fix values after defaults are applied
 #ddr.ddr_init_memory(current_reg_sets,force=False,warn=False): # will program to sequence 'MAIN'
 
 ddr.ddr_init_memory([],False,False) # will program to sequence 'MAIN'

test.mk

@@ -133,6 +133,7 @@ CONFIG_EZYNQ_DDR_FREQ_MHZ = 533.333333
 CONFIG_EZYNQ_DDR_BANK_ADDR_COUNT = 3
 CONFIG_EZYNQ_DDR_ROW_ADDR_COUNT = 15
 CONFIG_EZYNQ_DDR_COL_ADDR_COUNT = 10
+CONFIG_EZYNQ_DDR_BANK_ADDR_MAP  = 10 # number of combine CA and RA lower than BA0
 CONFIG_EZYNQ_DDR_CL = 7
 CONFIG_EZYNQ_DDR_CWL = 6
 #CONFIG_EZYNQ_DDR_T_RCD = 7
@@ -150,6 +151,9 @@ CONFIG_EZYNQ_DDR_CCD = 5 # 4 in Micron specs
 CONFIG_EZYNQ_DDR_RRD = 6 # 4 in Micron specs
 CONFIG_EZYNQ_DDR_T_RRD = 10.0
 
+CONFIG_EZYNQ_DDR_MRD = 4
+CONFIG_EZYNQ_DDR2_RTT = 75 # DISABLED, 75,150,50 - only used for DDR2              
+CONFIG_EZYNQ_DDR3_RTT = 60 # DISABLED, 60,120,40 - only used for DDR3