Fixing SDIO clock, adding more registers to setup, bug fixes

ezynq_clk.py

@@ -649,8 +649,8 @@ class EzynqClk:
         can0_cpu_1x_clkact    = 'CAN0'  in self.iface_divs # 0x1
         spi1_cpu_1x_clkact    = 'SPI1'  in self.iface_divs # 0x1
         spi0_cpu_1x_clkact    = 'SPI0'  in self.iface_divs # 0x1
-        sdi1_cpu_1x_clkact    = 'SDI1'  in self.iface_divs # 0x1
-        sdi0_cpu_1x_clkact    = 'SDI0'  in self.iface_divs # 0x1
+        sdi1_cpu_1x_clkact    = 'SDIO1' in self.iface_divs # 0x1
+        sdi0_cpu_1x_clkact    = 'SDIO0' in self.iface_divs # 0x1
         gem1_cpu_1x_clkact    = 'GIGE1' in self.iface_divs # 0x1
         gem0_cpu_1x_clkact    = 'GIGE0' in self.iface_divs # 0x1
         usb1_cpu_1x_clkact    = 'USB1'  in self.iface_divs # 0x1

ezynq_mio.py

@@ -280,13 +280,12 @@ ERROR_DEFS={
 
 class EzynqMIO:
     def __init__(self, verbosity, qualifier_char, regs_masked, permit_undefined_bits=False):
-        self.MIO_PINS_DEFS=  ezynq_slcr_clk_def.MIO_PINS_DEFS
+#        print ezynq_slcr_clk_def.MIO_PINS_DEFS
+        self.MIO_PINS_DEFS=  ezynq_slcr_clk_def.SLCR_DEFS #combined
         self.qualifier_char=qualifier_char
         self.verbosity=     verbosity
         self.slcr_register_set=  ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,regs_masked,permit_undefined_bits)
 
-#        self.DDRIOB_DEFS=ezynq_ddriob_def.DDRIOB_DEFS
-#        self.DDR_CFG_DEFS=ezynq_ddrcfg_defs.DDR_CFG_DEFS
     def generate_led_off_on(self, mio_pin):
         # generate code to be included in u-boot for debugging early boot stages
         led_register_set=  ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,[])
@@ -435,14 +434,6 @@ class EzynqMIO:
                             value='y'
                         else:
                             value=int(value)
-    #TODO: Value may be just 'y' if there is a single option
-    #Traceback (most recent call last):
-    #  File "./ezynq/ezynqcfg.py", line 455, in <module>
-    #    set_mio_interfaces(mio_interfaces, options)
-    #  File "./ezynq/ezynqcfg.py", line 369, in set_mio_interfaces
-    #    anypin=int(option['INTERFACE_GROUP'])
-    #ValueError: invalid literal for int() with base 10: 'y'
-                            
                             
                             
     #find if such pin name is defined for the interface
@@ -640,16 +631,6 @@ class EzynqMIO:
     #                print 'value=',value
                     mio[pin]['DATA_OUT']=value #Where is it used?
     
-#         ddriob_register_set=self.ddriob_register_set
-#         ddrc_register_set=  self.ddrc_register_set
-#         ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
-#         
-#         self.ddr_init_ddriob(force,warn) # will program to sequence 'MAIN'
-#         regs1=ddriob_register_set.get_register_sets(True,True)
-#         ddrc_register_set.set_initial_state(regs1, True)# add
-#         self.ddr_init_ddrc(force,warn) # will program to sequence 'MAIN'
-#         return ddrc_register_set.get_register_sets(True,True)
-
     
     
     
@@ -659,6 +640,24 @@ class EzynqMIO:
         self.slcr_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state   
         for i,mio_pin in enumerate(self.mio):
             self.slcr_register_set.set_word('mio_pin_%02i'%i,mio_pin['VALUE'],force) # active low soft reset
+# Add other than MIO_PIN registers
+        used_ifaces=self.get_used_interfaces()
+        sdio_ctrl_pins=[{},{}]
+        for iface in used_ifaces:
+            if iface['NAME'] == 'SDIO_CD':
+                sdio_ctrl_pins[iface['CHANNEL']]['CD'] = iface['PIN']
+            elif iface['NAME'] == 'SDIO_WP':
+                sdio_ctrl_pins[iface['CHANNEL']]['WP'] = iface['PIN']
+        for n, ch in enumerate(sdio_ctrl_pins):
+            if ch:
+                if 'CD' in ch:
+                    self.slcr_register_set.set_bitfields('sd%i_wp_cd_sel'%n, ( #SDIO x CD and WP source select
+                                                         ('sdio%i_ce_sel'%n,  ch['CD'])),force)
+                if 'WP' in ch:
+                    self.slcr_register_set.set_bitfields('sd%i_wp_cd_sel'%n, ( #SDIO x CD and WP source select
+                                                         ('sdio%i_wp_sel'%n,  ch['WP'])),force)
+
+            
         return self.slcr_register_set.get_register_sets(True,True)
     
     # Just add to the HTML output

ezynq_slcr_clk_def.py

@@ -167,8 +167,8 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
                   'spi0_cpu_1x_clkact':       {'r':(14,14),'d':0x1,   'c':'SPI0 AMBA clock control (1- enabled, 0- disabled)'},       # 0x0
                   'reserved2':                {'r':(13,13),'d':0,     'c':'reserved'},
                   'reserved3':                {'r':(12,12),'d':0,     'c':'reserved'},
-                  'sdi1_cpu_1x_clkact':       {'r':(11,11),'d':0x1,   'c':'SDI1 AMBA clock control (1- enabled, 0- disabled)'},       # 0x0
-                  'sdi0_cpu_1x_clkact':       {'r':(10,10),'d':0x1,   'c':'SDI0 AMBA clock control (1- enabled, 0- disabled)'},       # 0x1
+                  'sdi1_cpu_1x_clkact':       {'r':(11,11),'d':0x1,   'c':'SDIO 1 AMBA clock control (1- enabled, 0- disabled)'},       # 0x0
+                  'sdi0_cpu_1x_clkact':       {'r':(10,10),'d':0x1,   'c':'SDI0 0 AMBA clock control (1- enabled, 0- disabled)'},       # 0x1
                   'reserved4':                {'r':( 9, 9),'d':0,     'c':'reserved'},
                   'reserved5':                {'r':( 8, 8),'d':0,     'c':'reserved'},
                   'gem1_cpu_1x_clkact':       {'r':( 7, 7),'d':0x1,   'c':'Gigabit Ethernet 1 AMBA clock control (1- enabled, 0- disabled)'}, # 0x0
@@ -659,7 +659,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
                                    'COMMENTS':'Boot mode strapping pins state',
                                    'FIELDS':{
                   'reserved':                 {'r':( 5,31),'d':0,          'c':'reserved'},
-                  'pll_bypass':               {'r':( 4, 4),'d':0, 'm':'R', 'c':'1 PLL is enabled, outputs routed to clock generators, 0 - PLLs are diusabled and bypassed'}, 
+                  'pll_bypass':               {'r':( 4, 4),'d':0, 'm':'R', 'c':'1 PLL is enabled, outputs routed to clock generators, 0 - PLLs are disabled and bypassed'}, 
                   'boot_mode':                {'r':( 0, 3),       'm':'R', 'c':'boot mode pins as sampled'}}},
       'apu_ctrl':                 {'OFFS': 0x300,'DFLT':0,'RW':'RW', #  Never set
                                    'COMMENTS':'APU control',
@@ -722,6 +722,22 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
                   'reserved':                 {'r':( 1,31),'d':0,         'c':'reserved'},
                   'dfi_cal_st':               {'r':( 0, 3),'d':0,'m':'R', 'c':'Not clear'}}},
 
+      'sd0_wp_cd_sel':           {'OFFS': 0x830,'RW':'RW', #
+                                   'COMMENTS':'SDIO 0 CD and WP source select',
+                                   'FIELDS':{
+                  'reserved1':                {'r':(22,31),'d':0,         'c':'reserved'},
+                  'sdio0_ce_sel':             {'r':(16,21),'d':0,         'c':'Select MIO pin (any but 7,8) as a source for CD (>53 - EMIO)'},
+                  'reserved2':                {'r':( 6,15),'d':0,         'c':'reserved'},
+                  'sdio0_wp_sel':             {'r':( 0, 5),'d':0,         'c':'Select MIO pin (any but 7,8) as a source for WP (>53 - EMIO)'}}},
+
+      'sd1_wp_cd_sel':           {'OFFS': 0x834,'RW':'RW', #
+                                   'COMMENTS':'SDIO 1 CD and WP source select',
+                                   'FIELDS':{
+                  'reserved1':                {'r':(22,31),'d':0,         'c':'reserved'},
+                  'sdio1_ce_sel':             {'r':(16,21),'d':0,         'c':'Select MIO pin (any but 7,8) as a source for CD (>53 - EMIO)'},
+                  'reserved2':                {'r':( 6,15),'d':0,         'c':'reserved'},
+                  'sdio1_wp_sel':             {'r':( 0, 5),'d':0,         'c':'Select MIO pin (any but 7,8) as a source for WP (>53 - EMIO)'}}},
+                  
     }
 MIO_PINS_DEFS={'mio_pin_%02i'%i:{'OFFS': 0x700+4*i,
                              'DFLT':0x1601,
@@ -741,6 +757,7 @@ MIO_PINS_DEFS={'mio_pin_%02i'%i:{'OFFS': 0x700+4*i,
                                for i in range (54)}   
 MIO_PINS_DEFS['BASE_ADDR']=(0xF8000000,) # SLCR
 MIO_PINS_DEFS['MODULE_NAME']=('slcr',)
+SLCR_DEFS=    dict(MIO_PINS_DEFS.items()+SLCR_CLK_DEFS.items()) # combine.
     
 #UG585: table 25-6: multiplier (PLL_FDIV), PLL_CP, PLL_RES, LOCK_CNT
 PLL_PARS=(( 13,    2,6,750),

ezynq_uboot.py

@@ -26,6 +26,8 @@ import os
 import ezynq_feature_config
 #Use 'TYPE':'I' for decimal output, 'H' - for hex. On input both are accepted
 UBOOT_CFG_DEFS=[
+    {'NAME':'LOCK_SLCR',          'CONF_NAME':'CONFIG_EZYNQ_LOCK_SLCR','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':True,
+                'DESCRIPTION':'Lock SLCR after boot'},              
     {'NAME':'BOOT_DEBUG',         'CONF_NAME':'CONFIG_EZYNQ_BOOT_DEBUG','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
                 'DESCRIPTION':'Enable debug features during boot'},              
     {'NAME':'LED_DEBUG',          'CONF_NAME':'CONFIG_EZYNQ_LED_DEBUG','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
@@ -514,11 +516,14 @@ void lowlevel_init(void)
             self.cfile+='\tuart_wait_tx_fifo_empty(); /* u-boot may re-program UART differently, wait all is sent before getting there */\n'
 #uart_wait_tx_fifo_empty() - add if u-boot debug is on
         self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init()
+#LOCK_SLCR        
+        if self.features.get_par_value_or_none('LOCK_SLCR') is False:
+            self.cfile+='/* Leaving SLCR registers UNLOCKED */\n'
+        else:            
             self.cfile+='''/* Lock SLCR back after everything with it is done */
 \tlock_slcr();
-/*
-   This code was called from low OCM, so return should just get back correctly
- */
+'''
+        self.cfile+='''/* This code was called from low OCM, so return should just get back correctly */
 }
 '''
 

ezynqcfg.py

@@ -301,7 +301,8 @@ ddr.parse_parameters(raw_configs)
 ddr_type=ddr.get_ddr_type()
 
 used_mio_interfaces=mio_regs.get_used_interfaces()
-
+#for iface in used_mio_interfaces:
+#    print iface
 #clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False)
 clk=ezynq_clk.EzynqClk(args.verbosity,[],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set?
 clk.parse_parameters(raw_configs)
@@ -524,4 +525,4 @@ if (args.lowlevel):
     
     u_boot.make_lowlevel_init()
     u_boot.output_c_file(args.lowlevel)
-#print u_boot.get_c_file()
+#    print u_boot.get_c_file()

test.mk

 CONFIG_EZYNQ_BOOT_DEBUG = y # configure UARTx and send register dumps there
+CONFIG_EZYNQ_LOCK_SLCR = 0
 CONFIG_EZYNQ_LED_DEBUG = 47 # toggle LED during boot
 CONFIG_EZYNQ_UART_DEBUG_USE_LED = y # turn on/off LED while waiting for transmit FIFO not full
 

u-boot-tree/include/configs/ezynq/zed_ezynq.h

@@ -27,6 +27,7 @@
 
 /* Boot debug setup */
 #define CONFIG_EZYNQ_BOOT_DEBUG            /* configure UARTx and send register dumps there.*/
+#define CONFIG_EZYNQ_LOCK_SLCR         OFF /* Lock SLCR registers when all is done. */
 #define CONFIG_EZYNQ_LED_DEBUG          47 /* toggle LED during boot */
 #define CONFIG_EZYNQ_UART_DEBUG_USE_LED    /* turn on/off LED while waiting for transmit FIFO not full */
 
@@ -63,6 +64,13 @@
 #define CONFIG_EZYNQ_MIO_UART_1           48 //#  8+4*N
 /* LED will be OFF */
 #define CONFIG_EZYNQ_MIO_INOUT_47   OUT
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_40
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_41
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_42
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_43
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_44
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_45
+#define CONFIG_EZYNQ_MIO_PULLUP_EN_46
 
 /*